M2732A NMOS 32K (4K x 8) UV EPROM FAST ACCESS TIME: 200ns EXTENDED TEMPERATURE RANGE SINGLE 5V SUPPLY VOLTAGE LOW STANDBY CURRENT: 35mA max INPUTS and OUTPUTS TTL COMPATIBLE DURING READ and PROGRAM 24 1 COMPLETELY STATIC FDIP24W (F) DESCRIPTION The M2732A is a 32,768 bit UV erasable and electrically programmable memory EPROM. It is organized as 4,096 words by 8 bits. The M2732A with its single 5V power supply and with an access time of 200 ns, is ideal suited for applications where fast turn around and pattern experimentation one important requirements. The M2732A is honsed in a 24 pin Window Ceramic Frit-Seal Dual-in-Line package. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can be then written to the clerice by following the programming procedure. Figure 1. Logic Diagram VCC 12 8 A0-A11 E Table 1. Signal Names A0 - A11 Address Inputs Q0 - Q7 Data Outputs E Chip Enable GVPP Output Enable / Program Supply VCC Supply Voltage VSS Ground July 1994 Q0-Q7 M2732A GVPP VSS AI00780B 1/9 M2732A Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit Ambient Operating Temperature grade 1 grade 6 0 to 70 –40 to 85 °C TBIAS Temperature Under Bias grade 1 grade 6 –10 to 80 –50 to 95 °C TSTG Storage Temperature –65 to 125 °C VIO Input or Output Voltages –0.6 to 6 V VCC Supply Voltage –0.6 to 6 V VPP Program Supply Voltage –0.6 to 22 V TA Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. Figure 2. DIP Pin Connections A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 24 1 2 23 3 22 4 21 20 5 6 M2732A 19 18 7 17 8 16 9 15 10 11 14 12 13 be used to gate data to the output pins, independent of device selection. VCC A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3 AI00781 Assuming that the addresses are stable, address access time (tAVAQ) is equal to the delay from E to output (tELQV). Data is available at the outputs after the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M2732A has a standby mode which reduces the active power current by 70 %, from 125 mA to 35 mA. The M2732A is placed in the standby mode by applying a TTL high signal to E input. When in standby mode, the outputs are in a high impedance state, independent of the GVPP input. Two Line Output Control Because M2732A’s are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, DEVICE OPERATION The six modes of operation for the M2732A are listed in the Operating Modes Table. A single 5V power supply is required in the read mode. All inputs are TTL level except for VPP. Read Mode The M2732A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should 2/9 b. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that E be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. M2732A Programming When delivered, and after each erasure, all bits of the M2732A are in the “1" state. Data is introduced by selectively programming ”0’s" into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0" to a ”1" is by ultraviolet light erasure. The M2732A is in the programming mode when the GVPP input is at 21V. A 0.1µF capacitor must be placed across GVPP and ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied, 8 bits in parallel, to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, a 50ms, active low, TTL program pulse is applied to the E input. A program pulse must be applied at each address location to be programmed. Any location can be programmed at any time - either individually, sequentially, or at random. The program pulse has a maximum width of 55ms. The M2732A must not be programmed with a DC signal applied to the E input. Programming of multiple M2732As in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Inputs of the paralleled M2732As may be connected together when they are programmed with the same data. A low level TTL pulse applied to the E input programs the paralleled 2732As. Program Inhibit Programming of multiple M2732As in parallel with different data is also easily accomplished. Except for E, all like inputs (including GVPP) of the parallel M2732As may be common. A TTL level program pulse applied to a M2732A’s E input with GVPP at 21V will program that M2732A. A high level E input inhibits the other M2732As from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify is carried out with GVPP and E at VIL. ERASURE OPERATION The erasure characteristics of the M2732A are such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M2732A in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to the direct sunlight. If the M2732A is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M2732A window to prevent unintentional erasure. The recommended erasure procedure for the M2732A is exposure to shortwave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M2732A should be placed within 2.5 cm of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table 3. Operating Modes Mode E GVPP VCC Q0 - Q7 VIL VIL VCC Data Out VIL Pulse VPP VCC Data In Verify VIL VIL VCC Data Out Program Inhibit VIH VPP VCC Hi-Z Standby VIH X VCC Hi-Z Read Program Note: X = VIH or VIL. 3/9 M2732A Figure 4. AC Testing Load Circuit AC MEASUREMENT CONDITIONS Input Rise and Fall Times ≤ 20ns Input Pulse Voltages 0.45V to 2.4V Input and Output Timing Ref. Voltages 0.8V to 2.0V 1.3V 1N914 Note that Output Hi-Z is defined as the point where data is no longer driven. 3.3kΩ Figure 3. AC Testing Input Output Waveforms DEVICE UNDER TEST 2.4V OUT 2.0V CL = 100pF 0.8V 0.45V AI00827 CL includes JIG capacitance AI00828 Table 4. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance (except GVPP) VIN = 0V 6 pF CIN1 Input Capacitance (GVPP) VIN = 0V 20 pF COUT Output Capacitance VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms VALID A0-A11 tAVQV tAXQX E tEHQZ tGLQV G tGHQZ tELQV Q0-Q7 Hi-Z DATA OUT AI00782 4/9 M2732A Table 5. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Parameter Value Test Condition Min ILI Input Leakage Current ILO Output Leakage Current Unit Max 0 ≤ VIN ≤ VCC ±10 µA VOUT = VCC ±10 µA ICC Supply Current E = VIL, G = VIL 125 mA ICC1 Supply Current (Standby) E = VIH, G = VIL 35 mA VIL Input Low Voltage –0.1 0.8 V VIH Input High Voltage 2 VCC + 1 V VOL Output Low Voltage IOL = 2.1mA 0.45 V VOH Output High Voltage IOH = –400µA 2.4 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 6. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Alt Parameter Test Condition M2732A -2, -20 Min Max blank, -25 Min Max -3 Min Unit -4 Max Min Max tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 200 250 300 450 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 200 250 300 450 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 100 100 150 150 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 60 0 60 0 130 0 130 ns (2) tDF Output Enable High to Output Hi-Z E = VIL 0 60 0 60 0 130 0 130 ns tOH Address Transition to Output Transition E = VIL, G = VIL 0 tGHQZ tAXQX 0 0 0 ns Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 5/9 M2732A Table 7. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 5V ± 5%; VPP = 21V ± 0.5V) Symbol Parameter Test Condition Min Max Units ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA ICC Supply Current E = VIL, G = VIL 125 mA IPP Program Current E = VIL, G = VPP 30 mA VIL Input Low Voltage –0.1 0.8 V VIH Input High Voltage 2 VCC + 1 V VOL Output Low Voltage IOL = 2.1mA 0.45 V VOH Output High Voltage IOH = –400µA 2.4 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 8. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 5V ± 5%; VPP = 21V ± 0.5V) Symbol Alt Parameter Test Condition Min tAVEL tAS Address Valid to Chip Enable Low 2 µs tQVEL tDS Input Valid to Chip Enable Low 2 µs tVPHEL tOES VPP High to Chip Enable Low 2 µs tVPL1VPL2 tPRT VPP Rise Time 50 ns tELEH tPW Chip Enable Program Pulse Width 45 tEHQX tDH Chip Enable High to Input Transition 2 µs tEHVPX tOEH Chip Enable High to VPP Transition 2 µs tVPLEL tVR VPP Low to Chip Enable Low 2 µs tELQV tDV Chip Enable Low to Output Valid tEHQZ tDF Chip Enable High to Output Hi-Z 0 tEHAX tAH Chip Enable High to Address Transition 0 E = VIL, G = VIL Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 6/9 Max 55 Units ms 1 µs 130 ns ns M2732A Figure 6. Programming and Verify Modes AC Waveforms VALID A0-A11 tAVEL tEHAX DATA IN Q0-Q7 DATA OUT tQVEL tEHQX tELQV tEHQZ tEHVPX GVPP tVPHEL tVPLEL E tELEH VERIFY PROGRAM AI00783 ORDERING INFORMATION SCHEME Example: M2732A -2 Speed and VCC Tolerance -2 200 ns, 5V ±5% blank 250 ns, 5V ±5% -3 300 ns, 5V ±5% -4 450 ns, 5V ±5% -20 200 ns, 5V ±10% -25 250 ns, 5V ±10% F 1 Package F FDIP24W Temperature Range 1 0 to 70 °C 6 –40 to 85 °C For a list of available options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest to you. 7/9 M2732A FDIP24W - 24 pin Ceramic Frit-seal DIP, with window mm Symb Typ inches Min Max A Typ Min 5.71 0.225 A1 0.50 1.78 0.020 0.070 A2 3.90 5.08 0.154 0.200 B 0.40 0.55 0.016 0.022 B1 1.17 1.42 0.046 0.056 C 0.22 0.31 0.009 0.012 D 32.30 1.272 E 15.40 15.80 0.606 0.622 E1 13.05 13.36 0.514 0.526 e1 2.54 – – 0.100 – – e3 27.94 – – 1.100 – – eA 16.17 18.32 0.637 0.721 L 3.18 4.10 0.125 0.161 S 1.52 2.49 0.060 0.098 – – – – α 4° 15° 4° 15° N 24 ∅ 7.11 0.280 24 FDIP24W A2 A1 B1 B A L α e1 eA C e3 D S N ∅ E1 E 1 FDIPW-a Drawing is not to scale 8/9 Max M2732A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 9/9