M27C202 2 Mbit (128Kb x16) UV EPROM and OTP EPROM ■ 5V ± 10% SUPPLY VOLTAGE in READ OPERATION ■ ACCESS TIME: 45ns ■ LOW POWER CONSUMPTION: – Active Current 50mA at 5MHz – Standby Current 100µA ■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V ■ PROGRAMMING TIME: 100µs/word ■ ELECTRONIC SIGNATURE 40 40 1 1 FDIP40W (F) PDIP40 (B) – Manufacturer Code: 20h – Device Code: 1Ch DESCRIPTION The M27C202 is a 2 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs, in the application where the contents is stable and needs to be programmed only one time, and is organised as 131,072 by 16 bits. The FDIP40W (window ceramic frit-seal package) has a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C202 is offered in PDIP40, PLCC44 and TSOP40 (10 x 14 mm) packages. TSOP40 (N) 10 x 14 mm PLCC44 (K) Figure 1. Logic Diagram VCC VPP 17 16 A0-A16 P Q0-Q15 M27C202 E G VSS AI01815 April 1999 1/15 M27C202 Figure 2A. DIP Connections VPP E Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 VSS Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 G 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 M27C202 30 11 29 12 28 13 27 14 26 15 25 16 17 24 18 23 19 22 20 21 Figure 2B. TSOP Connections VCC P A16 A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 A12 A13 A14 A15 A16 P VCC VPP E DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 1 10 11 40 20 21 AI02784 AI01817B Table 1. Signal Names Q13 Q14 Q15 E VPP NC VCC P A16 A15 A14 Figure 2C. LCC Connections 1 44 Q12 Q11 Q10 Q9 Q8 VSS NC Q7 Q6 Q5 Q4 12 M27C202 34 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5 Q3 Q2 Q1 Q0 G NC A0 A1 A2 A3 A4 23 AI01816 2/15 31 30 M27C202 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS A0-A16 Address Inputs Q0-Q15 Data Outputs E Chip Enable G Output Enable P Program VPP Program Supply VCC Supply Voltage VSS Ground NC Not Connected Internally M27C202 Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature (3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V –2 to 13.5 V –2 to 14 V TA VCC VA9 (2) A9 Voltage Program Supply Voltage VPP Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes E G P A9 V PP Q15-Q0 Read VIL V IL V IH X VCC or VSS Data Output Output Disable VIL VIH X X VCC or VSS Hi-Z Program VIL X VIL Pulse X V PP Data Input Verify VIL V IL V IH X V PP Data Output Program Inhibit VIH X X X V PP Hi-Z Standby VIH X X X VCC or VSS Hi-Z Electronic Signature VIL V IL V IH VID VCC Codes Mode Note: X = VIH or VIL, VID = 12V ± 0.5V. Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 0 0 0 1 1 1 0 0 1Ch Note: Outputs Q15-Q8 are set to ’0’. 3/15 M27C202 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL 2.0V 0.8V 0.4V AI01822 CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condit ion Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. DEVICE OPERATION The operating modes of the M27C202 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C202 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, indepen- 4/15 dent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tOE from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-t GLQV. Standby Mode The M27C202 has a standby mode which reduces the supply current from 50mA to 100µA. The M27C202 is placed in the standby mode by applying a TTL high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. M27C202 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC) Symbol Parameter Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±10 µA 0V ≤ VOUT ≤ VCC ±10 µA E = VIL , G = VIL, IOUT = 0mA, f = 5MHz 50 mA E = VIH 1 mA E > VCC – 0.2V 100 µA V PP = VCC 100 µA ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH (2) Input High Voltage 2 VCC + 1 V VOL Output Low Voltage 0.4 V VOH IOL = 2.1mA Output High Voltage TTL IOH = –400µA 2.4 V Output High Voltage CMOS IOH = –100µA VCC – 0.7V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. Two Line Output Control Because OTP EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 5/15 M27C202 Table 8. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC) M27C202 Symbol Alt Parameter Test Condition -45 (3) Min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV -70 (3) Max Min -80 Max -100 Min Max Min Unit Max E = VIL, G = VIL 45 70 80 100 ns Chip Enable Low to Output Valid G = VIL 45 70 80 100 ns tOE Output Enable Low to Output Valid E = VIL 25 40 40 50 ns tEHQZ (2) t DF Chip Enable High to Output Hi-Z G = VIL 0 25 0 30 0 30 0 30 ns tGHQZ (2) t DF Output Enable High to Output Hi-Z E = VIL 0 25 0 30 0 30 0 30 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 0 0 ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. Figure 5. Read Mode AC Waveforms A0-A16 VALID tAVQV VALID tAXQX E tGLQV tEHQZ G tELQV Q0-Q15 tGHQZ Hi-Z AI01818B 6/15 M27C202 Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Parameter Test Condition Min 0 ≤ V IN ≤ VIH Max Unit ±10 µA 50 mA 50 mA ILI Input Leakage Current ICC Supply Current IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.4 V VOH Output High Voltage TTL VID A9 Voltage E = VIL IOL = 2.1mA IOH = –400µA 2.4 V 11.5 12.5 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Alt Parameter Test Condition Min Max tAVPL tAS Address Valid to Program Low 2 µs tQVPL tDS Input Valid to Program Low 2 µs tVPHPL tVPS VPP High to Program Low 2 µs t VCHPL tVCS VCC High to Program Low 2 µs tELPL tCES Chip Enable Low to Program Low 2 µs tPLPH tPW Program Pulse Width 95 tPHQX tDH Program High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 tGHAX tAH Output Enable High to Address Transition 0 105 Unit µs 100 ns 130 ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Programming When delivered (and after each ‘1’s erasure for UV EPROM), all bits of the M27C202 are in the ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in the data word. The only way to change a ‘0’ to a ‘1’ is by die exposure to ultraviolet light (UV EPROM). The M27C202 is in the programming mode when V PP input is at 12.75V, E is at V IL and P is pulsed to VIL. The data to be programmed is applied to 16 bits in parallel, to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. 7/15 M27C202 Figure 6. Programming and Verify Modes AC Waveforms VALID A0-A15 tAVPL Q0-Q15 DATA IN tQVPL DATA OUT tPHQX VPP tGLQV tVPHPL tGHQZ VCC tVCHPL tGHAX E tELPL P tPLPH tQXGL G PROGRAM VERIFY AI00706 Figure 7. Programming Flowchart VCC = 6.25V, VPP = 12.75V n =0 P = 100µs Pulse NO ++n = 25 YES FAIL NO VERIFY ++ Addr YES Last Addr NO YES CHECK ALL WORDS 1st: VCC = 6V 2nd: VCC = 4.2V AI00707C 8/15 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows programming of the whole array with a guaranteed margin, in a typical time of 13 seconds. Programming with PRESTO II consists of applying a sequence of 100µs program pulses to each word until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C202s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C202 may be common. A TTL low level pulse applied to a M27C202’s P input, with E low and VPP at 12.75V, will program that M27C202. A high level E input inhibits the other M27C202s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. M27C202 On-Board Programming The M27C202 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27C202. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C202 with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C202, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C202 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C202 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C202 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C202 window to prevent unintentional erasure. The recommended erasure procedure for the M27C202 is exposure to short wave ultraviolet light which has wavelength 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000µW/cm 2 power rating. The M27C202 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/15 M27C202 Table 11. Ordering Information Scheme Example: M27C202 -80 K 1 TR Device Type M27 Supply Voltage C = 5V ±10% Device Function 202 = 2 Mbit (128Kb x16) Speed -45 (1) = 45 ns -70 (1) = 70 ns -80 = 80 ns -100 = 100 ns Not For New Design (2) -120 = 120 ns -150 = 150 ns -200 = 200 ns Package F = FDIP40W B = PDIP40 K = PLCC44 N = TSOP40: 10 x 14 mm Temperature Range 1 = 0 to 70 °C 3 = –40 to 125 °C 6 = –40 to 85 °C Optio ns TR = Tape & Reel Packing Note: 1. High Speed, see AC Characteristics section for further information. 2. These speeds are replaced by the 100ns. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 10/15 M27C202 Table 12. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Mechanical Data Symb mm Typ inches Min Max A Typ Min 5.72 Max 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177 0.41 0.56 0.016 0.022 – – – – 0.23 0.30 0.009 0.012 51.79 52.60 2.039 2.071 – – 1.900 – – 0.600 B B1 1.45 C D D2 48.26 E 15.24 E1 e 2.54 eA 14.99 eB 0.057 – – 13.06 13.36 – – 0.100 – – 0.590 16.18 18.03 – – 0.514 0.526 – – – – 0.637 0.710 L 3.18 – 0.125 – S 1.52 2.49 0.060 0.098 ∅ – – α 8.13 4° 11° N 40 0.320 – – 4° 11° 40 Figure 8. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Outline A2 A3 A1 B1 B A L e α eA D2 C eB D S N ∅ E1 E 1 FDIPW-a Drawing is not to scale. 11/15 M27C202 Table 13. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data mm Symb inches Typ Min Max Typ Min Max A 4.45 – – 0.175 – – A1 0.64 0.38 – 0.025 0.015 – A2 3.56 3.91 0.140 0.154 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 51.78 52.58 2.039 2.070 – – – – E 14.80 16.26 0.583 0.640 E1 13.46 13.99 0.530 0.551 – D2 48.26 1.900 e1 2.54 – – 0.100 – eA 15.24 – – 0.600 – eB 15.24 17.78 0.600 0.700 L 3.05 3.81 0.120 0.150 S 1.52 2.29 0.060 0.090 α 0° 15° 0° 15° N 40 40 Figure 9. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline A2 A1 B1 B A L e1 α eA D2 C eB D S N E1 E 1 PDIP Drawing is not to scale. 12/15 M27C202 Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data mm inches Symb Typ Min Max A 4.20 A1 Min Max 4.70 0.165 0.185 2.29 3.04 0.090 0.120 A2 – 0.51 – 0.020 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 17.40 17.65 0.685 0.695 D1 16.51 16.66 0.650 0.656 D2 14.99 16.00 0.590 0.630 E 17.40 17.65 0.685 0.695 E1 16.51 16.66 0.650 0.656 E2 14.99 16.00 0.590 0.630 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 N Typ 0.050 0.035 44 44 CP 0.10 0.004 Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R CP PLCC Drawing is not to scale. 13/15 M27C202 Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data mm inches Symb Typ Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.80 14.20 0.543 0.559 D1 12.30 12.50 0.484 0.492 E 9.90 10.10 0.390 0.398 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 40 e 0.50 0.020 40 CP 0.10 0.004 Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a Drawing is not to scale. 14/15 A1 α L M27C202 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://w ww.st.com 15/15