STMicroelectronics M27V801-180P1TR 8 mbit 1mb x8 low voltage uv eprom and otp eprom Datasheet

M27V801
8 Mbit (1Mb x8) Low Voltage UV EPROM and OTP EPROM
■
LOW VOLTAGE READ OPERATION:
3V to 3.6V
■
FAST ACCESS TIME: 120ns
■
LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
32
32
– Standby Current 20µA
■
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■
PROGRAMMING TIME: 100µs/byte (typical)
■
ELECTRONIC SIGNATURE
1
1
FDIP32W (F)
PDIP32 (B)
– Manufacturer Code: 20h
– Device Code: 42h
DESCRIPTION
The M27V801 is a low voltage 8 Mbit EPROM offered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 1,048,576 by
8 bits.
The M27V801 operates in the read mode with a
supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP32W (window ceramic frit-seal package)
has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
VCC
20
8
A0-A19
E
Q0-Q7
M27V801
GVPP
Table 1. Signal Names
A0-A19
Address Inputs
Q0-Q7
Data Outputs
E
Chip Enable
GVPP
Output Enable / Program Supply
VCC
Supply Voltage
VSS
Ground
May 1998
VSS
AI01902
1/16
M27V801
VCC
A18
A17
A14
A13
A8
A9
A11
GVPP
A10
E
Q7
Q6
Q5
Q4
Q3
1 32
A7
A6
A5
A4
A3
A2
A1
A0
Q0
9
M27V801
25
A14
A13
A8
A9
A11
GVPP
A10
E
Q7
17
VSS
Q3
Q4
Q5
Q6
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
M27V801
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
A12
A15
A16
A19
VCC
A18
A17
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
Figure 2B. PLCC Pin Connections
Q1
Q2
Figure 2A. DIP Pin Connections
AI01904
AI01903
Figure 2C. TSOP Pin Connections
A11
A9
A8
A13
A14
A17
A18
VCC
A19
A16
A15
A12
A7
A6
A5
A4
1
8
9
16
32
M27V801
(Normal)
25
24
17
AI01905
2/16
For applications where the content is programmed
only one time and erasure is not required, the
M27V801 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
GVPP
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
DEVICE OPERATION
The operating modes of the M27V801 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for GVPP and 12V on A9 for Electronic Signature and Margin Mode Set or Reset .
Read Mode
The M27V801 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of t GLQV from the falling edge of G, assuming that
E has been low and the addresses have been stable for at least tAVQV-tGLQV.
M27V801
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage (except A9)
–2 to 7
V
Supply Voltage
–2 to 7
V
–2 to 13.5
V
–2 to 14
V
TA
VCC
VA9 (2)
A9 Voltage
Program Supply Voltage
VPP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
E
GVPP
A9
Q0-Q7
Read
VIL
VIL
X
Data Out
Output Disable
VIL
VIH
X
Hi-Z
V IL Pulse
VPP
X
Data In
Program Inhibit
V IH
VPP
X
Hi-Z
Standby
V IH
X
X
Hi-Z
Electronic Signature
VIL
VIL
VID
Codes
Mode
Program
Note: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
0
1
0
0
0
0
1
0
42h
Standby Mode
The M27V801 has a standby mode which reduces
the active current from 15mA to 20µA with low voltage operation VCC ≤ 3.6V, see Read Mode DC
Characteristics table for details.The M27V801 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the GVPP input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection.
The two line control function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
3/16
M27V801
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
≤ 20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
Standard
2.4V
OUT
CL
2.0V
0.8V
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
AI01822
CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol
C IN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
V IN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
4/16
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
M27V801
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%)
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ V CC
±10
µA
0V ≤ VOUT ≤ VCC
±10
µA
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, V CC ≤ 3.6V
15
mA
E = VIH
1
mA
E > VCC – 0.2V, VCC ≤ 3.6V
20
µA
VPP = VCC
10
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
IPP
Program Current
VIL
Input Low Voltage
–0.3
0.8
V
VIH (2)
Input High Voltage
2
VCC + 1
V
VOL
Output Low Voltage
0.4
V
VOH
IOL = 2.1mA
Output High Voltage TTL
IOH = –400µA
2.4
V
Output High Voltage CMOS
IOH = –100µA
VCC –0.7V
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
M27V801
Symbol
Alt
Parameter
Test Condi tion
-120
Min
tAVQV
tACC
Address Valid to Output Valid
tELQV
tCE
Chip Enable Low to Output Valid
tGLQV
tOE
Output Enable Low to Output Valid
tEHQZ (2)
tDF
Chip Enable High to Output Hi-Z
tGHQZ (2)
tDF
Output Enable High to Output Hi-Z
tAXQX
tOH
Address Transition to Output Transition
Max
-150
Min
Unit
Max
E = VIL, GVPP = VIL
120
150
ns
GVPP = VIL
120
150
ns
E = VIL
60
80
ns
GVPP = VIL
0
50
0
50
ns
E = VIL
0
50
0
50
ns
E = VIL, GVPP = VIL
0
0
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP
2. Sampled only, not 100% tested.
5/16
M27V801
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
M27V801
Symbol
Alt
Parameter
Test Condi tion
-180
Min
tAVQV
tACC
Address Valid to Output Valid
tELQV
tCE
Chip Enable Low to Output Valid
tGLQV
tOE
Output Enable Low to Output Valid
tEHQZ (2)
tDF
Chip Enable High to Output Hi-Z
tGHQZ (2)
tDF
Output Enable High to Output Hi-Z
tAXQX
tOH
Address Transition to Output Transition
Max
-200
Min
Max
E = VIL, GVPP = VIL
180
200
ns
GVPP = VIL
180
200
ns
E = VIL
90
100
ns
GVPP = VIL
0
50
0
70
ns
E = VIL
0
50
0
70
ns
E = VIL, GVPP = VIL
0
0
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A19
VALID
tAVQV
VALID
tAXQX
E
tGLQV
tEHQZ
G
tELQV
Q0-Q7
tGHQZ
Hi-Z
AI01583B
6/16
Unit
M27V801
Table 9. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Parameter
Test Conditio n
Min
VIL ≤ VIN ≤ VIH
Max
Unit
±10
µA
50
mA
50
mA
ILI
Input Leakage Current
ICC
Supply Current
IPP
Program Current
V IL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.4
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage TTL
IOH = –1mA
VID
A9 Voltage
E = VIL
3.6
V
11.5
12.5
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Table 10. MARGIN MODE AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
tA9HVPH
t AS9
VA9 High to VPP High
2
µs
tVPHEL
tVPS
VPP High to Chip Enable Low
2
µs
tA10HEH
tAS10
VA10 High to Chip Enable High (Set)
1
µs
tA10LEH
tAS10
VA10 Low to Chip Enable High (Reset)
1
µs
tEXA10X
tAH10
Chip Enable Transition to VA10 Transition
1
µs
t EXVPX
tVPH
Chip Enable Transition to VPP Transition
2
µs
tVPXA9X
tAH9
VPP Transition to VA9 Transition
2
µs
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Programming
The M27V801 has been designed to be fully compatible with the M27C801 and has the same electronic signature. As a result the M27V801 can be
programmed as the M27C801 on the same programming equipments applying 12.75V on VPP
and 6.25V on VCC by the use of the same PRESTO IIB algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V801
are in the ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations.
Although only ’0’ will be programmed, both ’1’ and
’0’ can be present in the data word. The only way
to change a ’0’ to a ’1’ is by die exposure to ultravi-
olet light (UV EPROM). The M27V801 is in the
programming mode when VPP input is at 12.75V
and E is pulsed to VIL. The data to be programmed
is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data
inputs are TTL. VCC is specified to be 6.25V ±
0.25V.
The M27V801 can use PRESTO IIB Programming
Algorithm that drastically reduces the programming time (typically 52 seconds). Nevertheless to
achieve compatibility with all programming equipments, PRESTO Programming Algorithm can be
used.
7/16
M27V801
Table 11. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
tAVEL
tAS
Address Valid to Chip Enable Low
2
µs
tQVEL
tDS
Input Valid to Chip Enable Low
2
µs
tVCHEL
tVCS
V CC High to Chip Enable Low
2
µs
tVPHEL
tOES
V PP High to Chip Enable Low
2
µs
tVPLVPH
tPRT
V PP Rise Time
50
ns
tELEH
tPW
Chip Enable Program Pulse Width (Initial)
45
tEHQX
tDH
Chip Enable High to Input Transition
2
µs
tEHVPX
tOEH
Chip Enable High to VPP Transition
2
µs
tVPLEL
tVR
V PP Low to Chip Enable Low
2
µs
tELQV
tDV
Chip Enable Low to Output Valid
tEHQZ (2)
tDFP
Chip Enable High to Output Hi-Z
0
tEHAX
tAH
Chip Enable High to Address Transition
0
55
µs
130
ns
ns
Figure 6. MARGIN MODE AC Waveforms
VCC
A8
A9
tVPXA9X
GVPP
tVPHEL
tEXVPX
E
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
8/16
µs
1
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
tA9HVPH
Unit
M27V801
Figure 7. Programming and Verify Modes AC Waveforms
VALID
A0-A19
tAVEL
Q0-Q7
tEHAX
DATA IN
DATA OUT
tQVEL
tEHQX
tEHQZ
VCC
tVCHEL
tEHVPX
tELQV
GVPP
tVPHEL
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI01270
Figure 8. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
SET MARGIN MODE
n=0
E = 50µs Pulse
NO
++n
= 25
YES
FAIL
NO
VERIFY
++ Addr
YES
Last
Addr
NO
YES
RESET MARGIN MODE
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
AI01271B
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. This can
be achieved with STMicroelectronics M27V801
due to several design innovations to improve programming efficiency and to provide adequate margin for reliability. Before starting the programming
the internal MARGIN MODE circuit is set in order
to guarantee that each cell is programmed with
enough margin. Then a sequence of 50µs program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are
applied since the verify in MARGIN MODE provides the necessary margin.
Program Inhibit
Programming of multiple M27V801s in parallel
with different data is also easily accomplished. Except for E, all like inputs including GVPP of the parallel M27V801 may be common. A TTL low level
pulse applied to a M27V801’s E input, with VPP at
12.75V, will program that M27V801. A high level E
input inhibits the other M27V801s from being programmed.
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G
at V IL. Data should be verified with tELQV after the
falling edge of E.
9/16
M27V801
On-Board Programming
The M27V801 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27V801. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V801. Two
identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from
VIL to VIH. All other address lines must be held at
VIL during Electronic Signature mode.
Byte 0 (A0=VIL) represents the manufacturer code
and byte 1 (A0=VIH) the device identifier code. For
the STMicroelectronics M27V801, these two identifier bytes are given in Table 4 and can be readout on outputs Q0 to Q7. Note that the M27V801
and M27C801 have the same identifier bytes.
10/16
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27V801 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range.
Research shows that constant exposure to room
level fluorescent lighting could erase a typical
M27V801 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27V801 is to be
exposed to these types of lighting conditions for
extended periods of time, it is suggested that
opaque labels be put over the M27V801 window to
prevent unintentional erasure. The recommended
erasure procedure for the M27V801 is exposure to
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 30 W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating.
The M27V801 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
M27V801
Table 12. Ordering Information Scheme
Example:
M27V801
-100 K
1
TR
Device Type
Operating Voltage
V = 3V
Speed
-120 = 120
-150 = 150
-180 = 180
-200 = 200
ns
ns
ns
ns
Package
F = FDIP32W
P = PDIP32
K = PLCC32
N = TSOP32: 8 x 20mm
Temperature Range
1 = –0 to 70 °C
6 = –40 to 85 °C
Optio n
TR =Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
11/16
M27V801
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
5.72
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
B1
1.45
C
D
–
–
0.23
0.30
0.057
–
–
0.009
0.012
41.73
42.04
1.643
1.655
D2
38.10
–
–
1.500
–
–
E
15.24
–
–
0.600
–
–
13.06
13.36
0.514
0.526
–
–
0.100
–
–
0.590
E1
e
2.54
eA
14.99
–
–
eB
16.18
18.03
L
3.18
S
1.52
2.49
–
–
0.260
0.420
K
6.60
K1
10.67
–
–
0.637
0.710
0.125
–
–
α
4°
11°
N
32
0.060
0.098
–
–
–
–
4°
11°
32
Figure 9. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
K
1
E1
E
K1
FDIPW-b
Drawing is not to scale.
12/16
Max
M27V801
Table 14. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm
Symb
Typ
inches
Min
Max
A
–
A1
Min
Max
5.08
–
0.200
0.38
–
0.015
–
A2
3.56
4.06
0.140
0.160
B
0.38
0.51
0.015
0.020
–
–
–
–
C
0.20
0.30
0.008
0.012
D
41.78
42.04
1.645
1.655
B1
1.52
Typ
0.060
D2
38.10
–
–
1.500
–
–
E
15.24
–
–
0.600
–
–
13.59
13.84
0.535
0.545
E1
e1
2.54
–
–
0.100
–
–
eA
15.24
–
–
0.600
–
–
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.03
0.070
0.080
α
0°
10°
0°
10°
N
32
32
Figure 10. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
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M27V801
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
mm
Symb
Typ
inches
Min
Max
A
2.54
A1
Min
Max
3.56
0.100
0.140
1.52
2.41
0.060
0.095
A2
–
0.38
–
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
Typ
0.050
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D
D1
A1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
PLCC
Drawing is not to scale.
14/16
CP
M27V801
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
Typ
Min
1.20
Max
0.047
A1
0.05
0.15
0.002
0.007
A2
0.95
1.05
0.037
0.041
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
7.90
8.10
0.311
0.319
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
32
e
0.50
0.020
32
CP
0.10
0.004
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
15/16
M27V801
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