M28C16A M28C17A 16 Kbit (2Kb x8) Parallel EEPROM FAST ACCESS TIME: – 150ns at 5V – 250ns at 3V SINGLE SUPPLY VOLTAGE: – 5V ± 10% for M28C16A and M28C17A – 2.7V to 3.6V for M28C16-xxW LOW POWER CONSUMPTION FAST WRITE CYCLE – 32 Bytes Page Write Operation – Byte or Page Write Cycle: 5ms ENHANCED END OF WRITE DETECTION – Ready/Busy Open Drain Output – Data Polling – Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY – Endurance >100,000 Erase/Write Cycles – Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT DESCRIPTION The M28C16A and M28C17Aare 2K x8 low power Parallel EEPROM fabricatedwith STMicroelectronics proprietarysingle polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V or 3V power supply. Table 1. Signal Names A0-A10 Address Input DQ0-DQ7 Data Input / Output W Write Enable E Chip Enable G Output Enable RB Ready / Busy VCC Supply Voltage VSS Ground August 1998 28 1 PDIP28 (BS) PLCC32 (KA) 28 1 SO28 (MS) 300 mils TSOP28 (NS) 8 x13.4mm Figure 1. Logic Diagram VCC 11 8 A0-A10 W DQ0-DQ7 M28C16A M28C17A E RB G VSS AI02109 1/19 M28C16A, M28C17A VCC W DU A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 RB or NC (1) DU VCC W DU 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M28C17A 8 21 9 20 10 19 11 18 12 17 13 16 14 15 1 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0 M28C16A M28C17A 9 25 A8 A9 NC NC G A10 E DQ7 DQ6 17 DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 RB NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 2B. LCC Pin Connections A7 NC Figure 2A. DIP Pin Connections AI02110 AI02111 Warning: NC = Not Connected, DU = Don’t Use. Warning: NC = Not Connected, DU = Don’t Use. Note: 1. Pin 2 is either RB for M28C17A or NC for M28C16A. Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections RB NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M28C17A 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W DU A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI02112 Warning: NC = Not Connected, DU = Don’t Use. 2/19 G NC A9 A8 DU W 22 VCC RB NC A7 A6 A5 A4 A3 28 1 7 21 M28C16A 15 14 8 A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 AI02113 Warning: NC = Not Connected, DU = Don’t Use. M28C16A, M28C17A Table 2. Absolute Maximum Ratings (1) Symbol TA Parameter Ambient Operating Temperature Value (2) Unit – 40 to 85 °C T STG Storage Temperature Range – 65 to 150 °C VCC Supply Voltage – 0.3 to 6.5 V V IO Input/Output Voltage – 0.3 to VCC +0.6 V VI Input Voltage – 0.3 to 6.5 V 3000 V VESD Electrostatic Discharge Voltage (Human Body model) Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. Table 3. Operating Modes Mode E G W DQ0 - DQ7 Read VIL VIL VIH Data Out Write VIL VIH VIL Data In Standby / Write Inhibit VIH X X Hi-Z Write Inhibit X X VIH Data Out or Hi-Z Write Inhibit X VIL X Data Out or Hi-Z Output Disable X VIH X Hi-Z Note: X = VIH or VIL DESCRIPTION (cont’d) The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshakingmode with Ready/Busy, Data Polling and Toggle Bit. The M28C16A/17A supports 32 byte page write operation. Write Enable (W). The Write Enable input controls the writing of data to the M28C16A/17A. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. Ready/Busy is available for the M28C17A in PDIP, PLCC and SO packages, and for the M28C16A in TSOP only. PIN DESCRITPION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28C16A/17A through the I/O pins. OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C16A/17Ais accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedancewhen either G or E is high. 3/19 M28C16A, M28C17A Figure 3. Block Diagram E VPP GEN A0-A5 ADDRESS LATCH X DECODE A6-A10 (Page Address) RESET G W CONTROL LOGIC 64K ARRAY ADDRESS LATCH Y DECODE SENSE AND DATA LATCH I/O BUFFERS PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING DQ0-DQ7 AI01520 OPERATION (cont’d) Write Write operations are initiated when both W and E are low and G is high.The M28C16A/17Asupports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows up to 32 bytes to be consecutively latched into the memory prior to initiating a Figure 4. Status Bit Assignment DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status 4/19 Hi-Z Hi-Z Hi-Z programming cycle. All bytes must be located in a single page address, that is A5 - A10 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data up to a maximum of tWHWH after the rising edge of E or W which ever occurs first. If a transition of E or W is not detected within tWHWH, the internal programming cycle will start. Microcontroller Control Interface The M28C16A/17A provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin. Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle. M28C16A, M28C17A Table 4. AC Measurement Conditions ≤ 20ns Input Rise and Fall Times Input Pulse Voltages 0.4V to 2.4V Input and Output Timing Ref. Voltages 0.8V to 2.0V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 5. AC Testing Input Output Waveforms Figure 6. AC Testing Equivalent Load Circuit VCC 4.5V to 5.5V Operating Voltage 2.4V 2.0V IOL 0.8V 0.4V DEVICE UNDER TEST 2.7V to 3.6V Operating Voltage OUT IOH CL = 30pF VCC – 0.3V 0.5 VCC 0V AI02101B CL includes JIG capacitance AI02114 Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol CIN C OUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. Table 6. Read Mode DC Characteristics for M28C16A and M28C17A (TA = –40 to 85°C, VCC = 4.5V to 5.5V) Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC 10 µA ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA E = VIL, G = VIL , f = 5MHz 25 mA E = VIH 1 mA E > VCC – 0.3V 50 µA ICC (1) Supply Current (TTL and CMOS inputs) ICC1 (1) Supply Current (Standby) TTL ICC2 (1) Supply Current (Standby) CMOS VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = –400 µA 2.4 V Note: 1. All I/O’s open circuit. 5/19 M28C16A, M28C17A Table 7. Power Up Timing for M28C16A and M28C17A (1) (TA = –40 to 85°C, VCC = 4.5V to 5.5V) Symbol Parameter Min Max Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ VWI) 10 ms VWI Write Inhibit Threshold 2.5 V 1.5 Note: 1. Sampled only, not 100% tested. Table 8. Read Mode DC Characteristics for M28C16A-W (TA = –40 to 85°C, VCC = 2.7V to 3.6V) Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC 10 µA ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA E = VIL, G = VIL , f = 5 MHz 15 mA E > VCC –0.3V 20 µA ICC ICC2 (1) (1) Supply Current (TTL and CMOS inputs) Supply Current (Standby) CMOS VIL Input Low Voltage –0.3 0.6 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.2 VCC V VOH Output High Voltage IOH = –400 µA 0.8 VCC V Note: 1. All I/O’s open circuit. Table 9. Power Up Timing for M28C16A-W (1) (TA = –40 to 85°C, VCC = 2.7V to 3.6V) Symbol Parameter Max Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ VWI) 10 ms VWI Write Inhibit Threshold 2.5 V Note: 1. Sampled only, not 100% tested. 6/19 Min 1.5 M28C16A, M28C17A Table 10. Read Mode AC Characteristics for M28C16A and M28C17A (TA = –40 to 85°C, VCC = 4.5V to 5.5V) M28C16A / M28C17A Symbol Alt Parameter Test Condition -15 min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV Unit -20 max min max E = VIL, G = VIL 150 200 ns Chip Enable Low to Output Valid G = VIL 150 200 ns tOE Output Enable Low to Output Valid E = VIL 70 80 ns tEHQZ (1) tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 60 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 60 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Table 11. Read Mode AC Characteristics for M28C16-W (TA = –40 to 85°C, VCC = 2.7V to 3.6V) M28C16A / M28C17A Symbol Alt Parameter Test Condition -25 min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV Unit -30 max min max E = VIL, G = VIL 250 300 ns Chip Enable Low to Output Valid G = VIL 250 300 ns tOE Output Enable Low to Output Valid E = VIL 100 100 ns tEHQZ (1) tDF Chip Enable High to Output Hi-Z G = VIL 0 70 0 80 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 0 70 0 80 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. 7/19 M28C16A, M28C17A Figure 7. Read Mode AC Waveforms A0-A10 VALID tAVQV tAXQX E tGLQV tEHQZ G tELQV DQ0-DQ7 tGHQZ DATA OUT Hi-Z AI01511B Note: Write Enable (W) = High Toggle bit (DQ6). The M28C16A/17A offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the first read value is ”0”) on subsequentattempts to read any address in the memory. When the internalcycle is completedthe togglingwill stopand the device will be accessible for a new Read or Write operation. 8/19 Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W up to tWHWH after the previous byte. Up to 32 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High M28C16A, M28C17A Table 12. Write Mode AC Characteristics for M28C16A and M28C17A (TA = –40 to 85°C, VCC = 4.5V to 5.5V) Symbol Alt tAVWL tAS tAVEL Parameter Test Condition Min Max Unit Address Valid to Write Enable Low E = VIL, G = VIH 0 ns tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns tWLAX tAH Write Enable Low to Address Transition 100 ns tELAX tAH Chip Enable Low to Address Transition 100 ns tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs tELEH tWP Chip Enable Low to Chip Enable High 100 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 200 ns tWLWH tWP Write Enable Low to Write Enable High 100 ns tWHWH tBLC Byte Load Repeat Cycle Time 0.2 tWHRH tWC Write Cycle Time tWHRL tDB Write Enable High to Ready/Busy Low tEHRL tDB Chip Enable High to Ready/Busy Low tDVWH tDS Data Valid before Write Enable High 50 ns tDVEH tDS Data Valid before Chip Enable High 50 ns 30 µs 5 ms Note 1 100 ns Note 1 100 ns Note: 1. With a 3.3 kΩ external pull-up resistor. 9/19 M28C16A, M28C17A Table 13. Write Mode AC Characteristics for M28C16-W (TA = –40 to 85°C, VCC = 2.7V to 3.6V) Symbol Alt tAVWL tAS tAVEL Parameter Test Condition Min Address Valid to Write Enable Low E = VIL, G = VIH 0 ns tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns tWLAX tAH Write Enable Low to Address Transition 200 ns tELAX tAH Chip Enable Low to Address Transition 200 ns tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs tELEH tWP Chip Enable Low to Chip Enable High 200 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 200 ns tWLWH tWP Write Enable Low to Write Enable High 200 ns tWHWH tBLC Byte Load Repeat Cycle Time 0.4 tWHRH tWC Write Cycle Time tWHRL tDB Write Enable High to Ready/Busy Low tEHRL tDB Chip Enable High to Ready/Busy Low tDVWH tDS Data Valid before Write Enable High 50 ns tDVEH tDS Data Valid before Chip Enable High 50 ns Note: 1. With a 3.3 kΩ external pull-up resistor. 10/19 Max Unit 50 µs 5 ms Note 1 250 ns Note 1 250 ns M28C16A, M28C17A Figure 8. Write Mode AC Waveforms - Write Enable Controlled A0-A10 VALID tAVWL tWLAX E tELWL tWHEH G tGHWL tWLWH tWHGL W tWLDV tWHWL DATA IN DQ0-DQ7 tDVWH tWHDX RB tWHRL AI01512 Figure 9. Write Mode AC Waveforms - Chip Enable Controlled A0-A10 VALID tAVEL tELAX E tGHEL tELEH G tWLEL tEHGL W tELDV DQ0-DQ7 tEHWH DATA IN tDVEH tEHDX RB tEHRL AI01513 11/19 M28C16A, M28C17A Figure 10. Page Write Mode AC Waveforms - Write Enable Controlled A0-A10 Addr 0 Addr 1 Addr 2 Addr n E tPLTS G tWHWL tWHRH W tWLWH tWHWH Byte 0 DQ0-DQ7 Byte 1 Byte 2 tWHWH Byte n DQ5 Byte n tWHRL RB AI01514 Figure 11. Data Polling Waveform Sequence A0-A10 Address of the last byte of the Page Write instruction E G W DQ7 DQ7 LAST WRITE DQ7 DQ7 DQ7 INTERNAL WRITE SEQUENCE DQ7 READY AI01516 12/19 M28C16A, M28C17A Figure 12. Toggle Bit Waveform Sequence A0-A10 E G W DQ6 (1) LAST WRITE TOGGLE INTERNAL WRITE SEQUENCE READY AI01517 Note: 1. First Toggle bit is forced to ’0’ 13/19 M28C16A, M28C17A ORDERING INFORMATION SCHEME Example: M28C16 – 20 W NS 6 T Option Device Identifier T C16 RB available only for the TSOP package Tape & Reel Packing C17 RB available Speed 15 (1) 150 ns 20 (1) 25 (2) 200 ns 250ns Operating Voltage blank 4.5V to 5.5V 5ms write W 2.7V to 3.6V 5ms write 30 (2) 300ns Package BS PDIP28 Temperature Range 6 –40 to 85 °C MS SO28 300 mils NS TSOP28 8 x 13.4mm KA PLCC32 Notes: 1. Available for M28C16A and M28C17A only. 2. Available for ”W” Operating Voltage only. Devices are shipped from the factory with the memory content set at all ”1’s” (FFh). For a listof availableoptions (Speed, Package,etc... ) or for further informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 14/19 M28C16A, M28C17A PDIP28 - 28 pin Plastic DIP, 600 mils width mm Symb Typ inches Min Max A – A1 Min Max 5.08 – 0.200 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160 B 0.38 0.51 0.015 0.020 – – – – C 0.20 0.30 0.008 0.012 D 36.83 37.34 1.450 1.470 B1 1.52 Typ 0.060 D2 33.02 – – 1.300 – – E 15.24 – – 0.600 – – 13.59 13.84 0.535 0.545 E1 e1 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 15.24 17.78 0.600 0.700 L 3.18 3.43 0.125 0.135 S 1.78 2.08 0.070 0.082 α 0° 10° 0° 10° N 28 28 A2 A1 B1 B A L e1 α eA D2 C eB D S N E1 E 1 PDIP Drawing is not to scale. 15/19 M28C16A, M28C17A PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symb Typ inches Min Max A 2.54 A1 Typ Min Max 3.56 0.100 0.140 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R PLCC Drawing is not to scale. 16/19 CP M28C16A, M28C17A SO28 - 28 lead Plastic Small Outline, 300 mils body width mm Symb Typ inches Min Max A 2.46 A1 Min Max 2.64 0.097 0.104 0.13 0.29 0.005 0.011 A2 2.29 2.39 0.090 0.094 B 0.35 0.48 0.014 0.019 C 0.23 0.32 0.009 0.013 D 17.81 18.06 0.701 0.711 E 7.42 7.59 0.292 0.299 – – – – H 10.16 10.41 0.400 0.410 L 0.61 1.02 0.024 0.040 α 0° 8° 0° 8° N 28 e 1.27 CP Typ 0.050 28 0.10 A2 0.004 A C B CP e D N E H 1 A1 α L SO-b Drawing is not to scale. 17/19 M28C16A, M28C17A TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm mm Symb Typ inches Min Max Typ Min A 1.25 0.049 A1 0.20 0.008 A2 0.95 1.15 0.037 0.045 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 - - - - L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 28 e 0.55 0.022 28 CP 0.10 0.004 A2 22 21 e 28 1 E B 7 8 D1 A CP D DIE C TSOP-c Drawing is not to scale. 18/19 Max A1 α L M28C16A, M28C17A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 19/19