M28W640HCT M28W640HCB 64 Mbit (4 Mb x 16, boot block) 3 V supply Flash memory Preliminary Data Features ■ Supply voltage – VDD = 2.7 V to 3.6 V – VPP = 12 V for fast program (optional) ■ Access times: 70 ns ■ Asynchronous Page Read mode – Page width: 4 words – Page access: 25 ns – Random access: 70 ns ■ Programming time: – 10 µs typical – Double Word Programming option – Quadruple Word Programming option ■ Common Flash interface ■ Memory blocks – Parameter blocks (top or bottom location) – Main blocks ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked – WP for block lock-down ■ Security – 128 bit user programmable OTP cells – 64 bit unique device identifier ■ Automatic standby mode ■ Program and Erase Suspend ■ 100,000 program/erase cycles per block ■ Electronic signature – Manufacturer code: 20h – Top device code, M28W640HCT: 8848h – Bottom device code, M28W640HCB: 8849h March 2008 FBGA TFBGA48 (ZB) 6.39 x 10.5 mm TSOP48 (N) 12 x 20 mm ■ Packages – ECOPACK® compliant Rev 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/72 www.numonyx.com 1 Contents M28W640HCT, M28W640HCB Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 4 2/72 2.1 Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.9 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 M28W640HCT, M28W640HCB 5 6 Contents 4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.12 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.15 Block Lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 26 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Program/Erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Erase Suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 Erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4 Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.5 VPP status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 Program Suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 Block Protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8 Reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3/72 Contents M28W640HCT, M28W640HCB Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Appendix D Command interface and Program/Erase controller state. . . . . . . . 67 11 4/72 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 M28W640HCT, M28W640HCB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read block lock signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program, Erase times and Program/Erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 24 Block Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power-up and Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 42 TFBGA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch, package mechanical data . . 43 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Top boot block addresses, M28W640HCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bottom boot block addresses, M28W640HCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Write state machine current/next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Write state machine current/next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5/72 List of figures M28W640HCT, M28W640HCB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. 6/72 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protection register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power-up and Reset AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 42 TFBGA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch, bottom view package outline 43 Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Double Word Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Quadruple Word Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 62 Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Protection Register Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 66 M28W640HCT, M28W640HCB 1 Description Description The M28W640HCT and M28W640HCB are 64 Mbit (4 Mbit x 16) non-volatile Flash memories that can be erased electrically at block level and programmed in-system on a word-by-word basis using a 2.7 V to 3.6 V VDD supply. An optional 12V VPP power supply is provided to speed up customer programming. The devices feature an asymmetrical blocked architecture. They have an array of 135 blocks: 8 parameter blocks of 4 Kwords and 127 main blocks of 32 Kwords. The M28W640HCT has the parameter blocks at the top of the memory address space while the M28W640HCB locates the parameter blocks starting from the bottom. The memory maps are shown in Figure 4: Block addresses. The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and lockeddown individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 192-bit protection register to increase the protection of a system design. The protection register is divided into a 64-bit segment and a 128-bit segment. The 64-bit segment contains a unique device number written by Numonyx, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 5, shows the protection register memory map. Program and Erase commands are written to the command interface of the memory. An onchip Program/Erase controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (12 × 20 mm) and TFBGA48 (6.39 × 10.5 mm, 0.75 mm pitch) packages and is supplied with all the bits erased (set to ’1’). 7/72 Description M28W640HCT, M28W640HCB Figure 1. Logic diagram VDD VPP 22 16 A0-A21 DQ0-DQ15 W E G M28W640HCT M28W640HCB RP WP VSS AI09903b Table 1. Signal names Name 8/72 Description Direction A0-A21 Address inputs Inputs DQ0-DQ15 Data input/output E Chip Enable Input G Output Enable Input W Write Enable Input RP Reset Input WP Write Protect Input VDD Power supply Power supply VPP Optional supply voltage for fast program & erase Power supply VSS Ground Power supply NC Not connected internally I/O – M28W640HCT, M28W640HCB Figure 2. Description TSOP connections A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 12 M28W640HCT 37 13 M28W640HCB 36 24 25 A16 VDD VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI09904c 1. All VDD pins must be connected to the power supply. 2. All VSS pins must be connected to the ground. 9/72 Description M28W640HCT, M28W640HCB Figure 3. TFBGA connections (top view through package) 1 2 3 A A13 A11 A8 B A14 A10 C A15 D 4 5 6 7 8 VPP WP A19 A7 A4 W RP A18 A17 A5 A2 A12 A9 A21 A20 A6 A3 A1 A16 DQ14 DQ5 DQ11 DQ2 DQ8 E A0 E VDD DQ15 DQ6 DQ12 DQ3 DQ9 DQ0 VSS F VSS DQ7 DQ13 DQ4 VDD DQ10 DQ1 G AI04380c 1. All VDD pins must be connected to the power supply. 2. All VSS pins must be connected to the ground. 10/72 M28W640HCT, M28W640HCB Figure 4. Description Block addresses M28W640HCB Bottom boot block addresses M28W640HCT Top boot block addresses 3FFFFF 3FFFFF 4 Kwords 32 Kwords 3F8000 3F7FFF 3FF000 Total of 8 4 Kword blocks 32 Kwords 3F0000 Total of 127 32 Kword blocks 3F8FFF 4 Kwords 3F8000 3F7FFF 32 Kwords 00FFFF 3F0000 32 Kwords 008000 007FFF 4 Kwords Total of 127 32 Kword blocks 007000 Total of 8 4 Kword blocks 00FFFF 32 Kwords 008000 007FFF 000FFF 32 Kwords 4 Kwords 000000 000000 AI09905b 1. Also see Appendix A, Tables 23 and 24 for a full listing of the block addresses. Figure 5. Protection register memory map PROTECTION REGISTER 8Ch User programmable OTP 85h 84h Unique device number 81h 80h Protection register lock 1 0 AI05520b 11/72 Signal descriptions 2 M28W640HCT, M28W640HCB Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A21) The Address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the internal state machine. 2.2 Data input/output (DQ0-DQ15) The Data I/O outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 Output Enable (G) The Output Enable controls data outputs during the bus read operation of the memory. 2.5 Write Enable (W) The Write Enable controls the bus write operation of the memory’s command interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. 2.6 Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the block cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the block can be locked or unlocked (refer to Table 7: Read Protection Register and Lock Register). 12/72 M28W640HCT, M28W640HCB 2.7 Signal descriptions Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the locked state. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. 2.8 VDD supply voltage VDD provides the power supply to the internal core and the I/O pins of the memory device. It is the main power supply for all operations (read, program and erase). 2.9 VPP program supply voltage VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The supply voltage, VDD, and the program supply voltage, VPP, can be applied in any order. If VPP is kept in a low voltage range (0 V to 3.6 V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Table 15: DC characteristics, for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on program or erase, however for Double or Quadruple Word Program the results are uncertain. If VPP is in the range 11.4 V to 12.6 V it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed (see Table 17 and Table 18). 2.10 VSS ground VSS is the reference for all voltage measurements. Note: Each device in a system should have VDD and VPP decoupled with a 0.1 µF capacitor close to the pin. See Figure 7: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents. 13/72 Bus operations 3 M28W640HCT, M28W640HCB Bus operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Read Read bus operations are used to output the contents of the memory array, the Electronic Signature, the Status Register and the common Flash interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Section 4: Command interface). See Figure 8: Read AC waveforms, and Table 16: Read AC characteristics, for details of when the output becomes valid. Read operations of the memory array can be performed in asynchronous page mode, which provides a fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the electronic signature, the Status Register, the command Flash interface, the Block Protection status, the Configuration Register status and the security code are performed as asynchronous read cycles (Random Read). Both Chip Enable, E, and Output Enable, G, must be at VIL in order to read the output of the memory (see Figure 9: Page Read AC waveforms). Read mode is the default state of the device when exiting reset or after power-up. 3.2 Write Bus write operations write commands to the memory or latch input data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figure 9 and Figure 11, Write AC waveforms, and Table 17 and Table 18, Write AC characteristics, for details of the timing requirements. 3.3 Output Disable The data outputs are high impedance when the Output Enable is at VIH. 3.4 Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the standby level and the outputs are set 14/72 M28W640HCT, M28W640HCB Bus operations to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. 3.5 Automatic Standby Automatic standby provides a low power consumption state during Read mode. Following a read operation, the device enters automatic standby after 150 ns of bus inactivity even if Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data inputs/outputs will still output data if a bus read operation is in progress. 3.6 Reset During Reset mode when Output Enable is Low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a program or erase, this operation is aborted and the memory content is no longer valid. Table 2. Bus operations(1) Operation E G W RP WP VPP DQ0-DQ15 Bus Read VIL VIL VIH VIH X Don't care Data output Bus Write VIL VIH VIL VIH X VDD or VPPH Data input Output Disable VIL VIH VIH VIH X Don't care Hi-Z Standby VIH X X VIH X Don't care Hi-Z X X X VIL X Don't care Hi-Z Reset 1. X = VIL or VIH, VPPH = 12 V ± 5%. 15/72 Command interface 4 M28W640HCT, M28W640HCB Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. An internal Program/Erase controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase controller provides a Status Register whose output may be read at any time to monitor the progress of the operation, or the Program/Erase states. See Table 3: Command codes, for a summary of the commands and see Appendix D, Table 31: Write state machine current/next, for a summary of the command interface. The command interface is reset to Read mode when power is first applied, when exiting from reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 4: Commands, in conjunction with the text descriptions below. 4.1 Read Memory Array command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. 4.2 Read Status Register command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register’s contents. Subsequent bus read operations read the Status Register at any address, until another command is issued. See Table 11: Status Register bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a program/erase operation. Any read attempt during a program/erase operation will automatically output the content of the Status Register. 4.3 Read Electronic Signature command The Read Electronic Signature command reads the manufacturer and device codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the manufacturer code, the device code, the Block Lock and Lock-Down Status, or the Protection and Lock Register. See Tables 5, 6 and 7 for the valid address. 16/72 M28W640HCT, M28W640HCB Table 3. Command interface Command codes Hex code 4.4 Command 01h Block Lock confirm 10h Program 20h Erase 2Fh Block Lock-down confirm 30h Double Word Program 40h Program 50h Clear Status Register 56h Quadruple Word Program 60h Block Lock, Block Unlock, Block Lock-down 70h Read Status Register 90h Read Electronic Signature 98h Read CFI Query B0h Program/Erase Suspend C0h Protection Register Program D0h Program/Erase Resume, Block Unlock confirm FFh Read Memory Array Read CFI Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent bus read operations read from the common Flash interface memory area. See Appendix B: Common Flash interface (CFI), tables 25, 26, 27, 28, 29 and 30 for details on the information contained in the common Flash interface memory area. 4.5 Block Erase command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command: ● The first bus cycle sets up the Erase command ● The second latches the block address in the internal state machine and starts the Program/Erase controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. 17/72 Command interface M28W640HCT, M28W640HCB Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. During erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 8: Program, Erase times and Program/Erase endurance cycles. See Appendix C, Figure 19: Erase flowchart and pseudocode, for a suggested flowchart for using the Erase command. 4.6 Program command The memory array can be programmed word-by-word. Two bus write cycles are required to issue the Program command: ● The first bus cycle sets up the Program command. ● The second latches the address and the data to be written and starts the Program/Erase controller. During program operations the memory will accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 8: Program, Erase times and Program/Erase endurance cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 15: Program flowchart and pseudocode, for the flowchart for using the Program command. 4.7 Double Word Program command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. Three bus write cycles are necessary to issue the Double Word Program command: ● The first bus cycle sets up the Double Word Program command ● The second bus cycle latches the address and the data of the first word to be written ● The third bus cycle latches the address and the data of the second word to be written and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 16: Double Word Program flowchart and pseudocode for the flowchart for using the Double Word Program command. 18/72 M28W640HCT, M28W640HCB 4.8 Command interface Quadruple Word Program command This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. Five bus write cycles are necessary to issue the Quadruple Word Program command: ● The first bus cycle sets up the Quadruple Word Program command. ● The second bus cycle latches the address and the data of the first word to be written ● The third bus cycle latches the address and the data of the second word to be written ● The fourth bus cycle latches the address and the data of the third word to be written ● The fifth bus cycle latches the address and the data of the fourth word to be written and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 17: Quadruple Word Program flowchart and pseudocode, for the flowchart for using the Quadruple Word Program command. 4.9 Clear Status Register command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. 4.10 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a program or erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the command interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, Block Lock-down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 18: Program Suspend & Resume flowchart and pseudocode, and Figure 20: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Suspend command. 19/72 Command interface 4.11 M28W640HCT, M28W640HCB Program/Erase Resume command The Program/Erase Resume command can be used to restart the Program/Erase controller after a program/erase suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent bus read operations read the Status Register. See Appendix C, Figure 18: Program Suspend & Resume flowchart and pseudocode, and Figure 20: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Resume command. 4.12 Protection Register Program command The Protection Register Program command is used to program the 128 bit user one-timeprogrammable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protection Register Program command: ● The first bus cycle sets up the Protection Register Program command ● The second latches the address and the data to be written to the Protection Register and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 5: Protection register memory map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. 4.13 Block Lock command The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command: ● The first bus cycle sets up the Block Lock command ● The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 10 shows the protection status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or powerdown/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. 20/72 M28W640HCT, M28W640HCB 4.14 Command interface Block Unlock command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command: ● The first bus cycle sets up the Block Unlock command ● The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 10 shows the protection status after issuing a Block Unlock command. Refer to the Section 5: Block locking, for a detailed explanation. 4.15 Block Lock-down command A locked block cannot be programmed or erased, or have its protection status changed when WP is Low, VIL. When WP is High, VIH, the Lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-down command: ● The first bus cycle sets up the Block Lock command ● The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 10 shows the protection status after issuing a Block Lock-down command. Refer to the Section 5: Block locking for a detailed explanation. 21/72 Command interface Table 4. M28W640HCT, M28W640HCB Commands(1) Commands Cycles Bus write operations 1st cycle Op. Add Data 2nd cycle Op. 3rd cycle Add Data 4th cycle 5th cycle Op. Add Data Op. Add Data Op. Add Data Read Memory 1+ Write Array X FFh Read RA RD Read Status Register 1+ Write X 70h Read X SRD Read Electronic Signature 1+ Write X 90h Read SA(2) IDh Read CFI Query 1+ Write X 98h Read QA QD Erase 2 Write X 20h Write BA D0h Program 2 Write X 40h or Write 10h PA PD Double Word Program(3) 3 Write X 30h Write PA1 PD1 Write PA2 PD2 Quadruple Word Program(4) 5 Write X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4 Clear Status Register 1 Write X 50h Program/Erase 1 Suspend Write X B0h Program/Erase 1 Resume Write X D0h Block Lock 2 Write X 60h Write BA 01h Block Unlock 2 Write X 60h Write BA D0h Block Lockdown 2 Write X 60h Write BA 2Fh Protection Register Program 2 Write X C0h Write PRA PRD 1. X = Don't care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (manufacturer and device code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data. 2. The signature addresses are listed in Tables 5, 6 and 7. 3. Program addresses 1 and 2 must be consecutive addresses differing only for A0. 4. Program addresses 1,2,3 and 4 must be consecutive addresses differing only for A0 and A1. 22/72 M28W640HCT, M28W640HCB Table 5. Command interface Read electronic signature(1) Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15 VIL VIL VIH VIL VIL 0 Don't care 20h 00h M28W640HCT VIL VIL VIH VIH VIL 0 Don't care 48h 88h M28W640HCB VIL VIL VIH VIH VIL 0 Don't care 49h 88h Manufacturer code Device code 1. RP = VIH. Table 6. Read block lock signature Block status E G W A0 A1 A2-A7 Locked block VIL VIL VIH VIL VIH 0 Unlocked block VIL VIL VIH VIL VIH Locked-down block VIL VIL VIH VIL VIH A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15 Don't care Block address 1 0 00h 0 Don't care Block address 0 0 00h 0 Don't care Block address X(1) 1 00h 1. A locked-down block can be locked ‘DQ0 = 1’ or unlocked ‘DQ0 = 0’; see Section 5: Block locking. Table 7. Read Protection Register and Lock Register E G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3DQ7 DQ8DQ15 Lock VIL VIL VIH 80h Don't care 0 OTP Prot. data 0 00h 00h Unique ID 0 VIL VIL VIH 81h Don't care ID data ID data ID data ID data ID data Unique ID 1 VIL VIL VIH 82h Don't care ID data ID data ID data ID data ID data Unique ID 2 VIL VIL VIH 83h Don't care ID data ID data ID data ID data ID data Unique ID 3 VIL VIL VIH 84h Don't care ID data ID data ID data ID data ID data OTP 0 VIL VIL VIH 85h Don't care OTP data OTP data OTP data OTP data OTP data OTP 1 VIL VIL VIH 86h Don't care OTP data OTP data OTP data OTP data OTP data OTP 2 VIL VIL VIH 87h Don't care OTP data OTP data OTP data OTP data OTP data OTP 3 VIL VIL VIH 88h Don't care OTP data OTP data OTP data OTP data OTP data OTP 4 VIL VIL VIH 89h Don't care OTP data OTP data OTP data OTP data OTP data OTP 5 VIL VIL VIH 8Ah Don't care OTP data OTP data OTP data OTP data OTP data OTP 6 VIL VIL VIH 8Bh Don't care OTP data OTP data OTP data OTP data OTP data OTP 7 VIL VIL VIH 8Ch Don't care OTP data OTP data OTP data OTP data OTP data Word 23/72 Command interface Table 8. M28W640HCT, M28W640HCB Program, Erase times and Program/Erase endurance cycles M28W640HCT, M28W640HCB Parameter Test conditions Unit Min Typ Max VPP = VDD 10 200 µs Double Word Program VPP = 12 V ± 5% 10 200 µs Quadruple Word Program VPP = 12 V ± 5% 10 200 µs 5 s 5 s 4 s Word Program Main Block Program (1) VPP = 12 V ± 5% 0.16/0.08 VPP = VDD Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase cycles (per block) 0.32 (1) VPP = 12 V ± 5% 0.02/0.01 VPP = VDD 0.04 4 s VPP = 12 V ± 5% 1 10 s VPP = VDD 1 10 s VPP = 12 V ± 5% 0.4 10 s VPP = VDD 0.4 10 s 100,000 cycles 1. Typical time to program a main or parameter block using the Double Word Program and the Quadruple Word Program commands respectively. 24/72 M28W640HCT, M28W640HCB 5 Block locking Block locking The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection: ● Lock/unlock - this first level allows software-only control of block locking ● Lock-down - this second level requires hardware interaction before locking can be changed ● VPP ≤VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to ‘Locked’, ‘Unlocked’, and ‘Lock-down’. Table 10, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 21, shows a flowchart for the locking operations. 5.1 Reading a block’s lock status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-down. DQ1 indicates the Lock-down status and is set by the Lock-down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. 5.2 Locked state The default status of all blocks on power-up or after a hardware reset is ‘Locked’ (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The status of a locked block can be changed to ‘Unlocked’ or ‘Lock-down’ using the appropriate software commands. An unlocked block can be locked by issuing the Lock command. 5.3 Unlocked state Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to ‘Locked’ or ‘Locked-down’ using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. 25/72 Block locking 5.4 M28W640HCT, M28W640HCB Lock-down state Blocks that are Locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by issuing the Lock-down command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The Lock-down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-down function is disabled (1,1,1) and Locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while WP remains High. When WP is Low, blocks that were previously Locked-down return to the Lock-down state (0,1,x) regardless of any changes made while WP was High. Device reset or power-down resets all blocks, including those in Lock-down or in a Locked state. 5.5 Locking operations during Erase Suspend Changes to block lock status can be performed during an Erase Suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the Lock Status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is Locked or Locked-down during an Erase Suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a Program Suspend. Refer to Appendix D, command interface and Program/Erase controller state, for detailed information on which commands are valid during Erase Suspend. Table 9. Block Lock status Item Address Block Lock configuration Data LOCK Block is Unlocked DQ0=0 xx002 26/72 Block is Locked DQ0=1 Block is Locked-down DQ1=1 M28W640HCT, M28W640HCB Table 10. Block locking Protection status Current Protection status(1) Next Protection status(1) (WP, DQ1, DQ0) (WP, DQ1, DQ0) Current state Program/Erase allowed After Block Lock command After Block Unlock command After Block Lock-down command After WP transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 no 0,0,1 0,0,0 0,1,1 1,0,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3) 1,0,1 0,0,1 (2) (2) 0,1,1 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. 27/72 Status Register 6 M28W640HCT, M28W640HCB Status Register The Status Register provides information on the current or previous program or erase operation. The various bits convey information and errors on the operation. To read the Status Register the Read Status Register command can be issued, refer to Section 4.2: Read Status Register command. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus read operations from any address always read the Status Register during program and erase operations. The bits in the Status Register are summarized in Table 11: Status Register bits. Refer to Table 11 in conjunction with the following text descriptions. 6.1 Program/Erase controller status (bit 7) The Program/Erase controller status bit indicates whether the Program/Erase controller is active or inactive. When the Program/Erase controller status bit is Low (set to ‘0’), the Program/Erase controller is active; when the bit is High (set to ‘1’), the Program/Erase controller is inactive, and the device is ready to process a new command. The Program/Erase controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase controller pauses. After the Program/Erase controller pauses the bit is High. During program, erase, operations the Program/Erase controller status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase controller completes the operation and the bit is High. After the Program/Erase controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. 6.2 Erase Suspend status (bit 6) The Erase Suspend status bit indicates that an erase operation has been suspended or is going to be suspended. When the Erase Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase controller status bit is High (Program/Erase controller inactive). Bit 7 is set within 30 µs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. 28/72 M28W640HCT, M28W640HCB 6.3 Status Register Erase status (bit 5) The Erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase status bit is High (set to ‘1’), the Program/Erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase controller status bit is High (Program/Erase controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 6.4 Program status (bit 4) The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Program/Erase controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase controller status bit is High (Program/Erase controller inactive). Once set High, the Program status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 6.5 VPP status (bit 3) The VPP status bit can be used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage; when the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 6.6 Program Suspend status (bit 2) The Program Suspend status bit indicates that a program operation has been suspended. When the Program Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend status should only be considered valid when the Program/Erase controller status bit is High (Program/Erase controller inactive). Bit 2 is set within 5 µs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. 29/72 Status Register 6.7 M28W640HCT, M28W640HCB Block Protection status (bit 1) The Block Protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a locked block. When the Block Protection status bit is High (set to ‘1’), a program or erase operation has been attempted on a locked block. Once set High, the Block Protection status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 6.8 Reserved (bit 0) Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix C: Flowcharts and pseudocodes, for using the Status Register. Table 11. Status Register bits(1) Bit 7 6 5 4 3 2 1 0 Name Definition '1' Ready '0' Busy '1' Suspended '0' In progress or completed '1' Erase error '0' Erase success '1' Program error '0' Program success '1' VPP invalid, abort '0' VPP OK '1' Suspended '0' In progress or completed '1' Program/Erase on protected Block, abort '0' No operation to protected blocks P/E.controller status Erase Suspend status Erase status Program status VPP status Program Suspend status Block Protection status Reserved 1. Logic level '1' is High, '0' is Low. 30/72 Logic level M28W640HCT, M28W640HCB 7 Maximum ratings Maximum ratings Stressing the device above the rating listed in Table 12: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 12. Absolute maximum ratings Value Symbol Parameter Unit Min Max Ambient operating temperature – 40 85 °C TBIAS Temperature under bias – 40 125 °C TSTG Storage temperature – 55 155 °C VIO Input or output voltage – 0.6 VDD+0.6 V VDD Supply voltage – 0.6 4.1 V VPP Program voltage – 0.6 13 V TA 31/72 DC and AC parameters 8 M28W640HCT, M28W640HCB DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 13: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 13. Operating and AC measurement conditions M28W640HCT, M28W640HCB Parameter 70 ns Units Min Max VDD supply voltage 2.7 3.6 V Ambient operating temperature –40 85 °C Load capacitance (CL) 50 Input rise and fall times 5 Input pulse voltages Input and output timing reference voltages Figure 6. V VDD/2 V AC measurement I/O waveform VDD/2 0V AI00610b AC measurement load circuit VDD VDD 25 kW DEVICE UNDER TEST CL 25 kW 0.1 µF CL includes JIG capacitance 32/72 ns 0 to VDD VDD Figure 7. pF AI00609d M28W640HCT, M28W640HCB Table 14. Symbol CIN COUT DC and AC parameters Capacitance(1) Parameter Input capacitance Output capacitance Test condition Min Max Unit VIN = 0 V 6 pF VOUT = 0 V 12 pF 1. Sampled only, not 100% tested. 33/72 DC and AC parameters Table 15. Symbol M28W640HCT, M28W640HCB DC characteristics Parameter Test condition Min Typ Max Unit 0 V ≤VIN ≤VDD ±1 µA ±10 µA ILI Input Leakage current ILO Output Leakage current 0 V ≤ VOUT ≤VDD IDD Supply current (Read) E = VSS, G = VIH, f = 5 MHz 9 18 mA IDD1 Supply current (Standby or Automatic Standby) E = VDD ± 0.2 V, RP = VDD ± 0.2 V 15 50 µA IDD2 Supply current (Reset) RP = VSS ± 0.2 V 15 50 µA Program in progress VPP = 12 V ± 5% 5 10 mA Program in progress VPP = VDD 10 20 mA Erase in progress VPP = 12 V ± 5% 10 20 mA Erase in progress VPP = VDD 10 20 mA E = VDD ± 0.2 V, Erase suspended 15 50 µA IDD3 IDD4 Supply current (Program) Supply current (Erase) IDD5 Supply current (Program/Erase Suspend) IPP Program current (Read or Standby) VPP > VDD 400 µA IPP1 Program current (Read or Standby) VPP ≤VDD 1 5 µA IPP2 Program current (Reset) RP = VSS ± 0.2 V 1 5 µA Program in progress VPP = 12 V ± 5% 1 10 mA Program in progress VPP = VDD 1 5 µA Erase in progress VPP = 12V ± 5% 3 10 mA Erase in progress VPP = VDD 1 5 µA –0.5 0.4 V VDD – 0.4 VDD + 0.4 V 0.1 V IPP3 IPP4 Program current (Program) Program Current (Erase) VIL Input Low voltage VIH Input High voltage VOL Output Low voltage IOL = 100 µA, VDD = VDD min VOH Output High voltage IOH = –100 µA, VDD = VDD min VPP1 Program voltage (program or erase operations) 1.65 3.6 V VPPH Program voltage (program or erase operations) 11.4 12.6 V VPPLK Program voltage (program and erase lockout) 1 V VLKO VDD supply voltage (Program and Erase lock-out) 2 V 34/72 VDD – 0.1 V M28W640HCT, M28W640HCB Figure 8. DC and AC parameters Read AC waveforms tAVAV VALID A0-A21 tAVQV tAXQX E tELQV tELQX tEHQX tEHQZ G tGLQV tGHQX tGLQX tGHQZ DQ0DQ15 VALID ADDR. VALID CHIP ENABLE OUTPUTS ENABLED DATA VALID STANDBY AI04387 Table 16. Symbol Read AC characteristics Alt M28W640HCT, M28W640HCB Parameter 70 ns Unit tAVAV tRC Address valid to Next Address Valid Min 70 ns tAVQV tACC Address valid to Random Output Valid Max 70 ns tAXQX(1) tOH Address Transition to Output Transition Min 0 ns tEHQX(1) tOH Chip Enable High to Output Transition Min 0 ns tEHQZ(1) tHZ Chip Enable High to Output Hi-Z Max 20 ns tELQV(2) tCE Chip Enable Low to Output Valid Max 70 ns tELQX(1) tLZ Chip Enable Low to Output Transition Min 0 ns tGHQX(1) tOH Output Enable High to Output Transition Min 0 ns tGHQZ(1) tDF Output Enable High to Output Hi-Z Max 20 ns tGLQV(2) tOE Output Enable Low to Output Valid Max 20 ns tGLQX(1) tOLZ Output Enable Low to Output Transition Min 0 ns tAVQV1 tPAGE Page address Valid to Page Output Valid Max 25 ns Min 0 ns tAXQX1 tOH Address Transition to Page Output Transition 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 35/72 36/72 DQ0-DQ15 G E tAVQV tELQV VALID VALID tGLQV VALID tAVQV1 VALID VALID VALID VALID tEHQX VALID tGHQX VALID tEHQZ tGHQZ AI06191b tAXQX1 Figure 9. A0-A1 A2-A21 DC and AC parameters M28W640HCT, M28W640HCB Page Read AC waveforms VPP WP DQ0-DQ15 W G E A0-A21 tWLWH COMMAND SET-UP COMMAND tDVWH tELWL tWHDX tWHWL tWHEH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHWH tWPHWH tAVWH VALID tAVAV tWHEL tWHGL tWHAX PROGRAM OR ERASE AI04388 tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV M28W640HCT, M28W640HCB DC and AC parameters Figure 10. Write AC waveforms, Write Enable controlled 37/72 DC and AC parameters Table 17. Symbol M28W640HCT, M28W640HCB Write AC characteristics, Write Enable controlled Alt Parameter 70 ns Unit tAVAV tWC Write Cycle time Min 70 ns tAVWH tAS Address Valid to Write Enable High Min 45 ns tDVWH tDS Data Valid to Write Enable High Min 45 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns Chip Enable Low to Output Valid Min 70 ns Output Valid to VPP Low Min 0 ns Output Valid to Write Protect Low Min 0 ns tELQV tQVVPL(1)(2) tQVWPL tVPHWH(1) tVPS VPP High to Write Enable High Min 200 ns tWHAX tAH Write Enable High to Address Transition Min 0 ns tWHDX tDH Write Enable High to Data Transition Min 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 ns tWHEL Write Enable High to Chip Enable Low Min 25 ns tWHGL Write Enable High to Output Enable Low Min 20 ns tWHWL tWPH Write Enable High to Write Enable Low Min 25 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 ns Write Protect High to Write Enable High Min 45 ns tWPHWH 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6 V). 38/72 M28W640HCT, M28W640HCB VPP WP DQ0-DQ15 E G W A0-A21 tELEH COMMAND POWER-UP AND SET-UP COMMAND tDVEH tWLEL tEHDX tEHEL tEHWH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHEH tWPHEH tAVEH VALID tAVAV tEHGL tEHAX PROGRAM OR ERASE AI04389 tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV M28W640HCT, M28W640HCB DC and AC parameters Figure 11. Write AC waveforms, Chip Enable controlled 39/72 DC and AC parameters Table 18. M28W640HCT, M28W640HCB Write AC characteristics, Chip Enable controlled Symbol Alt Parameter 70 ns Unit tAVAV tWC Write Cycle time Min 70 ns tAVEH tAS Address Valid to Chip Enable High Min 45 ns tDVEH tDS Data Valid to Chip Enable High Min 45 ns tEHAX tAH Chip Enable High to Address Transition Min 0 ns tEHDX tDH Chip Enable High to Data Transition Min 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 ns Chip Enable High to Output Enable Low Min 25 ns tEHGL tEHWH tWH Chip Enable High to Write Enable High Min 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 45 ns Chip Enable Low to Output Valid Min 70 ns Output Valid to VPP Low Min 0 ns Data Valid to Write Protect Low Min 0 ns tVPS VPP High to Chip Enable High Min 200 ns tCS Write Enable Low to Chip Enable Low Min 0 ns Write Protect High to Chip Enable High Min 45 ns tELQV tQVVPL (1)(2) tQVWPL tVPHEH (1) tWLEL tWPHEH 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6 V). 40/72 M28W640HCT, M28W640HCB M28W640HCT, M28W640HCB DC and AC parameters Figure 12. Power-up and Reset AC waveforms W, E, G tPHWL tPHEL tPHGL tPHWL tPHEL tPHGL RP tVDHPH tPLPH VDD Power-up Reset AI03537c Table 19. Symbol tPHWL tPHEL tPHGL Power-up and Reset AC characteristics Parameter Reset High to Write Enable Low, Chip Enable Low, Output Enable Low M28W640HCT, M28W640HCB Test condition 70 ns Unit During program and erase Min 50 µs others Min 30 ns tPLPH(1)(2) Reset Low to Reset High Min 100 ns tVDHPH(3) Supply voltages High to Reset High Min 300 µs 1. The device reset is possible but not guaranteed if tPLPH < 100 ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset. 41/72 Package mechanical 9 M28W640HCT, M28W640HCB Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 13. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 1 48 e D1 B 24 L1 25 A2 E1 E A A1 DIE α L C CP TSOP-G 1. Drawing is not to scale. Table 20. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data millimeters inches Symbol Typ Min A Typ Min 1.20 Max 0.047 A1 0.10 0.05 0.15 0.004 0.002 0.006 A2 1.00 0.95 1.05 0.039 0.037 0.041 B 0.22 0.17 0.27 0.009 0.007 0.011 0.10 0.21 0.004 0.008 C CP 42/72 Max 0.10 0.004 D1 12.00 11.90 12.10 0.472 0.468 0.476 E 20.00 19.80 20.20 0.787 0.779 0.795 E1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 – – 0.020 – – L 0.60 0.50 0.70 0.024 0.020 0.028 L1 0.80 α 3° 0° 5° 0.031 0° 5° 3° M28W640HCT, M28W640HCB Package mechanical Figure 14. TFBGA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch, bottom view package outline D D1 SD FD FE SE E E1 e BALL "A1" ddd e b A2 A A1 BGA-Z34 1. Drawing is not to scale. Table 21. TFBGA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.20 A1 0.047 0.26 A2 Max 0.010 1.00 0.039 b 0.40 0.35 0.45 0.016 0.014 0.018 D 6.39 6.29 6.49 0.252 0.248 0.255 D1 5.250 – – 0.207 – – ddd 0.10 0.004 E 10.50 10.40 10.60 0.413 0.409 0.417 E1 3.75 – – 0.148 – – e 0.75 – – 0.029 – – FD 0.57 – – 0.022 – – FE 3.37 – – 0.133 – – SD 0.37 – – 0.015 – – SE 0.37 – – 0.015 – – 43/72 Ordering information 10 M28W640HCT, M28W640HCB Ordering information Table 22. Ordering information scheme Example: M28W640HCT 70 N 6 E Device type M28 Operating voltage W = VDD = 2.7 V to 3.6 V Device function 640HC = 64 Mbit (4 Mb x 16), boot block Array matrix T = top boot B = bottom boot Speed 70 = 70 ns Package N = TSOP48: 12 x 20 mm ZB = TFBGA48: 6.39 x 10.5 mm, 0.75 mm pitch Temperature range 6 = –40 to 85 °C Option E = ECOPACK® package, standard packing F = ECOPACK® package, tape & reel packing Note: 44/72 Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. M28W640HCT, M28W640HCB Appendix A Block address tables Block address tables Table 23. Top boot block addresses, M28W640HCT # Size (Kword) Address range 0 4 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 4 4 3FB000-3FBFFF 5 4 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 3F8000-3F8FFF 8 32 3F0000-3F7FFF 9 32 3E8000-3EFFFF 10 32 3E0000-3E7FFF 11 32 3D8000-3DFFFF 12 32 3D0000-3D7FFF 13 32 3C8000-3CFFFF 14 32 3C0000-3C7FFF 15 32 3B8000-3BFFFF 16 32 3B0000-3B7FFF 17 32 3A8000-3AFFFF 18 32 3A0000-3A7FFF 19 32 398000-39FFFF 20 32 390000-397FFF 21 32 388000-38FFFF 22 32 380000-387FFF 23 32 378000-37FFFF 24 32 370000-377FFF 25 32 368000-36FFFF 26 32 360000-367FFF 27 32 358000-35FFFF 28 32 350000-357FFF 29 32 348000-34FFFF 30 32 340000-347FFF 31 32 338000-33FFFF 45/72 Block address tables Table 23. 46/72 M28W640HCT, M28W640HCB Top boot block addresses, M28W640HCT (continued) # Size (Kword) Address range 32 32 330000-337FFF 33 32 328000-32FFFF 34 32 320000-327FFF 35 32 318000-31FFFF 36 32 310000-317FFF 37 32 308000-30FFFF 38 32 300000-307FFF 39 32 2F8000-2FFFFF 40 32 2F0000-2F7FFF 41 32 2E8000-2EFFFF 42 32 2E0000-2E7FFF 43 32 2D8000-2DFFFF 44 32 2D0000-2D7FFF 45 32 2C8000-2CFFFF 46 32 2C0000-2C7FFF 47 32 2B8000-2BFFFF 48 32 2B0000-2B7FFF 49 32 2A8000-2AFFFF 50 32 2A0000-2A7FFF 51 32 298000-29FFFF 52 32 290000-297FFF 53 32 288000-28FFFF 54 32 280000-287FFF 55 32 278000-27FFFF 56 32 270000-277FFF 57 32 268000-26FFFF 58 32 260000-267FFF 59 32 258000-25FFFF 60 32 250000-257FFF 61 32 248000-24FFFF 62 32 240000-247FFF 63 32 238000-23FFFF 64 32 230000-237FFF 65 32 228000-22FFFF 66 32 220000-227FFF M28W640HCT, M28W640HCB Table 23. Block address tables Top boot block addresses, M28W640HCT (continued) # Size (Kword) Address range 67 32 218000-21FFFF 68 32 210000-217FFF 69 32 208000-20FFFF 70 32 200000-207FFF 71 32 1F8000-1FFFFF 72 32 1F0000-1F7FFF 73 32 1E8000-1EFFFF 74 32 1E0000-1E7FFF 75 32 1D8000-1DFFFF 76 32 1D0000-1D7FFF 77 32 1C8000-1CFFFF 78 32 1C0000-1C7FFF 79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF 82 32 1A0000-1A7FFF 83 32 198000-19FFFF 84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF 100 32 110000-117FFF 101 32 108000-10FFFF 47/72 Block address tables Table 23. 48/72 M28W640HCT, M28W640HCB Top boot block addresses, M28W640HCT (continued) # Size (Kword) Address range 102 32 100000-107FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF 111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF 116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF 119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF 124 32 050000-057FFF 125 32 048000-04FFFF 126 32 040000-047FFF 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF 130 32 020000-027FFF 131 32 018000-01FFFF 132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF M28W640HCT, M28W640HCB Table 24. Block address tables Bottom boot block addresses, M28W640HCB # Size (Kword) Address range 134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 131 32 3E0000-3E7FFF 130 32 3D8000-3DFFFF 129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 32 3B0000-3B7FFF 124 32 3A8000-3AFFFF 123 32 3A0000-3A7FFF 122 32 398000-39FFFF 121 32 390000-397FFF 120 32 388000-38FFFF 119 32 380000-387FFF 118 32 378000-37FFFF 117 32 370000-377FFF 116 32 368000-36FFFF 115 32 360000-367FFF 114 32 358000-35FFFF 113 32 350000-357FFF 112 32 348000-34FFFF 111 32 340000-347FFF 110 32 338000-33FFFF 109 32 330000-337FFF 108 32 328000-32FFFF 107 32 320000-327FFF 106 32 318000-31FFFF 105 32 310000-317FFF 104 32 308000-30FFFF 103 32 300000-307FFF 102 32 2F8000-2FFFFF 101 32 2F0000-2F7FFF 100 32 2E8000-2EFFFF 49/72 Block address tables Table 24. 50/72 M28W640HCT, M28W640HCB Bottom boot block addresses, M28W640HCB (continued) # Size (Kword) Address range 99 32 2E0000-2E7FFF 98 32 2D8000-2DFFFF 97 32 2D0000-2D7FFF 96 32 2C8000-2CFFFF 95 32 2C0000-2C7FFF 94 32 2B8000-2BFFFF 93 32 2B0000-2B7FFF 92 32 2A8000-2AFFFF 91 32 2A0000-2A7FFF 90 32 298000-29FFFF 89 32 290000-297FFF 88 32 288000-28FFFF 87 32 280000-287FFF 86 32 278000-27FFFF 85 32 270000-277FFF 84 32 268000-26FFFF 83 32 260000-267FFF 82 32 258000-25FFFF 81 32 250000-257FFF 80 32 248000-24FFFF 79 32 240000-247FFF 78 32 238000-23FFFF 77 32 230000-237FFF 76 32 228000-22FFFF 75 32 220000-227FFF 74 32 218000-21FFFF 73 32 210000-217FFF 72 32 208000-20FFFF 71 32 200000-207FFF 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF M28W640HCT, M28W640HCB Table 24. Block address tables Bottom boot block addresses, M28W640HCB (continued) # Size (Kword) Address range 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF 57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 51/72 Block address tables Table 24. 52/72 M28W640HCT, M28W640HCB Bottom boot block addresses, M28W640HCB (continued) # Size (Kword) Address range 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF 11 32 020000-027FFF 10 32 018000-01FFFF 9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF 4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF M28W640HCT, M28W640HCB Appendix B Common Flash interface (CFI) Common Flash interface (CFI) The Common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 25, 26, 27, 28, 29 and 30 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 30: Security code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read command to return to Read mode. Table 25. Query structure overview(1) Offset Sub-section name Description 00h Reserved Reserved for algorithm-specific information 10h CFI Query identification string Command set ID and algorithm data offset 1Bh System interface information Device timing & voltage information 27h Device geometry definition Flash device layout P Primary algorithm-specific extended query table Additional information specific to the primary algorithm (optional) A Alternate algorithm-specific extended query Additional information specific to the table alternate algorithm (optional) 1. Query data are always presented on the lowest order data outputs. 53/72 Common Flash interface (CFI) Table 26. M28W640HCT, M28W640HCB CFI query identification string(1) Offset Data Description 00h 0020h Manufacturer code 01h 8848h 8849h Device code Value Numonyx Top Bottom 02h-0Fh reserved Reserved 10h 0051h 11h 0052h 12h 0059h 13h 0003h 14h 0000h 15h 0035h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h ‘Q’ Query unique ASCII string ‘QRY’ ‘R’ ‘Y’ Primary algorithm command set and control interface ID code 16 bit ID code defining a specific algorithm Address for primary algorithm extended query table (see Table 28) Intel compatible P = 35h Alternate vendor command set and control interface ID code second vendor - specified algorithm supported (0000h means none exists) NA Address for Alternate algorithm extended query table (0000h means none exists) NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 54/72 M28W640HCT, M28W640HCB Table 27. Common Flash interface (CFI) CFI query system interface information Offset Data 1Bh 0027h VDD logic supply minimum program/erase or write voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 2.7 V 1Ch 0036h VDD logic supply maximum Program/Erase or Write voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 3.6 V 1Dh 00B4h VPP [programming] supply minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 11.4 V 1Eh 00C6h VPP [programming] supply maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 12.6 V 1Fh 0004h Typical time-out per single word program = 2n µs 16 µs 20h 0004h Description Value n Typical time-out for Double/Quadruple Word Program = 2 µs n 16 µs 21h 000Ah Typical time-out per individual block erase = 2 ms 1s 22h 0000h Typical time-out for full chip erase = 2n ms NA 0005h n 23h Maximum time-out for Word program = 2 times typical 512 µs n 24h 0005h Maximum time-out for Double/Quadruple Word Program = 2 times typical 25h 0003h Maximum time-out per individual block erase = 2n times typical 26h 0000h n Maximum time-out for chip erase = 2 times typical 512 µs 8s NA 55/72 Common Flash interface (CFI) M28W640HCB M28W640HCT Table 28. 56/72 M28W640HCT, M28W640HCB Device geometry definition Offset Word Mode Data 27h 0017h Device size = 2n in number of bytes 8 Mbyte 28h 29h 0001h 0000h Flash device interface code description x 16 Async. 2Ah 2Bh 0003h 0000h Maximum number of bytes in multi-byte program or page = 2n 8 2Ch 0002h Number of Erase block regions within the device. It specifies the number of regions within the device containing contiguous Erase blocks of the same size. 2 2Dh 2Eh 007Eh 0000h Region 1 information Number of identical-size erase block = 007Eh+1 2Fh 30h 0000h 0001h Region 1 information Block size in Region 1 = 0100h * 256 byte 31h 32h 0007h 0000h Region 2 information Number of identical-size erase block = 0007h+1 33h 34h 0020h 0000h Region 2 information Block size in region 2 = 0020h * 256 byte 2Dh 2Eh 0007h 0000h Region 1 information Number of identical-size erase block = 0007h+1 2Fh 30h 0020h 0000h Region 1 information Block size in region 1 = 0020h * 256 byte 31h 32h 007Eh 0000h Region 2 information Number of identical-size erase block = 007Eh=1 33h 34h 0000h 0001h Region 2 information Block size in region 2 = 0100h * 256 byte Description Value 127 64 Kbyte 8 8 Kbyte 8 8 Kbyte 127 64 Kbyte M28W640HCT, M28W640HCB Table 29. Common Flash interface (CFI) Primary algorithm-specific extended query table Offset P = 35h(1) Data (P+0)h = 35h 0050h (P+1)h = 36h 0052h (P+2)h = 37h 0049h (P+3)h = 38h 0031h Major version number, ASCII ‘1’ (P+4)h = 39h 0030h Minor version number, ASCII ‘0’ (P+5)h = 3Ah 0066h (P+6)h = 3Bh 0000h (P+7)h = 3Ch 0000h (P+8)h = 3Dh 0000h Extended query table contents for primary algorithm. address (P+5)h contains less significant byte. bit 0Chip Erase supported(1 = Yes, 0 = No) bit 1Suspend Erase supported(1 = Yes, 0 = No) bit 2Suspend Program supported(1 = Yes, 0 = No) bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4Queued Erase supported(1 = Yes, 0 = No) bit 5Instant individual block locking supported(1 = Yes, 0 = No) bit 6Protection bits supported(1 = Yes, 0 = No) bit 7Page mode read supported(1 = Yes, 0 = No) bit 8Synchronous read supported(1 = Yes, 0 = No) bit 31 to 9Reserved; undefined bits are ‘0’ No Yes Yes No No Yes Yes No No Supported functions after Suspend Read Array, Read Status Register and CFI query are always supported during erase or program operation bit 0Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1Reserved; undefined bits are ‘0’ Yes (P+9)h = 3Eh 0001h (P+A)h = 3Fh 0003h (P+B)h = 40h 0000h Description Value ‘P’ Primary algorithm extended query table unique ASCII string ‘PRI’ ‘R’ ‘I’ Block Lock status Defines which bits in the block Status Register section of the query are implemented. Address (P+A)h contains less significant byte bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 1Block Lock Status Register Lock-down bit active (1 = Yes, 0 = No) bit 15 to 2Reserved for future use; undefined bits are ‘0’ VDD logic supply optimum Program/Erase voltage (highest performance) bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV (P+C)h = 41h 0030h (P+D)h = 42h VPP supply optimum Program/Erase voltage 00C0h bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV (P+E)h = 43h 0001h Number of protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Yes Yes 3V 12 V 01 57/72 Common Flash interface (CFI) Table 29. M28W640HCT, M28W640HCB Primary algorithm-specific extended query table (continued) Offset P = 35h(1) Data (P+F)h = 44h 0080h (P+10)h = 45h 0000h (P+11)h = 46h 0003h (P+12)h = 47h 0004h (P+13)h = 48h Description 80h Protection field 1: protection description This field describes user-available one-time-programmable 00h (OTP) protection register bytes. Some are pre-programmed with 8 byte device unique serial numbers. Others are user programmable. bits 0–15 point to the Protection Register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and userprogrammable. 16 byte bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15Lock/bytes JEDEC-plane physical high address bit 16 to 23 "n" such that 2n = factory pre-programmed bytes bit 24 to 31 "n" such that 2n = user programmable bytes Reserved 1. See Table 26, offset 15 for P pointer definition. Table 30. Security code area Offset Data 80h 00XX 81h XXXX 82h XXXX 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 89h XXXX 8Ah XXXX 8Bh XXXX 8Ch XXXX Description Protection Register Lock 64 bits: unique device number 128 bits: user programmable OTP 58/72 Value M28W640HCT, M28W640HCB Appendix C Flowcharts and pseudocodes Flowcharts and pseudocodes Figure 15. Program flowchart and pseudocode Start program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ Write 40h or 10h writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ Write Address & Data do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1, 2) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.b4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI03538b 1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations. 59/72 Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 16. Double Word Program flowchart and pseudocode Start Write 30h double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1, 2) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.b4==1) /*program error */ error_handler ( ) ; YES b4 = 0 YES b1 = 0 NO Program to Protected Block Error (1, 2) if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI03539b 1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and address 2 must be consecutive addresses differing only for bit A0. 60/72 M28W640HCT, M28W640HCB Flowcharts and pseudocodes Figure 17. Quadruple Word Program flowchart and pseudocode Start quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (any_address, 0x56) ; Write 56h Write Address 1 & Data 1 (3) writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ Write Address 2 & Data 2 (3) writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ Write Address 3 & Data 3 (3) writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */ Write Address 4 & Data 4 (3) /*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1, 2) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.b4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06233 1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to address 4 must be consecutive addresses differing only for bits A0 and A1. 61/72 Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 18. Program Suspend & Resume flowchart and pseudocode Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; Write B0h writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b2 = 1 NO Program Complete YES Write FFh } Read data from another address Write D0h if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } Write FFh } Program Continues Read Data AI03540b 62/72 M28W640HCT, M28W640HCB Flowcharts and pseudocodes Figure 19. Erase flowchart and pseudocode Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; Write 20h writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ Write Block Address & D0h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1) YES Command Sequence Error (1) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; YES b4, b5 = 1 if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; NO b5 = 0 NO Erase Error (1) if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; YES b1 = 0 NO Erase to Protected Block Error (1) if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI03541b 1. If an error is found, the Status Register must be cleared before further program/erase operations. 63/72 Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 20. Erase Suspend & Resume flowchart and pseudocode Start erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; Write B0h writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b6 = 1 NO Erase Complete if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ; YES read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock } else Write D0h Write FFh Erase Continues Read Data { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } } AI03542b 64/72 M28W640HCT, M28W640HCB Flowcharts and pseudocodes Figure 21. Locking operations flowchart and pseudocode Start locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ Write 60h if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; Write 01h, D0h or 2Fh writeToFlash (any_address, 0x90) ; Write 90h Read Block Lock States Locking change confirmed? if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/ NO YES writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ Write FFh } End AI04364 65/72 Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 22. Protection Register Program flowchart and pseudocode Start protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ; Write C0h writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ Write Address & Data do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1, 2) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.b4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI04381 1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations. 66/72 M28W640HCT, M28W640HCB Appendix D Table 31. Command interface and Program/Erase controller state Command interface and Program/Erase controller state Write state machine current/next(1) . Command input (and next state) Current state SR Data when bit Read 7 Read Array ‘1’ Read Array (FFh) Program Setup (10/40h) Erase Setup (20h) Erase Confirm (D0h) Prog/Ers Suspend (B0h) Prog/Ers Resume (D0h) Read Clear Status Status (70h) (50h) Array Read Ers. Prog.Setup Array Setup Read Array Read Sts. Read Array Read Status ‘1’ Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Elect.Sg. ‘1’ Electronic signature Read Array Program Setup Erase Setup Read Array Read Status Read Array Read CFI Query ‘1’ CFI Read Array Program Setup Erase Setup Read Array Read Status Read Array Lock Lock Cmd Lock Lock Command (complete) Error (complete) Error Lock Setup ‘1’ Status Lock Cmd Error ‘1’ Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Lock (complete) ‘1’ Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Prot. Prog. Setup ‘1’ Status Protection Register Program Prot. Prog. (continue) ‘0’ Status Protection Register Program continue Prot. Prog. (complete) ‘1’ Status Read Status Read Array Prog. Setup ‘1’ Status Program (continue) ‘0’ Status Prog. Sus Status ‘1’ Prog. Sus ‘1’ Read Array Prog. Sus Read Elect.Sg. ‘1’ Lock Command Error Read Array Program Setup Erase Setup Read Array Program Program (continue) Prog. Sus Read Sts Program (continue) Status Prog. Prog. Sus Sus Program Suspend to Program Program Read Read Read Array (continue) (continue) Array Array Prog. Sus Read Sts Prog. Sus Read Array Array Prog. Prog. Sus Sus Program Suspend to Program Program Read Read Read Array (continue) (continue) Array Array Prog. Sus Read Sts Prog. Sus Read Array Electronic signature Prog. Prog. Sus Sus Program Suspend to Program Program Read Read Read Array (continue) (continue) Array Array Prog. Sus Read Sts Prog. Sus Read Array 67/72 Command interface and Program/Erase controller state Table 31. M28W640HCT, M28W640HCB Write state machine current/next(1) (continued) Command input (and next state) Current state SR Data when bit Read 7 Prog. Sus Read CFI ‘1’ CFI Program (complete) ‘1’ Status Erase Setup ‘1’ Status Erase Cmd.Error ‘1’ Status Erase (continue) ‘0’ Status Erase Sus Read Sts ‘1’ Erase Sus ‘1’ Read Array Erase Sus Read Elect.Sg. ‘1’ Read Array (FFh) Program Setup (10/40h) Erase Setup (20h) Erase Confirm (D0h) Prog/Ers Suspend (B0h) Prog/Ers Resume (D0h) Read Clear Status Status (70h) (50h) Prog. Prog. Sus Sus Program Suspend to Program Program Read Read Read Array (continue) (continue) Array Array Prog. Sus Read Sts Prog. Sus Read Array Read Array Read Status Read Array Program Setup Erase Setup Erase Command Error Read Array Program Setup Erase Setup Erase (continue) Read Array Erase Erase Erase Erase Command (continue) CmdError (continue) Error Read Status Read Array Erase Sus Read Sts Erase (continue) Status Erase Sus Read Array Program Setup Erase Sus Read Array Erase Sus Erase Erase Read (continue) (continue) Array Erase Sus Read Sts Erase Sus Read Array Array Erase Sus Read Array Program Setup Erase Sus Read Array Erase Sus Erase Erase Read (continue) (continue) Array Erase Sus Read Sts Erase Sus Read Array Electronic Signature Erase Sus Read Array Program Setup Erase Sus Read Array Erase Sus Erase Erase Read (continue) (continue) Array Erase Sus Read Sts Erase Sus Read Array Program Setup Erase Sus Read Array Erase Sus Erase Erase Read (continue) (continue) Array Erase Sus Read Sts Erase Sus Read Array Program Setup Erase Setup Read Array Read Status Read Array Erase Sus Read CFI ‘1’ CFI Erase Sus Read Array Erase (complete) ‘1’ Status Read Array 1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend. 68/72 Read Array M28W640HCT, M28W640HCB Table 32. Command interface and Program/Erase controller state Write state machine current/next(1) . Command input (and next state) Current state Read Elect.Sg. Read CFI Query (90h) (98h) Read Array Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup Read Array Read Status Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup Read Array Read Elect.Sg. Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup Read Array Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup Read Array Lock Setup Lock Setup (60h) Prot. Prog. Setup (C0h) Lock Confirm (01h) Lock Command Error Lock Down Confirm (2Fh) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup Read Array Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup Read Array Prot. Prog. Setup Protection Register Program Prot. Prog. (continue) Protection Register Program (continue) Read Elect.Sg. Read CFI Query (D0h) Lock (complete) Lock Cmd Error Prot. Prog. (complete) Unlock Confirm Lock Setup Prot. Prog. Setup Prog. Setup Program Program (continue) Program (continue) Read Array Prog. Suspend Read Status Prog. Suspend Read Elect.Sg. Prog. Suspend Read CFI Query Program Suspend Read Array Program (continue) Prog. Suspend Read Array Prog. Suspend Read Elect.Sg. Prog. Suspend Read CFI Query Program Suspend Read Array Program (continue) Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Prog. Suspend Read CFI Query Program Suspend Read Array Program (continue) Prog. Suspend Read CFI Prog. Suspend Read Elect.Sg. Prog. Suspend Read CFI Query Program Suspend Read Array Program (continue) Program (complete) Read Elect.Sg. Read CFIQuery Lock Setup Prot. Prog. Setup Read Array 69/72 Command interface and Program/Erase controller state Table 32. M28W640HCT, M28W640HCB Write state machine current/next(1) (continued) Command input (and next state) Current state Read Elect.Sg. Read CFI Query (90h) (98h) Erase Setup Erase Cmd.Error Lock Setup (60h) Prot. Prog. Setup (C0h) Lock Confirm (01h) Lock Down Confirm (2Fh) Read CFI Query Erase (continue) Lock Setup Prot. Prog. Setup (D0h) Erase (continue) Erase Command Error Read Elect.Sg. Unlock Confirm Read Array Erase (continue) Erase Suspend Read Ststus Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query Lock Setup Erase Suspend Read Array Erase (continue) Erase Suspend Read Array Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query Lock Setup Erase Suspend Read Array Erase (continue) Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query Lock Setup Erase Suspend Read Array Erase (continue) Erase Suspend Read CFI Query Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query Lock Setup Erase Suspend Read Array Erase (continue) Erase (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup 1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection. 70/72 Read Array M28W640HCT, M28W640HCB 11 Revision history Revision history Table 33. Document revision history Date Version Changes 29-Jan-2008 1 Initial release. 20-Mar-2008 2 Applied Numonyx branding. 71/72 M28W640HCT, M28W640HCB Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 72/72