STMICROELECTRONICS M29DW640D70N6E

M29DW640D
64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
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SUPPLY VOLTAGE
– VCC = 2.7V to 3.6V for Program, Erase
and Read
– VPP =12V for Fast Program (optional)
ASYNCHRONOUS PAGE READ MODE
– Page Width 4 Words
– Page Access 25, 30ns
– Random Access 70, 90ns
PROGRAMMING TIME
– 10µs per Byte/Word typical
– 4 Words / 8 Bytes at-a-time Program
MEMORY BLOCKS
– Quadruple Bank Memory Array:
8Mbit+24Mbit+24Mbit+8Mbit
– Parameter Blocks (at both Top and
Bottom)
DUAL OPERATIONS
– While Program or Erase in a group of
banks (from 1 to 3), Read in any of the
other banks
PROGRAM/ ERASE SUSPEND and
RESUME MODES
– Read from any Block during Program
Suspend
– Read and Program another Block during
Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
VPP/WP PIN for FAST PROGRAM and
WRITE PROTECT
TEMPORARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFACE
– 64 bit Security Code
EXTENDED MEMORY BLOCK
– Extra block used as security block or to
store additional information
December 2004
Figure 1. Packages
TSOP48 (N)
12 x 20mm
FBGA
TFBGA63 (ZA)
7 x 11mm
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LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 227Eh + 2202h + 2201h
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.
Table 1.
Figure 3.
Figure 4.
Table 2.
Figure 5.
Figure 6.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Double Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Octuple Byte Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Enter Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 22
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Figure 11.Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled . . . . . . . . . . . . 34
Figure 16.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 34
Table 18. Toggle and Alternative Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . . 36
Table 20. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 36
Figure 20.TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline. . . . . . . . . . . 37
Table 21. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 37
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 25. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 26. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 28. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Figure 23.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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SUMMARY DESCRIPTION
The M29DW640D is a 64 Mbit (8Mb x8 or 4Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode.
The device features an asymmetrical block architecture, with 16 parameter and 126 main blocks,
divided into four Banks, A, B, C and D, providing
multiple Bank operations. While programming or
erasing is underway in one group of banks (from 1
to 3), reading can be conducted in any of the other
banks. The bank architecture is summarized in Table 2. Eight of the Parameter Blocks are at the top
of the memory address space, and eight are at the
bottom.
The M29DW640D has one extra 256 Byte block
(Extended Block) that can be accessed using a
dedicated command. The Extended Block can be
protected and so is useful for storing security information. However the protection is irreversible,
once protected the protection cannot be undone.
Each block can be erased independently, so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase commands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identified. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12x20mm) and
TFBGA63 (7x11mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
VCC VPP/WP
22
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization Select
VCC
Supply Voltage
VPP/WP
VPP/Write Protect
VSS
Ground
NC
Not Connected Internally
15
A0-A21
DQ0-DQ14
DQ15A–1
W
E
A0-A21
M29DW640D
G
RB
RP
BYTE
VSS
6/56
AI06877b
M29DW640D
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
A21
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
37
12
M29DW640D
13
36
24
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI06878b
7/56
M29DW640D
Figure 4. TFBGA Connections (Top view through package)
1
2
A
NC(1)
NC(1)
B
NC(1)
3
4
5
6
7
8
NC(1)
NC(1)
NC(1)
NC(1)
C
A3
A7
RB
W
A9
A13
D
A4
A17
VPP/WP
RP
A8
A12
E
A2
A6
A18
A21
A10
A14
F
A1
A5
A20
A19
A11
A15
G
A0
DQ0
DQ2
DQ5
DQ7
A16
H
E
DQ8
DQ10
DQ12
DQ14
BYTE
J
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
K
VSS
DQ1
DQ3
DQ4
DQ6
VSS
L
NC(1)
NC(1)
NC(1)
NC(1)
M
NC(1)
NC(1)
NC(1)
NC(1)
AI06879
Note: 1. Balls are shorted together via the substrate but not connected to the die.
8/56
M29DW640D
Table 2. Bank Architecture
Parameter Blocks
Bank
Bank Size
Main Blocks
No. of
Blocks
Block Size
No. of Blocks
Block Size
A
8 Mbit
8
8KByte/ 4 KWord
15
64KByte/ 32 KWord
B
24 Mbit
—
—
48
64KByte/ 32 KWord
C
24 Mbit
—
—
48
64KByte/ 32 KWord
D
8 Mbit
8
8KByte/ 4 KWord
15
64KByte/ 32 KWord
Figure 5. Block Addresses (x8)
(x8)
Address lines A21-A0, DQ15A-1
000000h
001FFFh
400000h
8 KByte or
4 KWord
40FFFFh
Total of 8
Parameter
Blocks
00E000h
Bank A
00FFFFh
010000h
01FFFFh
64 KByte or
32 KWord
Total of 48
Main Blocks
Bank C
6F0000h
8 KByte or
4 KWord
6FFFFFh
700000h
64 KByte or
32 KWord
70FFFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 15
Main Blocks
0F0000h
0FFFFFh
100000h
10FFFFh
Total of 15
Main Blocks
7E0000h
64 KByte or
32 KWord
Bank D
64 KByte or
32 KWord
7EFFFFh
7F0000h
7F1FFFh
64 KByte or
32 KWord
8 KByte or
4 KWord
Total of 48
Main Blocks
Bank B
3F0000h
3FFFFFh
64 KByte or
32 KWord
Total of 8
Parameter
Blocks
7FE000h
7FFFFFh
8 KByte or
4 KWord
AI06880
Note: Also see Appendix A, Table 23 for a full listing of the Block Addresses.
9/56
M29DW640D
Figure 6. Block Addresses (x16)
(x16)
Address lines A21-A0
000000h
000FFFh
200000h
8 KByte or
4 KWord
207FFFh
Total of 8
Parameter
Blocks
007000h
Bank A
007FFFh
008000h
00FFFFh
64 KByte or
32 KWord
Total of 48
Main Blocks
Bank C
378000h
8 KByte or
4 KWord
37FFFFh
380000h
64 KByte or
32 KWord
387FFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 15
Main Blocks
Total of 15
Main Blocks
078000h
07FFFFh
080000h
087FFFh
3F0000h
64 KByte or
32 KWord
Bank D
64 KByte or
32 KWord
3F7FFFh
3F8000h
3F8FFFh
64 KByte or
32 KWord
8 KByte or
4 KWord
Total of 8
Parameter
Blocks
Total of 48
Main Blocks
Bank B
1F8000h
1FFFFFh
64 KByte or
32 KWord
3FF000h
3FFFFFh
8 KByte or
4 KWord
AI05555
Note: Also see Appendix A, Table 23 for a full listing of the Block Addresses.
10/56
M29DW640D
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state machine.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
VPP/Write Protect (VPP/WP). The
VPP/Write
Protect pin provides two functions. The VPP function allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware method of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the address space).
When VPP/Write Protect is Low, VIL, the memory
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while VPP/Write Protect is Low, even when RP is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode.
When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP, see Figure 18.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating
or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, IPP.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if VPP/WP is at VIL, then the four outermost boot blocks will remain protected even if RP
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 19 and Figure 17., Reset/
Block Temporary Unprotect AC Waveforms.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
11/56
M29DW640D
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 19 and Figure
17., Reset/Block Temporary Unprotect AC Waveforms.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 mode.
12/56
proVCC Supply Voltage (2.7V to 3.6V). VCC
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, ICC3.
VSS Ground. VSS is the reference for all voltage
measurements. The device features two VSS pins
both of which must be connected to the system
ground.
M29DW640D
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read (Random and
Page modes), Bus Write, Output Disable, Standby
and Automatic Standby.
Using the multiple bank architecture of the
M29DW640D, while programming or erasing is
underway in one group of banks (from 1 to 3),
reading can be conducted in any of the other
banks. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable, Write Enable, and Reset pins are ignored by
the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. To speed up the read operation
the memory array can be read in Page mode
where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.
A valid Bus Read operation involves setting the
desired address on the Address Inputs, applying a
Low signal, VIL, to Chip Enable and Output Enable
and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure
11., Random Read AC Waveforms, Figure
12., Page Read AC Waveforms, and Table
15., Read AC Characteristics, for details of when
the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 16 and 17, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 14., DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Protect and Chip Unprotect. Groups of
blocks can be protected against accidental Program or Erase. The Protection Groups are shown
in Appendix A, Table 23., Block Addresses The
whole chip can be unprotected to allow the data inside the blocks to be changed.
The VPP/Write Protect pin can be used to protect
the four outermost boot blocks. When VPP/Write
Protect is at VIL the four outermost boot blocks
are protected and remain protected regardless of
the Block Protection Status or the Reset/Block
Temporary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in Appendix D.
13/56
M29DW640D
Table 3. Bus Operations, BYTE = VIL
Address Inputs
Operation
E
G
W
A21A12
A3
A2
A1
A0
Data Inputs/Outputs
others,
DQ15A-1
DQ14
-DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
(Cycle 1)
VIL
VIL
VIH
Read Device Code
(Cycle 2)
VIL
VIL
Read Device Code
(Cycle 3)
VIL
Extended Block
Indicator Bit
(DQ7)
Block Protection
Verification
Output Disable
VIL
VIL
VIL
VIL
Hi-Z
20h
VIL
VIL
VIL
VIH
Hi-Z
7Eh
VIH
VIH
VIH
VIH
VIL
Hi-Z
02h
VIL
VIH
VIH
VIH
VIH
VIH
Hi-Z
01h
VIL
VIL
VIH
Bank
A
VIL
VIL
VIH
VIH
Hi-Z
80h (factory locked)
00h (not locked)
VIL
VIL
VIH
Block
Addrs
VIL
VIL
VIH
VIL
Hi-Z
01h (protected)
00h (unprotected)
Bank
Addrs
A6 = VIL
A9 = VID,
others =X
Note: X = VIL or VIH.
Table 4. Bus Operations, BYTE = VIH
Address Inputs
Operation
E
G
W
A21A12
A3
A2
A1
A0
Data Inputs/Outputs
others
DQ15A-1, DQ14-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Data Input
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
(Cycle 1)
VIL
VIL
VIH
Read Device Code
(Cycle 2)
VIL
VIL
Read Device Code
(Cycle 3)
VIL
Extended Block
Indicator Bit
(DQ7)
Block Protection
Verification
Output Disable
Note: X = VIL or VIH.
14/56
VIL
VIL
VIL
VIL
0020h
VIL
VIL
VIL
VIH
227Eh
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIH
Bank
A
VIL
VIL
VIH
VIH
0080h (factory locked)
0000h (not locked)
VIL
VIL
VIH
Block
Addrs
VIL
VIL
VIH
VIL
0001h (protected)
0000h (unprotected)
Bank
Addrs
A6 = VIL
A9 = VID,
others =X
2202h
2201h
M29DW640D
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command
The Read/Reset command returns the memory to
its Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset
command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the timeout of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
Auto Select Command
The Auto Select command is used to read the
Manufacturer Code and Device Code, the Block
Protection Status and the Extended Block Indicator. It can be addressed to either Bank. Three consecutive Bus Write operations are required to
issue the Auto Select command. The final Write
cycle must be addressed to one of the Banks.
Once the Auto Select command is issued Bus
Read operations to the Bank where the command
was issued output the Auto Select data. Bus Read
operations to the other Bank will output the contents of the memory array. The memory remains in
Auto Select mode until a Read/Reset or CFI Query
command is issued. This command must be issued addressing the same Bank, as was given
when entering Auto Select Mode.
In Auto Select mode the Manufacturer Code can
be read using a read operation, A6 and A3 to A0
each held at VIL, and A21-A19 set to the Bank Address. The other address bits may be set to either
VIL or VIH.
The Device Codes can be read using a read operation, A6 held at VIL, A3 to A0 each held at the levels given in Tables 3 and 4, and A21-A19 set to the
Bank Address. The other address bits may be set
to either VIL or VIH.
The Block Protection Status of each block can be
read using a read operation, A6 A3 A2 A0 each
held at VIL, A1 held at VIH, and A21-A19 set to the
Bank Address, and A18-A12 specifying the address of the block inside the Bank. The other address bits may be set to either VIL or VIH. If the
addressed block is protected then 01h is output on
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is
output.
The Extended Block Status of the Extended Block
can be read using a read operation, A6, A3 and
A2, at VIL, A0 and A1, at VIH, and A21-A19 set to
Bank Address A. The other bits may be set to either VIL or VIH (Don't Care). If the Extended Block
is "Factory Locked" then 80h is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output.
Read CFI Query Command
The Read CFI Query Command is used to put the
addressed bank in Read CFI Query mode. Once in
Read CFI Query mode Bus Read operations to the
same bank will output data from the Common
Flash Interface (CFI) Memory Area. If the read operations are to a different bank from the one specified in the command then the read operations will
output the contents of the memory array and not
the CFI data.
One Bus Write cycle is required to issue the Read
CFI Query Command. Care must be taken to issue
the command to one of the banks (A21-A19) along
with the address shown in Tables 3 and 4 (A-1,
A0-A10). Once the command is issued subsequent Bus Read operations in the same bank
(A21-A19) to the addresses shown in Appendix B
(A7-A0), will read from the Common Flash Interface Memory Area.
This command is valid only when the device is in
the Read Array or Autoselected mode. To enter
Read CFI query mode from Auto Select mode, the
Read CFI Query command must be issued to the
same bank address as the Auto Select command,
otherwise the device will not enter Read CFI Query mode.
The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselected mode.
See Appendix B, Tables 24, 25, 26, 27, 28 and 29
for details on the information contained in the
Common Flash Interface (CFI) memory area.
15/56
M29DW640D
Program Command
The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write operations, the final Write operation latches the address and data in the internal state machine and
starts the Program/Erase Controller.
Programming can be suspended and then resumed by issuing a Program Suspend command
and a Program Resume command, respectively
(see Program Suspend Command and Program
Resume Command paragraphs).
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
After programming has started, Bus Read operations in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of the
memory array. See the section on the Status Register for more details. Typical program times are
given in Table 7.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Fast Program Commands
There are five Fast Program commands available
to improve the programming throughput, by writing
several adjacent Words or Bytes in parallel.
Double Word Program Command. This
is
used to write two adjacent Words in x16 mode, in
parallel. The addresses of the two Words must differ only in A0.
Three bus write cycles are necessary to issue the
command.
■
The first bus cycle sets up the command.
■
The second bus cycle latches the Address and
the Data of the first Word to be written.
■
The third bus cycle latches the Address and
the Data of the second Word to be written and
starts the Program/Erase Controller.
Quadruple Word Program Command. This is
used to write a page of four adjacent Words, in x16
mode, in parallel. The addresses of the four Words
must differ only in A1 and A0.
16/56
Five bus write cycles are necessary to issue the
command.
■
The first bus cycle sets up the command.
■
The second bus cycle latches the Address and
the Data of the first Word to be written.
■
The third bus cycle latches the Address and
the Data of the second Word to be written.
■
The fourth bus cycle latches the Address and
the Data of the third Word to be written.
■
The fifth bus cycle latches the Address and the
Data of the fourth Word to be written and starts
the Program/Erase Controller.
Double Byte Program Command. This is used
to write two adjacent Bytes in x8 mode, in parallel.
The addresses of the two Bytes must differ only in
DQ15A-1.
Three bus write cycles are necessary to issue the
command.
■
The first bus cycle sets up the command.
■
The second bus cycle latches the Address and
the Data of the first Byte to be written.
■
The third bus cycle latches the Address and
the Data of the second Byte to be written and
starts the Program/Erase Controller.
Quadruple Byte Program Command. This
is
used to write four adjacent Bytes in x8 mode, in
parallel. The addresses of the four Bytes must differ only in A0, DQ15A-1.
Five bus write cycles are necessary to issue the
command.
■
The first bus cycle sets up the command.
■
The second bus cycle latches the Address and
the Data of the first Byte to be written.
■
The third bus cycle latches the Address and
the Data of the second Byte to be written.
■
The fourth bus cycle latches the Address and
the Data of the third Byte to be written.
■
The fifth bus cycle latches the Address and the
Data of the fourth Byte to be written and starts
the Program/Erase Controller.
Octuple Byte Program Command. This is used
to write eight adjacent Bytes, in x8 mode, in parallel. The addresses of the eight Bytes must differ
only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the
command.
■
The first bus cycle sets up the command.
■
The second bus cycle latches the Address and
the Data of the first Byte to be written.
■
The third bus cycle latches the Address and
the Data of the second Byte to be written.
■
The fourth bus cycle latches the Address and
the Data of the third Byte to be written.
M29DW640D
The fifth bus cycle latches the Address and the
Data of the fourth Byte to be written.
■
The sixth bus cycle latches the Address and
the Data of the fifth Byte to be written.
■
The seventh bus cycle latches the Address
and the Data of the sixth Byte to be written.
■
The eighth bus cycle latches the Address and
the Data of the seventh Byte to be written.
■
The ninth bus cycle latches the Address and
the Data of the eighth Byte to be written and
starts the Program/Erase Controller.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Fast programming should not be attempted when
VPP is not at VPPH.
After programming has started, Bus Read operations in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of the
memory array.
Programming can be suspended and then resumed by issuing a Program Suspend command
and a Program Resume command, respectively.
(See Program Suspend Command and Program
Resume Command paragraphs.)
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table
7., Program, Erase Times and Program, Erase
Endurance Cycles.
Unlock Bypass Command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long, considerable time saving can be
made by using these commands. Three Bus Write
operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. The
Unlock Bypass Program command can then be issued to program addresses within the bank, or the
Unlock Bypass Reset command can be issued to
■
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin
the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately.
Unlock Bypass Program Command
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the address and data in the internal state machine and
starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. The
operation cannot be aborted, a Bus Read operation to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Chip Erase Command
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start
the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend command. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 7. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
17/56
M29DW640D
Block Erase Command
The Block Erase command can be used to erase
a list of one or more blocks in one or more Banks.
It sets all of the bits in the unprotected selected
blocks to ’1’. All previous data in the selected
blocks is lost.
Six Bus Write operations are required to select the
first block in the list. Each additional block in the
list can be selected by repeating the sixth Bus
Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller after a time-out period of
50µs after the last Bus Write operation. Once the
Program/Erase Controller starts it is not possible
to select any more blocks. Each additional block
must therefore be selected within 50µs of the last
block. The 50µs timer restarts when an additional
block is selected. After the sixth Bus Write operation a Bus Read operation within the same Bank
will output the Status Register. See the Status
Register section for details on how to identify if the
Program/Erase Controller has started the Block
Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command and the Read/Reset command which is
only accepted during the 50µs time-out period.
Typical block erase times are given in Table 7.
After the Erase operation has started all Bus Read
operations to the Banks being erased will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Banks where the command was issued will continue to output the Status
Register. A Read/Reset command must be issued
to reset the error condition and return to Read
mode.
Erase Suspend Command
The Erase Suspend command may be used to
temporarily suspend a Block or multiple Block
Erase operation. One Bus Write operation specifying the Bank Address of one of the Blocks being
erased is required to issue the command. Issuing
the Erase Suspend command returns the whole
device to Read mode.
18/56
The Program/Erase Controller will suspend within
the Erase Suspend Latency time (see Table 7 for
value) of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Reading from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be accepted.
During Erase Suspend a Bus Read operation to
the Extended Block will output the Extended Block
data. Once in the Extended Block mode, the Exit
Extended Block command must be issued before
the erase operation can be resumed.
Erase Resume Command
The Erase Resume command is used to restart
the Program/Erase Controller after an Erase Suspend. The command must include the Bank Address of the Erase-Suspended Bank, otherwise
the Program/Erase Controller is not restarted.
The device must be in Read Array mode before
the Resume command will be accepted. An Erase
can be suspended and resumed more than once.
Program Suspend Command
The Program Suspend command allows the system to interrupt a program operation so that data
can be read from any block. When the Program
Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend Latency time
(see Table 7 for value) and updates the Status
Register bits. The Bank Addresses of the Block
being programmed must be specified in the Program Suspend command.
After the program operation has been suspended,
the system can read array data from any address.
M29DW640D
However, data read from Program-Suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an erase is
suspended. In this case, data may be read from
any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the Extended
Block area (One-time Program area), the user
must use the proper command sequences to enter
and exit this region.
The system may also issue the Auto Select command sequence when the device is in the Program
Suspend mode. The system can read as many
Auto Select codes as required. When the device
exits the Auto Select mode, the device reverts to
the Program Suspend mode, and is ready for another valid operation. See Auto Select command
sequence for more information.
Program Resume Command
After the Program Resume command is issued,
the device reverts to programming. The controller
can determine the status of the program operation
using the DQ7 or DQ6 status bits, just as in the
standard program operation. See Write Operation
Status for more information.
The system must write the Program Resume command, specifying the Bank addresses of the Program-Suspended Block, to exit the Program
Suspend mode and to continue the programming
operation.
Further issuing of the Resume command is ignored. Another Program Suspend command can
be written after the device has resumed programming.
Enter Extended Block Command
The M29DW640D has one extra 256-Byte block
(Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus
write cycles are required to issue the Extended
Block command. Once the command has been issued the device enters Extended Block mode
where all Bus Read or Program operations to the
000000h-00007Fh (Word) or 000000h-0000FFh
(Byte) addresses access the Extended Block. The
Extended Block cannot be erased, and can be
treated as one-time programmable (OTP) memory. In Extended Block mode only array cell locations (Bank A) with the same addresses as the
Extended Block (000000h-00007Fh (Word) or
000000h-0000FFh (Byte)) are not accessible. In
Extended Block mode dual operations are allowed
and the Extended Block physically belongs to
Bank A.
When in Extended Block mode, Erase, Chip
Erase, Erase Suspend and Erase resume commands are not allowed.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected, however
once protected the protection cannot be undone.
Exit Extended Block Command
The Exit Extended Block command is used to exit
from the Extended Block mode and return the device to Read mode. Four Bus Write operations are
required to issue the command.
Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against accidental Program or Erase. The Protection Groups
are shown in Appendix A, Table 23., Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix D.
19/56
M29DW640D
Command
Length
Table 5. Commands, 16-bit mode, BYTE = VIH
Bus Write Operations
1st
2nd
Add
Data
1
X
F0
3
555
Auto Select
3
Program
3rd
4th
Add
Data
Add
Data
AA
2AA
55
X
F0
555
AA
2AA
55
(BKA)
555
90
4
555
AA
2AA
55
555
A0
Double Word Program
3
555
50
PA0
PD0
PA1
PD1
Quadruple Word Program
3
555
56
PA0
PD0
PA1
PD1
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
Erase/Program Suspend
1
BKA
B0
Erase/Program Resume
1
BKA
30
Read CFI Query(2)
1
(BKA)
55
98
Enter Extended Block
3
555
AA
2AA
Exit Extended Block
4
555
AA
2AA
5th
Add
Data
PA
PD
PA2
80
555
80
55
555
88
55
555
90
6th
Add
Data
Add
Data
PD2
PA3
PD3
555
AA
2AA
55
555
10
555
AA
2AA
55
BA
30
X
00
Read/Reset
Note: 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table
are in hexadecimal.
2. Normally the Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands and A11-A21 are Don’t Care, however for the Read CFI command A21-A14 must specify a bank address, and the subsequent read operations must be addressed
to the same bank.
20/56
M29DW640D
Command
Length
Table 6. Commands, 8-bit mode, BYTE = VIL
1
Bus Write Operations
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data
X
F0
Read/Reset
3 AAA
AA 555 55
Auto Select
3 AAA
AA 555 55
Program
4 AAA
AA 555 55
X
F0
(BKA)
90
AAA
AAA
A0
PA
PD
Double Byte
3 AAA
Program
50 PA0 PD1 PA1 PD1
Quadruple
Byte
Program
56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
5 AAA
Octuple Byte
5 AAA
Program
8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7
Unlock
Bypass
3 AAA
AA 555 55
Unlock
Bypass
Program
2
X
A0
PA
PD
Unlock
Bypass
Reset
2
X
90
X
00
Chip Erase
6 AAA
Block Erase
AAA
20
AA 555 55
AAA
80 AAA AA
555
55 AAA 10
6
AAA
+
AA 555 55
AAA
80 AAA AA
555
55
Erase/
Program
Suspend
1 BKA
B0
Erase/
Program
Resume
1 BKA
30
Read CFI
Query(2)
1
Enter
Extended
Block
3 AAA
AA 555 55
AAA
88
Exit
Extended
Block
4 AAA
AA 555 55
AAA
90
BA
30
(BKA)
98
AA
X
00
Note: 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
2. Normally the Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands and A11-A21 are Don’t Care, however for the Read CFI command A21-A14 must specify a bank address, and the subsequent read operations must be addressed
to the same bank.
21/56
M29DW640D
Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Typ (1, 2)
Max(2)
Unit
Chip Erase
80
400(3)
s
Block Erase (64 KBytes)
0.8
6(4)
s
50(4)
µs
Parameter
Min
Erase Suspend Latency Time
Byte Program (1, 2, 4 or 8 at-a-time)
10
200(3)
µs
Word Program (1, 2 or 4 at-a-time)
10
200(3)
µs
Chip Program (Byte by Byte)
80
400(3)
s
Chip Program (Word by Word)
40
200(3)
s
Chip Program (Quadruple Byte or Double Word)
20
100(3)
s
Chip Program (Octuple Byte or Quadruple Word)
10
50(3)
s
4
µs
Program Suspend Latency Time
Program/Erase Cycles (per Block)
Data Retention
Note: 1.
2.
3.
4.
22/56
100,000
cycles
20
years
Typical values measured at room temperature and nominal voltages.
Sampled, but not 100% tested.
Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
Maximum value measured at worst case conditions for both temperature and VCC.
M29DW640D
STATUS REGISTER
The M29DW640D has one Status Register. The
Status Register provides information on the current or previous Program or Erase operations executed in each bank. The various bits convey
information and errors on the operation. Bus Read
operations from any address within the Bank, always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 8., Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 7., Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 8., Toggle Flowchart, gives an example of
how to use the Data Toggle Bit. Figures 15 and 16
describe Toggle Bit timing waveform.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased correctly.
Figures 15 and 16 describe Alternative Toggle Bit
timing waveform.
23/56
M29DW640D
Table 8. Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Bank Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Bank Address
DQ7
Toggle
0
–
–
0
Program Error
Bank Address
DQ7
Toggle
1
–
–
Hi-Z
Chip Erase
Any Address
0
Toggle
0
1
Toggle
Hi-Z
Block Erase before
timeout
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No Toggle
0
Erasing Block
0
Toggle
0
1
Toggle
Hi-Z
Non-Erasing Block
0
Toggle
0
1
No Toggle
0
Erasing Block
1
No Toggle
0
–
Toggle
Hi-Z
Block Erase
Erase Suspend
Non-Erasing Block
Data read as normal
Hi-Z
Good Block Address
0
Toggle
1
1
No Toggle
0
Faulty Block Address
0
Toggle
1
1
Toggle
0
Erase Error
Note: 1. Unspecified data bits should be ignored.
2. Figures 15 and 16 describe Toggle and Alternative Toggle Bits timing waveforms.
Figure 7. Data Polling Flowchart
Figure 8. Toggle Flowchart
START
READ DQ6
ADDRESS = BA
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
READ
DQ5 & DQ6
ADDRESS = BA
YES
DQ6
=
TOGGLE
NO
NO
YES
NO
NO
DQ5 = 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
FAIL
DQ5
=1
YES
READ DQ6
TWICE
ADDRESS = BA
YES
DQ6
=
TOGGLE
PASS
YES
FAIL
AI07760
NO
PASS
AI08929b
Note: BA = Address of Bank being Programmed or Erased.
24/56
M29DW640D
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the
M29DW640D gives greater flexibility for software
developers to split the code and data spaces within the memory array. The Dual Operations feature
simplifies the software management of the device
by allowing code to be executed from one bank
while another bank is being programmed or
erased.
The Dual Operations feature means that while programming or erasing in one bank, read operations
are possible in another bank with zero latency.
Only one bank at a time is allowed to be in program or erase mode. However, certain commands
can cross bank boundaries, which means that during an operation only the banks that are not concerned with the cross bank operation are available
for dual operations. For example, if a Block Erase
command is issued to erase blocks in both Bank A
and Bank B, then only Banks C or D are available
for read operations while the erase is being executed.
If a read operation is required in a bank, which is
programming or erasing, the program or erase operation can be suspended.
Also if the suspended operation was erase then a
program command can be issued to another
block, so the device can have one block in Erase
Suspend mode, one programming and other
banks in read mode.
By using a combination of these features, read operations are possible at any moment in the
M29DW640D device.
Tables 9 and 10 show the dual operations possible
in other banks and in the same bank. Note that
only the commonly used commands are represented in these tables.
Table 9. Dual Operations Allowed In Other Banks
Commands allowed in another bank(1)
Read
Array
Read
Status
Register(6)
Read
CFI
Query
Auto
Select
Program
Erase
Idle
Yes
Yes(2)
Yes
Yes
Yes
Yes
Yes(2)
Yes(3)
Programming
Yes
No
No
No
–
–
No
No
Erasing
Yes
No
No
No
–
–
No
No
Program Suspended
Yes
No
Yes
Yes
No
No
–
Yes(5)
Erase Suspended
Yes
No
Yes
Yes
Yes
No
–
Yes(4)
Status of bank(1)
Program/ Program/
Erase
Erase
Suspend Resume
Note: 1. If several banks are involved in a program or erase operation, then only the banks that are not concerned with the operation are
available for dual operations.
2. Only after a program or erase operation in that bank.
3. Only after a Program or Erase Suspend command in that bank.
4. Only an Erase Resume is allowed if the bank was previously in Erase Suspend mode.
5. Only a Program Resume is allowed if the bank was previously in Program Suspend mode.
6. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.
25/56
M29DW640D
Table 10. Dual Operations Allowed In Same Bank
Commands allowed in same bank
Status of bank
Read
Array
Read
Read
Status
CFI
Query
Register(6)
Auto
Select
Program
Erase
Program/ Program/
Erase
Erase
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes(2)
Yes(3)
Programming
No
Yes
No
No
–
–
Yes(4)
–
Erasing
No
Yes
No
No
–
No
Yes(5)
–
Program Suspended
Yes(1)
No
Yes
Yes
No
–
–
Yes
Erase Suspended
Yes(1)
Yes(7)
Yes
Yes
Yes(1)
No
–
Yes
Note: 1.
2.
3.
4.
5.
6.
7.
26/56
Not allowed in the Block or Word that is being erased or programmed.
Only after a program or erase operation in that bank.
Only after a Program or Erase Suspend command in that bank.
Only a Program Suspend.
Only an Erase suspend.
Read Status Register is not a command. The Status Register can be read during a block program or erase operation.
The Status Register can be read by addressing the block being erase suspended.
M29DW640D
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 11. Absolute Maximum Ratings
Symbol
Parameter
TBIAS
Temperature Under Bias
TSTG
Storage Temperature
TLEAD
Lead Temperature during
Min
Max
Unit
–50
125
°C
–65
150
°C
260(2)
°C
Soldering(1)
VIO
Input or Output Voltage (3,4)
–0.6
VCC +0.6
V
VCC
Supply Voltage
–0.6
4
V
VID
Identification Voltage
–0.6
13.5
V
Program Voltage
–0.6
13.5
V
VPP(5)
Note: 1.
2.
3.
4.
5.
ECOPACK®
Compliant with the
7191395 specification for Lead-free soldering processes.
Not exceeding 250°C for more than 30s, and peaking at 260°C.
Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
VPP must not remain at 12V for more than a total of 80hrs.
27/56
M29DW640D
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 12., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
M29DW640D
Parameter
70
90
Unit
Min
Max
Min
Max
VCC Supply Voltage
2.7
3.6
2.7
3.6
V
Ambient Operating Temperature
–40
85
–40
85
°C
Load Capacitance (CL)
30
30
Input Rise and Fall Times
pF
10
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 9. AC Measurement I/O Waveform
10
ns
0 to VCC
0 to VCC
V
VCC/2
VCC/2
V
Figure 10. AC Measurement Load Circuit
VPP
VCC
VCC
VCC
VCC/2
25kΩ
0V
DEVICE
UNDER
TEST
AI05557
25kΩ
CL
0.1µF
0.1µF
CL includes JIG capacitance
AI05558
Table 13. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
28/56
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
M29DW640D
Table 14. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
Supply Current (Standby)
E = VCC ±0.2V,
RP = VCC ±0.2V
100
µA
VPP/WP =
VIL or VIH
20
mA
VPP/WP = VPP
20
mA
ICC1(2)
ICC2
ICC3
(1,2)
Supply Current (Program/
Erase)
Program/Erase
Controller active
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7VCC
VCC +0.3
V
VPP
Voltage for VPP/WP Program
Acceleration
VCC = 2.7V ±10%
11.5
12.5
V
IPP
Current for VPP/WP Program
Acceleration
VCC =2.7V ±10%
15
mA
VOL
Output Low Voltage
IOL = 1.8mA
0.45
V
VOH
Output High Voltage
IOH = –100µA
VID
Identification Voltage
11.5
12.5
V
Program/Erase Lockout Supply
Voltage
1.8
2.3
V
VLKO
VCC –0.4
V
Note: 1. Sampled only, not 100% tested.
2. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
29/56
M29DW640D
Figure 11. Random Read AC Waveforms
tAVAV
A0-A21/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGHQZ
tGLQV
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05559
Figure 12. Page Read AC Waveforms
A2-A21/
A–1
VALID
A0-A1
VALID
VALID
VALID
VALID
tAVQV
E
tELQV
tEHQX
tEHQZ
G
tGLQV
tGHQX
tAVQV1
DQ0-DQ7/
DQ8-DQ15
VALID
tGHQZ
VALID
VALID
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI07762
30/56
M29DW640D
Table 15. Read AC Characteristics
M29DW640D
Symbol
Alt
Parameter
Test Condition
Unit
70
90
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
70
90
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
70
90
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
E = VIL,
G = VIL
Max
25
30
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
70
90
ns
tGLQX (1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
30
35
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
30
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
30
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output Transition
Min
0
0
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
25
30
ns
tBHQV
tFHQV
BYTE High to Output Valid
Max
30
40
ns
Note: 1. Sampled only, not 100% tested.
31/56
M29DW640D
Figure 13. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A21/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI05560
Table 16. Write AC Characteristics, Write Enable Controlled
M29DW640D
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
50
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
50
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
32/56
M29DW640D
Figure 14. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A21/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI05561
Table 17. Write AC Characteristics, Chip Enable Controlled
M29DW640D
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
50
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tEHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
33/56
M29DW640D
Figure 15. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled
Address Outside the Bank
Being Programmed or Erased
A0-A20
Address Outside the Bank
Being Programmed or Erased
Address in the Bank
Being Programmed or Erased
tAXEL
E
G
tELQV
tELQV
Data
DQ2(1)/DQ6(2)
Read Operation outside the Bank
Being Programmed or Erased
Toggle/
Alternative Toggle Bit
Toggle/
Alternative Toggle Bit
Read Operation in the Bank
Being Programmed or Erased
Data
Read Operation Outside the Bank
Being Programmed or Erased
AI08914c
Note: 1. The Toggle bit is output on DQ6.
2. The Alternative Toggle bit is output on DQ2.
Figure 16. Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled
Address Outside the Bank
Being Programmed or Erased
A0-A20
Address Outside the Bank
Being Programmed or Erased
Address in the Bank
Being Programmed or Erased
tAXGL
G
E
tGLQV
tGLQV
Data
DQ2(1)/DQ6(2)
Read Operation outside the Bank
Being Programmed or Erased
Toggle/
Alternative Toggle Bit
Toggle/
Alternative Toggle Bit
Read Operation in the Bank
Being Programmed or Erased
Data
Read Operation Outside the Bank
Being Programmed or Erased
AI08915c
Note: 1. The Toggle bit is output on DQ6.
2. The Alternative Toggle bit is output on DQ2.
Table 18. Toggle and Alternative Toggle Bits AC Characteristics
M29DW640D
Symbol
Alt
Parameter
Unit
70
90
tAXEL
Address Transition to Chip Enable Low
Min
10
10
ns
tAXGL
Address Transition to Output Enable Low
Min
10
10
ns
Note: tELQV and tGLQV values are presented in Table 15., Read AC Characteristics.
34/56
M29DW640D
Figure 17. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Table 19. Reset/Block Temporary Unprotect AC Characteristics
M29DW640D
Symbol
tPHWL (1)
tPHEL
Alt
Parameter
Unit
70
90
tRH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
tPLYH
tREADY
RP Low to Read Mode
Max
50
50
µs
tPHPHH (1)
tVIDR
RP Rise Time to VID
Min
500
500
ns
VPP Rise and Fall Time
Min
250
250
ns
tPHGL (1)
tRHWL (1)
tRHEL (1)
tRHGL
(1)
tVHVPP (1)
Note: 1. Sampled only, not 100% tested.
Figure 18. Accelerated Program Timing Waveforms
VPP
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI05563
35/56
M29DW640D
PACKAGE MECHANICAL
Figure 19. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
α
A1
DIE
L
C
CP
TSOP-G
Note: Drawing is not to scale.
Table 20. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3
0
5
36/56
0.0315
0
5
3
M29DW640D
Figure 20. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline
D
D1
SD
FD
e
E
ddd
SE
E1
BALL "A1"
FE
A
e
b
A2
A1
BGA-Z33
Note: Drawing is not to scale.
Table 21. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.250
A2
0.0098
0.900
b
Max
0.350
0.450
0.0354
0.0138
0.0177
D
7.000
6.900
7.100
0.2756
0.2717
0.2795
D1
5.600
–
–
0.2205
–
–
ddd
–
–
0.100
–
–
0.0039
E
11.000
10.900
11.100
0.4331
0.4291
0.4370
E1
8.800
–
–
0.3465
–
–
e
0.800
–
–
0.0315
–
–
FD
0.700
–
–
0.0276
–
–
FE
1.100
–
–
0.0433
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
37/56
M29DW640D
PART NUMBERING
Table 22. Ordering Information Scheme
Example:
M29DW640D
70
N
1
T
Device Type
M29
Architecture
D = Dual or Multiple Bank
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
640D = 64 Mbit (x8/x16), Boot Block, 8+24+24+8 partitioning
Speed
70 = 70ns
90 = 90ns
Package
N = TSOP48: 12 x 20 mm
ZA = FBGA63: 7 x 11mm, 0.80 mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
38/56
M29DW640D
APPENDIX A. BLOCK ADDRESSES
Bank A
Bank
Table 23. Block Addresses
Block
(KBytes/
KWords)
Protection Block
Group
(x8)
(x16)
0
8/4
Protection Group
000000h-001FFFh(1)
000000h–000FFFh(1)
1
8/4
Protection Group
002000h-003FFFh(1)
001000h–001FFFh(1)
2
8/4
Protection Group
004000h-005FFFh(1)
002000h–002FFFh(1)
3
8/4
Protection Group
006000h-007FFFh(1)
003000h–003FFFh(1)
4
8/4
Protection Group
008000h-009FFFh(1)
004000h–004FFFh(1)
5
8/4
Protection Group
00A000h-00BFFFh(1)
005000h–005FFFh(1)
6
8/4
Protection Group
00C000h-00DFFFh(1)
006000h–006FFFh(1)
7
8/4
Protection Group
00E000h-00FFFFh(1)
007000h–007FFFh(1)
8
64/32
010000h-01FFFFh
008000h–00FFFFh
9
64/32
020000h-02FFFFh
010000h–017FFFh
10
64/32
030000h-03FFFFh
018000h–01FFFFh
11
64/32
040000h-04FFFFh
020000h–027FFFh
12
64/32
050000h-05FFFFh
028000h–02FFFFh
Protection Group
Protection Group
13
64/32
060000h-06FFFFh
030000h–037FFFh
14
64/32
070000h-07FFFFh
038000h–03FFFFh
15
64/32
080000h-08FFFFh
040000h–047FFFh
16
64/32
090000h-09FFFFh
048000h–04FFFFh
Protection Group
17
64/32
0A0000h-0AFFFFh
050000h–057FFFh
18
64/32
0B0000h-0BFFFFh
058000h–05FFFFh
19
64/32
0C0000h-0CFFFFh
060000h–067FFFh
20
64/32
0D0000h-0DFFFFh
068000h–06FFFFh
Protection Group
21
64/32
0E0000h-0EFFFFh
070000h–077FFFh
22
64/32
0F0000h-0FFFFFh
078000h–07FFFFh
39/56
Bank
M29DW640D
Block
(KBytes/
KWords)
23
64/32
24
64/32
Protection Block
Group
(x8)
(x16)
100000h-10FFFFh
080000h–087FFFh
110000h-11FFFFh
088000h–08FFFFh
Protection Group
25
64/32
120000h-12FFFFh
090000h–097FFFh
26
64/32
130000h-13FFFFh
098000h–09FFFFh
27
64/32
140000h-14FFFFh
0A0000h–0A7FFFh
28
64/32
150000h-15FFFFh
0A8000h–0AFFFFh
Protection Group
29
64/32
160000h-16FFFFh
0B0000h–0B7FFFh
30
64/32
170000h-17FFFFh
0B8000h–0BFFFFh
31
64/32
180000h-18FFFFh
0C0000h–0C7FFFh
32
64/32
190000h-19FFFFh
0C8000h–0CFFFFh
Protection Group
33
64/32
1A0000h-1AFFFFh
0D0000h–0D7FFFh
34
64/32
1B0000h-1BFFFFh
0D8000h–0DFFFFh
35
64/32
1C0000h-1CFFFFh
0E0000h–0E7FFFh
36
64/32
1D0000h-1DFFFFh
0E8000h–0EFFFFh
Bank B
Protection Group
37
64/32
1E0000h-1EFFFFh
0F0000h–0F7FFFh
38
64/32
1F0000h-1FFFFFh
0F8000h–0FFFFFh
39
64/32
200000h-20FFFFh
100000h–107FFFh
40
64/32
210000h-21FFFFh
108000h–10FFFFh
Protection Group
41
64/32
220000h-22FFFFh
110000h–117FFFh
42
64/32
230000h-23FFFFh
118000h–11FFFFh
43
64/32
240000h-24FFFFh
120000h–127FFFh
44
64/32
250000h-25FFFFh
128000h–12FFFFh
Protection Group
45
64/32
260000h-26FFFFh
130000h–137FFFh
46
64/32
270000h-27FFFFh
138000h–13FFFFh
47
64/32
280000h-28FFFFh
140000h–147FFFh
48
64/32
290000h-29FFFFh
148000h–14FFFFh
Protection Group
49
64/32
2A0000h-2AFFFFh
150000h–157FFFh
50
64/32
2B0000h-2BFFFFh
158000h–15FFFFh
51
64/32
2C0000h-2CFFFFh
160000h–167FFFh
52
64/32
2D0000h-2DFFFFh
168000h–16FFFFh
Protection Group
40/56
53
64/32
2E0000h-2EFFFFh
170000h–177FFFh
54
64/32
2F0000h-2FFFFFh
178000h–17FFFFh
Bank
M29DW640D
Block
(KBytes/
KWords)
55
64/32
56
64/32
Protection Block
Group
(x8)
(x16)
300000h-30FFFFh
180000h–187FFFh
310000h-31FFFFh
188000h–18FFFFh
Protection Group
57
64/32
320000h-32FFFFh
190000h–197FFFh
58
64/32
330000h-33FFFFh
198000h–19FFFFh
59
64/32
340000h-34FFFFh
1A0000h–1A7FFFh
60
64/32
350000h-35FFFFh
1A8000h–1AFFFFh
Bank B
Protection Group
61
64/32
360000h-36FFFFh
1B0000h–1B7FFFh
62
64/32
370000h-37FFFFh
1B8000h–1BFFFFh
63
64/32
380000h-38FFFFh
1C0000h–1C7FFFh
64
64/32
390000h-39FFFFh
1C8000h–1CFFFFh
Protection Group
65
64/32
3A0000h-3AFFFFh
1D0000h–1D7FFFh
66
64/32
3B0000h-3BFFFFh
1D8000h–1DFFFFh
67
64/32
3C0000h-3CFFFFh
1E0000h–1E7FFFh
68
64/32
3D0000h-3DFFFFh
1E8000h–1EFFFFh
Protection Group
69
64/32
3E0000h-3EFFFFh
1F0000h–1F7FFFh
70
64/32
3F0000h-3FFFFFh
1F8000h–1FFFFFh
71
64/32
400000h–40FFFFh
200000h–207FFFh
72
64/32
410000h–41FFFFh
208000h–20FFFFh
Protection Group
73
64/32
420000h–42FFFFh
210000h–217FFFh
74
64/32
430000h–43FFFFh
218000h–21FFFFh
75
64/32
440000h–44FFFFh
220000h–227FFFh
76
64/32
450000h–45FFFFh
228000h–22FFFFh
Bank C
Protection Group
77
64/32
460000h–46FFFFh
230000h–237FFFh
78
64/32
470000h–47FFFFh
238000h–23FFFFh
79
64/32
480000h–48FFFFh
240000h–247FFFh
80
64/32
490000h–49FFFFh
248000h–24FFFFh
Protection Group
81
64/32
4A0000h–4AFFFFh
250000h–257FFFh
82
64/32
4B0000h–4BFFFFh
258000h–25FFFFh
83
64/32
4C0000h–4CFFFFh
260000h–267FFFh
84
64/32
4D0000h–4DFFFFh
268000h–26FFFFh
Protection Group
85
64/32
4E0000h–4EFFFFh
270000h–277FFFh
86
64/32
4F0000h–4FFFFFh
278000h–27FFFFh
41/56
Bank
M29DW640D
Block
(KBytes/
KWords)
87
64/32
88
64/32
Protection Block
Group
(x8)
(x16)
500000h–50FFFFh
280000h–287FFFh
510000h–51FFFFh
288000h–28FFFFh
Protection Group
89
64/32
520000h–52FFFFh
290000h–297FFFh
90
64/32
530000h–53FFFFh
298000h–29FFFFh
91
64/32
540000h–54FFFFh
2A0000h–2A7FFFh
92
64/32
550000h–55FFFFh
2A8000h–2AFFFFh
Protection Group
93
64/32
560000h–56FFFFh
2B0000h–2B7FFFh
94
64/32
570000h–57FFFFh
2B8000h–2BFFFFh
95
64/32
580000h–58FFFFh
2C0000h–2C7FFFh
96
64/32
590000h–59FFFFh
2C8000h–2CFFFFh
Protection Group
97
64/32
5A0000h–5AFFFFh
2D0000h–2D7FFFh
98
64/32
5B0000h–5BFFFFh
2D8000h–2DFFFFh
99
64/32
5C0000h–5CFFFFh
2E0000h–2E7FFFh
100
64/32
5D0000h–5DFFFFh
2E8000h–2EFFFFh
Bank C
Protection Group
101
64/32
5E0000h–5EFFFFh
2F0000h–2F7FFFh
102
64/32
5F0000h–5FFFFFh
2F8000h–2FFFFFh
103
64/32
600000h–60FFFFh
300000h–307FFFh
104
64/32
610000h–61FFFFh
308000h–30FFFFh
Protection Group
105
64/32
620000h–62FFFFh
310000h–317FFFh
106
64/32
630000h–63FFFFh
318000h–31FFFFh
107
64/32
640000h–64FFFFh
320000h–327FFFh
108
64/32
650000h–65FFFFh
328000h–32FFFFh
Protection Group
109
64/32
660000h–66FFFFh
330000h–337FFFh
110
64/32
670000h–67FFFFh
338000h–33FFFFh
111
64/32
680000h–68FFFFh
340000h–347FFFh
112
64/32
690000h–69FFFFh
348000h–34FFFFh
Protection Group
113
64/32
6A0000h–6AFFFFh
350000h–357FFFh
114
64/32
6B0000h–6BFFFFh
358000h–35FFFFh
115
64/32
6C0000h–6CFFFFh
360000h–367FFFh
116
64/32
6D0000h–6DFFFFh
368000h–36FFFFh
Protection Group
42/56
117
64/32
6E0000h–6EFFFFh
370000h–377FFFh
118
64/32
6F0000h–6FFFFFh
378000h–37FFFFh
Bank
M29DW640D
Block
(KBytes/
KWords)
119
64/32
120
64/32
Protection Block
Group
(x8)
(x16)
700000h–70FFFFh
380000h–387FFFh
710000h–71FFFFh
388000h–38FFFFh
Protection Group
121
64/32
720000h–72FFFFh
390000h–397FFFh
122
64/32
730000h–73FFFFh
398000h–39FFFFh
123
64/32
740000h–74FFFFh
3A0000h–3A7FFFh
124
64/32
750000h–75FFFFh
3A8000h–3AFFFFh
Protection Group
125
64/32
760000h–76FFFFh
3B0000h–3B7FFFh
126
64/32
770000h–77FFFFh
3B8000h–3BFFFFh
127
64/32
780000h–78FFFFh
3C0000h–3C7FFFh
128
64/32
790000h–79FFFFh
3C8000h–3CFFFFh
Bank D
Protection Group
129
64/32
7A0000h–7AFFFFh
3D0000h–3D7FFFh
130
64/32
7B0000h–7BFFFFh
3D8000h–3DFFFFh
131
64/32
7C0000h–7CFFFFh
3E0000h–3E7FFFh
132
64/32
7D0000h–7DFFFFh
3E8000h–3EFFFFh
133
64/32
7E0000h–7EFFFFh
3F0000h–3F7FFFh
134
8/4
Protection Group
7F0000h–7F1FFFh
3F8000h–3F8FFFh
135
8/4
Protection Group
7F2000h–7F3FFFh
3F9000h–3F9FFFh
136
8/4
Protection Group
7F4000h–7F5FFFh
3FA000h–3FAFFFh
137
8/4
Protection Group
7F6000h–7F7FFFh
3FB000h–3FBFFFh
138
8/4
Protection Group
7F8000h–7F9FFFh
3FC000h–3FCFFFh
139
8/4
Protection Group
7FA000h–7FBFFFh
3FD000h–3FDFFFh
140
8/4
Protection Group
7FC000h–7FDFFFh
3FE000h–3FEFFFh
141
8/4
Protection Group
7FE000h–7FFFFFh
3FF000h–3FFFFFh
Protection Group
43/56
M29DW640D
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the Read CFI Query command is issued the
addressed bank enters Read CFI Query mode and
read operations in the same bank (A21-A19) output the CFI data. Tables 24, 25, 26, 27, 28 and 29
show the addresses (A-1, A0-A10) used to retrieve
the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Table 29., Security Code Area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security number after it has been written by ST.
Table 24. Query Structure Overview
Address
Sub-section Name
Description
x16
x8
10h
20h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
36h
System Interface Information
Device timing & voltage information
27h
4Eh
Device Geometry Definition
Flash device layout
40h
80h
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
61h
C2h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 25. CFI Query Identification String
Address
Data
Description
x16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported
19h
32h
0000h
Address for Alternate Algorithm extended Query table
1Ah
34h
0000h
“Q”
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 28)
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
44/56
Value
AMD
Compatible
P = 40h
NA
NA
M29DW640D
Table 26. CFI Query System Interface Information
Address
Data
Description
Value
x16
x8
1Bh
36h
0027h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
2.7V
1Ch
38h
0036h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
3.6V
1Dh
3Ah
00B5h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.5V
1Eh
3Ch
00C5h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12.5V
1Fh
3Eh
0004h
Typical timeout per single Byte/Word program = 2n µs
16µs
20h
40h
0000h
Typical timeout for minimum size write buffer program = 2n µs
NA
21h
42h
000Ah
Typical timeout per individual block erase = 2n ms
1s
22h
44h
0000h
Typical timeout for full Chip Erase = 2n ms
NA
23h
46h
0004h
Maximum timeout for Byte/Word program = 2n times typical
256 µs
24h
48h
0000h
Maximum timeout for write buffer program = 2n times typical
NA
25h
4Ah
0003h
Maximum timeout per individual block erase = 2n times typical
8s
26h
4Ch
0000h
Maximum timeout for Chip Erase = 2n times typical
NA
Table 27. Device Geometry Definition
Address
Data
Description
Value
x16
x8
27h
4Eh
0017h
Device Size = 2n in number of Bytes
28h
29h
50h
52h
0002h
0000h
Flash Device Interface Code description
2Ah
2Bh
54h
56h
0003h
0000h
Maximum number of Bytes in multi-Byte program or page = 2n
8
2Ch
58h
0003h
Number of Erase Block Regions(1). It specifies the number of
regions containing contiguous Erase Blocks of the same size.
3
2Dh
2Eh
5Ah
5Ch
0007h
0000h
Erase Block Region 1 Information
Number of Erase Blocks of identical size = 0007h+1
8
2Fh
30h
5Eh
60h
0020h
0000h
Erase Block Region 1 Information
Block size in Region 1 = 0020h * 256 Byte
31h
32h
62h
64h
007Dh
0000h
Erase Block Region 2 Information
Number of Erase Blocks of identical size = 007Dh+1
33h
34h
66h
68h
0000h
0001h
Erase Block Region 2 Information
Block size in Region 2 = 0100h * 256 Byte
8 MBytes
x8, x16
Async.
8 KBytes
126
64 KBytes
45/56
M29DW640D
Address
Data
Description
x16
x8
35h
36h
6Ah
6Ch
0007h
0000h
Erase Block Region 3 information
Number of Erase Blocks of identical size = 0007h + 1
37h
38h
6Eh
70h
0020h
0000h
Erase Block Region 3 information
Block size in region 3 = 0020h * 256 Bytes
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 information
Value
8
8 KBytes
Note: 1. Erase Block Region 1 corresponds to addresses 000000h to 007FFFh; Erase block Region 2 corresponds to addresses 008000h
to 3F7FFFh and Erase Block Region 3 corresponds to addresses 3F8000h to 3FFFFFh.
Table 28. Primary Algorithm-Specific Extended Query Table
Address
Data
Description
Value
x16
x8
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
"1"
44h
88h
0033h
Minor version number, ASCII
"3"
45h
8Ah
0000h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
8Eh
0001h
Block Protection
00 = not supported, x = number of sectors in per group
1
48h
90h
0001h
Temporary Block Unprotect
00 = not supported, 01 = supported
49h
92h
0005h
Block Protect /Unprotect
04 = M29W400B
05 = M29DW640D
4Ah
94h
0077h
Simultaneous Operations,
x = number of blocks (excluding Bank A)
119
4Bh
96h
0000h
Burst Mode, 00 = not supported, 01 = supported
No
4Ch
98h
0001h
Page Mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page Word
Yes
4Dh
9Ah
00B5h
VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
4Eh
9Ch
00C5h
VPP Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5V
46/56
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
Yes
5
M29DW640D
Address
Data
Description
Value
x16
x8
4Fh
9Eh
0001h
Top/Bottom Boot Block Flag
00h = uniform device
01h = 8 x8 KByte Blocks, Top and Bottom Boot with Write Protect
02h = Bottom boot device
03h = Top Boot Device
04h = Both Top and Bottom
T/B
50h
A0h
0001h
Program Suspend, 00 = not supported, 01 = supported
Yes
57h
AEh
0004h
Bank Organization, 00 = data at 4Ah is zero
X = number of banks
4
58h
B0h
0017h
Bank A information
X = number of blocks in Bank A
23
59h
B2h
0030h
Bank B information
X = number of blocks in Bank B
48
5Ah
B4h
0030h
Bank C information
X = number of blocks in Bank C
48
5Bh
B6h
0017h
Bank D information
X = number of blocks in Bank D
23
Table 29. Security Code Area
Address
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
47/56
M29DW640D
APPENDIX C. EXTENDED MEMORY BLOCK
The M29DW640D has an extra block, the Extended Block, that can be accessed using a dedicated
command.
This Extended Block is 128 Words in x16 mode
and 256 Bytes in x8 mode. It is used as a security
block (to provide a permanent security identification number) or to store additional information.
The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit
DQ7. This bit is permanently set to either ‘1’ or ‘0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protected. When set to ‘0’, it
indicates that the device is customer lockable and
the Extended Block is unprotected. Bit DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot be used instead of a factory locked one.
Bit DQ7 is the most significant bit in the Extended
Block Verify Code and a specific procedure must
be followed to read it. See “Extended Block Indicator Bit” in Tables 3 and 4, Bus Operations, BYTE =
VIL and Bus Operations, BYTE = VIH, respectively,
for details of how to read bit DQ7.
The Extended Block can only be accessed when
the device is in Extended Block mode. For details
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Command and Exit Extended Block Command paragraphs, and to Tables 5 and 6, “Commands, 16-bit
mode, BYTE = VIH” and “Commands, 8-bit mode,
BYTE = VIL”, respectively.
Factory Locked Extended Block
In devices where the Extended Block is factory
locked, the Security Identification Number is written to the Extended Block address space (see Table 30., Extended Block Address and Data) in the
factory. The DQ7 bit is set to ‘1’ and the Extended
Block cannot be unprotected.
Customer Lockable Extended Block
A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protection of the Extended Block is not reversible.
There are two ways of protecting the Extended
Block:
■
Issue the Enter Extended Block command to
place the device in Extended Block mode,
then use the In-System Technique with RP
either at VIH or at VID(refer to Appendix D, InSystem Technique and to the corresponding
flowcharts, Figures 23 and 24, for a detailed
explanation of the technique).
■
Issue the Enter Extended Block command to
place the device in Extended Block mode,
then use the Programmer Technique (refer to
Appendix D, Programmer Technique and to
the corresponding flowcharts, Figures 21 and
22, for a detailed explanation of the
technique).
Once the Extended Block is programmed and protected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return
the device to Read mode.
Table 30. Extended Block Address and Data
Address(1)
Data
Device
M29DW640D
x8
x16
000000h-00000Fh
000000h-000007h
000010h-000020h
000008h-00000Fh
000021h-0000FFh 000010h-00007Fh
Note: 1. See Table 23., Block Addresses.
2. ENS = Electronic Serial Number.
48/56
Factory Locked
Random Number
ESN
(2)
Security Identification
Number
Unavailable
Customer
Lockable
Determined by
Customer
M29DW640D
APPENDIX D. BLOCK PROTECTION
BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP (1). This can be achieved without violating
the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to
the system.
To protect a group of blocks follow the flowchart in
Figure 23., In-System Equipment Group Protect
Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the
groups can be unprotected at the same time. To
unprotect the chip follow Figure 24., In-System
Equipment Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to
Appendix A, Table 23 for details of the Protection
Groups. Once protected, Program and Erase operations within the protected group fail to change
the data.
There are three techniques that can be used to
control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section.
To protect the Extended Block issue the Enter Extended Block command and then use either the
Programmer or In-System technique. Once protected issue the Exit Extended Block command to
return to read mode. The Extended Block protection is irreversible, once protected the protection
cannot be undone.
Programmer Technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a group of blocks follow the flowchart in
Figure 21., Programmer Equipment Group Protect
Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 22., Programmer
Equipment Chip Unprotect Flowchart. Table
31., Programmer Technique Bus Operations,
Note: 1. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
Table 31. Programmer Technique Bus Operations, BYTE = VIH or VIL
E
G
W
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block (Group)
Protect(1)
VIL
VID
VIL Pulse
A9 = VID, A12-A21 Block Address
Others = X
X
Chip Unprotect
VID
VID
VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
VIH
A0 = VIL, A1 = VIH, A2 = VIL, A3 = VIL,
A6 = VIL, A9 = VID,
A12-A21 Block Address
Others = X
Pass = xx01h
Retry = xx00h.
VIH
A0 = VIL, A1 = VIH, A2 = VIL, A3 = VIL,
A6 = VIH, A9 = VID,
A12-A21 Block Address
Others = X
Pass = xx00h
Retry = xx01h.
Operation
Block (Group)
Protect Verify
Block (Group)
Unprotect Verify
VIL
VIL
VIL
VIL
Note: 1. Block Protection Groups are shown in Appendix D, Table 23.
49/56
M29DW640D
Figure 21. Programmer Equipment Group Protect Flowchart
START
Set-up
ADDRESS =
GROUP ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Wait 4µs
Protect
W = VIL
Wait 100µs
W = VIH
E, G = VIH, A1 = VIH
A0, A2, A3, A6 = VIL
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA = 01h
NO
End
YES
++n
= 25
NO
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
PASS
FAIL
AI07756
Note: 1. Block Protection Groups are shown in Appendix D, Table 23.
50/56
M29DW640D
Figure 22. Programmer Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL
GROUPS
n=0
CURRENT GROUP = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Wait 4µs
Unprotect
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT
GROUP ADDRESS
A0, A2, A3 = VIL
A1, A6 = VIH
E = VIL
Wait 4µs
INCREMENT
CURRENT GROUP
Verify
G = VIL
Wait 60ns
Read DATA
NO
NO
DATA = 00h
++n
= 1000
YES
LAST
GROUP
End
YES
A9 = VIH
E, G = VIH
FAIL
NO
YES
A9 = VIH
E, G = VIH
PASS
AI07757
Note: 1. Block Protection Groups are shown in Appendix D, Table 23.
51/56
M29DW640D
Figure 23. In-System Equipment Group Protect Flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
Wait 100µs
Verify
WRITE 40h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
DATA = 01h
NO
End
YES
RP = VIH
++n
= 25
ISSUE READ/RESET
COMMAND
RP = VIH
PASS
NO
YES
ISSUE READ/RESET
COMMAND
FAIL
AI07758
Note: 1. Block Protection Groups are shown in Appendix D, Table 23.
2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
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M29DW640D
Figure 24. In-System Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3, A6 = VIL, A1 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3 = VIL, A1, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS =
CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1, A6 = VIH
Wait 4µs
INCREMENT
CURRENT GROUP
READ DATA
ADDRESS =
CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1, A6 = VIH
NO
End
NO
DATA = 00h
++n
= 1000
YES
YES
LAST
GROUP
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI07759
Note: 1. Block Protection Groups are shown in Appendix D, Table 23.
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REVISION HISTORY
Table 32. Document Revision History
Date
Version
10-Dec-2002
1.0
Document written
1.1
Typical after 100k W/E Cycles column removed from Table 7., Program, Erase Times and
Program, Erase Endurance Cycles, and Data Retention and Erase Suspend Latency
Time parameters added. Device code corrected. Address on DQ7-DQ0 modified for the
cycle No.2 of the Read Device code in Table 3., Bus Operations, BYTE = VIL.
Lead-free package options E and F added to Table 22., Ordering Information Scheme.
1.2
Document Status promoted to Preliminary Data. Page mode added, Appendix C
“Extended Memory Block” added. VSS signal description clarified. Parameter IID removed
from DC Characteristics Table. Read CFI Query command address clarified. Program
Suspend Latency time added to Table 7., Program, Erase Times and Program, Erase
Endurance Cycles. Dual operations section added.
15-May-2003
1.3
Note added to Table 22., Ordering Information Scheme. Table 20., TSOP48 – 48 lead
Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data and Figure
19., TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline,
modified.
Data modified at addresses 4Ah and 4Fh in Table 28, Primary Algorithm-Specific
Extended Query Table and at address 2Ch in Table 27, Device Geometry Definition.
18-Jul-2003
2.0
Note 1 removed from: Figures 5 and 6, Block Address (x8 and x16, respectively), and
from Table 23, Block Addresses. RB bit is High-Z (instead of 1), in Table 8.
Auto Select Command description modified. Extended Memory Block size modified in
Appendix C.
15-Sep-2003
2.1
Figures 15 and 16, Toggle and Alternative Toggle Bits Mechanisms added.
Table 16, Toggle and Alternative Toggle Bits AC Characteristics added.
Address 38h modified, addresses 39h to 3Ch added in Device Geometry Definition.
Address 44h modified in Table 28., Primary Algorithm-Specific Extended Query Table.
07-Oct-2003
2.2
Figures 15 and 16, Toggle and Alternative Toggle Bits Mechanisms modified; and Notes 1
and 2 added. Table 18., Toggle and Alternative Toggle Bits AC Characteristics updated.
Figure 8., Toggle Flowchart renamed and modified, Note added.
07-Nov-2003
2.3
Bank Address modified in the Auto Select command, Read CFI Query command and
COMMON FLASH INTERFACE (CFI) sections.
Addresses for Read CFI Query command modified in the Read CFI command section.
2.4
Vcc minimum value updated in Table 12., Operating and AC Measurement Conditions.
VPP and IPP test conditions updated in Table 14., DC Characteristics.
Customer Lockable Extended Block mechanism modified in APPENDIX C., EXTENDED
MEMORY BLOCK.
APPENDIX D., BLOCK PROTECTION updated: Note 1 added in the In-System
Technique section and Note 2 added below Figure 23., In-System Equipment Group
Protect Flowchart.
19-Dec-2003
2.5
Architecture Identifier updated in Table 22, Part Numbering Scheme.
Customer Lockable Extended Block mechanism modified in APPENDIX C., EXTENDED
MEMORY BLOCK .
APPENDIX D., BLOCK PROTECTION updated: Note 1 updated in the In-System
Technique section and Note 2 updated below Figure 23., In-System Equipment Group
Protect Flowchart.
12-Aug-2004
3.0
Figure 2., Logic Diagram and Figure 3., TSOP Connections updated.
Table 9., Dual Operations Allowed In Other Banks and Table 10., Dual Operations
Allowed In Same Bank updated in DUAL OPERATIONS AND MULTIPLE BANK
ARCHITECTURE section.
27-Feb-2003
01-Apr-2003
18-Nov-2003
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Revision Details
M29DW640D
Date
Version
10-Dec-2004
4.0
Revision Details
Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in
Table 8., Status Register Bits.
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M29DW640D
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