STMicroelectronics M29F002BT55N1T 2 mbit 256kb x8, boot block single supply flash memory Datasheet

M29F002BT, M29F002BNT
M29F002BB, M29F002BNB
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
■
SINGLE 5V ± 10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■
ACCESS TIME: 45 ns
■
PROGRAMMING TIME
– 8 µs by Byte typical
■
7 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
PLCC32 (K)
TSOP32 (N)
8 x 20mm
– 2 Parameter and 4 Main Blocks
■
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
■
32
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
1
PDIP32 (P)
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■
TEMPORARY BLOCK UNPROTECTION
MODE
■
LOW POWER CONSUMPTION
Figure 1. Logic Diagram
VCC
– Standby and Automatic Standby
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
20 YEARS DATA RETENTION
18
8
A0-A17
DQ0-DQ7
– Defectivity below 1 ppm/year
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
W
E
– Top Device Code M29F002BT: B0h
– Top Device Code M29F002BNT: B0h
– Bottom Device Code M29F002BB: 34h
G
M29F002BT
M29F002BB
M29F002BNT
M29F002BNB
RP
– Bottom Device Code M29F002BNB: 34h
VSS
AI02957B
April 2002
1/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Figure 3. TSOP Connections
A11
A9
A8
A13
A14
A17
W
VCC
A12
A15
A16
RP
VCC
W
A17
Figure 2. PLCC Connections
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
9
M29F002BT
M29F002BB
M29F002BNB
25
A14
A13
A8
A9
A11
G
A10
E
DQ7
RP
A16
A15
A12
A7
A6
A5
A4
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
17
1
8
9
32
M29F002BT
M29F002BB
16
AI02959B
Figure 4. PDIP Connections
RP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
17
AI02958
Table 1. Signal Names
1
2
3
4
5
6
7 M29F002BT
8 M29F002BB
9 M29F002BNT
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02960
2/22
25
24
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
VCC
W
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A0-A17
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
M29F002BT, M29F002BB:
Reset/Block Temporary Unprotect
RP
M29F002BNT, M29F002BNB:
Not Connected Internally
VCC
Supply Voltage
VSS
Ground
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (Temperature Range Option 1)
0 to 70
°C
Ambient Operating Temperature (Temperature Range Option 6)
–40 to 85
°C
Ambient Operating Temperature (Temperature Range Option 3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage
–0.6 to 6
V
VCC
Supply Voltage
–0.6 to 6
V
VID
Identification Voltage
–0.6 to 13.5
V
TA
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
SUMMARY DESCRIPTION
The M29F002B is a 2 Mbit (256Kb x8) non-volatile
memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM. The
M29F002B is fully backward compatible with the
M29F002.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP32 (8 x 20mm),
PLCC32 and PDIP packages and it is supplied
with all the bits erased (set to ’1’).
Table 3. Top Boot Block Addresses,
M29F002BT, M29F002BNT
Table 4. Bottom Boot Block Addresses,
M29F002BB
#
Size
(Kbytes)
Address Range
#
Size
(Kbytes)
Address Range
6
16
3C000h-3FFFFh
6
64
30000h-3FFFFh
5
8
3A000h-3BFFFh
5
64
20000h-2FFFFh
4
8
38000h-39FFFh
4
64
10000h-1FFFFh
3
32
30000h-37FFFh
3
32
08000h-0FFFFh
2
64
20000h-2FFFFh
2
8
06000h-07FFFh
1
64
10000h-1FFFFh
1
8
04000h-05FFFh
0
64
00000h-0FFFFh
0
16
00000h-03FFFh
3/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V IH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected. On the M29F002BNT the pin is not
connected internally and this feature is not available.
4/22
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V IL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after t PHEL
or tPLYH, whichever occurs last. See Table 15 and
Figure 12, Reset/Temporary Unprotect AC Characteristics for more details.
Holding RP at V ID will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Reset/Block Temporary Unprotect can be left unconnected. A weak internal pull-up resistor ensures that the memory always operates correctly.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V CC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC4.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See
Table 5, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V IL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 9, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus
Write operation. See Figures 10 and 11, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V IH.
Standby. When Chip Enable is High, VIH, the
Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at V IH the Supply Current is
reduced to the TTL Standby Supply Current, I CC2.
To further reduce the Supply Current to the CMOS
Standby Supply Current, ICC3, Chip Enable should
be held within V CC ± 0.2V. For Standby current
levels see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC4, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, ICC3.
The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 5, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against accidental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
Table 5. Bus Operations
Operation
G
W
Bus Read
VIL
VIL
VIH
Cell Address
Bus Write
VIL
VIH
VIL
Command Address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
20h
Read Device Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
B0h (M29F002BT)
B0h (M29F002BNT)
34h (M29F002BB)
Output Disable
Address Inputs
Data
Inputs/Outputs
E
Data Output
Data Input
Note: X = VIL or VIH.
5/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The commands are summarized in Table 6, Commands. Refer to Table 6 in conjunction with the
text descriptions below.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take upto 10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V IL and A1 = VIL. The other address bits
may be set to either V IL or VIH. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either V IL or VIH. The
Device Code for the M29F002BT is B0h, the
M29F002BNT is B0h and the M29F002BB is 34h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = V IH, and A13-A17 specifying the address of
the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected
then 01h is output on the Data Inputs/Outputs, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal
6/22
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 7. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be programmed; the operation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock Bypass Mode. See the Program command for details
on the behavior.
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Command
Length
Table 6. Commands
Bus Write Operations
1st
2nd
Addr
Data
1
X
F0
3
555
Auto Select
3
Program
3rd
4th
Addr
Data
Addr
Data
AA
2AA
55
X
F0
555
AA
2AA
55
555
90
4
555
AA
2AA
55
555
A0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
555
Erase Suspend
1
X
B0
Erase Resume
1
X
30
5th
Addr
Data
PA
PD
80
555
80
555
6th
Addr
Data
Addr
Data
AA
2AA
55
555
10
AA
2AA
55
BA
30
Read/Reset
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 7. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
7/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 7. All Bus Read operations during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased will output the Status Register. It
is also possible to enter the Auto Select mode: the
memory will behave as in the Auto Select mode on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Table 7. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Typ (1)
Typical after
100k W/E Cycles (1)
Chip Erase (All bits in the memory set to ‘0’)
0.8
0.8
Chip Erase
2.5
2.5
10
sec
Block Erase (64 Kbytes)
0.6
0.6
4
sec
8
8
150
µs
2.3
2.3
9
sec
Parameter
Min
Program
Chip Program
Program/Erase Cycles (per Block)
Note: 1. TA = 25 °C, VCC = 5V.
8/22
100,000
Max
Unit
sec
cycles
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 8, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 5, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 6, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so may
or may not set DQ5 at ’1’. In both cases, a successive Bus Read operation will show the bit is still ’0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Table 8. Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
Program
Any Address
DQ7
Toggle
0
–
–
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
Program Error
Any Address
DQ7
Toggle
1
–
–
Chip Erase
Any Address
0
Toggle
0
1
Toggle
Erasing Block
0
Toggle
0
0
Toggle
Non-Erasing Block
0
Toggle
0
0
No Toggle
Block Erase before timeout
Block Erase
Erase Suspend
Erase Error
Erasing Block
0
Toggle
0
1
Toggle
Non-Erasing Block
0
Toggle
0
1
No Toggle
Erasing Block
1
No Toggle
0
–
Toggle
Non-Erasing Block
Data read as normal
Good Block Address
0
Toggle
1
1
No Toggle
Faulty Block Address
0
Toggle
1
1
Toggle
Note: Unspecified data bits should be ignored.
9/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Figure 5. Data Polling Flowchart
Figure 6. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
NO
NO
YES
DQ5
=1
NO
YES
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
DQ5
=1
READ DQ6
TWICE
YES
DQ6
=
TOGGLE
NO
NO
YES
FAIL
PASS
FAIL
AI03598
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
10/22
PASS
AI01370B
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased correctly.
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 9. AC Measurement Conditions
M29F002B
Parameter
45 / 55
70 / 90 / 120
High Speed
Standard
30pF
100pF
Input Rise and Fall Times
≤ 10ns
≤ 10ns
Input Pulse Voltages
0 to 3V
0.45 to 2.4V
1.5V
0.8V and 2V
AC Test Conditions
Load Capacitance (CL)
Input and Output Timing Ref. Voltages
Figure 7. AC Testing Input Output Waveform
Figure 8. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
Standard
2.4V
OUT
CL = 30pF or 100pF
2.0V
0.8V
0.45V
AI01275B
CL includes JIG capacitance
AI03027
Table 10. Capacitance
(TA = 25 °C, f = 1 MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Max
Unit
VIN = 0V
Min
6
pF
VOUT = 0V
12
pF
Note: Sampled only, not 100% tested.
11/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 11. DC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Symbol
Parameter
Test Condition
ILI(1)
Input Leakage Current
ILR1
Min
Typ (3)
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
RP Leakage Current High
RP = VCC
±1
µA
ILR2
RP Leakage Current Low
RP = VSS
–10
µA
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
ICC1
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
15
mA
ICC2
Supply Current (Standby) TTL
1
mA
ICC3
Supply Current (Standby) CMOS
E = VCC ±0.2V,
RP = VCC ±0.2V
100
µA
ICC4 (2)
Supply Current (Program/Erase)
Program/Erase
Controller active
20
mA
–0.2
5
E = VIH
30
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2
VCC +0.5
V
VOL
Output Low Voltage
0.45
V
Output High Voltage TTL
IOH = –12.5mA
2.4
V
Output High Voltage CMOS
IOH = –100µA
VCC –0.4
V
VOH
VID
Identification Voltage
IID
Identification Current
VLKO (2)
Program/Erase Lockout Supply
Voltage
Note: 1. Excluding the RP input.
2. Sampled only, not 100% tested.
3. TA = 25°C, VCC = 5V.
12/22
IOL = 5.8mA
11.5
A9 = VID
3.2
12.5
V
100
µA
4.2
V
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 12. Read AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F002B
Symbol
Alt
Parameter
Test Condition
Unit
45
55
70 / 90 / 120
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
45
55
70
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
45
55
70
ns
tELQX (1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
Min
0
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
45
55
70
ns
tGLQX (1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
25
30
30
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
15
18
20
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
15
18
20
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output
Transition
Min
0
0
0
ns
Note: 1. Sampled only, not 100% tested.
Figure 9. Read Mode AC Waveforms
tAVAV
A0-A17
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGLQV
DQ0-DQ7
tGHQX
tGHQZ
VALID
AI02961
13/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 13. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F002B
Symbol
Alt
Parameter
Unit
45
55
70 / 90 / 120
tAVAV
tWC
Address Valid to Next Address Valid
Min
45
55
70
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
40
40
45
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
25
25
30
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
20
20
20
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
40
40
45
ns
Output Enable High to Write Enable Low
Min
0
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
0
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
50
µs
Figure 10. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A17
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7
tWHDX
VALID
VCC
tVCHEL
AI02083
14/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 14. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F002B
Symbol
Alt
Parameter
Unit
45
55
70 / 90 / 120
tAVAV
tWC
Address Valid to Next Address Valid
Min
45
55
70
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
40
40
45
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
25
25
30
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
20
20
20
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
40
40
45
ns
Output Enable High Chip Enable Low
Min
0
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
0
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
50
µs
Figure 11. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A17
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7
tEHDX
VALID
VCC
tVCHWL
AI02084
15/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 15. Reset/Block Temporary Unprotect AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F002B
Symbol
Alt
tPHWL (1)
tPHEL
Parameter
Unit
45
55
70 / 90 / 120
tRH
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
50
50
50
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
500
ns
tPLYH (1)
tREADY
RP Low to Read Mode
Max
10
10
10
µs
tPHPHH (1)
tVIDR
RP Rise Time to VID
Min
500
500
500
ns
tPHGL
(1)
Note: 1. Sampled only, not 100% tested.
Figure 12. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RP
tPLPX
tPHPHH
tPLYH
AI02943
16/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 16. Ordering Information Scheme
Example:
M29F002BB
45
N
1
T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
002B = 2 Mbit (256Kb x8), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
NT = Top Boot, No Reset/Block Temporary Unprotect pin
NB = Bottom Boot, No Reset/Block Temporary Unprotect pin
Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
90 = 90 ns
120 = 120 ns
Package
K = PLCC32
N = TSOP32: 8 x 20 mm
P = PDIP32
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
3 = –40 to 125 °C
Option
T = Tape & Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
17/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 17. Revision History
Date
Rev.
July 1999
-01
First Issue
-02
Chip Erase Max. specification added (Table 7)
Block Erase Max. specification added (Table 7)
Program Max. specification added (Table 7)
Chip Program Max. specification added (Table 7)
ICC1 and ICC3 Typ. specification added (Table 11)
ICC3 Test Condition changed (Table 11)
28-Jul-2000
-03
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 5)
Data Toggle Flowchart diagram change (Figure 6)
22-Apr-2002
-04
M29F002BNB device added
PLCC32 package mechanical data modified
07-Oct-1999
18/22
Revision Details
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
A1
A2
1 N
B1
E2
E3
e
E1 E
F
B
0.51 (.020)
E2
1.14 (.045)
A
D3
R
D2
CP
D2
PLCC-A
Note: Drawing is not to scale.
PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol
millimeters
Typ
inches
Min
Max
A
3.18
A1
Min
Max
3.56
0.125
0.140
1.53
2.41
0.060
0.095
A2
0.38
–
0.015
–
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
CP
Typ
0.10
0.004
D
12.32
12.57
0.485
0.495
D1
11.35
11.51
0.447
0.453
D2
4.78
5.66
0.188
0.223
–
–
–
–
E
14.86
15.11
0.585
0.595
E1
13.89
14.05
0.547
0.553
E2
6.05
6.93
0.238
0.273
–
–
0.400
–
–
0.050
D3
7.62
E3
10.16
e
1.27
–
–
F
0.00
0.13
N
32
R
0.89
–
0.300
–
–
0.000
0.005
32
–
0.035
–
–
19/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.20
Max
0.0472
A1
0.05
0.15
0.0020
0.0059
A2
0.95
1.05
0.0374
0.0413
B
0.15
0.27
0.0059
0.0106
C
0.10
0.21
0.0039
0.0083
D
19.80
20.20
0.7795
0.7953
D1
18.30
18.50
0.7205
0.7283
E
7.90
8.10
0.3110
0.3189
–
–
–
–
L
0.50
0.70
0.0197
0.0276
α
0°
5°
0°
5°
N
32
e
CP
20/22
Max
0.50
0.0197
32
0.10
0.0039
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline
A
A2
A1
B1
B
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Note: 1. Drawing is not to scale.
PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
Max.
A
–
A1
Min.
Max.
5.08
–
0.2000
0.38
–
0.0150
–
A2
3.56
4.06
0.1402
0.1598
B
0.38
0.51
0.0150
0.0201
–
–
–
–
C
0.20
0.30
0.0079
0.0118
D
41.78
42.04
1.6449
1.6551
B1
1.52
Typ.
0.0598
D2
38.10
–
–
1.5000
–
–
E
15.24
–
–
0.6000
–
–
13.59
13.84
0.5350
0.5449
E1
e1
2.54
–
–
0.1000
–
–
eA
15.24
–
–
0.6000
–
–
eB
15.24
17.78
0.6000
0.7000
L
3.18
3.43
0.1252
0.1350
S
1.78
2.03
0.0701
0.0799
α
0°
10°
0°
10°
N
32
32
21/22
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
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22/22