M29F100BT M29F100BB 1 Mbit (128Kb x8 or 64Kb x16, Boot Block) Single Supply Flash Memory ■ SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ ACCESS TIME: 45ns ■ PROGRAMMING TIME – 8µs per Byte/Word typical ■ 44 5 MEMORY BLOCKS – 1 Boot Block (Top or Bottom Location) – 2 Parameter and 2 Main Blocks ■ PROGRAM/ERASE CONTROLLER – Embedded Byte/Word Program algorithm 1 TSOP48 (N) 12 x 20mm SO44 (M) – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin ■ ERASE SUSPEND and RESUME MODES Figure 1. Logic Diagram – Read and Program another Block during Erase Suspend ■ UNLOCK BYPASS PROGRAM COMMAND VCC – Faster Production/Batch Programming ■ ■ TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION – Standby and Automatic Standby ■ ■ ■ 16 15 A0-A15 DQ0-DQ14 W 100,000 PROGRAM/ERASE CYCLES per BLOCK E 20 YEARS DATA RETENTION G – Defectivity below 1 ppm/year RP DQ15A–1 M29F100BT M29F100BB BYTE RB ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Top Device Code M29F100BT: 00D0h – Bottom Device Code M29F100BB: 00D1h VSS AI02916 July 2000 1/22 M29F100BT, M29F100BB Figure 2. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC NC A7 A6 A5 A4 A3 A2 A1 Figure 3. SO Connections 1 12 13 48 37 36 M29F100BT M29F100BB 24 25 NC BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC RB NC A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29F100BT 34 12 M29F100BB 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23 RP W A8 A9 A10 A11 A12 A13 A14 A15 NC BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC AI02918 AI02917 Table 1. Signal Names A0-A15 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select VCC Supply Voltage VSS Ground NC Not Connected Internally 2/22 SUMMARY DESCRIPTION The M29F100B is a 1 Mbit (128Kb x8 or 64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29F100B is fully backward compatible with the M29F100. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. M29F100BT, M29F100BB Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage –0.6 to 6 V VCC Supply Voltage –0.6 to 6 V V ID Identification Voltage –0.6 to 13.5 V TA Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to ’1’). Table 3. Top Boot Block Addresses M29F100BT Table 4. Bottom Boot Block Addresses M29F100BB # Size (Kbyte s) Address Range (x8) Address Range (x16) # Size (Kbyte s) Address Range (x8) Address Range (x16) 4 16 1C000h-1FFFF h E000h-FFFFh 4 64 10000h-1FFFFh 8000h-FFFFh 3 8 1A000h-1BFFFh D000h-DFFFh 3 32 08000h-0FFFFh 4000h-7FFFh 2 8 18000h-19FFFh C000h-CFFFh 2 8 06000h-07FFFh 3000h-3FFFh 1 32 10000h-17FFFh 8000h-BFFFh 1 8 04000h-05FFFh 2000h-2FFFh 0 64 00000h-0FFFF h 0000h-7FFFh 0 16 00000h-03FFFh 0000h-1FFFh 3/22 M29F100BT, M29F100BB SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or 4/22 tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 17 and Figure 11, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure 11, Reset/Temporary Unprotect AC Characteristics. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC4. Vss Ground. The VSS Ground is the reference for all voltage measurements. M29F100BT, M29F100BB BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8, Read Mode AC Waveforms, and Table 14, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 15 and 16, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Table 5. Bus Operations, BYTE = VIL Operation E G Address Inputs DQ15A–1, A0-A15 W Data Inputs/Outpu ts DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL V IH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input X VIH V IH X Hi-Z Hi-Z Standby V IH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL V IH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z D0h (M29F100BT) D1h (M29F100BB) Address Inputs A0-A15 Output Disable Note: X = VIL or VIH. Table 6. Bus Operations, BYTE = VIH Operation Data Inputs/Outpu ts DQ15A–1, DQ14-DQ0 E G W Bus Read VIL VIL V IH Cell Address Bus Write VIL VIH VIL Command Address X VIH V IH X Hi-Z Standby V IH X X X Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL V IH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 00D0h (M29F100BT) 00D1h (M29F100BB) Output Disable Data Output Data Input Note: X = VIL or VIH. 5/22 M29F100BT, M29F100BB Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level. When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current, I CC2. To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 13, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 5 and 6, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash. COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write oper- 6/22 ations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on the configuration that is being used, for a summary of the commands. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F100BT is 00D0h and for the M29F100BB is 00D1h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A15 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. M29F100BT, M29F100BB Command Length Table 7. Commands, 16-bit mode, BYTE = VIH Bus Write Operations 1st 2nd Addr Data 1 X F0 3 555 Auto Select 3 Program 3rd 4th Addr Data Addr Data AA 2AA 55 X F0 555 AA 2AA 55 555 90 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 Block Erase 6+ 555 AA 2AA 55 555 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read/Reset 5th Addr Data PA PD 80 555 80 555 6th Addr Data Addr Data AA 2AA 55 555 10 AA 2AA 55 BA 30 Command Length Table 8. Commands, 8-bit mode, BYTE = VIL Bus Write Operations 1st 2nd Addr Data 1 X F0 3 AAA Auto Select 3 Program 3rd 4th Addr Data Addr Data AA 555 55 X F0 AAA AA 555 55 AAA 90 4 AAA AA 555 55 AAA A0 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA Block Erase 6+ AAA AA 555 55 AAA Erase Suspend 1 X B0 Erase Resume 1 X 30 Read/Reset 5th Addr Data PA PD 80 AAA 80 AAA 6th Addr Data Addr Data AA 555 55 AAA 10 AA 555 55 BA 30 Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A15, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until the Timeout Bit is set. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode. 7/22 M29F100BT, M29F100BB Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 9. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The 8/22 command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 9. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. M29F100BT, M29F100BB Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 9. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once. Table 9. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) Typ (1) Typical after 100k W/E Cycles (1) Chip Erase (All bits in the memory set to ‘0’) 0.6 0.6 Chip Erase 1.3 1.3 6 sec Block Erase (64 Kbytes) 0.6 0.6 4 sec Program (Byte or Word) 8 8 150 µs Chip Program (Byte by Byte) 1.2 1.2 4.5 sec Chip Program (Word by Word) 0.6 0.6 2.5 sec Parameter Program/Erase Cycles (per Block) Min 100,000 Max Unit sec cycles Note: 1. TA = 25°C, VCC = 5V. 9/22 M29F100BT, M29F100BB STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 10, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Ad- dress is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 5, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so may or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Table 10. Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Any Address DQ7 Toggle 0 – – 0 Program During Erase Suspend Any Address DQ7 Toggle 0 – – 0 Program Error Any Address DQ7 Toggle 1 – – 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before timeout Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 – Toggle 1 Block Erase Erase Suspend Non-Erasing Block Data read as normal 1 Good Block Address 0 Toggle 1 1 No Toggle 0 Faulty Block Address 0 Toggle 1 1 Toggle 0 Erase Error Note: Unspecified data bits should be ignored. 10/22 M29F100BT, M29F100BB Figure 4. Data Polling Flowchart Figure 5. Data Toggle Flowchart START START READ DQ5 & DQ6 READ DQ5 & DQ7 at VALID ADDRESS READ DQ6 DQ7 = DATA YES DQ6 = TOGGLE NO NO YES NO DQ5 =1 NO YES YES READ DQ7 at VALID ADDRESS DQ7 = DATA READ DQ6 TWICE YES DQ6 = TOGGLE NO FAIL DQ5 =1 NO YES PASS FAIL PASS AI01370B AI03598 Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. 11/22 M29F100BT, M29F100BB Table 11. AC Measurement Conditions M29F100B Parameter 45 70 / 90 / 120 High Speed Standard 30pF 100pF Input Rise and Fall Times ≤ 10ns ≤ 10ns Input Pulse Voltages 0 to 3V 0.45 to 2.4V 1.5V 0.8V and 2.0V AC Test Conditions Load Capacitance (CL) Input and Output Timing Ref. Voltages Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL = 30pF or 100pF 2.0V 0.8V 0.45V AI01275B CL includes JIG capacitance AI03027 Table 12. Capacitance (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 12/22 Test Condition Min Max Unit V IN = 0V 6 pF VOUT = 0V 12 pF M29F100BT, M29F100BB Table 13. DC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) Symbol Parameter Test Condition ILI Input Leakage Current ILO Typ (2) Min Max Unit 0V ≤ V IN ≤ VCC ±1 µA Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 20 mA ICC2 Supply Current (Standby) TTL 1 mA ICC3 Supply Current (Standby) CMOS E = VCC ±0.2V, RP = VCC ±0.2V 100 µA ICC4 (1) Supply Current (Program/Erase) Program/Erase Controller active 20 mA 6 E = VIH 30 VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2 VCC +0.5 V VOL Output Low Voltage 0.45 V Output High Voltage TTL IOH = –2.5mA 2.4 V Output High Voltage CMOS IOH = –100µA VCC –0.4 V VOH VID Identification Voltage IID Identification Current VLKO (1) IOL = 5.8mA Program/Erase Lockout Supply Voltage 11.5 A9 = VID 3.2 12.5 V 100 µA 4.2 V Note: 1. Sampled only, not 100% tested. 2. TA = 25°C, VCC = 5V. 13/22 M29F100BT, M29F100BB Table 14. Read AC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) M29F100B Symbol Alt Parameter Test Condition Unit 45 70 / 90 / 120 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 45 70 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 45 70 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 45 70 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 25 30 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 15 20 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 15 20 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 ns tELBL tELBH tELFL tELFH Chip Enable to BYTE Low or High Max 5 5 ns tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 15 20 ns tBHQV tFHQV BYTE High to Output Valid Max 30 30 ns Note: 1. Sampled only, not 100% tested. Figure 8. Read Mode AC Waveforms tAVAV A0-A15/ A–1 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGLQV tGHQZ DQ0-DQ7/ DQ8-DQ15 VALID tBHQV BYTE tELBL/tELBH 14/22 tBLQZ AI02919 M29F100BT, M29F100BB Table 15. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) M29F100B Symbol Alt Parameter Unit 45 70 / 90 / 120 tAVAV tWC Address Valid to Next Address Valid Min 45 70 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 40 45 ns tDVWH tDS Input Valid to Write Enable High Min 25 30 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 40 45 ns Output Enable High to Write Enable Low Min 0 0 ns tGHWL tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns t VCHEL tVCS V CC High to Chip Enable Low Min 50 50 µs Note: 1. Sampled only, not 100% tested. Figure 9. Write AC Waveforms, Write Enable Controlled tAVAV A0-A15/ A–1 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 tWHDX VALID VCC tVCHEL RB tWHRL AI01980B 15/22 M29F100BT, M29F100BB Table 16. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) M29F100B Symbol Alt Parameter Unit 45 70 / 90 / 120 tAVAV tWC Address Valid to Next Address Valid Min 45 70 ns t WLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 40 45 ns tDVEH tDS Input Valid to Chip Enable High Min 25 30 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 40 45 ns Output Enable High Chip Enable Low Min 0 0 ns t GHEL t EHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns tVCHWL tVCS V CC High to Write Enable Low Min 50 50 µs Note: 1. Sampled only, not 100% tested. Figure 10. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A15/ A–1 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 tEHDX VALID VCC tVCHWL RB tEHRL 16/22 AI01981B M29F100BT, M29F100BB Table 17. Reset/Block Temporary Unprotect AC Characteristics (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) M29F100B Symbol tPHWL (1) tPHEL Alt Parameter Unit 45 70 / 90 / 120 tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 50 50 ns tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 ns tPLPX tRP RP Pulse Width Min 500 500 ns tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns tPHGL (1) tRHWL (1) tRHEL (1) tRHGL (1) Note: 1. Sampled only, not 100% tested. Figure 11. Reset/Block Temporary Unprotect AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931 17/22 M29F100BT, M29F100BB Table 18. Ordering Information Scheme Example: M29F100BB 55 N 1 T Device Type M29 Operating Voltage F = VCC = 5V ± 10% Device Function 100B = 1 Mbit (128Kb x8 or 64Kb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 45 = 45 ns 70 = 70 ns 90 = 90 ns 120 = 120 ns Package N = TSOP48: 12 x 20 mm M = SO44 Temperature Range 1 = 0 to 70 °C 3 = –40 to 125 °C 6 = –40 to 85 °C Optio n T = Tape & Reel Packing Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 18/22 M29F100BT, M29F100BB Table 19. Revision History Date Revision Details July 1999 First Issue 07/28/00 New document template Document type: from Preliminary Data to Data Sheet Chip Erase Max. specification added (Table 9) Block Erase Max. specification added (Table 9) Program Max. specification added (Table 9) Chip Program Max. specification added (Table 9) ICC1 and ICC3 Typ. specification added (Table 13) ICC3 Test Condition change (Table 13) Status Register bit DQ5 clarification Data Polling Flowchart diagram change (Figure 4) Data Toggle Flowchart diagram change (Figure 5) 19/22 M29F100BT, M29F100BB Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data millimeters inches Symbol Typ Min Max A Typ Min 1.200 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413 B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 D 19.800 20.200 0.7795 0.7953 D1 18.300 18.500 0.7205 0.7283 – – – – E 11.900 12.100 0.4685 0.4764 L 0.500 0.700 0.0197 0.0276 α 0° 5° 0° 5° N 48 e 0.500 0.0197 48 CP 0.100 0.0039 Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a Drawing is not to scale. 20/22 Max A1 α L M29F100BT, M29F100BB Table 21. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data millimeters inches Symbol Typ Min Max A 2.420 A1 A2 Min Max 2.620 0.0953 0.1031 0.220 0.242 0.0087 0.0095 2.250 2.350 0.0886 0.0925 B Typ 0.500 0.0197 C 0.100 0.250 0.0039 0.0098 D 28.100 28.300 1.1063 1.1142 – – – – E 13.200 13.400 0.5197 0.5276 H 15.900 16.100 0.6260 0.6339 e 1.270 0.0500 L 0.800 – – 0.0315 – – α 3° – – 3° – – N 44 CP 44 0.100 0.0039 Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A2 A C B CP e D N E H 1 A1 α L SO-b Drawing is not to scale. 21/22 M29F100BT, M29F100BB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com 22/22