M29W160BT M29W160BB 16 Mbit (2Mb x8 or 1Mb x16, Boot Block) Low Voltage Single Supply Flash Memory PRELIMINARY DATA ■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ ACCESS TIME: 70ns ■ PROGRAMMING TIME 44 – 10µs per Byte/Word typical ■ 35 MEMORY BLOCKS – 1 Boot Block (Top or Bottom Location) – 2 Parameter and 32 Main Blocks ■ 1 TSOP48 (N) 12 x 20mm SO44 (M) PROGRAM/ERASE CONTROLLER FBGA – Embedded Byte/Word Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits LFBGA48 (ZA) 8 x 6 solder balls – Ready/Busy Output Pin ■ ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend ■ Figure 1. Logic Diagram UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming ■ TEMPORARY BLOCK UNPROTECTION MODE ■ SECURITY MEMORY BLOCK ■ LOW POWER CONSUMPTION – Standby and Automatic Standby ■ ■ ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK VCC 20 A0-A19 DQ0-DQ14 W 20 YEARS DATA RETENTION E – Defectivity below 1 ppm/year G ELECTRONIC SIGNATURE 15 DQ15A–1 M29W160BT M29W160BB BYTE RB RP – Manufacturer Code: 0020h – Top Device Code M29W160BT: 22C4h – Bottom Device Code M29W160BB: 2249h VSS AI00981 Note: RB not available on SO44 package. February 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/25 M29W160BT, M29W160BB Figure 2. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 A19 NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 Figure 3. SO Connections 48 12 M29W160BT 37 13 M29W160BB 36 24 25 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI02994 Table 1. Signal Names A0-A19 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output (Not available on SO44 package) BYTE Byte/Word Organization Select VCC Supply Voltage VSS Ground NC Not Connected Internally DU Don’t Use as internally connected 2/25 RP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29W160BT 34 12 M29W160BB 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23 AI00978 W A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC M29W160BT, M29W160BB Figure 4. LFBGA Connections (Top view through package) 1 2 3 F A13 A12 A14 E A9 A8 D W C 4 5 6 7 8 A15 A16 BYTE DQ15 A–1 VSS A10 A11 DQ7 DQ14 DQ13 DQ6 RP DU A19 DQ5 DQ12 VCC DQ4 RB DU A18 DU DQ2 DQ10 DQ11 DQ3 B A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A A3 A4 A2 A1 A0 E G VSS AI02985B 3/25 M29W160BT, M29W160BB Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage –0.6 to 4 V VCC Supply Voltage –0.6 to 4 V VID Identification Voltage –0.6 to 13.5 V TA Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. SUMMARY DESCRIPTION The M29W160B is a 16 Mbit (2Mb x8 or 1Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. 4/25 The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 (0.8mm pitch) packages and it is supplied with all the bits erased (set to ’1’). M29W160BT, M29W160BB Table 3. Top Boot Block Addresses, M29W160BT Table 4. Bottom Boot Block Addresses, M29W160BB # Size (Kbytes) Address Range (x8) Address Range (x16) # Size (Kbytes) Address Range (x8) Address Range (x16) 34 16 1FC000h-1FFFFFh FE000h-FFFFF h 34 64 1F0000h-1FFFFFh F8000h-FFFFFh 33 8 1FA000h-1FBFFFh FD000h-FDFFFh 33 64 1E0000h-1EFFFFh F0000h-F7FFFh 32 8 1F8000h-1F9FFFh FC000h-FCFFFh 32 64 1D0000h-1DFFFFh E8000h-EFFFFh 31 32 1F0000h-1F7FFFh F8000h-FBFFFh 31 64 1C0000h-1CFFFFh E0000h-E7FFFh 30 64 1E0000h-1EFFFFh F0000h-F7FFFh 30 64 1B0000h-1BFFFFh D8000h-DFFFF h 29 64 1D0000h-1DFFFFh E8000h-EFFFFh 29 64 1A0000h-1AFFFFh D0000h-D7FFFh 28 64 1C0000h-1CFFFFh E0000h-E7FFFh 28 64 190000h-19FFFFh C8000h-CFFFF h 27 64 1B0000h-1BFFFFh D8000h-DFFFFh 27 64 180000h-18FFFFh C0000h-C7FFFh 26 64 1A0000h-1AFFFFh D0000h-D7FFFh 26 64 170000h-17FFFFh B8000h-BFFFFh 25 64 190000h-19FFFFh C8000h-CFFFFh 25 64 160000h-16FFFFh B0000h-B7FFFh 24 64 180000h-18FFFFh C0000h-C7FFFh 24 64 150000h-15FFFFh A8000h-AFFFFh 23 64 170000h-17FFFFh B8000h-BFFFFh 23 64 140000h-14FFFFh A0000h-A7FFFh 22 64 160000h-16FFFFh B0000h-B7FFFh 22 64 130000h-13FFFFh 98000h-9FFFF h 21 64 150000h-15FFFFh A8000h-AFFFFh 21 64 120000h-12FFFFh 90000h-97FFFh 20 64 140000h-14FFFFh A0000h-A7FFFh 20 64 110000h-11FFFFh 88000h-8FFFF h 19 64 130000h-13FFFFh 98000h-9FFFFh 19 64 100000h-10FFFFh 80000h-87FFFh 18 64 120000h-12FFFFh 90000h-97FFFh 18 64 0F0000h-0FFFFFh 78000h-7FFFF h 17 64 110000h-11FFFFh 88000h-8FFFFh 17 64 0E0000h-0EFFFFh 70000h-77FFFh 16 64 100000h-10FFFFh 80000h-87FFFh 16 64 0D0000h-0DFFFFh 68000h-6FFFF h 15 64 0F0000h-0FFFFFh 78000h-7FFFFh 15 64 0C0000h-0CFFFFh 60000h-67FFFh 14 64 0E0000h-0EFFFFh 70000h-77FFFh 14 64 0B0000h-0BFFFFh 58000h-5FFFF h 13 64 0D0000h-0DFFFFh 68000h-6FFFFh 13 64 0A0000h-0AFFFFh 50000h-57FFFh 12 64 0C0000h-0CFFFFh 60000h-67FFFh 12 64 090000h-09FFFFh 48000h-4FFFF h 11 64 0B0000h-0BFFFFh 58000h-5FFFFh 11 64 080000h-08FFFFh 40000h-47FFFh 10 64 0A0000h-0AFFFFh 50000h-57FFFh 10 64 070000h-07FFFFh 38000h-3FFFF h 9 64 090000h-09FFFFh 48000h-4FFFFh 9 64 060000h-06FFFFh 30000h-37FFFh 8 64 080000h-08FFFFh 40000h-47FFFh 8 64 050000h-05FFFFh 28000h-2FFFF h 7 64 070000h-07FFFFh 38000h-3FFFFh 7 64 040000h-04FFFFh 20000h-27FFFh 6 64 060000h-06FFFFh 30000h-37FFFh 6 64 030000h-03FFFFh 18000h-1FFFF h 5 64 050000h-05FFFFh 28000h-2FFFFh 5 64 020000h-02FFFFh 10000h-17FFFh 4 64 040000h-04FFFFh 20000h-27FFFh 4 64 010000h-01FFFFh 08000h-0FFFF h 3 64 030000h-03FFFFh 18000h-1FFFFh 3 32 008000h-00FFFFh 04000h-07FFFh 2 64 020000h-02FFFFh 10000h-17FFFh 2 8 006000h-007FFFh 03000h-03FFFh 1 64 010000h-01FFFFh 08000h-0FFFFh 1 8 004000h-005FFFh 02000h-02FFFh 0 64 000000h-00FFFFh 00000h-07FFFh 0 16 000000h-003FFFh 00000h-01FFFh 5/25 M29W160BT, M29W160BB SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus 6/25 Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 18 and Figure 12, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 18 and Figure 12, Reset/Temporary Unprotect AC Characteristics. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC3. Vss Ground. The VSS Ground is the reference for all voltage measurements. M29W160BT, M29W160BB BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Read Mode AC Waveforms, and Table 15, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 10 and 11, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing requirements. Table 5. Bus Operations, BYTE = VIL Operation E G Address Inputs DQ15A–1, A0-A19 W Data Inpu ts/Outputs DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL V IH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input X VIH V IH X Hi-Z Hi-Z Standby V IH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL V IH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z C4h (M29W160BT) 49h (M29W160BB) Address Inputs A0-A19 Output Disable Note: X = VIL or VIH. Table 6. Bus Operations, BYTE = VIH Operation Data Inpu ts/Outputs DQ15A–1, DQ14-DQ0 E G W Bus Read VIL VIL V IH Cell Address Bus Write VIL VIH VIL Command Address X VIH V IH X Hi-Z Standby V IH X X X Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL V IH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 22C4h (M29W160BT) 2249h (M29W160BB) Output Disable Data Output Data Input Note: X = VIL or VIH. 7/25 M29W160BT, M29W160BB Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 5 and 6, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash. COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on the configuration that is being used, for a summary of the commands. 8/25 Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless stated otherwise (see Security Data command). It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29W160BT is 22C4h and for the M29W160BB is 2249h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 10. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. M29W160BT, M29W160BB Table 7. Commands, 16-bit mode, BYTE = VIH Read/Reset Auto Select Length Command Bus Write Operations Addr Data 1 X F0 1st 2nd 3rd Addr Data 4th Addr Data 3 555 AA 2AA 55 X F0 3 555 AA 2AA 55 555 90 5th Addr Data PA PD 6th Addr Data Addr Data Program 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Security Data 1 X B8 Table 8. Commands, 8-bit mode, BYTE = VIL Read/Reset Length Command Bus Write Operations Addr Data 1 X F0 1st 2nd 3rd Addr Data 4th Addr Data 5th Addr Data PA PD 6th Addr Data Addr Data 3 AAA AA 555 55 X F0 Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Security Data 1 X B8 Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until Timeout Bit is set. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode. Security Data. After the Security Data command read the Security Memory Block. Use an address outside the Security Memory Block when issuing the command. 9/25 M29W160BT, M29W160BB After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any com10/25 mand to abort the operation. Typical chip erase times are given in Table 10. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 10. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. M29W160BT, M29W160BB Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once. Security Data Command. The Security Data command can be used to read the Security Memory Block. The Security Memory Block is a block of 256 words that is usually undefined. Volume customers can request that a unique security code is pre-programmed by ST into each part. One Bus Write operation is required to issue the Security Data command. Once the Security Data command is issued Bus Read operations read from the Security Memory Block instead of the memory array, until another command is issued. After issuing the Security Data command from Auto Select mode a Read/Reset command will return to Auto Select mode. An invalid command will return to Read mode. Valid addresses for the Security Memory Block are given in Table 9, Security Memory Block Addresses. Although the address for the Security Data command is Don’t Care, it is necessary to choose an address outside the Security Memory Block for correct operation. Table 9. Security Memory Block Addresses Size (words) Address Range (x8) Address Range (x16) 256 000000h-0001FFh 000000h-0000FFh Table 10. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C or –40 to 85°C) Typ (1) Typical after 100k W/E Cycles (1) Chip Erase (All bits in the memory set to ‘0’) 10 10 Chip Erase 22 22 120 sec Block Erase (64 Kbytes) 0.8 0.8 6 sec Program (Byte or Word) 10 10 200 µs Chip Program (Byte by Byte) 22 22 120 sec Chip Program (Word by Word) 11 11 60 sec Parameter Program/Erase Cycles (per Block) Min 100,000 Max Unit sec cycles Note: 1. TA = 25°C, VCC = 3.3V. 11/25 M29W160BT, M29W160BB STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 11, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 5, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 6, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so may or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Table 11. Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Any Address DQ7 Toggle 0 – – 0 Program During Erase Suspend Any Address DQ7 Toggle 0 – – 0 Program Error Any Address DQ7 Toggle 1 – – 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before timeout Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 – Toggle 1 Block Erase Erase Suspend Non-Erasing Block Data read as normal 1 Good Block Address 0 Toggle 1 1 No Toggle 0 Faulty Block Address 0 Toggle 1 1 Toggle 0 Erase Error Note: Unspecified data bits should be ignored. 12/25 M29W160BT, M29W160BB Figure 5. Data Polling Flowchart Figure 6. Data Toggle Flowchart START START READ DQ5 & DQ6 READ DQ5 & DQ7 at VALID ADDRESS READ DQ6 DQ7 = DATA YES DQ6 = TOGGLE NO NO NO YES DQ5 =1 NO YES READ DQ7 at VALID ADDRESS DQ5 =1 YES READ DQ6 TWICE DQ7 = DATA YES DQ6 = TOGGLE NO FAIL PASS AI03598 NO YES FAIL PASS AI01370B Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. 13/25 M29W160BT, M29W160BB Table 12. AC Measurement Conditions M29W160B Parameter 70 90 120 3.0 to 3.6V 2.7 to 3.6V 2.7 to 3.6V 30pF 30pF 100pF Input Rise and Fall Times ≤ 10ns ≤ 10ns ≤ 10ns Input Pulse Voltages 0 to 3V 0 to 3V 0 to 3V 1.5V 1.5V 1.5V VCC Supply Voltage Load Capacitance (CL) Input and Output Timing Ref. Voltages Figure 7. AC Testing Input Output Waveform Figure 8. AC Testing Load Circuit 0.8V 1N914 3V 1.5V 0V 3.3kΩ AI01417 DEVICE UNDER TEST OUT CL = 30pF or 100pF CL includes JIG capacitance AI02762 Table 13. Capacitance (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 14/25 Test Condition Min Max Unit V IN = 0V 6 pF VOUT = 0V 12 pF M29W160BT, M29W160BB Table 14. DC Characteristics (TA = 0 to 70°C or –40 to 85°C) Symbol Parameter Test Condition ILI Input Leakage Current ILO Typ (2) Max Unit 0V ≤ VIN ≤ VCC ±1 µA Output Leakage Current 0V ≤ VOUT ≤ V CC ±1 µA ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 5 10 mA ICC2 Supply Current (Standby) E = VCC ± 0.2V, RP = VCC ± 0.2V 35 100 µA Supply Current (Program/Erase) Program/Erase Controller active 20 mA ICC3 (1) Min V IL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7V CC VCC + 0.3 V VOL Output Low Voltage IOL = 1.8mA 0.45 V VOH Output High Voltage IOH = –100µA VID Identification Voltage IID Identification Current V LKO (1) Program/Erase Lockout Supply Voltage VCC – 0.4 11.5 A9 = VID 1.8 V 12.5 V 100 µA 2.3 V Note: 1. Sampled only, not 100% tested. 2. TA = 25°C, VCC = 3.3V. 15/25 M29W160BT, M29W160BB Table 15. Read AC Characteristics (TA = 0 to 70°C or –40 to 85°C) M29W160B Symbol Alt Parameter Test Condit ion Unit 70 90 120 tAVAV tRC Address Valid to Next Address Valid E = VIL , G = VIL Min 70 90 120 ns tAVQV tACC Address Valid to Output Valid E = VIL , G = VIL Max 70 90 120 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 120 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 50 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 30 30 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 30 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 0 ns tELBL tELBH tELFL tELFH Chip Enable to BYTE Low or High Max 5 5 5 ns tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 30 ns tBHQV tFHQV BYTE High to Output Valid Max 30 40 40 ns Note: 1. Sampled only, not 100% tested. Figure 9. Read Mode AC Waveforms tAVAV A0-A19/ A–1 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGLQV tGHQZ DQ0-DQ7/ DQ8-DQ15 VALID tBHQV BYTE tELBL/tELBH 16/25 tBLQZ AI02922 M29W160BT, M29W160BB Table 16. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C or –40 to 85°C) M29W160B Symbol Alt Parameter Unit 70 90 120 tAVAV tWC Address Valid to Next Address Valid Min 70 90 120 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 50 50 ns tDVWH tDS Input Valid to Write Enable High Min 45 50 50 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 30 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 50 50 ns Output Enable High to Write Enable Low Min 0 0 0 ns tGHWL tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 50 ns t VCHEL tVCS V CC High to Chip Enable Low Min 50 50 50 µs Note: 1. Sampled only, not 100% tested. Figure 10. Write AC Waveforms, Write Enable Controlled tAVAV A0-A19/ A–1 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 tWHDX VALID VCC tVCHEL RB tWHRL AI02923 17/25 M29W160BT, M29W160BB Table 17. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C or –40 to 85°C) M29W160B Symbol Alt Parameter Unit 70 90 120 tAVAV tWC Address Valid to Next Address Valid Min 70 90 120 ns t WLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns tELEH tCPH Chip Enable High to Chip Enable High Min 45 50 50 ns tDVEH tDS Input Valid to Chip Enable High Min 45 50 50 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns tEHEL tCP Chip Enable Low to Chip Enable Low Min 30 30 30 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 50 50 ns Output Enable High Chip Enable Low Min 0 0 0 ns t GHEL t EHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns t EHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 50 ns tVCHWL tVCS V CC High to Write Enable Low Min 50 50 50 µs Note: 1. Sampled only, not 100% tested. Figure 11. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A19/ A–1 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 tEHDX VALID VCC tVCHWL RB tEHRL 18/25 AI02924 M29W160BT, M29W160BB Table 18. Reset/Block Temporary Unprotect AC Characteristics (TA = 0 to 70°C or –40 to 85°C) M29W160B Symbol Alt tPHWL (1) tPHEL Parameter Unit 70 90 120 tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 50 50 50 ns tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 0 ns tPLPX tRP RP Pulse Width Min 500 500 500 ns tPLYH (1) tREADY RP Low to Read Mode Max 10 10 10 µs tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 500 ns tPHGL (1) tRHWL (1) tRHEL (1) tRHGL (1) Note: 1. Sampled only, not 100% tested. Figure 12. Reset/Block Temporary Unprotect AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931 19/25 M29W160BT, M29W160BB Table 19. Ordering Information Scheme Example: M29W160BB 90 N 1 T Device Type M29 Operating Voltage W = VCC = 2.7 to 3.6V Device Function 160B = 16 Mbit (2Mb x8 or 1Mb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns 90 = 90 ns 120 = 120 ns Package N = TSOP48: 12 x 20 mm M = SO44 ZA = LFBGA48: 0.80mm pitch Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Optio n T = Tape & Reel Packing Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 20/25 M29W160BT, M29W160BB Table 20. Revision History Date Revision Details July 1999 First Issue 10/08/99 FBGA Connections change (Table 1, Figure 4) Chip Erase Max. specification added (Table 10) Block Erase Max. specification added (Table 10) Program Max. specification added (Table 10) Chip Program Max. specification added (Table 10) ICC1, ICC2 Typ. specification added (Table 14) ICC2 Test Condition change (Table 14) ICC2 Max. specification change (Table 14) tWLWH, 90ns speed, change (Table 16) tDVWH, 70 and 90ns speed, change (Table 16) tWLAX, 90ns speed, change (Table 16) tELEH, 90ns speed, change (Table 17) tDVEH, 70 and 90ns speed, change (Table 17) tELAX, 90ns speed, change (Table 17.) 10/27/99 Device Code in Auto Select Program, corrected 02/09/00 Security Data Command change (Table 7, 8) Status Register bit DQ5 clarification Data Polling Flowchart diagram change (Figure 5) Data Toggle Flowchart diagram change (Figure 6) LFBGA Package Mechanical Data change (Table 23) LFBGA Package Outline drawing change (Figure 15) 21/25 M29W160BT, M29W160BB Table 21. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data mm Symbol Typ inches Min Max A Typ Min 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 11.90 12.10 0.4685 0.4764 – – – – L 0.50 0.70 0.0197 0.0276 α 0° 5° 0° 5° N 48 E e 0.50 0.0197 48 CP 0.10 0.0039 Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a Drawing is not to scale. 22/25 Max A1 α L M29W160BT, M29W160BB Table 22. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data mm inches Symbol Typ Min Max A 2.42 A1 A2 Min Max 2.62 0.0953 0.1031 0.22 0.23 0.0087 0.0091 2.25 2.35 0.0886 0.0925 B Typ 0.50 0.0197 C 0.10 0.25 0.0039 0.0098 D 28.10 28.30 1.1063 1.1142 E 13.20 13.40 0.5197 0.5276 – – – – 15.90 16.10 0.6260 0.6339 e 1.27 H 0.0500 L 0.80 – – 0.0315 – – α 3° – – 3° – – N 44 CP 44 0.10 0.0039 Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A2 A C B CP e D N E H 1 A1 α L SO-b Drawing is not to scale. 23/25 M29W160BT, M29W160BB Table 23. LFBGA48 - 8 x 6 balls, 0.80mm pitch, Package Mechanical Data mm inch Symbol Typ Min Max A Typ Min Max 1.350 A1 0.300 0.200 0.350 A2 0.750 b 0.0531 0.0118 0.0079 0.0138 1.000 0.0295 0.0394 0.300 0.550 0.0118 0.0217 D 9.000 8.800 9.200 0.3543 0.3465 0.3622 D1 5.600 – – 0.2205 – – ddd 0.150 0.0059 e 0.800 – – 0.0315 – – E 8.000 7.800 8.200 0.3150 0.3071 0.3228 E1 4.000 – – 0.1575 – – FD 1.700 – – 0.0669 – – FE 2.000 – – 0.0787 – – SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – – Figure 15. LFBGA48 - 8 x 6 balls, 0.80 mm pitch, Bottom View Package Outline D D1 FD FE SD SE E E1 ddd A e b A2 A1 BGA-Z00 Drawing is not to scale. 24/25 M29W160BT, M29W160BB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. 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