128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L PRELIMINARY (4-BANK x 2,097,152-WORD x 16-BIT) Some of contents are described for general products and are subject to change without notice. DESCRIPTION M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems. FEATURES M2V28S20/30/40ATP ITEM -6 tCLK Clock Cycle Time tRAS Active to Precharge Command Period (Min.) tRCD Row to Column Delay (Min.) tAC Access Time from CLK Ref/Active Command Period (Max.) (CL=3) (Min.) tRC Icc1 Icc6 Operation Current Self Refresh Current (Min.) 7.5ns (Max.) (Single Bank) -7 10ns -8 10ns 45ns 50ns 50ns 20ns 20ns 6ns 20ns 6ns 70ns 70ns 5.4ns 67.5ns V28S20 100mA 95mA 95mA V28S30 110mA 100mA 100mA V28S40 130mA 120mA 120mA 2mA 2mA 2mA (Max.) - Single 3.3V ±0.3V power supply - Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQML and DQMU (M2V28S40ATP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 4096 refresh cycles /64ms - LVTTL Interface - Package M2V28S20ATP/30ATP/40ATP 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch MITSUBISHI ELECTRIC 1 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) PIN CONFIGURATION (TOP VIEW) M2V28S20ATP M2V28S30ATP M2V28S40ATP PIN CONFIGURATION (TOP VIEW) Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss CLK : Master Clock DQM : Output Disable/ Write Mask CKE /CS : Clock Enable : Chip Select A0-11 : Address Input /RAS : Row Address Strobe BA0,1 Vdd : Bank Address : Power Supply VddQ Vss : Power Supply for Output : Ground VssQ : Ground for Output /CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O MITSUBISHI ELECTRIC 2 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) BLOCK DIAGRAM DQ0-7 I/O Buffer Memory Array Memory Array Memory Array Memory Array 4096 x1024 x8 Cell Array 4096 x1024 x8 Cell Array 4096 x1024 x8 Cell Array 4096 x1024 x8 Cell Array Bank #0 Bank #1 Bank #2 Bank #3 Mode Register Control Circuitry Address Buffer Control Signal Buffer Clock Buffer A0-11 BA0,1 CLK /CS CKE /RAS /CAS /WE DQM Note : This figure shows the M2V28S30ATP. The M2V28S20ATP configration is 4096x2048x4 of cell array and DQ 0-3. The M2V28S40ATP configration is 4096x512x16 of cell array and DQ 0-15. Type Designation Code These rules are only applied to the Synchronous DRAM family. M2 V 28 S 3 0 A TP -8 Access Item Package Type -6 : 7.5ns (PC133/3-3-3), -7 : 10ns(PC100/2-2-2), -8 : 10ns(PC100/3-2-2) TP : TSOP(II) Process Generation A : 2nd. gen. Function 0 : Random Column Organization 2: x4, 3: x8, 4: x16 Synchronous DRAM Density 28 : 128Mbit Interface V : LVTTL Mitsubishi DRAM MITSUBISHI ELECTRIC 3 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) PIN FUNCTION Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / selfrefresh. After self refresh mode is started, CKE becomes synchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1 Input Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. DQ0-7 Input / Output CLK A0-11 Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. DQM Input Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. MITSUBISHI ELECTRIC 4 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) BASIC FUNCTIONS The M2V28S30ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. CLK /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Refresh Option @ refresh command A10 Precharge Option @ precharge or read/write command define basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MITSUBISHI ELECTRIC 5 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) COMMAND TRUTH TABLE CKE CKE n-1 n COMMAND MNEMONIC Deselect DESEL H X H X X X X No Operation NOP H X L H H H Row Address Entry & Bank Activate ACT H X L L H Single Bank Precharge PRE H X L L PREA H X L WRITE H X WRITEA H Column Address Entry & Read READ Column Address Entry & Read with Auto-Precharge A10 A0-9 X X X X X X X H V V V V H L V X L X L H L X X H X L H L L V V L V X L H L L V V H V H X L H L H V V L V READA H X L H L H V V H V Auto-Refresh REFA H H L L L H X X X X Self-Refresh Entry REFS H L L L L H X X X X L H H X X X X X X X L H L H H H X X X X H X L L L L L L L V*1 Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Self-Refresh Exit Mode Register Set /CS /RAS /CAS /WE BA0,1 A11 REFSX MRS H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address MITSUBISHI ELECTRIC 6 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE Current State /CS IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA NOP*4 L L L H X REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVE /RAS /CAS /WE Address Command READ / READA WRITE / WRITEA Action Bank Active, Latch RA Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge MITSUBISHI ELECTRIC 7 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE (continued) Current State /CS READ H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst L H L H BA, CA, A10 READ /READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge*3 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE /RAS /CAS /WE Address Command READ / READA WRITE / WRITEA Action Bank Active / ILLEGAL*2 Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 MITSUBISHI ELECTRIC 8 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE (continued) Current State READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE /CS /RAS /CAS /WE Address Command Action H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ / READA WRITE / WRITEA READ / READA WRITE / WRITEA ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 MITSUBISHI ELECTRIC 9 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE (continued) Current State PRE CHARGING ROW ACTIVATING /CS /RAS /CAS /WE Address Command Action H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Row Active after tRCD) L H H H X NOP NOP (Row Active after tRCD) L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MITSUBISHI ELECTRIC 10 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE (continued) Current State WRITE RECOVERING REFRESHING /CS /RAS /CAS /WE Address Command Action H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after tRC) L H H H X NOP NOP (Idle after tRC) L H H L BA TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MITSUBISHI ELECTRIC 11 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE (continued) Current State MODE REGISTER SETTING /CS /RAS /CAS /WE Address Command Action H X X X X DESEL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L BA L H L X BA, CA, A10 L L H H L L H L L L L TBST ILLEGAL READ / WRITE ILLEGAL BA, RA ACT ILLEGAL L BA, A10 PRE / PREA ILLEGAL L H X REFA ILLEGAL L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. MITSUBISHI ELECTRIC 12 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) FUNCTION TRUTH TABLE for CKE Current State SELFREFRESH*1 POWER DOWN ALL BANKS IDLE*2 ANY STATE other than listed above CKE n-1 CKE n /CS H X X X L H H L H L /RAS /CAS /WE Add Action X X X INVALID X X X X Exit Self-Refresh (Idle after tRC) L H H H X Exit Self-Refresh (Idle after tRC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. MITSUBISHI ELECTRIC 13 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFSX MODE REGISTER SET MRS REFA IDLE AUTO REFRESH CKEL CLK SUSPEND CKEH ACT POWER DOWN CKEL CKEH ROW ACTIVE WRITE WRITE SUSPEND READ WRITEA CKEL READA READ WRITE WRITE CKEH READA WRITEA POWER APPLIED READ SUSPEND CKEH WRITEA WRITEA SUSPEND CKEL READ READA CKEL CKEL WRITEA PRE CKEH CKEH POWER ON READA PRE PRE READA SUSPEND PRE PRE CHARGE Automatic Sequence Command Sequence MITSUBISHI ELECTRIC 14 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. CLK /CS /RAS /CAS /WE V BA0,1 A11-A0 BA0 BA1 A11 A10 A9 0 0 CL LATENCY MODE 0 0 A8 0 A7 A6 0 0 /CAS LATENCY 000 001 R R 010 011 100 101 110 111 2 3 R R R R A5 A4 A3 LTMODE A2 BT A1 A0 BL BURST LENGTH BURST TYPE BL BT= 0 BT= 1 000 001 010 011 100 1 2 4 8 R 1 2 4 8 R 101 110 111 R R FP R R R 0 1 SEQUENTIAL INTERLEAVED R: Reserved for Future Use MITSUBISHI ELECTRIC 15 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) CLK Command Read Write Address Y Y Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 Q3 D0 Burst Length D1 D2 D3 Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 Sequential Interleaved 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 MITSUBISHI ELECTRIC 16 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC , although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=4, CL=3) CLK 2 ACT command / tRCmin tRCmin Command ACT ACT READ tRRD A0-9 Xa PRE ACT tRAS Xb Y 0 tRP Xb tRCD A10 Xa Xb A11 Xa Xb BA0,1 00 01 DQ 1 Xb Xb 00 01 Qa0 Qa1 Qa2 Qa3 Precharge all READ After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) , and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. (Need to keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA. MITSUBISHI ELECTRIC 17 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Multi Bank Interleaving READ (BL=4, CL=3) CLK Command ACT READ ACT READ PRE tRCD A0-9 Xa Y Xb Y A10 Xa 0 Xb 0 0 A11 Xa BA0,1 00 10 00 Qa1 Qa2 Xb 00 10 DQ Qa0 /CAS latency Qa3 Qb0 Qb1 Qb2 Burst Length READ with Auto-Precharge (BL=4, CL=3) CLK BL + tRP Command ACT A0-9 Xa Y Xa A10 Xa 1 Xa A11 Xa BA0,1 00 READ tRCD ACT BL tRP Xa 00 00 Qa0 DQ Qa1 Qa2 Qa3 Internal precharge start READ Auto-Precharge Timing (BL=4) CLK Command ACT READ BL CL=3 DQ CL=2 DQ Qa0 Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa3 Internal Precharge Start Timing MITSUBISHI ELECTRIC 18 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. (Need to keep tRAS min.) The next ACT command can be issued after tRP from the internal precharge timing. Multi Bank Interleaving WRITE (BL=4) CLK Command ACT Write ACT A0-9 Xa Y Xb Y A10 Xa Xa 0 Xb 0 A11 Xa Xa BA0,1 00 tRCD Write PRE PRE 0 0 0 0 10 00 10 Db0 Db1 tRCD Xb DQ 00 10 Da0 Da1 Da2 Da3 Db2 Db3 WRITE with Auto-Precharge (BL=4) CLK Command ACT Write ACT A0-9 Xa Y Xa A10 Xa 1 Xa A11 Xa BA0,1 00 tRCD DQ tWR tRP Xa 00 Da0 00 Da1 Da2 Da3 Internal precharge starts MITSUBISHI ELECTRIC 19 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK.. Read Interrupted by Read (BL=4, CL=3) CLK Command READ READ READ READ A0-9 Yi Yj Yk Yl A10 0 0 0 0 00 00 10 01 A11 BA0,1 Qai0 DQ Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3) CLK Command READ Write A0-9 Yi Yj A10 0 0 00 00 A11 BA0,1 DQM Q D Qai0 Daj0 DQM control Daj1 Daj2 Daj3 Write control MITSUBISHI ELECTRIC 20 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4) CLK Command PRE READ DQ Command CL=3 READ CL=2 READ DQ PRE Q0 READ Q1 Q2 PRE Q0 DQ Command Q1 Q0 DQ Command Q0 Q2 READ PRE DQ Command Q1 PRE DQ Command Q0 Q1 READ PRE Q0 MITSUBISHI ELECTRIC 21 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4) CLK Command Write Write Write Write A0-9 Yi Yj Yk Yl A10 0 0 0 0 BA0,1 00 00 10 00 DQ Dai0 A11 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3) CLK Command Write READ Write READ A0-9 Yi Yj Yk Yl A10 0 0 0 0 00 00 10 00 A11 BA0,1 DQM DQ Dai0 Qaj0 Qaj1 Dbk0 Dbk1 MITSUBISHI ELECTRIC Qal0 22 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Write recovery time (tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4) CLK Command Write A0-9 Yi A10 0 PRE tWR tRP Xb 0 Xb Xb A11 BA0,1 ACT 00 00 00 DQM DQ Dai0 Dai1 Dai2 MITSUBISHI ELECTRIC 23 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command. Auto-Refresh CLK /CS NOP or DESELECT /RAS /CAS /WE CKE minimum tRC A0-11 BA0,1 Auto Refresh on All Banks Auto Refresh on All Banks MITSUBISHI ELECTRIC 24 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh CLK Stable CLK /CS NOP /RAS /CAS /WE CKE tSRX new command A0-11 X BA0,1 00 Self Refresh Entry Self Refresh Exit MITSUBISHI ELECTRIC minimum tRC +1 CLOCK for recovery 25 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext.CLK CKE int.CLK Power Down by CKE CLK Standby Power Down CKE Command PRE NOP NOP NOP NOP Active Power Down CKE Command NOP NOP NOP ACT NOP NOP NOP NOP NOP NOP NOP DQ Suspend by CKE CLK CKE Command Write DQ D0 READ D1 D2 D3 Q0 MITSUBISHI ELECTRIC Q1 Q2 Q3 26 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) DQM CONTROL DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to write mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2. DQM Function CLK Command Write READ DQM DQ D0 D2 D3 masked by DQM=H MITSUBISHI ELECTRIC Q0 Q1 Q3 disabled by DQM=H 27 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Supply Voltage with respect to Vss -0.5 - 4.6 V Supply Voltage for Output with respect to VssQ -0.5 - 4.6 V VI Input Voltage with respect to Vss -0.5 - 4.6 V VO Output Voltage with respect to VssQ -0.5 - 4.6 V IO Output Current Pd Power Dissipation Vdd VddQ Ta = 25ºC Unit 50 mA 1000 mW Topr Operating Temperature 0 - 70 ºC Tstg Storage Temperature -65 - 150 ºC RECOMMENDED OPERATING CONDITIONS (Ta=0 – 70ºC, unless otherwise noted ) Symbol Limits Parameter Unit Min. Typ. Max. Vdd Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VddQ Supply Voltage for Output 3.0 3.3 3.6 V VssQ Supply Voltage for Output 0 0 0 V VIH*1 High-level Input Voltage all inputs 2.0 VddQ +0.3 V VIL*2 Low-level Input Voltage all inputs -0.3 0.8 V NOTES) 1. VIH(max)=5.5V for pulse width less than 10ns. 2. VIL(min)=-1.0V for pulse width less than 10ns. CAPACITANCE (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Symbol Test Condition Parameter CI(A) Input Capacitance, address pin CI(C) Input Capacitance, contorl pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin @ 1MHz 1.4V bias 200mV swing Vcc=3.3V Limits (min.) Limits (max.) -6 (PC133) -7/-8(PC100) Unit 2.5 3.8 5.0 pF 2.5 3.8 5.0 pF 2.5 3.5 4.0 pF 4.0 6.5 6.5 pF MITSUBISHI ELECTRIC 28 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) AVERAGE SUPPLY CURRENT from Vdd (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) ITEM Organization Symbol -8 x4 100 95 95 110 100 100 x16 130 120 120 Icc2N x4/x8/x16 25 25 Icc2NS x4/x8/x16 15 tCLK = 15ns CKE = L Icc2P x4/x8/x16 CLK = L CKE = L Icc2PS CKE = H, tCLK=15ns CKE = H, CLK=L single bank operation Icc1 tCLK = 15ns CKE = H VIH > Vcc - 0.2V VIL < 0.2V precharge standby current in Non Power down mode CLK = L & CKE = H VIH > Vcc - 0.2V VIL < 0.2V all input signals are fixed. /CS > Vcc -0.2V precharge standby current in Power down mode /CS > Vcc -0.2V mA *1 25 mA *1 15 15 mA *1 2 2 2 mA *1 x4/x8/x16 1 1 1 mA *1 Icc3N x4/x8/x16 30 30 30 mA *1 Icc3NS x4/x8/x16 20 20 20 x4 140 110 110 x8 150 120 120 mA *1 x16 160 130 130 160 160 160 mA *1 active standby current burst current Unit Note -7 x8 operating current tRC=min, tCLK =min, BL=1 , CL=3 Limits (max.) -6 All Bank Active tCLK = min BL=4, CL=3 Icc4 auto-refresh current tRC=min, tCLK=min Icc5 x4/x8/x16 self-refresh current CKE < 0.2V Icc6 x4/x8/x16 2 2 2 mA *1 0.8 0.8 0.8 mA *1,2 NOTE) 1. Icc(max) is specified at the output open condition. 2. Low Power version. (-6L,-7L,-8L only) AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Symbol Parameter Limits Test Conditions Min. VOH (DC) High-Level Output Voltage (DC) IOH=-2mA VOL (DC) Low-level Output Voltage (DC) IOL= 2mA IOZ Off-state Output Current Q floating VO=0 -- VddQ II Input Current VIH = 0 -- VddQ +0.3V MITSUBISHI ELECTRIC unit Max. V 2.4 0.4 V -10 10 µA -10 10 µA 29 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) AC TIMING REQUIREMENTS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Input Pulse Levels: 0.8V – 2.0V Input Timing Measurement Level: 1.4V Limits Symbol -6 Parameter Min. tCLK CLK cycle time -7 Max. Min. Unit -8 Max. Min. Max. CL=2 10 10 13 ns CL=3 7.5 10 10 ns tCH CLK High pulse width 2.5 3 3 ns tCL CLK Low pulse width 2.5 3 3 ns Transition time of CLK 1 tT 10 10 1 1 10 ns tIS Input Setup time (all inputs) 1.5 2 2 ns tIH Input Hold time (all inputs) 0.8 1 1 ns tRC Row Cycle time 67.5 70 70 ns 20 20 ns tRCD Row to Column Delay 20 tRAS Row Active time 45 100K 100K 50 50 100K ns tRP Row Precharge time 20 20 20 ns tWR Write Recovery time 15 20 20 ns tRRD Act to Act Delay time 15 20 20 ns tRSC Mode Register Set Cycle time 15 20 20 ns tSRX Self-refresh Exit time 7.5 10 10 ns tPDE Power Down Exit time 7.5 10 10 ns tREF Refresh Interval time 64 CLK 1.4V DQ 1.4V 64 64 ms Any AC timing is referenced to the input signal passing through 1.4V. MITSUBISHI ELECTRIC 30 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) SWITCHING CHARACTERISTICS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Limits Symbol Parameter -6 Min. tAC tOH Access time from CLK Output Hold time from CLK -8 -7 Max. Max. Min. Min. Unit Note Max. CL=2 6 6 7 ns CL=3 5.4 6 6 ns CL=2 CL=3 3 3 3 ns 2.7 3 3 ns 0 0 ns tOLZ Delay time, output lowimpedance from CLK 0 tOHZ Delay time, output highimpedance from CLK 2.7 5.4 3 6 3 6 *1 ns NOTE) 1. If clock rising time is longer than 1ns, (tr /2–0.5ns) should be added to the parameter. Output Load Condition CLK VOUT 1.4V 50pF DQ 1.4V Output Timing Measurement Reference Point CLK 1.4V tOLZ DQ 1.4V tAC tOH tOHZ MITSUBISHI ELECTRIC 31 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Burst Write (single bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQM A0-8 X Y A10 X X A9,11 X X BA0,1 0 0 D0 DQ ACT#0 X 0 D0 WRITE#0 D0 0 D0 Y 0 D0 PRE#0 ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 32 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-8 X X A10 X A9,11 BA0,1 X X X X X X X X X 0 1 DQ Y 0 D0 ACT#0 Y D0 WRITE#0 ACT#1 D0 D0 1 0 D1 D1 0 D1 PRE#0 WRITE#1 D1 1 2 Y 0 D0 ACT#0 D0 D0 D0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 33 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Burst Read (single bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-8 X A10 X X A9,11 X X BA0,1 0 Y X 0 0 0 Y 0 CL=3 Q0 DQ ACT#0 READ#0 Q0 Q0 PRE#0 Q0 Q0 ACT#0 Q0 READ#0 READ to PRE ³BL allows full data out Italic parameter indicates minimum case MITSUBISHI ELECTRIC 34 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Burst Read (multiple bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-8 X X A10 X A9,11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 Q0 Q0 CL=3 DQ READ#0 ACT#1 1 2 Q1 Q1 Q1 0 CL=3 Q0 ACT#0 0 Y Q0 PRE#0 READ#1 Q1 ACT#0 PRE#1 Q0 READ#0 ACT#2 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 35 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Burst Write (multi bank) with Auto-Precharge @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL-1+ tWR + tRP BL-1+ tWR + tRP /WE CKE DQM A0-8 X X A10 X X X X A9,11 X X X X BA0,1 0 1 Y 0 D0 DQ ACT#0 ACT#1 Y X 1 D0 D0 WRITE#0 with AutoPrecharge D0 D1 D1 D1 Y X 0 0 1 D1 D0 D0 ACT#0 WRITE#1 with AutoPrecharge Y 1 D0 D0 D1 WRITE#0 ACT#1 WRITE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 36 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL+tRP BL+tRP /WE CKE DQM DQM read latency =2 A0-8 X X Y Y A10 X X X X A9,11 X X X X BA0,1 0 1 0 1 CL=3 DQ Y 0 0 CL=3 Q0 ACT#0 ACT#1 X READ#0 with Auto-Precharge Q0 Q0 X Y 1 1 CL=3 Q0 Q1 Q1 ACT#0 READ#1 with Auto-Precharge Q1 Q1 Q0 Q0 READ#0 ACT#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 37 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Page Mode Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X X A10 X X A9,11 X X BA0,1 0 1 DQ Y Y Y Y 0 0 1 0 D0 ACT#0 D0 WRITE#0 ACT#1 D0 D0 D0 D0 D0 D0 D1 D1 WRITE#0 D1 D1 D0 D0 D0 WRITE#0 WRITE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 38 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Page Mode Burst Read (multi bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-8 X X A10 X X A9,11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 CL=3 DQ CL=3 Q0 ACT#0 READ#0 ACT#1 Q0 Q0 Q0 CL=3 Q0 Q0 Q0 READ#0 Q0 Q1 Q1 Q1 Q1 READ#0 READ#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 39 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Write Interrupted by Write / Read @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQM A0-8 X X A10 X X A9,11 X X BA0,1 0 1 Y Y Y Y Y 0 0 0 1 0 D0 D0 CL=3 D0 DQ ACT#0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 40 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Read Interrupted by Read / Write @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-8 X X A10 X X A9,11 X X BA0,1 0 1 DQ ACT#0 Y Y Y Y Y Y 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 D0 READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 41 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Write Interrupted by Precharge @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 X X Y A10 X X X A9,11 X X X BA0,1 0 1 0 D0 DQ ACT#0 Y D0 WRITE#0 ACT#1 D0 D0 X 1 0 D1 D1 1 1 1 D1 PRE#0 WRITE#1 PRE#1 Burst Write is not interrupted by Precharge of the other bank. Y ACT#1 D1 D1 WRITE#1 Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 42 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Read Interrupted by Precharge @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRP tRRD /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency=2 A0-8 X X Y Y A10 X X X A9,11 X X X BA0,1 0 1 0 Q0 DQ ACT#0 READ#0 ACT#1 X 1 0 1 Q0 Q0 Q0 1 Q1 1 Q1 PRE#0 READ#1 PRE#1 Burst Read is not interrupted by Precharge of the other bank. Y ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 43 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Mode Register Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRSC tRC /RAS tRCD /CAS /WE CKE DQM M A0-8 X A10 X A9,11 X 0 BA0,1 0 Y 0 D0 DQ Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 44 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Auto-Refresh @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRC /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 Y 0 DQ D0 D0 D0 Auto-Refresh ACT#0 Before Auto-Refresh, all banks must be idle state. After tRC from Auto-Refresh, all banks are idle state. D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 45 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Self-Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CLK can be stopped tRC /CS /RAS /CAS /WE tSRX CKE CKE must be low to maintain Self-Refresh DQM X A0-8 X A10 X A9,11 0 BA0,1 DQ Self-Refresh Entry Self-Refresh Exit Before Self-Refresh Entry, all banks must be idle state. ACT#0 After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 46 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) DQM Write Mask @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 Y Y Y 0 0 0 masked masked D0 DQ ACT#0 D0 WRITE#0 D0 D0 D0 WRITE#0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 47 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) DQM Read Mask @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=2 DQM A0-8 X A10 X A9,11 X BA0,1 0 Y Y Y 0 0 0 masked Q0 DQ ACT#0 READ#0 Q0 Q0 READ#0 Q0 masked Q0 Q0 Q0 READ#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 48 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS /CAS /WE Standby Power Down CKE Active Power Down CKE latency=1 DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ Precharge All ACT#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 49 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) CLK Suspend @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 CKE latency=1 DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ Y Y 0 0 D0 ACT#0 D0 D0 D0 WRITE#0 CLK suspended Q0 Q0 Q0 Q0 READ#0 CLK suspended Italic parameter indicates minimum case MITSUBISHI ELECTRIC 50 128M Synchronous DRAM SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) Nov. '99 (4-BANK x 4,194,304-WORD x 8-BIT) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT) Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MITSUBISHI ELECTRIC 51