Renesas M30302GAPGP Single-chip 16-bit cmos microcomputer Datasheet

M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.
REJ03B0088-0122
Rev.1.22
Mar 30, 2007
Overview
The M16C/30P Group of single-chip microcomputers is built using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and is packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. In addition, these
microcomputers contain a multiplier and DMAC which combined with fast instruction processing capability, make it
suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/
logic operations.
1.1
Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 1 of 53
M16C/30P Group
1.2
1. Overview
Performance Outline
Table 1.1 lists Performance Outline of M16C/30P Group.
Table 1.1
Performance Outline of M16C/30P Group
Item
Performance
Number of Basic Instructions 91 instructions
Minimum Instruction
62.5ns(f(XIN)=16MHz, VCC1=VCC2=3.0 to 5.5V, no wait)
Execution Time
100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait)
Operation Mode
Single-chip, memory expansion and microprocessor
mode
Memory Space
1 Mbyte
Memory Capacity
See Table 1.2 Product List
Peripheral
Port
Input/Output : 87 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 3 channels,
Timer B : 16 bits x 3 channels
Serial Interface
1 channels
Clock synchronous, UART, I2CBus(1), IEBus(2)
2 channels
Clock synchronous, UART, I2CBus(1)
A/D Converter
10-bit A/D converter: 1 circuit, 18 channels
DMAC
2 channels
CRC Calculation Circuit
CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Interrupt
Internal: 20 sources, External: 7 sources, Software: 4
sources, Priority level: 7 levels
Clock Generating Circuit
2 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
(*)Equipped with a built-in feedback resistor.
Electric
Supply Voltage
VCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz)
Characteristics
VCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait)
Power Consumption
10 mA (VCC1=VCC2=5V, f(XIN)=16MHz)
8 mA (VCC1=VCC2=3V, f(XIN)=10MHz)
1.8 μA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7 μA(VCC1=VCC2=3V, stop mode)
One time flash Program Supply Voltage
3.3±0.3 V or 5.0±0.5 V
version
Flash memory Program/Erase Supply
3.3±0.3 V or 5.0±0.5 V
version
Voltage
Program and Erase
100 times (all area)
Endurance
Operating Ambient Temperature
-20 to 85°C, -40 to 85°C
Package
100-pin plastic mold QFP, LQFP
CPU
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. Use the M16C/30P on VCC1 = VCC2.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 2 of 53
M16C/30P Group
1.3
1. Overview
Block Diagram
Figure 1.1 is a M16C/30P Group Block Diagram.
8
8
Port P0
8
Port P1
8
Port P3
Port P2
8
8
Port P4
Port P5
7
UART or
clock synchronous serial I/O
8
Output (timer A): 3
Input (timer B): 3
Port P8
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
A/D converter
(10 bits X 18 channels)
Timer (16-bit)
Port P6
Port P7
Internal peripheral functions
8
(3 channels)
Port P8_5
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core
R0H
R1H
R0L
R1L
R2
R3
DMAC
SB
ISP
INTB
(2 channels)
RAM (2)
PC
FLG
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
Figure 1.1
M16C/30P Group Block Diagram
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 3 of 53
8
Multiplier
Port P10
A0
A1
FB
ROM (1)
USP
8
(15 bits)
Port P9
Watchdog timer
Memory
M16C/30P Group
1.4
1. Overview
Product List
Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Part No., Memory Size, and Package. Table
1.4 lists Product Code of MASK ROM version for M16C/30P. Figure 1.3 shows the Marking Diagram of Mask
ROM Version for M16C/30P (Top View). Table 1.5 lists Product Code of One Time Flash version, Flash Memory
version, and ROM-less version for M16C/30P. Figure 1.4 shows the Marking Diagram of One Time Flash version,
Flash Memory version, and ROM-less Version for M16C/30P (Top View). Please specify the marking for
M16C30P (MASK ROM version) when placing an order for ROM.
Table 1.2
Product List (1)
Part No.
M30302MAP-XXXFP
M30302MAP-XXXGP
M30302MCP-XXXFP
M30302MCP-XXXGP
M30302MDP-XXXFP
M30302MDP-XXXGP
M30302MEP-XXXFP
M30302MEP-XXXGP
M30302GAPFP
M30302GAPGP
M30302GCPFP
M30302GCPGP
M30302GDPFP
M30302GDPGP
M30304GDPFP
M30304GDPGP
M30302GEPFP
M30302GEPGP
M30304GEPFP
M30304GEPGP
M30302GGPFP
M30302GGPGP
M30302GAP-XXXFP
M30302GAPvGP
M30302GCP-XXXFP
M30302GCP-XXXGP
M30302GDP-XXXFP
M30302GDP-XXXGP
M30304GDP-XXXFP
M30304GDP-XXXGP
M30302GEP-XXXFP
M30302GEP-XXXGP
M30304GEP-XXXFP
M30304GEP-XXXGP
M30302GGP-XXXFP
M30302GGP-XXXGP
ROM Capacity
96 Kbytes
As of March 2007
RAM Capacity
5 Kbytes
128 Kbytes
160 Kbytes
6 Kbytes
192 Kbytes
96 Kbytes
5 Kbytes
(D)
128 Kbytes
(D)
160 Kbytes
(D)
(D)
(D)
12 Kbytes
192 Kbytes
(D)
(D)
(D)
(D)
(D)
6 Kbytes
6 Kbytes
12 Kbytes
256 Kbytes
12 Kbytes
96 Kbytes
5 Kbytes
(D)
128 Kbytes
(D)
160 Kbytes
(D)
(D)
(D)
12 Kbytes
192 Kbytes
(D)
(D)
(D)
(D)
(D)
6 Kbytes
6 Kbytes
12 Kbytes
256 Kbytes
12 Kbytes
(D): Under development
(P): Under planning
NOTES:
1. Previous package codes are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A
2. Block A (4-Kbytes space) is available in flash memory version.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 4 of 53
package code
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
(1)
Remarks
Mask ROM version
One Time Flash
version
(blank product)
One Time Flash
version
(factory programmed
product)
M16C/30P Group
Table 1.3
1. Overview
Product List (2)
Part No.
M30302FAPFP
M30302FAPGP
M30302FCPFP
M30302FCPGP
M30302FEPFP
M30302FEPGP
M30302SPFP
M30302SPGP
ROM Capacity
96 K + 4 Kbytes
As of March 2007
RAM Capacity
5 Kbytes
128 K + 4 Kbytes
192 K + 4 Kbytes
6 Kbytes
-
6 Kbytes
package code (1)
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
Remarks
Flash memory
version(2)
ROM-less version
(D): Under development
(P): Under planning
NOTES:
1. Previous package codes are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A
2. Block A (4-Kbytes space) is available in flash memory version.
Part No.
M3030 2 M E P- XXX HP
Package type:
FP : Package PRQP0100JB-A (100P6S-A)
GP : Package PLQP0100KB-A (100P6Q-A)
ROM No.
M16C/30P Group
ROM
A
C
D
E
G
capacity:
:
96 Kbytes
: 128 Kbytes
: 160 Kbytes
: 192 Kbytes
: 256 Kbytes
Memory type:
M : Mask ROM version
G : One Time Flash version
F : Flash Memory version
S : ROM-less version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/30 Series
M16C Family
Figure 1.2
Part No., Memory Size, and Package
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 5 of 53
M16C/30P Group
Table 1.4
1. Overview
Product Code of MASK ROM version for M16C/30P
Product Code
Package
Operating Ambient Temperature
U1
Lead-free
-20°C to 85°C
U4
-40°C to 85°C
PRQP0100JB-A (100P6S-A)
1. Standard Renesas Mark
M1 6C
M3 0 3 0 2 M D P - X X X F P
A U1 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package)
Chip version, product code and date code
A
: Shows chip version.
Henceforth, whenever it changes a version,
it continues with A, B, and C.
U1
: Shows Product code. (See table 1.3 Product Code)
XXXXXXX : Seven digits
2. Customer’s Parts Number + Renesas catalog name
M3 0 3 0 2 M D P - X X X F P
A U1
M1 6 C X X X X X X X
Part No. (See Figure 1.2 Part No., Memory Size, and Package)
Chip version and product code
A
: Shows chip version.
Henceforth, whenever it changes a version,
it continues with A, B, and C.
U1
: Shows Product code. (See table 1.3 Product Code)
Date code seven digits
PLQP0100KB-A (100P6Q-A)
1. Standard Renesas Mark
M1 6C
M 3 0 3 0 2 MD P
- X X XGP
A U 1 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package)
Chip version, product code and date code
A
: Shows chip version.
Henceforth, whenever it changes a version,
it continues with A, B, and C.
U1
: Shows Product code. (See table 1.3 Product Code)
XXXXXXX : Seven digits
2. Customer’s Parts Number + Renesas catalog name
M 3 0 3 0 2 MD P
A U 1
- X X XGP
M1 6 C XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package)
Chip version and product code
A
: Shows chip version.
Henceforth, whenever it changes a version,
it continues with A, B, and C.
U1
: Shows Product code. (See table 1.3 Product Code)
Date code seven digits
NOTES:
1. Refer to the mark specification form for details of the Mask ROM version marking.
Figure 1.3
Marking Diagram of Mask ROM Version for M16C/30P (Top View)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 6 of 53
M16C/30P Group
Table 1.5
1. Overview
Product Code of One Time Flash version, Flash Memory version, and ROM-less
version for M16C/30P
Internal ROM
Product
Code
One Time Flash
version
Flash Memory
version
Package
U3
Temperature
Range
Leadfree
U5
U3
U3
0°C to 60°C
100
0°C to 60°C
-40°C to 85°C
-40°C to 85°C
-20°C to 85°C
−
Leadfree
U5
0
Operating
Ambient
Temperature
-20°C to 85°C
Leadfree
U5
ROM-less version
Program
and Erase
Endurance
−
-40°C to 85°C
-20°C to 85°C
NOTES:The one time flash version can be written once only.
PRQP0100JB-A (100P6S-A)
M1
M3 03 0 2 SP
A
XXXXX
6
F
U
X
C
P
3
X
Part No. (See Figure 1.2 Part No., Memory Size, and Package)
Chip version and product code
A
: Shows chip version.
Henceforth, whenever it changes a version,
it continues with A, B, and C.
U3
: Shows Product code. (See table 1.3 Product Code)
Date code seven digits
PLQP0100KB-A (100P6Q-A)
M1 6C
M 3 0 3 0 2 S PGP
A U3
XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package)
Chip version and product code
A
: Shows chip version.
Henceforth, whenever it changes a version,
it continues with A, B, and C.
U3
: Shows Product code. (See table 1.3 Product Code)
Date code seven digits
The product without marking of chip version of One Time Flash version, Flash
Memory version, and the ROMless version corresponds to the chip version “A”.
Figure 1.4
Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less
Version for M16C/30P (Top View)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 7 of 53
M16C/30P Group
1.5
1. Overview
Pin Configuration
Figures 1.5 to 1.6 show the pin configurations (top view).
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15
P2_0/A0
P2_1/A1
P2_2/A2
P2_3/A3
P2_4/A4
P2_5/A5
P2_6/A6
P2_7/A7
VSS
P3_0/A8
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
50
49
48
81
82
83
84
85
86
87
47
46
88
89
90
91
92
M16C/30P Group
93
94
95
96
97
98
99
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
100
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P9_6/ANEX1
P9_5/ANEX0
P9_4
P9_3
P9_2/TB2IN
P9_1/TB1IN
P9_0/TB0IN
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2
P8_3/INT1
P8_2/INT0
P8_1
P8_0
P7_7
P7_6
P7_5/TA2IN
P7_4/TA2OUT
P7_3/CTS2/RTS2/TA1IN
P7_2/CLK2/TA1OUT
P7_1/RXD2/SCL2/TA0IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/30P on VCC1=VCC2.
Package : PRQP0100JB-A (100P6S-A)
Figure 1.5
Pin Configuration (Top View)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 8 of 53
M16C/30P Group
1. Overview
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15
P2_0/A0
P2_1/A1
P2_2/A2
P2_3/A3
P2_4/A4
P2_5/A5
P2_6/A6
P2_7/A7
VSS
P3_0/A8
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
P9_6/ANEX1
P9_5/ANEX0
76
77
50
49
78
79
48
47
46
45
80
81
82
44
43
42
41
40
83
84
85
86
87
88
89
M16C/30P Group
90
91
92
93
39
38
37
36
35
34
94
95
96
33
32
31
30
97
29
98
99
28
27
100
26
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT(1)
P7_1/RXD2/SCL2/TA0IN(1)
P7_2/CLK2/TA1OUT
P9_4
P9_3
P9_2/TB2IN
P9_1/TB1IN
P9_0/TB0IN
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2
P8_3/INT1
P8_2/INT0
P8_1
P8_0
P7_7
P7_6
P7_5/TA2IN
P7_4/TA2OUT
P7_3/CTS2/RTS2/TA1IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/30P on VCC1=VCC2.
Package : PLQP0100KB-A (100P6Q-A)
Figure 1.6
Pin Configuration (Top View)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 9 of 53
M16C/30P Group
Table 1.6
Pin No.
FP GP
1. Overview
Pin Characteristics (1)
Control
Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
1
99
P9_6
ANEX1
2
100
P9_5
ANEX0
3
1
P9_4
4
2
P9_3
5
3
P9_2
TB2IN
6
4
P9_1
TB1IN
7
5
P9_0
TB0IN
8
6
Bus Control
Pin
BYTE
9
7
CNVSS
10
8
XCIN
P8_7
11
9
XCOUT
P8_6
12
10
RESET
13
11
XOUT
14
12
VSS
15
13
XIN
16
14
VCC1
17
15
P8_5
NMI
18
16
P8_4
INT2
19
17
P8_3
INT1
20
18
P8_2
INT0
21
19
P8_1
22
20
P8_0
23
21
P7_7
24
22
P7_6
25
23
P7_5
TA2IN
26
24
P7_4
TA2OUT
27
25
P7_3
TA1IN
28
26
P7_2
TA1OUT
CLK2
29
27
P7_1
TA0IN
RXD2/SCL2
30
28
P7_0
TA0OUT
31
29
P6_7
TXD1/SDA1
32
30
P6_6
RXD1/SCL1
33
31
P6_5
CLK1
34
32
P6_4
CTS1/RTS1/CTS0/CLKS1
35
33
P6_3
TXD0/SDA0
36
34
P6_2
RXD0/SCL0
37
35
P6_1
CLK0
38
36
P6_0
CTS0/RTS0
39
37
P5_7
RDY/CLKOUT
40
38
P5_6
ALE
41
39
P5_5
HOLD
42
40
P5_4
HLDA
43
41
P5_3
BCLK
44
42
P5_2
RD
45
43
P5_1
WRH/BHE
46
44
P5_0
WRL/WR
47
45
P4_7
CS3
48
46
P4_6
CS2
49
47
P4_5
CS1
50
48
P4_4
CS0
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CTS2/RTS2
TXD2/SDA2
M16C/30P Group
Table 1.7
1. Overview
Pin Characteristics (2)
Pin No.
Control Pin
FP GP
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
52
49
50
P4_3
P4_2
A19
A18
53
54
51
P4_1
A17
52
P4_0
A16
P3_7
A15
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
53
54
55
56
57
58
59
60 VCC2
61
62 VSS
63
64
65
66
67
68
69
70
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A14
A13
A12
A11
A10
A9
P3_0
A8
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
A7
A6
A5
A4
A3
A2
A1
A0
73
71
P1_7
D15
74
72
P1_6
INT4
D14
75
73
INT3
76
77
74
75
P1_5
P1_4
P1_3
D13
D12
D11
78
76
P1_2
D10
79
77
P1_1
D9
55
80
78
P1_0
81
82
83
84
85
79
80
81
82
83
P0_7
P0_6
P0_5
P0_4
P0_3
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
D7
D6
D5
D4
D3
D8
86
84
P0_2
AN0_2
D2
87
88
85
86
P0_1
P0_0
AN0_1
AN0_0
D1
D0
89
87
P10_7
KI3
AN7
90
88
P10_6
KI2
AN6
91
89
P10_5
KI1
AN5
92
90
91
92
93
94 AVSS
95
P10_4
P10_3
P10_2
P10_1
KI0
93
94
95
96
97
AN4
AN3
AN2
AN1
98
96 VREF
99
97 AVCC
100
98
P10_0
AN0
P9_7
ADTRG
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M16C/30P Group
1.6
1. Overview
Pin Description
Table 1.8
Pin Description (1)
Signal Name
Power supply input
Analog power
supply input
Reset input
Pin Name
VCC1, VCC2
VSS
AVCC
AVSS
RESET
CNVSS
CNVSS
External data bus
width select input
BYTE
Bus control pins
D0 to D7
D8 to D15
A0 to A19
I : Input
O : Output
I/O Type
Description
I
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 = VCC2.
I
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
I
The microcomputer is in a reset state when applying “L” to the this
pin.
I
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
I
Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
I/O
Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
I/O
Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
O
Output address bits (A0 to A19).
CS0 to CS3
O
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
WRL/WR
WRH/BHE
RD
O
ALE
O
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
• WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
• WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE is a signal to latch the address.
HOLD
I
HLDA
O
In a hold state, HLDA outputs a "L" signal.
RDY
I
While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
I/O : Input and output
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While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
M16C/30P Group
Table 1.9
Signal Name
Main clock
input
Main clock
output
Sub clock
input
Sub clock
output
Clock output
1. Overview
Pin Description (2)
Pin Name
XIN
I/O Type
I
Description
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. To use the
external clock, input the clock from XIN and leave XOUT open.
XOUT
O
XCIN
I
XCOUT
O
CLKOUT
The clock of the same cycle as fC, f8, or f32 is outputted.
I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator
between XCIN and XCOUT. To use the external clock, input the clock
from XCIN and leave XCOUT open.
INT interrupt
input
INT0 to INT4
O
I
NMI interrupt
input
Key input
interrupt input
Timer A
NMI
I
Input pin for the NMI interrupt.
KI0 to KI3
I
Input pins for the key input interrupt.
Timer B
Serial
interface
CTS0 to CTS2
I2C mode
Reference
voltage input
A/D converter
I/O port
Input port
I : Input
TA0OUT to
TA2OUT
TA0IN to TA2IN
TB0IN to TB2IN
I/O
Input pins for the INT interrupt.
I
I
I
These are timer A0 to timer A2 I/O pins. (however, the output of
TA0OUT for the N-channel open drain output.)
These are timer A0 to timer A2 input pins.
These are timer B0 to timer B2 input pins.
These are send control input pins.
RTS0 to RTS2
CLK0 to CLK2
RXD0 to RXD2
TXD0 to TXD2
O
These are receive control output pins.
I/O
I
O
CLKS1
SDA0 to SDA2
O
I/O
SCL0 to SCL2
I/O
VREF
I
These are transfer clock I/O pins.
These are serial data input pins.
These are serial data output pins. (however, TXD2 for the N-channel
open drain output.)
This is output pin for transfer clock output from multiple pins function.
These are serial data I/O pins. (however, SDA2 for the N-channel
open drain output.)
These are transfer clock I/O pins. (however, SCL2 for the N-channel
open drain output.)
Applies the reference voltage for the A/D converter.
AN0 to AN7,
AN0_0 to AN0_7
I
Analog input pins for the A/D converter.
ADTRG
ANEX0
I
This is an A/D trigger input pin.
I/O
ANEX1
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to P10_7
P8_0 to P8_4,
P8_6, P8_7
P8_5
O : Output
I
I/O
I/O
I
I/O : Input and output
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This is the extended analog input pin for the A/D converter, and is the
output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
8-bit I/O ports in CMOS, having a direction register to select an input
or output.
Each pin is set as an input port or output port. An input port can be set
for a pull-up or for no pull-up in 4-bit unit by program. (however, P7_0
and P7_1 for the N-channel open drain output.)
I/O ports having equivalent functions to P0.
Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit
in the P8 register.
M16C/30P Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8 b7
R2
R0H
R3
R1H
b0
R0L
R1L
Data Registers (1)
R2
R3
A0
Address Registers (1)
A1
FB
b19
b15
Frame Base Registers (1)
b0
INTBH
Interrupt Table Register
INTBL
b19
b0
Program Counter
PC
b15
b0
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
SB
Static Base Register
b15
b0
FLG
b15
b8
IPL
b7
U I
Flag Register
b0
O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
2.1
Central Processing Unit Register
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
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M16C/30P Group
2.2
2. Central Processing Unit (CPU)
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3
Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4
Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6
Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
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M16C/30P Group
2.8.8
2. Central Processing Unit (CPU)
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
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M16C/30P Group
3.
3. Memory
Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte
internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses
from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no
functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000h
SFR
00400h
Internal RAM
XXXXXh
Reserved area
(1)
FFE00h
0F000h
Internal ROM
(data area) (3, 4)
0FFFFh
Special page
vector table
10000h
External area
27000h
Reserved area
Internal RAM
Size
Address XXXXXh
Internal ROM
Size
(5)
017FFh
96 Kbytes
E8000h
6 Kbytes
01BFFh
128 Kbytes
E0000h
12 Kbytes
033FFh
160 Kbytes
D8000h
192 Kbytes
D0000h
256 Kbytes
C0000h(6)
D0000h
Reserved area (2, 4)
YYYYYh
Internal ROM
(program area) (5)
FFFFFh
NOTES:
1. During memory expansion and microprocessor modes, can be used.
2. In memory expansion mode, can be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1” .
5. When using the masked ROM version, write nothing to internal ROM area.
6. When the PM13 bit is set to "0", the address of Internal ROM becomes D0000h, and when
the PM13 bit is set to "1", the address becomes C0000h.
Figure 3.1
Memory Map
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Undefined instruction
Overflow
External area
Address YYYYYh
5 Kbytes
FFFDCh
28000h
FFFFFh
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
M16C/30P Group
4.
4. Special Function Register (SFR)
Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR
information.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0 (2)
PM0
00000000b(CNVSS pin is “L”)
00000011b(CNVSS pin is “H”)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
PM1
CM0
CM1
CSR
AIER
PRCR
00XXX0X0b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
RMAD0
XXh
00XXXXXXb
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
DMA0 Source Pointer
SAR0
XXh
XXh
XXh
DMA0 Destination Pointer
DAR0
XXh
XXh
XXh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh
XXh
XXh
DMA1 Destination Pointer
DAR1
XXh
XXh
XXh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
00000X00b
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. The PM00 and PM01 bits do not change at software reset.
X : Nothing is mapped to this bit
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M16C/30P Group
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
to
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
to
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
to
033Fh
4. Special Function Register (SFR)
SFR Information (2) (1)
Register
Symbol
After Reset
INT3 Interrupt Control Register
INT3IC
XX00X000b
UART1 BUS Collision Detection Interrupt Control Register
UART0 BUS Collision Detection Interrupt Control Register
U1BCNIC
U0BCNIC
XXXXX000b
XXXXX000b
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
Flash Memory Control Register 1 (2)
FMR1
0X00XX0Xb
Flash Memory Control Register 0 (3)
FMR0
00000001b
Peripheral Clock Select Register
PCLKR
00000011b
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
3. This register is included in the flash memory version and one time flash version.
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X : Nothing is mapped to this bit
M16C/30P Group
Table 4.3
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
4. Special Function Register (SFR)
SFR Information (3) (1)
Register
Symbol
After Reset
Interrupt Factor Select Register 2
Interrupt Factor Select Register
IFSR2A
IFSR
00XXXXXXb
00h
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
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M16C/30P Group
Table 4.4
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
4. Special Function Register (SFR)
SFR Information (4) (1)
Count Start Flag
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
000XX000b
0XXXXXXXb
00XXX000b
XXXX0000b
XX0XX000b (2)
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
XXh
XXh
XXh
XXh
XXh
XXh
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
TA0MR
TA1MR
TA2MR
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
TB0MR
TB1MR
TB2MR
00XX0000b
00XX0000b
00XX0000b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
UART Transmit/Receive Control Register 2
UCON
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X0000000b
DMA0 Request Factor Select Register
DM0SL
00h
DMA1 Request Factor Select Register
DM1SL
00h
CRC Data Register
CRCD
CRC Input Register
CRCIN
XXh
XXh
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Rev.1.22 Mar 30, 2007
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Page 21 of 53
M16C/30P Group
Table 4.5
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
4. Special Function Register (SFR)
SFR Information (5) (1)
Register
Symbol
After Reset
A/D Register 0
AD0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Control Register 2
ADCON2
XXX000X0b
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
000X0XXXb
00000XXXb
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00X00000b
00h
XXh
Port P10 Direction Register
PD10
00h
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
Pull-Up Control Register 2
Port Control Register
PUR2
PCR
00h
00000000b (2)
00000010b (2)
00h
00h
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. At hardware reset, the register is as follows:
• “00000000b” where “L” is inputted to the CNVSS pin
• “00000010b” where “H” is inputted to the CNVSS pin
At software reset, the register is as follows:
• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).
• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode).
X : Nothing is mapped to this bit
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 22 of 53
M16C/30P Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Condition
Rated Value
Unit
VCC
Supply Voltage(VCC1=VCC2)
Parameter
VCC1=VCC2=AVCC
−0.3 to 6.5
V
AVCC
Analog Supply Voltage
VCC1=VCC2=AVCC
−0.3 to 6.5
V
VI
Input Voltage
RESET, CNVSS, BYTE,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
VREF, XIN
−0.3 to VCC+0.3
V
VO
Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
XOUT
Pd
Power Dissipation
Topr
Operating
Ambient
Temperature
P7_0, P7_1
P7_0, P7_1
When the Microcomputer is Operating
One Time Flash Program Erase
Flash Program Erase
Tstg
Storage Temperature
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 23 of 53
−40°C<Topr≤85°C
−0.3 to 6.5
V
−0.3 to VCC+0.3
V
−0.3 to 6.5
V
300
mW
−20 to 85 / −40 to 85
°C
0 to 60
0 to 60
−65 to 150
°C
M16C/30P Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions (1)
Symbol
VCC
Supply Voltage (VCC1=VCC2)
AVCC
Analog Supply Voltage
VSS
Supply Voltage
AVSS
Analog Supply Voltage
VIH
HIGH Input
Voltage
VIL
Standard
Parameter
LOW Input
Voltage
Min.
2.7
Typ.
Max.
5.0
5.5
Unit
V
VCC
V
0
V
0
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
0.8VCC
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0.8VCC
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0.5VCC
VCC
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, XIN, RESET, CNVSS, BYTE
0.8VCC
VCC
V
P7_0, P7_1
0.8VCC
6.5
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
0
0.2VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0.2VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0
0.16VCC
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
XIN, RESET, CNVSS, BYTE
0
0.2VCC
V
IOH(peak)
HIGH Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
−10.0
mA
IOH(avg)
HIGH Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
−5.0
mA
IOL(peak)
LOW Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
10.0
mA
IOL(avg)
LOW Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
5.0
mA
f(XIN)
Main Clock Input VCC=3.0V to 5.5V
Oscillation
VCC=2.7V to 3.0V
Frequency (4)
0
16
MHz
0
20×VCC1−44
MHz
f(XCIN)
Sub-Clock Oscillation Frequency
f(BCLK)
CPU Operation Clock
32.768
0
50
kHz
16
MHz
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5,
P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be −40mA max. The total
IOH(peak) for ports P3, P4 and P5 must be −40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be −40mA
max.
The total IOH(peak) for ports P8_6, P8_7 and P9 must be −40mA max. Set Average Output Current to 1/2 of peak.
4. Relationship between main clock oscillation frequency, and supply voltage.
f(XIN) operating maximum frequency [MHz]
Main clock input oscillation frequency
20 x VCC1-44MHz
16.0
10.0
0.0
2.7
3.0
VCC1[V] (main clock: no division)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 24 of 53
5.5
M16C/30P Group
Table 5.3
5. Electrical Characteristics
A/D Conversion Characteristics (1)
Symbol
Parameter
−
Resolution
INL
Integral Non-Linearity
Error
−
Measuring Condition
Standard
Min.
Typ.
VREF=VCC
Absolute Accuracy
10bit
Max.
Unit
10
Bits
VREF=
VCC=
5V
AN0 to AN7 input,
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
±5
LSB
VREF=
VCC=
3.3V
AN0 to AN7 input,
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
±7
LSB
8bit
VREF=VCC=5V, 3.3V
±2
LSB
10bit
VREF=
VCC=
5V
AN0 to AN7 input,
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
±5
LSB
VREF=
VCC
=3.3V
AN0 to AN7 input,
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
±7
LSB
±2
LSB
8bit
VREF=VCC=5V, 3.3V
−
Tolerance Level Impedance
DNL
Differential Non-Linearity Error
±2
LSB
−
Offset Error
±5
LSB
−
Gain Error
±5
LSB
RLADDER
Ladder Resistance
VREF=VCC
10
40
kΩ
tCONV
10-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC=5V, φAD=10MHz
3.3
μs
tCONV
8-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC=5V, φAD=10MHz
2.8
μs
tSAMP
Sampling Time
0.3
VREF
Reference Voltage
3.0
VCC
V
VIA
Analog Input Voltage
0
VREF
V
3
kΩ
μs
NOTES:
1. Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold function is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.
4. When sample & hold function is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 25 of 53
M16C/30P Group
Table 5.4
5. Electrical Characteristics
Flash Memory Version Electrical Characteristics (1)
Symbol
Standard
Parameter
Min.
Typ.
Max.
Unit
−
Program and Erase Endurance (2)
−
Word Program Time (VCC1=5.0V)
25
200
μs
−
Lock Bit Program Time
25
200
μs
−
Block Erase Time
(VCC1=5.0V)
4-Kbyte block
0.3
4
s
8-Kbyte block
0.3
4
s
−
32-Kbyte block
0.5
4
s
−
64-Kbyte block
0.8
4
s
15
μs
−
100(3)
tPS
Flash Memory Circuit Stabilization Wait Time
−
Data Hold Time (4)
cycle
10
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified.
2. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is 100, each block can be erased 100 times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
3. Maximum number of E/W cycles for which operation is guaranteed.
4. Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5).
Table 5.5
Flash Memory Version Program / Erase Voltage and Read Operation Voltage
Characteristics
Flash Program, Erase Voltage
VCC1 = 3.3 ± 0.3 V or 5.0 ± 0.5 (Topr = 0°C to 60°C )
Flash Read Operation Voltage
VCC1=2.7 to 5.5 V (Topr = -40°C to 85°C (U3)
-20°C to 85°C (U5))
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 26 of 53
M16C/30P Group
Table 5.6
5. Electrical Characteristics
One Time Flash Version Electrical Characteristics (1)
Symbol
Standard
Parameter
Min.
−
Program Endurance
−
Word Program Time (VCC1=5.0V)
tPS
One Time Flash Memory Circuit Stabilization Wait Time
−
Data Hold Time (4)
Max.
50
500
μs
15
μs
1
10
NOTES:
1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified.
2. Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5).
Table 5.7
One Time Flash Version Program Voltage and Read Operation Voltage Characteristics
Flash Program Voltage
VCC1 = 3.3 ± 0.3 V or 5.0 ± 0.5 (Topr = 0°C to 60°C )
Flash Read Operation Voltage
VCC1=2.7 to 5.5 V (Topr = -40°C to 85°C (U3)
-20°C to 85°C (U5))
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 27 of 53
Unit
Typ.
cycle
year
M16C/30P Group
Table 5.8
5. Electrical Characteristics
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Measuring Condition
td(P-R)
Time for Internal Power Supply Stabilization
During Powering-On
td(R-S)
td(W-S)
Typ.
VCC=2.7V to 5.5V
Max.
Unit
2
ms
STOP Release Time
1500
μs
Low Power Dissipation Mode Wait Mode
Release Time
1500
μs
Recommended
operation voltage
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
VCC
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b)Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation
Mode Wait Mode Release
Time
CPU clock
(a)
(b)
Figure 5.1
Standard
Min.
Power Supply Circuit Timing Diagram
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 28 of 53
td(R-S)
td(W-S)
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.9
Electrical Characteristics(1)
Symbol
VOH
VOH
VOH
Parameter
VOL
VOL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH=−5mA
HIGH
Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH=−200μA
HIGH Output Voltage
XOUT
XCOUT
HIGHPOWER
With no load applied
2.5
With no load applied
1.6
2.0
V
0.45
V
HIGHPOWER
IOL=1mA
2.0
IOL=0.5mA
2.0
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
TA0IN to TA2IN, TB0IN to TB2IN,
INT0 to INT4, NMI, ADTRG, CTS0 to CTS2,
CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3,
RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2
RESET
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=5V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=0V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7
VI=0V
V
V
LOWPOWER
HIGH Input
Current
Resistance
V
LOWPOWER
Hysteresis
RPULLUP Pull-Up
VCC
VCC
IIH
LOW Input
Current
VCC−0.3
VCC
VT+-VT-
IIL
V
VCC−2.0
IOL=200μA
Hysteresis
VCC
VCC−2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
Unit
VCC−2.0
IOH=−0.5mA
LOW
Output
Voltage
XCOUT
Max.
IOH=−1mA
IOL=5mA
XOUT
Typ.
LOWPOWER
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW Output Voltage
Standard
Min.
HIGHPOWER
LOW
Output
Voltage
LOW Output Voltage
VT+-VT-
Measuring Condition
HIGH
Output
Voltage
HIGH Output Voltage
VOL
(1)
V
V
0.2
1.0
V
0.2
2.5
V
5.0
μA
−5.0
μA
170
kΩ
30
50
RfXIN
Feedback Resistance XIN
1.5
MΩ
RfXCIN
Feedback Resistance XCIN
15
MΩ
VRAM
RAM Retention Voltage
At stop mode
2.0
V
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN) =16MHz unless otherwise specified.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 29 of 53
M16C/30P Group
Table 5.10
5. Electrical Characteristics
Electrical Characteristics (2) (1)
Symbol
ICC
Parameter
Power Supply Current
In single-chip
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
other pins are VSS
Measuring Condition
Standard
Min.
Typ.
Max.
Mask ROM
f(XIN)=16MHz
No division
10
15
mA
One Time
Flash
f(XIN)=16MHz,
No division
10
18
mA
Flash
Memory
f(XIN)=16MHz,
No division
12
18
mA
One Time
Flash
f(XIN)=10MHz,
VCC1=5.0V
15
mA
Flash Memory
Program
f(XIN)=10MHz,
VCC1=5.0V
15
mA
Flash Memory
Erase
f(XIN)=10MHz,
VCC1=5.0V
25
mA
Mask ROM
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
μA
25
μA
350
μA
25
μA
f(XCIN)=32kHz
Low power dissipation
mode, Flash Memory (3)
420
μA
f(XCIN)=32kHz
Wait mode (2),
Oscillation capability High
7.5
μA
f(XCIN)=32kHz
Wait mode (2),
Oscillation capability Low
2.0
μA
Stop mode
Topr =25°C
0.8
One Time
Flash
f(XCIN)=32kHz
Low power dissipation
mode, RAM (3)
f(XCIN)=32kHz
Low power dissipation
mode, Flash Memory (3)
Flash Memory
Mask ROM
One Time Flash
Flash Memory
f(XCIN)=32kHz
Low power dissipation
mode, RAM (3)
3.0
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=16MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 30 of 53
Unit
μA
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.11
External Clock Input (XIN input) (1)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External Clock Input Cycle Time
62.5
ns
tw(H)
External Clock Input HIGH Pulse Width
25
ns
tw(L)
External Clock Input LOW Pulse Width
25
tr
External Clock Rise Time
15
ns
tf
External Clock Fall Time
15
ns
ns
NOTES:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 5.12
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data Input Access Time (for setting with no wait)
(NOTE 1)
ns
tac2(RD-DB)
Data Input Access Time (for setting with wait)
(NOTE 2)
ns
tsu(DB-RD)
Data Input Setup Time
40
tsu(RDY-BCLK)
RDY Input Setup Time
30
ns
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 45 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
n is ”2” for 1-wait setting.
Page 31 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.13
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
40
ns
tw(TAL)
TAiIN Input LOW Pulse Width
40
ns
Table 5.14
Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
200
ns
tw(TAL)
TAiIN Input LOW Pulse Width
200
ns
Table 5.15
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
100
ns
tw(TAL)
TAiIN Input LOW Pulse Width
100
ns
Table 5.16
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN Input HIGH Pulse Width
100
ns
tw(TAL)
TAiIN Input LOW Pulse Width
100
ns
Table 5.17
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input HIGH Pulse Width
1000
ns
tw(UPL)
TAiOUT Input LOW Pulse Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Table 5.18
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
800
tsu(TAIN-TAOUT)
TAiOUT Input Setup Time
200
ns
tsu(TAOUT-TAIN)
TAiIN Input Setup Time
200
ns
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 32 of 53
ns
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.19
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on both edges)
80
ns
Table 5.20
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
200
ns
tw(TBL)
TBiIN Input LOW Pulse Width
200
ns
Table 5.21
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
200
ns
tw(TBL)
TBiIN Input LOW Pulse Width
200
ns
Table 5.22
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG Input Cycle Time
1000
ns
tw(ADL)
ADTRG input LOW Pulse Width
125
ns
Table 5.23
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi Input Cycle Time
200
ns
tw(CKH)
CLKi Input HIGH Pulse Width
100
ns
tw(CKL)
CLKi Input LOW Pulse Width
100
td(C-Q)
TXDi Output Delay Time
th(C-Q)
TXDi Hold Time
0
ns
tsu(D-C)
RXDi Input Setup Time
70
ns
th(C-D)
RXDi Input Hold Time
90
ns
Table 5.24
tw(INL)
ns
External Interrupt INTi Input
Symbol
tw(INH)
ns
80
Parameter
Standard
Min.
Max.
Unit
INTi Input HIGH Pulse Width
250
ns
INTi Input LOW Pulse Width
250
ns
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 33 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.25
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
Standard
Parameter
Min.
Max.
25
Unit
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
−3
ns
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
td(DB-WR)
ns
25
ns
15
ns
−3
See
Figure 5.2
ns
−4
ns
25
ns
0
ns
25
ns
0
ns
40
ns
4
ns
Data Output Delay Time (in relation to WR)
(NOTE 1)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR) (3)
(NOTE 2)
td(BCLK-HLDA)
HLDA Output Delay Time
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ]
f(BCLK) is 12.5MHz or less.
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC1)
by a circuit of the right figure.
For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.2
Ports P0 to P10 Measurement Circuit
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 34 of 53
ns
40
ns
R
DBi
C
30pF
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.26
Memory Expansion and Microprocessor Modes (for 1 wait setting and external area
access)
Symbol
Standard
Parameter
Min.
Max.
25
Unit
ns
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
−3
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
td(DB-WR)
ns
25
ns
15
ns
−3
See
Figure 5.2
ns
−4
ns
25
ns
0
ns
25
ns
0
ns
40
ns
4
ns
Data Output Delay Time (in relation to WR)
(NOTE 1)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)(3)
(NOTE 2)
td(BCLK-HLDA)
HLDA Output Delay Time
ns
40
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 40 [ ns ]
n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC1)
by a circuit of the right figure.
For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC1 / VCC1)
= 6.7ns.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 35 of 53
R
DBi
C
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
th(TIN-UP) tsu(UP-TIN)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.3
Timing Diagram (1)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 36 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 5.4
Timing Diagram (2)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 37 of 53
th(C-D)
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD−BCLK)
th(BCLK−HOLD)
HOLD input
HLDA input
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK−HLDA)
Hi−Z
(1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the BYTE pin,
PM06 bit in PM0 register.
· Measuring conditions :
· VCC1=VCC2=5V
· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
· Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 5.5
Timing Diagram (3)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 38 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
−3ns.min
25ns.max
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
−3ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
25ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
−3ns.min
25ns.max
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
−3ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.6
Timing Diagram (4)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 39 of 53
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
−3ns.min
25ns.max
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
−3ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
25ns.max
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
25ns.max
0ns.min
RD
tac2(RD-DB)
(1.5 × tcyc-45)ns.max
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
−3ns.min
25ns.max
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
−3ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.7
Timing Diagram (5)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 40 of 53
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Table 5.27
Electrical Characteristics (1)
Symbol
VOH
VOH
Parameter
HIGH
Output
Voltage
HIGH Output Voltage
VOL
LOW
Output
Voltage
XOUT
LOW Output Voltage XOUT
Hysteresis
Max.
VCC−0.5
VCC
IOH=−0.1mA
VCC−0.5
VCC
LOWPOWER
IOH=−50μA
VCC−0.5
VCC
HIGHPOWER
With no load applied
2.5
LOWPOWER
With no load applied
1.6
0.5
IOL=0.1mA
0.5
LOWPOWER
IOL=50μA
0.5
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
TA0IN to TA2IN,
TB0IN to TB2IN, INT0 to INT4, NMI,
ADTRG, CTS0 to CTS2, RXD0 to RXD2,
CLK0 to CLK2, TA0OUT to TA2OUT,
KI0 to KI3, SCL0 to SCL2, SDA0 to SDA2
0.2
RESET
IIH
HIGH Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=3V
LOW Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=0V
0.2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=0V
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
RfXIN
Feedback Resistance
XIN
RfXCIN
Feedback Resistance
XCIN
VRAM
RAM Retention Voltage
At stop mode
50
(0.7)
100
Page 41 of 53
V
V
V
V
V
0.8
V
1.8
V
4.0
μA
−4.0
μA
500
kΩ
3.0
MΩ
25
MΩ
2.0
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless
otherwise specified.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Unit
V
HIGHPOWER
Hysteresis
RPULLUP Pull-Up
Resistance
Typ.
HIGHPOWER
VT+-VT-
IIL
Standard
Min.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL=1mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW Output Voltage XCOUT
VT+-VT-
Measuring Condition
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH=−1mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
HIGH Output Voltage XCOUT
VOL
(1)
V
M16C/30P Group
Table 5.28
5. Electrical Characteristics
Electrical Characteristics (2) (1)
Symbol
ICC
Parameter
Power Supply Current
In single-chip
(VCC1=VCC2=2.7V to 3.6V) mode, the output
pins are open and
other pins are VSS
Measuring Condition
Standard
Min.
Typ.
Max.
Mask ROM
f(XIN)=10MHz
No division
8
11
mA
One Time
Flash
f(XIN)=10MHz,
No division
8
13
mA
Flash
Memory
f(XIN)=10MHz,
No division
8
13
mA
Flash Memory
Program
f(XIN)=10MHz,
VCC1=3.0V
12
mA
One Time
f(XIN)=10MHz,
Flash Program VCC1=3.0V
12
mA
Flash Memory
Erase
f(XIN)=10MHz,
VCC1=3.0V
22
mA
Mask ROM
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
μA
f(XCIN)=32kHz
Low power dissipation
mode, RAM (3)
25
μA
f(XCIN)=32kHz
Low power dissipation
mode, Flash Memory (3)
350
μA
f(XCIN)=32kHz
Low power dissipation
mode, RAM (3)
25
μA
f(XCIN)=32kHz
Low power dissipation
mode, Flash Memory (3)
420
μA
f(XCIN)=32kHz
Wait mode (2),
Oscillation capability High
6.0
μA
f(XCIN)=32kHz
Wait mode (2),
Oscillation capability Low
1.8
μA
Stop mode
Topr =25°C
0.7
One Time
Flash
Flash Memory
Mask ROM
One Time Flash
Flash Memory
3.0
NOTES:
1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 42 of 53
Unit
μA
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.29
External Clock Input (XIN input)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External Clock Input Cycle Time
(NOTE 2)
ns
tw(H)
External Clock Input HIGH Pulse Width
(NOTE 3)
ns
tw(L)
External Clock Input LOW Pulse Width
(NOTE 3)
tr
External Clock Rise Time
(NOTE 4)
ns
tf
External Clock Fall Time
(NOTE 4)
ns
ns
NOTES:
1. The condition is VCC1=VCC2=2.7 to 3.0V.
2. Calculated according to the VCC1 voltage as follows:
10 – 6
---------------------------------------- [ns]
20 × V C C1 – 44
3. Calculated according to the VCC1 voltage as follows:
–6
10
---------------------------------------- × 0.4 [ns]
20 × V C C1 – 44
4. Calculated according to the VCC1 voltage as follows:
– 10 × V C C1 + 45 [ns]
Table 5.30
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data Input Access Time (for setting with no wait)
(NOTE 1)
ns
tac2(RD-DB)
Data Input Access Time (for setting with wait)
(NOTE 2)
ns
tsu(DB-RD)
Data Input Setup Time
50
tsu(RDY-BCLK)
RDY Input Setup Time
40
ns
50
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 60 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
n is ”2” for 1-wait setting.
Page 43 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.31
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
150
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
60
ns
tw(TAL)
TAiIN Input LOW Pulse Width
60
ns
Table 5.32
Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
600
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
300
ns
tw(TAL)
TAiIN Input LOW Pulse Width
300
ns
Table 5.33
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
300
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
150
ns
tw(TAL)
TAiIN Input LOW Pulse Width
150
ns
Table 5.34
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN Input HIGH Pulse Width
150
ns
tw(TAL)
TAiIN Input LOW Pulse Width
150
ns
Table 5.35
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(UP)
TAiOUT Input Cycle Time
3000
ns
tw(UPH)
TAiOUT Input HIGH Pulse Width
1500
ns
tw(UPL)
TAiOUT Input LOW Pulse Width
1500
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
600
ns
th(TIN-UP)
TAiOUT Input Hold Time
600
ns
Table 5.36
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
μs
tc(TA)
TAiIN Input Cycle Time
tsu(TAIN-TAOUT)
TAiOUT Input Setup Time
500
ns
tsu(TAOUT-TAIN)
TAiIN Input Setup Time
500
ns
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 44 of 53
2
Max.
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.37
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
150
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on one edge)
60
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on one edge)
60
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
300
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on both edges)
120
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on both edges)
120
ns
Table 5.38
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time
600
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
300
ns
tw(TBL)
TBiIN Input LOW Pulse Width
300
ns
Table 5.39
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time
600
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
300
ns
tw(TBL)
TBiIN Input LOW Pulse Width
300
ns
Table 5.40
A/D Trigger Input
Symbol
tc(AD)
tw(ADL)
Table 5.41
Parameter
Standard
Min.
Max.
Unit
ADTRG Input Cycle Time
1500
ns
ADTRG Input LOW Pulse Width
200
ns
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi Input Cycle Time
300
ns
tw(CKH)
CLKi Input HIGH Pulse Width
150
ns
tw(CKL)
CLKi Input LOW Pulse Width
150
td(C-Q)
TXDi Output Delay Time
th(C-Q)
TXDi Hold Time
0
ns
tsu(D-C)
RXDi Input Setup Time
100
ns
th(C-D)
RXDi Input Hold Time
90
ns
Table 5.42
tw(INL)
ns
External Interrupt INTi Input
Symbol
tw(INH)
ns
160
Parameter
Standard
Min.
Max.
Unit
INTi Input HIGH Pulse Width
380
ns
INTi Input LOW Pulse Width
380
ns
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 45 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.43
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
Standard
Parameter
Min.
Max.
30
Unit
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
ns
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
td(DB-WR)
0
ns
30
ns
0
ns
25
See
Figure 5.8
ns
−4
ns
30
ns
0
ns
30
ns
0
ns
40
ns
4
ns
Data Output Delay Time (in relation to WR)
(NOTE 1)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR) (3)
(NOTE 2)
td(BCLK-HLDA)
HLDA Output Delay Time
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ]
f(BCLK) is 12.5MHz or less.
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC1)
by a circuit of the right figure.
For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.8
Ports P0 to P10 Measurement Circuit
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 46 of 53
ns
40
ns
R
DBi
C
30pF
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.44
Memory Expansion and Microprocessor Modes (for 1 wait setting and external area
access)
Symbol
Standard
Parameter
Min.
Unit
Max.
30
ns
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
ns
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
td(DB-WR)
0
ns
30
ns
0
ns
25
See
Figure 5.8
ns
-4
ns
30
ns
0
ns
30
ns
0
ns
40
ns
4
ns
Data Output Delay Time (in relation to WR)
(NOTE 1)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)(3)
(NOTE 2)
td(BCLK-HLDA)
HLDA Output Delay Time
ns
40
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 )x10
------------------------------------ – 40 [ ns ]
n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC1)
by a circuit of the right figure.
For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC1 / VCC1)
= 6.7ns.
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 47 of 53
R
DBi
C
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in
Event Counter Mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.9
Timing Diagram (1)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 48 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 5.10
Timing Diagram (2)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 49 of 53
th(C-D)
M16C/30P Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA output
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
td(BCLK−HLDA)
Hi−Z
NOTES:
1. These pins are set to high-impedance regardless of the input level of the BYTE pin,
PM06 bit in PM0 register.
Measuring conditions :
· VCC1=VCC2=3V
· Input timing voltage : Determined with V IL=0.6V, VIH=2.4V
· Output timing voltage : Determined with V OL=1.5V, VOH=1.5V
Figure 5.11
Timing Diagram (3)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 50 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
0ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
ADi
BHE
0ns.min
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
30ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
0ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
0ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
30ns.max
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.12
Timing Diagram (4)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 51 of 53
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
0ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
0ns.min
ADi
BHE
td(BCLK−ALE)
th(RD−AD)
th(BCLK−ALE)
0ns.min
−4ns.min
30ns.max
ALE
td(BCLK−RD)
th(BCLK−RD)
30ns.max
0ns.min
RD
tac2(RD−DB)
(1.5 × tcyc−60)ns.max
Hi−Z
DBi
th(RD−DB)
tsu(DB−RD)
0ns.min
50ns.min
Write timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
0ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
0ns.min
ADi
BHE
td(BCLK−ALE)
th(BCLK−ALE)
th(WR−AD)
(0.5 × tcyc−10)ns.min
−4ns.min
30ns.max
ALE
td(BCLK−WR)
30ns.max
th(BCLK−WR)
0ns.min
WR,WRL,
WRH
td(BCLK−DB)
th(BCLK−DB)
40ns.max
4ns.min
Hi−Z
DBi
td(DB−WR)
tcyc=
(0.5 × tcyc−40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.13
Timing Diagram (5)
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
Page 52 of 53
th(WR−DB)
(0.5 × tcyc−10)ns.min
M16C/30P Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section
of the Renesas Technology website.
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-QFP100-14x20-0.65
PRQP0100JB-A
100P6S-A
1.6g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
Dimension in Millimeters
Min
Nom
Max
D
19.8
20.0
20.2
E
13.8
14.0
14.2
2.8
A2
30
Index mark
ZD
c
F
A2
1
HD
22.5
22.8
23.1
HE
16.5
16.8
17.1
A1
0
0.1
0.2
bp
0.25
0.3
0.4
c
0.13
0.15
A1
A
A
L
*3
e
y
3.05
0°
bp
Detail F
e
0.5
0.65
y
0.575
ZD
JEITA Package Code
RENESAS Code
P-LQFP100-14x14-0.50
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
0.8
0.10
ZE
L
0.2
10°
0.825
0.4
0.6
0.8
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
Terminal cross section
26
Nom
Max
D
13.9
14.0
14.1
E
13.9
14.0
14.1
A2
ZE
100
Dimension in Millimeters
Min
1.4
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A1
0.05
0.1
0.15
bp
0.15
0.20
0.25
A
1
25
Index mark
ZD
F
1.7
b1
0.09
c
0°
e
*3
bp
A1
e
y
L
x
L1
Detail F
Page 53 of 53
8°
0.08
x
y
0.08
1.0
1.0
ZE
L1
0.20
0.5
ZD
L
Rev.1.22 Mar 30, 2007
REJ03B0088-0122
0.145
0.125
c1
A2
A
c
0.18
0.35
0.5
1.0
0.65
REVISION HISTORY
M16C/30P Group Datasheet
Description
Rev.
Date
0.70
Aug 26, 2004
−
First Edition issued
0.80
Mar 18, 2005
−
development support tools -> development tools
−
BCLK -> CPU clock
2
Table 1.1 Performance Outline of M16C/30P Group
Serial interface is revised.
4
Figure 1.2 Type., Memory Size, and Package is partly revised.
8
Table 1.4 Pin Detection (2) is partly revised.
20
Note 2 Table 5.3 A/D Conversion Characteristics is partly revised.
21
Symbol of Table 5.4 Power Supply Circuit Timing Characteristics is partly
revised.
22
Table 5.5 Electrical Characteristics is revised.
28
Table 5.19 Electrical Characteristics is revised.
1.00
Sep 01, 2005
Page
Summary
2
Table 1.1 Performance Outline of M16C/30P Group is partly revised.
4
Table 1.2 Product List is partly revised.
Figure 1.2 Type No., Memory Size, and Package is partly revised.
5
Figure 1.3 Pin Configuration is partly revised.
6
Figure 1.4 Pin Configuration is partly revised.
7-8
Tables 1.3 to 1.4 Pin Characteristics are added.
9
Table 1.5 Pin Description is revised.
14
3. Memory is partly revised.
15
Table 4.1 SFR Information is partly revised.
19
Table 4.5 SFR Information is partly revised
21
Table 5.2 Recommended Operating Conditions is partly revised.
22
Table 5.3 A/D Conversion Characteristics is partly revised.
25
Note 1 is added in Table 5.6 External Clock Input (XIN input)
Table 5.7 Memory Expansion Mode and Microprocessor Mode is added.
28
Table 5.20 Memory Expansion Mode and Microprocessor Modes (for
setting with no wait) is added.
Figure 5.2 Ports P0 to P10 Measurement Circuit is added.
29
Table 5.21 Memory Expansion Mode and Microprocessor Modes (for 1- to
3-wait setting and external area access) is added.
32
Figure 5.5 Timing Diagram (3) is added.
33
Figure 5.6 Timing Diagram (4) is added.
34
Figure 5.7 Timing Diagram (5) is added.
36
Note 1 to 4 are added in Table 5.23 External Clock Input (XIN input)
Table 5.24 Memory Expansion Mode and Microprocessor Mode is added.
39
Table 5.37 Memory Expansion Mode and Microprocessor Modes (for
setting with no wait) is added.
Figure 5.8 Ports P0 to P10 Measurement Circuit is added.
40
Table 5.38 Memory Expansion Mode and Microprocessor Modes (for 1- to
3-wait setting and external area access) is added.
43
Figure 5.11 Timing Diagram (3) is added.
C-1
REVISION HISTORY
Rev.
1.10
Date
Oct 01, 2005
M16C/30P Group Datasheet
Description
Page
Summary
44
Figure 5.12 Timing Diagram (4) is added.
45
Figure 5.13 Timing Diagram (5) is added.
2
Table 1.1 Performance Outline of M16C/30P Group is partly revised.
4
Table 1.2 Product List is partly revised.
Figure 1.2 Type No., Memory Size, and Package is partly revised.
5
Table 1.3 Product Code of Mask ROM version Version for M16C/30P is
added.
Figure 1.3 Marking Diagram of Mask ROM Version for M16C/30P is
added.
1.11
May 31, 2006
6
Figure 1.4 Marking Diagram of ROM -less Version for M16C/30P is added.
6
Table 1.4 Product Code of ROM-less version for M16C/30P is added.
16
Figure 3.1 Memory Map is partly added.
23
Table 5.2 information is revised.
4
1.4 Product List information is revised.
Table 1.2 Product List is partly revised.
5
Figure 1.2 Type No., Memory Size, and Package is partly added.
7
Table 1.4 Product Code of Flash Memory version and ROM-less version
for M16C/30P is partly revised.
Figure 1.4 Marking Diagram of Flash Memory version and ROM-less
Version for M16C/30P (Top View) is partly added.
17
3. Memory information is revised.
18
Table 4.1 SFR Information(1) is partly revised.
19
Table 4.2 SFR Information(2) is partly added.
23
Table 5.1 Absolute Maximum Ratings information is revised.
26
Table 5.4 Flash Memory Version Electrical Characteristics is added.
28
Table 5.5 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is added.
Table 5.7 Electrical Characteristics(1) is partly deleted.
29
Table 5.8 Electrical Characteristics (2) is partly revised.
33
Table 5.23 Memory Expansion and Microprocessor Modes
NOTES 3 is partly revised.
34
Table 5.24 Memory Expansion and Microprocessor Modes
NOTES 3 is partly revised.
40
Table 5.25 Electrical Characteristics (1) is partly deleted.
41
Table 5.26 Electrical Characteristics (2) is partly revised.
45
Table 5.41 Memory Expansion and Microprocessor Modes
NOTES 3 is partly revised.
46
Table 5.42 Memory Expansion and Microprocessor Modes
NOTES 3 is partly revised.
Figure 3.1 Memory Map is partly revised.
C-2
REVISION HISTORY
Rev.
Date
1.20
Oct 17, 2006
M16C/30P Group Datasheet
Description
Page
Summary
1
Note is partly deleted.
2
Table 1.1 Performance Outline of M16C/30P Group is partly added.
4
Table 1.2 Product List is partly revised.
5
Figure 1.2 Type No., Memory Size, and Package is added.
7
Table 1.4 Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P is partly added.
Figure 3.1 Memory Map is partly added.
17
19
Table 4.2 SFR Information (2) is partly added.
23
Table 5.1 Absolute Maximum Ratings is partly added.
27
Table 5.6 One Time Flash Version Electrical Characteristics and
Table 5.7 One Time Flash Version Program Voltage and Read Operation
Voltage Characteristics is added.
30
Table 5.10 Electrical Characteristics (2) is partly added.
42
Table 5.28 Electrical Characteristics (2) is partly added.
1.21
Nov 02 2006
7
Table 1.4 Product Code of One Time Flash version, Flash Memory
version, and ROM-less version for M16C/30P is partly revised.
1.22
Mar 30, 2007
4
Table 1.2 Product List (1) is partly revised.
5
Table 1.3 Product List (2) is partly revised.
19
Table 4.2 SFR Information (2) is partly revised.
C-3
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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