REJ09B0014-0100Z
32182 Group
32
User's Manual
RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER
M32R FAMILY / M32R/ECU SERIES
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Rev. 1.00
Revision date: Jun 4, 2003
www.renesas.com
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32182 Group User’s Manual
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Jun 4, 2003
–
First edition issued
(1/1)
Table of contents
CHAPTER 1 OVERVIEW
1.1 Outline of the 32182 Group --------------------------------------------------------------------------------------------- 1-2
1.1.1
M32R Family CPU Core with Built-in FPU (M32R-FPU) --------------------------------------------- 1-2
1.1.2
Built-in Multiplier/Accumulator ------------------------------------------------------------------------------- 1-3
1.1.3
Built-in Single-precision FPU -------------------------------------------------------------------------------- 1-3
1.1.4
Built-in Flash Memory and RAM ---------------------------------------------------------------------------- 1-3
1.1.5
Built-in Clock Frequency Multiplier ------------------------------------------------------------------------- 1-4
1.1.6
Powerful Peripheral Functions Built-in -------------------------------------------------------------------- 1-4
1.2 Block Diagram -------------------------------------------------------------------------------------------------------------- 1-5
1.3 Pin Functions --------------------------------------------------------------------------------------------------------------- 1-8
1.4 Pin Assignments ----------------------------------------------------------------------------------------------------------- 1-14
CHAPTER 2 CPU
2.1 CPU Registers ------------------------------------------------------------------------------------------------------------- 2-2
2.2 General-purpose Registers --------------------------------------------------------------------------------------------- 2-2
2.3 Control Registers ---------------------------------------------------------------------------------------------------------- 2-2
2.3.1
Processor Status Word Register: PSW (CR0) ---------------------------------------------------------- 2-3
2.3.2
Condition Bit Register: CBR (CR1) ------------------------------------------------------------------------ 2-4
2.3.3
Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) ------------------------- 2-4
2.3.4
Backup PC: BPC (CR6) -------------------------------------------------------------------------------------- 2-4
2.3.5
Floating-point Status Register: FPSR (CR7) ------------------------------------------------------------ 2-5
2.4 Accumulator ----------------------------------------------------------------------------------------------------------------- 2-7
2.5 Program Counter ---------------------------------------------------------------------------------------------------------- 2-7
2.6 Data Formats --------------------------------------------------------------------------------------------------------------- 2-8
2.6.1
Data Types ------------------------------------------------------------------------------------------------------- 2-8
2.6.2
Data Formats ---------------------------------------------------------------------------------------------------- 2-9
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution ----------------- 2-14
CHAPTER 3 ADDRESS SPACE
3.1 Outline of the Address Space ------------------------------------------------------------------------------------------ 3-2
3.2 Operation Modes ---------------------------------------------------------------------------------------------------------- 3-5
3.3 Internal ROM and Extended External Areas ------------------------------------------------------------------------ 3-9
3.3.1
Internal ROM Area --------------------------------------------------------------------------------------------- 3-9
3.3.2
Extended External Area -------------------------------------------------------------------------------------- 3-9
3.4 Internal RAM and SFR Areas ------------------------------------------------------------------------------------------ 3-10
3.4.1
Internal RAM Area --------------------------------------------------------------------------------------------- 3-10
3.4.2
SFR (Special Function Register) Area -------------------------------------------------------------------- 3-10
3.5 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 3-33
3.6 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 3-34
3.7 Notes about Address Space -------------------------------------------------------------------------------------------- 3-36
(1)
CHAPTER 4 EIT
4.1 Outline of EIT --------------------------------------------------------------------------------------------------------------- 4-2
4.2 EIT Events ------------------------------------------------------------------------------------------------------------------ 4-3
4.2.1
Exception --------------------------------------------------------------------------------------------------------- 4-3
4.2.2
Interrupt ----------------------------------------------------------------------------------------------------------- 4-5
4.2.3
Trap ---------------------------------------------------------------------------------------------------------------- 4-6
4.3 EIT Processing Procedure ---------------------------------------------------------------------------------------------- 4-6
4.4 EIT Processing Mechanism --------------------------------------------------------------------------------------------- 4-7
4.5 Acceptance of EIT Events ----------------------------------------------------------------------------------------------- 4-8
4.6 Saving and Restoring the PC and PSW ----------------------------------------------------------------------------- 4-8
4.7 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 4-10
4.8 Exception Processing ---------------------------------------------------------------------------------------------------- 4-11
4.8.1
Reserved Instruction Exception (RIE) --------------------------------------------------------------------- 4-11
4.8.2
Address Exception (AE) -------------------------------------------------------------------------------------- 4-12
4.8.3
Floating-Point Exception (FPE) ----------------------------------------------------------------------------- 4-13
4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------ 4-15
4.9.1
Reset Interrupt (RI) -------------------------------------------------------------------------------------------- 4-15
4.9.2
System Break Interrupt (SBI) -------------------------------------------------------------------------------- 4-15
4.9.3
External Interrupt (EI) ----------------------------------------------------------------------------------------- 4-17
4.10 Trap Processing ---------------------------------------------------------------------------------------------------------- 4-18
4.10.1 Trap ---------------------------------------------------------------------------------------------------------------- 4-18
4.11 EIT Priority Levels ------------------------------------------------------------------------------------------------------- 4-19
4.12 Example of EIT Processing ------------------------------------------------------------------------------------------- 4-20
4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------ 4-22
CHAPTER 5 INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller -------------------------------------------------------------------------------------- 5-2
5.2 ICU Related Registers --------------------------------------------------------------------------------------------------- 5-4
5.2.1
Interrupt Vector Register ------------------------------------------------------------------------------------- 5-5
5.2.2
Interrupt Request Mask Register --------------------------------------------------------------------------- 5-6
5.2.3
SBI (System Break Interrupt) Control Register --------------------------------------------------------- 5-7
5.2.4
Interrupt Control Registers ----------------------------------------------------------------------------------- 5-8
5.3 Interrupt Request Sources in Internal Peripheral I/O ------------------------------------------------------------- 5-11
5.4 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 5-12
5.5 Description of Interrupt Operation ------------------------------------------------------------------------------------- 5-13
5.5.1
Acceptance of Internal Peripheral I/O Interrupts ------------------------------------------------------- 5-13
5.5.2
Processing by Internal Peripheral I/O Interrupt Handlers -------------------------------------------- 5-15
5.6 Description of System Break Interrupt (SBI) Operation ---------------------------------------------------------- 5-18
5.6.1
Acceptance of SBI --------------------------------------------------------------------------------------------- 5-18
5.6.2
SBI Processing by Handler ---------------------------------------------------------------------------------- 5-18
CHAPTER 6 INTERNAL MEMORY
6.1 Outline of the Internal Memory ----------------------------------------------------------------------------------------- 6-2
6.2 Internal RAM ---------------------------------------------------------------------------------------------------------------- 6-2
6.3 Internal Flash Memory --------------------------------------------------------------------------------------------------- 6-2
(2)
6.4 Registers Associated with the Internal Flash Memory ----------------------------------------------------------- 6-5
6.4.1
Flash Mode Register ------------------------------------------------------------------------------------------ 6-5
6.4.2
Flash Status Registers ---------------------------------------------------------------------------------------- 6-6
6.4.3
Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-6
6.4.4
Flash Control Registers --------------------------------------------------------------------------------------- 6-8
6.4.5
Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-12
6.5 Programming the Internal Flash Memory ---------------------------------------------------------------------------- 6-13
6.5.1
Outline of Internal Flash Memory Programming -------------------------------------------------------- 6-13
6.5.2
Controlling Operation Modes during Flash Programming -------------------------------------------- 6-18
6.5.3
Procedure for Programming/Erasing the Internal Flash Memory ---------------------------------- 6-21
6.5.4
Flash Programming Time (Reference) -------------------------------------------------------------------- 6-30
6.6 Virtual Flash Emulation Function -------------------------------------------------------------------------------------- 6-31
6.6.1
Virtual Flash Emulation Area -------------------------------------------------------------------------------- 6-32
6.6.2
Entering Virtual Flash Emulation Mode ------------------------------------------------------------------- 6-35
6.6.3
Application Example of Virtual Flash Emulation Mode ------------------------------------------------ 6-36
6.7 Connecting to A Serial Programmer ---------------------------------------------------------------------------------- 6-38
6.8 Internal Flash Memory Protect Function ----------------------------------------------------------------------------- 6-40
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory -------------------------------------- 6-41
CHAPTER 7 RESET
7.1 Outline of Reset ------------------------------------------------------------------------------------------------------------ 7-2
7.2 Reset Operation ----------------------------------------------------------------------------------------------------------- 7-2
7.2.1
Reset at Power-on --------------------------------------------------------------------------------------------- 7-3
7.2.2
Reset during Operation --------------------------------------------------------------------------------------- 7-3
7.2.3
Reset at Entering RAM Backup Mode -------------------------------------------------------------------- 7-3
7.2.4
Reset Vector Relocation during Flash Programming -------------------------------------------------- 7-3
7.3 Internal State Immediately after Reset ------------------------------------------------------------------------------- 7-4
7.4 Things to Be Considered after Reset --------------------------------------------------------------------------------- 7-4
CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.1 Outline of Input/Output Ports ------------------------------------------------------------------------------------------- 8-2
8.2 Selecting Pin Functions -------------------------------------------------------------------------------------------------- 8-3
8.3 Input/Output Port Related Registers ---------------------------------------------------------------------------------- 8-5
8.3.1
Port Data Registers -------------------------------------------------------------------------------------------- 8-7
8.3.2
Port Direction Registers -------------------------------------------------------------------------------------- 8-8
8.3.3
Port Operation Mode Registers ----------------------------------------------------------------------------- 8-9
8.3.4
Port Peripheral Output Select Registers ------------------------------------------------------------------ 8-20
8.3.5
Port Input Special Function Control Register ------------------------------------------------------------ 8-21
8.4 Port Input Level Switching Function ---------------------------------------------------------------------------------- 8-24
8.5 Port Peripheral Circuits -------------------------------------------------------------------------------------------------- 8-27
8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------ 8-31
(3)
CHAPTER 9 DMAC
9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2
9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4
9.2.1
DMA Channel Control Registers --------------------------------------------------------------------------- 9-6
9.2.2
DMA Software Request Generation Registers ---------------------------------------------------------- 9-18
9.2.3
DMA Source Address Registers ---------------------------------------------------------------------------- 9-19
9.2.4
DMA Destination Address Registers ---------------------------------------------------------------------- 9-20
9.2.5
DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21
9.2.6
DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22
9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27
9.3.1
DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27
9.3.2
DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33
9.3.3
Starting DMA ---------------------------------------------------------------------------------------------------- 9-34
9.3.4
DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34
9.3.5
Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34
9.3.6
Transfer Units --------------------------------------------------------------------------------------------------- 9-35
9.3.7
Transfer Counts ------------------------------------------------------------------------------------------------- 9-35
9.3.8
Address Space -------------------------------------------------------------------------------------------------- 9-35
9.3.9
Transfer Operation --------------------------------------------------------------------------------------------- 9-35
9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37
9.3.11 Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37
9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38
CHAPTER 10 MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2
10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-8
10.2.1
MJT Common Unit Register Map -------------------------------------------------------------------------- 10-9
10.2.2
Prescaler Unit -------------------------------------------------------------------------------------------------- 10-10
10.2.3
Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-11
10.2.4
Input Processing Control Unit ------------------------------------------------------------------------------ 10-15
10.2.5
Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-21
10.2.6
Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-26
10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-43
10.3.1 Outline of TOP -------------------------------------------------------------------------------------------------- 10-43
10.3.2 Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-45
10.3.3 TOP Related Register Map ---------------------------------------------------------------------------------- 10-47
10.3.4 TOP Control Registers ---------------------------------------------------------------------------------------- 10-49
10.3.5 TOP Counters (TOP0CT–TOP10CT) --------------------------------------------------------------------- 10-54
10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) ----------------------------------------------------------- 10-55
10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) ----------------------------------------------------- 10-56
10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------ 10-57
10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-59
10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-65
10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-70
(4)
10.4 TIO (Input/Output-Related 16-Bit Timer) --------------------------------------------------------------------------- 10-73
10.4.1 Outline of TIO --------------------------------------------------------------------------------------------------- 10-73
10.4.2 Outline of Each Mode of TIO -------------------------------------------------------------------------------- 10-75
10.4.3 TIO Related Register Map ----------------------------------------------------------------------------------- 10-78
10.4.4 TIO Control Registers ----------------------------------------------------------------------------------------- 10-80
10.4.5 TIO Counters (TIO0CT–TIO9CT) -------------------------------------------------------------------------- 10-88
10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) --------------------------------------------- 10-89
10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ---------------------------------------------------------- 10-90
10.4.8 TIO Enable Control Registers ------------------------------------------------------------------------------- 10-91
10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-93
10.4.10 Operation in TIO Noise Processing Input Mode -------------------------------------------------------- 10-95
10.4.11 Operation in TIO PWM Output Mode ---------------------------------------------------------------------- 10-96
10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ----------------------- 10-99
10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ----------- 10-101
10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ----------------------- 10-103
10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-105
10.5.1 Outline of TMS -------------------------------------------------------------------------------------------------- 10-105
10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------ 10-105
10.5.3 TMS Related Register Map ---------------------------------------------------------------------------------- 10-107
10.5.4 TMS Control Registers ---------------------------------------------------------------------------------------- 10-108
10.5.5 TMS Counters (TMS0CT, TMS1CT) ---------------------------------------------------------------------- 10-109
10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ---------------------------------------------- 10-109
10.5.7 Operation of TMS Measure Input -------------------------------------------------------------------------- 10-110
10.6 TML (Input-Related 32-Bit Timer) ------------------------------------------------------------------------------------ 10-111
10.6.1 Outline of TML -------------------------------------------------------------------------------------------------- 10-111
10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------ 10-112
10.6.3 TML Related Register Map ---------------------------------------------------------------------------------- 10-112
10.6.4 TML Control Registers ---------------------------------------------------------------------------------------- 10-113
10.6.5 TML Counters --------------------------------------------------------------------------------------------------- 10-114
10.6.6 TML Measure Registers -------------------------------------------------------------------------------------- 10-114
10.6.7 Operation of TML Measure Input --------------------------------------------------------------------------- 10-115
CHAPTER 11 A-D CONVERTER
11.1 Outline of A-D Converter ----------------------------------------------------------------------------------------------- 11-2
11.1.1 Conversion Modes --------------------------------------------------------------------------------------------- 11-5
11.1.2 Operation Modes ----------------------------------------------------------------------------------------------- 11-5
11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-8
11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-11
11.1.5 Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-11
11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-12
11.2.1 A-D Single Mode Register 0 --------------------------------------------------------------------------------- 11-14
11.2.2 A-D Single Mode Register 1 --------------------------------------------------------------------------------- 11-16
11.2.3 A-D Scan Mode Register 0 ---------------------------------------------------------------------------------- 11-18
11.2.4 A-D Scan Mode Register 1 ---------------------------------------------------------------------------------- 11-20
11.2.5 A-D Conversion Speed Control Register ----------------------------------------------------------------- 11-22
(5)
11.2.6 A-D Disconnection Detection Assist Function Control Register ------------------------------------ 11-23
11.2.7 A-D Disconnection Detection Assist Method Select Register --------------------------------------- 11-24
11.2.8 A-D Successive Approximation Register ----------------------------------------------------------------- 11-27
11.2.9 A-D Comparate Data Register ------------------------------------------------------------------------------ 11-28
11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------ 11-29
11.2.11 8-bit A-D Data Registers -------------------------------------------------------------------------------------- 11-30
11.3 Functional Description of A-D Converter --------------------------------------------------------------------------- 11-31
11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------ 11-31
11.3.2 A-D Conversion by Successive Approximation Method ---------------------------------------------- 11-32
11.3.3 Comparator Operation ---------------------------------------------------------------------------------------- 11-33
11.3.4 Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-34
11.3.5 Accuracy of A-D Conversion -------------------------------------------------------------------------------- 11-37
11.4 Inflow Current Bypass Circuit ----------------------------------------------------------------------------------------- 11-39
11.5 Precautions on Using A-D Converter ------------------------------------------------------------------------------- 11-41
CHAPTER 12 SERIAL I/O
12.1 Outline of Serial I/O ----------------------------------------------------------------------------------------------------- 12-2
12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------ 12-5
12.2.1 SIO Interrupt Related Registers ---------------------------------------------------------------------------- 12-6
12.2.2 SIO Transmit Control Registers ---------------------------------------------------------------------------- 12-13
12.2.3 SIO Transmit/Receive Mode Registers ------------------------------------------------------------------- 12-14
12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------ 12-17
12.2.5 SIO Receive Buffer Registers ------------------------------------------------------------------------------- 12-18
12.2.6 SIO Receive Control Registers ----------------------------------------------------------------------------- 12-19
12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------ 12-22
12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-23
12.3.1 Setting the CSIO Baud Rate --------------------------------------------------------------------------------- 12-23
12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------ 12-24
12.3.3 Starting CSIO Transmission --------------------------------------------------------------------------------- 12-26
12.3.4 Successive CSIO Transmission ---------------------------------------------------------------------------- 12-26
12.3.5 Processing at End of CSIO Transmission ---------------------------------------------------------------- 12-27
12.3.6 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-27
12.3.7 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-27
12.3.8 Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-29
12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-31
12.4.1 Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-31
12.4.2 Starting CSIO Reception ------------------------------------------------------------------------------------- 12-33
12.4.3 Processing at End of CSIO Reception -------------------------------------------------------------------- 12-33
12.4.4 About Successive Reception -------------------------------------------------------------------------------- 12-34
12.4.5 Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-35
12.4.6 Example of CSIO Receive Operation --------------------------------------------------------------------- 12-36
12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-38
12.6 Transmit Operation in UART Mode --------------------------------------------------------------------------------- 12-39
12.6.1 Setting the UART Baud Rate -------------------------------------------------------------------------------- 12-39
12.6.2 UART Transmit/Receive Data Formats ------------------------------------------------------------------- 12-39
12.6.3 Initializing UART Transmission ----------------------------------------------------------------------------- 12-41
12.6.4 Starting UART Transmission -------------------------------------------------------------------------------- 12-43
(6)
12.6.5 Successive UART Transmission --------------------------------------------------------------------------- 12-43
12.6.6 Processing at End of UART Transmission --------------------------------------------------------------- 12-43
12.6.7 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-43
12.6.8 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-44
12.6.9 Example of UART Transmit Operation -------------------------------------------------------------------- 12-45
12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-47
12.7.1 Initialization for UART Reception --------------------------------------------------------------------------- 12-47
12.7.2 Starting UART Reception ------------------------------------------------------------------------------------ 12-49
12.7.3 Processing at End of UART Reception ------------------------------------------------------------------- 12-49
12.7.4 Example of UART Receive Operation -------------------------------------------------------------------- 12-51
12.7.5 Start Bit Detection during UART Reception -------------------------------------------------------------- 12-53
12.8 Fixed Period Clock Output Function -------------------------------------------------------------------------------- 12-54
12.9 Precautions on Using UART Mode ---------------------------------------------------------------------------------- 12-55
CHAPTER 13 CAN MODULE
13.1 Outline of the CAN Module -------------------------------------------------------------------------------------------- 13-2
13.2 CAN Module Related Registers -------------------------------------------------------------------------------------- 13-4
13.2.1 CAN Control Registers ---------------------------------------------------------------------------------------- 13-15
13.2.2 CAN Status Registers ----------------------------------------------------------------------------------------- 13-18
13.2.3 CAN Frame Format Select Registers --------------------------------------------------------------------- 13-21
13.2.4 CAN Configuration Registers -------------------------------------------------------------------------------- 13-22
13.2.5 CAN Timestamp Count Registers -------------------------------------------------------------------------- 13-24
13.2.6 CAN Error Count Registers ---------------------------------------------------------------------------------- 13-25
13.2.7 CAN Baud Rate Prescalers ---------------------------------------------------------------------------------- 13-26
13.2.8 CAN Interrupt Related Registers --------------------------------------------------------------------------- 13-27
13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------ 13-45
13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------ 13-46
13.2.11 CAN DMA Transfer Request Select Register ----------------------------------------------------------- 13-47
13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------ 13-48
13.2.13 CAN Single-Shot Mode Control Registers --------------------------------------------------------------- 13-52
13.2.14 CAN Message Slot Control Registers --------------------------------------------------------------------- 13-53
13.2.15 CAN Message Slots ------------------------------------------------------------------------------------------- 13-57
13.3 CAN Protocol ------------------------------------------------------------------------------------------------------------- 13-72
13.3.1 CAN Protocol Frames ----------------------------------------------------------------------------------------- 13-72
13.3.2 Data Formats during CAN Transmission/Reception --------------------------------------------------- 13-73
13.3.3 CAN Controller Error States --------------------------------------------------------------------------------- 13-74
13.4 Initializing the CAN Module -------------------------------------------------------------------------------------------- 13-75
13.4.1 Initializing the CAN Module ---------------------------------------------------------------------------------- 13-75
13.5 Transmitting Data Frames --------------------------------------------------------------------------------------------- 13-78
13.5.1 Data Frame Transmit Procedure --------------------------------------------------------------------------- 13-78
13.5.2 Data Frame Transmit Operation ---------------------------------------------------------------------------- 13-79
13.5.3 Transmit Abort Function -------------------------------------------------------------------------------------- 13-80
13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------ 13-81
13.6.1 Data Frame Receive Procedure ---------------------------------------------------------------------------- 13-81
13.6.2 Data Frame Receive Operation ----------------------------------------------------------------------------- 13-82
13.6.3 Reading Out Received Data Frames ---------------------------------------------------------------------- 13-84
(7)
13.7 Transmitting Remote Frames ---------------------------------------------------------------------------------------- 13-86
13.7.1 Remote Frame Transmit Procedure ----------------------------------------------------------------------- 13-86
13.7.2 Remote Frame Transmit Operation ------------------------------------------------------------------------ 13-87
13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ------------- 13-89
13.8 Receiving Remote Frames -------------------------------------------------------------------------------------------- 13-91
13.8.1 Remote Frame Receive Procedure ------------------------------------------------------------------------ 13-91
13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------ 13-92
13.9 Precautions about CAN Module -------------------------------------------------------------------------------------- 13-95
CHAPTER 14 REAL TIME DEBUGGER (RTD)
14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------ 14-2
14.2 Pin Functions of the RTD ---------------------------------------------------------------------------------------------- 14-3
14.3 Functional Description of the RTD ----------------------------------------------------------------------------------- 14-4
14.3.1
Outline of the RTD Operation ------------------------------------------------------------------------------ 14-4
14.3.2
Operation of RDR (Real-time RAM Content Output) ------------------------------------------------- 14-4
14.3.3
Operation of the WRR (RAM Content Forcible Rewrite) --------------------------------------------- 14-6
14.3.4
Operation of VER (Continuous Monitor) ----------------------------------------------------------------- 14-7
14.3.5
Operation of VEI (Interrupt Request) --------------------------------------------------------------------- 14-7
14.3.6
Operation of RCV (Recover from Runaway) ----------------------------------------------------------- 14-8
14.3.7
Method for Setting a Specified Address when Using the RTD ------------------------------------- 14-9
14.3.8
Resetting the RTD --------------------------------------------------------------------------------------------- 14-10
14.4 Typical Connection with the Host ------------------------------------------------------------------------------------ 14-11
CHAPTER 15 EXTERNAL BUS INTERFACE
15.1 Outline of the External Bus Interface ------------------------------------------------------------------------------- 15-2
15.1.1
External Bus Interface Related Signals ------------------------------------------------------------------ 15-2
15.2 External Bus Interface Related Registers ------------------------------------------------------------------------- 15-4
15.2.1
Port Operation Mode Registers ---------------------------------------------------------------------------- 15-4
15.2.2
Port Peripheral Output Select Register ------------------------------------------------------------------ 15-8
15.2.3
Bus Mode Control Register --------------------------------------------------------------------------------- 15-9
15.3 Read/Write Operations ------------------------------------------------------------------------------------------------- 15-10
15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------ 15-16
15.5 Typical Connection of External Extension Memory ------------------------------------------------------------- 15-18
15.6 Example of Bus Voltage Settings Using VCC-BUS ------------------------------------------------------------- 15-21
CHAPTER 16 WAIT CONTROLLER
16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2
16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4
16.2.1 CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4
16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6
CHAPTER 17 RAM BACKUP MODE
17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2
17.2 Example of RAM Backup when Power is Off -------------------------------------------------------------------------- 17-3
17.2.1 Normal Operating State --------------------------------------------------------------------------------------- 17-3
17.2.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-4
(8)
17.3 Example of RAM Backup for Saving Power Consumption ---------------------------------------------------- 17-5
17.3.1 Normal Operating State --------------------------------------------------------------------------------------- 17-5
17.3.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-6
17.3.3 Precautions to Be Observed at Power-On --------------------------------------------------------------- 17-7
17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------ 17-8
CHAPTER 18 OSCILLATOR CIRCUIT
18.1 Oscillator Circuit ---------------------------------------------------------------------------------------------------------- 18-2
18.1.1 Example of an Oscillator Circuit ---------------------------------------------------------------------------- 18-2
18.1.2 XIN Oscillation Stoppage Detection Circuit -------------------------------------------------------------- 18-3
18.1.3 Oscillation Drive Capability Select Function ------------------------------------------------------------- 18-5
18.1.4 System Clock Output Function ------------------------------------------------------------------------------ 18-7
18.1.5 Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7
18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------ 18-8
CHAPTER 19 JTAG
19.1 Outline of JTAG ---------------------------------------------------------------------------------------------------------- 19-2
19.2 Configuration of the JTAG Circuit ------------------------------------------------------------------------------------ 19-3
19.3 JTAG Registers ---------------------------------------------------------------------------------------------------------- 19-4
19.3.1 Instruction Register (JTAGIR) ------------------------------------------------------------------------------- 19-4
19.3.2 Data Register ---------------------------------------------------------------------------------------------------- 19-5
19.4 Basic Operation of JTAG ---------------------------------------------------------------------------------------------- 19-6
19.4.1 Outline of JTAG Operation ----------------------------------------------------------------------------------- 19-6
19.4.2 IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8
19.4.3 DR Path Sequence -------------------------------------------------------------------------------------------- 19-9
19.4.4 Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10
19.5 Boundary Scan Description Language ----------------------------------------------------------------------------- 19-11
19.6 Notes on Board Design when Connecting JTAG ---------------------------------------------------------------------- 19-12
19.7 Processing Pins when Not Using JTAG ---------------------------------------------------------------------------- 19-13
CHAPTER 20 POWER SUPPLY CIRCUIT
20.1 Configuration of the Power Supply Circuit ------------------------------------------------------------------------- 20-2
20.2 Power-On Sequence ---------------------------------------------------------------------------------------------------- 20-3
20.2.1 Power-On Sequence when Not Using RAM Backup -------------------------------------------------- 20-3
20.2.2 Power-On Sequence when Using RAM Backup -------------------------------------------------------- 20-4
20.3 Power-Off Sequence ---------------------------------------------------------------------------------------------------- 20-5
20.3.1 Power-Off Sequence when Not Using RAM Backup -------------------------------------------------- 20-5
20.3.2 Power-Off Sequence when Using RAM Backup ------------------------------------------------------- 20-6
CHAPTER 21 ELECTRICAL CHARACTERISTICS
21.1 Absolute Maximum Ratings ------------------------------------------------------------------------------------------- 21-2
21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ---------------------------------------------- 21-3
21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) ------------------- 21-3
21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) ----------------------------------------- 21-5
21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -------------------------- 21-6
(9)
21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------ 21-7
21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) -------------------- 21-7
21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ------------------------------------------- 21-9
21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ---------------------------- 21-10
21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz -------------------------------------------- 21-11
21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------ 21-11
21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ---------------------------- 21-13
21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------------- 21-14
21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz ---------------------------------------------- 21-15
21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) -------- 21-15
21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) ------------------------------ 21-17
21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) --------------- 21-18
21.6 Flash Memory Related Characteristics ----------------------------------------------------------------------------- 21-19
21.7 A.C. Characteristics (when VCCE = 5 V) -------------------------------------------------------------------------- 21-20
21.7.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-20
21.7.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-24
21.7.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-27
21.8 A.C. Characteristics (when VCCE = 3.3 V) ----------------------------------------------------------------------- 21-36
21.8.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-36
21.8.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-40
21.8.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-43
CHAPTER 22 TYPICAL CHARACTERISTICS
To be written at a later time --------------------------------------------------------------------------------------------------- 22-2
APPENDIX 1 MECHANICAL SPECIFICAITONS
Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2
APPENDIX 2 INSTRUCTION PROCESSING TIME
Appendix 2.1 32182 Instruction Processing Time ------------------------------------------------------------ Appendix 2-2
APPENDIX 3 PROCESSING OF UNUSED PINS
Appendix 3.1 Example Processing of Unused Pins --------------------------------------------------------- Appendix 3-2
APPENDIX 4 SUMMARY OF PRECAUTIONS
Appendix 4.1 Precautions about the CPU --------------------------------------------------------------------Appendix 4.1.1 Precautions Regarding Data Transfer -----------------------------------------------Appendix 4.2 Precautions about the Address Space ------------------------------------------------------Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------Appendix 4.3 Precautions about EIT --------------------------------------------------------------------------Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory --------Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------Appendix 4.5.1 Input/output Ports --------------------------------------------------------------------------
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Appendix 4-2
Appendix 4-2
Appendix 4-3
Appendix 4-3
Appendix 4-3
Appendix 4-3
Appendix 4-4
Appendix 4-4
Appendix 4.6 Precautions about Input/Output Ports --------------------------------------------------Appendix 4.6.1 When Using Input/Output Ports in Output Mode ------------------------------Appendix 4.6.2 About the Port Input Disable Function -------------------------------------------Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------Appendix 4.7.1 About Writing to the DMAC Related Registers ---------------------------------Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer -------------Appendix 4.7.3 About the DMA Interrupt Request Status Register ----------------------------Appendix 4.7.4 About the Stable Operation of DMA Transfer ----------------------------------Appendix 4.8 Precautions about the Multijunction Timers -------------------------------------------Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode -----------------------Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode -----------Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ------------------------Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes --------Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ---------------------------------Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ------------------------Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode -------------Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode -------------------------Appendix 4.8.9 Precautions on Using TMS Measure Input --------------------------------------Appendix 4.8.10 Precautions on Using TML Measure Input -------------------------------------Appendix 4.9 Precautions about the A-D Converters -------------------------------------------------Appendix 4.10 Precautions about Serial I/O --------------------------------------------------------------Appendix 4.10.1 Precautions on Using CSIO Mode ------------------------------------------------Appendix 4.10.2 Precautions on Using UART Mode -----------------------------------------------Appendix 4.11 Precautions about RAM Backup Mode ------------------------------------------------Appendix 4.11.1 Precautions to Be Observed at Power-On -------------------------------------Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------Appendix 4.12.1 Notes on Board Design when Connecting JTAG ------------------------------Appendix 4.12.2 Processing Pins when Not Using JTAG -----------------------------------------Appendix 4.13 Precautions about Noise ------------------------------------------------------------------Appendix 4.13.1 Reduction of Wiring Length --------------------------------------------------------Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines --------------Appendix 4.13.3 Processing Analog Input Pin Wiring ---------------------------------------------Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ---------------------------Appendix 4.13.5 Processing Input/Output Ports -----------------------------------------------------
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Appendix 4-4
Appendix 4-4
Appendix 4-4
Appendix 4-5
Appendix 4-5
Appendix 4-5
Appendix 4-5
Appendix 4-5
Appendix 4-6
Appendix 4-6
Appendix 4-8
Appendix 4-9
Appendix 4-9
Appendix 4-9
Appendix 4-9
Appendix 4-10
Appendix 4-10
Appendix 4-10
Appendix 4-11
Appendix 4-12
Appendix 4-15
Appendix 4-15
Appendix 4-16
Appendix 4-17
Appendix 4-17
Appendix 4-18
Appendix 4-18
Appendix 4-19
Appendix 4-20
Appendix 4-20
Appendix 4-23
Appendix 4-23
Appendix 4-24
Appendix 4-28
This page is blank for reasons of layout.
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CHAPTER 4 EIT
4.1 Outline of EIT --------------------------------------------------------------------------------------------------------------- 4-2
4.2 EIT Events ------------------------------------------------------------------------------------------------------------------ 4-3
4.2.1
Exception --------------------------------------------------------------------------------------------------------- 4-3
4.2.2
Interrupt ----------------------------------------------------------------------------------------------------------- 4-5
4.2.3
Trap ---------------------------------------------------------------------------------------------------------------- 4-6
4.3 EIT Processing Procedure ---------------------------------------------------------------------------------------------- 4-6
4.4 EIT Processing Mechanism --------------------------------------------------------------------------------------------- 4-7
4.5 Acceptance of EIT Events ----------------------------------------------------------------------------------------------- 4-8
4.6 Saving and Restoring the PC and PSW ----------------------------------------------------------------------------- 4-8
4.7 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 4-10
4.8 Exception Processing ---------------------------------------------------------------------------------------------------- 4-11
4.8.1
Reserved Instruction Exception (RIE) --------------------------------------------------------------------- 4-11
4.8.2
Address Exception (AE) -------------------------------------------------------------------------------------- 4-12
4.8.3
Floating-Point Exception (FPE) ----------------------------------------------------------------------------- 4-13
4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------ 4-15
4.9.1
Reset Interrupt (RI) -------------------------------------------------------------------------------------------- 4-15
4.9.2
System Break Interrupt (SBI) -------------------------------------------------------------------------------- 4-15
4.9.3
External Interrupt (EI) ----------------------------------------------------------------------------------------- 4-17
4.10 Trap Processing ---------------------------------------------------------------------------------------------------------- 4-18
4.10.1 Trap ---------------------------------------------------------------------------------------------------------------- 4-18
4.11 EIT Priority Levels ------------------------------------------------------------------------------------------------------- 4-19
4.12 Example of EIT Processing ------------------------------------------------------------------------------------------- 4-20
4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------ 4-22
CHAPTER 5 INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller -------------------------------------------------------------------------------------- 5-2
5.2 ICU Related Registers --------------------------------------------------------------------------------------------------- 5-4
5.2.1
Interrupt Vector Register ------------------------------------------------------------------------------------- 5-5
5.2.2
Interrupt Request Mask Register --------------------------------------------------------------------------- 5-6
5.2.3
SBI (System Break Interrupt) Control Register --------------------------------------------------------- 5-7
5.2.4
Interrupt Control Registers ----------------------------------------------------------------------------------- 5-8
5.3 Interrupt Request Sources in Internal Peripheral I/O ------------------------------------------------------------- 5-11
5.4 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 5-12
5.5 Description of Interrupt Operation ------------------------------------------------------------------------------------- 5-13
5.5.1
Acceptance of Internal Peripheral I/O Interrupts ------------------------------------------------------- 5-13
5.5.2
Processing by Internal Peripheral I/O Interrupt Handlers -------------------------------------------- 5-15
5.6 Description of System Break Interrupt (SBI) Operation ---------------------------------------------------------- 5-18
5.6.1
Acceptance of SBI --------------------------------------------------------------------------------------------- 5-18
5.6.2
SBI Processing by Handler ---------------------------------------------------------------------------------- 5-18
CHAPTER 6 INTERNAL MEMORY
6.1 Outline of the Internal Memory ----------------------------------------------------------------------------------------- 6-2
6.2 Internal RAM ---------------------------------------------------------------------------------------------------------------- 6-2
6.3 Internal Flash Memory --------------------------------------------------------------------------------------------------- 6-2
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6.4 Registers Associated with the Internal Flash Memory ----------------------------------------------------------- 6-5
6.4.1
Flash Mode Register ------------------------------------------------------------------------------------------ 6-5
6.4.2
Flash Status Registers ---------------------------------------------------------------------------------------- 6-6
6.4.3
Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-6
6.4.4
Flash Control Registers --------------------------------------------------------------------------------------- 6-8
6.4.5
Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-12
6.5 Programming the Internal Flash Memory ---------------------------------------------------------------------------- 6-13
6.5.1
Outline of Internal Flash Memory Programming -------------------------------------------------------- 6-13
6.5.2
Controlling Operation Modes during Flash Programming -------------------------------------------- 6-18
6.5.3
Procedure for Programming/Erasing the Internal Flash Memory ---------------------------------- 6-21
6.5.4
Flash Programming Time (Reference) -------------------------------------------------------------------- 6-30
6.6 Virtual Flash Emulation Function -------------------------------------------------------------------------------------- 6-31
6.6.1
Virtual Flash Emulation Area -------------------------------------------------------------------------------- 6-32
6.6.2
Entering Virtual Flash Emulation Mode ------------------------------------------------------------------- 6-35
6.6.3
Application Example of Virtual Flash Emulation Mode ------------------------------------------------ 6-36
6.7 Connecting to A Serial Programmer ---------------------------------------------------------------------------------- 6-38
6.8 Internal Flash Memory Protect Function ----------------------------------------------------------------------------- 6-40
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory -------------------------------------- 6-41
CHAPTER 7 RESET
7.1 Outline of Reset ------------------------------------------------------------------------------------------------------------ 7-2
7.2 Reset Operation ----------------------------------------------------------------------------------------------------------- 7-2
7.2.1
Reset at Power-on --------------------------------------------------------------------------------------------- 7-3
7.2.2
Reset during Operation --------------------------------------------------------------------------------------- 7-3
7.2.3
Reset at Entering RAM Backup Mode -------------------------------------------------------------------- 7-3
7.2.4
Reset Vector Relocation during Flash Programming -------------------------------------------------- 7-3
7.3 Internal State Immediately after Reset ------------------------------------------------------------------------------- 7-4
7.4 Things to Be Considered after Reset --------------------------------------------------------------------------------- 7-4
CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.1 Outline of Input/Output Ports ------------------------------------------------------------------------------------------- 8-2
8.2 Selecting Pin Functions -------------------------------------------------------------------------------------------------- 8-3
8.3 Input/Output Port Related Registers ---------------------------------------------------------------------------------- 8-5
8.3.1
Port Data Registers -------------------------------------------------------------------------------------------- 8-7
8.3.2
Port Direction Registers -------------------------------------------------------------------------------------- 8-8
8.3.3
Port Operation Mode Registers ----------------------------------------------------------------------------- 8-9
8.3.4
Port Peripheral Output Select Registers ------------------------------------------------------------------ 8-20
8.3.5
Port Input Special Function Control Register ------------------------------------------------------------ 8-21
8.4 Port Input Level Switching Function ---------------------------------------------------------------------------------- 8-24
8.5 Port Peripheral Circuits -------------------------------------------------------------------------------------------------- 8-27
8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------ 8-31
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CHAPTER 9 DMAC
9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2
9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4
9.2.1
DMA Channel Control Registers --------------------------------------------------------------------------- 9-6
9.2.2
DMA Software Request Generation Registers ---------------------------------------------------------- 9-18
9.2.3
DMA Source Address Registers ---------------------------------------------------------------------------- 9-19
9.2.4
DMA Destination Address Registers ---------------------------------------------------------------------- 9-20
9.2.5
DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21
9.2.6
DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22
9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27
9.3.1
DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27
9.3.2
DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33
9.3.3
Starting DMA ---------------------------------------------------------------------------------------------------- 9-34
9.3.4
DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34
9.3.5
Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34
9.3.6
Transfer Units --------------------------------------------------------------------------------------------------- 9-35
9.3.7
Transfer Counts ------------------------------------------------------------------------------------------------- 9-35
9.3.8
Address Space -------------------------------------------------------------------------------------------------- 9-35
9.3.9
Transfer Operation --------------------------------------------------------------------------------------------- 9-35
9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37
9.3.11 Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37
9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38
CHAPTER 10 MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2
10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-8
10.2.1
MJT Common Unit Register Map -------------------------------------------------------------------------- 10-9
10.2.2
Prescaler Unit -------------------------------------------------------------------------------------------------- 10-10
10.2.3
Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-11
10.2.4
Input Processing Control Unit ------------------------------------------------------------------------------ 10-15
10.2.5
Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-21
10.2.6
Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-26
10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-43
10.3.1 Outline of TOP -------------------------------------------------------------------------------------------------- 10-43
10.3.2 Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-45
10.3.3 TOP Related Register Map ---------------------------------------------------------------------------------- 10-47
10.3.4 TOP Control Registers ---------------------------------------------------------------------------------------- 10-49
10.3.5 TOP Counters (TOP0CT–TOP10CT) --------------------------------------------------------------------- 10-54
10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) ----------------------------------------------------------- 10-55
10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) ----------------------------------------------------- 10-56
10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------ 10-57
10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-59
10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-65
10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-70
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10.4 TIO (Input/Output-Related 16-Bit Timer) --------------------------------------------------------------------------- 10-73
10.4.1 Outline of TIO --------------------------------------------------------------------------------------------------- 10-73
10.4.2 Outline of Each Mode of TIO -------------------------------------------------------------------------------- 10-75
10.4.3 TIO Related Register Map ----------------------------------------------------------------------------------- 10-78
10.4.4 TIO Control Registers ----------------------------------------------------------------------------------------- 10-80
10.4.5 TIO Counters (TIO0CT–TIO9CT) -------------------------------------------------------------------------- 10-88
10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) --------------------------------------------- 10-89
10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ---------------------------------------------------------- 10-90
10.4.8 TIO Enable Control Registers ------------------------------------------------------------------------------- 10-91
10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-93
10.4.10 Operation in TIO Noise Processing Input Mode -------------------------------------------------------- 10-95
10.4.11 Operation in TIO PWM Output Mode ---------------------------------------------------------------------- 10-96
10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ----------------------- 10-99
10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ----------- 10-101
10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ----------------------- 10-103
10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-105
10.5.1 Outline of TMS -------------------------------------------------------------------------------------------------- 10-105
10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------ 10-105
10.5.3 TMS Related Register Map ---------------------------------------------------------------------------------- 10-107
10.5.4 TMS Control Registers ---------------------------------------------------------------------------------------- 10-108
10.5.5 TMS Counters (TMS0CT, TMS1CT) ---------------------------------------------------------------------- 10-109
10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ---------------------------------------------- 10-109
10.5.7 Operation of TMS Measure Input -------------------------------------------------------------------------- 10-110
10.6 TML (Input-Related 32-Bit Timer) ------------------------------------------------------------------------------------ 10-111
10.6.1 Outline of TML -------------------------------------------------------------------------------------------------- 10-111
10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------ 10-112
10.6.3 TML Related Register Map ---------------------------------------------------------------------------------- 10-112
10.6.4 TML Control Registers ---------------------------------------------------------------------------------------- 10-113
10.6.5 TML Counters --------------------------------------------------------------------------------------------------- 10-114
10.6.6 TML Measure Registers -------------------------------------------------------------------------------------- 10-114
10.6.7 Operation of TML Measure Input --------------------------------------------------------------------------- 10-115
CHAPTER 11 A-D CONVERTER
11.1 Outline of A-D Converter ----------------------------------------------------------------------------------------------- 11-2
11.1.1 Conversion Modes --------------------------------------------------------------------------------------------- 11-5
11.1.2 Operation Modes ----------------------------------------------------------------------------------------------- 11-5
11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-8
11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-11
11.1.5 Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-11
11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-12
11.2.1 A-D Single Mode Register 0 --------------------------------------------------------------------------------- 11-14
11.2.2 A-D Single Mode Register 1 --------------------------------------------------------------------------------- 11-16
11.2.3 A-D Scan Mode Register 0 ---------------------------------------------------------------------------------- 11-18
11.2.4 A-D Scan Mode Register 1 ---------------------------------------------------------------------------------- 11-20
11.2.5 A-D Conversion Speed Control Register ----------------------------------------------------------------- 11-22
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11.2.6 A-D Disconnection Detection Assist Function Control Register ------------------------------------ 11-23
11.2.7 A-D Disconnection Detection Assist Method Select Register --------------------------------------- 11-24
11.2.8 A-D Successive Approximation Register ----------------------------------------------------------------- 11-27
11.2.9 A-D Comparate Data Register ------------------------------------------------------------------------------ 11-28
11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------ 11-29
11.2.11 8-bit A-D Data Registers -------------------------------------------------------------------------------------- 11-30
11.3 Functional Description of A-D Converter --------------------------------------------------------------------------- 11-31
11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------ 11-31
11.3.2 A-D Conversion by Successive Approximation Method ---------------------------------------------- 11-32
11.3.3 Comparator Operation ---------------------------------------------------------------------------------------- 11-33
11.3.4 Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-34
11.3.5 Accuracy of A-D Conversion -------------------------------------------------------------------------------- 11-37
11.4 Inflow Current Bypass Circuit ----------------------------------------------------------------------------------------- 11-39
11.5 Precautions on Using A-D Converter ------------------------------------------------------------------------------- 11-41
CHAPTER 12 SERIAL I/O
12.1 Outline of Serial I/O ----------------------------------------------------------------------------------------------------- 12-2
12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------ 12-5
12.2.1 SIO Interrupt Related Registers ---------------------------------------------------------------------------- 12-6
12.2.2 SIO Transmit Control Registers ---------------------------------------------------------------------------- 12-13
12.2.3 SIO Transmit/Receive Mode Registers ------------------------------------------------------------------- 12-14
12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------ 12-17
12.2.5 SIO Receive Buffer Registers ------------------------------------------------------------------------------- 12-18
12.2.6 SIO Receive Control Registers ----------------------------------------------------------------------------- 12-19
12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------ 12-22
12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-23
12.3.1 Setting the CSIO Baud Rate --------------------------------------------------------------------------------- 12-23
12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------ 12-24
12.3.3 Starting CSIO Transmission --------------------------------------------------------------------------------- 12-26
12.3.4 Successive CSIO Transmission ---------------------------------------------------------------------------- 12-26
12.3.5 Processing at End of CSIO Transmission ---------------------------------------------------------------- 12-27
12.3.6 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-27
12.3.7 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-27
12.3.8 Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-29
12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-31
12.4.1 Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-31
12.4.2 Starting CSIO Reception ------------------------------------------------------------------------------------- 12-33
12.4.3 Processing at End of CSIO Reception -------------------------------------------------------------------- 12-33
12.4.4 About Successive Reception -------------------------------------------------------------------------------- 12-34
12.4.5 Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-35
12.4.6 Example of CSIO Receive Operation --------------------------------------------------------------------- 12-36
12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-38
12.6 Transmit Operation in UART Mode --------------------------------------------------------------------------------- 12-39
12.6.1 Setting the UART Baud Rate -------------------------------------------------------------------------------- 12-39
12.6.2 UART Transmit/Receive Data Formats ------------------------------------------------------------------- 12-39
12.6.3 Initializing UART Transmission ----------------------------------------------------------------------------- 12-41
12.6.4 Starting UART Transmission -------------------------------------------------------------------------------- 12-43
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12.6.5 Successive UART Transmission --------------------------------------------------------------------------- 12-43
12.6.6 Processing at End of UART Transmission --------------------------------------------------------------- 12-43
12.6.7 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-43
12.6.8 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-44
12.6.9 Example of UART Transmit Operation -------------------------------------------------------------------- 12-45
12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-47
12.7.1 Initialization for UART Reception --------------------------------------------------------------------------- 12-47
12.7.2 Starting UART Reception ------------------------------------------------------------------------------------ 12-49
12.7.3 Processing at End of UART Reception ------------------------------------------------------------------- 12-49
12.7.4 Example of UART Receive Operation -------------------------------------------------------------------- 12-51
12.7.5 Start Bit Detection during UART Reception -------------------------------------------------------------- 12-53
12.8 Fixed Period Clock Output Function -------------------------------------------------------------------------------- 12-54
12.9 Precautions on Using UART Mode ---------------------------------------------------------------------------------- 12-55
CHAPTER 13 CAN MODULE
13.1 Outline of the CAN Module -------------------------------------------------------------------------------------------- 13-2
13.2 CAN Module Related Registers -------------------------------------------------------------------------------------- 13-4
13.2.1 CAN Control Registers ---------------------------------------------------------------------------------------- 13-15
13.2.2 CAN Status Registers ----------------------------------------------------------------------------------------- 13-18
13.2.3 CAN Frame Format Select Registers --------------------------------------------------------------------- 13-21
13.2.4 CAN Configuration Registers -------------------------------------------------------------------------------- 13-22
13.2.5 CAN Timestamp Count Registers -------------------------------------------------------------------------- 13-24
13.2.6 CAN Error Count Registers ---------------------------------------------------------------------------------- 13-25
13.2.7 CAN Baud Rate Prescalers ---------------------------------------------------------------------------------- 13-26
13.2.8 CAN Interrupt Related Registers --------------------------------------------------------------------------- 13-27
13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------ 13-45
13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------ 13-46
13.2.11 CAN DMA Transfer Request Select Register ----------------------------------------------------------- 13-47
13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------ 13-48
13.2.13 CAN Single-Shot Mode Control Registers --------------------------------------------------------------- 13-52
13.2.14 CAN Message Slot Control Registers --------------------------------------------------------------------- 13-53
13.2.15 CAN Message Slots ------------------------------------------------------------------------------------------- 13-57
13.3 CAN Protocol ------------------------------------------------------------------------------------------------------------- 13-72
13.3.1 CAN Protocol Frames ----------------------------------------------------------------------------------------- 13-72
13.3.2 Data Formats during CAN Transmission/Reception --------------------------------------------------- 13-73
13.3.3 CAN Controller Error States --------------------------------------------------------------------------------- 13-74
13.4 Initializing the CAN Module -------------------------------------------------------------------------------------------- 13-75
13.4.1 Initializing the CAN Module ---------------------------------------------------------------------------------- 13-75
13.5 Transmitting Data Frames --------------------------------------------------------------------------------------------- 13-78
13.5.1 Data Frame Transmit Procedure --------------------------------------------------------------------------- 13-78
13.5.2 Data Frame Transmit Operation ---------------------------------------------------------------------------- 13-79
13.5.3 Transmit Abort Function -------------------------------------------------------------------------------------- 13-80
13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------ 13-81
13.6.1 Data Frame Receive Procedure ---------------------------------------------------------------------------- 13-81
13.6.2 Data Frame Receive Operation ----------------------------------------------------------------------------- 13-82
13.6.3 Reading Out Received Data Frames ---------------------------------------------------------------------- 13-84
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13.7 Transmitting Remote Frames ---------------------------------------------------------------------------------------- 13-86
13.7.1 Remote Frame Transmit Procedure ----------------------------------------------------------------------- 13-86
13.7.2 Remote Frame Transmit Operation ------------------------------------------------------------------------ 13-87
13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ------------- 13-89
13.8 Receiving Remote Frames -------------------------------------------------------------------------------------------- 13-91
13.8.1 Remote Frame Receive Procedure ------------------------------------------------------------------------ 13-91
13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------ 13-92
13.9 Precautions about CAN Module -------------------------------------------------------------------------------------- 13-95
CHAPTER 14 REAL TIME DEBUGGER (RTD)
14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------ 14-2
14.2 Pin Functions of the RTD ---------------------------------------------------------------------------------------------- 14-3
14.3 Functional Description of the RTD ----------------------------------------------------------------------------------- 14-4
14.3.1
Outline of the RTD Operation ------------------------------------------------------------------------------ 14-4
14.3.2
Operation of RDR (Real-time RAM Content Output) ------------------------------------------------- 14-4
14.3.3
Operation of the WRR (RAM Content Forcible Rewrite) --------------------------------------------- 14-6
14.3.4
Operation of VER (Continuous Monitor) ----------------------------------------------------------------- 14-7
14.3.5
Operation of VEI (Interrupt Request) --------------------------------------------------------------------- 14-7
14.3.6
Operation of RCV (Recover from Runaway) ----------------------------------------------------------- 14-8
14.3.7
Method for Setting a Specified Address when Using the RTD ------------------------------------- 14-9
14.3.8
Resetting the RTD --------------------------------------------------------------------------------------------- 14-10
14.4 Typical Connection with the Host ------------------------------------------------------------------------------------ 14-11
CHAPTER 15 EXTERNAL BUS INTERFACE
15.1 Outline of the External Bus Interface ------------------------------------------------------------------------------- 15-2
15.1.1
External Bus Interface Related Signals ------------------------------------------------------------------ 15-2
15.2 External Bus Interface Related Registers ------------------------------------------------------------------------- 15-4
15.2.1
Port Operation Mode Registers ---------------------------------------------------------------------------- 15-4
15.2.2
Port Peripheral Output Select Register ------------------------------------------------------------------ 15-8
15.2.3
Bus Mode Control Register --------------------------------------------------------------------------------- 15-9
15.3 Read/Write Operations ------------------------------------------------------------------------------------------------- 15-10
15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------ 15-16
15.5 Typical Connection of External Extension Memory ------------------------------------------------------------- 15-18
15.6 Example of Bus Voltage Settings Using VCC-BUS ------------------------------------------------------------- 15-21
CHAPTER 16 WAIT CONTROLLER
16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2
16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4
16.2.1 CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4
16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6
CHAPTER 17 RAM BACKUP MODE
17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2
17.2 Example of RAM Backup when Power is Off -------------------------------------------------------------------------- 17-3
17.2.1 Normal Operating State --------------------------------------------------------------------------------------- 17-3
17.2.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-4
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17.3 Example of RAM Backup for Saving Power Consumption ---------------------------------------------------- 17-5
17.3.1 Normal Operating State --------------------------------------------------------------------------------------- 17-5
17.3.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-6
17.3.3 Precautions to Be Observed at Power-On --------------------------------------------------------------- 17-7
17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------ 17-8
CHAPTER 18 OSCILLATOR CIRCUIT
18.1 Oscillator Circuit ---------------------------------------------------------------------------------------------------------- 18-2
18.1.1 Example of an Oscillator Circuit ---------------------------------------------------------------------------- 18-2
18.1.2 XIN Oscillation Stoppage Detection Circuit -------------------------------------------------------------- 18-3
18.1.3 Oscillation Drive Capability Select Function ------------------------------------------------------------- 18-5
18.1.4 System Clock Output Function ------------------------------------------------------------------------------ 18-7
18.1.5 Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7
18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------ 18-8
CHAPTER 19 JTAG
19.1 Outline of JTAG ---------------------------------------------------------------------------------------------------------- 19-2
19.2 Configuration of the JTAG Circuit ------------------------------------------------------------------------------------ 19-3
19.3 JTAG Registers ---------------------------------------------------------------------------------------------------------- 19-4
19.3.1 Instruction Register (JTAGIR) ------------------------------------------------------------------------------- 19-4
19.3.2 Data Register ---------------------------------------------------------------------------------------------------- 19-5
19.4 Basic Operation of JTAG ---------------------------------------------------------------------------------------------- 19-6
19.4.1 Outline of JTAG Operation ----------------------------------------------------------------------------------- 19-6
19.4.2 IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8
19.4.3 DR Path Sequence -------------------------------------------------------------------------------------------- 19-9
19.4.4 Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10
19.5 Boundary Scan Description Language ----------------------------------------------------------------------------- 19-11
19.6 Notes on Board Design when Connecting JTAG ---------------------------------------------------------------------- 19-12
19.7 Processing Pins when Not Using JTAG ---------------------------------------------------------------------------- 19-13
CHAPTER 20 POWER SUPPLY CIRCUIT
20.1 Configuration of the Power Supply Circuit ------------------------------------------------------------------------- 20-2
20.2 Power-On Sequence ---------------------------------------------------------------------------------------------------- 20-3
20.2.1 Power-On Sequence when Not Using RAM Backup -------------------------------------------------- 20-3
20.2.2 Power-On Sequence when Using RAM Backup -------------------------------------------------------- 20-4
20.3 Power-Off Sequence ---------------------------------------------------------------------------------------------------- 20-5
20.3.1 Power-Off Sequence when Not Using RAM Backup -------------------------------------------------- 20-5
20.3.2 Power-Off Sequence when Using RAM Backup ------------------------------------------------------- 20-6
CHAPTER 21 ELECTRICAL CHARACTERISTICS
21.1 Absolute Maximum Ratings ------------------------------------------------------------------------------------------- 21-2
21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ---------------------------------------------- 21-3
21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) ------------------- 21-3
21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) ----------------------------------------- 21-5
21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -------------------------- 21-6
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21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------ 21-7
21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) -------------------- 21-7
21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ------------------------------------------- 21-9
21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ---------------------------- 21-10
21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz -------------------------------------------- 21-11
21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------ 21-11
21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ---------------------------- 21-13
21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------------- 21-14
21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz ---------------------------------------------- 21-15
21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) -------- 21-15
21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) ------------------------------ 21-17
21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) --------------- 21-18
21.6 Flash Memory Related Characteristics ----------------------------------------------------------------------------- 21-19
21.7 A.C. Characteristics (when VCCE = 5 V) -------------------------------------------------------------------------- 21-20
21.7.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-20
21.7.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-24
21.7.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-27
21.8 A.C. Characteristics (when VCCE = 3.3 V) ----------------------------------------------------------------------- 21-36
21.8.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-36
21.8.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-40
21.8.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-43
CHAPTER 22 TYPICAL CHARACTERISTICS
To be written at a later time --------------------------------------------------------------------------------------------------- 22-2
APPENDIX 1 MECHANICAL SPECIFICAITONS
Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2
APPENDIX 2 INSTRUCTION PROCESSING TIME
Appendix 2.1 32182 Instruction Processing Time ------------------------------------------------------------ Appendix 2-2
APPENDIX 3 PROCESSING OF UNUSED PINS
Appendix 3.1 Example Processing of Unused Pins --------------------------------------------------------- Appendix 3-2
APPENDIX 4 SUMMARY OF PRECAUTIONS
Appendix 4.1 Precautions about the CPU --------------------------------------------------------------------Appendix 4.1.1 Precautions Regarding Data Transfer -----------------------------------------------Appendix 4.2 Precautions about the Address Space ------------------------------------------------------Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------Appendix 4.3 Precautions about EIT --------------------------------------------------------------------------Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory --------Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------Appendix 4.5.1 Input/output Ports --------------------------------------------------------------------------
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Appendix 4-2
Appendix 4-2
Appendix 4-3
Appendix 4-3
Appendix 4-3
Appendix 4-3
Appendix 4-4
Appendix 4-4
Appendix 4.6 Precautions about Input/Output Ports --------------------------------------------------Appendix 4.6.1 When Using Input/Output Ports in Output Mode ------------------------------Appendix 4.6.2 About the Port Input Disable Function -------------------------------------------Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------Appendix 4.7.1 About Writing to the DMAC Related Registers ---------------------------------Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer -------------Appendix 4.7.3 About the DMA Interrupt Request Status Register ----------------------------Appendix 4.7.4 About the Stable Operation of DMA Transfer ----------------------------------Appendix 4.8 Precautions about the Multijunction Timers -------------------------------------------Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode -----------------------Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode -----------Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ------------------------Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes --------Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ---------------------------------Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ------------------------Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode -------------Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode -------------------------Appendix 4.8.9 Precautions on Using TMS Measure Input --------------------------------------Appendix 4.8.10 Precautions on Using TML Measure Input -------------------------------------Appendix 4.9 Precautions about the A-D Converters -------------------------------------------------Appendix 4.10 Precautions about Serial I/O --------------------------------------------------------------Appendix 4.10.1 Precautions on Using CSIO Mode ------------------------------------------------Appendix 4.10.2 Precautions on Using UART Mode -----------------------------------------------Appendix 4.11 Precautions about RAM Backup Mode ------------------------------------------------Appendix 4.11.1 Precautions to Be Observed at Power-On -------------------------------------Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------Appendix 4.12.1 Notes on Board Design when Connecting JTAG ------------------------------Appendix 4.12.2 Processing Pins when Not Using JTAG -----------------------------------------Appendix 4.13 Precautions about Noise ------------------------------------------------------------------Appendix 4.13.1 Reduction of Wiring Length --------------------------------------------------------Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines --------------Appendix 4.13.3 Processing Analog Input Pin Wiring ---------------------------------------------Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ---------------------------Appendix 4.13.5 Processing Input/Output Ports -----------------------------------------------------
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Appendix 4-4
Appendix 4-4
Appendix 4-4
Appendix 4-5
Appendix 4-5
Appendix 4-5
Appendix 4-5
Appendix 4-5
Appendix 4-6
Appendix 4-6
Appendix 4-8
Appendix 4-9
Appendix 4-9
Appendix 4-9
Appendix 4-9
Appendix 4-10
Appendix 4-10
Appendix 4-10
Appendix 4-11
Appendix 4-12
Appendix 4-15
Appendix 4-15
Appendix 4-16
Appendix 4-17
Appendix 4-17
Appendix 4-18
Appendix 4-18
Appendix 4-19
Appendix 4-20
Appendix 4-20
Appendix 4-23
Appendix 4-23
Appendix 4-24
Appendix 4-28
This page is blank for reasons of layout.
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CHAPTER 1
OVERVIEW
1.1
1.2
1.3
1.4
Outline of the 32182 Group
Block Diagram
Pin Functions
Pin Assignments
OVERVIEW
1
1.1 Outline of the 32182 Group
1.1 Outline of the 32182 Group
The 32182 group (hereafter simply the 32182) belongs to the M32R/ECU series in the M32R family of
Renesas microcomputers. For details about the current development status of the 32182, please contact your
nearest office of Renesas or its distributor.
Table 1.1.1 Product List
Type Name
ROM Size
RAM Size
Package Type
Operating Ambient Temperature
M32182F3VFP
384 Kbytes
64 Kbytes
144-pin LQFP: 144P6Q-A (0.5 mm pitch)
–40°C to 125°C (@64 MHz)
M32182F3UFP
384 Kbytes
64 Kbytes
144-pin LQFP: 144P6Q-A (0.5 mm pitch)
–40°C to 105°C (@80 MHz)
M32182F3TFP
384 Kbytes
64 Kbytes
144-pin LQFP: 144P6Q-A (0.5 mm pitch)
–40°C to 85°C (@80 MHz)
M32182F8VFP
1 Mbyte
64 Kbytes
144-pin LQFP: 144P6Q-A (0.5 mm pitch)
–40°C to 125°C (@64 MHz)
M32182F8UFP
1 Mbyte
64 Kbytes
144-pin LQFP: 144P6Q-A (0.5 mm pitch)
–40°C to 105°C (@80 MHz)
M32182F8TFP
1 Mbyte
64 Kbytes
144-pin LQFP: 144P6Q-A (0.5 mm pitch)
–40°C to 85°C (@80 MHz)
1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)
(1) Based on a RISC architecture
• The 32182 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of
microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize
the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32182
products listed in the above table are built around the M32R-FPU and incorporates flash memory,
RAM and various peripheral functions, all integrated into a single chip.
• The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store
instructions, and various arithmetic/logic operations are executed using register-to-register operation
instructions.
• The internally has sixteen 32-bit general-purpose registers. The instruction set consists of 100 discrete instructions in total (83 instructions common to the M32R family plus 17 FPU and extended
instructions). These instructions are either 16 bits or 32 bits long.
• In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions
such as Load & Address Update and Store & Address Update. These instructions help to speed up
data transfers.
(2) Five-stage pipelined processing
• The M32R-FPU supports five-stage pipelined instruction processing consisting of Instruction Fetch,
Decode, Execute, Memory Access and Write Back (processed in six stages when performing floating-point arithmetic). Not just load/store instructions and register-to-register operation instructions,
but also floating-point arithmetic instructions and compound instructions such as Load & Address
Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 12.5
ns when f(CPUCLK) = 80 MHz).
• Although instructions are supplied to the execution stage in the order in which they were fetched, it is
possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory
access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32RFPU is able to control instruction execution without wasting clock cycles.
(3) Compact instruction code
• The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the
16-bit instruction format especially helps to suppress the code size of a program.
• Moreover, the availability of 32-bit instructions makes programming easier and provides higher performance at the same clock speed than in architectures where the address space is segmented. For
example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward
from the currently executed address in one instruction, making programming easy.
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1.1 Outline of the 32182 Group
1.1.2 Built-in Multiplier/Accumulator
(1) Built-in high-speed multiplier
• The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to
execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods.
(2) DSP-comparable sum-of-products instructions
• The M32R-FPU supports the following four types of sum-of-products calculation instructions (or multiplication instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator.
(1)
(2)
(3)
(4)
16 high-order bits of register × 16 high-order bits of register
16 low-order bits of register × 16 low-order bits of register
Whole 32 bits of register × 16 high-order bits of register
Whole 32 bits of register × 16 low-order bits of register
• The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or
32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because
these instructions are also executed in one CPUCLK period, when used in combination with highspeed data transfer instructions such as Load & Address Update or Store & Address Update, they
enable the M32R-FPU to exhibit data processing capability comparable to that of a DSP.
1.1.3 Built-in Single-precision FPU
• The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by
Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0,
round toward + Infinity and round toward – Infinity) are supported. What’s more, because generalpurpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced.
1.1.4 Built-in Flash Memory and RAM
• The 32182 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed
embedded system.
• The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the development
stage can be used directly in mass-production, allowing for a smooth transition from prototype to
mass-production without the need to change the printed circuit board.
• The internal flash memory can be rewritten as many as 100 times.
• The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be
superficially mapped into part of the internal flash memory. When combined with the internal RealTime Debugger (RTD) and the M32R family’s common debug interface (Scalable Debug Interface or
SDI), this function makes the ROM table data tuning easy.
• The internal RAM can be accessed for reading or rewriting data from an external device independently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated
using the Real-Time Debugger’s exclusive clock-synchronized serial I/O.
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1.1 Outline of the 32182 Group
1.1.5 Built-in Clock Frequency Multiplier
• The 32182 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below.
XIN pin
(8MHz-10MHz)
X8
CPUCLK (CPU clock)
(64MHz-80MHz)
PLL
1/4
BCLK (peripheral clock)
(16MHz-20MHz)
Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier
Table 1.1.2 Clock
Functional Block
Features
CPUCLK
• CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for
BCLK
• Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency
the M32R-FPU core, internal flash memory and internal RAM.
for the internal peripheral I/O and external data bus.
Clock output (BCLK pin output)
• A clock with the same frequency as f(BCLK) is output from this pin.
1.1.6 Powerful Peripheral Functions Built-in
(1) Multijunction timer (MJT)
(2) 10-channel DMAC
(3) 12-channel A-D converter (ADC)
(4) 4-channel high-speed serial I/O (SIO)
(5) Real-time debugger (RTD)
(6) 8-level interrupt controller (ICU)
(7) Three operation modes
(8) Wait controller
(9) 2-channel Full-CAN
(10) M32R family’s common debug function (Scalable Debug Interface or SDI)
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1.2 Block Diagram
1.2 Block Diagram
Figure 1.2.1 shows a block diagram of the 32182. The features of each block are described in Table 1.2.1.
Internal Bus
Interface
M32R-FPU Core
(80 MHz)
DMAC
(10 channels)
(M32182F3: 384 Kbytes)
(M32182F8: 1 Mbyte)
A-D Converter
(A-D0: 10-bit converter, 12 channels)
Internal 16-bit bus
Internal Flash Memory
Multijunction Timer
(37 channels)
Internal 32-bit bus
Single-precision FPU
(fully IEEE 754 compliant)
Internal 32-bit bus
Multiplier/Accumulator
(32 bits × 16 bits + 56 bits)
Internal RAM
(64 Kbytes)
Serial I/O
(4 channels)
Interrupt Controller
(23 sources, 8 levels)
Wait Controller
Real-Time Debugger
(RTD)
Full CAN
(2 channels)
PLL Clock Generator
External Bus
Interface
Internal Power Supply
Generator (VDC)
Data
Address
Input/output ports, 97 lines
Figure 1.2.1 Block Diagram of the 32182
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1.2 Block Diagram
Table 1.2.1 Features of the 32182 (1/2)
Functional Block
Features
M32R-FPU CPU core
• Implementation: Five-stage pipelined instruction processing (processed in six stages when
performing floating-point arithmetic)
• Internal 32-bit structure of the core
• Register configuration
General-purpose registers: 32 bits × 16 registers
Control registers: 32 bits × 6 registers
• Instruction set
16 and 32-bit instruction formats
100 discrete instructions and six addressing modes
• Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)
• Internal single-precision floating-point arithmetic unit (FPU)
RAM
• Capacity: 64 Kbytes, accessible with zero wait state
• The internal RAM can be accessed for reading or rewriting data from the outside independently of
the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to
decrease.
Flash memory
• Capacity
M32182F3: 384 Kbytes, 1M32182F8: 1 Mbyte
• One-wait access
• Durability: Rewritable 100 times
Bus specification
• Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz)
• Logical address space : 4 Gbytes linear
• Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)
(or accessed in 64 bits when accessing the internal flash memory for
instructions)
: Internal 16-bit data bus (for internal peripheral I/O access)
• Extended external area: Maximum 3 Mbytes (1 Mbytes × 3 blocks during external
extension mode)
• External data address: 20-bit address
• External data bus: 16-bit data bus
• Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write
Multijunction timer (MJT)
• 37-channel multi-functional timer
16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,
16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels
• Flexible timer configuration is possible by interconnecting these timer channels.
• Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level
from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)
• DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or
low level from the TIN pin (These can be used as external DMA transfer request inputs
irrespective of timer operation.)
DMAC
• Number of channels: 10
• Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O
and internal RAM are supported.
• Capable of advanced DMA transfers when used in combination with internal peripheral I/O
• Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)
• DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a
transfer on another channel.)
• Interrupt request: DMA transfer counter register underflow
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1.2 Block Diagram
Table 1.2.1 Features of the 32182 (2/2)
Functional Block
A-D converter (ADC)
Features
• 12 channels: 10-bit resolution A-D converter
• Conversion modes: Ordinary conversion modes plus comparator mode
• Operation modes: Single conversion mode and n-channel scan mode (n = 1–12)
• Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary.
• A-D disconnection detection assist function: Influences of the analog input voltage leakage from
any preceding channel during scan mode operation are suppressed.
• An inflow current bypass circuit is built-in.
• Can generate an interrupt or start DMA transfer upon completion of A-D conversion.
• Either 8 or 10-bit conversion results can be read out.
• Interrupt request: Completion of A-D conversion
• DMA transfer request: Completion of A-D conversion
Serial I/O (SIO)
• 4-channel serial I/O
• Can be chosen to be clock-synchronized serial I/O or UART.
• Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or
156 Kbits per second during UART mode when f(BCLK) = 20 MHz).
• Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed
• DMA transfer request: Reception completed or transmit buffer empty
CAN
• 16 message slots × 2 blocks
• Compliant with CAN specification 2.0B active.
• Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off
or single shot
• DMA transfer request: Failed to send, transmission completed or reception completed
Real-Time Debugger
(RTD)
• Internal RAM can be rewritten or monitored independently of the CPU by entering a command
from the outside.
• Comes with exclusive clock-synchronized serial ports.
• Interrupt request: RTD interrupt command input
Interrupt Controller (ICU)
• Controls interrupt requests from the internal peripheral I/O.
• Supports 8-level interrupt priority including an interrupt disabled state.
• External interrupt: 11 sources (SBI#, TIN0,TIN3, TIN16-TIN23)
• TIN pin input sensing: Rising, falling or both edges or high or low level
Wait Controller
• Controls wait states for access to the extended external area.
• Insertion of 0–7 wait states by setting up in software + wait state extension by entering WAIT# signal
PLL
• A multiply-by-8 clock generating circuit
Clock
• Maximum external input clock frequency (XIN) is 10.0 MHz.
• CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM
The maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz).
• BCLK: Operating clock for the internal peripheral I/O and external data bus
The maximum peripheral clock is 20 MHz (peripheral module access when
f(XIN) = 10 MHz).
• Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin.
JTAG
• Boundary scan function
VDC
• Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an
external single power supply (5 or 3.3 V).
Ports
• Input/output pins: 97 pins
• The port input threshold can be set in a program to one of three levels individually for each port
group (with or without Schmitt circuit, selectable).
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32182 Group User’s Manual (Rev.1.0)
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1.3 Pin Functions
1.3 Pin Functions
OSC-VCC
Figure 1.3.1 shows the 32182’s pin function diagram. Pin functions are described in Table 1.3.1.
XIN
XOUT
VCNT
Clock
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
OSC-VCC
P87/SCLKI1/SCLKO1
RESET#
VCCE
5
MOD0
Mode
MOD1
Port 10
8
Port 1
P10/DB8-P17/DB15
8
Port 2
P20/A23-P27/A30
8
VCC-BUS
8
Address bus
P41/BLW#/BLE#
P42/BHW#/BHE#
Port 11
P124/TCLK0-P127/TCLK3
Port 12
5
P130/TIN16-P134/TIN20
P43/RD#
Serial
I/O
CAN
Port 13
P137/TIN23
P44/CS0#
2
P61-P63
3
VCC-BUS
VCCE
P46/A13, P47/A14
P70/BCLK/WR#
P71/WAIT#
P72/HREQ#
Bus control
P110/TO0-P117/TO7
4
P136/TIN22/CRX1
P45/CS1#
Port 6
P103/TO11-P107/TO15
8
P73/HACK#
Port 7
2
P150/TIN0, P153/TIN3
P174/TXD2
P175/RXD2
Port 15
Port 17
P220/CTX0
Serial
I/O
CAN
P221/CRX0
Port 22
VCC-BUS
Port 4
5
P135/TIN21/RXD3
32182 Group
Bus control
Multijunction
timer
P102/TO10/CTX1
VCCE
P00/DB0-P07/DB7
P30/A15-P37/A22
Port 9
P101/TO9/TXD3
Port 0
Port 3
P93/TO16-P97/TO20
P100/TO8
FP
Data bus
Serial
I/O
P86/RXD1
OSC-VSS
Reset
Port 8
P224/A11/CS2#
P225/A12/CS3#
Address bus
Bus control
P74/RTDTXD
P75/RTDRXD
VCCE
P76/RTDACK
P77/RTDCLK
Interrupt
controller
JTMS
SBI#
AD0IN0-AD0IN11
12
JTCK
VCCE
RTD
JTRST
AVCC0
JTDO
AVSS0
JTDI
A-D converter
JTAG
VREF0
VDDE
7
VSS
EXCVDD
4
VCCE
2
EXCVCC
VCC-BUS
2
Note • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.
• VCCE : Operates with the VCCE power supply
VCC-BUS : Operates with the VCC-BUS power supply
OSC-VCC : Operates with the OSC-VCC power supply
Figure 1.3.1 Pin Function Diagram
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1.3 Pin Functions
Table 1.3.1 Description of Pin Functions (1/5)
Type
Pin Name
Signal Name
Input/Output Description
Power supply
VCCE
Main power supply
–
EXCVCC
Internal power supply –
This pin connects an external capacitor.
VCC-BUS
Bus power supply
Power supply for the bus control pins (5.0 V ± 0.5 V or 3.3 V
Power supply for the device (5.0 V ± 0.5 V or 3.3 V ± 0.3 V).
–
± 0.3 V).
VDDE
RAM power supply
–
Backup power supply for the internal RAM (5.0 V ± 0.5 V or
3.3 V ± 0.3 V).
EXCVDD
Internal power
–
This pin connects an external capacitor for the internal power
supply of RAM
Clock
supply of the internal RAM.
VSS
Ground
–
Connect all VSS pins to ground (GND).
XIN,
Clock input
Input
These are clock input/output pins. A PLL-based ×8 frequency
XOUT
Clock output
Output
multiplier is included, which accepts as input a clock whose
frequency is 1/8 of the internal CPU clock frequency. (XIN
input is 10 MHz when f(CPUCLK) = 80 MHz.)
BCLK
System clock
Output
This pin outputs a clock whose frequency is twice that of the
external input clock (XIN). (BCLK output is 20 MHz when
f(CPUCLK) = 80 MHz.) Use this clock to synchronize the
operation of external devices.
OSC-VCC
Clock power supply –
Power supply for the oscillator circuit. Connect OSC-VCC to
OSC-VSS
Clock ground
–
Connect OSC-VSS to ground.
VCNT
PLL control
–
Connect a resistor and capacitor for control of the PLL circuit.
Reset
RESET#
Reset
Input
Reset input pin for the internal circuit.
Mode
MOD0,
Mode
Input
Set the microcomputer’s operation mode.
the main power supply.
MOD1
MOD0
MOD1
Mode
0
0
Single-chip mode
0
1
External extension mode
1
0
Processor mode
(Boot mode) (Note 1)
1
Flash protect
FP
Flash protect
Input
1
(Settings inhibited)
This special pin protects the flash memory against rewrites
in hardware.
Address bus
A11–A30
Address bus
Output
Twenty address lines (A11–A30) are included that support
up to 2 MB of memory space per chip select. However, A11
and A12 are shared with CS#2 and CS#3, respectively.
A31 is not output.
Note 1: Boot mode requires that the FP pin should be at the high level. For details about boot mode, see Chapter 6, “Internal
Memory.”
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1.3 Pin Functions
Table 1.3.1 Description of Pin Functions (2/5)
Type
Pin Name
Signal Name
Input/Output Description
Data bus
DB0–DB15
Data bus
Input/output This 16-bit data bus is used to connect external devices.
When writing in byte units during a write cycle, the output
data at the invalid byte position is undefined. During a
read cycle, data on the entire 16-bit bus is always read in.
However, only the data at the valid byte position is
transferred into the internal circuit.
Bus control
CS0#–CS3# Chip select
Output
These are chip select signals for external devices.
RD#
Read
Output
This signal is output when reading an external device.
WR#
Write
Output
This signal is output when writing to an external device.
BHW#/BLW# Byte high/low write
Output
When writing to an external device, this signal indicates the
valid byte position to which data is transferred. BHW# and
BLW# correspond to the upper address side (bits 0–7 are
valid) and the lower address side (bits 8–15 are valid),
respectively.
BHE#
Byte high enable
Output
During an external device access, this signal indicates that
the high-order data (bits 0–7) is valid.
BLE#
Byte low enable
Output
During an external device access, this signal indicates that
the low-order data (bits 8–15) is valid.
WAIT#
Wait
Input
When accessing an external device, a low-level input on
WAIT# pin extends the wait cycle.
HREQ#
Hold request
Input
This input is used by an external device to request control
of the external bus. A low-level input on HREQ# pin places
the CPU in a hold state.
HACK#
Hold acknowledge
Output
This signal notifies that the CPU has entered a hold state
and relinquished control of the external bus.
Multijunction
TIN0, TIN3,
timer
TIN16–TIN23
Timer input
Input
Input pins for the multijunction timer.
TO0–TO20
Timer output
Output
Output pins for the multijunction timer.
TCLK0
Timer clock
Input
Clock input pins for the multijunction timer.
–TCLK3
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1.3 Pin Functions
Table 1.3.1 Description of Pin Functions (3/5)
Type
Pin Name
Signal Name
Input/Output Description
A-D converter
AVCC0
Analog power supply
–
AVCC0 is the power supply for the A-D0 converter.
Connect AVCC0 to the power supply rail.
AVSS0
Analog ground
–
AVSS0 is the analog ground for the A-D0 converter.
AD0IN0
Analog input
Input
12-channel analog input pins for the A-D0 converter.
Reference voltage
Input
VREF0 is the reference voltage input pin for the A-D0
Connect AVSS0 to ground.
–AD0IN11
VREF0
input
Interrupt
SBI#
controller
Serial I/O
System break
converter.
Input
This is the system break interrupt (SBI) input pin for the
interrupt
SCLKI0/
SCLKO0
UART transmit/receive
interrupt controller.
Input/output When channel 0 is in UART mode:
clock output or CSIO
This pin outputs a clock derived from BRG output by
transmit/receive clock
dividing it by 2.
input/output
When channel 0 is in CSIO mode:
This pin accepts as input a transmit/receive clock when
external clock is selected or outputs a transmit/receive
clock when internal clock is selected.
SCLKI1/
UART transmit/receive
Input/output When channel 1 is in UART mode:
SCLKO1
clock output or CSIO
This pin outputs a clock derived from BRG output by
transmit/receive clock
dividing it by 2.
input/output
When channel 1 is in CSIO mode:
This pin accepts as input a transmit/receive clock when
external clock is selected or outputs a transmit/receive
clock when internal clock is selected.
1-11
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.3 Pin Functions
Table 1.3.1 Description of Pin Functions (4/5)
Type
Pin Name
Signal Name
Input/Output Description
Serial I/O
TXD0
Transmit data
Output
Transmit data output pin for serial I/O channel 0.
RXD0
Received data
Input
Received data input pin for serial I/O channel 0.
TXD1
Transmit data
Output
Transmit data output pin for serial I/O channel 1.
RXD1
Received data
Input
Received data input pin for serial I/O channel 1.
TXD2
Transmit data
Output
Transmit data output pin for serial I/O channel 2.
RXD2
Received data
Input
Received data input pin for serial I/O channel 2.
TXD3
Transmit data
Output
Transmit data output pin for serial I/O channel 3.
RXD3
Received data
Input
Received data input pin for serial I/O channel 3.
Real-time
RTDTXD
RTD transmit data
Output
Serial data output pin for the real-time debugger.
debugger
RTDRXD
RTD received data
Input
Serial data input pin for the real-time debugger.
(RTD)
RTDCLK
RTD clock input
Input
Serial data transmit/receive clock input pin for the real-time
debugger.
RTDACK
RTD acknowledge
Output
A low-level pulse is output from this pin synchronously with
the start clock for the real-time debugger’s serial data output
word. The low-level pulse width indicates the type of command/
data received by the real-time debugger.
CAN
JTAG
CTX0, CTX1 Transmit data
Output
This pin outputs data from the CAN module.
CRX0, CRX1 Received data
Input
This pin accepts as input the data for the CAN module.
JTMS
Input
Test mode select
Test mode select input to control the state transition of the
test circuit.
JTCK
Test clock
Input
JTRST
Test reset
Input
Clock input for the debug module and test circuit.
Test reset input to initialize the test circuit asynchronously
with device operation.
JTDI
Test data input
Input
This pin accepts as input the test instruction code or test data
that is serially received.
JTDO
Test data output
Output
This pin outputs the test instruction code or test data serially.
1-12
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.3 Pin Functions
Table 1.3.1 Description of Pin Functions (5/5)
Type
Pin Name
Signal Name
Input/Output Description
Input/output
P00–P07
Input/output port 0
Input/output Programmable input/output port.
ports
P10–P17
Input/output port 1
(Note 1)
P20–P27
Input/output port 2
P30–P37
Input/output port 3
P41–P47
Input/output port 4
P61–P63
Input/output port 6
P70–P77
Input/output port 7
P82–P87
Input/output port 8
P93–P97
Input/output port 9
P100–P107
Input/output port 10
P110–P117
Input/output port 11
P124–P127
Input/output port 12
P130–P137
Input/output port 13
P150–P153
Input/output port 15
P174, P175
Input/output port 17
P220, P221, Input/output port 22
P224, P225
Note 1: • Input/output port 5 is reserved for future use.
• P221 is input-only port.
• Input/output functions cannot be used for the ports listed below, because no external pins are available for these pins.
P65-P67
P140-P147
P151, P152, P154-P157
P160-P167
P172, P173, P176, P177
P180-P187
P190-P197
P200-P203
P210-P217
P222, P223, P226, P227
1-13
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.4 Pin Assignments
1.4 Pin Assignments
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
VSS
VCCE
P44/CS0#
P45/CS1#
P224/A11/CS2#
P225/A12/CS3#
P46/A13
P47/A14
P30/A15
P31/A16
P32/A17
P33/A18
P34/A19
P35/A20
P36/A21
P37/A22
P20/A23
P21/A24
P22/A25
P23/A26
P24/A27
P25/A28
P26/A29
P27/A30
VCC-BUS
VSS
P93/TO16
P94/TO17
P95/TO18
P96/TO19
Figure 1.4.1 shows the 32182’s pin assignment diagram. A pin assignment table is shown in Table 1.4.1.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32182 Group
P97/TO20
P117/TO7
P116/TO6
P115/TO5
P114/TO4
P113/TO3
P112/TO2
P111/TO1
P110/TO0
P127/TCLK3
P126/TCLK2
P125/TCLK1
P124/TCLK0
EXCVCC
VCCE
VSS
VSS
SBI#
P63
P62
P61
AD0IN11
AD0IN10
AD0IN9
AD0IN8
AVSS0
AD0IN7
AD0IN6
AD0IN5
AD0IN4
AD0IN3
AD0IN2
AD0IN1
AD0IN0
VREF0
AVCC0
P150/TIN0
P153/TIN3
P130/TIN16
P131/TIN17
P132/TIN18
P133/TIN19
P134/TIN20
P135/TIN21/RXD3
P136/TIN22/CRX1
P137/TIN23
P220/CTX0
P221/CRX0
VCCE
VCNT
OSC-VCC
XIN
OSC-VSS
XOUT
RESET#
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
JTDI
JTDO
JTRST
JTCK
JTMS
P100/TO8
P101/TO9/TXD3
P102/TO10/CTX1
P103/TO11
P104/TO12
P105/TO13
P106/TO14
P107/TO15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P174/TXD2
P175/RXD2
FP
MOD0
MOD1
EXCVDD
VSS
EXCVCC
VDDE
VSS
VCCE
P17/DB15
P16/DB14
P15/DB13
P14/DB12
P13/DB11
P12/DB10
P11/DB9
P10/DB8
P07/DB7
P06/DB6
P05/DB5
P04/DB4
P03/DB3
P02/DB2
P01/DB1
P00/DB0
P73/HACK#
P72/HREQ#
P71/WAIT#
P70/BCLK/WR#
P43/RD#
P42/BHW#/BHE#
P41/BLW#/BLE#
VCC-BUS
VSS
Package: 144P6Q-A (0.5 mm pitch)
Note: • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.
Figure 1.4.1 Pin Assignment Diagram (Top View)
1-14
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.4 Pin Assignments
The pins directed for input go to a high-impedance state (Hi-z) when reset. The term “when reset” means that
input on RESET# pin is held low (the device remains reset), and that the RESET# pin is released back high
(the device comes out of reset).
Table 1.4.1 Pin Assignments of the 32182 (1/4)
Pin State When Reset
Function
Pin
No.
Symbol
Port
Other than
port
Other than
port
Type
Condition
Function
Type
State during State at reset
release
reset
1
P150/TIN0
P150
TIN0
-
Input/output
P150
Input
Hi-z
Hi-z
2
P153/TIN3
P153
TIN3
-
Input/output
P153
Input
Hi-z
Hi-z
3
P130/TIN16
P130
TIN16
-
Input/output
P130
Input
Hi-z
Hi-z
4
P131/TIN17
P131
TIN17
-
Input/output
P131
Input
Hi-z
Hi-z
5
P132/TIN18
P132
TIN18
-
Input/output
P132
Input
Hi-z
Hi-z
6
P133/TIN19
P133
TIN19
-
Input/output
P133
Input
Hi-z
Hi-z
7
P134/TIN20
P134
TIN20
-
Input/output
P134
Input
Hi-z
Hi-z
8
P135/TIN21/RXD3
P135
TIN21
RXD3
Input/output
P135
Input
Hi-z
Hi-z
9
P136/TIN22/CRX1
P136
TIN22
CRX1
Input/output
P136
Input
Hi-z
Hi-z
10
P137/TIN23
P137
TIN23
-
Input/output
P137
Input
Hi-z
Hi-z
11
P220/CTX0
P220
CTX0
-
Input/output
P220
Input
Hi-z
Hi-z
12
P221/CRX0
P221
CRX0
-
Input
P221
Input
Hi-z
Hi-z
13
VCCE
-
VCCE
-
-
VCCE
-
-
-
14
VCNT
-
VCNT
-
-
VCNT
-
-
-
15
OSC-VCC
-
OSC-VCC
-
-
OSC-VCC
-
-
-
16
XIN
-
XIN
-
Input
XIN
Input
-
-
17
OSC-VSS
-
OSC-VSS
-
-
OSC-VSS
-
-
-
18
XOUT
-
XOUT
-
Output
XOUT
Output
XOUT
XOUT
19
RESET#
-
RESET#
-
Input
RESET#
Input
Hi-z
Hi-z
20
P74/RTDTXD
P74
RTDTXD
-
Input/output
P74
Input
Hi-z
Hi-z
21
P75/RTDRXD
P75
RTDRXD
-
Input/output
P75
Input
Hi-z
Hi-z
22
P76/RTDACK
P76
RTDACK
-
Input/output
P76
Input
Hi-z
Hi-z
23
P77/RTDCLK
P77
RTDCLK
-
Input/output
P77
Input
Hi-z
Hi-z
24
JTDI (Note 1)
-
JTDI
-
Input
JTDI
Input
Hi-z
Hi-z
Hi-z
25
JTDO (Note 1)
-
JTDO
-
Output
JTDO
Output
Hi-z
26
JTRST (Note 1)
-
JTRST
-
Input
JTRST
Input
Hi-z
Hi-z
27
JTCK (Note 1)
-
JTCK
-
Input
JTCK
Input
Hi-z
Hi-z
28
JTMS (Note 1)
-
JTMS
-
Input
JTMS
Input
Hi-z
Hi-z
29
P100/TO8
P100
TO8
-
Input/output
P100
Input
Hi-z
Hi-z
30
P101/TO9/TXD3
P101
TO9
TXD3
Input/output
P101
Input
Hi-z
Hi-z
31
P102/TO10/CTX1
P102
TO10
CTX1
Input/output
P102
Input
Hi-z
Hi-z
32
P103/TO11
P103
TO11
-
Input/output
P103
Input
Hi-z
Hi-z
33
P104/TO12
P104
TO12
-
Input/output
P104
Input
Hi-z
Hi-z
34
P105/TO13
P105
TO13
-
Input/output
P105
Input
Hi-z
Hi-z
35
P106/TO14
P106
TO14
-
Input/output
P106
Input
Hi-z
Hi-z
36
P107/TO15
P107
TO15
-
Input/output
P107
Input
Hi-z
Hi-z
37
AVCC0
-
AVCC0
-
-
AVCC0
-
-
-
38
VREF0
-
VREF0
-
-
VREF0
-
-
-
39
AD0IN0
-
AD0IN0
-
Input
AD0IN0
Input
Hi-z
Hi-z
40
AD0IN1
-
AD0IN1
-
Input
AD0IN1
Input
Hi-z
Hi-z
41
AD0IN2
-
AD0IN2
-
Input
AD0IN2
Input
Hi-z
Hi-z
42
AD0IN3
-
AD0IN3
-
Input
AD0IN3
Input
Hi-z
Hi-z
43
AD0IN4
-
AD0IN4
-
Input
AD0IN4
Input
Hi-z
Hi-z
44
AD0IN5
-
AD0IN5
-
Input
AD0IN5
Input
Hi-z
Hi-z
45
AD0IN6
-
AD0IN6
-
Input
AD0IN6
Input
Hi-z
Hi-z
46
AD0IN7
-
AD0IN7
-
Input
AD0IN7
Input
Hi-z
Hi-z
47
AVSS0
-
AVSS0
-
-
AVSS0
-
-
-
48
AD0IN8
-
AD0IN8
-
Input
AD0IN8
Input
Hi-z
Hi-z
49
AD0IN9
-
AD0IN9
-
Input
AD0IN9
Input
Hi-z
Hi-z
50
AD0IN10
-
AD0IN10
-
Input
AD0IN10
Input
Hi-z
Hi-z
51
AD01N11
-
AD01N11
-
Input
AD01N11
Input
Hi-z
Hi-z
Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.
1-15
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.4 Pin Assignments
Table 1.4.1 Pin Assignments of the 32182 (2/4)
Function
Pin
No.
Symbol
Pin State When Reset
Other than
port
Port
Type
Condition
Function
Type
State during State at reset
release
reset
52
P61
P61
-
-
Input/output
P61
Input
Hi-z
Hi-z
53
P62
P62
-
-
Input/output
P62
Input
Hi-z
Hi-z
54
P63
P63
-
-
Input/output
P63
Input
Hi-z
Hi-z
55
SBI#
-
SBI#
-
Input
SBI#
Input
Hi-z
Hi-z
56
VSS
-
VSS
-
-
VSS
-
-
-
57
VSS
-
VSS
-
-
VSS
-
-
-
58
VCCE
-
VCCE
-
-
VCCE
-
-
-
59
EXCVCC
-
EXCVCC
-
-
EXCVCC
-
-
-
60
P124/TCLK0
P124
TCLK0
-
Input/output
P124
Input
Hi-z
Hi-z
61
P125/TCLK1
P125
TCLK1
-
Input/output
P125
Input
Hi-z
Hi-z
62
P126/TCLK2
P126
TCLK2
-
Input/output
P126
Input
Hi-z
Hi-z
63
P127/TCLK3
P127
TCLK3
-
Input/output
P127
Input
Hi-z
Hi-z
64
P110/TO0
P110
TO0
-
Input/output
P110
Input
Hi-z
Hi-z
65
P111/TO1
P111
TO1
-
Input/output
P111
Input
Hi-z
Hi-z
66
P112/TO2
P112
TO2
-
Input/output
P112
Input
Hi-z
Hi-z
67
P113/TO3
P113
TO3
-
Input/output
P113
Input
Hi-z
Hi-z
68
P114/TO4
P114
TO4
-
Input/output
P114
Input
Hi-z
Hi-z
69
P115/TO5
P115
TO5
-
Input/output
P115
Input
Hi-z
Hi-z
70
P116/TO6
P116
TO6
-
Input/output
P116
Input
Hi-z
Hi-z
71
P117/TO7
P117
TO7
-
Input/output
P117
Input
Hi-z
Hi-z
72
P97/TO20
P97
TO20
-
Input/output
P97
Input
Hi-z
Hi-z
73
P96/TO19
P96
TO19
-
Input/output
P96
Input
Hi-z
Hi-z
74
P95/TO18
P95
TO18
-
Input/output
P95
Input
Hi-z
Hi-z
75
P94/TO17
P94
TO17
-
Input/output
P94
Input
Hi-z
Hi-z
76
P93/TO16
P93
TO16
-
Input/output
P93
Input
Hi-z
Hi-z
77
VSS
-
VSS
-
-
VSS
-
-
-
78
VCC-BUS
-
VCC-BUS
-
-
VCC-BUS
-
-
-
P27
Input
Hi-z
Hi-z
Undefined
79
80
81
82
83
84
85
86
87
88
89
90
P27/A30
P26/A29
P25/A28
P24/A27
P23/A26
P22/A25
P21/A24
P20/A23
P37/A22
P36/A21
P35/A20
P34/A19
P27
P26
P25
P24
P23
P22
P21
P20
P37
P36
P35
P34
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
-
-
-
-
-
-
-
-
-
-
-
-
Input/output
During single-chip and
external extension modes
Input/output
During processor mode
During single-chip and
external extension modes
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Hi-z
Input
Hi-z
Hi-z
A29
Output
Hi-z
Undefined
P25
Input
Hi-z
Hi-z
A28
Output
Hi-z
Undefined
During single-chip and
external extension modes
P24
Input
Hi-z
Hi-z
A27
Output
Hi-z
Undefined
P23
Input
Hi-z
Hi-z
A26
Output
Hi-z
Undefined
P22
Input
Hi-z
Hi-z
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
A25
Output
Hi-z
Undefined
During single-chip and
external extension modes
P21
Input
Hi-z
Hi-z
During processor mode
During single-chip and
external extension modes
During processor mode
A24
Output
Hi-z
Undefined
P20
Input
Hi-z
Hi-z
Undefined
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
Input/output
During processor mode
During single-chip and
external extension modes
1-16
Output
During processor mode
During single-chip and
external extension modes
During processor mode
Input/output
Input/output
A30
P26
During processor mode
During single-chip and
external extension modes
During processor mode
A23
Output
Hi-z
P37
Input
Hi-z
Hi-z
A22
Output
Hi-z
Undefined
P36
Input
Hi-z
Hi-z
A21
Output
Hi-z
Undefined
P35
Input
Hi-z
Hi-z
A20
Output
Hi-z
Undefined
P34
Input
Hi-z
Hi-z
A19
Output
Hi-z
Undefined
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.4 Pin Assignments
Table 1.4.1 Pin Assignments of the 32182 (3/4)
Function
Pin
No.
91
92
93
94
95
96
97
98
99
Symbol
P33/A18
P32/A17
P31/A16
P30/A15
P47/A14
P46/A13
P225/A12/CS3#
P224/A11/CS2#
P45/CS1#
100 P44/CS0#
Pin State When Reset
Port
Other than
port
Other than
port
P33
A18
-
P32
P31
P30
P47
P46
P225
P224
P45
P44
A17
A16
A15
A14
A13
A12
A11
CS1#
CS0#
-
-
-
-
-
CS3#
CS2#
-
-
Type
Condition
Function
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Type
State during State at reset
release
reset
During single-chip and
external extension modes
P33
Input
Hi-z
Hi-z
During processor mode
A18
Output
Hi-z
Undefined
During single-chip and
external extension modes
P32
Input
Hi-z
Hi-z
During processor mode
A17
Output
Hi-z
Undefined
During single-chip and
external extension modes
P31
Input
Hi-z
Hi-z
During processor mode
A16
Output
Hi-z
Undefined
During single-chip and
external extension modes
P30
Input
Hi-z
Hi-z
During processor mode
A15
Output
Hi-z
Undefined
During single-chip and
external extension modes
P47
Input
Hi-z
Hi-z
During processor mode
A14
Output
Hi-z
Undefined
During single-chip and
external extension modes
P46
Input
Hi-z
Hi-z
During processor mode
A13
Output
Hi-z
Undefined
During single-chip and
external extension modes
P225
Input
Hi-z
Hi-z
During processor mode
A12
Output
Hi-z
Undefined
During single-chip and
external extension modes
P224
Input
Hi-z
Hi-z
During processor mode
A11
Output
Hi-z
Undefined
During single-chip and
external extension modes
P45
Input
Hi-z
Hi-z
During processor mode
CS1#
Output
Hi-z
High level
During single-chip and
external extension modes
P44
Input
Hi-z
Hi-z
During processor mode
CS0#
Output
Hi-z
High level
101 VCCE
-
VCCE
-
-
VCCE
-
-
-
102 VSS
-
VSS
-
-
VSS
-
-
-
103 P87/SCLKI1/SCLKO1
P87
SCLKI1
SCLKO1
Input/output
P87
Input
Hi-z
Hi-z
104 P86/RXD1
P86
RXD1
-
Input/output
P86
Input
Hi-z
Hi-z
105 P85/TXD1
P85
TXD1
-
Input/output
P85
Input
Hi-z
Hi-z
106 P84/SCLKI0/SCLKO0
P84
SCLKI0
SCLKO0
Input/output
P84
Input
Hi-z
Hi-z
107 P83/RXD0
P83
RXD0
-
Input/output
P83
Input
Hi-z
Hi-z
108 P82/TXD0
P82
TXD0
-
Input/output
P82
Input
Hi-z
Hi-z
109 P174/TXD2
P174
TXD2
-
Input/output
P174
Input
Hi-z
Hi-z
110 P175/RXD2
P175
RXD2
-
Input/output
P175
Input
Hi-z
Hi-z
111 FP
-
FP
-
Input
FP
Input
Hi-z
Hi-z
112 MOD0
-
MOD0
-
Input
MOD0
Input
Hi-z
Hi-z
113 MOD1
-
MOD1
-
Input
MOD1
Input
Hi-z
Hi-z
114 EXCVDD
-
EXCVDD
-
-
EXCVDD
-
-
-
115 VSS
-
VSS
-
-
VSS
-
-
-
116 EXCVCC
-
EXCVCC
-
-
EXCVCC
-
-
-
117 VDDE
-
VDDE
-
-
VDDE
-
-
-
118 VSS
-
VSS
-
-
VSS
-
-
-
119 VCCE
-
VCCE
-
-
VCCE
-
-
-
P17
DB15
-
Input/output
P17
Input
Hi-z
Hi-z
DB15
Input/output
Hi-z
Hi-z
P16
Input
Hi-z
Hi-z
DB14
Input/output
Hi-z
Hi-z
P15
Input
Hi-z
Hi-z
DB13
Input/output
Hi-z
Hi-z
P14
Input
Hi-z
Hi-z
DB12
Input/output
Hi-z
Hi-z
120 P17/DB15
121 P16/DB14
122 P15/DB13
123 P14/DB12
P16
P15
P14
DB14
DB13
DB12
-
-
-
Input/output
Input/output
Input/output
1-17
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
32182 Group User’s Manual (Rev.1.0)
OVERVIEW
1
1.4 Pin Assignments
Table 1.4.1 Pin Assignments of the 32182 (4/4)
Pin
No.
Pin State When Reset
Function
Symbol
124 P13/DB11
125 P12/DB10
126 P11/DB9
127 P10/DB8
128 P07/DB7
129 P06/DB6
130 P05/DB5
131 P04/DB4
132 P03/DB3
133 P02/DB2
134 P01/DB1
Port
Other than
port
Other than
port
P13
DB11
-
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
-
-
-
-
-
-
-
-
-
-
Type
Condition
Type
State during
reset
State at reset
release
P13
Input
Hi-z
Hi-z
DB11
Input/output
Hi-z
Hi-z
P12
Input
Hi-z
Hi-z
DB10
Input/output
Hi-z
Hi-z
Hi-z
Function
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
P11
Input
Hi-z
DB9
Input/output
Hi-z
Hi-z
P10
Input
Hi-z
Hi-z
DB8
Input/output
Hi-z
Hi-z
P07
Input
Hi-z
Hi-z
DB7
Input/output
Hi-z
Hi-z
P06
Input
Hi-z
Hi-z
DB6
Input/output
Hi-z
Hi-z
P05
Input
Hi-z
Hi-z
DB5
Input/output
Hi-z
Hi-z
P04
Input
Hi-z
Hi-z
DB4
Input/output
Hi-z
Hi-z
P03
Input
Hi-z
Hi-z
DB3
Input/output
Hi-z
Hi-z
Hi-z
P02
Input
Hi-z
DB2
Input/output
Hi-z
Hi-z
P01
Input
Hi-z
Hi-z
DB1
Input/output
Hi-z
Hi-z
P00
Input
Hi-z
Hi-z
135 P00/DB0
P00
DB0
-
Input/output
136 P73/HACK#
P73
HACK#
-
Input/output
DB0
P73
Input/output
Input
Hi-z
Hi-z
Hi-z
Hi-z
137 P72/HREQ#
P72
HREQ#
-
Input/output
P72
Input
Hi-z
Hi-z
138 P71/WAIT#
P71
WAIT#
-
Input/output
P71
Input
Hi-z
Hi-z
139 P70/BCLK/WR#
P70
BCLK
WR#
Input/output
P70
Input
Hi-z
Hi-z
P43
Input
Hi-z
Hi-z
RD#
Output
Hi-z
High level
During processor mode
140 P43/RD#
P43
RD#
-
Input/output
141 P42/BHW#/BHE#
P42
BHW#
BHE#
Input/output
142 P41/BLW#/BLE#
P41
BLW#
BLE#
Input/output
143 VCC-BUS
-
VCC-BUS
-
144 VSS
-
VSS
-
During external extension
and processor modes
During processor mode
During external extension
and processor modes
Input
Hi-z
Hi-z
Output
Hi-z
High level
P41
Input
Hi-z
Hi-z
BLE#/BLE#
Output
Hi-z
High level
-
VCC-BUS
-
-
-
-
-
-
-
-
1-18
During processor mode
During external extension
and processor modes
P42
BHE#/BHE#
32182 Group User’s Manual (Rev.1.0)
CHAPTER 2
CPU
2.1
2.2
2.3
2.4
2.5
2.6
2.7
CPU Registers
General-purpose Registers
Control Registers
Accumulator
Program Counter
Data Formats
Supplementary Explanation for BSET, BCLR,
LOCK and UNLOCK Instruction Execution
CPU
2
2.1 CPU Registers
2.1 CPU Registers
The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter.
The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration.
2.2 General-purpose Registers
The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as
well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack
pointer. The link register is used to store the return address when executing a subroutine call instruction. The
Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on
the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW).
After reset, the value of the general-purpose registers is undefined.
b0
b0
b31
b31
R8
R9
R10
R11
R12
R13
R14 (Link register)
R15 (Stack pointer) (Note 1)
R0
R1
R2
R3
R4
R5
R6
R7
Note 1: The stack pointer functions as either the SPI or the SPU depending on
the value of the SM bit in the PSW.
Figure 2.2.1 General-purpose Registers
2.3 Control Registers
There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register
(CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floatingpoint Status Register (FPSR).
The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.
In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction.
CRn
b0
CR0
CR1
CR2
CR3
PSW
CBR
SPI
SPU
Processor Status Word Register
Condition Bit Register
Interrupt Stack Pointer
User Stack Pointer
CR6
CR7
BPC
FPSR
Backup PC
Floating-point Status Register
b31
Notes: • CRn (n = 0-3, 6 and 7) denotes the control register number.
• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.
• The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instructions.
Figure 2.3.1 Control Registers
2-2
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.3 Control Registers
2.3.1 Processor Status Word Register: PSW (CR0)
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
b31
BSM
BIE
BC
SM
IE
?
?
0
0
0
0
0
?
0
0
0
0
0
0
0
BPSW field
C
0
PSW field
<After reset: B’0000 0000 0000 0000 ??00 000? 0000 0000>
b
Bit Name
0–15
No function assigned. Fix to "0".
16
BSM
Backup SM Bit
17
BIE
Backup IE Bit
18–22
No function assigned. Fix to "0".
23
BC
Backup C Bit
24
25
R
W
0
0
Saves value of SM bit when EIT occurs
R
W
Saves value of IE bit when EIT occurs
R
W
0
0
Saves value of C bit when EIT occurs
R
W
SM
Stack Mode Bit
0: Uses R15 as the interrupt stack pointer
1: Uses R15 as the user stack pointer
R
W
IE
Interrupt Enable Bit
0: Does not accept interrupt
1: Accepts interrupt
R
W
0
0
Indicates carry, borrow or overflow resulting
from operations (instruction dependent)
R
W
26–30
No function assigned. Fix to "0".
31
C
Condition Bit
Function
The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field
which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs.
The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit.
The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the
Backup Condition (BC) bit.
After reset, BSM, BIE and BC are undefined. All other bits are "0".
2-3
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.3 Control Registers
2.3.2 Condition Bit Register: CBR (CR1)
The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value
written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the
register with the MVTC instruction is ignored.)
After reset, the value of CBR is H’0000 0000.
b0
0
CBR
b31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)
The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack
pointer. These registers can be accessed as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW.
After reset, the values of the SPI and SPU are undefined.
b0
b31
SPI
SPI
b0
b31
SPU
SPU
2.3.4 Backup PC: BPC (CR6)
The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed
to "0".
When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next
instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is
executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns
to the word-aligned address.)
After reset, the value of the BPC is undefined.
b0
BPC
b31
BPC
2-4
0
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.3 Control Registers
2.3.5 Floating-point Status Register: FPSR (CR7)
b0
1
2
3
4
5
FS
FX
FU
FZ
FO
FV
0
0
0
0
0
b16
0
6
7
8
9
10
11
12
13
14
b15
0
0
0
0
0
0
0
0
0
0
0
22
30
17
18
19
20
21
EX
EU
EZ
EO
EV
0
0
0
0
0
0
23
24
25
26
27
28
29
DN
CE
CX
CU
CZ
CO
CV
1
0
0
0
0
0
0
b31
RM
0
0
<After reset: H’0000 0100>
b
Bit Name
Function
R
W
0
FS
Reflects the logical sum of FU, FZ, FO and FV.
Floating-point Exception Summary Bit
R
–
1
FX
Inexact Exception Flag
Set to "1" when an inexact exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
R
W
2
FU
Underflow Exception Flag
Set to "1" when an underflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
R
W
3
FZ
Zero Divide Exception Flag
Set to "1" when a zero divide exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
R
W
4
FO
Overflow Exception Flag
Set to "1" when an overflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
R
W
R
W
0
0
it is cleared to "0" in software.
5
FV
Invalid Operation Exception Flag
Set to "1" when an invalid operation exception occurs (if EIT processing
is unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
6–16
No function assigned. Fix to "0".
17
EX
Inexact Exception Enable Bit
0: Mask EIT processing to be executed when an inexact exception occurs.
1: Execute EIT processing when an inexact exception occurs.
R
W
18
EU
Underflow Exception Enable Bit
0: Mask EIT processing to be executed when an underflow exception
occurs.
1: Execute EIT processing when an underflow exception occurs.
R
W
19
EZ
Zero Divide Exception Enable Bit
0: Mask EIT processing to be executed when a zero divide exception
occurs.
1: Execute EIT processing when a zero divide exception occurs.
R
W
20
EO
Overflow Exception Enable Bit
0: Mask EIT processing to be executed when an overflow exception
occurs.
1: Execute EIT processing when an overflow exception occurs.
R
W
21
EV
Invalid Operation Exception Enable Bit
0: Mask EIT processing to be executed when an invalid operation
exception occurs.
1: Execute EIT processing when an invalid operation exception occurs.
R
W
22
No function assigned. Fix to "0".
0
0
23
DN
Denormalized Number Zero Flush Bit
(Note 2)
0: Handle the denormalized number as a denormalized number.
1: Handle the denormalized number as zero.
R
W
24
CE
Unimplemented Operation
Exception Cause Bit
0: No unimplemented operation exception occurred.
1: An unimplemented operation exception occurred. When the bit is
set to "1", the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
25
CX
Inexact Exception Cause Bit
0: No inexact exception occurred.
1: An inexact exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
2-5
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.3 Control Registers
26
CU
Underflow Exception Cause Bit
0: No underflow exception occurred
1: An underflow exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
27
CZ
Zero Divide Exception Cause Bit
0: No zero divide exception occurred.
1: A zero divide exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
28
CO
Overflow Exception Cause Bit
0: No overflow exception occurred.
1: An overflow exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
29
CV
0: No invalid operation exception occurred.
Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
30, 31
RM
Rounding Mode Selection Bit
R
00: Round to nearest
01: Round toward Zero
10: Round toward + Infinity
11: Round toward – Infinity
W
Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set to
"0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their
corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In
this case, these two flags do not change state regardless of the enable bits settings.
Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs.
Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write).
2-6
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.4 Accumulator
2.4 Accumulator
The Accumulator (ACC) is a 56-bit register used for DSP function instructions.
The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the
accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The
accumulator is also used for the multiply instruction “MUL,” in which case the accumulator value is destroyed by
instruction execution.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively.
Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI,
MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the low-order 32 bits (bits
32–63) and the middle 32 bits (bits 16–47), respectively.
After reset, the value of accumulator is undefined.
(Note 1)
b0
Read range of MVFACMI instruction
78
15 16
31 32
47 48
b63
ACC
Write and read ranges of MVTACHI
and MVFACHI instructions
Write and read ranges of MVTACLO
and MVFACLO instructions
Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this
bit field is ignored.
2.5 Program Counter
The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the
M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0".
After reset, the value of PC is H’0000 0000.
b0
PC
b31
PC
2-7
0
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.6 Data Formats
2.6 Data Formats
2.6.1 Data Types
The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit
integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements.
b0
Signed byte
(8-bit) integer
b7
S
b0
b7
Unsigned byte
(8-bit) integer
b0
Signed halfword
(16-bit) integer
b15
S
b0
b15
Unsigned halfword
(16-bit) integer
b0
Signed word
(32-bit) integer
b31
S
b0
b31
Unsigned word
(32-bit) integer
b0 b1
Single-precision
floating-point number
S
b8 b9
b31
E
F
S: Sign bit; E: Exponent field; F: Fraction field
Figure 2.6.1 Data Types
2-8
32182 Group User’s Manual (Rev.1.0)
CPU
2
2.6 Data Formats
2.6.2 Data Formats
(1) Data formats in registers
The data sizes in the M32R-FPU registers are always words (32 bits).
When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended
(LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before
being loaded in the register.
When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions,
respectively.
From memory
(LDB, LDUB instructions)
<Load>
b0
Sign-extended (LDB instruction) or
zero-extended (LDUB instruction)
b31
24
Byte
Rn
From memory (LDH, LDUH instructions)
Sign-extended (LDH instruction) or
b0 zero-extended (LDUH instruction) 16
b31
Halfword
Rn
From memory (LD instruction)
b0
b31
Word
Rn
<Store>
b0
24
b31
Byte
Rn
To memory (STB instruction)
b0
16
b31
Halfword
Rn
To memory (STH instruction)
b0
Rn
b31
Word
To memory (ST instruction)
Figure 2.6.2 Data Formats in Registers
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32182 Group User’s Manual (Rev.1.0)
CPU
2
2.6 Data Formats
(2) Data formats in memory
The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can
be located at any address, halfword and word data must be located at the addresses aligned with a
halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits =
"00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs.
Address
+0 address
b0
+1 address
7 8
+2 address
15 16
+3 address
23 24
b31
Byte
Byte
Byte
Byte
Byte
b0
b31
15
Halfword
Halfword
Halfword
b0
b31
Word
Word
Figure 2.6.3 Data Formats in Memory
(3) Endian
The diagrams below show a general endian system and the endian adopted for the M32R family microcomputers.
Bit endian
(H'01)
Big endian
B'0000001
b0
Little endian
Byte endian
(H'01234567)
b7
B'0000001
b7
b0
H'01
H'23
H'45
H'67
HH
HL
LH
LL
H'67
H'45
H'23
H'01
LL
LH
HL
HH
Note: • Even when bits are arranged in big endian, H'01 is not B'10000000.
Figure 2.6.4 General Endian System
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2.6 Data Formats
Renesas
microcomputer
family name
7700 and M16C families
Endian
(bit/byte)
Little/little
M32R family
Little/big
Big/big
Address
+0
+1
+2
+3
+0
+1
+2
+3
+0
+1
+2
+3
Data arrangement
LL
LH
HL
HH
HH
HL
LH
LL
HH
HL
LH
LL
7–0
15–8
31–24
31–24
23–16
15–8
7–0
0–7
8–15
Bit number
Example:
0x01234567
23–16
.byte 67,45,23,01
.byte 01,23,45,67
16–23
24–31
.byte 01,23,45,67
Note: • The M32R family uses the big endian for both bits and bytes.
Figure 2.6.5 Endian Adopted for the M32R Family
(4) Transfer instructions
• Constant transfer
LD24
Rdest, #imm24
imm24
LD24
Rdest, #imm24
LDI
Rdest, #imm16
LDI
Rdest, #imm8
SETH Rdest, #imm16
b0
b23
Rdest
00
b0
8
b31
SETH Rdest, #imm16
imm16
b0
b15
Rdest
00
b0
15
00
b31
• Register to register transfer
MV
MV
Rdest, Rsrc
Rdest, Rsrc
Rsrc
b31
b0
Rdest
b0
b31
• Control register transfer
MVTC Rsrc, CRdest
MVFC Rdest, CRsrc
Rsrc
MVTC Rsrc, CRdest
b0
b31
CRdest
b0
b31
Note: • The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction.
Figure 2.6.6 Transfer Instructions
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2.6 Data Formats
(5) Transfer from memory (signed) to registers
LD24 Rsrc, #label
LD
Rdest, @Rsrc
Register
Memory
• Signed 32 bits
label
Rdest
+0
+1
+2
+3
b0
b31
• Signed 16 bits
label
LD24 Rsrc, #label
LDH Rdest, @Rsrc
• Signed 8 bits
LD24 Rsrc, #label
LDB Rdest, @Rsrc
Rdest
+0
+1
+2
+3
Determined by MSB
0: Positive number
1: Negative number
label
00
00
FF
FF
b0
b31
Rdest
+3
+0
+1
+2
Determined by MSB
0: Positive number
1: Negative number
00
00
00
FF
FF
FF
b0
b31
Figure 2.6.7 Transfer from Memory (Signed) to Registers
(6) Transfer from memory (unsigned) to registers
Register
Memory
• Unsigned 32 bits
LD24 Rsrc, #label
LD
Rdest, @Rsrc
Rdest
label
+0
+1
+2
+3
b0
b31
• Unsigned 16 bits
LD24 Rsrc, #label
LDUH Rdest, @Rsrc
• Unsigned 8 bits
label
Rdest
00
+0
+1
+2
+3
label
00
b0
b31
Rdest
LD24 Rsrc, #label
LDUB Rdest, @Rsrc
00
+0
+1
+2
+3
b0
00
00
b31
Figure 2.6.8 Transfer from Memory (Unsigned) to Registers
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2.6 Data Formats
(7) Notes on data transfer
When transferring data, be aware that data arrangements in registers and memory are different.
Data in registers
Data in memory
• Word data (32 bits)
(R0–R15)
HH
+0
HL
LH
b0
LL
+1
HH
b31
HL
+2
+3
LH
LL
b0
b31
• Halfword data (16 bits)
(R0–R15)
H
b0
+0
+1
H
L
L
b31
b0
(R0–R15)
b0
+3
+2
+3
H
L
b15
+0
H
+2
+1
L
b31
b16
b31
• Byte data (8 bits)
(R0–R15)
b0
+0
b31
(R0–R15)
b0
b31
b8
+0
+3
+1
+2
+3
+2
+3
b15
+1
b31
(R0–R15)
b0
+2
b7
+0
(R0–R15)
b0
b0
+1
b16 b23
+0
b31
+1
+2
+3
b24 b31
Figure 2.6.9 Difference in Data Arrangements
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CPU
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK
Instruction Execution
The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR
instruction finishes.
The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction
is used to clear the LOCK bit.
The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit
controls granting of bus control requested by devices other than the CPU.
• When LOCK bit = "0"
Control of the bus requested by devices other than the CPU is granted
• When LOCK bit = "1"
Control of the bus requested by devices other than the CPU is denied
In the 32182 group, control of the bus may be requested by devices other than the CPU in the following two cases:
• When DMA transfer is requested by the internal DMAC
• When HREQ# input is pulled low to request that the CPU be placed in a hold state
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CHAPTER 3
ADDRESS SPACE
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Outline of the Address Space
Operation Modes
Internal ROM and Extended External Areas
Internal RAM and SFR Areas
EIT Vector Entry
ICU Vector Table
Notes about Address Space
ADDRESS SPACE
3
3.1 Outline of the Address Space
3.1 Outline of the Address Space
The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4
Gbytes. The address space of the M32R/ECU consists of the following:
(1) User space
• Internal ROM area
• Extended external area
• Internal RAM area
• SFR (Special Function Register) area
(2) System space (not open to the user)
(1) User space
The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space.
Located in this space are the internal ROM area, an extended external area, the internal RAM area and the
SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the
internal ROM and extended external areas are located differently depending on mode settings as will be
described later.
(2) System space
The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space.
This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and
cannot be used by the user.
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ADDRESS SPACE
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3.1 Outline of the Address Space
EIT vector entry
Logical address
H'0000 0000
H'0000 0000
Internal ROM area
384 Mbytes
(Note 1)
H'0005 FFFF
16 Mbytes
H'0006 0000
CS0 area
H'001F FFFF
H'0020 0000
CS1 area
User space
H'003F FFFF
H'0040 0000
2 Gbytes
Ghost area
in 16-Mbyte
units
CS2 area
H'005F FFFF
H'0060 0000
CS3 area
H'7FFF FFFF
H'8000 0000
SFR area
16 Kbytes
H'007F FFFF
H'0080 0000
H'0080 3FFF
H'0080 4000
RAM area
64 Kbytes
H'0081 3FFF
H'0081 4000
2 Gbytes
Reserved area
48 Kbytes
System space
H'0081 FFFF
H'0082 0000
Ghost area in
128-Kbyte units
H'FFFF FFFF
H'00FF FFFF
Note 1: This area is located differently depending on how chip mode is set.
Figure 3.1.1 Address Space of the M32182F3
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ADDRESS SPACE
3
3.1 Outline of the Address Space
EIT vector entry
Logical address
H'0000 0000
H'0000 0000
Internal ROM area
1 Mbyte
(Note 1)
H'000F FFFF
16 Mbytes
H'0010 0000
CS0 area
H'001F FFFF
H'0020 0000
CS1 area
User space
H'003F FFFF
H'0040 0000
2 Gbytes
Ghost area
in 16-Mbyte
units
CS2 area
H'005F FFFF
H'0060 0000
CS3 area
H'7FFF FFFF
H'8000 0000
SFR area
16 Kbytes
H'007F FFFF
H'0080 0000
H'0080 3FFF
H'0080 4000
RAM area
64 Kbytes
H'0081 3FFF
H'0081 4000
2 Gbytes
Reserved area
48 Kbytes
System space
H'0081 FFFF
H'0082 0000
Ghost area in
128-Kbyte units
H'FFFF FFFF
H'00FF FFFF
Note 1: This area is located differently depending on how chip mode is set.
Figure 3.1.2 Address Space of the M32182F8
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ADDRESS SPACE
3
3.2 Operation Modes
3.2 Operation Modes
The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by
MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately
in Section 6.5, “Programming the Internal Flash Memory.”
Table 3.2.1 Operation Mode Settings
MOD0
MOD1 (Note 1)
Operation mode (Note 2)
VSS
VSS
Single-chip mode
VSS
VCCE
External extension mode
VCCE
VSS
Processor mode (FP = VSS)
VCCE
VCCE
Reserved (use inhibited)
Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively.
Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above
table, see Section 6.5, “Programming the Internal Flash Memory.”
The internal ROM and extended external areas are located differently depending on how operation mode is set.
(All other areas in the address space are located the same way.) The diagram below shows how the internal ROM
and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode,
see Section 6.5, “Programming the Internal Flash Memory.”)
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ADDRESS SPACE
3
3.2 Operation Modes
Pin function (Note 1)
Logical address
H'0000 0000
H'0005 FFFF
H'0006 0000
CS0#
CS0#
CS0#
CS1#
CS1#
CS1#
CS0#
CS1#
A11 / CS2#
A11 / CS2#
A11 / CS2#
A11 / CS2#
A12 / CS3#
A12 / CS3#
A12 / CS3#
A12 / CS3#
Internal ROM
(384 Kbytes)
Internal ROM
(384 Kbytes)
Internal ROM
(384 Kbytes)
Internal ROM
(384 Kbytes)
Reserved area
(640 Kbytes)
Reserved area
(640 Kbytes)
Reserved area
(640 Kbytes)
Reserved area
(640 Kbytes)
CS0 area
(512 Kbytes)
CS0 area
(512 Kbytes)
CS1 area
(512 Kbytes)
CS1 area
(512 Kbytes)
H'000F FFFF
H'0010 0000
CS0 area
(1 Mbyte)
CS0 area
(1 Mbyte)
H'001F FFFF
H'0020 0000
CS1 area
(1 Mbyte)
CS1 area
(2 Mbytes)
CS1 area
(512 Kbytes)
H'003F FFFF
H'0040 0000
CS2 area
(512 Kbytes)
CS2 area
(1 Mbyte)
H'005F FFFF
H'0060 0000
CS3 area
(512 Kbytes)
CS3 area
(512 Kbytes)
CS3 area
(512 Kbytes)
H'007F FFFF
Note 1: Enclosed in
are the valid pin function.
Figure 3.2.1 Internal ROM and Extended External Area of the M32182F3 in External Extension Mode
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ADDRESS SPACE
3
3.2 Operation Modes
Pin function (Note 1)
Logical address
CS0#
CS0#
CS0#
CS1#
CS1#
CS1#
CS0#
CS1#
A11 / CS2#
A11 / CS2#
A11 / CS2#
A11 / CS2#
A12 / CS3#
A12 / CS3#
A12 / CS3#
A12 / CS3#
Internal ROM
Internal ROM
Internal ROM
Internal ROM
(1 Mbyte)
(1 Mbyte)
(1 Mbyte)
(1 Mbyte)
CS0 area
(512 Kbytes)
CS0 area
(512 Kbytes)
CS1 area
(512 Kbytes)
CS1 area
(512 Kbytes)
H'0000 0000
H'000F FFFF
H'0010 0000
CS0 area
(1 Mbyte)
CS0 area
(1 Mbyte)
H'001F FFFF
H'0020 0000
CS1 area
(1 Mbyte)
CS1 area
(2 Mbytes)
CS1 area
(512 Kbytes)
H'003F FFFF
H'0040 0000
CS2 area
(512 Kbytes)
CS2 area
(1 Mbyte)
H'005F FFFF
H'0060 0000
CS3 area
(512 Kbytes)
CS3 area
(512 Kbytes)
CS3 area
(512 Kbytes)
H'007F FFFF
Note 1: Enclosed in
are the valid pin function.
Figure 3.2.2 Internal ROM and Extended External Area of the M32182F8 in External Extension Mode
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ADDRESS SPACE
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3.2 Operation Modes
Pin function (Note 2)
CS0#
CS0#
CS0#
CS1#
CS1#
CS1#
CS0#
CS1#
A11 / CS2#
A11 / CS2#
A11 / CS2#
A11 / CS2#
A12 / CS3#
A12 / CS3#
A12 / CS3#
A12 / CS3#
CS0 area
(512 Kbytes)
CS0 area
(512 Kbytes)
H'0000 0000
CS0 area
(1 Mbyte)
CS0 area
(2 Mbytes)
CS0 area
(512 Kbytes)
H'001F FFFF
H'0020 0000
CS1 area
(512 Kbytes)
CS1 area
(512 Kbytes)
CS1 area
(1 Mbyte)
CS1 area
(2 Mbytes)
CS1 area
(512 Kbytes)
H'003F FFFF
H'0040 0000
CS2 area
(512 Kbytes)
CS2 area
(1 Mbyte)
H'005F FFFF
H'0060 0000
CS3 area
(512 Kbytes)
CS3 area
(512 Kbytes)
CS3 area
(512 Kbytes)
H'007F FFFF
Note 2: Enclosed in
are the valid pin function.
Figure 3.2.3 Extended External Area in Processor Mode
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ADDRESS SPACE
3
3.3 Internal ROM and Extended External Areas
3.3 Internal ROM and Extended External Areas
The 8-Mbyte area in the user space from the address H’0000 0000 to the address H’007F FFFF comprise the
internal ROM and extended external areas. For the address mapping of these areas that differs with each operation mode, see Section 3.2, “Operation Modes.”
3.3.1 Internal ROM Area
The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT
vector entry (and the ICU vector table).
Table 3.3.1 Internal ROM Allocation Address
Type Name
Size
Allocation Address
M32182F3
384 Kbytes
H’0000 0000 to H’0005 FFFF
M32182F8
1 Mbyte
H’0000 0000 to H’000F FFFF
3.3.2 Extended External Area
The extended external area is only available when external extension or processor mode is selected by operation mode settings. When accessing the extended external area, the control signals necessary to access external devices are output.
The CS0# through CS3# signals are output corresponding to the address mapping of the extended external
area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respectively.
Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode
Operation Mode
Address Mapping of Extended External Area
Single-chip mode
None
External extension mode
H’0010 0000 to H’001F FFFF (CS0 area: 1 Mbyte)
H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes)
H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes)
H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes)
Processor mode
H’0000 0000 to H’001F FFFF (CS0 area: 2 Mbytes)
H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes)
H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes)
H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes)
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3.4 Internal RAM and SFR Areas
3.4 Internal RAM and SFR Areas
The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and
SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area
from the address H’0080 0000 to the address H’0081 FFFF. The other areas here are ghosts in 128-Kbyte units.
(Do not use the ghost area intentionally during programming.)
3.4.1 Internal RAM Area
The internal RAM area is allocated to the addresses shown below.
Table 3.4.1 Internal RAM Allocation Address
Type Name
Size
Allocation Address
M32182F3
64 Kbytes
H’0080 4000 to H’0081 3FFF
M32182F8
64 Kbytes
H’0080 4000 to H’0081 3FFF
3.4.2 SFR (Special Function Register) Area
The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in
this area are the internal peripheral I/O registers.
H'0080 0000
SFR area
(16 Kbytes)
H'0080 3FFF
H'0080 4000
H'0080 7FFF
H'0080 8000
Virtual flash emulation areas
separated in 4-Kbyte units
can be allocated here.
For details, see Section 6.6.
Internal RAM
(64 Kbytes)
H'0080 FFFF
H'0081 0000
H'0081 3FFF
Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32182F3
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ADDRESS SPACE
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3.4 Internal RAM and SFR Areas
0
7 8
15
0
+0 address +1 address
7
8
15
+0 address +1 address
H'0080 0000
H'0080 0FE0
H'0080 0FFE
H'0080 1000
Interrupt Controller
(ICU)
H'0080 007E
H'0080 0080
MJT(TML1)
CAN0
A-D Converter
H'0080 11FE
H'0080 00EE
H'0080 1400
H'0080 0100
Serial I/O
CAN1
H'0080 0146
H'0080 15FE
H'0080 0180
H'0080 0186
H'0080 01E0
H'0080 01F8
H'0080 0200
H'0080 023E
H'0080 0240
Wait Controller
H'0080 3FFE
Flash control
MJT (common part)
MJT(TOP)
H'0080 02FE
H'0000 0300
Multijunction
timer (MJT)
MJT(TIO)
H'0080 03BE
H'0080 03C0
H'0080 03DE
H'0080 03E0
H'0080 03FE
H'0080 0400
MJT(TMS)
MJT(TML0)
DMAC
H'0080 0478
H'0080 0700
Input/output port
H'0080 0786
Note: • The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to
the CPU.
Figure 3.4.2 Outline Mapping of the SFR Area
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ADDRESS SPACE
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3.4 Internal RAM and SFR Areas
SFR Area Register Map (1/21)
Address
+0 address
b0
H'0080 0000
H'0080 0002
H'0080 0004
H'0080 0006
|
H'0080 0066
H'0080 0068
H'0080 006A
H'0080 006C
H'0080 006E
H'0080 0070
H'0080 0072
H'0080 0074
H'0080 0076
H'0080 0078
H'0080 007A
H'0080 007C
H'0080 007E
H'0080 0080
H'0080 0082
b15
Interrupt Request Mask Register
(IMASK)
SBI Control Register
(SBICR)
|
H'0080 0060
+1 address
b7 b8
Interrupt Vector Register
(IVECT)
(Use inhibited area)
(Use inhibited area)
5-6
(Use inhibited area)
5-7
(Use inhibited area)
5-8
RTD Interrupt Control Register
(IRTDCR)
DMA5–9 Interrupt Control Register
(IDMA59CR)
5-8
(Use inhibited area)
CAN0 Transmit/Receive & Error Interrupt Control Register
(ICAN0CR)
(Use inhibited area)
(Use inhibited area)
SIO2, 3 Transmit/Receive Interrupt Control Register
(ISIO23CR)
(Use inhibited area)
A-D0 Conversion Interrupt Control Register
(IAD0CCR)
SIO0 Receive Interrupt Control Register
(ISIO0RXCR)
SIO1 Receive Interrupt Control Register
(ISIO1RXCR)
TIO0–3 Output Interrupt Control Register
(ITIO03CR)
TOP0–5 Output Interrupt Control Register
(ITOP05CR)
TIO4–7 Output Interrupt Control Register
(ITIO47CR)
TIO8,9 Output Interrupt Control Register
(ITOP89CR)
(Use inhibited area)
SIO0 Transmit Interrupt Control Register
(ISIO0TXCR)
SIO1 Transmit Interrupt Control Register
(ISIO1TXCR)
DMA0–4 Interrupt Control Register
(IDMA04CR)
TOP6, 7 Output Interrupt Control Register
(ITOP67CR)
TIO8, 9 Output Interrupt Control Register
(ITIO89CR)
TOP10 Output Interrupt Control Register
(ITOP10CR)
TMS0, 1 Output Interrupt Control Register
(ITMS01CR)
TIN0–2 Input Interrupt Control Register
(ITIN02CR)
TIN12–19 Input Interrupt Control Register
TIN20–29 Input Interrupt Control Register
(ITIN1219CR)
(ITIN2029CR)
TIN3–6 Input Interrupt Control Register
CAN1 Transmit/Receive & Error Interrupt Control Register
(ITIN36CR)
(ICAN1CR)
A-D0 Single Mode Register 0
A-D0 Single Mode Register 1
(AD0SIM0)
(AD0SIM1)
(Use inhibited area)
H'0080 0084
A-D0 Scan Mode Register 0
A-D0 Scan Mode Register 1
(AD0SCM0)
(AD0SCM1)
H'0080 0086 A-D0 Disconnection Detection Assist Function Control Register
A-D0 Conversion Speed Control Register
(AD0DDACR)
(AD0CVSCR)
H'0080 0088
A-D0 Successive Approximation Register
(AD0SAR)
H'0080 008A
A-D0 Disconnection Detection Assist Method Select Register
(AD0DDASEL)
H'0080 008C
A-D0 Comparate Data Register
(AD0CMP)
H'0080 008E
(Use inhibited area)
H'0080 0090
H'0080 0092
H'0080 0094
H'0080 0096
H'0080 0098
H'0080 009A
H'0080 009C
See
pages
5-5
10-bit A-D0 Data Register
(AD0DT0)
10-bit A-D0 Data Register
(AD0DT1)
10-bit A-D0 Data Register
(AD0DT2)
10-bit A-D0 Data Register
(AD0DT3)
10-bit A-D0 Data Register
(AD0DT4)
10-bit A-D0 Data Register
(AD0DT5)
10-bit A-D0 Data Register
(AD0DT6)
3-12
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
11-14
11-16
11-18
11-20
11-23
11-22
11-27
11-24
11-28
0
11-29
1
11-29
2
11-29
3
11-29
4
11-29
5
11-29
6
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ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (2/21)
Address
+0 address
b0
H'0080 009E
H'0080 00A0
H'0080 00A2
H'0080 00A4
H'0080 00A6
|
H'0080 00D0
(Use inhibited area)
H'0080 00D2
(Use inhibited area)
H'0080 00D4
(Use inhibited area)
H'0080 00D6
(Use inhibited area)
H'0080 00D8
(Use inhibited area)
H'0080 00DA
(Use inhibited area)
H'0080 00DC
(Use inhibited area)
H'0080 00DE
(Use inhibited area)
H'0080 00E0
(Use inhibited area)
H'0080 00E2
(Use inhibited area)
H'0080 00E4
(Use inhibited area)
H'0080 00E6
(Use inhibited area)
|
H'0080 0100
H'0080 0102
|
H'0080 0110
H'0080 0112
H'0080 0114
H'0080 0116
|
H'0080 0120
H'0080 0122
H'0080 0124
H'0080 0126
|
H'0080 0130
H'0080 0132
H'0080 0134
+1 address
b7 b8
10-bit A-D0 Data Register 7
(AD0DT7)
10-bit A-D0 Data Register 8
(AD0DT8)
10-bit A-D0 Data Register 9
(AD0DT9)
10-bit A-D0 Data Register 10
(AD0DT10)
10-bit A-D0 Data Register 11
(AD0DT11)
(Use inhibited area)
b15
See
pages
11-29
11-29
11-29
11-29
11-29
8-bit A-D0 Data Register 0
(AD08DT0)
8-bit A-D0 Data Register 1
(AD08DT1)
8-bit A-D0 Data Register 2
(AD08DT2)
8-bit A-D0 Data Register 3
(AD08DT3)
8-bit A-D0 Data Register 4
(AD08DT4)
8-bit A-D0 Data Register 5
(AD08DT5)
8-bit A-D0 Data Register 6
(AD08DT6)
8-bit A-D0 Data Register 7
(AD08DT7)
8-bit A-D0 Data Register 8
(AD08DT8)
8-bit A-D0 Data Register 9
(AD08DT9)
8-bit A-D0 Data Register 10
(AD08DT10)
8-bit A-D0 Data Register 11
(AD08DT11)
11-30
11-30
11-30
11-30
11-30
11-30
11-30
11-30
11-30
11-30
11-30
11-30
(Use inhibited area)
SIO23 Interrupt Request Status Register
SIO03 Interrupt Request Enable Register
(SI23STAT)
(SI03EN)
SIO03 Interrupt Request Source Select Register
(Use inhibited area)
(SI03SEL)
(Use inhibited area)
12-9
12-10
12-11
SIO0 Transmit Control Register
SIO0 Transmit/Receive Mode Register
(S0TCNT)
(S0MOD)
SIO0 Transmit Buffer Register
(S0TXB)
SIO0 Receive Buffer Register
(S0RXB)
SIO0 Receive Control Register
SIO0 Baud Rate Register
(S0RCNT)
(S0BAUR)
(Use inhibited area)
12-13
12-14
12-17
SIO1 Transmit Control Register
SIO1 Transmit/Receive Mode Register
(S1TCNT)
(S1MOD)
SIO1 Transmit Buffer Register
(S1TXB)
SIO1 Receive Buffer Register
(S1RXB)
SIO1 Receive Control Register
SIO1 Baud Rate Register
(S1RCNT)
(S1BAUR)
(Use inhibited area)
12-13
12-14
12-17
SIO2 Transmit Control Register
SIO2 Transmit/Receive Mode Register
(S2TCNT)
(S2MOD)
SIO2 Transmit Buffer Register
(S2TXB)
SIO2 Receive Buffer Register
(S2RXB)
12-13
12-14
12-17
3-13
12-18
12-19
12-22
12-18
12-19
12-22
12-18
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (3/21)
Address
+0 address
+1 address
b0
H'0080 0136
b7 b8
SIO2 Receive Control Register
(S2RCNT)
|
H'0080 0140
H'0080 0142
H'0080 0144
H'0080 0146
|
H'0080 0180
H'0080 0182
H'0080 01E2
H'0080 01E4
SIO2 Baud Rate Register
(S2BAUR)
SIO3 Transmit Control Register
SIO3 Transmit/Receive Mode Register
(S3TCNT)
(S3MOD)
SIO3 Transmit Buffer Register
(S3TXB)
SIO3 Receive Buffer Register
(S3RXB)
SIO3 Receive Control Register
SIO3 Baud Rate Register
(S3RCNT)
(S3BAUR)
(Use inhibited area)
12-13
12-14
12-17
CS0 Area Wait Control Register
(CS0WTCR)
CS2 Area Wait Control Register
(CS2WTCR)
CS1 Area Wait Control Register
(CS1WTCR)
CS3 Area Wait Control Register
(CS3WTCR)
16-4
Flash Status Register 1
(FSTAT1)
Flash Control Register 2
(FCNT2)
Flash Control Register 4
(FCNT4)
6-5
6-6
6-8
6-9
6-10
Flash Mode Register
(FMOD)
Flash Control Register 1
(FCNT1)
Flash Control Register 3
(FCNT3)
(Use inhibited area)
H'0080 01E8
Virtual Flash S Bank Register 0
(FESBANK0)
Virtual Flash S Bank Register 1
(FESBANK1)
Virtual Flash S Bank Register 2
(FESBANK2)
Virtual Flash S Bank Register 3
(FESBANK3)
Virtual Flash S Bank Register 4
(FESBANK4)
Virtual Flash S Bank Register 5
(FESBANK5)
Virtual Flash S Bank Register 6
(FESBANK6)
Virtual Flash S Bank Register 7
(FESBANK7)
(Use inhibited area)
H'0080 01EA
H'0080 01EC
H'0080 01EE
H'0080 01F0
H'0080 01F2
H'0080 01F4
H'0080 01F6
|
H'0080 0200
(Use inhibited area)
H'0080 0202
Prescaler Register 0
(PRS0)
Prescaler Register 2
(PRS2)
|
H'0080 0210
H'0080 0212
|
H'0080 0218
H'0080 021A
|
H'0080 0220
H'0080 0222
12-18
12-19
12-22
16-4
(Use inhibited area)
H'0080 01E6
H'0080 0204
See
Pages
12-19
12-22
(Use inhibited area)
|
H'0080 01E0
b15
6-12
6-12
6-12
6-12
6-12
6-12
6-12
6-12
Clock Bus & Input Event Bus Control Register
(CKIEBCR)
Prescaler Register 1
(PRS1)
Output Event Bus Control Register
(OEBCR)
(Use inhibited area)
10-14
10-10
10-10
10-15
TCLK Input Processing Control Register
(TCLKCR)
TIN0–4 Input Processing Control Register
(TIN04CR)
(Use inhibited area)
10-18
TIN12–19 Input Processing Control Register
(TIN1219CR)
TIN20–23, TIN30–33 Input Processing Control Register
(TIN2023_3033CR)
(Use inhibited area)
10-20
10-19
F/F6–15 Source Select Register
(FF615S)
(Use inhibited area)
F/F16–19 Source Select Register
(FF1619S)
3-14
10-20
10-22
10-23
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (4/21)
Address
+0 address
b0
H'0080 0224
H'0080 0226
H'0080 0228
(Use inhibited area)
H'0080 022A
(Use inhibited area)
|
H'0080 0230
H'0080 0232
H'0080 0234
H'0080 0236
H'0080 0238
H'0080 023A
H'0080 023C
H'0080 023E
H'0080 0240
H'0080 0242
H'0080 0244
H'0080 0246
|
H'0080 0250
H'0080 0252
H'0080 0254
H'0080 0256
|
H'0080 0260
H'0080 0262
H'0080 0264
H'0080 0266
|
H'0080 0270
H'0080 0272
H'0080 0274
H'0080 0276
|
H'0080 0280
H'0080 0282
+1 address
b7 b8
F/F0–15 Protect Register
(FF015P)
F/F0–15 Data Register
(FF015D)
b15
See
pages
10-24
10-25
F/F16–20 Protect Register
(FF1620P)
F/F16–20 Data Register
(FF1620D)
10-24
10-25
(Use inhibited area)
TOP0–5 Interrupt Request Status Register
TOP0–5 Interrupt Request Mask Register
(TOP05IST)
(TOP05IMA)
TOP6, 7 Interrupt Request Mask & Status Register
TOP8, 9 Interrupt Request Mask & Status Register
(TOP67IMS)
(TOP89IMS)
TIO0–3 Interrupt Request Mask & Status Register
TIO4–7 Interrupt Request Mask & Status Register
(TIO03IMS)
(TIO47IMS)
TIO8, 9 Interrupt Request Mask & Status Register
TMS0, 1 Interrupt Request Mask & Status Register
(TIO89IMS)
(TMS01IMS)
TIN0–2 Interrupt Request Mask & Status Register
TIN3–6 Interrupt Request Mask & Status Register
(TIN02IMS)
(TIN36IMS)
(Use inhibited area)
TIN12–19 Interrupt Request Status Register
TIN12–19 Interrupt Request Mask Register
(TIN1219IST)
(TIN1219IMA)
TIN20–23 Interrupt Request Mask & Status Register
(Use inhibited area)
(TIN2023IMS)
TOP0 Counter
(TOP0CT)
TOP0 Reload Register
(TOP0RL)
(Use inhibited area)
10-30
10-32
10-33
10-34
10-35
10-36
10-37
10-38
10-39
10-40
10-42
10-54
10-55
TOP0 Correction Register
(TOP0CC)
(Use inhibited area)
10-56
TOP1 Counter
(TOP1CT)
TOP1 Reload Register
(TOP1RL)
(Use inhibited area)
10-54
10-55
TOP1 Correction Register
(TOP1CC)
(Use inhibited area)
10-56
TOP2 Counter
(TOP2CT)
TOP2 Reload Register
(TOP2RL)
(Use inhibited area)
10-54
10-55
TOP2 Correction Register
(TOP2CC)
(Use inhibited area)
10-56
TOP3 Counter
(TOP3CT)
TOP3 Reload Register
(TOP3RL)
(Use inhibited area)
10-54
10-55
TOP3 Correction Register
(TOP3CC)
(Use inhibited area)
10-56
TOP4 Counter
(TOP4CT)
TOP4 Reload Register
(TOP4RL)
10-54
3-15
10-55
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFSFR Area Register Map (5/21)
Address
+0 address
b0
H'0080 0284
H'0080 0286
|
H'0080 0290
H'0080 0292
H'0080 0294
H'0080 0296
H'0080 0298
H'0080 029A
H'0080 029C
|
H'0080 02A0
H'0080 02A2
H'0080 02A4
H'0080 02A6
H'0080 02A8
H'0080 02AA
|
H'0080 02B0
H'0080 02B2
H'0080 02B4
H'0080 02B6
|
H'0080 02C0
H'0080 02C2
H'0080 02C4
H'0080 02C6
|
H'0080 02D0
H'0080 02D2
H'0080 02D4
H'0080 02D6
|
H'0080 02E0
H'0080 02E2
+1 address
b7 b8
(Use inhibited area)
b15
See
pages
TOP4 Correction Register
(TOP4CC)
(Use inhibited area)
10-56
TOP5 Counter
(TOP5CT)
TOP5 Reload Register
(TOP5RL)
(Use inhibited area)
10-54
10-55
TOP5 Correction Register
(TOP5CC)
(Use inhibited area)
10-56
TOP0–5 Control Register 0
(TOP05CR0)
10-50
(Use inhibited area)
TOP0–5 Control Register 1
(TOP05CR1)
10-50
(Use inhibited area)
TOP6 Counter
(TOP6CT)
TOP6 Reload Register
(TOP6CC)
(Use inhibited area)
10-54
10-55
TOP6 Correction Register
(TOP6CC)
(Use inhibited area)
10-56
TOP6, 7 Control Register
(TOP67CR)
(Use inhibited area)
10-52
TOP7 Counter
(TOP7CT)
TOP7 Reload Register
(TOP7RL)
(Use inhibited area)
10-54
10-55
TOP7 Correction Register
(TOP7CC)
(Use inhibited area)
10-56
TOP8 Counter
(TOP8CT)
TOP8 Reload Register
(TOP8RL)
(Use inhibited area)
10-54
10-55
TOP8 Correction Register
(TOP8CC)
(Use inhibited area)
10-56
TOP9 Counter
(TOP9CT)
TOP9 Reload Register
(TOP9RL)
(Use inhibited area)
10-54
10-55
TOP9 Correction Register
(TOP9CC)
(Use inhibited area)
10-56
TOP10 Counter
(TOP10CT)
TOP10 Reload Register
(TOP10RL)
10-54
3-16
10-55
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (6/21)
Address
+0 address
+1address
b0
b7 b8
(Use inhibited area)
H'0080 02E4
H'0080 02E6
10-56
TOP8–10 Control Register
(TOP810CR)
(Use inhibited area)
10-53
TOP External Enable Permit Register
(TOPEEN)
TOP Enable Protect Register
(TOPPRO)
TOP Count Enable Register
(TOPCEN)
TIO0 Counter
(TIO0CT)
(Use inhibited area)
10-57
H'0080 02EA
|
H'0080 02FC
H'0080 02FE
H'0080 0300
H'0080 0302
H'0080 0304
|
H'0080 0310
H'0080 0312
H'0080 0314
H'0080 0316
H'0080 0318
H'0080 031A
|
H'0080 0320
H'0080 0322
H'0080 0324
H'0080 0326
|
H'0080 0330
H'0080 0332
H'0080 0334
H'0080 0336
|
H'0080 0340
H'0080 0343
H'0080 0344
H'0080 0346
10-57
10-58
10-88
TIO0 Reload 1 Register
(TIO0RL1)
TIO0 Reload 0/ Measure Register
(TIO0RL0)
(Use inhibited area)
H'0080 0306
H'0080 031C
See
pages
TOP10 Correction Register
(TOP10CC)
(Use inhibited area)
H'0080 02E8
H'0080 02FA
b15
10-90
10-89
TIO1 Counter
(TIO1CT)
(Use inhibited area)
10-88
TIO1 Reload 1 Register
(TIO1RL1)
TIO1 Reload 0/ Measure Register
(TIO1RL0)
(Use inhibited area)
10-90
10-89
TIO0–3 Control Register 0
(TIO03CR0)
10-81
(Use inhibited area)
TIO0–3 Control Register 1
(TIO03CR1)
10-82
(Use inhibited area)
TIO2 Counter
(TIO2CT)
(Use inhibited area)
10-88
TIO2 Reload 1 Register
(TIO2RL1)
TIO2 Reload 0/ Measure Register
(TIO2RL0)
(Use inhibited area)
10-90
TIO3 Counter
(TIO3CT)
(Use inhibited area)
10-88
TIO3 Reload 1 Register
(TIO3RL1)
TIO3 Reload 0/ Measure Register
(TIO3RL0)
(Use inhibited area)
10-90
10-89
10-89
TIO4 Counter
(TIO4CT)
(Use inhibited area)
10-88
TIO4 Reload 1 Register
(TIO4RL1)
TIO4 Reload 0/ Measure Register
(TIO4RL0)
10-90
3-17
10-89
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (7/21)
Address
+0 address
b0
H'0080 0348
H'0080 034A
TIO4 Control Register
(TIO4CR)
|
H'0080 0352
H'0080 0354
H'0080 0356
|
H'0080 0360
H'0080 0362
H'0080 0364
H'0080 0366
H'0080 0368
H'0080 0372
H'0080 0374
H'0080 0376
|
H'0080 0380
H'0080 0382
H'0080 0384
H'0080 0386
H'0080 0388
H'0080 0390
H'0080 0392
H'0080 0394
H'0080 0396
|
H'0080 03BC
H'0080 03BE
H'0080 03C0
See
pages
10-83
10-85
TIO5 Counter
(TIO5CT)
(Use inhibited area)
10-88
TIO5 Reload 1 Register
(TIO5RL1)
TIO5 Reload 0/ Measure Register
(TIO5RL0)
(Use inhibited area)
10-90
10-89
TIO6 Counter
(TIO6CT)
(Use inhibited area)
10-88
TIO6 Reload 1 Register
(TIO6RL1)
TIO6 Reload 0/ Measure Register
(TIO6RL0)
(Use inhibited area)
10-90
10-89
TIO7 Control Register
(TIO7CR)
10-86
10-87
(Use inhibited area)
H'0080 0370
|
TIO5 Control Register
(TIO5CR)
TIO6 Control Register
(TIO6CR)
|
H'0080 038A
b15
(Use inhibited area)
H'0080 0350
H'0080 036A
+1 address
b7 b8
(Use inhibited area)
TIO7 Counter
(TIO7CT)
(Use inhibited area)
10-88
TIO7 Reload 1 Register
(TIO7RL1)
TIO7 Reload 0/ Measure Register
(TIO7RL0)
(Use inhibited area)
10-90
10-89
TIO8 Counter
(TIO8CT)
(Use inhibited area)
10-88
TIO8 Reload 1 Register
(TIO8RL1)
TIO8 Reload 0/ Measure Register
(TIO8RL0)
(Use inhibited area)
10-90
TIO8 Control Register
(TIO8CR)
10-89
TIO9 Control Register
(TIO9CR)
10-87
10-88
(Use inhibited area)
TIO9 Counter
(TIO9CT)
(Use inhibited area)
10-88
TIO9 Reload 1 Register
(TIO9RL1)
TIO9 Reload 0/ Measure Register
(TIO9RL0)
(Use inhibited area)
10-90
TIO Enable Protect Register
(TIOPRO)
TIO Count Enable Register
(TIOCEN)
TMS0 Counter
(TMS0CT)
3-18
10-89
10-91
10-92
10-109
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (8/21)
Address
+0 address
+1address
b0
H'0080 03C2
TMS0
H'0080 03C4
TMS0
H'0080 03C6
TMS0
H'0080 03C8
TMS0
H'0080 03CA
b7 b8
Measure 3 Register
(TMS0MR3)
Measure 2 Register
(TMS0MR2)
Measure 1 Register
(TMS0MR1)
Measure 0 Register
(TMS0MR0)
TMS0 Control Register
(TMS0CR)
(Use inhibited area)
H'0080 03D0
TMS1 Counter
(TMS1CT)
TMS1 Measure 3 Register
(TMS1MR3)
TMS1 Measure 2 Register
(TMS1MR2)
TMS1 Measure 1 Register
(TMS1MR1)
TMS1 Measure 0 Register
(TMS1MR0)
(Use inhibited area)
H'0080 03D4
H'0080 03D6
H'0080 03D8
|
H'0080 03E0
TML0 Counter
(TML0CT)
H'0080 03E2
(Use inhibited area)
(Use inhibited area)
H'0080 03F0
TML0 Measure 3 Register
(TML0MR3)
H'0080 03F2
TML0 Measure 2 Register
(TML0MR2)
TML0 Measure 1 Register
(TML0MR1)
|
H'0080 0408
|
H'0080 0410
H'0080 0412
H'0080 0414
H'0080 0416
H'0080 0418
H'0080 041A
10-109
10-109
10-109
10-109
(Upper)
10-114
TML0 Control Register
(TML0CR)
10-113
(Upper)
10-114
(Upper)
10-114
(Upper)
10-114
(Lower)
TML0 Measure 0 Register
(TML0MR0)
H'0080 03FE
H'0080 0400
10-109
(Lower)
H'0080 03FA
H'0080 03FC
10-108
(Lower)
H'0080 03F6
H'0080 03F8
10-109
(Use inhibited area)
|
H'0080 03F4
10-109
(Lower)
|
H'0080 03EA
See
pages
10-109
10-109
TMS1 Control Register
(TMS1CR)
|
H'0080 03D2
b15
(Upper)
10-114
(Lower)
DMA0–4 Interrupt Request Status Register
DMA0–4 Interrupt Request Mask Register
(DM04ITST)
(DM04ITMK)
(Use inhibited area)
9-24
9-25
DMA5–9 Interrupt Request Status Register
DMA5–9 Interrupt Request Mask Register
(DM59ITST)
(DM59ITMK)
(Use inhibited area)
9-24
9-25
DMA0 Channel Control Register 0
DMA0 Channel Control Register 1
(DM0CNT0)
(DM0CNT1)
DMA0 Source Address Register
(DM0SA)
DMA0 Destination Address Register
(DM0DA)
DMA0 Transfer Count Register
(DM0TCT)
DMA5 Channel Control Register 0
DMA5 Channel Control Register 1
(DM5CNT0)
(DM5CNT1)
DMA5 Source Address Register
(DM5SA)
9-6
3-19
9-19
9-20
9-21
9-11
9-19
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (9/21)
Address
+0 address
b0
H'0080 041C
H'0080 041E
H'0080 0420
DMA1
H'0080 0422
H'0080 0424
H'0080 0426
H'0080 0428
DMA6
H'0080 042A
H'0080 042C
H'0080 042E
H'0080 0430
DMA2
H'0080 0432
H'0080 0434
H'0080 0436
H'0080 0438
DMA7
H'0080 043A
H'0080 043C
H'0080 043E
H'0080 0440
DMA3
H'0080 0442
H'0080 0444
H'0080 0446
H'0080 0448
DMA8
H'0080 044A
H'0080 044C
H'0080 044E
H'0080 0450
DMA4
H'0080 0452
H'0080 0454
H'0080 0456
H'0080 0458
H'0080 045A
H'0080 045C
H'0080 045E
H'0080 0460
DMA9
+1 address
b7 b8
DMA5 Destination Address Register
(DM5DA)
DMA5 Transfer Count Register
(DM5TCT)
Channel Control Register 0
DMA1 Channel Control
(DM1CNT0)
(DM1CNT1)
DMA1 Source Address Register
(DM1SA)
DMA1 Destination Address Register
(DM1DA)
DMA1 Transfer Count Register
(DM1TCT)
Channel Control Register 0
DMA6 Channel Control
(DM6CNT0)
(DM6CNT1)
DMA6 Source Address Register
(DM6SA)
DMA6 Destination Address Register
(DM6DA)
DMA6 Transfer Count Register
(DM6TCT)
Channel Control Register 0
DMA2 Channel Control
(DM2CNT0)
(DM2CNT1)
DMA2 Source Address Register
(DM2SA)
DMA2 Destination Address Register
(DM2DA)
DMA2 Transfer Count Register
(DM2TCT)
Channel Control Register 0
DMA7 Channel Control
(DM7CNT0)
(DM7CNT1)
DMA7 Source Address Register
(DM7SA)
DMA7 Destination Address Register
(DM7DA)
DMA7 Transfer Count Register
(DM7TCT)
Channel Control Register 0
DMA3 Channel Control
(DM3CNT0)
(DM3CNT1)
DMA3 Source Address Register
(DM3SA)
DMA3 Destination Address Register
(DM3DA)
DMA3 Transfer Count Register
(DM3TCT)
Channel Control Register 0
DMA8 Channel Control
(DM8CNT0)
(DM8CNT1)
DMA8 Source Address Register
(DM8SA)
DMA8 Destination Address Register
(DM8DA)
DMA8 Transfer Count Register
(DM8TCT)
Channel Control Register 0
DMA4 Channel Control
(DM4CNT0)
(DM4CNT1)
DMA4 Source Address Register
(DM4SA)
DMA4 Destination Address Register
(DM4DA)
DMA4 Transfer Count Register
(DM4TCT)
Channel Control Register 0
DMA9 Channel Control
(DM9CNT0)
(DM9CNT1)
DMA9 Source Address Register
(DM9SA)
DMA9 Destination Address Register
(DM9DA)
DMA9 Transfer Count Register
(DM9TCT)
DMA0 Software Request Generation Register
(DM0SRI)
3-20
b15
See
pages
9-20
9-21
Register 1
9-7
9-19
9-20
9-21
Register 1
9-12
9-19
9-20
9-21
Register 1
9-8
9-19
9-20
9-21
Register 1
9-13
9-19
9-20
9-21
Register 1
9-9
9-19
9-20
9-21
Register 1
9-14
9-19
9-20
9-21
Register 1
9-10
9-19
9-20
9-21
Register 1
9-15
9-19
9-20
9-21
9-18
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (10/21)
Address
+0 address
b0
H'0080 0462
DMA1
H'0080 0464
DMA2
H'0080 0466
DMA3
H'0080 0468
DMA4
|
H'0080 0470
H'0080 0472
H'0080 0474
H'0080 0476
H'0080 0478
|
H'0080 0700
H'0080 0702
H'0080 0704
H'0080 0706
H'0080 0708
H'0080 070A
H'0080 070C
H'0080 070E
H'0080 0710
H'0080 0712
H'0080 0714
H'0080 0716
DMA5 Software Request Generation
(DM5SRI)
DMA6 Software Request Generation
(DM6SRI)
DMA7 Software Request Generation
(DM7SRI)
DMA8 Software Request Generation
(DM8SRI)
DMA9 Software Request Generation
(DM9SRI)
(Use inhibited area)
P0 Data Register
(P0DATA)
P2 Data Register
(P2DATA)
P4 Data Register
(P4DATA)
P6 Data Register
(P6DATA)
P8 Data Register
(P8DATA)
P10 Data Register
(P10DATA)
P12 Data Register
(P12DATA)
P14 Data Register
(P14DATA)
P16 Data Register
(P16DATA)
P18 Data Register
(P18DATA)
P20 Data Register
(P20DATA)
P22 Data Register
(P22DATA)
|
H'0080 0720
H'0080 0722
H'0080 0724
H'0080 0726
H'0080 0728
H'0080 072A
H'0080 072C
H'0080 072E
H'0080 0730
H'0080 0732
H'0080 0734
+1 address
b7 b8
Software Request Generation
(DM0SRI)
Software Request Generation
(DM2SRI)
Software Request Generation
(DM3SRI)
Software Request Generation
(DM4SRI)
(Use inhibited area)
Register
See
pages
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
b15
P1 Data Register
(P1DATA)
P3 Data Register
(P3DATA)
(Use inhibited area)
P7 Data Register
(P7DATA)
P9 Data Register
(P9DATA)
P11 Data Register
(P11DATA)
P13 Data Register
(P13DATA)
P15 Data Register
(P15DATA)
P17 Data Register
(P17DATA)
P19 Data Register
(P19DATA)
P21 Data Register
(P21DATA)
(Use inhibited area)
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
(Use inhibited area)
P0 Direction Register
(P0DIR)
P2 Direction Register
(P2DIR)
P4 Direction Register
(P4DIR)
P6 Direction Register
(P6DIR)
P8 Direction Register
(P8DIR)
P10 Direction Register
(P10DIR)
P12 Direction Register
(P12DIR)
P14 Direction Register
(P14DIR)
P16 Direction Register
(P16DIR)
P18 Direction Register
(P18DIR)
P20 Direction Register
(P20DIR)
P1 Direction Register
(P1DIR)
P3 Direction Register
(P3DIR)
(Use inhibited area)
P7 Direction Register
(P7DIR)
P9 Direction Register
(P9DIR)
P11 Direction Register
(P11DIR)
P13 Direction Register
(P13DIR)
P15 Direction Register
(P15DIR)
P17 Direction Register
(P17DIR)
P19 Direction Register
(P19DIR)
P21 Direction Register
(P21DIR)
3-21
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (11/21)
Address
+0 address
b0
H'0080 0736
H'0080 0742
H'0080 0744
H'0080 0746
H'0080 0748
H'0080 074A
H'0080 074C
H'0080 074E
H'0080 0750
H'0080 0752
H'0080 0754
H'0080 0756
H'0080 0762
H'0080 0764
|
H'0080 076A
|
H'0080 0776
|
H'0080 077E
P0 Operation Mode Register
(P0MOD)
P2 Operation Mode Register
(P2MOD)
P4 Operation Mode Register
(P4MOD)
P6 Operation Mode Register
(P6MOD)
P8 Operation Mode Register
(P8MOD)
P10 Operation Mode Register
(P10MOD)
P12 Operation Mode Register
(P12MOD)
P14 Operation Mode Register
(P14MOD)
P16 Operation Mode Register
(P16MOD)
P18 Operation Mode Register
(P18MOD)
P20 Operation Mode Register
(P20MOD)
P22 Operation Mode Register
(P22MOD)
P1 Operation Mode Register
(P1MOD)
P3 Operation Mode Register
(P3MOD)
Port Input Special Function Control Register
(PICNT)
P7 Operation Mode Register
(P7MOD)
P9 Operation Mode Register
(P9MOD)
P11 Operation Mode Register
(P11MOD)
P13 Operation Mode Register
(P13MOD)
P15 Operation Mode Register
(P15MOD)
P17 Operation Mode Register
(P17MOD)
P19 Operation Mode Register
(P19MOD)
P21 Operation Mode Register
(P21MOD)
(Use inhibited area)
Port Group 0, 1 Input Level Setting Register
Port Group 2, 3 Input Level Setting Register
(PG01LEV)
(PG23LEV)
Port Group 4, 5 Input Level Setting Register
Port Group 6, 7 Input Level Setting Register
(PG45LEV)
(PG67LEV)
Port Group 8 Input Level Setting Register
(Use inhibited area)
(PG8LEV)
(Use inhibited area)
8-19
8-25
8-25
8-25
8-20
P22 Peripheral Output Select Register
(P22SMOD)
(Use inhibited area)
(Use inhibited area)
8-20
Bus Mode Control Register
(BUSMODC)
15-9
(Use inhibited area)
18-5
(Upper)
10-114
(Use inhibited area)
(Use inhibited area)
Clock Control Register
(CLKCR)
(Use inhibited area)
TML1 Counter
(TML1CT)
H'0080 0FE2
(Lower)
|
H'0080 0FF0
8-11
8-21
8-11
8-12
8-12
8-13
8-13
8-14
8-14
8-15
8-15
8-16
8-16
8-17
8-17
8-18
8-18
(Use inhibited area)
H'0080 0FE0
|
8-10
P10 Peripheral Output Select Register
(P10SMOD)
(Use inhibited area)
|
H'0080 0FEA
8-9
(Use inhibited area)
|
H'0080 0786
(Use inhibited area)
See
pages
8-8
(Use inhibited area)
|
H'0080 0760
b15
P22 Direction Register
(P22DIR)
|
H'0080 0740
+1 address
b7 b8
(Use inhibited area)
(Use inhibited area)
TML1 Control Register
(TML1CR)
10-113
(Upper)
10-114
(Use inhibited area)
TML1 Measure 3 Register
(TML1MR2)
H'0080 0FF2
(Lower)
3-22
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (12/21)
Address
+0 address
b0
H'0080 0FF4
+1 address
b7 b8
TML1 Measure 2 Register
(TML1MR2)
H'0080 0FF6
H'0080 0FF8
TML1 Measure 1 Register
(TML1MR1)
H'0080 1000
H'0080 1002
H'0080 1004
H'0080 1006
H'0080 1008
H'0080 100A
H'0080 100C
H'0080 100E
H'0080 1010
H'0080 1012
H'0080 1014
H'0080 1016
H'0080 1018
|
H'0080 1028
H'0080 102A
H'0080 102C
H'0080 102E
H'0080 1030
H'0080 1032
H'0080 1034
H'0080 1036
H'0080 1038
H'0080 103A
H'0080 103C
H'0080 103E
H'0080 1040
H'0080 1042
(Upper)
10-114
(Lower)
TML1 Measure 0 Register
(TML1MR0)
H'0080 0FFE
|
(Upper)
See
pages
10-114
(Lower)
H'0080 0FFA
H'0080 0FFC
b15
(Upper)
10-114
(Lower)
(Use inhibited area)
CAN0 Control Register
(CAN0CNT)
CAN0 Status Register
(CAN0STAT)
CAN0 Frame Format Select Register
(CAN0FFS)
CAN0 Configuration Register
(CAN0CONF)
CAN0 Timestamp Count Register
(CAN0TSTMP)
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
(CAN0REC)
(CAN0TEC)
CAN0 Slot Interrupt Request Status Register
(CAN0SLIST)
(Use inhibited area)
13-15
13-18
13-21
13-22
13-24
13-25
13-29
CAN0 Slot Interrupt Request Enable Register
(CAN0SLIEN)
(Use inhibited area)
13-30
CAN0 Error Interrupt Request Status Register
CAN0 Error Interrupt Request Enable Register
(CAN0ERIST)
(CAN0ERIEN)
CAN0 Baud Rate Prescaler
CAN0 Cause of Error Register
(CAN0BRP)
(CAN0EF)
CAN0 Mode Register
CAN0 DMA Transfer Request Select Register
(CAN0MOD)
(CAN0DMARQ)
(Use inhibited area)
13-31
13-32
13-26
13-45
13-46
13-47
CAN0 Global Mask Register Standard ID 0
CAN0 Global Mask Register Standard ID 1
(C0GMSKS0)
(C0GMSKS1)
CAN0 Global Mask Register Extended ID 0
CAN0 Global Mask Register Extended ID 1
(C0GMSKE0)
(C0GMSKE1)
CAN0 Global Mask Register Extended ID 2
(Use inhibited area)
(C0GMSKE2)
(Use inhibited area)
13-48
13-49
13-50
CAN0 Local Mask Register A Standard ID 0
CAN0 Local Mask Register A Standard ID 1
(C0LMSKAS0)
(C0LMSKAS1)
CAN0 Local Mask Register A Extended ID 0
CAN0 Local Mask Register A Extended ID 1
(C0LMSKAE0)
(C0LMSKAE1)
CAN0 Local Mask Register A Extended ID 2
(Use inhibited area)
(C0LMSKAE2)
(Use inhibited area)
13-48
CAN0 Local Mask Register B Standard ID 0
CAN0 Local Mask Register B Standard ID 1
(C0LMSKBS0)
(C0LMSKBS1)
CAN0 Local Mask Register B Extended ID 0
CAN0 Local Mask Register B Extended ID 1
(C0LMSKBE0)
(C0LMSKBE1)
CAN0 Local Mask Register B Extended ID 2
(Use inhibited area)
(C0LMSKBE2)
(Use inhibited area)
13-48
CAN0 Single Shot Mode Control Register
(CAN0SSMODE)
(Use inhibited area)
13-52
3-23
13-49
13-50
13-49
13-50
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (13/21)
Address
+0 address
b0
H'0080 1044
H'0080 1046
H'0080 1048
H'0080 1050
H'0080 1052
H'0080 1054
H'0080 1056
H'0080 1058
H'0080 105A
H'0080 105C
H'0080 105E
|
H'0080 1100
H'0080 1102
H'0080 1104
H'0080 1106
H'0080 1108
H'0080 110A
H'0080 110C
H'0080 110E
H'0080 1110
H'0080 1112
H'0080 1114
H'0080 1116
H'0080 1118
H'0080 111A
H'0080 111C
H'0080 111E
H'0080 1120
H'0080 1122
H'0080 1124
H'0080 1126
H'0080 1128
H'0080 112A
H'0080 112C
+1address
b7 b8
CAN0 Single-Shot Interrupt Request Status Register
(CAN0SSIST)
(Use inhibited area)
CAN0 Single-Shot Interrupt Request Enable Register
(CAN0SSIEN)
CAN0 Message Slot 0 Control Register
CAN0 Message Slot 1 Control Register
(C0MSL0CNT)
(C0MSL1CNT)
CAN0 Message Slot 2 Control Register
CAN0 Message Slot 3 Control Register
(C0MSL2CNT)
(C0MSL3CNT)
CAN0 Message Slot 4 Control Register
CAN0 Message Slot 5 Control Register
(C0MSL4CNT)
(C0MSL5CNT)
CAN0 Message Slot 6 Control Register
CAN0 Message Slot 7 Control Register
(C0MSL6CNT)
(C0MSL7CNT)
CAN0 Message Slot 8 Control Register
CAN0 Message Slot 9 Control Register
(C0MSL8CNT)
(C0MSL9CNT)
CAN0 Message Slot 10 Control Register
CAN0 Message Slot 11 Control Register
(C0MSL10CNT)
(C0MSL11CNT)
CAN0 Message Slot 12 Control Register
CAN0 Message Slot 13 Control Register
(C0MSL12CNT)
(C0MSL13CNT)
CAN0 Message Slot 14 Control Register
CAN0 Message Slot 15 Control Register
(C0MSL14CNT)
(C0MSL15CNT)
(Use inhibited area)
CAN0 Message Slot 0 Standard ID 0
CAN0 Message Slot 0 Standard ID 1
(C0MSL0SID0)
(C0MSL0SID1)
CAN0 Message Slot 0 Extended ID 0
CAN0 Message Slot 0 Extended ID 1
(C0MSL0EID0)
(C0MSL0EID1)
CAN0 Message Slot 0 Extended ID 2
CAN0 Message Slot 0 Data Length Register
(C0MSL0EID2)
(C0MSL0DLC)
CAN0 Message Slot 0 Data 0
CAN0 Message Slot 0 Data 1
(C0MSL0DT0)
(C0MSL0DT1)
CAN0 Message Slot 0 Data 2
CAN0 Message Slot 0 Data 3
(C0MSL0DT2)
(C0MSL0DT3)
CAN0 Message Slot 0 Data 4
CAN0 Message Slot 0 Data 5
(C0MSL0DT4)
(C0MSL0DT5)
CAN0 Message Slot 0 Data 6
CAN0 Message Slot 0 Data 7
(C0MSL0DT6)
(C0MSL0DT7)
CAN0 Message Slot 0 Timestamp
(C0MSL0TSP)
CAN0 Message Slot 1 Standard ID 0
CAN0 Message Slot 1 Standard ID 1
(C0MSL1SID0)
(C0MSL1SID1)
CAN0 Message Slot 1 Extended ID 0
CAN0 Message Slot 1 Extended ID 1
(C0MSL1EID0)
(C0MSL1EID1)
CAN0 Message Slot 1 Extended ID 2
CAN0 Message Slot 1 Data Length Register
(C0MSL1EID2)
(C0MSL1DLC)
CAN0 Message Slot 1 Data 0
CAN0 Message Slot 1 Data 1
(C0MSL1DT0)
(C0MSL1DT1)
CAN0 Message Slot 1 Data 2
CAN0 Message Slot 1 Data 3
(C0MSL1DT2)
(C0MSL1DT3)
CAN0 Message Slot 1 Data 4
CAN0 Message Slot 1 Data 5
(C0MSL1DT4)
(C0MSL1DT5)
CAN0 Message Slot 1 Data 6
CAN0 Message Slot 1 Data 7
(C0MSL1DT6)
(C0MSL1DT7)
CAN0 Message Slot 1 Timestamp
(C0MSL1TSP)
CAN0 Message Slot 2 Standard ID 0
CAN0 Message Slot 2 Standard ID 1
(C0MSL2SID0)
(C0MSL2SID1)
CAN0 Message Slot 2 Extended ID 0
CAN0 Message Slot 2 Extended ID 1
(C0MSL2EID0)
(C0MSL2EID1)
CAN0 Message Slot 2 Extended ID 2
CAN0 Message Slot 2 Data Length Register
(C0MSL2EID2)
(C0MSL2DLC)
CAN0 Message Slot 2 Data 0
CAN0 Message Slot 2 Data 1
(C0MSL2DT0)
(C0MSL2DT1)
CAN0 Message Slot 2 Data 2
CAN0 Message Slot 2 Data 3
(C0MSL2DT2)
(C0MSL2DT3)
CAN0 Message Slot 2 Data 4
CAN0 Message Slot 2 Data 5
(C0MSL2DT4)
(C0MSL2DT5)
CAN0 Message Slot 2 Data 6
CAN0 Message Slot 2 Data 7
(C0MSL2DT6)
(C0MSL2DT7)
3-24
b15
See
pages
13-33
13-34
13-53
13-53
13-53
13-53
13-53
13-53
13-53
13-53
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (14/21)
Address
+0 address
b0
H'0080 112E
H'0080 1130
H'0080 1132
H'0080 1134
H'0080 1136
H'0080 1138
H'0080 113A
H'0080 113C
H'0080 113E
H'0080 1140
H'0080 1142
H'0080 1144
H'0080 1146
H'0080 1148
H'0080 114A
H'0080 114C
H'0080 114E
H'0080 1150
H'0080 1152
H'0080 1154
H'0080 1156
H'0080 1158
H'0080 115A
H'0080 115C
H'0080 115E
H'0080 1160
H'0080 1162
H'0080 1164
H'0080 1166
H'0080 1168
H'0080 116A
H'0080 116C
H'0080 116E
H'0080 1170
H'0080 1172
+1 address
b7 b8
b15
CAN0 Message Slot 2 Timestamp
(C0MSL2TSP)
CAN0 Message Slot 3 Standard ID 0
CAN0 Message Slot 3 Standard ID 1
(C0MSL3SID0)
(C0MSL3SID1)
CAN0 Message Slot 3 Extended ID 0
CAN0 Message Slot 3 Extended ID 1
(C0MSL3EID0)
(C0MSL3EID1)
CAN0 Message Slot 3 Extended ID 2
CAN0 Message Slot 3 Data Length Register
(C0MSL3EID2)
(C0MSL3DLC)
CAN0 Message Slot 3 Data 0
CAN0 Message Slot 3 Data 1
(C0MSL3DT0)
(C0MSL3DT1)
CAN0 Message Slot 3 Data 2
CAN0 Message Slot 3 Data 3
(C0MSL3DT2)
(C0MSL3DT3)
CAN0 Message Slot 3 Data 4
CAN0 Message Slot 3 Data 5
(C0MSL3DT4)
(C0MSL3DT5)
CAN0 Message Slot 3 Data 6
CAN0 Message Slot 3 Data 7
(C0MSL3DT6)
(C0MSL3DT7)
CAN0 Message Slot 3 Timestamp
(C0MSL3TSP)
CAN0 Message Slot 4 Standard ID 0
CAN0 Message Slot 4 Standard ID 1
(C0MSL4SID0)
(C0MSL4SID1)
CAN0 Message Slot 4 Extended ID 0
CAN0 Message Slot 4 Extended ID 1
(C0MSL4EID0)
(C0MSL4EID1)
CAN0 Message Slot 4 Extended ID 2
CAN0 Message Slot 4 Data Length Register
(C0MSL4EID2)
(C0MSL4DLC)
CAN0 Message Slot 4 Data 0
CAN0 Message Slot 4 Data 1
(C0MSL4DT0)
(C0MSL4DT1)
CAN0 Message Slot 4 Data 2
CAN0 Message Slot 4 Data 3
(C0MSL4DT2)
(C0MSL4DT3)
CAN0 Message Slot 4 Data 4
CAN0 Message Slot 4 Data 5
(C0MSL4DT4)
(C0MSL4DT5)
CAN0 Message Slot 4 Data 6
CAN0 Message Slot 4 Data 7
(C0MSL4DT6)
(C0MSL4DT7)
CAN0 Message Slot 4 Timestamp
(C0MSL4TSP)
CAN0 Message Slot 5 Standard ID 0
CAN0 Message Slot 5 Standard ID 1
(C0MSL5SID0)
(C0MSL5SID1)
CAN0 Message Slot 5 Extended ID 0
CAN0 Message Slot 5 Extended ID 1
(C0MSL5EID0)
(C0MSL5EID1)
CAN0 Message Slot 5 Extended ID 2
CAN0 Message Slot 5 Data Length Register
(C0MSL5EID2)
(C0MSL5DLC)
CAN0 Message Slot 5 Data 0
CAN0 Message Slot 5 Data 1
(C0MSL5DT0)
(C0MSL5DT1)
CAN0 Message Slot 5 Data 2
CAN0 Message Slot 5 Data 3
(C0MSL5DT2)
(C0MSL5DT3)
CAN0 Message Slot 5 Data 4
CAN0 Message Slot 5 Data 5
(C0MSL5DT4)
(C0MSL5DT5)
CAN0 Message Slot 5 Data 6
CAN0 Message Slot 5 Data 7
(C0MSL5DT6)
(C0MSL5DT7)
CAN0 Message Slot 5 Timestamp
(C0MSL5TSP)
CAN0 Message Slot 6 Standard ID 0
CAN0 Message Slot 6 Standard ID 1
(C0MSL6SID0)
(C0MSL6SID1)
CAN0 Message Slot 6 Extended ID 0
CAN0 Message Slot 6 Extended ID 1
(C0MSL6EID0)
(C0MSL6EID1)
CAN0 Message Slot 6 Extended ID 2
CAN0 Message Slot 6 Data Length Register
(C0MSL6EID2)
(C0MSL6DLC)
CAN0 Message Slot 6 Data 0
CAN0 Message Slot 6 Data 1
(C0MSL6DT0)
(C0MSL6DT1)
CAN0 Message Slot 6 Data 2
CAN0 Message Slot 6 Data 3
(C0MSL6DT2)
(C0MSL6DT3)
CAN0 Message Slot 6 Data 4
CAN0 Message Slot 6 Data 5
(C0MSL6DT4)
(C0MSL6DT5)
CAN0 Message Slot 6 Data 6
CAN0 Message Slot 6 Data 7
(C0MSL6DT6)
(C0MSL6DT7)
CAN0 Message Slot 6 Timestamp
(C0MSL6TSP)
CAN0 Message Slot 7 Standard ID 0
CAN0 Message Slot 7 Standard ID 1
(C0MSL7SID0)
(C0MSL7SID1)
CAN0 Message Slot 7 Extended ID 0
CAN0 Message Slot 7 Extended ID 1
(C0MSL7EID0)
(C0MSL7EID1)
3-25
See
pages
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (15/21)
Address
+0 address
b0
H'0080 1174
H'0080 1176
H'0080 1178
H'0080 117A
H'0080 117C
H'0080 117E
H'0080 1180
H'0080 1182
H'0080 1184
H'0080 1186
H'0080 1188
H'0080 118A
H'0080 118C
H'0080 118E
H'0080 1190
H'0080 1192
H'0080 1194
H'0080 1196
H'0080 1198
H'0080 119A
H'0080 119C
H'0080 119E
H'0080 11A0
H'0080 11A2
H'0080 11A4
H'0080 11A6
H'0080 11A8
H'0080 11AA
H'0080 11AC
H'0080 11AE
H'0080 11B0
H'0080 11B2
H'0080 11B4
H'0080 11B6
H'0080 11B8
+1 address
b7 b8
b15
CAN0 Message Slot 7 Extended ID 2
CAN0 Message Slot 7 Data Length Register
(C0MSL7EID2)
(C0MSL7DLC)
CAN0 Message Slot 7 Data 0
CAN0 Message Slot 7 Data 1
(C0MSL7DT0)
(C0MSL7DT1)
CAN0 Message Slot 7 Data 2
CAN0 Message Slot 7 Data 3
(C0MSL7DT2)
(C0MSL7DT3)
CAN0 Message Slot 7 Data 4
CAN0 Message Slot 7 Data 5
(C0MSL7DT4)
(C0MSL7DT5)
CAN0 Message Slot 7 Data 6
CAN0 Message Slot 7 Data 7
(C0MSL7DT6)
(C0MSL7DT7)
CAN0 Message Slot 7 Timestamp
(C0MSL7TSP)
CAN0 Message Slot 8 Standard ID 0
CAN0 Message Slot 8 Standard ID 1
(C0MSL8SID0)
(C0MSL8SID1)
CAN0 Message Slot 8 Extended ID 0
CAN0 Message Slot 8 Extended ID 1
(C0MSL8EID0)
(C0MSL8EID1)
CAN0 Message Slot 8 Extended ID 2
CAN0 Message Slot 8 Data Length Register
(C0MSL8EID2)
(C0MSL8DLC)
CAN0 Message Slot 8 Data 0
CAN0 Message Slot 8 Data 1
(C0MSL8DT0)
(C0MSL8DT1)
CAN0 Message Slot 8 Data 2
CAN0 Message Slot 8 Data 3
(C0MSL8DT2)
(C0MSL8DT3)
CAN0 Message Slot 8 Data 4
CAN0 Message Slot 8 Data 5
(C0MSL8DT4)
(C0MSL8DT5)
CAN0 Message Slot 8 Data 6
CAN0 Message Slot 8 Data 7
(C0MSL8DT6)
(C0MSL8DT7)
CAN0 Message Slot 8 Timestamp
(C0MSL8TSP)
CAN0 Message Slot 9 Standard ID 0
CAN0 Message Slot 9 Standard ID 1
(C0MSL9SID0)
(C0MSL9SID1)
CAN0 Message Slot 9 Extended ID 0
CAN0 Message Slot 9 Extended ID 1
(C0MSL9EID0)
(C0MSL9EID1)
CAN0 Message Slot 9 Extended ID 2
CAN0 Message Slot 9 Data Length Register
(C0MSL9EID2)
(C0MSL9DLC)
CAN0 Message Slot 9 Data 0
CAN0 Message Slot 9 Data 1
(C0MSL9DT0)
(C0MSL9DT1)
CAN0 Message Slot 9 Data 2
CAN0 Message Slot 9 Data 3
(C0MSL9DT2)
(C0MSL9DT3)
CAN0 Message Slot 9 Data 4
CAN0 Message Slot 9 Data 5
(C0MSL9DT4)
(C0MSL9DT5)
CAN0 Message Slot 9 Data 6
CAN0 Message Slot 9 Data 7
(C0MSL9DT6)
(C0MSL9DT7)
CAN0 Message Slot 9 Timestamp
(C0MSL9TSP)
CAN0 Message Slot 10 Standard ID 0
CAN0 Message Slot 10 Standard ID 1
(C0MSL10SID0)
(C0MSL10SID1)
CAN0 Message Slot 10 Extended ID 0
CAN0 Message Slot 10 Extended ID 1
(C0MSL10EID0)
(C0MSL10EID1)
CAN0 Message Slot 10 Extended ID 2
CAN0 Message Slot 10 Data Length Register
(C0MSL10EID2)
(C0MSL10DLC)
CAN0 Message Slot 10 Data 0
CAN0 Message Slot 10 Data 1
(C0MSL10DT0)
(C0MSL10DT1)
CAN0 Message Slot 10 Data 2
CAN0 Message Slot 10 Data 3
(C0MSL10DT2)
(C0MSL10DT3)
CAN0 Message Slot 10 Data 4
CAN0 Message Slot 10 Data 5
(C0MSL10DT4)
(C0MSL10DT5)
CAN0 Message Slot 10 Data 6
CAN0 Message Slot 10 Data 7
(C0MSL10DT6)
(C0MSL10DT7)
CAN0 Message Slot 10 Timestamp
(C0MSL10TSP)
CAN0 Message Slot 11 Standard ID 0
CAN0 Message Slot 11 Standard ID 1
(C0MSL11SID0)
(C0MSL11SID1)
CAN0 Message Slot 11 Extended ID 0
CAN0 Message Slot 11 Extended ID 1
(C0MSL11EID0)
(C0MSL11EID1)
CAN0 Message Slot 11 Extended ID 2
CAN0 Message Slot 11 Data Length Register
(C0MSL11EID2)
(C0MSL11DLC)
CAN0 Message Slot 11 Data 0
CAN0 Message Slot 11 Data 1
(C0MSL11DT0)
(C0MSL11DT1)
CAN0 Message Slot 11 Data 2
CAN0 Message Slot 11 Data 3
(C0MSL11DT2)
(C0MSL11DT3)
3-26
See
pages
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (16/21)
Address
+0 address
b0
H'0080 11BA
H'0080 11BC
H'0080 11BE
H'0080 11C0
H'0080 11C2
H'0080 11C4
H'0080 11C6
H'0080 11C8
H'0080 11CA
H'0080 11CC
H'0080 11CE
H'0080 11D0
H'0080 11D2
H'0080 11D4
H'0080 11D6
H'0080 11D8
H'0080 11DA
H'0080 11DC
H'0080 11DE
H'0080 11E0
H'0080 11E2
H'0080 11E4
H'0080 11E6
H'0080 11E8
H'0080 11EA
H'0080 11EC
H'0080 11EE
H'0080 11F0
H'0080 11F2
H'0080 11F4
H'0080 11F6
H'0080 11F8
H'0080 11FA
H'0080 11FC
+1 address
b7 b8
b15
CAN0 Message Slot 11 Data 4
CAN0 Message Slot 11 Data 5
(C0MSL11DT4)
(C0MSL11DT5)
CAN0 Message Slot 11 Data 6
CAN0 Message Slot 11 Data 7
(C0MSL11DT6)
(C0MSL11DT7)
CAN0 Message Slot 11 Timestamp
(C0MSL11TSP)
CAN0 Message Slot 12 Standard ID 0
CAN0 Message Slot 12 Standard ID 1
(C0MSL12SID0)
(C0MSL12SID1)
CAN0 Message Slot 12 Extended ID 0
CAN0 Message Slot 12 Extended ID 1
(C0MSL12EID0)
(C0MSL12EID1)
CAN0 Message Slot 12 Extended ID 2
CAN0 Message Slot 12 Data Length Register
(C0MSL12EID2)
(C0MSL12DLC)
CAN0 Message Slot 12 Data 0
CAN0 Message Slot 12 Data 1
(C0MSL12DT0)
(C0MSL12DT1)
CAN0 Message Slot 12 Data 2
CAN0 Message Slot 12 Data 3
(C0MSL12DT2)
(C0MSL12DT3)
CAN0 Message Slot 12 Data 4
CAN0 Message Slot 12 Data 5
(C0MSL12DT4)
(C0MSL12DT5)
CAN0 Message Slot 12 Data 6
CAN0 Message Slot 12 Data 7
(C0MSL12DT6)
(C0MSL12DT7)
CAN0 Message Slot 12 Timestamp
(C0MSL12TSP)
CAN0 Message Slot 13 Standard ID 0
CAN0 Message Slot 13 Standard ID 1
(C0MSL13SID0)
(C0MSL13SID1)
CAN0 Message Slot 13 Extended ID 0
CAN0 Message Slot 13 Extended ID 1
(C0MSL13EID0)
(C0MSL13EID1)
CAN0 Message Slot 13 Extended ID 2
CAN0 Message Slot 13 Data Length Register
(C0MSL13EID2)
(C0MSL13DLC)
CAN0 Message Slot 13 Data 0
CAN0 Message Slot 13 Data 1
(C0MSL13DT0)
(C0MSL13DT1)
CAN0 Message Slot 13 Data 2
CAN0 Message Slot 13 Data 3
(C0MSL13DT2)
(C0MSL13DT3)
CAN0 Message Slot 13 Data 4
CAN0 Message Slot 13 Data 5
(C0MSL13DT4)
(C0MSL13DT5)
CAN0 Message Slot 13 Data 6
CAN0 Message Slot 13 Data 7
(C0MSL13DT6)
(C0MSL13DT7)
CAN0 Message Slot 13 Timestamp
(C0MSL13TSP)
CAN0 Message Slot 14 Standard ID 0
CAN0 Message Slot 14 Standard ID 1
(C0MSL14SID0)
(C0MSL14SID1)
CAN0 Message Slot 14 Extended ID 0
CAN0 Message Slot 14 Extended ID 1
(C0MSL14EID0)
(C0MSL14EID1)
CAN0 Message Slot 14 Extended ID 2
CAN0 Message Slot 14 Data Length Register
(C0MSL14EID2)
(C0MSL14DLC)
CAN0 Message Slot 14 Data 0
CAN0 Message Slot 14 Data 1
(C0MSL14DT0)
(C0MSL14DT1)
CAN0 Message Slot 14 Data 2
CAN0 Message Slot 14 Data 3
(C0MSL14DT2)
(C0MSL14DT3)
CAN0 Message Slot 14 Data 4
CAN0 Message Slot 14 Data 5
(C0MSL14DT4)
(C0MSL14DT5)
CAN0 Message Slot 14 Data 6
CAN0 Message Slot 14 Data 7
(C0MSL14DT6)
(C0MSL14DT7)
CAN0 Message Slot 14 Timestamp
(C0MSL14TSP)
CAN0 Message Slot 15 Standard ID 0
CAN0 Message Slot 15 Standard ID 1
(C0MSL15SID0)
(C0MSL15SID1)
CAN0 Message Slot 15 Extended ID 0
CAN0 Message Slot 15 Extended ID 1
(C0MSL15EID0)
(C0MSL15EID1)
CAN0 Message Slot 15 Extended ID 2
CAN0 Message Slot 15 Data Length Register
(C0MSL15EID2)
(C0MSL15DLC)
CAN0 Message Slot 15 Data 0
CAN0 Message Slot 15 Data 1
(C0MSL15DT0)
(C0MSL15DT1)
CAN0 Message Slot 15 Data 2
CAN0 Message Slot 15 Data 3
(C0MSL15DT2)
(C0MSL15DT3)
CAN0 Message Slot 15 Data 4
CAN0 Message Slot 15 Data 5
(C0MSL15DT4)
(C0MSL15DT5)
CAN0 Message Slot 15 Data 6
CAN0 Message Slot 15 Data 7
(C0MSL15DT6)
(C0MSL15DT7)
3-27
See
pages
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (17/21)
Address
+0 address
b0
H'0080 11FE
|
H'0080 1400
H'0080 1402
H'0080 1404
H'0080 1406
H'0080 1408
H'0080 140A
H'0080 140C
H'0080 140E
H'0080 1410
H'0080 1412
H'0080 1414
H'0080 1416
H'0080 1418
|
H'0080 1428
H'0080 142A
H'0080 142C
H'0080 142E
H'0080 1430
H'0080 1432
H'0080 1434
H'0080 1436
H'0080 1438
H'0080 143A
H'0080 143C
H'0080 143E
H'0080 1440
H'0080 1442
H'0080 1444
H'0080 1446
H'0080 1448
|
H'0080 1450
+1 address
b7 b8
CAN0 Message Slot 15 Timestamp
(C0MSL15TSP)
(Use inhibited area)
b15
CAN1 Control Register
(CAN1CNT)
CAN1 Status Register
(CAN1STAT)
CAN1 Frame Format Select Register
(CAN1FFS)
CAN1 Configuration Register
(CAN1CONF)
CAN1 Timestamp Count Register
(CAN1TSTMP)
CAN1 Receive Error Count Register
CAN1 Transmit Error Count Register
(CAN1REC)
(CAN1TEC)
CAN1 Slot Interrupt Request Status Register
(CAN1SLIST)
(Use inhibited area)
See
pages
13-71
13-15
13-18
13-21
13-22
13-24
13-25
13-29
CAN1 Slot Interrupt Request Enable Register
(CAN1SLIEN)
(Use inhibited area)
13-30
CAN1 Error Interrupt Request Status Register
CAN1 Error Interrupt Request Enable Register
(CAN1ERIST)
(CAN1ERIEN)
CAN1 Baud Rate Prescaler
CAN1 Cause of Error Register
(CAN1BRP)
(CAN1EF)
CAN1 Mode Register
(Use inhibited area)
(CAN1MOD)
(Use inhibited area)
13-31
13-32
13-26
13-45
13-46
CAN1 Global Mask Register Standard ID 0
CAN1 Global Mask Register Standard ID 1
(C1GMSKS0)
(C1GMSKS1)
CAN1 Global Mask Register Extended ID 0
CAN1 Global Mask Register Extended ID 1
(C1GMSKE0)
(C1GMSKE1)
CAN1 Global Mask Register Extended ID 2
(Use inhibited area)
(C1GMSKE2)
(Use inhibited area)
13-48
13-49
13-50
CAN1 Local Mask Register A Standard ID 0
CAN1 Local Mask Register A Standard ID 1
(C1LMSKAS0)
(C1LMSKAS1)
CAN1 Local Mask Register A Extended ID 0
CAN1 Local Mask Register A Extended ID 1
(C1LMSKAE0)
(C1LMSKAE1)
CAN1 Local Mask Register A Extended ID 2
(Use inhibited area)
(C1LMSKAE2)
(Use inhibited area)
13-48
CAN1 Local Mask Register B Standard ID 0
CAN1 Local Mask Register B Standard ID 1
(C1LMSKBS0)
(C1LMSKBS1)
CAN1 Local Mask Register B Extended ID 0
CAN1 Local Mask Register B Extended ID 1
(C1LMSKBE0)
(C1LMSKBE1)
CAN1 Local Mask Register B Extended ID 2
(Use inhibited area)
(C1LMSKBE2)
(Use inhibited area)
13-48
CAN1 Single-Shot Mode Control Register
(CAN1SSMODE)
(Use inhibited area)
13-52
CAN1 Single-Shot Interrupt Request Status Register
(CAN1SSIST)
(Use inhibited area)
13-33
CAN1 Single-Shot Interrupt Request Enable Register
(CAN1SSIEN)
(Use inhibited area)
13-34
CAN1 Message Slot 0 Control Register
(C1MSL0CNT)
CAN1 Message Slot 1 Control Register
(C1MSL1CNT)
3-28
13-49
13-50
13-49
13-50
13-53
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (18/21)
Address
+0 address
b0
H'0080 1452
H'0080 1454
H'0080 1456
H'0080 1458
H'0080 145A
H'0080 145C
H'0080 145E
|
H'0080 1500
H'0080 1502
H'0080 1504
H'0080 1506
H'0080 1508
H'0080 150A
H'0080 150C
H'0080 150E
H'0080 1510
H'0080 1512
H'0080 1514
H'0080 1516
H'0080 1518
H'0080 151A
H'0080 151C
H'0080 151E
H'0080 1520
H'0080 1522
H'0080 1524
H'0080 1526
H'0080 1528
H'0080 152A
H'0080 152C
H'0080 152E
H'0080 1530
H'0080 1532
H'0080 1534
+1 address
b7 b8
b15
CAN1 Message Slot 2 Control Register
CAN1 Message Slot 3 Control Register
(C1MSL0CNT)
(C1MSL3CNT)
CAN1 Message Slot 4 Control Register
CAN1 Message Slot 5 Control Register
(C1MSL4CNT)
(C1MSL5CNT)
CAN1 Message Slot 6 Control Register
CAN1 Message Slot 7 Control Register
(C1MSL6CNT)
(C1MSL7CNT)
CAN1 Message Slot 8 Control Register
CAN1 Message Slot 9 Control Register
(C1MSL8CNT)
(C1MSL9CNT)
CAN1 Message Slot 10 Control Register
CAN1 Message Slot 11 Control Register
(C1MSL10CNT)
(C1MSL11CNT)
CAN1 Message Slot 12 Control Register
CAN1 Message Slot 13 Control Register
(C1MSL12CNT)
(C1MSL13CNT)
CAN1 Message Slot 14 Control Register
CAN1 Message Slot 15 Control Register
(C1MSL14CNT)
(C1MSL15CNT)
(Use inhibited area)
CAN1 Message Slot 0 Standard ID 0
CAN1 Message Slot 0 Standard ID 1
(C1MSL0SID0)
(C1MSL0SID1)
CAN1 Message Slot 0 Extended ID 0
CAN1 Message Slot 0 Extended ID 1
(C1MSL0EID0)
(C1MSL0EID1)
CAN1 Message Slot 0 Extended ID 2
CAN1 Message Slot 0 Data Length Register
(C1MSL0EID2)
(C1MSL0DLC)
CAN1 Message Slot 0 Data 0
CAN1 Message Slot 0 Data 1
(C1MSL0DT0)
(C1MSL0DT1)
CAN1 Message Slot 0 Data 2
CAN1 Message Slot 0 Data 3
(C1MSL0DT2)
(C1MSL0DT3)
CAN1 Message Slot 0 Data 4
CAN1 Message Slot 0 Data 5
(C1MSL0DT4)
(C1MSL0DT5)
CAN1 Message Slot 0 Data 6
CAN1 Message Slot 0 Data 7
(C1MSL0DT6)
(C1MSL0DT7)
CAN1 Message Slot 0 Timestamp
(C1MSL0TSP)
CAN1 Message Slot 1 Standard ID 0
CAN1 Message Slot 1 Standard ID 1
(C1MSL1SID0)
(C1MSL1SID1)
CAN1 Message Slot 1 Extended ID 0
CAN1 Message Slot 1 Extended ID 1
(C1MSL1EID0)
(C1MSL1EID1)
CAN1 Message Slot 1 Extended ID 2
CAN1 Message Slot 1 Data Length Register
(C1MSL1EID2)
(C1MSL1DLC)
CAN1 Message Slot 1 Data 0
CAN1 Message Slot 1 Data 1
(C1MSL1DT0)
(C1MSL1DT1)
CAN1 Message Slot 1 Data 2
CAN1 Message Slot 1 Data 3
(C1MSL1DT2)
(C1MSL1DT3)
CAN1 Message Slot 1 Data 4
CAN1 Message Slot 1 Data 5
(C1MSL1DT4)
(C1MSL1DT5)
CAN1 Message Slot 1 Data 6
CAN1 Message Slot 1 Data 7
(C1MSL1DT6)
(C1MSL1DT7)
CAN1 Message Slot 1 Timestamp
(C1MSL1TSP)
CAN1 Message Slot 2 Standard ID 0
CAN1 Message Slot 2 Standard ID 1
(C1MSL2SID0)
(C1MSL2SID1)
CAN1 Message Slot 2 Extended ID 0
CAN1 Message Slot 2 Extended ID 1
(C1MSL2EID0)
(C1MSL2EID1)
CAN1 Message Slot 2 Extended ID 2
CAN1 Message Slot 2 Data Length Register
(C1MSL2EID2)
(C1MSL2DLC)
CAN1 Message Slot 2 Data 0
CAN1 Message Slot 2 Data 1
(C1MSL2DT0)
(C1MSL2DT1)
CAN1 Message Slot 2 Data 2
CAN1 Message Slot 2 Data 3
(C1MSL2DT2)
(C1MSL2DT3)
CAN1 Message Slot 2 Data 4
CAN1 Message Slot 2 Data 5
(C1MSL2DT4)
(C1MSL2DT5)
CAN1 Message Slot 2 Data 6
CAN1 Message Slot 2 Data 7
(C1MSL2DT6)
(C1MSL2DT7)
CAN1 Message Slot 2 Timestamp
(C1MSL2TSP)
CAN1 Message Slot 3 Standard ID 0
CAN1 Message Slot 3 Standard ID 1
(C1MSL3SID0)
(C1MSL3SID1)
CAN1 Message Slot 3 Extended ID 0
CAN1 Message Slot 3 Extended ID 1
(C1MSL3EID0)
(C1MSL3EID1)
CAN1 Message Slot 3 Extended ID 2
CAN1 Message Slot 3 Data Length Register
(C1MSL3EID2)
(C1MSL3DLC)
3-29
See
pages
13-53
13-53
13-53
13-53
13-53
13-53
13-53
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
32182 Group User’s Manual (Rev.1.0)
ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (19/21)
Address
+0 address
b0
H'0080 1536
H'0080 1538
H'0080 153A
H'0080 153C
H'0080 153E
H'0080 1540
H'0080 1542
H'0080 1544
H'0080 1546
H'0080 1548
H'0080 154A
H'0080 154C
H'0080 154E
H'0080 1550
H'0080 1552
H'0080 1554
H'0080 1556
H'0080 1558
H'0080 155A
H'0080 155C
H'0080 155E
H'0080 1560
H'0080 1562
H'0080 1564
H'0080 1566
H'0080 1568
H'0080 156A
H'0080 156C
H'0080 156E
H'0080 1570
H'0080 1572
H'0080 1574
H'0080 1576
H'0080 1578
H'0080 157A
+1 address
b7 b8
b15
CAN1 Message Slot 3 Standard ID 0
CAN1 Message Slot 3 Standard ID 1
(C1MSL3DT0)
(C1MSL3DT1)
CAN1 Message Slot 3 Data 2
CAN1 Message Slot 3 Data 3
(C1MSL3DT2)
(C1MSL3DT3)
CAN1 Message Slot 3 Data 4
CAN1 Message Slot 3 Data 5
(C1MSL3DT4)
(C1MSL3DT5)
CAN1 Message Slot 3 Data 6
CAN1 Message Slot 3 Data 7
(C1MSL3DT6)
(C1MSL3DT7)
CAN1 Message Slot 3 Timestamp
(C1MSL3TSP)
CAN1 Message Slot 4 Standard ID 0
CAN1 Message Slot 4 Standard ID 1
(C1MSL4SID0)
(C1MSL4SID1)
CAN1 Message Slot 4 Extended ID 0
CAN1 Message Slot 4 Extended ID 1
(C1MSL4EID0)
(C1MSL4EID1)
CAN1 Message Slot 4 Extended ID 2
CAN1 Message Slot 4 Data Length Register
(C1MSL4EID2)
(C1MSL4DLC)
CAN1 Message Slot 4 Data 0
CAN1 Message Slot 4 Data 1
(C1MSL4DT0)
(C1MSL4DT1)
CAN1 Message Slot 4 Data 2
CAN1 Message Slot 4 Data 3
(C1MSL4DT2)
(C1MSL4DT3)
CAN1 Message Slot 4 Data 4
CAN1 Message Slot 4 Data 5
(C1MSL4DT4)
(C1MSL4DT5)
CAN1 Message Slot 4 Data 6
CAN1 Message Slot 4 Data 7
(C1MSL4DT6)
(C1MSL4DT7)
CAN1 Message Slot 4 Timestamp
(C1MSL4TSP)
CAN1 Message Slot 5 Standard ID 0
CAN1 Message Slot 5 Standard ID 1
(C1MSL5SID0)
(C1MSL5SID1)
CAN1 Message Slot 5 Extended ID 0
CAN1 Message Slot 5 Extended ID 1
(C1MSL5EID0)
(C1MSL5EID1)
CAN1 Message Slot 5 Extended ID 2
CAN1 Message Slot 5 Data Length Register
(C1MSL5EID2)
(C1MSL5DLC)
CAN1 Message Slot 5 Data 0
CAN1 Message Slot 5 Data 1
(C1MSL5DT0)
(C1MSL5DT1)
CAN1 Message Slot 5 Data 2
CAN1 Message Slot 5 Data 3
(C1MSL5DT2)
(C1MSL5DT3)
CAN1 Message Slot 5 Data 4
CAN1 Message Slot 5 Data 5
(C1MSL5DT4)
(C1MSL5DT5)
CAN1 Message Slot 5 Data 6
CAN1 Message Slot 5 Data 7
(C1MSL5DT6)
(C1MSL5DT7)
CAN1 Message Slot 5 Timestamp
(C1MSL5TSP)
CAN1 Message Slot 6 Standard ID 0
CAN1 Message Slot 6 Standard ID 1
(C1MSL6SID0)
(C1MSL6SID1)
CAN1 Message Slot 6 Extended ID 0
CAN1 Message Slot 6 Extended ID 1
(C1MSL6EID0)
(C1MSL6EID1)
CAN1 Message Slot 6 Extended ID 2
CAN1 Message Slot 6 Data Length Register
(C1MSL6EID2)
(C1MSL6DLC)
CAN1 Message Slot 6 Data 0
CAN1 Message Slot 6 Data 1
(C1MSL6DT0)
(C1MSL6DT1)
CAN1 Message Slot 6 Data 2
CAN1 Message Slot 6 Data 3
(C1MSL6DT2)
(C1MSL6DT3)
CAN1 Message Slot 6 Data 4
CAN1 Message Slot 6 Data 5
(C1MSL6DT4)
(C1MSL6DT5)
CAN1 Message Slot 6 Data 6
CAN1 Message Slot 6 Data 7
(C1MSL6DT6)
(C1MSL6DT7)
CAN1 Message Slot 6 Timestamp
(C1MSL6TSP)
CAN1 Message Slot 7 Standard ID 0
CAN1 Message Slot 7 Standard ID 1
(C1MSL7SID0)
(C1MSL7SID1)
CAN1 Message Slot 7 Extended ID 0
CAN1 Message Slot 7 Extended ID 1
(C1MSL7EID0)
(C1MSL7EID1)
CAN1 Message Slot 7 Extended ID 2
CAN1 Message Slot 7 Data Length Register
(C1MSL7EID2)
(C1MSL7DLC)
CAN1 Message Slot 7 Data 0
CAN1 Message Slot 7 Data 1
(C1MSL7DT0)
(C1MSL7DT1)
CAN1 Message Slot 7 Data 2
CAN1 Message Slot 7 Data 3
(C1MSL7DT2)
(C1MSL7DT3)
CAN1 Message Slot 7 Data 4
CAN1 Message Slot 7 Data 5
(C1MSL7DT4)
(C1MSL7DT5)
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ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (20/21)
Address
+0 address
b0
H'0080 157C
H'0080 157E
H'0080 1580
H'0080 1582
H'0080 1584
H'0080 1586
H'0080 1588
H'0080 158A
H'0080 158C
H'0080 158E
H'0080 1590
H'0080 1592
H'0080 1594
H'0080 1596
H'0080 1598
H'0080 159A
H'0080 159C
H'0080 159E
H'0080 15A0
H'0080 15A2
H'0080 15A4
H'0080 15A6
H'0080 15A8
H'0080 15AA
H'0080 15AC
H'0080 15AE
H'0080 15B0
H'0080 15B2
H'0080 15B4
H'0080 15B6
H'0080 15B8
H'0080 15BA
H'0080 15BC
H'0080 15BE
H'0080 15C0
+1address
b7 b8
b15
CAN1 Message Slot 7 Data 6
CAN1 Message Slot 7 Data 7
(C1MSL7DT6)
(C1MSL7DT7)
CAN1 Message Slot 7 Timestamp
(C1MSL7TSP)
CAN1 Message Slot 8 Standard ID 0
CAN1 Message Slot 8 Standard ID 1
(C1MSL8SID0)
(C1MSL8SID1)
CAN1 Message Slot 8 Extended ID 0
CAN1 Message Slot 8 Extended ID 1
(C1MSL8EID0)
(C1MSL8EID1)
CAN1 Message Slot 8 Extended ID 2
CAN1 Message Slot 8 Data Length Register
(C1MSL8EID2)
(C1MSL8DLC)
CAN1 Message Slot 8 Data 0
CAN1 Message Slot 8 Data 1
(C1MSL8DT0)
(C1MSL8DT1)
CAN1 Message Slot 8 Data 2
CAN1 Message Slot 8 Data 3
(C1MSL8DT2)
(C1MSL8DT3)
CAN1 Message Slot 8 Data 4
CAN1 Message Slot 8 Data 5
(C1MSL8DT4)
(C1MSL8DT5)
CAN1 Message Slot 8 Data 6
CAN1 Message Slot 8 Data 7
(C1MSL8DT6)
(C1MSL8DT7)
CAN1 Message Slot 8 Timestamp
(C1MSL8TSP)
CAN1 Message Slot 9 Standard ID 0
CAN1 Message Slot 9 Standard ID 1
(C1MSL9SID0)
(C1MSL9SID1)
CAN1 Message Slot 9 Extended ID 0
CAN1 Message Slot 9 Extended ID 1
(C1MSL9EID0)
(C1MSL9EID1)
CAN1 Message Slot 9 Extended ID 2
CAN1 Message Slot 9 Data Length Register
(C1MSL9EID2)
(C1MSL9DLC)
CAN1 Message Slot 9 Data 0
CAN1 Message Slot 9 Data 1
(C1MSL9DT0)
(C1MSL9DT1)
CAN1 Message Slot 9 Data 2
CAN1 Message Slot 9 Data 3
(C1MSL9DT2)
(C1MSL9DT3)
CAN1 Message Slot 9 Data 4
CAN1 Message Slot 9 Data 5
(C1MSL9DT4)
(C1MSL9DT5)
CAN1 Message Slot 9 Data 6
CAN1 Message Slot 9 Data 7
(C1MSL9DT6)
(C1MSL9DT7)
CAN1 Message Slot 9 Timestamp
(C1MSL9TSP)
CAN1 Message Slot 10 Standard ID 0
CAN1 Message Slot 10 Standard ID 1
(C1MSL10SID0)
(C1MSL10SID1)
CAN1 Message Slot 10 Extended ID 0
CAN1 Message Slot 10 Extended ID 1
(C1MSL10EID0)
(C1MSL10EID1)
CAN1 Message Slot 10 Extended ID 2
CAN1 Message Slot 10 Data Length Register
(C1MSL10EID2)
(C1MSL10DLC)
CAN1 Message Slot 10 Data 0
CAN1 Message Slot 10 Data 1
(C1MSL10DT0)
(C1MSL10DT1)
CAN1 Message Slot 10 Data 2
CAN1 Message Slot 10 Data 3
(C1MSL10DT2)
(C1MSL10DT3)
CAN1 Message Slot 10 Data 4
CAN1 Message Slot 10 Data 5
(C1MSL10DT4)
(C1MSL10DT5)
CAN1 Message Slot 10 Data 6
CAN1 Message Slot 10 Data 7
(C1MSL10DT6)
(C1MSL10DT7)
CAN1 Message Slot 10 Timestamp
(C1MSL10TSP)
CAN1 Message Slot 11 Standard ID 0
CAN1 Message Slot 11 Standard ID 1
(C1MSL11SID0)
(C1MSL11SID1)
CAN1 Message Slot 11 Extended ID 0
CAN1 Message Slot 11 Extended ID 1
(C1MSL11EID0)
(C1MSL11EID1)
CAN1 Message Slot 11 Extended ID 2
CAN1 Message Slot 11 Data Length Register
(C1MSL11EID2)
(C1MSL11DLC)
CAN1 Message Slot 11 Data 0
CAN1 Message Slot 11 Data 1
(C1MSL11DT0)
(C1MSL11DT1)
CAN1 Message Slot 11 Data 2
CAN1 Message Slot 11 Data 3
(C1MSL11DT2)
(C1MSL11DT3)
CAN1 Message Slot 11 Data 4
CAN1 Message Slot 11 Data 5
(C1MSL11DT4)
(C1MSL11DT5)
CAN1 Message Slot 11 Data 6
CAN1 Message Slot 11 Data 7
(C1MSL11DT6)
(C1MSL11DT7)
CAN1 Message Slot 11 Timestamp
(C1MSL11TSP)
CAN1 Message Slot 12 Standard ID 0
CAN1 Message Slot 12 Standard ID 1
(C1MSL12SID0)
(C1MSL12SID1)
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ADDRESS SPACE
3
3.4 Internal RAM and SFR Areas
SFR Area Register Map (21/21)
Address
+0 address
b0
H'0080 15C2
H'0080 15C4
H'0080 15C6
H'0080 15C8
H'0080 15CA
H'0080 15CC
H'0080 15CE
H'0080 15D0
H'0080 15D2
H'0080 15D4
H'0080 15D6
H'0080 15D8
H'0080 15DA
H'0080 15DC
H'0080 15DE
H'0080 15E0
H'0080 15E2
H'0080 15E4
H'0080 15E6
H'0080 15E8
H'0080 15EA
H'0080 15EC
H'0080 15EE
H'0080 15F0
H'0080 15F2
H'0080 15F4
H'0080 15F6
H'0080 15F8
H'0080 15FA
H'0080 15FC
H'0080 15FE
+1 address
b7 b8
b15
CAN1 Message Slot 12 Extended ID 0
CAN1 Message Slot 12 Extended ID 1
(C1MSL12EID0)
(C1MSL12EID1)
CAN1 Message Slot 12 Extended ID 2
CAN1 Message Slot 12 Data Length Register
(C1MSL12EID2)
(C1MSL12DLC)
CAN1 Message Slot 12 Data 0
CAN1 Message Slot 12 Data 1
(C1MSL12DT0)
(C1MSL12DT1)
CAN1 Message Slot 12 Data 2
CAN1 Message Slot 12 Data 3
(C1MSL12DT2)
(C1MSL12DT3)
CAN1 Message Slot 12 Data 4
CAN1 Message Slot 12 Data 5
(C1MSL12DT4)
(C1MSL12DT5)
CAN1 Message Slot 12 Data 6
CAN1 Message Slot 12 Data 7
(C1MSL12DT6)
(C1MSL12DT7)
CAN1 Message Slot 12 Timestamp
(C1MSL12TSP)
CAN1 Message Slot 13 Standard ID 0
CAN1 Message Slot 13 Standard ID 1
(C1MSL13SID0)
(C1MSL13SID1)
CAN1 Message Slot 13 Extended ID 0
CAN1 Message Slot 13 Extended ID 1
(C1MSL13EID0)
(C1MSL13EID1)
CAN1 Message Slot 13 Extended ID 2
CAN1 Message Slot 13 Data Length Register
(C1MSL13EID2)
(C1MSL13DLC)
CAN1 Message Slot 13 Data 0
CAN1 Message Slot 13 Data 1
(C1MSL13DT0)
(C1MSL13DT1)
CAN1 Message Slot 13 Data 2
CAN1 Message Slot 13 Data 3
(C1MSL13DT2)
(C1MSL13DT3)
CAN1 Message Slot 13 Data 4
CAN1 Message Slot 13 Data 5
(C1MSL13DT4)
(C1MSL13DT5)
CAN1 Message Slot 13 Data 6
CAN1 Message Slot 13 Data 7
(C1MSL13DT6)
(C1MSL13DT7)
CAN1 Message Slot 13 Timestamp
(C1MSL13TSP)
CAN1 Message Slot 14 Standard ID 0
CAN1 Message Slot 14 Standard ID 1
(C1MSL14SID0)
(C1MSL14SID1)
CAN1 Message Slot 14 Extended ID 0
CAN1 Message Slot 14 Extended ID 1
(C1MSL14EID0)
(C1MSL14EID1)
CAN1 Message Slot 14 Extended ID 2
CAN1 Message Slot 14 Data Length Register
(C1MSL14EID2)
(C1MSL14DLC)
CAN1 Message Slot 14 Data 0
CAN1 Message Slot 14 Data 1
(C1MSL14DT0)
(C1MSL14DT1)
CAN1 Message Slot 14 Data 2
CAN1 Message Slot 14 Data 3
(C1MSL14DT2)
(C1MSL14DT3)
CAN1 Message Slot 14 Data 4
CAN1 Message Slot 14 Data 5
(C1MSL14DT4)
(C1MSL14DT5)
CAN1 Message Slot 14 Data 6
CAN1 Message Slot 14 Data 7
(C1MSL14DT6)
(C1MSL14DT7)
CAN1 Message Slot 14 Timestamp
(C1MSL14TSP)
CAN1 Message Slot 15 Standard ID 0
CAN1 Message Slot 15 Standard ID 1
(C1MSL15SID0)
(C1MSL15SID1)
CAN1 Message Slot 15 Extended ID 0
CAN1 Message Slot 15 Extended ID 1
(C1MSL15EID0)
(C1MSL15EID1)
CAN1 Message Slot 15 Extended ID 2
CAN1 Message Slot 15 Data Length Register
(C1MSL15EID2)
(C1MSL15DLC)
CAN1 Message Slot 15 Data 0
CAN1 Message Slot 15 Data 1
(C1MSL15DT0)
(C1MSL15DT1)
CAN1 Message Slot 15 Data 2
CAN1 Message Slot 15 Data 3
(C1MSL15DT2)
(C1MSL15DT3)
CAN1 Message Slot 15 Data 4
CAN1 Message Slot 15 Data 5
(C1MSL15DT4)
(C1MSL15DT5)
CAN1 Message Slot 15 Data 6
CAN1 Message Slot 15 Data 7
(C1MSL15DT6)
(C1MSL15DT7)
CAN1 Message Slot 15 Timestamp
(C1MSL15TSP)
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ADDRESS SPACE
3
3.5 EIT Vector Entry
3.5 EIT Vector Entry
The EIT vector entry is located at the beginning of the internal ROM/extended external areas. The branch instruction for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch
instruction and not the jump address itself that is written here. For details, see Chapter 4, “EIT.”
0
31
H'0000 0000
H'0000 0004
RI (Reset Interrupt)
H'0000 0008
H'0000 000C
H'0000 0010
H'0000 0014
SBI (System Break Interrupt)
H'0000 0018
H'0000 001C
H'0000 0020
H'0000 0024
RIE (Reserved Instruction Exception)
H'0000 0028
H'0000 002C
H'0000 0030
H'0000 0034
AE (Address Exception)
H'0000 0038
H'0000 003C
H'0000 0040
TRAP0
H'0000 0044
TRAP1
H'0000 0048
TRAP2
H'0000 004C
TRAP3
H'0000 0050
TRAP4
H'0000 0054
TRAP5
H'0000 0058
TRAP6
H'0000 005C
TRAP7
H'0000 0060
TRAP8
H'0000 0064
TRAP9
H'0000 0068
TRAP10
H'0000 006C
TRAP11
H'0000 0070
TRAP12
H'0000 0074
TRAP13
H'0000 0078
TRAP14
H'0000 007C
TRAP15
H'0000 0080
EI (External Interrupt) (Note 1)
H'0000 0090
FPE (Floating-Point Exception)
Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000.
Figure 3.5.1 EIT Vector Entry
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ADDRESS SPACE
3
3.6 ICU Vector Table
3.6 ICU Vector Table
The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses
shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal
peripheral I/Os are set. For details, see Chapter 5, “Interrupt Controller.”
ICU Vector Table Memory Map (1/2)
Address
+0 address
b0
+1 address
b7 b8
b15
H'0000 0094
TIN3–6 Input Interrupt Handler Start Address (A0–A15)
H'0000 0096
TIN3–6 Input Interrupt Handler Start Address (A16–A31)
H'0000 0098
TIN20–29 Input Interrupt Handler Start Address (A0–A15)
H'0000 009A
TIN20–29 Input Interrupt Handler Start Address (A16–A31)
H'0000 009C
TIN12–19 Input Interrupt Handler Start Address (A0–A15)
H'0000 009E
TIN12–19 Input Interrupt Handler Start Address (A16–A31)
H'0000 00A0
TIN0–2 Input Interrupt Handler Start Address (A0–A15)
H'0000 00A2
TIN0–2 Input Interrupt Handler Start Address (A16–A31)
H'0000 00A4
(Note 1)
H'0000 00A6
H'0000 00A8
TMS0, 1 Output Interrupt Handler Start Address (A0–A15)
H'0000 00AA
TMS0, 1 Output Interrupt Handler Start Address (A16–A31)
H'0000 00AC
TOP8, 9 Output Interrupt Handler Start Address (A0–A15)
H'0000 00AE
TOP8, 9 Output Interrupt Handler Start Address (A16–A31)
H'0000 00B0
TOP10 Output Interrupt Handler Start Address (A0–A15)
H'0000 00B2
TOP10 Output Interrupt Handler Start Address (A16–A31)
H'0000 00B4
TIO4–7 Output Interrupt Handler Start Address (A0–A15)
H'0000 00B6
TIO4–7 Output Interrupt Handler Start Address (A16–A31)
H'0000 00B8
TIO8, 9 Output Interrupt Handler Start Address (A0–A15)
H'0000 00BA
TIO8, 9 Output Interrupt Handler Start Address (A16–A31)
H'0000 00BC
TOP0–5 Output Interrupt Handler Start Address (A0–A15)
H'0000 00BE
TOP0–5 Output Interrupt Handler Start Address (A16–A31)
H'0000 00C0
TOP6, 7 Output Interrupt Handler Start Address (A0–A15)
H'0000 00C2
TOP6, 7 Output Interrupt Handler Start Address (A16–A31)
H'0000 00C4
TIO0–3 Output Interrupt Handler Start Address (A0–A15)
H'0000 00C6
TIO0–3 Output Interrupt Handler Start Address (A16–A31)
H'0000 00C8
DMA0–4 Interrupt Handler Start Address (A0–A15)
H'0000 00CA
DMA0–4 Interrupt Handler Start Address (A16–A31)
H'0000 00CC
SIO1 Receive Interrupt Handler Start Address (A0–A15)
H'0000 00CE
SIO1 Receive Interrupt Handler Start Address (A16–A31)
H'0000 00D0
SIO1 Transmit Interrupt Handler Start Address (A0–A15)
H'0000 00D2
SIO1 Transmit Interrupt Handler Start Address (A16–A31)
H'0000 00D4
SIO0 Receive Interrupt Handler Start Address (A0–A15)
H'0000 00D6
SIO0 Receive Interrupt Handler Start Address (A16–A31)
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ADDRESS SPACE
3
3.6 ICU Vector Table
ICU Vector Table Memory Map (2/2)
Address
+0 address
+1 address
b0
b7
b8
b15
H'0000 00D8
SIO0 Transmit Interrupt Handler Start Address (A0–A15)
H'0000 00DA
SIO0 Transmit Interrupt Handler Start Address (A16–A31)
H'0000 00DC
A-D0 Conversion Interrupt Handler Start Address (A0–A15)
H'0000 00DE
A-D0 Conversion Interrupt Handler Start Address (A16–A31)
H'0000 00E0
(Note 1)
H'0000 00E2
H'0000 00E4
(Note 1)
H'0000 00E6
H'0000 00E8
DMA5–9 Interrupt Handler Start Address (A0–A15)
H'0000 00EA
DMA5–9 Interrupt Handler Start Address (A16–A31)
H'0000 00EC
SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0–A15)
H'0000 00EE
SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16–A31)
H'0000 00F0
RTD Interrupt Handler Start Address (A0–A15)
H'0000 00F2
RTD Interrupt Handler Start Address (A16–A31)
H'0000 00F4
(Note 1)
H'0000 00F6
H'0000 00F8
(Note 1)
H'0000 00FA
H'0000 00FC
(Note 1)
H'0000 00FE
H'0000 0100
(Note 1)
H'0000 0102
H'0000 0104
(Note 1)
H'0000 0106
H'0000 0108
(Note 1)
H'0000 010A
H'0000 010C
CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0–A15)
H'0000 010E
CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16–A31)
H'0000 0110
CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0–A15)
H'0000 0112
CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16–A31)
Note 1: Valid for the interrupt requests in the 32180. No interrupt requests are generated in the 32182.
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ADDRESS SPACE
3.7 Notes about Address Space
3
3.7 Notes about Address Space
• Virtual flash emulation function
The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000
into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as
the virtual flash emulation function.
This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the flash memory
contents at the addresses specified by the Virtual Flash Bank Register. For details about this function, see
Section 6.6, “Virtual Flash Emulation Function.”
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CHAPTER 4
EIT
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
Outline of EIT
EIT Events
EIT Processing Procedure
EIT Processing Mechanism
Acceptance of EIT Events
Saving and Restoring the PC and PSW
EIT Vector Entry
Exception Processing
Interrupt Processing
Trap Processing
EIT Priority Levels
Example of EIT Processing
Precautions on EIT
EIT
4
4.1 Outline of EIT
4.1 Outline of EIT
If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the
program being executed and execute another program. Events like this one are referred to by a generic name as
EIT (Exception, Interrupt and Trap).
(1) Exception
This is an event related to the context being executed. It is generated by an error or violation during instruction
execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and FloatingPoint Exception (FPE).
(2) Interrupt
This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal
from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI),
System Break Interrupt (SBI) and External Interrupt (EI).
(3) Trap
This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally
generated in a program as in the OS’s system call by the programmer.
EIT
Exception (Exception)
Reserved Instruction Exception (RIE)
Address Exception (AE)
Floating-Point Exception (FPE)
Reset Interrupt (RI)
Interrupt (Interrupt)
System Break Interrupt (SBI)
External Interrupt (EI)
Trap (Trap)
Trap (TRAP)
Figure 4.1.1 Classification of EITs
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EIT
4
4.2 EIT Events
4.2 EIT Events
4.2.1 Exception
(1) Reserved Instruction Exception (RIE)
Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented
instruction) is detected.
(2) Address Exception (AE)
Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions.
(3) Floating-point Exception (FPE)
Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions
specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is
outlined below.
1) Overflow Exception (OVF)
The exception occurs when the absolute value of the operation result exceeds the largest describable
precision in the floating-point format. The following table shows the operation results when an OVF occurs.
Table 4.2.1 Operation Results When an OVF Occurred
Operation Result (Content of the Destination Register)
Rounding Mode
-Infinity
+Infinity
0
Nearest
Sign of the Result
When the OVF EIT processing is
masked (Note 1)
+
+MAX
-
-Infinity
+
+Infinity
-
-MAX
+
+MAX
-
-MAX
+
+Infinity
-
-Infinity
When the OVF EIT processing is
executed (Note 2)
No change
Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0"
Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1"
Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.
• +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF
2) Underflow Exception (UDF)
The exception occurs when the absolute value of the operation result is less than the largest describable
precision in the floating-point format. The following table shows the operation results when a UDF occurs.
Table 4.2.2 Operation Results when a UDF Occurred
Operation Result (Content of the Destination Register)
When UDF EIT processing is masked (Note 1)
When UDF EIT processing is executed (Note 2)
DN = 0: An unimplemented exception occurs
No change
DN = 1: 0 is returned
Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0"
Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1"
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4.2 EIT Events
3) Inexact Exception (IXCT)
The exception occurs when the operation result differs from a result led out with an infinite range of
precision. The following table shows the operation results and the respective conditions in which each
IXCT occurs.
Table 4.2.3 Operation Results when an IXCT Occurred
Operation Result (Content of the Destination Register)
Occurrence Condition
When the IXCT EIT processing for is When the IXCT EIT processing is
masked (Note 1)
executed (Note 2)
Overflow occurs in OVF masked
condition
Reference OVF operation results
No change
Rounding occurs
Rounded value
No change
Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0"
Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1"
4) Zero Division Exception (DIV0)
The exception occurs when a finite nonzero value is divided by zero. The following table shows the
operation results when a DIV0 is occurs.
Table 4.2.4 Operation Results When a DIV0 Occurred
Operation Result (Content of the Destination Register)
Dividend
Nonzero finite value
When the DIV0 EIT processing is
masked (Note 1)
When the DIV0 EIT processing is
executed (Note 2)
+-Infinity (Sign is derived by
exclusive ORing the signs of the
divisor and dividend.)
No change
Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0"
Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1"
Please note that the DIV0 EIT processing does not occur in the following conditions.
Table 4.2.5 Cases in Which No DIV0 Occur
Dividend
Behavior
0
An invalid operation exception occurs
Infinity
No exceptions occur (with the result = "Infinity")
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4.2 EIT Events
5) Invalid Operation Exception (IVLD)
The exception occurs when an invalid operation is executed. The following table shows the operation
results and the respective conditions in which each IVLD occurs.
Table 4.2.6 Operation Results When an IVLD Occurred
Operation Result (Content of the Destination Register)
Occurrence Condition
When the IVLD EIT
When the IVLD EIT processing is masked (Note 1) processing is executed
(Note 2)
Operation for SNaN operand
+Infinity-(+Infinity), -Infinity-(-Infinity)
0 x Infinity
QNaN
0 / 0, Infinity / Infinity
When FTOI Return value w hen pre-conversion signed bit is:
instruction
"0": H’7FFF FFFF
overflow ed
w as executed "1": H’8000 0000
• When NaN or Infinity w as converted When FTOS Return value w hen pre-conversion signed bit is:
"0": H’0000 7FFF
into an integer
instruction
w as executed "1": H’FFFF 8000
When < or > comparison w as performed on NaN
Comparison results (comparison invalid)
• When an integer conversion
No change
Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0"
Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1"
Note: • NaN (Not a Number)
SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the
source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used
as the initial value in a variable. However, SNaNs cannot be generated by hardware.
QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the
source operand in an operation, an IVLD will not occur (excluding comparison and format conversion).
Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without
executing an EIT processing. QNaNs are created by hardware.
6) Unimplemented Exception (UIPL)
The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and
a denormalized number is given as an operation operand. (Note 1)
Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination
register remains unchanged.
Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if
the DN bit (FPSR register bit 23) = "0", an UIPL occurs.
4.2.2 Interrupt
(1) Reset Interrupt (RI)
Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the
highest priority.
For details about the reset interrupt, see Chapter 7, “Reset.”
(2) System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt
processing, control will not return to the program that was being executed when the interrupt occurred.
(3) External Interrupt (EI)
External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The
interrupt controller manages these interrupts by assigning each one of eight priority levels including an
interrupt-disabled state.
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4.2 EIT Events
4.2.3 Trap
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector
addresses are provided corresponding to TRAP instruction operands 0–15.
4.3 EIT Processing Procedure
EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which
they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted,
except for a rest interrupt, is shown below.
EIT request
generated
Program execution restarted
Instruction Instruction Instruction
A
B
C
Program suspended
and EIT request
accepted
Instruction Instruction
C
D
Instruction
processing-canceled
type (RIE, AE)
PC→BPC
PSW→BPSW Hardware preprocessing
(Note 1)
Instruction processing-completed
type (FPE, EI, TRAP)
Hardware postprocessing
(Note 1)
BPSW→PSW
BPC→PC
User-created EIT handler
EIT vector
entry
Branch
instruction
(SBI)
EIT handler except for SBI
BPC, PSW, FPSR
and general-purpose
registers are saved
to the stack
Processing
by handler
SBI
(System Break
Interrupt processing)
General-purpose
registers, PSW, FPSR
and BPC are restored
from the stack
RTE
instruction
Program terminated
or system is reset
Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.
Figure 4.3.1 Outline of the EIT Processing Procedure
When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described
later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for
the EIT handler (not the jump address itself) is written.
In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s
PSW field is transferred to the BPSW field in that register.
Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and
PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the
stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember
that all these registers must be saved to the stack in a program by the user.
When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute
the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed
when the EIT occurred. (This does not apply to the System Break Interrupt, however.)
In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field
is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW
field after executing the RTE instruction are undefined.
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4.4 EIT Processing Mechanism
4.4 EIT Processing Mechanism
The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/
Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW
register). The EIT processing mechanism is shown below.
M32R/ECU
M32R CPU core
RI
RESET#
RI
High
AE, RIE, FPE, TRAP
Priority
SBI#
Internal
peripheral
I/Os
Interrupt
controller
(ICU)
SBI
SBI
EI
EI
Low
IE flag
(PSW)
BPC register
BPSW PSW
PC register
PSW register
Figure 4.4.1 EIT Processing Mechanism
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4.5 Acceptance of EIT Events
4.5 Acceptance of EIT Events
When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT
processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are
accepted are shown below.
Table 4.5.1 Acceptance of EIT Events
EIT Event
Type of Processing
Acceptance Timing
Values Set in BPC Register
Reserved Instruction
Exception (RIE)
Address Exception (AE)
Instruction processingcanceled type
Instruction processingcanceled type
Instruction processingcompleted type
Instruction processingaborted type
Instruction processingcompleted type
Instruction processingcompleted type
Instruction processingcompleted type
During instruction execution
PC value of the instruction that
generated RIE
PC value of the instruction that
generated AE
PC value of the instruction that
generated FPE + 4
Undefined value
Floating-Point Exception
(FPE)
Reset Interrupt (RI)
System Break Interrupt
(SBI)
External Interrupt (EI)
Trap (TRAP)
During instruction execution
Break in instructions
Each machine cycle
Break in instructions
(word boundary only)
Break in instructions
(word boundary only)
Break in instructions
PC value of the next instruction
PC value of the next instruction
PC value of TRAP instruction + 4
4.6 Saving and Restoring the PC and PSW
The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the
RTE instruction.
(1) Hardware preprocessing when an EIT is accepted
[1] Save the PSW register’s SM, IE and C bits in its backup field.
BSM
←
SM
BIE
←
IE
BC
←
C
[2] Update the PSW register’s SM, IE and C bits
SM
←
Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI)
IE
←
Cleared to "0"
C
←
Cleared to "0"
[3] Save the PC register
BPC
←
PC
[4] Set the vector address in the PC register
Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring
control to the user-created EIT handler.
(2) Hardware postprocessing when the RTE instruction is executed
[A] Restore the PSW register’s SM, IE and C bits from its backup field.
SM
←
BSM
IE
←
BIE
C
←
BC
[B] Restore the PC register from the BPC register.
PC
←
BPC
Note: • The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE
instruction are undefined.
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4.6 Saving and Restoring the PC and PSW
[1] Saving the SM, IE and C bits
BSM
←
SM
BIE
←
IE
BC
←
C
[3] Saving the PC
BPC
PC
SM
←
Unchanged or 0
IE
←
0
C
←
0
[A] Restoring the SM, IE and C bits from the
backup field
←
BSM
IE
←
BIE
C
←
BC
PC
[4] Setting the vector address in the PC
[2] Updating the SM, IE and C bits
SM
←
←
Vector address
[B] Restoring the PC from the BPC register
The value stored in the BPC register
after executing the RTE instruction is
undefined.
The values stored in the BSM, BIE
and BC bits after executing the RTE
instruction are undefined.
PSW
BPC
PC
[1]
When EIT is accepted
[3]
[2]
When RTE instruction
is executed
[4]
[A]
[B]
BPSW field
0(MSB)
PSW
7
8
15 16 17
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSM
PSW field
23 24 25
0 0 0 0 0
BIE
BC
31(LSB)
0 0 0 0 0
SM
IE
C
Figure 4.6.1 Saving and Restoring the PC and PSW
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4.7 EIT Vector Entry
4.7 EIT Vector Entry
The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the
EIT vector entry.
Table 4.7.1 EIT Vector Entry
Name
Abbreviation Vector Address
Reset Interrupt
RI
System Break
SM
IE
BPC
H'0000 0000 (Note 1) 0
0
Undefined
SBI
H'0000 0010
0
0
PC of the next instruction
RIE
H'0000 0020
Unchanged 0
PC of the instruction that generated RIE
Interrupt
Reserved Instruction
Exception
Address Exception
AE
H'0000 0030
Unchanged 0
PC of the instruction that generated AE
Trap
TRAP0
H'0000 0040
Unchanged 0
PC of TRAP instruction + 4
TRAP1
H'0000 0044
Unchanged 0
PC of TRAP instruction + 4
TRAP2
H'0000 0048
Unchanged 0
PC of TRAP instruction + 4
TRAP3
H'0000 004C
Unchanged 0
PC of TRAP instruction + 4
TRAP4
H'0000 0050
Unchanged 0
PC of TRAP instruction + 4
TRAP5
H'0000 0054
Unchanged 0
PC of TRAP instruction + 4
TRAP6
H'0000 0058
Unchanged 0
PC of TRAP instruction + 4
TRAP7
H'0000 005C
Unchanged 0
PC of TRAP instruction + 4
TRAP8
H'0000 0060
Unchanged 0
PC of TRAP instruction + 4
TRAP9
H'0000 0064
Unchanged 0
PC of TRAP instruction + 4
TRAP10
H'0000 0068
Unchanged 0
PC of TRAP instruction + 4
TRAP11
H'0000 006C
Unchanged 0
PC of TRAP instruction + 4
TRAP12
H'0000 0070
Unchanged 0
PC of TRAP instruction + 4
TRAP13
H'0000 0074
Unchanged 0
PC of TRAP instruction + 4
TRAP14
H'0000 0078
Unchanged 0
PC of TRAP instruction + 4
TRAP15
H'0000 007C
Unchanged 0
PC of TRAP instruction + 4
External Interrupt
EI
H'0000 0080 (Note 2) 0
Floating-Point Exception
FPE
H'0000 0090
0
Unchanged 0
PC of the next instruction
PC of the instruction that generated FPE + 4
Note 1: During boot mode, the CPU starts executing the boot program after reset. For details, see Section 6.5,
“Programming the Internal Flash Memory.”
Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080
4000). For details, see Section 6.5, “Programming the Internal Flash Memory.”
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4.8 Exception Processing
4.8 Exception Processing
4.8.1 Reserved Instruction Exception (RIE)
[Occurrence Conditions]
Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is
detected. Instruction check is performed on the op-code part of the instruction.
When a reserved instruction exception occurs, the instruction that generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved
instruction exception that is accepted.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
BIE ←
IE
BC ←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM ←
Unchanged
IE
←
0
C
←
0
(3) Saving the PC
The PC value of the instruction that generated the reserved instruction exception is set in the BPC register.
For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4
is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at
address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates
whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC
register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT handler
has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned
to the PC.)
+0
+1
+2
+3
+0
Address
H'04
H'08
+2
+3
Address
H'00
Return
address
+1
H'00
Return
address
RIE occurred
H'0C
H'04
H'08
RIE occurred
H'0C
BPC
BPC
H'04
H'06
Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE)
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4.8 Exception Processing
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.
Also, save the accumulator and FPSR register as necessary.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time,
the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure
4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruction exception suggests that the system has some fatal fault already existing in it. In such a case, therefore,
do not return from the reserved instruction exception handler to the program that was being executed when
the exception occurred.
4.8.2 Address Exception (AE)
[Occurrence Conditions]
Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions. The following lists the combination of instructions and accessed addresses that may cause
address exceptions to occur.
• Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’
• Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’
When an address exception occurs, memory access by the instruction that generated the exception is not
performed. If an external interrupt is requested at the same time an address exception is detected, it is the
address exception that is accepted.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
BIE ←
IE
BC ←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM ←
Unchanged
IE
←
0
C
←
0
(3) Saving the PC
The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC
register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set
in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that
generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on
a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT handler
has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned
to the PC.)
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4.8 Exception Processing
+0
+1
+2
+3
+0
Address
H'04
H'08
+2
+3
Address
H'00
Return
address
+1
H'00
Return
address
AE occurred
H'0C
H'04
H'08
AE occurred
H'0C
BPC
BPC
H'04
H'06
Figure 4.8.2 Example of a Return Address for Address Exception (AE)
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.
Also, save the accumulator and FPSR register as necessary.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time,
the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure
4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests
that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the
address exception handler to the program that was being executed when the exception occurred.
4.8.3 Floating-Point Exception (FPE)
[Occurrence Conditions]
Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions
specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected.
Note, however, that the EIT processing described below is executed only when the exception that occurred
is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented exception.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
BIE ←
IE
BC ←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM ←
Unchanged
IE
←
0
C
←
0
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4.8 Exception Processing
(3) Saving the PC
The PC value of the instruction that generated the FPE exception + 4 is set in the BPC register.
Because all of the instructions that generate an FPE exception are 32 bits long, the address to which the
RTE returns is always the instruction next to the one that generated the FPE exception.
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0090 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0090 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC, PSW and FPSR registers and the necessary general-purpose registers to the
stack.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed.
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4.9 Interrupt Processing
4.9 Interrupt Processing
4.9.1 Reset Interrupt (RI)
[Occurrence Conditions]
A reset interrupt is accepted in machine cycle by pulling the RESET# input signal low. The reset interrupt is
assigned the highest priority among all EITs.
[EIT Processing]
(1) Initializing SM, IE and C bits
The PSW register’s SM, IE and C bits are initialized as shown below.
SM ←
0
IE
←
0
C
←
0
For the reset interrupt, the values of BSM, BIE and BC bits are undefined.
(2) Branching to the EIT vector entry
The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode,
the CPU jumps to the boot program. For details, see Section 6.5, “Programming the Internal Flash Memory.”
(3) Jumping from the EIT vector entry to the user program
The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In
the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of
the user program.
4.9.2 System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW
register IE bit.
Therefore, the system break interrupt can only be used when the system has some fatal event already existing in
it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI
handler, control will not return to the program that was being executed when the system break interrupt occurred.
[Occurrence Conditions]
A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot
be masked by the PSW register IE bit.)
In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that
starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately
after branching.) Note also that because of the instruction processing-completed type, a system break
interrupt is accepted after the instruction is completed.
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4.9 Interrupt Processing
Order in which instructions are executed
Address 1000
Address 1002
Address 1004
Address 1008
32-bit instruction
16-bit instruction 16-bit instruction
×
Interrupt may
be accepted
Interrupt cannot Interrupt may
be accepted
be accepted
Interrupt may
be accepted
Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
BIE ←
IE
BC ←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM ←
0
IE
←
0
C
←
0
(3) Saving the PC
The address of the next instruction (always on word boundary) following one in which the interrupt was
detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next
instruction is one that exists at the jump address.
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector
entry to jump to the start address of the user-created handler.
The system break interrupt can only be used when the system has some fatal event already existing in it
when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the
SBI handler, control will not return to the program that was being executed when the system break interrupt
occurred.
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4
4.9 Interrupt Processing
4.9.3 External Interrupt (EI)
An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal
interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority
levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each
section in which the relevant internal peripheral I/O is described.
[Occurrence Conditions]
External interrupts are managed based on interrupt requests from each internal peripheral I/O by the
microcomputer’s internal interrupt controller, and are sent to the CPU via the interrupt controller. The CPU checks
these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is
detected and the PSW register IE flag = "1", accepts it as an external interrupt.
In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from
a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.)
Order in which instructions are executed
Address 1000
Address 1002
Address 1004
Address 1008
32-bit instruction
16-bit instruction 16-bit instruction
×
Interrupt may
be accepted
Interrupt cannot
be accepted
Interrupt may
be accepted
Interrupt may
be accepted
Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
BIE ←
IE
BC ←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM ←
0
IE
←
0
C
←
0
(3) Saving the PC
The content of the PC register (always on word boundary) is saved to the BPC register.
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0080 in the user space. However, when operating in flash E/W enable
mode, the CPU goes to the beginning of the internal RAM (address H’0080 4000). (For details, see Section 6.5,
“Programming the Internal Flash Memory.”) This is the last operation performed in hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0080 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.
Also, save the accumulator and FPSR register as necessary.
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4
4.9 Interrupt Processing
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed.
4.10 Trap Processing
4.10.1 Trap
[Occurrence Conditions]
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are
generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector
entries are provided.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
BIE ←
IE
BC ←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM ←
Unchanged
IE
←
0
C
←
0
(3) Saving the PC
When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For
example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register.
Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register. The
value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC
register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT
handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to ‘00’
when returned to the PC.)
+0
+1
+2
+3
+0
Address
Return
address
+1
+2
+3
Address
H'00
H'04 TRAP instruction
H'08
H'00
Return
address
H'0C
H'04
H'08
TRAP instruction
H'0C
BPC
BPC
H'08
H'0A
Figure 4.10.1 Example of a Return Address for Trap (TRAP)
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4.10 Trap Processing
(4) Branching to the EIT vector entry
The CPU branches to the addresses H’0000 0040–H’0000 007C in the user space. This is the last operation
performed in hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H’0000 007C of
the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the usercreated EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to
the stack. Also, save the accumulator and FPSR register as necessary.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from
the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing
is automatically performed. At this time, the CPU restarts from the next word-boundary instruction including
the instruction that generates a trap (see Figure 4.10.1).
4.11 EIT Priority Levels
The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with
the highest priority is accepted first.
Table 4.11.1 Priority of EIT Events and How Returned from EIT
Priority
EIT Event
Type of Processing
Values Set in BPC Register
1 (Highest) Reset Interrupt (RI)
Instruction processing-aborted type
Undefined
2
Address Exception (AE)
Instruction processing-canceled type
PC of the instruction that
Reserved Instruction
Instruction processing-canceled type
generated AE
Exception (RIE)
Floating-Point Exception
generated RIE
Instruction processing-completed type
(FPE)
3
PC of the instruction that
PC of the instruction that
generated FPE + 4
Trap (TRAP)
Instruction processing-completed type
TRAP instruction + 4
System Break Interrupt
Instruction processing-completed type
PC of the next instruction
Instruction processing-completed type
PC of the next instruction
(SBI)
4
External Interrupt (EI)
Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the
microcomputer’s internal interrupt controller. For details, see Chapter 5, “Interrupt Controller.”
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4
4.12 Example of EIT Processing
4.12 Example of EIT Processing
(1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly
IE = 1
BPC register = Return address A
IE = 0
RIE, AE, FPE, SBI, EI or TRAP
occurs singly
If IE = 0, no events but reset and
SBI are accepted.
Return address A:
IE = 1
RTE instruction
: EIT handler
Figure 4.12.1 Processing of Events When RIE, AE, FPE, SBI, EI or TRAP Occurs Singly
(2) When RIE, AE, FPE or TRAP and EI occur simultaneously
RIE, AE, FPE or TRAP is accepted first.
BPC register = Return address A
IE = 1
IE = 0
RIE, AE, FPE or TRAP and EI
occur simultaneously
Return address A:
RTE instruction
IE = 1
IE = 0
IE = 1
EI is accepted next.
BPC register = Return address A
RTE instruction
: EIT handler
Figure 4.12.2 Processing of Events When RIE, AE, FPE or TRAP and EI Occur Simultaneously
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4
4.12 Example of EIT Processing
EIT vector entry
BRA instruction
(Other than SBI)
(SBI)
EIT handler
PC→BPC
Hardware
PSW→BPSW
preprocessing
(Note 1)
Save BPC to the stack
Save PSW to the stack
System Break Interrupt
(SBI) processing
Program being
executed
Save general-purpose
registers to the stack
EIT event
occurs
Processing by
EIT handler
Program terminated
or system reset
Restore general-purpose
registers from the stack
(Note 1)
Hardware
BPSW→PSW
postprocessing
BPC→PC
Restore PSW from the stack
Restore BPC from the stack
RTE
Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.
Figure 4.12.3 Example of EIT Processing
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4.13 Precautions on EIT
4.13 Precautions on EIT
The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register
update” addressing mode (following three) generates an address exception when it is executed, the values of the
registers to be automatically updated (Rsrc and Rsrc2) become undefined.
Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when
used in other addressing modes.
• Applicable instructions
LD
Rdest, @Rsrc+
ST
Rsrc1, @-Rsrc2
ST
Rsrc1, @+Rsrc2
If the above case applies, consider the fact that the register values become undefined when you design the processing
to be performed after executing said instructions. (If an address exception occurs, it means that the system has some
fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned
from the address exception handler to the program that was being executed when the exception occurred.)
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CHAPTER 5
INTERRUPT CONTROLLER (ICU)
5.1
5.2
5.3
5.4
5.5
5.6
Outline of the Interrupt Controller
ICU Related Registers
Interrupt Request Sources in Internal
Peripheral I/O
ICU Vector Table
Description of Interrupt Operation
Description of System Break Interrupt (SBI)
Operation
INTERRUPT CONTROLLER (ICU)
5
5.1 Outline of the Interrupt Controller
5.1 Outline of the Interrupt Controller
The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break
interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external
interrupts (EI).
The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels
including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the
same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request
generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for
internal peripheral I/Os.
On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI#
signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault
condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register
IE bit status. After processing of an SBI, shut down or reset the system without returning to the program that was
being executed when the interrupt occurred.
Specifications of the Interrupt Controller are outlined below.
Table 5.1.1 Outline of the Interrupt Controller (ICU)
Item
Specification
Interrupt request source
Maskable interrupt requests from internal peripheral I/Os: 23 sources (Note 1)
System break interrupt request: 1 source (input from SBI# pin)
Priority management
8 priority levels including an interrupt-disabled state
(However, interrupts with the same priority level have their priorities resolved by fixed
hardware priority.)
Note 1: There are actually a total of 123 interrupt request resources when counted individually, which are grouped into 23
interrupt request resources.
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INTERRUPT CONTROLLER (ICU)
5
5.1 Outline of the Interrupt Controller
Interrupt Controller
System Break Interrupt (SBI)
request generated
(nonmaskable)
SBI Control Register
(SBICR)
SBIREQ
SBI
SBI#
To the CPU core
Peripheral circuits
Edge
Interrupt request
Edge
IREQ
IREQ
IREQ
IREQ
Interrupt
control circuit
Level
IREQ
Interrupt
control circuit
Level
Interrupt
control circuit
Level
IREQ
ILEVEL
Priority resolved by fixed hardware priority
Edge
Interrupt request
Priority resolved by interrupt priority levels set
Interrupt request
External Interrupt (EI)
request generated
(maskable)
Interrupt Vector Register
(IVECT)
EI
IMASK
comparison
To the CPU core
NEW_IMASK
Interrupt Request Mask
Register (IMASK)
Interrupt Control Register
Figure 5.1.1 Block Diagram of the Interrupt Controller
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INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
5.2 ICU Related Registers
The diagram below shows a register map associated with the Interrupt Controller (ICU).
ICU Related Register Map
Address
+0 address
b0
H'0080 0000
H'0080 0002
H'0080 0004
H'0080 0006
Interrupt Request Mask Register
(IMASK)
SBI Control Register
(SBICR)
|
H'0080 0060
|
H'0080 0066
H'0080 0068
H'0080 006A
H'0080 006C
H'0080 006E
H'0080 0070
H'0080 0072
H'0080 0074
H'0080 0076
H'0080 0078
H'0080 007A
H'0080 007C
H'0080 007E
+1 address
b7 b8
Interrupt Vector Register
(IVECT)
(Use inhibited area)
See pages
b15
5-5
(Use inhibited area)
5-6
(Use inhibited area)
5-7
(Use inhibited area)
5-8
RTD Interrupt Control Register
(IRTDCR)
DMA5–9 Interrupt Control Register
(IDMA59CR)
5-8
(Use inhibited area)
CAN0 Transmit/Receive & Error Interrupt Control Register
(ICAN0CR)
(Use inhibited area)
(Use inhibited area)
SIO2,3 Transmit/Receive Interrupt Control Register
(ISIO23CR)
(Use inhibited area)
A-D0 Conversion Interrupt Control Register
(IAD0CCR)
SIO0 Receive Interrupt Control Register
(ISIO0RXCR)
SIO1 Receive Interrupt Control Register
(ISIO1RXCR)
TIO0–3 Output Interrupt Control Register
(ITIO03CR)
TOP0–5 Output Interrupt Control Register
(ITOP05CR)
TIO4–7 Output Interrupt Control Register
(ITIO47CR)
TOP8,9 Output Interrupt Control Register
(ITOP89CR)
(Use inhibited area)
SIO0 Transmit Interrupt Control Register
(ISIO0TXCR)
SIO1 Transmit Interrupt Control Register
(ISIO1TXCR)
DMA0–4 Interrupt Control Register
(IDMA04CR)
TOP6,7 Output Interrupt Control Register
(ITOP67CR)
TIO8,9 Output Interrupt Control Register
(ITIO89CR)
TOP10 Output Interrupt Control Register
(ITOP10CR)
TMS0,1 Output Interrupt Control Register
(ITMS01CR)
TIN0–2 Input Interrupt Control Register
(ITIN02CR)
TIN20–29 Input Interrupt Control Register
(ITIN2029CR)
CAN1 Transmit/Receive & Error Interrupt Control Register
(ICAN1CR)
TIN12–19 Input Interrupt Control Register
(ITIN1219CR)
TIN3–6 Input Interrupt Control Register
(ITIN36CR)
5-4
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
5-8
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INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
5.2.1 Interrupt Vector Register
Interrupt Vector Register (IVECT)
b0
1
2
3
4
<Address: H’0080 0000>
5
6
7
8
9
10
11
12
13
14
?
?
?
?
?
?
?
b15
IVECT
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0-15
IVECT
When an interrupt request is accepted, the 16-low-order
R
N
16 low-order bits of ICU vector table address
bits of the ICU vector table address for the accepted
interrupt request source are stored in this register.
Note: • This register must always be accessed in halfwords (2 bytes). (This is a read-only register.)
The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order
bits of the ICU vector table address for the accepted interrupt request source.
Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 0113) must have
set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is
accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are
stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruction
to get the ICU vector table address.
When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware.
(1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK register as
a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source
are masked.)
(2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recognized
interrupt request sources).
(3) The interrupt request (EI) to the CPU core is deasserted.
(4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution).
Notes: • Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are disabled
(PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask
Register (IMASK) first before reading the IVECT register.
• To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register
(IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. (The
ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler
Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, therefore, does not require adding a dummy access.)
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INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
5.2.2 Interrupt Request Mask Register
Interrupt Request Mask Register (IMASK)
b0
1
2
3
4
5
<Address: H’0080 0004>
6
b7
IMASK
0
0
0
0
0
1
1
1
<After reset: H’07>
b
Bit Name
0–4
No function assigned. Fix to "0"
5–7
IMASK
Interrupt request mask bit
Function
R
W
0
0
000: Disable maskable interrupts
001: Accept interrupts with priority level 0
010: Accept interrupts with priority levels 0–1
011: Accept interrupts with priority levels 0–2
100: Accept interrupts with priority levels 0–3
101: Accept interrupts with priority levels 0–4
110: Accept interrupts with priority levels 0–5
111: Accept interrupts with priority levels 0–6
R
W
The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt
request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been
set for each interrupt request source.
When the Interrupt Vector Register (IVECT) described above is read, the interrupt priority level of the accepted
interrupt request source is set in this IMASK register as a new mask value.
When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in
hardware.
(1) The interrupt request (EI) to the CPU core is deasserted.
(2) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution).
Notes: • Do not write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts
are disabled (PSW register IE bit = "0").
• To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask
Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts.
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INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
5.2.3 SBI (System Break Interrupt) Control Register
SBI (System Break Interrupt) Control Register (SBICR)
b0
1
2
3
4
5
6
<Address: H’0080 0006>
b7
SBIREQ
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0–6
7
No function assigned. Fix to "0"
SBIREQ
SBI request bit
0: SBI not requested
1: SBI requested
R
W
0
0
R(Note 1)
Note 1: This bit can only be cleared (see below)
The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin.
When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt
(SBI) request is generated to the CPU.
This bit cannot be set to "1" in software, it can only be cleared.
To clear this bit to "0", follow the procedure described below.
1. Write "1" to the SBI request bit.
2. Write "0" to the SBI request bit.
Note: • Unless this bit is set to "1", do not perform the above clearing operation.
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INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
5.2.4 Interrupt Control Registers
CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR)
RTD Interrupt Control Register (IRTDCR)
SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR)
DMA5–9 Interrupt Control Register (IDMA59CR)
A-D0 Conversion Interrupt Control Register (IAD0CCR)
SIO0 Transmit Interrupt Control Register (ISIO0TXCR)
SIO0 Receive Interrupt Control Register (ISIO0RXCR)
SIO1 Transmit Interrupt Control Register (ISIO1TXCR)
SIO1 Receive Interrupt Control Register (ISIO1RXCR)
DMA0–4 Interrupt Control Register (IDMA04CR)
TIO0–3 Output Interrupt Control Register (ITIO03CR)
TOP6,7 Output Interrupt Control Register (ITOP67CR)
TOP0–5 Output Interrupt Control Register (ITOP05CR)
TIO8,9 Output Interrupt Control Register (ITIO89CR)
TIO4–7 Output Interrupt Control Register (ITIO47CR)
TOP10 Output Interrupt Control Register (ITOP10CR)
TOP8,9 Output Interrupt Control Register (ITOP89CR)
TMS0,1 Output Interrupt Control Register (ITMS01CR)
TIN0–2 Input Interrupt Control Register (ITIN02CR)
TIN12–19 Input Interrupt Control Register (ITIN1219CR)
TIN20–29 Input Interrupt Control Register (ITIN2029CR)
TIN3–6 Input Interrupt Control Register (ITIN36CR)
CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR)
b0
(b8
1
9
2
10
0
0
0
3
11
4
12
5
13
0
1
IREQ
0
6
14
<Address: H’0080 0060>
<Address: H’0080 0067>
<Address: H’0080 0068>
<Address: H’0080 0069>
<Address: H’0080 006C>
<Address: H’0080 006D>
<Address: H’0080 006E>
<Address: H’0080 006F>
<Address: H’0080 0070>
<Address: H’0080 0071>
<Address: H’0080 0072>
<Address: H’0080 0073>
<Address: H’0080 0074>
<Address: H’0080 0075>
<Address: H’0080 0076>
<Address: H’0080 0077>
<Address: H’0080 0078>
<Address: H’0080 0079>
<Address: H’0080 007B>
<Address: H’0080 007C>
<Address: H’0080 007D>
<Address: H’0080 007E>
<Address: H’0080 007F>
b7
b15)
ILEVEL
1
1
<After reset: H’07>
b
Bit Name
0–2
(8–10)
No function assigned. Fix to "0"
3
(11)
IREQ
Interrupt request bit
4
(12)
No function assigned. Fix to "0"
5–7
(13–15)
ILEVEL
Interrupt priority level bits
Function
R
W
0
0
<When edge recognized>
At read
0: Interrupt not requested
1: Interrupt requested
At write
0: Clear interrupt request
1: Generate interrupt request
R
W
<When level-recognized>
At read
0: Interrupt not requested
1: Interrupt requested
R
0
0
0
R
W
000:
001:
010:
011:
100:
101:
110:
111:
5-8
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
priority
priority
priority
priority
priority
priority
priority
priority
level 0
level 1
level 2
level 3
level 4
level 5
level 6
level 7 (interrupt disabled)
32182 Group User’s Manual (Rev.1.0)
INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
(1) IREQ (Interrupt Request) bit (Bit 3 or 11)
When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1".
This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for
level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt request generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not
cleared in the case of level-recognized interrupt request).
If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in
software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the
same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority.
Note: • External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External
Interrupt (EI) to the CPU core can only be deasserted by the following operation:
(1) Reset
(2) IVECT register read
(3) Write to the IMASK register
Interrupt request from
each internal peripheral I/O
Data bus
IREQ Set
Bit 3 or 11
Set/clear
F/F
Interrupt enabled
Reset
IVECT read
IMASK write
Clear
Bits 5-7 or bits 13-15
3
ILEVEL
(levels 0-7)
Interrupt priority
resolving circuit
Set
F/F
EI
To the CPU core
Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)
Interrupt request from each
group internal peripheral I/O
Group interrupt
Read
Data bus
b3, b11
Read-only circuit
IREQ
Interrupt enabled
Reset
IVECT read
IMASK write
Clear
b5-b7, b13-b15 3
ILEVEL
(levels 0-7)
Interrupt priority
resolving circuit
Set
F/F
EI
To the CPU core
Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type)
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INTERRUPT CONTROLLER (ICU)
5
5.2 ICU Related Registers
(2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15)
These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’
to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O.
When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt
sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether
to forward an EI request to the CPU or keep the interrupt request pending.
The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts
are accepted.
Table 5.2.1 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set
IMASK values at which interrupts are accepted
0 (ILEVEL = "000")
Accepted when IMASK is 1–7
1 (ILEVEL = "001")
Accepted when IMASK is 2–7
2 (ILEVEL = "010")
Accepted when IMASK is 3–7
3 (ILEVEL = "011")
Accepted when IMASK is 4–7
4 (ILEVEL = "100")
Accepted when IMASK is 5–7
5 (ILEVEL = "101")
Accepted when IMASK is 6–7
6 (ILEVEL = "110")
Accepted when IMASK is 7
7 (ILEVEL = "111")
Not accepted (interrupts disabled)
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INTERRUPT CONTROLLER (ICU)
5
5.3 Interrupt Request Sources in Internal Peripheral I/O
5.3 Interrupt Request Sources in Internal Peripheral I/O
The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O,
A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal
peripheral I/O is described.
Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O
Interrupt Request Sources
Contents
TIN3–6 input interrupt request
TIN20–29 input interrupt request
TIN12–19 input interrupt request
TIN0–2 input interrupt request
TMS0,1 output interrupt request
TOP8,9 output interrupt request
TOP10 output interrupt request
TIO4–7 output interrupt request
TIO8,9 output interrupt request
TOP0–5 output interrupt request
TOP6,7 output interrupt request
TIO0–3 output interrupt request
DMA0-4 interrupt request
SIO1 receive interrupt request
SIO1 transmit interrupt request
TIN3 input
TIN20–TIN23 inputs
TIN16–TIN19 inputs
TIN0 input
TMS0, TMS1 output
TOP8, TOP9 output
TOP10 output
TIO4–TIO7 outputs
TIO8, TIO9 outputs
TOP0–TOP5 outputs
TOP6–TOP7 outputs
TIO0–TIO3 outputs
DMA0–4 transfer completed
SIO1 reception-completed or receive error interrupt
SIO1 transmission-completed or transmit buffer empty
interrupt
SIO0 receive interrupt request
SIO0 reception-completed or receive error interrupt
SIO0 transmit interrupt request
SIO0 transmission-completed or transmit buffer empty
interrupt
A-D0 conversion interrupt request
A-D0 converter’s scan mode one-shot operation,
single mode or comparate mode completed
DMA5–9 interrupt request
DMA5–9 transfer completed
SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt,
request
transmission-completed or transmit buffer empty interrupt
RTD interrupt request
RTD interrupt generation command
CAN0 transmit/receive & error
CAN0 transmission or reception completed, CAN0 error
interrupt request
passive, CAN0 error bus-off, CAN0 bus error, single shot
CAN1 transmit/receive & error
CAN1 transmission or reception completed, CAN1 error
interrupt request
Number of
Input Sources
ICU Type of Input
Source ( Note 1)
1
4
4
1
2
2
1
4
2
6
2
4
5
1
1
Level-recognized
Level-recognized
Level-recognized
Level-recognized
Level-recognized
Level-recognized
Edge-recognized
Level-recognized
Level-recognized
Level-recognized
Level-recognized
Level-recognized
Level-recognized
Edge-recognized
Edge-recognized
1
1
Edge-recognized
Edge-recognized
1
Edge-recognized
5
4
Level-recognized
Level-recognized
1
35
Edge-recognized
Level-recognized
35
Level-recognized
passive, CAN1 error bus-off, CAN1 bus error, single shot
Note 1: ICU type of input source
• Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.
• Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For
this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.
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INTERRUPT CONTROLLER (ICU)
5
5.4 ICU Vector Table
5.4 ICU Vector Table
The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The
32-source interrupt requests (of these, 23 sources are used in the 32182) are assigned the following vector table
addresses.
Table 5.4.1 ICU Vector Table Addresses
Interrupt Request Source
ICU Vector Table Addresses
TIN3–6 input interrupt request
H'0000 0094
–
H'0000 0097
TIN20–23 input interrupt request
H'0000 0098
–
H'0000 009B
TIN12–19 input interrupt request
H'0000 009C
–
H'0000 009F
TIN0–2 input interrupt request
H'0000 00A0
–
H'0000 00A3
(Note 1)
H'0000 00A4
–
H'0000 00A7
TMS0,1 output interrupt request
H'0000 00A8
–
H'0000 00AB
TOP8,9 output interrupt request
H'0000 00AC
–
H'0000 00AF
TOP10 output interrupt request
H'0000 00B0
–
H'0000 00B3
TIO4–7 output interrupt request
H'0000 00B4
–
H'0000 00B7
TIO8,9 output interrupt request
H'0000 00B8
–
H'0000 00BB
TOP0–5 output interrupt request
H'0000 00BC
–
H'0000 00BF
TOP6,7 output interrupt request
H'0000 00C0
–
H'0000 00C3
TIO0–3 output interrupt request
H'0000 00C4
–
H'0000 00C7
DMA0–4 interrupt request
H'0000 00C8
–
H'0000 00CB
SIO1 receive interrupt request
H'0000 00CC
–
H'0000 00CF
SIO1 transmit interrupt request
H'0000 00D0
–
H'0000 00D3
SIO0 receive interrupt request
H'0000 00D4
–
H'0000 00D7
SIO0 transmit interrupt request
H'0000 00D8
–
H'0000 00DB
A-D0 conversion interrupt request
H'0000 00DC
–
H'0000 00DF
(Note 1)
H'0000 00E0
–
H'0000 00E3
(Note 1)
H'0000 00E4
–
H'0000 00E7
DMA5–9 interrupt request
H'0000 00E8
–
H'0000 00EB
SIO2,3 transmit/receive interrupt request
H'0000 00EC
–
H'0000 00EF
RTD interrupt request
H'0000 00F0
–
H'0000 00F3
(Note 1)
H'0000 00F4
–
H'0000 00F7
(Note 1)
H'0000 00F8
–
H'0000 00FB
(Note 1)
H'0000 00FC
–
H'0000 00FF
(Note 1)
H'0000 0100
–
H'0000 0103
(Note 1)
H'0000 0104
–
H'0000 0107
(Note 1)
H'0000 0108
–
H'0000 010B
CAN0 transmit/receive & error interrupt request
H'0000 010C
–
H'0000 010F
CAN1 transmit/receive & error interrupt request
H'0000 0110
–
H'0000 0113
Note 1: Valid for the interrupt requests in the 32180. No interrupt requests are generated in the 32182.
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INTERRUPT CONTROLLER (ICU)
5
5.5 Description of Interrupt Operation
5.5 Description of Interrupt Operation
5.5.1 Acceptance of Internal Peripheral I/O Interrupts
An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its
ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register.
If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt
requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests following the procedure described below.
1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are
compared with each other.
2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority.
3) The ILEVEL and IMASK values are compared.
If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels
set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If
the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed
priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its
priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU.
Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control
Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit.
Interrupt
requested
or not
1)
2)
3)
Resolve priority
according to
Interrupt Priority
Level (ILEVEL)
Resolve priority
according to
hardware priority
Compare with
IMASK value
Can be accepted
when IMASK = 4-7
(ILEVEL settings)
TIN3-6 input interrupt request
TIO4-7 output interrupt request
TOP8,9 output interrupt request
SIO0 transmit interrupt request
DMA0-4 interrupt request
A-D0 conversion interrupt request
Level 3
Requested
Level 4
Requested
Level 5
Requested
Level 3
Requested
Level 1
Not requested
Level 3
Requested
Accept interrupt
if PSW register
IE bit = 1
Level 3
Hardware
fixed priority
Level 3
Level 3
Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests
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INTERRUPT CONTROLLER (ICU)
5
5.5 Description of Interrupt Operation
Table 5.5.1 Hardware Fixed Priority Levels
Priority
High
Interrupt Request Source
ICU Vector Table Address
ICU Type of Input Source
TIN3–6 input interrupt request
H'0000 0094
–
H'0000 0097
Level-recognized
TIN20–23 input interrupt request
H'0000 0098
–
H'0000 009B
Level-recognized
TIN12–19 input interrupt request
H'0000 009C
–
H'0000 009F
Level-recognized
TIN0–2 input interrupt request
H'0000 00A0
–
H'0000 00A3
Level-recognized
TMS0,1 output interrupt request
H'0000 00A8
–
H'0000 00AB
Level-recognized
TOP8,9 output interrupt request
H'0000 00AC
–
H'0000 00AF
Level-recognized
TOP10 output interrupt request
H'0000 00B0
–
H'0000 00B3
Edge-recognized
TIO4–7 output interrupt request
H'0000 00B4
–
H'0000 00B7
Level-recognized
TIO8,9 output interrupt request
H'0000 00B8
–
H'0000 00BB
Level-recognized
TOP0–5 output interrupt request
H'0000 00BC
–
H'0000 00BF
Level-recognized
TOP6,7 output interrupt request
H'0000 00C0
–
H'0000 00C3
Level-recognized
TIO0–3 output interrupt request
H'0000 00C4
–
H'0000 00C7
Level-recognized
DMA0–4 interrupt request
H'0000 00C8
–
H'0000 00CB
Level-recognized
SIO1 receive interrupt request
H'0000 00CC
–
H'0000 00CF
Edge-recognized
SIO1 transmit interrupt request
H'0000 00D0
–
H'0000 00D3
Edge-recognized
SIO0 receive interrupt request
H'0000 00D4
–
H'0000 00D7
Edge-recognized
SIO0 transmit interrupt request
H'0000 00D8
–
H'0000 00DB
Edge-recognized
A-D0 conversion interrupt request
H'0000 00DC
–
H'0000 00DF
Edge-recognized
DMA5–9 interrupt request
H'0000 00E8
–
H'0000 00EB
Level-recognized
SIO2,3 transmit/receive interrupt request H'0000 00EC
–
H'0000 00EF
Level-recognized
RTD interrupt request
H'0000 00F0
–
H'0000 00F3
Edge-recognized
CAN0 transmit/receive & error interrupt
H'0000 010C
–
H'0000 010F
Level-recognized
H'0000 0110
–
H'0000 0113
Level-recognized
request
CAN1 transmit/receive & error interrupt
Low
request
Table 5.5.2 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set
IMASK values at which interrupts are accepted
0 (ILEVEL = "000")
Accepted when IMASK is 1–7
1 (ILEVEL = "001")
Accepted when IMASK is 2–7
2 (ILEVEL = "010")
Accepted when IMASK is 3–7
3 (ILEVEL = "011")
Accepted when IMASK is 4–7
4 (ILEVEL = "100")
Accepted when IMASK is 5–7
5 (ILEVEL = "101")
Accepted when IMASK is 6–7
6 (ILEVEL = "110")
Accepted when IMASK is 7
7 (ILEVEL = "111")
Not accepted (interrupts disabled)
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INTERRUPT CONTROLLER (ICU)
5
5.5 Description of Interrupt Operation
5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers
(1) Branching to the interrupt handler
Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware
preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External
Interrupt (EI) is located at the address H’0000 0080. This address is where the instruction (not the jump
address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is
written.
(2) Processing in the External Interrupt (EI) handler
A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown
in Figure 5.5.2.
[1] Saving each register to the stack
Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR
register to the stack as necessary.
[2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack
Read the Interrupt Request Mask Register and save its content to the stack.
[3] Reading the Interrupt Vector Register (IVECT)
Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table
for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the
Interrupt Vector Register is read, the following processing is automatically performed in hardware:
• The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a
new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request
source are masked.)
• The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request
sources).
• The interrupt request (EI) to the CPU core is dropped.
• The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution).
[4] Reading and overwriting the Interrupt Request Mask Register (IMASK)
Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK
register causes the following processing to be automatically performed in hardware:
• The interrupt request (EI) to the CPU core is dropped.
• The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution).
Note: • Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below.
[5] Reading the ICU vector table
Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table
address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in
[3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source).
The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request
source concerned.)
[6] Enabling multiple interrupts
To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple
interrupts), set the PSW register IE bit to "1".
[7] Branching to the internal peripheral I/O interrupt handler
Branch to the start address of the interrupt handler that was read out in [5].
[8] Processing in the internal peripheral I/O interrupt handler
[9] Disabling interrupts
Clear the PSW register IE bit to "0" to disable interrupts.
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INTERRUPT CONTROLLER (ICU)
5
5.5 Description of Interrupt Operation
[10] Restoring the Interrupt Request Mask Register (IMASK)
Restore the Interrupt Request Mask Register that was saved to the stack in [2].
[11] Restoring registers from the stack
Restore the registers that were saved to the stack in [1].
[12] Completion of external interrupt processing
Execute the RTE instruction to complete the external interrupt processing. The program returns to the
state in which it was before the currently processed interrupt request was accepted.
(3) Identifying the source of the interrupt request generated
If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status
Register provided for each internal peripheral I/O to identify the source of the interrupt request generated.
(4) Enabling multiple interrupts
To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable
interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register
(BPC, PSW, general-purpose registers and IMASK) to the stack.
Note: • Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU
vector table, as shown in Figure 5.5.2, “Typical Handler Operation for Interrupts from Internal
Peripheral I/O.”
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INTERRUPT CONTROLLER (ICU)
5
5.5 Description of Interrupt Operation
EI (External Interrupt)
vector entry
H'0000 0080
BRA instruction
EI (External Interrupt)
handler
Hardware preprocessing
when EIT is accepted
(Note 1)
Save BPC to the stack
[1]
Save PSW to the stack
Save general-purpose
registers to the stack
Program being
executed
[2]
Read and save Interrupt
Request Mask Register
(IMASK) to the stack
[3]
Read Interrupt Vector
Register (IVECT)
Interrupt
generated
[4]
Read and overwrite
Interrupt Request Mask
Register (IMASK)
[5]
Read ICU vector table
H'0080 0004
H'0080 0000
(Note 2)
(Note 3)
ICU vector table
H'0000 0113
Branch to the interrupt handler
for each internal peripheral I/O
Hardware postprocessing
when RTE instruction
is executed
Interrupt
handler
(Note 1)
[9]
[10]
Interrupt handler
start address
Set PSW register IE bit to 1 (Note 4)
(Note 5)
[7]
IVECT
(Note 2)
H'0000 0094
[6]
IMASK
Clear PSW register
IE bit to 0
Restore Interrupt Request
Mask Register (IMASK)
from the stack
Interrupt
handler
[8]
(Note 4)
(Note 2)
Restore general-purpose
registers from the stack
[11]
Restore PSW from the stack
[1] to [12]: Processing of EI
by interrupt handler
Restore BPC from the stack
[12]
RTE
Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure."
Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK)
in the EIT handler unless interrupts are disabled (PSW register IE bit = 0).
Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple
interrupts are enabled by executing processing in [6] and [9].
Note 4: To enable multiple interrupts, execute processing in [6] and [9].
Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT),
perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here,
there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register.
Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register
(IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts.
Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O
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INTERRUPT CONTROLLER (ICU)
5
5.6 Description of System Break Interrupt (SBI) Operation
5.6 Description of System Break Interrupt (SBI) Operation
5.6.1 Acceptance of SBI
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be
masked.
5.6.2 SBI Processing by Handler
When the system break interrupt generated has been serviced, shut down or reset the system without returning
to the program that was being executed when the interrupt occurred.
SBI (System Break Interrupt)
vector entry
H'0000 0010
BRA instruction
SBI (System Break Interrupt)
handler
Program being
executed
Processing to shut
down the system
(Note 1)
SBI generated
Shut down or
reset the system
Note 1: Do not return to the program that was being executed when the interrupt occurred.
Figure 5.6.1 Typical SBI Operation
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32182 Group User’s Manual (Rev.1.0)
CHAPTER 6
INTERNAL MEMORY
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Outline of the Internal Memory
Internal RAM
Internal Flash Memory
Registers Associated with the Internal
Flash Memory
Programming the Internal Flash Memory
Virtual Flash Emulation Function
Connecting to A Serial Programmer
Internal Flash Memory Protect Function
Precautions To Be Taken when Rewriting
the Internal Flash Memory
INTERNAL MEMORY
6
6.1 Outline of the Internal Memory
6.1 Outline of the Internal Memory
The 32182 internally contains the following types of memory:
• 64-Kbyte RAM
• 384-Kbytes flash memory
6.2 Internal RAM
Specifications of the internal RAM are shown below.
Table 6.2.1 Specifications of the Internal RAM
Item
Specification
Size
64 Kbytes
Location address
H’0080 4000 to H’0081 3FFF
Wait insertion
Operates with zero wait states
Internal bus connection
Connected by 32-bit bus
Dual port
By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of
the internal RAM via serial communication from external devices independently of the CPU. (See
Chapter 14, “Real-Time Debugger.”)
Notes: • Immediately after power-on reset (for the power-on case in which VDDE also goes up from GND), the value of the
RAM is undefined.
• If the RAM is reset during RAM backup (power for only VDDE is on), the RAM retains the value it had immediately
before being reset.
6.3 Internal Flash Memory
Specifications of the internal flash memory are shown below.
Table 6.3.1 Specifications of the Internal Flash Memory
Item
Specification
Size
M32182F3: 384 Kbytes
M32182F8: 1 Mbyte
Location address
M32182F3: H’0000 0000 to H’0005 FFFF
M32182F8: H’0000 0000 to H’000F FFFF
Wait insertion
Operates with one wait state
Durability
Can be rewritten 100 times
Internal bus connection
Instruction access: Connected by 64-bit bus (Transfer rates equivalent to zero wait states on 32-bit
bus are possible.)
Data access: Connected by 32-bit bus
Other
Virtual flash emulation function is incorporated. (See Section 6.6, “Virtual Flash Emulation Function.”)
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INTERNAL MEMORY
6
6.3 Internal Flash Memory
Internal flash memory area of the M32182F3 (384 Kbytes)
H'0000 0000
16KB
Block 0
H'0000 4000
H'0000 6000
H'0000 8000
8KB
8KB
Block 1
Block 2
32KB
Block 3
64KB
Block 4
64KB
Block 5
64KB
Block 6
64KB
Block 7
64KB
Block 8
Unequal blocks
H'0001 0000
H'0002 0000
H'0003 0000
Equal blocks
H'0004 0000
H'0005 0000
H'0005 FFFF
Figure 6.3.1 Block Configuration of the M32182F3’s Internal Flash Memory
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INTERNAL MEMORY
6
Internal flash memory area of the M32182F8 (1 Mbyte)
H'0000 0000
16KB
H'0000 4000
H'0000 6000
H'0000 8000
8KB
8KB
Block 0
Block 1
Block 2 Unequal blocks
32KB
Block 3
64KB
Block 4
64KB
Block 5
64KB
Block 6
64KB
Block 7
64KB
Block 8
64KB
Block 9
64KB
Block 10
64KB
Block 11 Equal blocks
64KB
Block 12
64KB
Block 13
64KB
Block 14
64KB
Block 15
64KB
Block 16
64KB
Block 17
64KB
Block 18
H'0001 0000
H'0002 0000
H'0003 0000
H'0004 0000
H'0005 0000
H'0006 0000
H'0007 0000
H'0008 0000
H'0009 0000
H'000A 0000
H'000B 0000
H'000C 0000
H'000D 0000
H'000E 0000
H'000F 0000
H'000F FFFF
Figure 6.3.2 Block Configuration of the M32182F8’s Internal Flash Memory
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INTERNAL MEMORY
6
6.4 Registers Associated with the Internal Flash Memory
6.4 Registers Associated with the Internal Flash Memory
A register map associated with the internal flash memory is shown below.
Internal Flash Memory Related Register Map
Address
+0 address
+1 address
b0
b7 b8
H'0080 01E0
Flash Mode Register
(FMOD)
Flash Control Register 1
(FCNT1)
Flash Control Register 3
(FCNT3)
H'0080 01E2
H'0080 01E4
See pages
b15
Flash Status Register 1
(FSTAT1)
Flash Control Register 2
(FCNT2)
Flash Control Register 4
(FCNT4)
H'0080 01E6
6-5
6-6
6-8
6-9
6-10
(Use inhibited area)
H'0080 01E8
Virtual Flash S Bank Register
(FESBANK0)
Virtual Flash S Bank Register
(FESBANK1)
Virtual Flash S Bank Register
(FESBANK2)
Virtual Flash S Bank Register
(FESBANK3)
Virtual Flash S Bank Register
(FESBANK4)
Virtual Flash S Bank Register
(FESBANK5)
Virtual Flash S Bank Register
(FESBANK6)
Virtual Flash S Bank Register
(FESBANK7)
H'0080 01EA
H'0080 01EC
H'0080 01EE
H'0080 01F0
H'0080 01F2
H'0080 01F4
H'0080 01F6
0
6-12
1
6-12
2
6-12
3
6-12
4
6-12
5
6-12
6
6-12
7
6-12
6.4.1 Flash Mode Register
Flash Mode Register (FMOD)
b0
1
2
3
<Address: H’0080 01E0>
4
5
6
b7
FPMOD
0
0
0
0
0
0
0
?
<After reset: H’0?>
b
Bit Name
0–6
No function assigned. Fix to "0"
7
FPMOD
External FP pin status bit
Function
R
W
0
0
0: FP pin = "low"
1: FP pin = "high"
R
–
The Flash Mode Register (FMOD) is a read-only status register, with its FPMOD bit indicating the FP (Flash
Protect) pin status.
The internal flash memory is enabled for programming or erase operation only when FPMOD = "1", and is
protected against programming or erase operation when FPMOD = "0".
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6
6.4 Registers Associated with the Internal Flash Memory
6.4.2 Flash Status Registers
There are two registers to indicate the status of the internal flash memory: Flash Status Register 1 (FSTAT1)
located in the SFR area (H’0080 01E1) and Flash Status Register 2 (FSTAT2) included in the internal flash
memory. Use these two status registers (FSTAT1 and FSTAT2) to control the programming or erase operation
performed on the internal flash memory.
Flash Status Register 1 (FSTAT1)
b8
9
10
11
12
<Address: H’0080 01E1>
13
14
b15
FSTAT
0
0
0
0
0
0
0
1
<After reset: H’01>
b
Bit Name
Function
8–14
No function assigned. Fix to "0".
15
FSTAT
Ready/busy status bit
0: Busy
1: Ready
R
W
0
0
R
–
Flash Status Register 1 (FSTAT1) is a read-only status register used to know the status of the programming or
erase operation performed on the internal flash memory. When FSTAT = "0" (busy), the internal flash memory is
being programmed or erased, during which time do not start a new programming or erase operation on it. When
FSTAT = "1" (ready), a new programming or erase operation can be started on it.
Furthermore, while FSTAT = "0" (busy), do not operate on the FCNT4 register FRESET bit described later.
6.4.3 Flash Status Register 2 (FSTAT2)
Flash Status Register 2 (FSTAT2)
b8
9
FBUSY
1
10
11
12
13
14
b15
0
0
0
ERASE WRERR1 WRERR2
0
0
0
0
<After reset: H’80>
b
Bit Name
Function
R
W
8
FBUSY
Flash busy bit
0: Being programmed or erased
1: Ready state
R
–
9
No function assigned. Fix to "0".
0
–
R
–
10
ERASE
0: Erase normally operating or terminated
Erase status confirmation bit
1: Erase error occurred
11
WRERR1
Write status confirmation bit 1
0: Programming normally operating or terminated
1: Programming error occurred
R
–
12
WRERR2
Write status confirmation bit 2
0: Programming normally operating or terminated
1: Over-programming occurred
R
–
13–15
No function assigned. Fix to "0".
0
0
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6
6.4 Registers Associated with the Internal Flash Memory
This status register is included in the internal flash memory, and can be enabled for read by writing the Read
Status command (H’7070) to any address of the internal flash memory. For details, see Section 6.5, “Programming the Internal Flash Memory.”
Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits that indicate the operation
condition of the internal flash memory.
(1) FBUSY (Flash Busy) bit (Bit 8)
The FBUSY bit is used to determine whether the operation on the internal flash memory is finished when it is
being programmed or erased. When FBUSY = "0", it means that the programming or erase operation is being
executed; when FBUSY = "1", the operation is finished.
(2) ERASE (Erase status) bit (Bit 10)
The ERASE bit is used to determine after execution of processing whether the erase operation performed on
the internal flash memory resulted in an error. When ERASE = "0", it means that the erase operation terminated normally; when ERASE = "1", the erase operation terminated in an error.
(3) WRERR1 (Write status 1) bit (Bit 11)
The WRERR1 bit is used to determine after completion of processing whether the programming operation
performed on the internal flash memory resulted in an error. When WRERR1 = "0", it means that the programming operation terminated normally; when WRERR1 = "1", the programming operation terminated in an
error.
The condition under which WRERR1 is set to "1" is when any bit other than those that must be "0" is found to
be "0" by comparison between the write data and the data in the internal flash memory.
(4) WRERR2 (Write status 2) bit (Bit 12)
The WRERR2 bit is used to determine after execution of processing whether the programming operation
performed on the internal flash memory resulted in an error. When WRERR2 = "0", it means that the programming operation terminated normally; when WRERR2 = "1", the programming operation terminated in an
error.
The condition under which WRERR2 is set to "1" is when the internal flash memory cannot be written to even
by repeating the programming operation a specified number of times.
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6
6.4 Registers Associated with the Internal Flash Memory
6.4.4 Flash Control Registers
Flash Control Register 1 (FCNT1)
b0
1
2
3
4
<Address: H’0080 01E2>
5
6
FENTRY
0
0
0
0
b7
FEMMOD
0
0
0
0
<After reset: H’00>
b
Bit Name
0–2
No function assigned. Fix to "0".
3
FENTRY
Flash E/W enable mode entry bit
4–6
No function assigned. Fix to "0".
7
FEMMOD
Virtual flash emulation mode bit
Function
R
0
0
0: Normal read
1: Program/erase enable
R
W
0
0
R
W
0: Normal mode
1: Virtual flash emulation mode
W
Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory.
(1) FENTRY (Flash Mode Entry) bit (Bit 3)
The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when
FENTRY = "1".
To set the FENTRY bit to "1", write "0" and then "1" to the FENTRY bit in succession while the FP pin = "high". To
clear the FENTRY bit, check to see that the FSTAT1 register FSTAT bit = "1" (ready) and then write "0" to the
FENTRY bit.
Note that the following operations cannot be performed while programming or erasing the internal flash
memory (FSTAT1 register FSTAT bit = "0" (busy)). If one of these operations is attempted, the FENTRY bit
is cleared to "0" in hardware.
1) Writing "0" to the FENTRY bit
2) Entering a low-level signal to the FP pin
3) Entering a low-level signal to the RESET# pin
When running a program resident in the internal flash memory while the FENTRY bit = "0", the EI vector entry
is located at the address H’0000 0080 of the internal flash memory. When running the flash write/erase
program in the RAM while the FENTRY bit = "1", the EI vector entry is located at the address H’0080 4000 of
the RAM, allowing the flash programming/erase operation to be controlled using interrupts.
Table 6.4.1 Changes of the EI Vector Entry by FENTRY
FENTRY
EI Vector Entry
Address
0
Internal flash memory area
H'0000 0080
1
Internal RAM area
H'0080 4000
(2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7)
The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by
setting the FEMMOD bit to "1" while the FENTRY bit = "0". (For details, see Section 6.6, “Virtual Flash
Emulation Function.”)
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6
6.4 Registers Associated with the Internal Flash Memory
Flash Control Register 2 (FCNT2)
b8
9
10
11
12
<Address: H’0080 01E3>
13
14
b15
FPROT
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
8–14
No function assigned. Fix to "0".
15
FPROT
Unlock bit
0: Protection by lock bit effective
1: Protection by lock bit invalidated
R
W
0
0
R
W
Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit
(protection against programming/erase operation). Protection of the internal flash memory is invalidated by
setting the FPROT bit to "1", so that any blocks protected by a lock bit can now be programmed or erased.
To set the FPROT bit to "1", write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1". To
clear the FPROT bit to "0", write "0" to the FPROT bit.
If one of the following operations is attempted, the FPROT bit is cleared to "0".
1) Writing "0" to the FPROT bit
2) Entering a low-level signal to the FP pin
3) Clearing the FENTRY bit to "0"
4) Entering a low-level signal to the RESET# pin
FENTRY = 1
NO
FPROT = 0
YES
FENTRY = 1
FPROT = 0
FPROT is not set to 1 if a write cycle
to any other area occurs during this time.
FPROT = 1
FPROT = 1
Figure 6.4.1 Protection Unlocking Flow
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6
6.4 Registers Associated with the Internal Flash Memory
Flash Control Register 3 (FCNT3)
b0
1
2
3
4
<Address: H’0080 01E4>
5
6
b7
FELEVEL
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0–6
No function assigned. Fix to "0".
Function
7
FELEVEL
0: Normal level
Erase margin-up bit
1: Raise erase margin up
R
W
0
0
R
W
Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one
of erase commands. The internal flash memory erase level can be deepened by setting the FELEVEL bit to "1".
Flash Control Register 4 (FCNT4)
b8
9
10
11
12
<Address: H’0080 01E5>
13
14
b15
FRESET
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
0
R
W
8–14
No function assigned. Fix to "0".
15
FRESET
0: No operation
Flash reset bit
1: Reset
W
Flash Control Register 4 (FCNT4) controls initializing each status bit of Flash Status Register 2 (FSTAT2) or
canceling a programming/erase operation.
Setting the FRESET bit to "1" initializes each status bit of the FSTAT2 register or cancels a programming/erase
operation.
The FRESET bit is effective only when the FENTRY bit = "1". If the FENTRY bit = "0", the FRESET bit information is ignored.
When programming or easing the internal flash memory, make sure the FRESET bit remains "0".
An example for clearing each status of FSTAT2 during a programming/erase operation, and an example for
forcibly terminating (canceling) a programming/erase operation due to time-out are shown below.
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6.4 Registers Associated with the Internal Flash Memory
FENTRY = 0
FENTRY = 1
Program/erase
the flash memory
* At this point in time,
the FSTAT1 register FSTAT bit = 1 (ready).
Error found
NO
YES
FRESET = 1
Programming/erase
operation terminated normally
FRESET = 0
Program/erase
the flash memory
Figure 6.4.2 Example of FCNT4 Register Operation 1 (Clearing each status of the FSTAT2 register)
Flash programming/erase operation has timed out
Forcibly terminate
FRESET = 1
FRESET = 0
Figure 6.4.3 Example of FCNT4 Register Operation 2 (Forcibly terminating operation when programming/
erasing the internal flash memory)
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6
6.4 Registers Associated with the Internal Flash Memory
6.4.5 Virtual Flash S Bank Registers
Virtual
Virtual
Virtual
Virtual
Virtual
Virtual
Virtual
Virtual
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
b0
1
S
S
S
S
S
S
S
S
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Register
Register
Register
Register
Register
Register
Register
Register
2
3
0
1
2
3
4
5
6
7
4
(FESBANK0)
(FESBANK1)
(FESBANK2)
(FESBANK3)
(FESBANK4)
(FESBANK5)
(FESBANK6)
(FESBANK7)
5
6
<Address: H’0080 01E8>
<Address: H’0080 01EA>
<Address: H’0080 01EC>
<Address: H’0080 01EE>
<Address: H’0080 01F0>
<Address: H’0080 01F2>
<Address: H’0080 01F4>
<Address: H’0080 01F6>
7
8
9
10
MODENS
0
11
12
13
14
0
0
b15
SBANKAD
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
0
Bit Name
Function
R
W
MODENS
0: Disable virtual flash emulation function
R
W
Virtual flash emulation enable bit
1: Enable virtual flash emulation function
0
0
R
W
1–7
No function assigned. Fix to "0".
8-15
SBANKAD
S bank address
Start address A12–A19 of the relevant S bank
Note: • These registers must always be accessed in halfwords.
(1) MODENS (Virtual Flash Emulation Enable) bit (Bit 0)
The MODENS bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to
"1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the S bank
area selected by the SBANKAD bits.
(2) SBANKAD (S Bank Address) bits (Bits 8–15)
The SBANKAD bits are provided for selecting one of the S banks that are separated every 4 KB. Use these
SBANKAD bits to set the eight bits A12–A19 of the 32-bit start address of the desired S bank.
Note: • For details, see Section 6.6, “Virtual Flash Emulation Function.”
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INTERNAL MEMORY
6
6.5 Programming the Internal Flash Memory
6.5 Programming the Internal Flash Memory
6.5.1 Outline of Internal Flash Memory Programming
To program or erase the internal flash memory, there are following two methods to choose depending on the
situation:
(1) When the flash write/erase program does not exist in the internal flash memory
(2) When the flash write/erase program already exists in the internal flash memory
For (1), set the FP pin = "high", MOD0 = "high" and MOD1 = "low" to enter boot mode. In this case, the CPU
starts running the boot program immediately after reset.
The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a
location in the RAM and use the RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit
to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode +
flash E/W enable mode).
When the above is done, use the flash write/erase program that has been transferred into the internal RAM to
program or erase the internal flash memory.
For (2), set the FP pin = "high", MOD0 = "low" and MOD1 = "low" to enter single-chip mode. Transfer the flash
write/erase program from the internal flash memory in which it has been prepared into the internal RAM. After
the transfer, jump to the RAM and use the program transferred into the RAM to set the Flash Control Register 1
(FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e.,
placed in single-chip mode + flash E/W enable mode).
When the above is done, use the flash write/erase program that has been transferred into the internal RAM to
program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension
mode by setting the FP pin = "high", MOD0 = "low" and MOD1 = "high".
During flash E/W enable mode (FP pin = 1, FENTRY = 1), the EIT vector entry for External Interrupt (EI) is
relocated to the start address (H’0080 4000) of the internal RAM. During normal mode, it is located in the flash
area (H’0000 0080).
Flash E/W enable mode
(FENTRY = 1)
Normal mode
(FENTRY = 0)
H'0000 0000
H'0000 0000
EI vector entry
(H'0000 0080)
Internal ROM area
Internal ROM area
EI vector entry
H'0080 3FFF
H'0080 4000
(H'0080 4000)
H'0080 3FFF
H'0080 4000
Internal RAM
Internal RAM
H'00FF FFFF
H'00FF FFFF
Figure 6.5.1 EI Vector Entry during Flash E/W Enable Mode
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INTERNAL MEMORY
6
6.5 Programming the Internal Flash Memory
(1) When the flash write/erase program does not exist in the internal flash memory
In this case, the boot program is used to program or erase the internal flash memory. To transfer the write
data, use serial I/O1 in clock-synchronized serial mode.
To program or erase the internal flash memory using a flash programmer, follow the procedure described below.
FP = L or H MOD1 = L
MOD0 = L RESET = L
<Step 1>
• Initial state (Flash write/erase program nonexistent in the internal
flash memory)
CPU
RAM
Boot
program
Flash
memory
Write data
SIO1
External device (e.g., flash programmer)
M32R/ECU
FP = H
RAM
MOD1 = L
MOD0 = H RESET = H
Flash write/
erase
program
<Step 2>
• Set the FP pin high, MOD0 pin high and MOD1 pin low to place the
flash memory in boot mode + flash E/W enable mode.
• Dessert reset signal and start up with the boot program.
• Transfer the flash write/erase program into the RAM.
• Jump to the flash write/erase program in the RAM.
CPU
Boot
program
Flash
memory
Write data
SIO1
External device (e.g., flash programmer)
M32R/ECU
FP = H
RAM
Flash
memory
MOD1 = L
MOD0 = H RESET = H
Flash write/
erase
program
Flash write
data
CPU
Boot
program
SIO1
M32R/ECU
<Step 3>
• Using the flash write/erase program in the RAM, set the Flash Control
Register 1 (FCNT1) FENTRY bit to 1.
• Program or erase the internal flash memory using the flash write/erase
program.
• When finished, reset MOD0 low and jump to the internal flash memory
or apply a reset to enter normal mode.
Write data
External device (e.g., flash programmer)
Figure 6.5.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase
program does not exist in it)
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6
6.5 Programming the Internal Flash Memory
Reset signal deasserted
(Boot program starts)
POWER ON
Mode
selected
Reset signal deasserted
Mode
selected
RESET# pin
MOD0 pin
MOD1 pin
FP pin
Settings by the
boot program
FENTRY bit
Flash programming/erasing
by the boot program
Figure 6.5.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it)
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6
6.5 Programming the Internal Flash Memory
(2) When the flash write/erase program already exists in the internal flash memory
In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase
the internal flash memory.
For programming/erase operation here, use the internal peripheral circuits in the manner suitable for the
programming system. (All resources of the internal peripheral circuits such as the data bus, serial I/O and
ports can be used.)
The following shows an example for programming or erasing the internal flash memory by using serial I/O0 in
single-chip mode.
FP = L or H
MOD1 = L
MOD0 = L
RAM
CPU
Flash write/
erase
program
SIO0
<Step 1>
• Initial state (Flash write/erase program existing in the internal flash memory)
• An ordinary program in the internal flash memory is being executed.
Write data
External device
M32R/ECU
FP = H
RAM
MOD1 = L
MOD0 = L
Flash write/
erase
program
CPU
Flash
memory
SIO0
<Step 2>
• Set the FP pin high, MOD1 pin low and MOD0 pin low to place the
flash memory in single-chip + flash E/W enable mode.
• After determining the FP pin and MOD1 pin levels, transfer the flash
write/erase program from the internal flash memory area into the RAM.
• Jump to the flash write/erase program in the RAM.
Write data
External device
M32R/ECU
FP = H
RAM
Flash
memory
MOD1 = L
Flash write/
erase
program
Flash write
data
MOD0 = L
<Step 3>
• Using the flash write/erase program in the RAM, set the Flash Control
Register 1 (FCNT1) FENTRY bit to 1.
• Program or erase the internal flash memory using the flash write/erase
program in the RAM.
• When finished, jump to the program in the flash memory or apply a
reset to enter normal mode.
CPU
SIO0
Write data
External device
M32R/ECU
Figure 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase
program already exists in it)
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6
6.5 Programming the Internal Flash Memory
Flash rewrite Flash mode
turned on
starts
Flash mode
turned off
RESET# pin High or low
MOD0 pin Low
MOD1 pin High or low (single-chip or external extension)
FP pin High or low
FENTRY bit
Flash programming/erasing by
the flash write/erase program
Flash write/erase program
transferred into the RAM
Figure 6 .5.5 Internal Flash Memory Write/Erase Timing (when the flash write/erase program already exists in it)
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6
6.5 Programming the Internal Flash Memory
6.5.2 Controlling Operation Modes during Flash Programming
The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY
bit. The table below lists operation modes that may be used when programming or erasing the internal flash
memory.
Table 6.5.1 Operation Modes Set during Flash Programming/Erase
FP
MOD0 MOD1 FENTRY (Note 1) Operation Mode
Reset Vector Entry
EI Vector Entry
0
0
0
0
Start address of internal
Flash area
1
0
0
0
flash memory
(H'0000 0080)
Single-chip mode
(H'0000 0000)
0
1
0
0
Processor mode
Start address of external
External area
area
(H'0000 0000)
(H'0000 0080)
0
0
1
0
External extension
Start address of internal
Flash area
1
0
1
0
mode
flash memory
(H'0000 0080)
1
0
0
1
Single-chip mode
Start address of internal
Beginning of internal RAM
+ flash E/W enable
flash memory
(H'0080 4000)
(H'0000 0000)
(H'0000 0000)
1
1
1
–
1
1
0
1
0
0
1
1
0
1
1
–
Boot mode
Boot program starts
Flash area
running
(H'0000 0080)
Boot mode + flash
Boot program starts
Beginning of internal RAM
E/W enable
running
(H'0080 4000)
External extension
Start address of internal
Beginning of internal RAM
mode + flash E/W
flash memory
(H'0080 4000)
enable
(H'0000 0000)
Use inhibited
–
–
Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (– denotes “Don’t care”). However, if FP = "0",
writing "1" to FENTRY only results in it cleared to "0".
(1) Flash E/W enable mode
Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash
E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the necessary
program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be
executed in the RAM.
(2) Entering flash E/W enable mode
Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode.
Furthermore, it is only when the FP pin = "high" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1"
that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operating in
processor mode or the FP pin = "low".
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6
6.5 Programming the Internal Flash Memory
(3) Detecting the MOD0 and MOD1 pin levels
The MOD0 and MOD1 pin levels ("high" or "low") can be known by checking the P8 Data Register (Port Data
Register, H’0080 0708) MOD0DT and MOD1DT bits.
P8 Data Register (P8DATA)
b0
1
2
MOD0DT MOD1DT P82DT
?
?
<Address: H’0080 0708>
3
4
5
6
b7
P83DT
P84DT
P85DT
P86DT
P87DT
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0
MOD0DT
MOD0 data bit
0: MOD0 pin = "low"
1: MOD0 pin = "high"
R
–
1
MOD1DT
MOD1 data bit
0: MOD1 pin = "low"
1: MOD1 pin = "high"
R
–
2
P82DT
Port P82 data bit
At read
Depends on how the Port Direction Register is set
R
W
3
P83DT
• If direction bit = "0" (input mode)
Port P83 data bit
4
P84DT
Port P84 data bit
5
P85DT
Port P85 data bit
6
P86DT
Port P86 data bit
7
P87DT
0: Port input pin = "low"
1: Port input pin = "high"
• If direction bit = "1" (output mode) (Note 1)
0: Port output latch = "0" / Port pin level = "low"
1: Port output latch = "1" / Port pin level = "high"
At write
Write to the port output latch
Port P87 data bit
Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL).
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6.5 Programming the Internal Flash Memory
START
Enter one of the following modes:
• Single-chip mode
• Boot mode
• External extension mode
Check
MOD0/1 and FP pin
levels
FMOD(H'0080 01E0)
FPMOD
P8DATA(H'0080 0708)
D0 = MOD0DT
D1 = MOD1DT
NO
OK
END
Transfer the flash write/erase program
into the internal RAM
Set the Flash Control Register in SFR area
(FCNT1, H'0080 01E2) FENTRY bit to 0
Set the Flash Control Register in SFR area
(FCNT1, H'0080 01E2) FENTRY bit to 1
Switched to the flash write/erase
program
→ Go to flash E/W enable mode
Wait for 1 µs
(using a hardware or software timer)
Execute flash write/erase command and
various read commands (Note 1)
Jump to the flash memory or apply reset
Switched to normal mode
END
Note 1: For details about each command, see Section 6.5.4, "Procedure for Programming/Erasing
the Internal Flash Memory."
Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode
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6.5 Programming the Internal Flash Memory
6.5.3 Procedure for Programming/Erasing the Internal Flash Memory
To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the
flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory.
In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode,
no programs present in it can be executed. Therefore, the flash write/erase program must be made available in
the internal RAM before entering flash E/W enable mode. (Once flash E/W enable mode is entered into, only
flash commands and no other commands can be used to access the internal flash memory.)
To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory
address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode.
Note: • During flash E/W enable mode, the internal flash memory cannot be accessed for read or write
wordwise.
Table 6.5.2 Commands in Flash E/W Enable Mode
Command Name
Issued Command Data
Read Array command
H'FFFF
Page Program command
H'4141
Lock Bit Program command
H'7777
Block Erase command
H'2020
Erase All Unlocked Blocks command
H'A7A7
Read Status Register command
H'7070
Clear Status Register command
H'5050
Read Lock Bit Status command
H'7171
Verify command (Note 1)
H'D0D0
Note 1: • This command is used in conjunction with Lock Bit Program, Block Erase and Erase All Unlocked Blocks
operations.
• This command must be issued immediately after the Lock Bit Program, Block Erase or Erase All Unlocked Blocks
command.
• If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by the Read Array command (H’FFFF), the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is canceled.
• If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by other than the Verify
(H'D0D0) or Read Array (H'FFFF) command, the Lock Bit Program, Block Erase or Erase All Unlocked Blocks
command is not executed normally and terminated in error.
(1) Read Array command
Writing the command (H’FFFF) to any address of the internal flash memory places it in read mode. Then read
the desired flash memory address, and the content of that address will be read out.
Before exiting flash E/W enable mode, always be sure to execute the Read Array command.
START
Write the Read Array command (H'FFFF)
to any address of the internal flash memory
Read the desired flash memory address
END
Figure 6.5.7 Read Array Command
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6.5 Programming the Internal Flash Memory
(2) Page Program command
The internal flash memory is programmed one page at a time, each page consisting of 256 bytes (lower
addresses H’00 to H’FF). To program the flash memory, write the Page Program command (H’4141) to any
address of the internal flash memory and then the program data to the address to be programmed.
The protected flash memory blocks cannot be accessed for write by the Page Program command.
Page programming is automatically performed by the internal control circuit, and whether the Page Program
command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See
Section 6.4.2, “Flash Status Registers.”) While the FSTAT bit = "0" (busy), the next programming (by the
Page Program command) cannot be performed.
START
Write the Page Program command
(H'4141) to any address of
the internal flash memory
Write the program data to the internal flash
memory address to be programmed (Note 1)
Write the next program data to the
previously programmed address + 2
NO
Finished programming
one page?
YES
Internal flash memory is programmed
by Page Program (Note 2)
Wait for 1 µs
(using a hardware or software timer)
NO
FSTAT bit = 1
YES
To next page
Read any address of the internal flash
memory (Note 3) to check for programming
error (see Figure 6.4.2)
NO
TIME OUT?
0.5s
NO
YES
Forcibly terminated
(see Figure 6.4.3.)
Last address?
YES
END
Note 1: Start programming from the beginning of a 256-byte boundary (lower address H'00).
Note 2: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command,
so that there is no need to enter the Read Status command until another command is entered.
Note 3: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check
for programming error.
Figure 6.5.8 Page Program Command
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6.5 Programming the Internal Flash Memory
(3) Lock Bit Program command
The internal flash memory can be protected against programming/erase operation one block at a time. The
Lock Bit Program command is provided for protecting the flash memory blocks.
Write the Lock Bit Program command (H’7777) to any address of the internal flash memory. Next, write the
Verify command (H’D0D0) to the last even address of the flash memory block to be protected, and this
memory block is thereby protected against programming/erase operation. To remove protection, use the
Flash Control Register 2 (FCNT2) FPROT bit to invalidate protection by a lock bit (see Section 6.4.3, “Flash
Control Registers”) and erase the flash memory block whose protection is to be removed. (The content of
that memory block is also erased.)
Executing a programming/erase operation on flash memory blocks protected by a lock bit results in an error.
If erased, the FSTAT2 register ERASE bit is set to "1" (erase error occurred); if programmed, the FSTAT2
register WRERR1 bit is set to "1" (programming error occurred).
The table below lists the target flash memory blocks and their addresses to be specified when writing the
Verify command.
Table 6.5.3 M32182F3 Target Blocks and Specified Addresses
Target Block
Specified Address
0
H'0000 3FFE
1
H'0000 5FFE
2
H'0000 7FFE
3
H'0000 FFFE
4
H'0001 FFFE
5
H'0002 FFFE
6
H'0003 FFFE
7
H'0004 FFFE
8
H'0005 FFFE
Table 6.5.4 M32182F8 Target Blocks and Specified Addresses
Target Block
Specified Address
0
H'0000 3FFE
1
H'0000 5FFE
2
H'0000 7FFE
3
H'0000 FFFE
4
H'0001 FFFE
5
H'0002 FFFE
6
H'0003 FFFE
7
H'0004 FFFE
8
H'0005 FFFE
9
H'0006 FFFE
10
H'0007 FFFE
11
H'0008 FFFE
12
H'0009 FFFE
13
H'000A FFFE
14
H'000B FFFE
15
H'000C FFFE
16
H'000D FFFE
17
H'000E FFFE
18
H'000F FFFE
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6.5 Programming the Internal Flash Memory
START
Write the Lock Bit Program command
(H'7777) to any address of the
internal flash memory
Write the Verify command (H'D0D0)
to the last even address of the flash
memory block to be protected
Lock bit is programmed
by Lock Bit Program (Note 1)
Wait for 1 µs
(using a hardware or software timer)
NO
FSTAT bit = 1
YES
TIME OUT?
0.5s
Read any address of the internal flash
memory (Note 2) to check for
programming error (see Figure 6.4.2)
NO
YES
Forcibly terminated
(see Figure 6.4.3.)
END
Note 1: When a programming operation started, the internal flash memory is automatically readied to run the Read Status
command, so that there is no need to enter the Read Status command until another command is entered.
Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2)
bits to check for programming error.
Figure 6.5.9 Lock Bit Program Command
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6.5 Programming the Internal Flash Memory
(4) Block Erase command
The Block Erase command erases the content of the internal flash memory one block at a time. To perform
this operation, write the Block Erase command (H’2020) to any address of the internal flash memory. Next,
write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see
Table 6.5.3, “M32182F3 Target Blocks and Specified Addresses”).
The protected flash memory blocks cannot be erased by the Block Erase command.
Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase
command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See
Section 6.4.2, “Flash Status Registers.”) While the FSTAT bit = "0" (busy), the next block erase operation (by
the Block Erase command) cannot be performed.
START
Write the Block Erase command
(H'2020) to any address of the
internal flash memory
Write the Verify command (H'D0D0) to
the last even address of the flash
memory block to be erased
Internal flash memory contents
are erased by the Block Erase
command (Note 1)
Wait for 1 µs
(using a hardware or software timer)
NO
FSTAT bit = 1
YES
TIME OUT?
1s
Read any address of the internal flash
memory (Note 2) to check for erase
error (see Figure 6.4.2)
NO
YES
Forcibly terminated
(see Figure 6.4.3.)
END
Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command,
so that there is no need to enter the Read Status command until another command is entered.
Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits
to check for erase error.
Figure 6.5.10 Block Erase Command
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6.5 Programming the Internal Flash Memory
(5) Erase All Unlocked Blocks command
The Erase All Unlocked Blocks command erases all flash memory blocks that are not protected. To erase all
unlocked blocks, write the command (H’A7A7) to any address of the internal flash memory. Next, write the
Verify command (H’D0D0) to any address of the internal flash memory, and all unlocked memory blocks are
thereby erased.
START
Write the Erase All Unlocked Blocks
command (H'A7A7) to any address of the
internal flash memory
Write the Verify command (H'D0D0) to
any address of the internal flash memory
Flash memory contents are erased
by Erase All Unlocked Blocks
(Note 1)
Wait for 1 µs
(using a hardware or software timer)
NO
FSTAT bit = 1
YES
TIME OUT?
10s
Read any address of the internal flash
memory (Note 2) to check for erase
error (see Figure 6.4.2)
NO
YES
Forcibly terminated
(see Figure 6.4.3.)
END
Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command,
so that there is no need to enter the Read Status command until another command is entered.
Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits
to check for erase error.
Figure 6.5.11 Erase All Unlocked Blocks Command
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6.5 Programming the Internal Flash Memory
(6) Read Status Register command
The Read Status Register command reads the content of Flash Status Register 2 (FSTAT2) that indicates
whether flash memory programming or erase operation has terminated normally. To read Flash Status Register 2, write the Read Status Register command (H’7070) to any address of the internal flash memory. Next,
read any address of the internal flash memory, and Flash Status Register 2 (FSTAT2) will be read out.
START
Write the Read Status Register
command (H'7070) to any address
of the internal flash memory
Read any address of the
internal flash memory
END
Figure 6.5.12 Read Status Register Command
(7) Clear Status Register command
The Clear Status Register command clears the Flash Status Register 2 ERASE (erase status), WRERR1
(write status 1) and WRERR2 (write status 2) bits to "0". Write the Clear Status Register command (H’5050)
to any address of the internal flash memory, and Flash Status Register 2 is thereby initialized.
If an error occurs when programming or erasing the internal flash memory and the Flash Status Register 2
ERASE (erase status), WRERR1 (write status 1) or WRERR2 (write status 2) bit is set to "1", the next
programming or erase operation cannot be executed unless each status bit is cleared to "0".
START
Write the Clear Status Register command (H'5050)
to any address of the internal flash memory
END
Figure 6.5.13 Clear Status Register Command
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6.5 Programming the Internal Flash Memory
(8) Read Lock Bit Status command
The Read Lock Bit Status command is provided for checking whether a flash memory block is protected
against programming/erase operation. Write the Read Lock Bit Status command (H’7171) to any address of
the internal flash memory. Next, read the last even address of the flash memory block to be checked (see
Table 6.5.3, “M32182F3 Target Blocks and Specified Addresses”), and the read data shows whether the
target block is protected.
If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) in the read data both are "0", it means that the target
memory block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) both are "1", it means that the
target memory block is not protected.
START
Write the Read Lock Bit Status command
(H'7171) to any address of the
internal flash memory
Read the last even address of the
flash memory block to be checked
END
Figure 6.5.14 Read Lock Bit Status Command
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6.5 Programming the Internal Flash Memory
Lock Bit Status Register (FLBST)
b0
1
2
3
4
5
6
7
8
FLBST0
?
?
9
10
11
12
13
14
?
?
?
?
?
b15
FLBST1
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0
No function assigned.
1
FLBST0
Lock bit 0
2–8
No function assigned.
9
FLBST1
Lock bit 1
Function
R
W
?
–
0: Protected
1: Not protected
R
–
?
–
R
–
?
–
0: Protected
1: Not protected
(Same content as FLBST0 is output)
10–15
No function assigned.
The Lock Bit Status Register is a read-only register, which is included for each memory block independently of
one another. The following shows how the lock bits in this register are set.
a) Setting the lock bit to "0" (protected)
Issue the Lock Bit Program command (H’7777) to the memory block to be protected.
b) Setting the lock bit to "1" (not protected)
Set the Flash Control Register 2 FPROT bit to invalidate protection by a lock bit, then issue the Block Erase
command (H’2020) or Erase All Unlocked Blocks command (H’A7A7) to erase the memory block which is to
be unprotected. This is the only way to set the lock bit to "1". In no way can the lock bit alone be set to "1".
c) Lock bit status after reset
Because the lock bits are nonvolatile, they are unaffected by a reset and power-off.
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6.5 Programming the Internal Flash Memory
6.5.4 Flash Programming Time (Reference)
The following shows the time needed to program internal flash memory for reference.
(1) Time required for transfer by SIO (for a transfer data size of 384 KB)
1/57,600 bps × 1 (frame) × 11 (number of bits transferred) × 384 KB = approx. 75.1 [s]
(2) Time required for programming the flash memory
384 KB / 256-byte block × 8 ms = approx. 12.3 [s]
(3) Time required for erasing the entire area
50 ms × 9 (blocks) = approx. 450 [ms]
(4) Total flash programming time (entire 384 KB area)
When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very
short compared to the serial communication time. Therefore, the total flash programming time can be calculated using the equation below.
(1) + (3) = approx. 76 [s]
If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest
programming time possible can be calculated using the equation below.
(2) + (3) = approx. 13 [s]
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6.6 Virtual Flash Emulation Function
6.6 Virtual Flash Emulation Function
The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into
areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the
Virtual Flash Emulation Function.
This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the contents of
internal flash memory at the addresses specified by the Virtual Flash S Bank Register. That way, the relevant RAM
data can read out by reading the content of internal flash memory.
For applications that require modifying the contents of internal flash memory (e.g., data table) during operation,
this function enables dynamic data modification by modifying the relevant RAM data.
The RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual RAM.
This function, when used in combination with the microcomputer’s internal Real-Time Debugger (RTD), allows the
data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facilitating data table tuning from an external device.
Note: • Before programming/erasing the internal flash memory, always be sure to exit this virtual flash
emulation mode.
H'0080 4000
(Cannot be used for
virtual flash emulation)
H'0080 8000
RAM bank block 0
(FESBANK0)
4 Kbytes
H'0080 9000
RAM bank block 1
(FESBANK1)
4 Kbytes
H'0080 A000
RAM bank block 2
(FESBANK2)
4 Kbytes
H'0080 B000
RAM bank block 3
(FESBANK3)
4 Kbytes
H'0080 C000
RAM bank block 4
(FESBANK4)
4 Kbytes
H'0080 D000
RAM bank block 5
(FESBANK5)
4 Kbytes
H'0080 E000
RAM bank block 6
(FESBANK6)
4 Kbytes
H'0080 F000
RAM bank block 7
(FESBANK7)
4 Kbytes
Internal RAM area
H'0081 0000
(Cannot be used for
virtual flash emulation)
H'0081 3FFF
Figure 6.6.1 Internal RAM Bank Configuration of the M32182F3
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6.6 Virtual Flash Emulation Function
6.6.1 Virtual Flash Emulation Area
The following shows the internal flash memory areas in which the Virtual Flash Emulation Function is applicable.
Using the Virtual Flash S Bank Register (FESBANK0–FESBANK7), select one among all S banks of internal
flash memory that are divided in 4-Kbyte units (by setting the eight start address bits A12–A19 of the desired S
bank in the Virtual Flash S Bank Register SBANKAD bits). Then set the Virtual Flash S Bank Register’s flash
emulation enable bit (MODENS) to "1", and the selected S bank area will be replaced with 4-Kbyte blocks of the
internal RAM beginning with the address H’0080 8000, up to eight such blocks in all.
Notes: • If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0–
FESBANK7) and each register’s flash emulation enable bit (MODENS) is set to "1" (enabled), the
bank is assigned the corresponding internal RAM area (4-Kbyte) according to the priority of Virtual
Flash S Bank Registers given below.
FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 >
FESBANK6 > FESBANK7
• During virtual flash emulation mode, RAM can be accessed for read and write from both the
internal RAM area and the flash emulation areas set in the internal flash memory.
• Before reading any flash emulation area after setting the Flash Control Register 1 (FCNT1) flash
emulation mode bit (FEMMOD) to "1", be sure to check that the flash emulation mode bit
(FEMMOD) has been set to "1" by reading it once.
• Before reading any flash emulation area after setting the Virtual Flash S Bank Register
(FESBANK0–FESBANK7) flash emulation enable bit (MODENS) and bank address bits
(SBANKAD), be sure to check that those MODENS and SBANKAD bits have been set to the
intended values by reading them once.
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6.6 Virtual Flash Emulation Function
<Internal flash>
H'0000 0000
H'0000 1000
H'0000 2000
H'0005 D000
H'0005 E000
H'0005 F000
S bank 0
(4 Kbytes)
<Internal RAM>
H'0080 4000
S bank 1
(4 Kbytes)
S bank 2
(4 Kbytes)
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
S bank 93
(4 Kbytes)
S bank 94
(4 Kbytes)
S bank 95
(4 Kbytes)
H'0080 8000
H'0080 9000
H'0080 A000
H'0080 B000
H'0080 C000
H'0080 D000
H'0080 E000
H'0080 F000
H'0081 3FFF
Notes: • If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0-FESBANK7) and each register's flash
emulation enable bit (MODENS) is set to 1, the bank is assigned the corresponding internal RAM area in order of priority:
FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7.
• If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Register is accessed, its corresponding internal RAM area
is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and
the flash emulation areas set in the internal flash memory.
Figure 6.6.2 Virtual Flash Emulation Area of the M32182F3
<Internal flash>
H'0000 0000
H'0000 1000
H'0000 2000
H'000F D000
H'000F E000
H'000F F000
S bank 0
(4 Kbytes)
<Internal RAM>
H'0080 4000
S bank 1
(4 Kbytes)
S bank 2
(4 Kbytes)
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
S bank 253
(4 Kbytes)
S bank 254
(4 Kbytes)
S bank 255
(4 Kbytes)
H'0080 8000
H'0080 9000
H'0080 A000
H'0080 B000
H'0080 C000
H'0080 D000
H'0080 E000
H'0080 F000
H'0081 3FFF
Notes: • If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0-FESBANK7) and each register's flash
emulation enable bit (MODENS) is set to 1, the bank is assigned the corresponding internal RAM area in order of priority:
FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7.
• If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Register is accessed, its corresponding internal RAM area
is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and
the flash emulation areas set in the internal flash memory.
Figure 6.6.3 Virtual Flash Emulation Area of the M32182F8
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S bank
Start address of S bank
in flash memory
Values set in S bank
address (SBANKAD) bits
S bank 0
H'0000 0000
(Note 1)
H'00
S bank 1
H'0000 1000
(Note 1)
H'01
S bank 2
H'0000 2000
(Note 1)
H'02
S bank 94
H'0005 E000
(Note 1)
H'5E
S bank 95
H'0005 F000
(Note 1)
H'5F
Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units
in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits.
Figure 6.6.4 Values Set in the M32182F3’s Virtual Flash S Bank Register
S bank
Start address of S bank
in flash memory
Values set in S bank
address (SBANKAD) bits
S bank 0
H'0000 0000
(Note 1)
H'00
S bank 1
H'0000 1000
(Note 1)
H'01
S bank 2
H'0000 2000
(Note 1)
H'02
S bank 254
H'000F E000
(Note 1)
H'FE
S bank 255
H'000F F000
(Note 1)
H'FF
Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units
in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits.
Figure 6.6.5 Values Set in the M32182F8’s Virtual Flash S Bank Register
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6.6 Virtual Flash Emulation Function
6.6.2 Entering Virtual Flash Emulation Mode
To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1".
After entering virtual flash emulation mode, set the Virtual Flash S Bank Register MODENS bit to "1" to enable
the Virtual Flash Emulation Function.
Even during virtual flash emulation mode, the internal RAM area (H’0080 8000 through H’0080 FFFF) can be
accessed the same way as in usual internal RAM.
Settings start
Write flash data to RAM
Enter virtual flash emulation mode
FEMMOD ← 1
Set RAM location address in
Virtual Flash S Bank Register
SBANKADn ← Address A12–A19
Enable virtual flash emulation
MODENS ← 1
Settings completed
Figure 6.6.6 Virtual Flash Emulation Mode Sequence
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6.6 Virtual Flash Emulation Function
6.6.3 Application Example of Virtual Flash Emulation Mode
By using two RAM areas that have been set in the same flash area by the Virtual Flash Emulation Function, the
data in the flash memory can be replaced successively.
(1) Operation when reset
Flash memory
Bank xx
Replace area
Initial value
RAM block 0
Data write to RAM0
RAM block 1
(2) Programming operation using RAM block 0
Flash memory
Replaced
Bank xx
RAM block 0
Initial value
Bank xx specified
RAM block 0
RAM block 1
Data write to RAM1
(3) Programming operation switched from RAM block 0 to RAM block 1
Flash memory
Replaced
Bank xx
Initial value
RAM block 0
RAM block 1
Bank xx specified
Bank xx specified
(settings invalid)
RAM block 0
RAM block 1
Figure 6.6.7 Application Example of Virtual Flash Emulation Mode (1/2)
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INTERNAL MEMORY
6
6.6 Virtual Flash Emulation Function
(4) Programming operation using RAM block 1
Flash memory
Replaced
Bank xx
Initial value
RAM block 0
RAM block 1
(Bank specification cleared)
Data write to RAM0
Bank xx specified
RAM block 1
(5) Programming operation switched from RAM block 1 to RAM block 0
Flash memory
Replaced
Bank xx
Initial value
RAM block 0
RAM block 1
Bank xx specified
Bank xx specified
(settings invalid)
RAM block 0
RAM block 1
(6) Go to (2)
Note: Enclosed in
are the valid area.
Figure 6.6.8 Application Example of Virtual Flash Emulation Mode (2/2)
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INTERNAL MEMORY
6
6.7 Connecting to A Serial Programmer
6.7 Connecting to A Serial Programmer
For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose
serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial
programmer, as shown below.
Table 6.7.1 Processing Microcomputer Pins before Using a Serial Programmer
Pin Name
Pin No.
Function
Remark
SCLKI1
103
Transfer clock input
Need to be pulled high
RXD1
104
Serial data input (received data)
Need to be pulled high
TXD1
105
Serial data output (transmit data)
P84
106
Transmit/receive enable output
Need to be pulled high
FP
111
Flash memory protect
Connect to the main power supply
MOD0
112
Operation mode 0
Connect to the main power supply
MOD1
113
Operation mode 1
Connect to ground
RESET#
19
Reset
After setting MOD0/MOD1, ground and
back to main power supply
JTRST
26
JTAG reset
Pull low via resistor
XIN
16
Clock input
XOUT
18
Clock output
VCNT
14
Control input for PLL circuit
OSC-VCC
15
PLL circuit power supply
Connect to the main power supply
OSC-VSS
17
PLL circuit ground
Connect to ground
VREF0
38
Reference voltage input for A-D
converter
Connect to the main power supply
AVCC0
37
Analog power supply
Connect to the main power supply
AVSS0
47
Analog ground
Connect to ground
VDDE
117
RAM backup power supply
Connect to the main power supply
VCCE
13,58,101,119
Main power supply
5 V + - 10% or 3.3 V + - 10%
VCC-BUS
78,143
Bus power supply
Depends on the target system
EXCVCC
EXCVDD
59,116
114
Internal power supply
Need to be grounded to earth via
bypass capacitor
VSS
56,57,77,102,115,118,144
Ground
0V
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INTERNAL MEMORY
6
6.7 Connecting to A Serial Programmer
The diagram below shows an example of a user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the internal flash memory in clocksynchronized serial mode. No communication problems associated with the oscillator frequency may occur. If the
system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse
effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the
internal flash memory needs to be protected, set any ID in this area.
User system board
Connect to the VCCE (5 or 3.3 V)
power supply rail
VCCE
VDDE
OSC-VCC
AVCC0
Connect to
Main power supply the user
Connect to the
system power
VCCE (5 or 3.3V) supply rail
power supply rail
VREF0
EXCVCC
EXCVDD
Flash programmer signals
Connector
VCC-BUS
Main power supply
(for reference)
RxD (input)
P85/TXD1
TxD (output)
SCLK0 (output)
P86/RXD1
P87/SCLKI1/SCLKO1
BUSY (input)
P84/SCLKI0/SCLKO0
MOD0
MOD0 (output)
FP (output)
RESET (output)
FP
RESET#
GND (common)
VSS
AVSS0
OSC-VSS
To system circuit
MOD1
JTRST
2kW
Set microcomputer
operating conditions
XIN
XOUT
VCNT
32182
Notes: • Turn on the power for the user system before writing to the internal flash memory.
• If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration.
• SBI# must be fixed high or low to ensure that no interrupts will be generated.
• The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition.
• The typical pullup resistance values of P84, P86 and P87 are 4.7 to 10 KW.
• The status of any other ports that are not shown here will not affect flash memory programming.
• Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes
while rewriting the internal flash memory.
Figure 6.7.1 Pin Connection Diagram
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INTERNAL MEMORY
6
6.8 Internal Flash Memory Protect Function
6.8 Internal Flash Memory Protect Function
The internal flash memory has the following four types of protect functions to prevent it from being inadvertently
rewritten or illegally copied, programmed or erased.
(1) Flash memory protect ID
When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emulator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID
is entered, no programming/erase operations can be performed. (For some tools, tool execution is enabled after
erasing the entire flash memory area, and the internal flash memory becomes accessible for write.)
(2) Protection by FP pin
The internal flash memory is protected in hardware against programming/erase operation by pulling the FP
(Flash Protect) pin low. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)’s FPMOD (external FP pin status) bit in the flash write/erase program, the internal flash memory can
also be protected in software. For systems that do not require protection by setting external pins, the FP pin may
be fixed high to simplify the operation to program/erase the internal flash memory.
(3) Protection by FENTRY bit
Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)’s FENTRY (flash
mode entry) bit is set to "1". To set the FENTRY bit to "1", write "0" and then "1" in succession while the FP pin
is high.
(4) Protection by a lock bit
Any block of internal flash memory can be protected by setting the lock bit provided for it to "0". That memory
block is disabled against programming/erase operation.
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6
INTERNAL MEMORY
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory
The following describes precautions to be taken when programming/erasing the internal flash memory.
• When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode
transitions during programming/erase operation may cause the chip to break down, make sure the mode setting
pin/power supply voltages do not fluctuate to prevent unintended changes of modes.
• If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be
taken to prevent adverse effects on the system when the tool is connected.
• If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set
any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 008F).
• If the internal flash memory does not need to be protected while using a general-purpose programming/erase
tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 008F) with H’FF.
• If the Flash Status Register 2 (FSTAT2)’s each error status is to be cleared (initialized to H’80) by resetting the
Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register 1 (FSTAT1) FSTAT
bit = "1" (ready) before clearing the error status.
• Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0", check to see that the Flash
Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) or the Flash Status Register 2 (FSTAT2) FBUSY bit = "1"
(ready).
• Do not clear the FENTRY bit if the Flash Control Register 1 (FCNT1) FENTRY bit = "1" and the Flash Status
Register 1 (FSTAT1) FSTAT bit = "0" (busy), or the Flash Status Register 2 (FSTAT2) FBUSY bit = "0" (being
programmed or erased).
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6
INTERNAL MEMORY
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory
This page is blank for reasons of layout.
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32182 Group User’s Manual (Rev.1.0)
CHAPTER 7
RESET
7.1
7.2
7.3
7.4
Outline of Reset
Reset Operation
Internal State Immediately after Reset
Things to Be Considered after Reset
RESET
7
7.1 Outline of Reset
7.1 Outline of Reset
The microcomputer is reset by applying a low-level signal to the RESET# input pin. The microcomputer is gotten
out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in
the Program Counter (PC) and the CPU starts executing from the reset vector entry.
7.2 Reset Operation
When a low-level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the
RESET# pin, the microcomputer is reset. At this time, pins on the microcomputer are reset (see the Pin State
When Reset in Table 1.4.1, “Pin Assignments”), and an internal bus hold request signal is output internally. Furthermore, the internal circuits (including the CPU) are reset 9–10 BCLK periods later.
When the RESET# input is returned high, the microcomputer pins get out of a reset state and the internal bus hold
request is deasserted 17–18 BCLK periods later. Then the internal circuits get out of a reset state 15 BCLK
periods after that.
Flip-flop
Counter
Pin reset signal
RESET#
Noise Canceller
S
R
OVF
Internal circuit reset signal
Figure 7.2.1 Reset Circuit
Extended for a duration during which
the RESET# input is held low
Duration needed for
noise cancellation (Note 1)
RESET# pin
200ns
Reset signal (internal signal)
past the noise canceller
17–18BCLK
Pin reset (Note 2) and
internal bus hold request
(internal signal)
15BCLK
Internal circuit reset
(internal signal)
9–10BCLK
Note 1: If the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller.
Note 2: The port-related registers also are reset.
Figure 7.2.2 Reset Sequence
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32180 Group User’s Manual (Rev.1.0)
RESET
7
7.2 Reset Operation
7.2.1 Reset at Power-on
When powering on the microcomputer, hold the RESET# signal input pin low until the rated power supply voltage is reached and the microcomputer’s internal x8 clock generator becomes oscillating stably.
7.2.2 Reset during Operation
To reset the microcomputer during operation, hold the RESET# signal input pin low for more than 200 ns.
7.2.3 Reset at Entering RAM Backup Mode
To prevent the RAM access by the CPU or DMA from becoming interrupted by a reset, first an internal bus hold
request is output internally after accepting the reset input. Then the internal circuits are reset after the internal
bus is placed in a hold state.
Note: • Reset input at entering RAM backup mode cannot be used in the following cases (because the
internal bus hold request may not be accepted and the RAM contents may be corrupted):
• When the lock bit = 1 (see Section 2.7, “Supplementary Explanation for BSET, BCLR, LOCK
and UNLOCK Instruction Execution”)
• When executing any instruction present in external memory
7.2.4 Reset Vector Relocation during Flash Programming
When entering the boot mode, the reset vector entry address is relocated to the start address (H'8000 0000) of
the boot program space. For details, see Section 6.5, “Programming the Internal Flash Memory.”
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RESET
7
7.3 Internal State Immediately after Reset
7.3 Internal State Immediately after Reset
The table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. For
details about the initial register state of each internal peripheral I/O, see each section in this manual in which the
relevant internal peripheral I/O is described.
Table 7.3.1 Internal State Immediately after Reset
Register
State after Reset
PSW
(CR0)
B'0000 0000 0000 0000 ??00 000? 0000 0000
(BSM, BIE, BC bits = undefined)
CBR
(CR1)
H'0000 0000 (C bits = 0)
SPI
(CR2)
Undefined
SPU
(CR3)
Undefined
BPC
(CR6)
Undefined
FPSR
(CR7)
H'0000 0100
(Only DN bit = 1)
PC
H'0000 0000
(Executed beginning with the address H’0000 0000) (Note 1)
R0–R15
Undefined
ACC (accumulator)
Undefined
RAM
Undefined when reset at power-on. (However, if the RAM is gotten out of reset after
returning from backup mode, it retains the content it had before being reset.)
Note 1: When in boot mode, the CPU executes the boot program.
7.4 Things to Be Considered after Reset
• Input/output ports
After reset, the microcomputer’s input/output ports are disabled against input in order to prevent current from
flowing through the port. To use any ports in input mode, set the Port Input Special Function Control Register
(PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, “Input/Output Port Related Registers.”
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32180 Group User’s Manual (Rev.1.0)
CHAPTER 8
INPUT/OUTPUT PORTS
AND PIN FUNCTIONS
8.1
8.2
8.3
8.4
8.5
8.6
Outline of Input/Output Ports
Selecting Pin Functions
Input/Output Port Related Registers
Port Input Level Switching Function
Port Peripheral Circuits
Precautions on Input/Output Ports
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.1 Outline of Input/Output Ports
8.1 Outline of Input/Output Ports
The 32182 has a total of 97 input/output ports from P0-P13, P15, P17 and P22 (except P5, which is reserved for
future use). These input/output ports can be used as input or output ports by setting the respective direction
registers.
Each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or
extended external bus signal line. Pin functions are selected depending on the current operation mode or by
setting the input/output port operation mode registers. (If any internal peripheral I/O has still another function, it is
also necessary to set the register provided for that peripheral I/O.)
The microcomputer also has a port input function enable bit that can be used to prevent current from flowing into
the input ports. This helps to simplify the software and hardware processing to be performed immediately after
reset or during flash programming. Note that before any ports can be used in input mode, this port input function
enable bit must be set accordingly.
The input/output ports are outlined below.
Table 8.1.1 Outline of Input/Output Ports
Item
Specification
Number of ports
Total 97 ports
Port function
P0
:
P00–P07
(8 ports)
P1
:
P10–P17
(8 ports)
P2
:
P20–P27
(8 ports)
P3
:
P30–P37
(8 ports)
P4
:
P41–P47
(7 ports)
P6
:
P61–P63
(3 ports)
P7
:
P70–P77
(8 ports)
P8
:
P82–P87
(6 ports)
P9
:
P93–P97
(5 ports)
P10
:
P100–P107
(8 ports)
P11
:
P110–P117
(8 ports)
P12
:
P124–P127
(4 ports)
P13
:
P130–P137
(8 ports)
P15
:
P150, P153
(2 ports)
P17
:
P174, P175
(2 ports)
P22
:
P220, P221, P224, P225
(4 ports)
The input/output ports can individually be set for input or output mode using the direction control register
provided for each input/output port. (However, P221 is input-only port.)
Pin function
Shared with peripheral I/O or extended external signals to serve dual-functions (or shared with two or
more peripheral I/O functions to serve triple-functions)
Pin function
P0–P4, P224, P225: Depends on the CPU operation mode (that is set by MOD0 and MOD1 pins). (Note 1)
selection
P6–P22: As set by each input/output port’s operation mode register.
(However, peripheral I/O pin functions are selected by peripheral I/O registers.)
Note 1: If the CPU operation mode is external extension mode, P0–P3, P44–P47, P224 and P225 initially are input/output
port pins, and are switched to extended external signal pin functions by setting the respective port operation mode
registers. P41–P43, when in external extension mode, serve as dedicated external bus interface signal pins.
Note: • P14, P16, P18-P21 are nonexist.
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.2 Selecting Pin Functions
8.2 Selecting Pin Functions
Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external
bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are
selected depending on the current operation mode or by setting the input/output port operation mode registers.
P0–P4, P224 and P225, when the CPU is set to operate in processor mode, all are switched to serve as signal
pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins
are set (see the table below).
Table 8.2.1 CPU Operation Modes and P0–P4, P224 and P225 Pin Functions
MOD0
MOD1
Operation Mode
P0–P4, P224 and P225 Pin Function
VSS
VSS
Single-chip mode
Input/output port pin
VSS
VCCE
External extension mode
Input/output port pin or extended external signal pin (Note 1)
VCCE
VSS
Processor mode (FP pin = VSS)
Extended external signal pin
VCCE
VCCE
Reserved (use inhibited)
–
Note 1: P41–P43 serve as dedicated external bus interface signal pins.
Note: • VCCE and VSS are connected to 5 or 3.3 V and GND, respectively.
Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins
by setting the respective port operation mode registers. If any internal peripheral I/O has two or more pin functions,
use the register provided for that peripheral I/O to select the desired pin function.
Note that FP and MOD1 pin settings during internal flash memory programming do not affect the pin functions.
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.2 Selecting Pin Functions
CPU operation
mode settings
(Note 1)
0
1
2
3
4
5
6
7
P0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
P1
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
P2
A23
A24
A25
A26
A27
A28
A29
A30
P3
A15
A16
A17
A18
A19
A20
A21
A22
BLW# /
BLE#
BHW# /
BHE#
RD#
CS0#
CS1#
A13
A14
(P61)
(P62)
(P63)
WAIT#
HREQ#
HACK#
MOD0
MOD1
(Note 3)
(Note 3)
TXD0
RXD0
SCLKI0 /
SCLKO0
TXD1
RXD1
SCLKI1 /
SCLKO1
TO16
TO17
TO18
TO19
TO20
TO11
TO12
TO13
TO14
TO15
TO3
TO4
TO5
TO6
TO7
TCLK0
TCLK1
TCLK2
TCLK3
P4
(Reserved)
P5
P6
P7
P8
BCLK /
WR#
P9
P10
TO8
P11
TO0
TO9 /
TO10 /
TXD3(Note 2) CTX1(Note 2)
TO1
TO2
SBI#
(Note 3)
(P67)
RTDTXD RTDRXD RTDACK RTDCLK
P12
Input/output
port operation
mode setting
SCLKI4 / SCLKI5 /
SCLKO4 SCLKO5
P13
TIN16
TIN17
TIN18
TIN19
TIN20
TIN21 /
RXD3
TIN22 /
CRX1
TIN23
P14
TIN8
TIN9
TIN10
TIN11
TIN12
TIN13
TIN14
TIN15
P15
TIN0
TIN1
TIN2
TIN3
TIN4
TIN5
TIN6
TIN7
P16
TO21
TO22
TO23
TO24
TO25
TO26
TO27
TO28
TIN24
TIN25
TXD2
RXD2
TXD3
RXD3
P17
P18
TO29
TO30
TO31
TO32
TO33
TO34
TO35
TO36
P19
TIN26
TIN27
TIN28
TIN29
TIN30
TIN31
TIN32
TIN33/
PWMOFF2
P20
TXD4
RXD4
TXD5
RXD5
P21
TO37
TO38
TO39
TO40
TO41
TO42
TO43
TO44
P22
CTX0
CRX0
CTX1
CRX1
CS2#
CS3#
A11 /
A12 /
CS2#(Note 2)CS3#(Note 2)
(Note 1)
Note 1: During processor mode, these ports are switched to function as extended external signal pins. During external extension
mode, only P41-P43 are switched to function as external bus interface pins. Other pins become input/output port pins
when reset, so that some of these pins, if needed, must be set to function as external bus interface pins.
Note 2: These are triple-function pins. Their desired output function must be selected using the peripheral output select register.
Note 3: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from
these ports.
Note: • No pins are available for those in shaded sections
. However, because internal circuits are included, make sure
the ports are set for low-level output when initialized (to prevent current from flowing in through the port). These pins exist
in only the 32180 and are nonexistent in the 32182. However, P223 is an input-only pin and internally pulled high, so that
there is no need to set it for output.
Figure 8.2.1 Input/Output Ports and Pin Function Assignments
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
8.3 Input/Output Port Related Registers
The input/output port related registers included in the microcomputer consists of the port data register, port direction register and port operation mode register.
Note that P5 is reserved for future use. The tables below show an input/output port related register map.
Input/Output Port Related Register Map (1/2)
Address
+0 address
b0
H'0080 0700
H'0080 0702
H'0080 0704
H'0080 0706
H'0080 0708
H'0080 070A
H'0080 070C
H'0080 070E
H'0080 0710
H'0080 0712
H'0080 0714
H'0080 0716
P0 Data Register
(P0DATA)
P2 Data Register
(P2DATA)
P4 Data Register
(P4DATA)
P6 Data Register
(P6DATA)
P8 Data Register
(P8DATA)
P10 Data Register
(P10DATA)
P12 Data Register
(P12DATA)
P14 Data Register
(P14DATA)
P16 Data Register
(P16DATA)
P18 Data Register
(P18DATA)
P20 Data Register
(P20DATA)
P22 Data Register
(P22DATA)
|
H'0080 0720
H'0080 0722
H'0080 0724
H'0080 0726
H'0080 0728
H'0080 072A
H'0080 072C
H'0080 072E
H'0080 0730
H'0080 0732
H'0080 0734
H'0080 0736
|
+1 address
b7 b8
See pages
b15
P1 Data Register
(P1DATA)
P3 Data Register
(P3DATA)
(Use inhibited area)
P7 Data Register
(P7DATA)
P9 Data Register
(P9DATA)
P11 Data Register
(P11DATA)
P13 Data Register
(P13DATA)
P15 Data Register
(P15DATA)
P17 Data Register
(P17DATA)
P19 Data Register
(P19DATA)
P21 Data Register
(P21DATA)
(Use inhibited area)
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
8-7
(Use inhibited area)
P0 Direction Register
(P0DIR)
P2 Direction Register
(P2DIR)
P4 Direction Register
(P4DIR)
P6 Direction Register
(P6DIR)
P8 Direction Register
(P8DIR)
P10 Direction Register
(P10DIR)
P12 Direction Register
(P12DIR)
P14 Direction Register
(P14DIR)
P16 Direction Register
(P16DIR)
P18 Direction Register
(P18DIR)
P20 Direction Register
(P20DIR)
P22 Direction Register
(P22DIR)
P1 Direction Register
(P1DIR)
P3 Direction Register
(P3DIR)
(Use inhibited area)
P7 Direction Register
(P7DIR)
P9 Direction Register
(P9DIR)
P11 Direction Register
(P11DIR)
P13 Direction Register
(P13DIR)
P15 Direction Register
(P15DIR)
P17 Direction Register
(P17DIR)
P19 Direction Register
(P19DIR)
P21 Direction Register
(P21DIR)
(Use inhibited area)
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
8-8
(Use inhibited area)
Note: • Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176,
P177, P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the
port).
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
Input/Output Port Related Register Map (2/2)
Address
+0 address
+1 address
b0
H'0080 0740
H'0080 0742
H'0080 0744
H'0080 0746
H'0080 0748
H'0080 074A
H'0080 074C
H'0080 074E
H'0080 0750
H'0080 0752
H'0080 0754
H'0080 0756
|
H'0080 0760
H'0080 0762
H'0080 0764
|
H'0080 076A
|
H'0080 0776
b7 b8
P0 Operation Mode Register
(P0MOD)
P2 Operation Mode Register
(P2MOD)
P4 Operation Mode Register
(P4MOD)
P6 Operation Mode Register
(P6MOD)
P8 Operation Mode Register
(P8MOD)
P10 Operation Mode Register
(P10MOD)
P12 Operation Mode Register
(P12MOD)
P14 Operation Mode Register
(P14MOD)
P16 Operation Mode Register
(P16MOD)
P18 Operation Mode Register
(P18MOD)
P20 Operation Mode Register
(P20MOD)
P22 Operation Mode Register
(P22MOD)
See pages
b15
P1 Operation Mode Register
(P1MOD)
P3 Operation Mode Register
(P3MOD)
Port Input Special Function Control Register
(PICNT)
P7 Operation Mode Register
(P7MOD)
P9 Operation Mode Register
(P9MOD)
P11 Operation Mode Register
(P11MOD)
P13 Operation Mode Register
(P13MOD)
P15 Operation Mode Register
(P15MOD)
P17 Operation Mode Register
(P17MOD)
P19 Operation Mode Register
(P19MOD)
P21 Operation Mode Register
(P21MOD)
(Use inhibited area)
8-9
8-10
8-11
8-21
8-11
8-12
8-12
8-13
8-13
8-14
8-14
8-15
8-15
8-16
8-16
8-17
8-17
8-18
8-18
8-19
(Use inhibited area)
Port Group 0,1 Input Level Setting Register
Port Group 2,3 Input Level Setting Register
(PG01LEV)
(PG23LEV)
Port Group 4,5 Input Level Setting Register
Port Group 6,7 Input Level Setting Register
(PG45LEV)
(PG67LEV)
Port Group 8 Input Level Setting Register
(Use inhibited area)
(PG8LEV)
(Use inhibited area)
8-25
8-25
8-25
P10 Peripheral Output Select Register
(P10SMOD)
(Use inhibited area)
(Use inhibited area)
8-20
P22 Peripheral Output Select Register
(P22SMOD)
(Use inhibited area)
8-20
Note: • Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176,
P177, P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the
port).
8-6
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
8.3.1 Port Data Registers
P0 Data Register (P0DATA)
P1 Data Register (P1DATA)
P2 Data Register (P2DATA)
P3 Data Register (P3DATA)
P4 Data Register (P4DATA)
P6 Data Register (P6DATA)
P7 Data Register (P7DATA)
P8 Data Register (P8DATA)
P9 Data Register (P9DATA)
P10 Data Register (P10DATA)
P11 Data Register (P11DATA)
P12 Data Register (P12DATA)
P13 Data Register (P13DATA)
P14 Data Register (P14DATA)
P15 Data Register (P15DATA)
P16 Data Register (P16DATA)
P17 Data Register (P17DATA)
P18 Data Register (P18DATA)
P19 Data Register (P19DATA)
P20 Data Register (P20DATA)
P21 Data Register (P21DATA)
P22 Data Register (P22DATA)
b0
(b8
1
9
Pn0DT Pn1DT
?
?
2
10
3
11
Pn2DT Pn3DT
?
?
4
12
<Address: H’0080 0700>
<Address: H’0080 0701>
<Address: H’0080 0702>
<Address: H’0080 0703>
<Address: H’0080 0704>
<Address: H’0080 0706>
<Address: H’0080 0707>
<Address: H’0080 0708>
<Address: H’0080 0709>
<Address: H’0080 070A>
<Address: H’0080 070B>
<Address: H’0080 070C>
<Address: H’0080 070D>
<Address: H’0080 070E>
<Address: H’0080 070F>
<Address: H’0080 0710>
<Address: H’0080 0711>
<Address: H’0080 0712>
<Address: H’0080 0713>
<Address: H’0080 0714>
<Address: H’0080 0715>
<Address: H’0080 0716>
5
13
6
14
Pn4DT Pn5DT Pn6DT
?
?
?
b7
b15)
Pn7DT
?
n = 0–22 (not including P5)
<After reset: Undefined>
b
Bit Name
Function
R
W
0(b8)
Pn0DT (Port Pn0 data bit)
<At read>
R
W
1(b9)
Pn1DT (Port Pn1 data bit)
Depends on how the Port Direction Register is set
2(b10)
Pn2DT (Port Pn2 data bit)
If direction bit = "0" (input mode)
3(b11)
Pn3DT (Port Pn3 data bit)
0: Port input pin = "low"
4(b12)
Pn4DT (Port Pn4 data bit)
1: Port input pin = "high"
5(b13)
Pn5DT (Port Pn5 data bit)
If direction bit = "1" (output mode) (Note 1)
6(b14)
Pn6DT (Port Pn6 data bit)
0: Port output latch = "0" / Port pin level = "low"
7(b15)
Pn7DT (Port Pn7 data bit)
1: Port output latch = "1" / Port pin level = "high"
<At write>
Write to the port output latch
Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL).
Notes: • No data bits are provided for the following ports (read as "0", writing has no effect):
P40, P60, P90–P92, P120–P123, P170, P171, P204–P207
• The SBI# pin level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect.
• The MOD0 and MOD1 pin levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT
and P81DT bits has no effect.
• P221 is input-only port. Writing to the P221DT bit has no effect.
• Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176, P177,
P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make
sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port).
• Alhough no pins are available for P223, it is internally pulled high (read as "0", writing has no effect).
8-7
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
8.3.2 Port Direction Registers
P0 Direction Register (P0DIR)
P1 Direction Register (P1DIR)
P2 Direction Register (P2DIR)
P3 Direction Register (P3DIR)
P4 Direction Register (P4DIR)
P6 Direction Register (P6DIR)
P7 Direction Register (P7DIR)
P8 Direction Register (P8DIR)
P9 Direction Register (P9DIR)
P10 Direction Register (P10DIR)
P11 Direction Register (P11DIR)
P12 Direction Register (P12DIR)
P13 Direction Register (P13DIR)
P14 Direction Register (P14DIR)
P15 Direction Register (P15DIR)
P16 Direction Register (P16DIR)
P17 Direction Register (P17DIR)
P18 Direction Register (P18DIR)
P19 Direction Register (P19DIR)
P20 Direction Register (P20DIR)
P21 Direction Register (P21DIR)
P22 Direction Register (P22DIR)
b0
(b8
1
9
2
10
3
11
Pn0DR Pn1DR Pn2DR Pn3DR
0
0
0
0
4
12
<Address: H’0080 0720>
<Address: H’0080 0721>
<Address: H’0080 0722>
<Address: H’0080 0723>
<Address: H’0080 0724>
<Address: H’0080 0726>
<Address: H’0080 0727>
<Address: H’0080 0728>
<Address: H’0080 0729>
<Address: H’0080 072A>
<Address: H’0080 072B>
<Address: H’0080 072C>
<Address: H’0080 072D>
<Address: H’0080 072E>
<Address: H’0080 072F>
<Address: H’0080 0730>
<Address: H’0080 0731>
<Address: H’0080 0732>
<Address: H’0080 0733>
<Address: H’0080 0734>
<Address: H’0080 0735>
<Address: H’0080 0736>
5
13
6
14
b7
b15)
Pn4DR Pn5DR Pn6DR Pn7DR
0
0
0
0
n = 0–22 (not including P5)
<After reset: H’00>
b
Bit Name
Function
0(b8)
Pn0DR (Port Pn0 direction bit)
0: Input mode
1(b9)
Pn1DR (Port Pn1 direction bit)
1: Output mode
2(b10)
Pn2DR (Port Pn2 direction bit)
3(b11)
Pn3DR (Port Pn3 direction bit)
4(b12)
Pn4DR (Port Pn4 direction bit)
5(b13)
Pn5DR (Port Pn5 direction bit)
6(b14)
Pn6DR (Port Pn6 direction bit)
7(b15)
Pn7DR (Port Pn7 direction bit)
R
W
R
W
Notes: • No direction bits are provided for the following ports (read as 0, writing has no effect):
P40, P60, P64, P80, P81, P90–P92, P120–P123, P170, P171, P204–P207, P221, P223
• After reset, all ports are set for input mode.
• Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176, P177,
P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make
sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port).
8-8
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
8.3.3 Port Operation Mode Registers
P0 Operation Mode Register (P0MOD)
<Address: H’0080 0740>
b0
1
2
3
4
5
6
b7
P00MD
P01MD
P02MD
P03MD
P04MD
P05MD
P06MD
P07MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
P00MD
Port P00 operation mode bit
0: P00
1: DB0
R
W
1
P01MD
Port P01 operation mode bit
0: P01
1: DB1
R
W
2
P02MD
Port P02 operation mode bit
0: P02
1: DB2
R
W
R
W
3
P03MD
0: P03
Port P03 operation mode bit
1: DB3
4
P04MD
Port P04 operation mode bit
0: P04
1: DB4
R
W
5
P05MD
Port P05 operation mode bit
0: P05
1: DB5
R
W
R
W
R
W
6
7
P06MD
0: P06
Port P06 operation mode bit
1: DB6
P07MD
Port P07 operation mode bit
0: P07
1: DB7
Note: • P0 Operation Mode Register is useful only when the CPU operates in external extension mode.
P1 Operation Mode Register (P1MOD)
<Address: H’0080 0741>
b8
9
10
11
12
13
14
b15
P10MD
P11MD
P12MD
P13MD
P14MD
P15MD
P16MD
P17MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
P10MD
Port P10 operation mode bit
0: P10
1: DB8
R
W
9
P11MD
Port P11 operation mode bit
0: P11
1: DB9
R
W
10
P12MD
Port P12 operation mode bit
0: P12
1: DB10
R
W
11
P13MD
Port P13 operation mode bit
0: P13
1: DB11
R
W
12
P14MD
Port P14 operation mode bit
0: P14
1: DB12
R
W
13
P15MD
Port P15 operation mode bit
0: P15
1: DB13
R
W
14
P16MD
Port P16 operation mode bit
0: P16
1: DB14
R
W
15
P17MD
Port P17 operation mode bit
0: P17
1: DB15
R
W
Note: • P1 Operation Mode Register is useful only when the CPU operates in external extension mode.
8-9
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P2 Operation Mode Register (P2MOD)
<Address: H’0080 0742>
b0
1
2
3
4
5
6
b7
P20MD
P21MD
P22MD
P23MD
P24MD
P25MD
P26MD
P27MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
P20MD
Port P20 operation mode bit
0: P20
1: A23
R
W
1
P21MD
Port P21 operation mode bit
0: P21
1: A24
R
W
2
P22MD
Port P22 operation mode bit
0: P22
1: A25
R
W
R
W
3
P23MD
0: P23
Port P23 operation mode bit
1: A26
4
P24MD
Port P24 operation mode bit
0: P24
1: A27
R
W
5
P25MD
Port P25 operation mode bit
0: P25
1: A28
R
W
6
P26MD
Port P26 operation mode bit
0: P26
1: A29
R
W
7
P27MD
Port P27 operation mode bit
0: P27
1: A30
R
W
Note: • P2 Operation Mode Register is useful only when the CPU operates in external extension mode.
P3 Operation Mode Register (P3MOD)
<Address: H’0080 0743>
b8
9
10
11
12
13
14
b15
P30MD
P31MD
P32MD
P33MD
P34MD
P35MD
P36MD
P37MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
P30MD
Port P30 operation mode bit
0: P30
1: A15
R
W
9
P31MD
Port P31 operation mode bit
0: P31
1: A16
R
W
R
W
10
P32MD
0: P32
Port P32 operation mode bit
1: A17
11
P33MD
Port P33 operation mode bit
0: P33
1: A18
R
W
12
P34MD
Port P34 operation mode bit
0: P34
1: A19
R
W
13
P35MD
Port P35 operation mode bit
0: P35
1: A20
R
W
14
P36MD
Port P36 operation mode bit
0: P36
1: A21
R
W
15
P37MD
Port P37 operation mode bit
0: P37
1: A22
R
W
Note: • P3 Operation Mode Register is useful only when the CPU operates in external extension mode.
8-10
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P4 Operation Mode Register (P4MOD)
b0
1
2
3
0
0
0
0
<Address: H’0080 0744>
4
5
6
b7
P44MD
P45MD
P46MD
P47MD
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0–3
No function assigned. Fix to "0".
0
0
4
P44MD
Port P44 operation mode bit
0: P44
1: CS0#
R
W
5
P45MD
Port P45 operation mode bit
0: P45
1: CS1#
R
W
R
W
R
W
6
7
P46MD
0: P46
Port P46 operation mode bit
1: A13
P47MD
Port P47 operation mode bit
0: P47
1: A14
Note: • P4 Operation Mode Register is useful only when the CPU operates in external extension mode.
P6 Operation Mode Register (P6MOD)
b0
0
1
0
2
0
3
0
4
0
<Address: H’0080 0746>
5
6
P65MD
P66MD
0
0
b7
0
<After reset: H’00>
b
Bit Name
0–4
Function
R
W
No function assigned. Fix to "0".
0
0
5, 6
Fix to "0".
0
0
7
No function assigned. Fix to "0".
0
0
Notes: • Port P60 is nonexistent.
• P61–P63 are always input/output ports (single-function pins).
• Port P64 is the SBI# input-only pin. The pin level can be known by reading the data register for P64.
• Although no pins are available for P65 and P66, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port).
8-11
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P7 Operation Mode Register (P7MOD)
<Address: H’0080 0747>
b8
9
10
11
12
13
14
b15
P70MD
P71MD
P72MD
P73MD
P74MD
P75MD
P76MD
P77MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
P70MD
Port P70 operation mode bit
0: P70
1: BCLK/WR#
R
W
9
P71MD
Port P71 operation mode bit
0: P71
1: WAIT#
R
W
10
P72MD
Port P72 operation mode bit
0: P72
1: HREQ#
R
W
R
W
11
P73MD
0: P73
Port P73 operation mode bit
1: HACK#
12
P74MD
Port P74 operation mode bit
0: P74
1: RTDTXD
R
W
13
P75MD
Port P75 operation mode bit
0: P75
1: RTDRXD
R
W
14
P76MD
Port P76 operation mode bit
0: P76
1: RTDACK
R
W
15
P77MD
Port P77 operation mode bit
0: P77
1: RTDCLK
R
W
P8 Operation Mode Register (P8MOD)
b0
0
1
0
<Address: H’0080 0748>
2
3
4
5
6
b7
P82MD
P83MD
P84MD
P85MD
P86MD
P87MD
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0,1
No function assigned. Fix to "0".
2
P82MD
Port P82 operation mode bit
3
Function
R
W
0
0
0: P82
1: TXD0
R
W
P83MD
Port P83 operation mode bit
0: P83
1: RXD0
R
W
4
P84MD
Port P84 operation mode bit
0: P84
1: SCLKI0/SCLKO0
R
W
5
P85MD
Port P85 operation mode bit
0: P85
1: TXD1
R
W
6
P86MD
Port P86 operation mode bit
0: P86
1: RXD1
R
W
7
P87MD
Port P87 operation mode bit
0: P87
1: SCLKI1/SCLKO1
R
W
Note: • Ports P80 and P81 are nonexistent.
8-12
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P9 Operation Mode Register (P9MOD)
b8
0
9
10
0
0
<Address: H’0080 0749>
11
12
13
14
b15
P93MD
P94MD
P95MD
P96MD
P97MD
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8–10
No function assigned. Fix to "0".
0
0
11
P93MD
Port P93 operation mode bit
0: P93
1: TO16
R
W
12
P94MD
Port P94 operation mode bit
0: P94
1: TO17
R
W
R
W
13
P95MD
0: P95
Port P95 operation mode bit
1: TO18
14
P96MD
Port P96 operation mode bit
0: P96
1: TO19
R
W
15
P97MD
Port P97 operation mode bit
0: P97
1: TO20
R
W
Note: • Ports P90–P92 are nonexistent.
P10 Operation Mode Register (P10MOD)
<Address: H’0080 074A>
b0
1
2
3
4
5
6
b7
P100MD
P101MD
P102MD
P103MD
P104MD
P105MD
P106MD
P107MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
P100MD
0: P100
R
W
Port P100 operation mode bit
1: TO8
1
P101MD
Port P101 operation mode bit
0: P101
1: TO9/TXD3 (Note 1)
R
W
2
P102MD
Port P102 operation mode bit
0: P102
R
W
1: TO10/CTX1 (Note 1)
3
P103MD
Port P103 operation mode bit
0: P103
1: TO11
R
W
4
P104MD
0: P104
R
W
Port P104 operation mode bit
1: TO12
5
P105MD
Port P105 operation mode bit
0: P105
1: TO13
R
W
6
P106MD
Port P106 operation mode bit
0: P106
1: TO14
R
W
7
P107MD
Port P107 operation mode bit
0: P107
1: TO15
R
W
Note 1: These functions are selected using the P10 Peripheral Output Select Register.
8-13
32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P11 Operation Mode Register (P11MOD)
<Address: H’0080 074B>
b8
9
10
11
12
13
14
b15
P110MD
P111MD
P112MD
P113MD
P114MD
P115MD
P116MD
P117MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
P110MD
Port P110 operation mode bit
0: P110
1: TO0
R
W
9
P111MD
Port P111 operation mode bit
0: P111
1: TO1
R
W
10
P112MD
Port P112 operation mode bit
0: P112
1: TO2
R
W
R
W
11
P113MD
0: P113
Port P113 operation mode bit
1: TO3
12
P114MD
Port P114 operation mode bit
0: P114
1: TO4
R
W
13
P115MD
Port P115 operation mode bit
0: P115
1: TO5
R
W
14
P116MD
Port P116 operation mode bit
0: P116
1: TO6
R
W
15
P117MD
Port P117 operation mode bit
0: P117
1: TO7
R
W
P12 Operation Mode Register (P12MOD)
b0
0
1
0
2
0
3
0
<Address: H’0080 074C>
4
5
6
b7
P124MD
P125MD
P126MD
P127MD
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0–3
No function assigned. Fix to "0".
0
0
4
P124MD
Port P124 operation mode bit
0: P124
1: TCLK0
R
W
5
P125MD
Port P125 operation mode bit
0: P125
1: TCLK1
R
W
6
P126MD
Port P126 operation mode bit
0: P126
1: TCLK2
R
W
7
P127MD
Port P127 operation mode bit
0: P127
1: TCLK3
R
W
Note: • Ports P120–P123 are nonexistent.
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P13 Operation Mode Register (P13MOD)
<Address: H’0080 074D>
b8
9
10
11
12
13
14
b15
P130MD
P131MD
P132MD
P133MD
P134MD
P135MD
P136MD
P137MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
P130MD
Port P130 operation mode bit
0: P130
1: TIN16
R
W
9
P131MD
Port P131 operation mode bit
0: P131
1: TIN17
R
W
10
P132MD
Port P132 operation mode bit
0: P132
1: TIN18
R
W
R
W
11
P133MD
0: P133
Port P133 operation mode bit
1: TIN19
12
P134MD
Port P134 operation mode bit
0: P134
1: TIN20
R
W
13
P135MD
Port P135 operation mode bit
0: P135
1: TIN21/RXD3 (Note 1)
R
W
14
P136MD
Port P136 operation mode bit
0: P136
1: TIN22/CRX1 (Note 1)
R
W
15
P137MD
Port P137 operation mode bit
0: P137
1: TIN23
R
W
Note 1: Both inputs are enabled.
P14 Operation Mode Register (P14MOD)
<Address: H’0080 074E>
b0
1
2
3
4
5
6
b7
P140MD
P141MD
P142MD
P143MD
P144MD
P145MD
P146MD
P147MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0-7
Fix to "0".
Function
R
W
0
0
Note : • Although no pins are available for P140 to P147, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port).
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P15 Operation Mode Register (P15MOD)
<Address: H’0080 074F>
b8
9
10
11
12
13
14
b15
P150MD
P151MD
P152MD
P153MD
P154MD
P155MD
P156MD
P157MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
P150MD
Port P150 operation mode bit
0: P150
1: TIN0
R
W
0
0
0: P153
1: TIN3
R
W
0
0
9, 10
Fix to "0".
11
P153MD
Port P153 operation mode bit
12-15
Fix to "0".
Note : • Although no pins are available for P151, P152 and P154-P157, because internal circuits are included, make sure the ports
are set for low-level output when initialized (to prevent current from flowing in through the port).
P16 Operation Mode Register (P16MOD)
<Address: H’0080 0750>
b0
1
2
3
4
5
6
b7
P160MD
P161MD
P162MD
P163MD
P164MD
P165MD
P166MD
P167MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0-7
Fix to "0".
Function
R
W
0
0
Note : • Although no pins are available for P160 to P167, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port).
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P17 Operation Mode Register (P17MOD)
b8
0
9
0
<Address: H’0080 0751>
10
11
12
13
14
b15
P172MD
P173MD
P174MD
P175MD
P176MD
P177MD
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
8, 9
No function assigned. Fix to "0".
10, 11
Fix to "0".
12
P174MD
Port P174 operation mode bit
13
14, 15
R
W
0
0
0
0
0: P174
1: TXD2
R
W
P175MD
0: P175
R
W
Port P175 operation mode bit
1: RXD2
0
0
Fix to "0".
Notes: • Ports P170 and P171 are nonexistent.
• Although no pins are available for P172, P173, P176 and P177, because internal circuits are included, make sure the ports
are set for low-level output when initialized (to prevent current from flowing in through the port).
P18 Operation Mode Register (P18MOD)
<Address: H’0080 0752>
b0
1
2
3
4
5
6
b7
P180MD
P181MD
P182MD
P183MD
P184MD
P185MD
P186MD
P187MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0-7
Fix to "0".
Function
R
W
0
0
Note : • Although no pins are available for P180 to P187, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port).
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P19 Operation Mode Register (P19MOD)
<Address: H’0080 0753>
b8
9
10
11
12
13
14
b15
P190MD
P191MD
P192MD
P193MD
P194MD
P195MD
P196MD
P197MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–15
Fix to "0"
Function
R
W
0
0
Note : • Although no pins are available for P190 to P197, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port).
P20 Operation Mode Register (P20MOD)
b0
1
2
3
P200MD
P201MD
P202MD
P203MD
0
0
0
0
<Address: H’0080 0754>
4
5
6
b7
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0–3
Fix to "0".
0
0
4–7
No function assigned. Fix to "0".
0
0
Notes : • Although no pins are available for P200 to P203, because internal circuits are included, make sure the ports are set for low
level output when initialized (to prevent current from flowing in through the port).
• Ports P204–P207 are nonexistent.
P21 Operation Mode Register (P21MOD)
<Address: H’0080 0755>
b8
9
10
11
12
13
14
b15
P210MD
P211MD
P212MD
P213MD
P214MD
P215MD
P216MD
P217MD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–15
Fix to "0".
Function
R
W
0
0
Note : • Although no pins are available for P210 to P217, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port).
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
P22 Operation Mode Register (P22MOD)
b0
1
P220MD
0
0
<Address: H’0080 0756>
2
3
4
5
6
b7
P222MD
P223MD
P224MD
P225MD
P226MD
P227MD
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
P220MD
Port P220 operation mode bit
0: P220
1: CTX0
R
W
1
No function assigned. Fix to "0".
0
0
2, 3
Fix to "0".
0
0
4
P224MD
0: P224
R
W
Port P224 operation mode bit (Note 1)
1: A11/CS2# (Note 2)
5
P225MD
Port P225 operation mode bit (Note 1)
0: P225
1: A12/CS3# (Note 2)
R
W
6, 7
Fix to "0".
0
0
Note 1: Port P224, P225 operation mode bits are useful only when the CPU operates in external extension mode.
Note 2: These functions are selected using the P22 Peripheral Output Select Register.
Notes: • P221 is the CAN input-only pin.
• Although no pins are available for P222, P223, P226 and P227, because internal circuits are included, make sure the ports
are set for low-level output when initialized (to prevent current from flowing in through the port). Port 223 is an input-only pin
so that there is no need to set it for output.
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
8.3.4 Port Peripheral Output Select Registers
P10 Peripheral Output Select Register (P10SMOD)
b0
1
2
3
4
5
6
b7
0
P101
SMD
0
P102
SMD
0
0
0
0
0
0
<Address: H’0080 076A>
<After reset: H’00>
b
Bit Name
Function
0
No function assigned. Fix to "0".
1
P101SMD
Port P101 peripheral output select mode bit
2
P102SMD
Port P102 peripheral output select mode bit
3–7
No function assigned. Fix to "0".
R
W
0
0
0: TO9
1: TXD3
R
W
0: TO10
1: CTX1
R
W
0
0
P22 Peripheral Output Select Register (P22SMOD)
b0
0
1
0
2
0
3
4
5
6
b7
0
P224
SMD
0
P225
SMD
0
0
0
<Address: H’0080 0776>
<After reset: H’00>
b
Bit Name
Function
R
W
0–3
No function assigned. Fix to "0".
0
0
4
P224SMD
Port P224 peripheral output select mode bit
0: A11
1: CS2#
R
W
5
P225SMD
Port P225 peripheral output select mode bit
0: A12
1: CS3#
R
W
6–7
No function assigned. Fix to "0".
0
0
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
8.3.5 Port Input Special Function Control Register
Port Input Special Function Control Register (PICNT)
b8
9
10
11
12
13
XSTAT
0
0
0
0
0
0
14
b15
PISEL
PIEN0
0
0
<Address: H’0080 0745>
<After reset: H’00>
b
Bit Name
8–10
No function assigned. Fix to "0".
11
XSTAT
XIN oscillation status bit
12–13
No function assigned. Fix to "0".
14
15
Function
R
W
0
0
0: XIN oscillating
1: XIN inactive
R(Note 1)
PISEL
0: Content of port output latch
Port input data select bit
1: Port pin level
PIEN0
0: Disable input
Port input enable bit
1: Enable input
0
0
R
W
R
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
(1) XSTAT (XIN oscillation status) bit (Bit 11)
1) Conditions under which XSTAT is set to "1"
XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for
a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped.
When operating normally, XIN changes state (high or low) once every BCLK period.
2) Conditions under which XSTAT is cleared to "0"
XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set in (1)
above, the former has priority. Writing "1" to XSTAT is ignored.
3) Method for using XSTAT to detect XIN oscillation stoppage
Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscillation has stopped.
By reading XSTAT without clearing it never once after reset, it is possible to know whether XIN has ever
stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0", it
is possible to know the current oscillating status of XIN. (However, there must be an interval of at least 5
BCLK periods (20 CPU clock periods) between read and write.)
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
(1) To know whether XIN oscillation has ever stopped after being reset
Read XSTAT
(2) To know the current status of XIN oscillation
Write XSTAT = 0
Wait before inspecting XSTAT
Wait for 20 CPU
clock periods or more
Read XSTAT
Figure 8.3.1 Procedure for Setting XSTAT
(2) PISEL (Port input data select) bit (Bit 14)
When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data
Register. This bit is unaffected by the Port Operation Mode Register.
Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register
Direction Register
PISEL Settings
Target Data to Be Read
0 (input)
0/1
Port pin level
1 (output)
0
Port output latch
1
Port pin level
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.3 Input/Output Port Related Registers
(3) PIEN0 (Port input enable) bit (Bit 15)
This bit is used to prevent current from flowing into the port input pins.
Because the input/output ports are disabled against input after reset, if any ports need to be used in input
mode they must be enabled for input by setting this bit to "1".
When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has
a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled
pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the low-level input on it.
The following shows the procedure for selecting a peripheral input function.
(1) Enable the port for input when its pin level is valid (high or low)
(2) Select a function using the port operation mode bit
During boot mode, the pins shared with serial I/O functions are enabled for input and can therefore be
protected against current flowing in from the pins other than serial I/O functions during flash programming by
clearing PIEN0.
The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode.
Table 8.3.2 Pins Controllable by PIEN0 Bit
Mode Name
Single-chip
External extension
Microprocessor
Boot
(single-chip)
Controllable Pins
Uncontrolled Pins
P00–P07, P10–P17, P20–P27
P30–P37, P41–P47, P61–P63
P65–P67, P70–P77, P82–P87
P93–P97, P100–P107, P110–P117
P124–P127, P130–P137, P140–P147
P150–P157, P160–P167, P172–P177
P180–P187, P190–P197, P200–P203
P210–P217, P220, P222, P224–P227
P221, P223,
FP, MOD0, MOD1, SBI#, RESET#
P61–P63, P65–P67, P70–P77
P82–P87, P93–P97, P100–P107
P110–P117, P124–P127, P130–P137
P140–P147, P150–P157, P160–P167
P172–P177, P180–P187, P190–P197
P200–P203, P210–P217, P220, P222
P00–P07, P10–P17
P20–P27, P30–P37
P41–P47, P221, P223–P227
FP, MOD0, MOD1, SBI#, RESET#
P00–P07, P10–P17, P20–P27
P30–P37, P41–P47, P61–P63
P67, P70–P77, P93–P97
P100, P102–P107, P110–P117, P124–P127
P130–P134, P137, P140–P147, P150–P157
P160–P167, P172–P173, P180–P187
P190–P197, P210–P217, P220
P222, P224–P227
P65, P66, P82–P87, P101
P135–P136, P174–P177, P200–P203
P221, P223,
FP, MOD0, MOD1, SBI#, RESET#
Note : • No pins are available for P65-P67, P140-P147, P151, P152, P154-P157, P160-P167, P172, P173, P176, P177,
P180-P187, P190-P197, P200-P203, P210-P217, P222, P223, P226 and P227.
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.4 Port Input Level Switching Function
8.4 Port Input Level Switching Function
The port input level switching function allows the port threshold to be switched to one of three voltage levels (with
or without Schmitt as selected) in units of the following port group.
Port group 0
Port group 3
Port group 4
32182 Group
Port group 5
Port group 6
Port group 6
Port group 7
Port group 7
Port group 8
Port group 0
Port group 8
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
P97/TO20
P117/TO7
P116/TO6
P115/TO5
P114/TO4
P113/TO3
P112/TO2
P111/TO1
P110/TO0
P127/TCLK3
P126/TCLK2
P125/TCLK1
P124/TCLK0
EXCVCC
VCCE
VSS
VSS
SBI#
P63
P62
P61
AD0IN11
AD0IN10
AD0IN9
AD0IN8
AVSS0
AD0IN7
AD0IN6
AD0IN5
AD0IN4
AD0IN3
AD0IN2
AD0IN1
AD0IN0
VREF0
AVCC0
P150/TIN0
P153/TIN3
P130/TIN16
P131/TIN17
P132/TIN18
P133/TIN19
P134/TIN20
P135/TIN21/RXD3
P136/TIN22/CRX1
P137/TIN23
P220/CTX0
P221/CRX0
VCCE
VCNT
OSC-VCC
XIN
OSC-VSS
XOUT
RESET#
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
JTDI
JTDO
JTRST
JTCK
JTMS
P100/TO8
P101/TO9/TXD3
P102/TO10/CTX1
P103/TO11
P104/TO12
P105/TO13
P106/TO14
P107/TO15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P174/TXD2
P175/RXD2
FP
MOD0
MOD1
EXCVDD
VSS
EXCVCC
VDDE
VSS
VCCE
P17/DB15
P16/DB14
P15/DB13
P14/DB12
P13/DB11
P12/DB10
P11/DB9
P10/DB8
P07/DB7
P06/DB6
P05/DB5
P04/DB4
P03/DB3
P02/DB2
P01/DB1
P00/DB0
P73/HACK#
P72/HREQ#
P71/WAIT#
P70/BCLK/WR#
P43/RD#
P42/BHW#/BHE#
P41/BLW#/BLE#
VCC-BUS
VSS
Port group 1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
VSS
VCCE
P44/CS0#
P45/CS1#
P224/A11/CS2#
P225/A12/CS3#
P46/A13
P47/A14
P30/A15
P31/A16
P32/A17
P33/A18
P34/A19
P35/A20
P36/A21
P37/A22
P20/A23
P21/A24
P22/A25
P23/A26
P24/A27
P25/A28
P26/A29
P27/A30
VCC-BUS
VSS
P93/TO16
P94/TO17
P95/TO18
P96/TO19
Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224-P227
Group 1: P65–P67, P82–P87, P172–P177
Group 2: P160–P167, P210–P217
Group 3: P93–P97, P110–P117
Group 4: P124–P127, P140–P147, P190–P197
Group 5: P61–P63, SBI#
Group 6: P74–P77, P180–P187, P100–P107
Group 7: P136, P220–P223
Group 8: P130–P135, P137, P150–P157, P200–P203
Figure 8.4.1 Port Input Level Switching Groups
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.4 Port Input Level Switching Function
Port Group 0,1 Input Level Setting Register (PG01LEV)
b0
1
2
3
4
5
6
<Address: H’0080 0760>
b7
WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1
0
0
0
1
0
0
0
1
Port Group 2,3 Input Level Setting Register (PG23LEV)
b8
9
10
11
12
13
14
<Address: H’0080 0761>
b15
WF2SEL PT2SEL VT2SEL0 VT2SEL1 WF3SEL PT3SEL VT3SEL0 VT3SEL1
0
0
0
1
0
0
0
1
Port Group 4,5 Input Level Setting Register (PG45LEV)
b0
1
2
3
4
5
6
<Address: H’0080 0762>
b7
WF4SEL PT4SEL VT4SEL0 VT4SEL1 WF5SEL PT5SEL VT5SEL0 VT5SEL1
0
0
0
1
0
0
0
1
Port Group 6,7 Input Level Setting Register (PG67LEV)
b8
9
10
11
12
13
14
<Address: H’0080 0763>
b15
WF6SEL PT6SEL VT6SEL0 VT6SEL1 WF7SEL PT7SEL VT7SEL0 VT7SEL1
0
0
0
1
0
0
0
1
Port Group 8 Input Level Setting Register (PG8LEV)
b0
1
2
3
4
5
6
b7
0
0
0
0
<Address: H’0080 0764>
WF8SEL PT8SEL VT8SEL0 VT8SEL1
0
0
0
1
Note: • The PG8LEV register bits 4–7 have no functions assigned.
<After reset: B’0001>
b
Bit Name
Function
R
W
0(4)
8(12)
WFnSEL
Group n dual-function input select bit
0: Select standard input for each pin
1: Select threshold switching function
R
W
1(5)
9(13)
PTnSEL
Group n port input select bit
0: Select CMOS input
1: Select Schmitt input
R
W
2–3
(6–7)
10–11
(14–15)
VTnSEL
Group n input threshold select bit
<When PTnSEL = "0" (CMOS input selected)>
00: Select 0.35 VCCE
01: Select 0.5 VCCE
10: Select 0.7 VCCE
11: Settings inhibited
<When PTnSEL = "1" (Schmitt input selected)>
00: VT+ = 0.5 VCCE
VT– = 0.35 VCCE
01: Settings inhibited
10: VT+ = 0.7 VCCE
VT– = 0.35 VCCE
11: VT+ = 0.7 VCCE
VT– = 0.5VCCE
R
W
Notes: • The following ports operate with the VCC-BUS power supply, and not with the VCCE power supply. Therefore, the
reference voltages for these ports are the VCC-BUS input voltage.
P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224–P227
• No pins are available for P65-P67, P140-P147, P151, P152, P154-P157, P160-P167, P172, P173, P176, P177, P180P187, P190-P197, P200-P203, P210-P217, P222, P223, P226 and P227.
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.4 Port Input Level Switching Function
0.7VCCE
S
VT+
S
VT-
Schmitt
0.5VCCE
Pin
Port input
S
Input function enable
0.35VCCE
Threshold
S
CMOS
PTnSEL
VTnSELL
Standard input level for each peripheral function pin
S
Peripheral function
input
WFnSEL
Figure 8.4.2 Port Level Switching Function
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.5 Port Peripheral Circuits
8.5 Port Peripheral Circuits
Figures 8.5.1 through 8.5.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages.
P00–P07(DB0–DB7)
P10–P17(DB8–DB15)
P20–P27(A23–A30)
P30–P37(A15–A22)
P46, P47(A13, A14)
P71(WAIT#)
P73(HACK#)
P74(RTDTXD)
P76(RTDACK)
P224(A11/CS2#)
P225(A12/CS3#)
Direction register
Data bus
Port output latch
Input data select bit
Operation mode register
(Note 1)
Port level
switching function
(Standard:
peripheral TTL)
Peripheral function input
Input function
enable
P44(CS0#)
P45(CS1#)
P70(BCLK/WR#)
P82(TXD0)
P85(TXD1)
P93–P97(TO16–TO20)
P100(TO8)
P103–P107(TO11–TO15)
P110–P117(TO0–TO7)
P174(TXD2)
P220(CTX0)
Direction register
Data bus
Port output latch
Input data select bit
Operation mode register
(Note 1)
Port level switching
function (No
peripheral input)
Peripheral function output
Input function
enable
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function."
Notes: • During processor mode, P00-P07, P10-P17, P20-P27, P30-P37, P45-P47, P224, and P225 are external bus
interface control signal pins, but their functional description in this block diagram is omitted.
• Although P224 and P225 serve triple functions, their functional description in this block diagram is omitted.
• The circle denotes a pin.
• The symbol
denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the
VCCE voltage.
• The input capacitance of each pin is approximately 10 pF.
Figure 8.5.1 Port Peripheral Circuit Diagram (1)
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.5 Port Peripheral Circuits
P101(TO9/TXD3)
P102(TO10/CTX1)
Direction register
Data bus
Port output latch
Input data select bit
Operation mode register
(Note 1)
Port level switching
function (No
peripheral input)
Peripheral output
select register
Input function
enable
Peripheral function output 1
Peripheral function output 2
P72(HREQ#)
P75(RTDRXD)
P77(RTDCLK)
P83(RXD0)
P86(RXD1)
P124–P127(TCLK0–TCLK3)
P130–P134(TIN16–TIN20)
P137(TIN23)
P150, P153(TIN0, TIN3)
P175(RXD2)
Direction register
Data bus
Port output latch
Input data select bit
(Note 1)
Port level switching
function (Standard:
peripheral Schmitt)
Operation mode register
Peripheral function input
Input function
enable
P135(TIN21/RXD3)
P136(TIN22/CRX1)
Direction register
Data bus
Port output latch
Input data select bit
(Note 1)
Port level switching
function (Standard:
peripheral Schmitt)
Operation mode register
Peripheral function input 1
Peripheral function input 2
Input function
enable
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function."
Notes: • The circle denotes a pin.
• The symbol
denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage.
• The input capacitance of each pin is approximately 10 pF.
Figure 8.5.2 Port Peripheral Circuit Diagram (2)
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.5 Port Peripheral Circuits
P41(BLW#/BLE#)
P42(BHW#/BHE#)
P43(RD#)
P61-P63
Direction register
Data bus
Port output latch
Input data select bit
(Note 1)
Port level switching
function (No
peripheral input)
Input function
enable
Direction register
Data bus
Port output latch
Input data select bit
P84(SCLKI0/SCLKO0)
P87(SCLKI1/SCLKO1)
Operation mode register
UART/CSIO function
select bit
Internal/external clock
select bit
(Note 1)
Port level switching
function (Standard:
peripheral Schmitt)
SCLKOi output
SCLKIi input
Input function
enable
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function."
Notes: • During processor and external extension modes, P41-P43 are external bus interface control signal pins, but their
functional description in this block diagram is omitted.
• The circle denotes a pin.
• The symbol
denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage.
• The input capacitance of each pin is approximately 10 pF.
Figure 8.5.3 Port Peripheral Circuit Diagram (3)
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32182 Group User’s Manual (Rev.1.0)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.5 Port Peripheral Circuits
SBI#
P221(CRX0)
Data bus
Port level switching
function (Standard:
peripheral Schmitt)
SBI#, CRX0
MOD0, MOD1
FP
JTDI, JTCK, JTMS
Output control
JTDO
RESET#, XIN, JTRST
OSC-VCC,
VCCE, VDDE
VCC-BUS,
EXCVCC, EXCVDD
AD0IN0–12,
VREF0,
XOUT
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function."
Notes: • The circle denotes a pin.
• The symbol
denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed
the VCCE voltage.
Figure 8.5.4 Port Peripheral Circuit Diagram (4)
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8
8.6 Precautions on Input/Output Ports
8.6 Precautions on Input/Output Ports
• When using input/output ports in output mode
Because the value of the Port Data Register is undefined after reset, the Port Data Register must have its initial
value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register
is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value
until any data is written into it.
• About the port input disable function
Because the input/output ports are disabled against input after reset, they must be enabled for input by setting
the Port Input Enable (PIEN0) bit to "1" before their input functions can be used.
When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a
low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin)
while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due
to the low-level input on it.
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32182 Group User’s Manual (Rev.1.0)
8
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.6 Precautions on Input/Output Ports
This page is blank for reasons of layout.
8-32
32182 Group User’s Manual (Rev.1.0)
CHAPTER 9
DMAC
9.1
9.2
9.3
9.4
Outline of the DMAC
DMAC Related Registers
Functional Description of the DMAC
Precautions about the DMAC
DMAC
9
9.1 Outline of the DMAC
9.1 Outline of the DMAC
The microcomputer internally contains a 10-channel DMAC (Direct Memory Access Controller). It allows data to
be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or
between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O.
Table 9.1.1 Outline of the DMAC
Item
Description
Number of channels
10 channels
Transfer request sources • Software trigger
• Request from internal peripheral I/Os: A-D converter, multijunction timer, serial I/O (reception
completed, transmit buffer empty) or CAN
• DMA channels can be cascaded (Note 1)
Maximum number of
65,536 times
times transferred
Transferable address
• 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF)
space
• Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and
between internal RAMs are supported.
Transfer data size
16 or 8 bits
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dualaddress transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination:
• Address fixed
• Address incremental
• Ring buffered
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9
(Priority is fixed)
Maximum transfer rate
13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz)
Interrupt request
Group interrupt request can be generated when each transfer count register underflows.
Transfer area
64 Kbytes from H’0080 0000 to H’0080 FFFF (Note 2)
Note 1: The DMA channels can be cascaded in the manner described below.
• Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0
• Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count
register)
• Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1
• Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2
• Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2
• Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3
• Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5
• Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6
• Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7
• Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7
• Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8
Note 2: Address space from H'0081 0000 to H'0081 3FFF cannot be transferred into the internal RAM area.
9-2
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.1 Outline of the DMAC
Input event bus
Output event bus
3 2 1 0
0 1 2 3
AD0 conversion
completed
TIO8_udf
TIN0S
S
AD0 conversion
completed
TIO8_udf
S
Software
start
DMA0
udf
end
DMA1
udf
end
DMA2
udf
end
DMA3
udf
end
DMA4
udf
end
CAN0_S0/S15
TIN3S
S
Software start
S
TIN18S
Software start
S
SIO0_TXD
SIO1_RXD
Software start
S
SIO0_RXD
Software start
S
CAN0_S1/S14
S
TIN0S
S
TIN19S
SIO0_TXD
S
TIN20S
DMA0–4
interrupt
Software start
S
SIO1_RXD
SIO2_RXD
S
DMA5
udf
end
DMA6
udf
end
DMA7
udf
end
DMA8
udf
end
DMA9
udf
end
SIO1_TXD
S
Software start
S
SIO3_TXD
SIO2_TXD
S
S
Software start
SIO3_RXD
Software start
S
S
SIO3_TXD
S
Software start
3 2 1 0
S
DMA5–9
interrupt
0 1 2 3
Figure 9.1.1 Block Diagram of the DMAC
9-3
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
9.2 DMAC Related Registers
The diagram below shows a memory map of the DMAC related registers.
DMAC Related Register Map (1/2)
Address
+0 address
b0
H'0080 0400
|
H'0080 0408
|
H'0080 0410
H'0080 0412
H'0080 0414
H'0080 0416
H'0080 0418
H'0080 041A
H'0080 041C
H'0080 041E
H'0080 0420
H'0080 0422
H'0080 0424
H'0080 0426
H'0080 0428
H'0080 042A
H'0080 042C
H'0080 042E
H'0080 0430
H'0080 0432
H'0080 0434
H'0080 0436
H'0080 0438
H'0080 043A
H'0080 043C
H'0080 043E
+1 address
See pages
b7 b8
b15
DMA0–4 Interrupt Request Status Register
DMA0–4 Interrupt Request Mask Register
(DM04ITST)
(DM04ITMK)
(Use inhibited area)
9-24
9-25
DMA5–9 Interrupt Request Status Register
DMA5–9 Interrupt Request Mask Register
(DM59ITST)
(DM59ITMK)
(Use inhibited area)
9-24
9-25
DMA0 Channel Control Register 0
DMA0 Channel Control
(DM0CNT0)
(DM0CNT1)
DMA0 Source Address Register
(DM0SA)
DMA0 Destination Address Register
(DM0DA)
DMA0 Transfer Count Register
(DM0TCT)
DMA5 Channel Control Register 0
DMA5 Channel Control
(DM5CNT0)
(DM5CNT1)
DMA5 Source Address Register
(DM5SA)
DMA5 Destination Address Register
(DM5DA)
DMA5 Transfer Count Register
(DM5TCT)
DMA1 Channel Control Register 0
DMA1 Channel Control
(DM1CNT0)
(DM1CNT1)
DMA1 Source Address Register
(DM1SA)
DMA1 Destination Address Register
(DM1DA)
DMA1 Transfer Count Register
(DM1TCT)
DMA6 Channel Control Register 0
DMA6 Channel Control
(DM6CNT0)
(DM6CNT1)
DMA6 Source Address Register
(DM6SA)
DMA6 Destination Address Register
(DM6DA)
DMA6 Transfer Count Register
(DM6TCT)
DMA2 Channel Control Register 0
DMA2 Channel Control
(DM2CNT0)
(DM2CNT1)
DMA2 Source Address Register
(DM2SA)
DMA2 Destination Address Register
(DM2DA)
DMA2 Transfer Count Register
(DM2TCT)
DMA7 Channel Control Register 0
DMA7 Channel Control
(DM7CNT0)
(DM7CNT1)
DMA7 Source Address Register
(DM7SA)
DMA7 Destination Address Register
(DM7DA)
DMA7 Transfer Count Register
(DM7TCT)
9-4
Register 1
9-6
9-19
9-20
9-21
Register 1
9-11
9-19
9-20
9-21
Register 1
9-7
9-19
9-20
9-21
Register 1
9-12
9-19
9-20
9-21
Register 1
9-8
9-19
9-20
9-21
Register 1
9-13
9-19
9-20
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32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMAC Related Register Map (2/2)
Address
+0 address
b0
H'0080 0440
H'0080 0442
H'0080 0444
H'0080 0446
H'0080 0448
H'0080 044A
H'0080 044C
H'0080 044E
H'0080 0450
H'0080 0452
H'0080 0454
H'0080 0456
H'0080 0458
H'0080 045A
H'0080 045C
H'0080 045E
H'0080 0460
H'0080 0462
H'0080 0464
H'0080 0466
H'0080 0468
|
H'0080 0470
H'0080 0472
H'0080 0474
H'0080 0476
H'0080 0478
+1 address
See pages
b7 b8
b15
DMA3 Channel Control Register 0
DMA3 Channel Control
(DM3CNT0)
(DM3CNT1)
DMA3 Source Address Register
(DM3SA)
DMA3 Destination Address Register
(DM3DA)
DMA3 Transfer Count Register
(DM3TCT)
DMA8 Channel Control Register 0
DMA8 Channel Control
(DM8CNT0)
(DM8CNT1)
DMA8 Source Address Register
(DM8SA)
DMA8 Destination Address Register
(DM8DA)
DMA8 Transfer Count Register
(DM8TCT)
DMA4 Channel Control Register 0
DMA4 Channel Control
(DM4CNT0)
(DM4CNT1)
DMA4 Source Address Register
(DM4SA)
DMA4 Destination Address Register
(DM4DA)
DMA4 Transfer Count Register
(DM4TCT)
DMA9 Channel Control Register 0
DMA9 Channel Control
(DM9CNT0)
(DM9CNT1)
DMA9 Source Address Register
(DM9SA)
DMA9 Destination Address Register
(DM9DA)
DMA9 Transfer Count Register
(DM9TCT)
DMA0 Software Request Generation Register
(DM0SRI)
DMA1 Software Request Generation Register
(DM1SRI)
DMA2 Software Request Generation Register
(DM2SRI)
DMA3 Software Request Generation Register
(DM3SRI)
DMA4 Software Request Generation Register
(DM4SRI)
(Use inhibited area)
DMA5 Software Request Generation
(DM5SRI)
DMA6 Software Request Generation
(DM6SRI)
DMA7 Software Request Generation
(DM7SRI)
DMA8 Software Request Generation
(DM8SRI)
DMA9 Software Request Generation
(DM9SRI)
9-5
Register 1
9-9
9-19
9-20
9-21
Register 1
9-14
9-19
9-20
9-21
Register 1
9-10
9-19
9-20
9-21
Register 1
9-15
9-19
9-20
9-21
9-18
9-18
9-18
9-18
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
Register
9-18
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
9.2.1 DMA Channel Control Registers
DMA0 Channel Control Register 0 (DM0CNT0)
b0
1
2
MDSEL0 TREQF0
0
0
3
0
4
TENL0
REQSL0
0
5
6
<Address: H’0080 0410>
b7
TSZSL0 SADSL0 DADSL0
0
0
0
0
<After reset: H’00>
b
Bit Name
R
W
0
MDSEL0
DMA0 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF0
DMA0 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL0
DMA0 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL0
0: Disable transfer
R
W
DMA0 transfer enable bit
1: Enable transfer
5
TSZSL0
DMA0 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL0
DMA0 source address direction select bit
0: Fixed
1: Increment
R
W
DADSL0
0: Fixed
R
W
DMA0 destination address direction select bit
1: Increment
7
Function
Software start or one DMA2 transfer completed
A-D0 conversion completed
MJT (TIO8_udf)
Extended DMA0 transfer request source select
(DMA0 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA0 Channel Control Register 1 (DM0CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0411>
b15
REQESEL0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL0
Extended DMA0 transfer request source select bit
Function
0000: MJT (input event bus 2)
0001: Settings inhibited
0010: CAN (CAN0_S0/S15)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
|
|
R
W
0
0
R
W
1111: Settings inhibited
9-6
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA1 Channel Control Register 0 (DM1CNT0)
b0
1
2
MDSEL1 TREQF1
0
0
3
0
4
TENL1
REQSL1
0
5
6
<Address: H’0080 0420>
b7
TSZSL1 SADSL1 DADSL1
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL1
DMA1 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF1
DMA1 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL1
DMA1 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL1
0: Disable transfer
R
W
DMA1 transfer enable bit
1: Enable transfer
5
TSZSL1
DMA1 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL1
DMA1 source address direction select bit
0: Fixed
1: Increment
R
W
7
DADSL1
0: Fixed
R
W
DMA1 destination address direction select bit
1: Increment
Software start
MJT (output event bus 0)
Settings inhibited
Extended DMA1 transfer request source select
(DMA1 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA1 Channel Control Register 1 (DM1CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0421>
b15
REQESEL1
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL1
Extended DMA1 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
One DMA0 transfer completed
MJT(TIN3S)
Settings inhibited
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-7
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA2 Channel Control Register 0 (DM2CNT0)
b0
1
2
MDSEL2 TREQF2
0
0
3
REQSL2
0
0
4
5
TENL2
TSZSL2
0
0
6
<Address: H’0080 0430>
b7
SADSL2 DADSL2
0
0
<After reset: H’00>
b
Bit Name
R
W
0
MDSEL2
DMA2 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF2
DMA2 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL2
DMA2 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL2
0: Disable transfer
R
W
DMA2 transfer enable bit
1: Enable transfer
5
TSZSL2
DMA2 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL2
DMA2 source address direction select bit
0: Fixed
1: Increment
R
W
DADSL2
0: Fixed
R
W
DMA2 destination address direction select bit
1: Increment
7
Function
Software start
MJT (output event bus 1)
MJT (TIN18S)
Extended DMA2 transfer request source select
(DMA2 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA2 Channel Control Register 1 (DM2CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0431>
b15
REQESEL2
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL2
Extended DMA2 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
One DMA1 transfer completed
Settings inhibited
CAN(CAN0_S1/S14)
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-8
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA3 Channel Control Register 0 (DM3CNT0)
b0
1
2
MDSEL3 TREQF3
0
0
3
REQSL3
0
0
4
5
TENL3
TSZSL3
0
0
6
<Address: H’0080 0440>
b7
SADSL3 DADSL3
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL3
DMA3 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF3
DMA3 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL3
DMA3 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL3
0: Disable transfer
R
W
DMA3 transfer enable bit
1: Enable transfer
5
TSZSL3
DMA3 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL3
DMA3 source address direction select bit
0: Fixed
1: Increment
R
W
7
DADSL3
0: Fixed
R
W
DMA3 destination address direction select bit
1: Increment
Software start
SIO0_TXD (transmit buffer empty)
SIO1_RXD
Extended DMA3 transfer request source select
(DMA3 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA3 Channel Control Register 1 (DM3CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0441>
b15
REQESEL3
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL3
Extended DMA3 transfer request source select bit
Function
0000: MJT(TIN0)
0001: One DMA2 transfer completed
0010: Settings inhibited
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
|
|
R
W
0
0
R
W
1111: Settings inhibited
9-9
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA4 Channel Control Register 0 (DM4CNT0)
b0
1
2
MDSEL4 TREQF4
0
0
3
REQSL4
0
0
4
5
TENL4
TSZSL4
0
0
6
<Address: H’0080 0450>
b7
SADSL4 DADSL4
0
0
<After reset: H’00>
b
Bit Name
R
W
0
MDSEL4
DMA4 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF4
DMA4 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL4
DMA4 transfer request source select bit
00: Software start
01: One DMA3 transfer completed
10: SIO0_RXD
11: Extended DMA4 transfer request source select
(DMA4 Channel Control Register 1)
R
W
4
TENL4
0: Disable transfer
R
W
DMA4 transfer enable bit
1: Enable transfer
5
TSZSL4
DMA4 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL4
DMA4 source address direction select bit
0: Fixed
1: Increment
R
W
DADSL4
0: Fixed
R
W
DMA4 destination address direction select bit
1: Increment
7
Function
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA4 Channel Control Register 1 (DM4CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0451>
b15
REQESEL4
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL4
Extended DMA4 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
MJT(TIN19S)
SIO0_TXD (transmit buffer empty)
Settings inhibited
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-10
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA5 Channel Control Register 0 (DM5CNT0)
b0
1
2
MDSEL5 TREQF5
0
0
3
REQSL5
0
0
<Address: H’0080 0418>
4
5
6
b7
TENL5
TSZSL5
SADSL5
DADSL5
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL5
DMA5 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF5
DMA5 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL5
DMA5 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL5
0: Disable transfer
R
W
DMA5 transfer enable bit
1: Enable transfer
5
TSZSL5
DMA5 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL5
DMA5 source address direction select bit
0: Fixed
1: Increment
R
W
7
DADSL5
0: Fixed
R
W
DMA5 destination address direction select bit
1: Increment
Software start or one DMA7 transfer completed
All DMA0 transfers completed
SIO2_RXD
Extended DMA5 transfer request source select
(DMA5 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA5 Channel Control Register 1 (DM5CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0419>
b15
REQESEL5
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL5
Extended DMA5 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
MJT(TIN20S)
Settings inhibited
Settings inhibited
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-11
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA6 Channel Control Register 0 (DM6CNT0)
b0
1
2
MDSEL6 TREQF6
0
0
3
0
4
TENL6
REQSL6
0
5
6
<Address: H’0080 0428>
b7
TSZSL6 SADSL6 DADSL6
0
0
0
0
<After reset: H’00>
b
Bit Name
R
W
0
MDSEL6
DMA6 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF6
DMA6 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL6
DMA6 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL6
0: Disable transfer
R
W
DMA6 transfer enable bit
1: Enable transfer
5
TSZSL6
DMA6 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL6
DMA6 source address direction select bit
0: Fixed
1: Increment
R
W
DADSL6
0: Fixed
R
W
DMA6 destination address direction select bit
1: Increment
7
Function
Software start
SIO1_TXD (transmit buffer empty)
Settings inhibited
Extended DMA6 transfer request source select
(DMA6 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA6 Channel Control Register 1 (DM6CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0429>
b15
REQESEL6
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL6
Extended DMA6 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
One DMA5 transfer completed
Settings inhibited
SIO1_RXD
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-12
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA7 Channel Control Register 0 (DM7CNT0)
b0
1
2
MDSEL7 TREQF7
0
0
3
REQSL7
0
0
4
5
TENL7
TSZSL7
0
0
6
<Address: H’0080 0438>
b7
SADSL7 DADSL7
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL7
DMA7 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF7
DMA7 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL7
DMA7 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL7
0: Disable transfer
R
W
DMA7 transfer enable bit
1: Enable transfer
5
TSZSL7
DMA7 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL7
DMA7 source address direction select bit
0: Fixed
1: Increment
R
W
7
DADSL7
0: Fixed
R
W
DMA7 destination address direction select bit
1: Increment
Software start
SIO2_TXD (transmit buffer empty)
Settings inhibited
Extended DMA7 transfer request source select
(DMA7 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA7 Channel Control Register 1 (DM7CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0439>
b15
REQESEL7
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL7
Extended DMA7 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
One DMA6 transfer completed
Settings inhibited
SIO3_TXD (transmit buffer empty)
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-13
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA8 Channel Control Register 0 (DM8CNT0)
b0
1
2
MDSEL8 TREQF8
0
0
3
REQSL8
0
0
4
5
TENL8
TSZSL8
0
0
6
<Address: H’0080 0448>
b7
SADSL8 DADSL8
0
0
<After reset: H’00>
b
Bit Name
R
W
0
MDSEL8
DMA8 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF8
DMA8 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL8
DMA8 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL8
0: Disable transfer
R
W
DMA8 transfer enable bit
1: Enable transfer
5
TSZSL8
DMA8 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL8
DMA8 source address direction select bit
0: Fixed
1: Increment
R
W
DADSL8
0: Fixed
R
W
DMA8 destination address direction select bit
1: Increment
7
Function
Software start
MJT (input event bus 0)
SIO3_RXD
Extended DMA8 transfer request source select
(DMA8 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA8 Channel Control Register 1 (DM8CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0449>
b15
REQESEL8
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL8
Extended DMA8 transfer request source select bit
Function
0000: Settings inhibited
0001: Settings inhibited
0010: One DMA7 transfer completed
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
|
|
R
W
0
0
R
W
1111: Settings inhibited
9-14
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
DMA9 Channel Control Register 0 (DM9CNT0)
b0
1
2
MDSEL9 TREQF9
0
0
3
0
4
TENL9
REQSL9
0
5
6
<Address: H’0080 0458>
b7
TSZSL9 SADSL9 DADSL9
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL9
DMA9 transfer mode select bit
0: Normal mode
1: Ring buffer mode
R
W
1
TREQF9
DMA9 transfer request flag bit
0: Transfer not requested
1: Transfer requested
R(Note 1)
2, 3
REQSL9
DMA9 transfer request source select bit
00:
01:
10:
11:
R
W
4
TENL9
0: Disable transfer
R
W
DMA9 transfer enable bit
1: Enable transfer
5
TSZSL9
DMA9 transfer size select bit
0: 16 bits
1: 8 bits
R
W
6
SADSL9
DMA9 source address direction select bit
0: Fixed
1: Increment
R
W
7
DADSL9
0: Fixed
R
W
DMA9 destination address direction select bit
1: Increment
Software start
SIO3_TXD (transmit buffer empty)
Settings inhibited
Extended DMA9 transfer request source select
(DMA9 Channel Control Register 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA9 Channel Control Register 1 (DM9CNT1)
b8
9
10
11
12
13
14
<Address: H’0080 0459>
b15
REQESEL9
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
REQESEL9
Extended DMA9 transfer request source select bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
|
One DMA8 transfer completed
Settings inhibited
Settings inhibited
Common 1) MJT (input event bus 1)
Common 2) MJT (input event bus 3)
Common 3) MJT (output event bus 2)
Common 4) MJT (output event bus 3)
Common 5) AD0 conversion completed
Common 6) MJT (TIN0S)
Common 7) MJT (TIO8_udf)
Settings inhibited
|
R
W
0
0
R
W
1111: Settings inhibited
9-15
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the
DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as
those to set the transfer size and the source/destination address directions.
[DMnCNT0 Register]
(1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0)
When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting
this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode.
In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control
is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer
Count Register counts in free-run mode, during which time transfer operation is continued until the transfer enable
bit is reset to "0" (to disable transfer). In ring buffer mode, no interrupt is generated at completion of DMA transfer.
(2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1)
This flag is set to "1" when a DMA transfer request occurs, and is cleared to "0" when the transfer for that
transfer request is completed. Reading this flag helps to know DMA transfer requests on each channel.
Writing "0" to this bit clears the generated DMA transfer request. Writing "1" has no effect; the bit retains the
value it had before the write.
If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been
set to "1", the next DMA transfer request is not accepted until the transfer being performed on that channel is
completed.
(3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2–3)
These bits select the cause or source of DMA transfer request on each DMA channel.
(4) TENLn (DMAn Transfer Enable) bit (Bit 4)
Setting this bit to "1" enables transfer, and the channel is made ready for DMA transfer. When all transfers on
that channel are completed (i.e., the Transfer Counter Register underflows), the bit is cleared to "0".
Setting this bit to "0" disables transfer. However, if a transfer request has already been accepted, transfers
on that channel are not disabled until after the requested transfer is completed.
(5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5)
This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer).
The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1".
(6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6)
This bit selects the direction in which the source address changes. This mode can be selected from two
choices: Address fixed or Address incremental.
(7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7)
This bit selects the direction in which the destination address changes. This mode can be selected from two
choices: Address fixed or Address incremental.
[DMnCNT1 Register]
(1) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15)
These bits select the cause or source of extended DMA transfer request on each DMA channel.
Note: • The extended DMA transfer request sources selected by the REQESELn (Extended DMAn
Transfer Request Source Select) bits have no effect unless the “Extended” DMA transfer request source is selected with the DMA Channel Control Register’s DMA Request Source Select (REQSLn) bits.
9-16
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
Extended DMA transfer
request source selected
S
DMAn transfer
request source
DMAn
S
Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection
9-17
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
9.2.2 DMA Software Request Generation Registers
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
Software
Software
Software
Software
Software
Software
Software
Software
Software
Software
b0
?
Request
Request
Request
Request
Request
Request
Request
Request
Request
Request
1
?
2
?
Generation
Generation
Generation
Generation
Generation
Generation
Generation
Generation
Generation
Generation
3
?
4
?
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
(DM0SRI)
(DM1SRI)
(DM2SRI)
(DM3SRI)
(DM4SRI)
(DM5SRI)
(DM6SRI)
(DM7SRI)
(DM8SRI)
(DM9SRI)
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
7
8
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
0460>
0462>
0464>
0466>
0468>
0470>
0472>
0474>
0476>
0478>
5
6
9
10
11
12
13
14
b15
?
DM0SRI–DM9SRI
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
DM0SRI–DM9SRI
DMA software request generation bits
DMA transfer request is generated by writing any
data to these bits.
?
W
Note: • This register may be accessed in either bytes or halfwords.
The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA
transfer request can be generated by writing any data to this register when “Software start” has been selected
for the cause of DMA transfer request.
(1) DM0SRI–DM9SRI (DMA Software Request Generation) bits
A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in
byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA
transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to ‘00’).
9-18
32182 Group User’s Manual (Rev.1.0)
DMAC
9
9.2 DMAC Related Registers
9.2.3 DMA Source Address Registers
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
Source
Source
Source
Source
Source
Source
Source
Source
Source
Source
b0
?
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
1
?
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
2
?
3
?
(DM0SA)
(DM1SA)
(DM2SA)
(DM3SA)
(DM4SA)
(DM5SA)
(DM6SA)
(DM7SA)
(DM8SA)
(DM9SA)
4
?
5
?
<Address: H’0080 0412>
<Address: H’0080 0422>
<Address: H’0080 0432>
<Address: H’0080 0442>
<Address: H’0080 0452>
<Address: H’0080 041A>
<Address: H’0080 042A>
<Address: H’0080 043A>
<Address: H’0080 044A>
<Address: H’0080 045A>
6
?
7
8
DM0SA–DM9SA
?
?
9
10
11
12
13
14
b15
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
DM0SA–DMA9SA
Source address bits A16–A31
(A0–A15 are fixed to H’0080)
R
W
Note: • This register must always be accessed in halfwords.
The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0
and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the
values read from this register are always the current value.
When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address
fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address
incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last
transfer address + 2 (for 16-bit transfer).
The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even
address. If accessed in bytes, the value in this register is undefined.
(1) DM0SA–DM9SA (Source Address bits A16–A31)
Set this register to specify the source address of DMA transfer in the internal I/O or RAM space from the
address H’0080 0000 to the address H’0080 FFFF.
The 16 high-order source address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16
low-order source address bits (with bit 0 corresponding to the source address A16, and bit 15 corresponding
to the source address A31).
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9.2 DMAC Related Registers
9.2.4 DMA Destination Address Registers
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
b0
?
1
?
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
2
?
3
?
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
4
?
(DM0DA)
(DM1DA)
(DM2DA)
(DM3DA)
(DM4DA)
(DM5DA)
(DM6DA)
(DM7DA)
(DM8DA)
(DM9DA)
5
?
<Address: H’0080 0414>
<Address: H’0080 0424>
<Address: H’0080 0434>
<Address: H’0080 0444>
<Address: H’0080 0454>
<Address: H’0080 041C>
<Address: H’0080 042C>
<Address: H’0080 043C>
<Address: H’0080 044C>
<Address: H’0080 045C>
6
?
7
8
DM0DA–DM9DA
?
?
9
10
11
12
13
14
b15
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
DM0DA–DM9DA
Destination address bits A16–A31
(A0–A15 are fixed to H’0080)
R
W
Note: • This register must always be accessed in halfwords
The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that
bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register,
the values read from this register are always the current value.
When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address
fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address
incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last
transfer address + 2 (for 16-bit transfer).
The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even
address. If accessed in bytes, the value in this register is undefined.
(1) DM0DA–DM9DA (Destination Address bits A16–A31)
Set this register to specify the destination address of DMA transfer in the internal I/O or RAM space from the
address H’0080 0000 to the address H’0080 FFFF.
The 16 high-order destination address bits (A0–A15) are always fixed to H’0080. Use this register to set the
16 low-order destination address bits (with bit 0 corresponding to the destination address A16, and bit 15
corresponding to the destination address A31).
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9
9.2 DMAC Related Registers
9.2.5 DMA Transfer Count Registers
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
b0
?
Count
Count
Count
Count
Count
Count
Count
Count
Count
Count
1
?
2
?
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
3
?
(DM0TCT)
(DM1TCT)
(DM2TCT)
(DM3TCT)
(DM4TCT)
(DM5TCT)
(DM6TCT)
(DM7TCT)
(DM8TCT)
(DM9TCT)
4
?
<Address: H’0080 0416>
<Address: H’0080 0426>
<Address: H’0080 0436>
<Address: H’0080 0446>
<Address: H’0080 0456>
<Address: H’0080 041E>
<Address: H’0080 042E>
<Address: H’0080 043E>
<Address: H’0080 044E>
<Address: H’0080 045E>
5
6
9
10
11
12
13
14
b15
?
DM0TCT–DM15TCT
?
?
?
?
7
8
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
DM0TCT–DM9TCT
(Has no effect during ring buffer mode)
DMA transfer count
R
W
Note: • This register must always be accessed in halfwords.
The DMA Transfer Count Register is used to set the number of times data is transferred on each channel.
However, the value in this register has no effect during ring buffer mode.
The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register
is comprised of a current register, the values read from this register are always the current value. (However, if
the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count
register before the transfer began.) When transfer finishes, this count register underflows and the value read
from it is H’FFFF.
When transfer is enabled, this register is protected in hardware and cannot be accessed for write.
During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until
transfer is disabled. No interrupt is generated at underflow.
If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel
starts.
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9.2 DMAC Related Registers
9.2.6 DMA Interrupt Related Registers
The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the
Interrupt Controller.
(1) Interrupt request status bit
This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs,
this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has
no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt
request mask bit, it can be used to inspect the operating status of peripheral functions.
In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the
interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been
serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit.
(2) Interrupt request mask bit
This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to
enable interrupt requests or "1" to disable interrupt requests.
Group interrupt
Interrupt request from
each peripheral function
Set
Data bus
Data = 0
clear
Interrupt request status
F/F
To the Interrupt
Controller
F/F
Interrupt request enabled
Figure 9.2.2 Interrupt Request Status and Mask Registers
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9
9.2 DMAC Related Registers
Example for clearing interrupt request status
Interrupt request status
Initial state
b4
5
6
b7
0
0
0
0
Interrupt request
Event occurs on bit 6
0
0
1
0
Event occurs on bit 4
1
0
1
0
1
0
0
0
Write to the interrupt request status
b4
5
6
b7
1
1
0
1
Only bit 6 cleared
Bit 4 data retained
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
Event occurs on bit 6
b4
5
6
b7
0
0
1
0
Read
0
Event occurs on bit 4
1
0
1
0
0
1
0
0
Clear bit 6 (AND'ing with 1101)
0
0
0
0
0
0
0
Write
Only bit 6 cleared
Bit 4 also cleared
Figure 9.2.3 Example for Clearing Interrupt Request Status
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9
9.2 DMAC Related Registers
DMA0–4 Interrupt Request Status Register (DM04ITST)
b0
1
2
3
4
5
6
<Address: H’0080 0400>
b7
DMITST4 DMITST3 DMITST2 DMITST1 DMITST0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0–2
No function assigned. Fix to "0".
3
DMITST4 (DMA4 interrupt request status bit)
0: Interrupt not requested
4
DMITST3 (DMA3 interrupt request status bit)
1: Interrupt requested
5
DMITST2 (DMA2 interrupt request status bit)
6
DMITST1 (DMA1 interrupt request status bit)
7
DMITST0 (DMA0 interrupt request status bit)
R
W
0
0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA5–9 Interrupt Request Status Register (DM59ITST)
b0
1
2
0
0
0
3
4
5
6
<Address: H’0080 0408>
b7
DMITST9 DMITST8 DMITST7 DMITST6 DMITST5
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
0
R(Note 1)
0–2
No function assigned. Fix to "0".
3
DMITST9 (DMA9 interrupt request status bit)
0: Interrupt not requested
4
DMITST8 (DMA8 interrupt request status bit)
1: Interrupt requested
5
DMITST7 (DMA7 interrupt request status bit)
6
DMITST6 (DMA6 interrupt request status bit)
7
DMITST5 (DMA5 interrupt request status bit)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn
interrupt request status bit (n = 0–9) is set to "1", it means that a DMA interrupt request on the corresponding
channel has been generated.
(1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0–9)
[Setting the DMAn interrupt request status bit]
This bit is set in hardware, and cannot be set in software.
[Clearing the DMAn interrupt request status bit]
This bit is cleared by writing "0" in software.
Note: • The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt
Control Register’s “interrupt request bit” included in the Interrupt Controller.
When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0"
and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and
retain the value they had before the write.
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9.2 DMAC Related Registers
DMA0–4 Interrupt Request Mask Register (DM04ITMK)
b8
9
10
11
12
13
14
<Address: H’0080 0401>
b15
DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
8–10
No function assigned. Fix to "0".
11
DMITMK4 (DMA4 interrupt request mask bit)
0: Enable interrupt request
12
DMITMK3 (DMA3 interrupt request mask bit)
1: Mask (disable) interrupt request
13
DMITMK2 (DMA2 interrupt request mask bit)
14
DMITMK1 (DMA1 interrupt request mask bit)
15
DMITMK0 (DMA0 interrupt request mask bit)
DMA5–9 Interrupt Request Mask Register (DM59ITMK)
b8
9
10
11
12
13
14
R
W
0
0
R
W
<Address: H’0080 0409>
b15
DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–10
No function assigned. Fix to "0".
Function
11
DMITMK9 (DMA9 interrupt request mask bit)
0: Enable interrupt request
12
DMITMK8 (DMA8 interrupt request mask bit)
1: Mask (disable) interrupt request
13
DMITMK7 (DMA7 interrupt request mask bit)
14
DMITMK6 (DMA6 interrupt request mask bit)
15
DMITMK5 (DMA5 interrupt request mask bit)
R
W
0
0
R
W
The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel.
(1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0–9)
Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. However,
if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the
contents of this mask register.
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9.2 DMAC Related Registers
DM04ITST (H'0080 0400)
DM04ITMK (H'0080 0401)
DMA4UDF
Data bus
b3
DMITST4
F/F
b11
DMITMK4
F/F
5-source inputs
(Level)
DMA transfer interrupt request 0
DMA3UDF
b4
DMITST3
F/F
b12
DMITMK3
F/F
DMA2UDF
b5
DMITST2
F/F
b13
DMITMK2
F/F
DMA1UDF
b6
DMITST1
F/F
b14
DMITMK1
F/F
DMA0UDF
b7
DMITST0
F/F
b15
DMITMK0
F/F
Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0
DM59ITST (H'0080 0408)
DM59ITMK (H'0080 0409)
DMA9UDF
Data bus
b3
DMITST9
F/F
b11
DMITMK9
F/F
5-source inputs
(Level)
DMA transfer interrupt request 1
DMA8UDF
b4
DMITST8
F/F
b12
DMITMK8
F/F
DMA7UDF
b5
DMITST7
F/F
b13
DMITMK7
F/F
DMA6UDF
b6
DMITST6
F/F
b14
DMITMK6
F/F
DMA5UDF
b7
DMITST5
F/F
b15
DMITMK5
F/F
Figure 9.2.5 Block Diagram of DMA Transfer Interrupt Request 1
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9.3 Functional Description of the DMAC
9.3 Functional Description of the DMAC
9.3.1 DMA Transfer Request Sources
For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are
various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some
internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all
transfers on another DMA channel (cascade mode).
The causes or sources of DMA transfer requests are selected using the transfer request source select bits
REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source
select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or
sources of DMA transfer requests on each channel.
Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0
REQSL0
0
0
DMA Transfer Request Source
DMA Transfer Request Generation Timing
Software start or one DMA2
When any data is written to the DMA0 Software Request Generation Register
transfer completed
(software start) or when one DMA2 transfer is completed (cascade mode)
0
1
A-D0 conversion completed
When A-D0 conversion is completed
1
0
MJT (TIO8_udf)
When MJT TIO8 underflows
1
1
Extended DMA0 transfer request
The source selected by the DMA0 Channel Control Register 1 (DM0CNT1)
source selected
REQESEL0 bits (see below)
REQESEL0 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
MJT (input event bus 2)
When MJT input event bus 2 signal is generated
0001
Settings inhibited
–
0010
CAN (CAN0_S0/S15)
When CAN0 slot 0 transmission failed or slot 15 transmission reception finished
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
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9.3 Functional Description of the DMAC
Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1
REQSL1
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
Software start
When any data is written to the DMA1 Software Request Generation Register
0
1
MJT (output event bus 0)
When MJT output event bus 0 signal is generated
1
0
Settings inhibited
–
1
1
Extended DMA1 transfer request
The source selected by the DMA1 Channel Control Register 1 (DM1CNT1)
source selected
REQESEL1 bits (see below)
REQESEL1 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
One DMA0 transfer completed
When one DMA0 transfer is completed (cascade mode)
0001
MJT (TIN3 input signal)
When MJT TIN3 input signal is generated
0010
Settings inhibited
–
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2
REQSL2
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
Software start
When any data is written to the DMA2 Software Request Generation Register
0
1
MJT (output event bus 1)
When MJT output event bus 1 signal is generated
1
0
MJT (TIN18 input signal)
When MJT TIN18 input signal is generated
1
1
Extended DMA2 transfer request
The source selected by the DMA2 Channel Control Register 1 (DM2CNT1)
source selected
REQESEL2 bits (see below)
REQESEL2 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
One DMA1 transfer completed
When one DMA1 transfer is completed (cascade mode)
0001
Settings inhibited
–
0010
CAN(CAN0_S1/S14)
When CAN0 slot 1 transmission failed or slot 14 transmission reception finished
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
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9.3 Functional Description of the DMAC
Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3
REQSL3
DMA Transfer Request Source
DMA Transfer Request Generation Timing
When any data is written to the DMA3 Software Request Generation Register
0
0
Software start
0
1
Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
1
0
Serial I/O1 (reception completed) When serial I/O1 reception is completed
1
1
Extended DMA3 transfer request
The source selected by the DMA3 Channel Control Register 1 (DM3CNT1)
source selected
REQESEL3 bits (see below)
REQESEL3 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
0001
One DMA2 transfer completed
When one DMA2 transfer is completed (cascade mode)
0010
Settings inhibited
–
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4
REQSL4
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
Software start
When any data is written to the DMA4 Software Request Generation Register
0
1
One DMA3 transfer completed
When one DMA3 transfer is completed (cascade mode)
1
0
Serial I/O0 (reception completed) When serial I/O0 reception is completed
1
1
Extended DMA4 transfer request
The source selected by the DMA4 Channel Control Register 1 (DM4CNT1)
source selected
REQESEL4 bits (see below)
REQESEL4 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
MJT (TIN19 input signal)
When MJT TIN19 input signal is generated
0001
Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
0010
Settings inhibited
–
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
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9.3 Functional Description of the DMAC
Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5
REQSL5
0
0
DMA Transfer Request Source
DMA Transfer Request Generation Timing
Software start or one DMA7
When any data is written to the DMA5 Software Request Generation Register
transfer completed
(software start) or when one DMA7 transfer is completed (cascade mode)
When all DMA0 transfers are completed (cascade mode)
0
1
All DMA0 transfers completed
1
0
Serial I/O2 (reception completed) When serial I/O2 reception is completed
1
1
Extended DMA5 transfer request
The source selected by the DMA5 Channel Control Register 1 (DM5CNT1)
source selected
REQESEL5 bits (see below)
REQESEL5 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
MJT (TIN20 input signal)
When MJT TIN20 input signal is generated
0001
Settings inhibited
–
0010
Settings inhibited
–
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6
REQSL6
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
Software start
When any data is written to the DMA6 Software Request Generation Register
0
0
1
Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty
1
0
Settings inhibited
–
1
1
Extended DMA6 transfer request
The source selected by the DMA6 Channel Control Register 1 (DM6CNT1)
source selected
REQESEL6 bits (see below)
REQESEL6 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
One DMA5 transfer completed
When one DMA5 transfer is completed (cascade mode)
0001
Settings inhibited
–
0010
Serial I/O1 (reception completed) When serial I/O1 reception is completed
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
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DMAC
9
9.3 Functional Description of the DMAC
Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7
REQSL7
DMA Transfer Request Source
DMA Transfer Request Generation Timing
When any data is written to the DMA7 Software Request Generation Register
0
0
Software start
0
1
Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty
1
0
Settings inhibited
1
1
–
Extended DMA7 transfer request
The source selected by the DMA7 Channel Control Register 1 (DM7CNT1)
source selected
REQESEL7 bits (see below)
REQESEL7 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
One DMA6 transfer completed
When one DMA6 transfer is completed (cascade mode)
0001
Settings inhibited
–
0010
Serial I/O3 (reception completed) When serial I/O3 reception is completed
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8
REQSL8
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
Software start
When any data is written to the DMA8 Software Request Generation Register
0
1
MJT (input event bus 0)
When MJT input event bus 0 signal is generated
1
0
Serial I/O3 (reception completed) When serial I/O3 reception is completed
1
1
Extended DMA8 transfer request
The source selected by the DMA8 Channel Control Register 1 (DM8CNT1)
source selected
REQESEL8 bits (see below)
REQESEL8 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
Settings inhibited
–
0001
Settings inhibited
–
0010
One DMA7 transfer completed
When one DMA7 transfer is completed (cascade mode)
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
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DMAC
9
9.3 Functional Description of the DMAC
Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9
REQSL9
DMA Transfer Request Source
DMA Transfer Request Generation Timing
When any data is written to the DMA9 Software Request Generation Register
0
0
Software start
0
1
Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty
1
0
Settings inhibited
1
1
–
Extended DMA9 transfer request
The source selected by the DMA9 Channel Control Register 1 (DM9CNT1)
source selected
REQESEL9 bits (see below)
REQESEL9 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
One DMA8 transfer completed
When one DMA8 transfer is completed (cascade mode)
0001
Settings inhibited
–
0010
Settings inhibited
–
0011
MJT (input event bus 1)
When MJT input event bus 1 signal is generated
0100
MJT (input event bus 3)
When MJT input event bus 3 signal is generated
0101
MJT (output event bus 2)
When MJT output event bus 2 signal is generated
0110
MJT (output event bus 3)
When MJT output event bus 3 signal is generated
0111
A-D0 conversion completed
When A-D0 conversion is completed
1000
MJT (TIN0 input signal)
When MJT TIN0 input signal is generated
1001
MJT (TIO8_udf)
When MJT TIO8 underflow occurs
Settings inhibited
–
1010
|
1111
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DMAC
9
9.3 Functional Description of the DMAC
9.3.2 DMA Transfer Processing Procedure
Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0.
DMA transfer
processing starts
Setting interrupt
controller-related
registers
Set the interrupt controller's
DMA0-4 Interrupt Control Register
Set DMA0 Channel Control Register 0
Set DMA0-4 Interrupt Request Status Registers 0 and 1
Setting
DMAC-related
registers
Starting DMA transfer
• Interrupt priority level
• Transfers disabled
• Interrupt request status
bits cleared
Set DMA0-4 Interrupt Request Mask Register
• Interrupt request enabled
Set DMA0 Source Address Register
• Source address of transfer
Set DMA0 Destination Address Register
• Destination address of transfer
Set DMA0 Count Register
• Number of times DMA transfer
is performed
Set DMA0 Channel Control Registers 0 and 1
• Transfer mode, request source,
transfer size, address direction
and transfer enable
DMA transfer starts as requested by
internal peripheral I/O
Transfer count register underflows
DMA transfer
completed
Interrupt request generated
DMA operation
completed
Figure 9.3.1 Example of a DMA Transfer Processing Procedure
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DMAC
9
9.3 Functional Description of the DMAC
9.3.3 Starting DMA
Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel
Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of
DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1". DMA transfer begins when
the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer
enable) bit to "1".
Note: • If the transfer request source selected by the REQSL (DMA transfer request source select) and
REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time
required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input
signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or,
depending on the preceding or following bus usage condition, up to five cycles (250 ns when the
internal peripheral clock = 20 MHz) may be required. (However, this applies when the external
bus, HOLD and the LOCK instruction all are unused.)
To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input
signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Section 21.7, “AC
Characteristics (when VCCE = 5 V),” and Section 21.8, “AC Characteristics (when VCCE = 3.3 V).”)
9.3.4 DMA Channel Priority
DMA0 has the highest priority. The priority of this and other channels is shown below.
DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9
This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the
channel that has the highest priority is selected.
9.3.5 Gaining and Releasing Control of the Internal Bus
For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single
transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer
request is accepted and after executing one DMA transfer (in one read and one write internal clock cycle),
returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.
Requested
Gained
Requested
Gained
Requested
Gained
Internal bus arbitration
(requests from the DMAC)
CPU
Released
Internal bus
DMAC
R
Released
W
R
One DMA transfer
W
Released
R
One DMA transfer
W
One DMA transfer
R: Read
W: Write
Figure 9.3.2 Gaining and Releasing Control of the Internal Bus
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DMAC
9
9.3 Functional Description of the DMAC
9.3.6 Transfer Units
Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be
transferred in one DMA transfer.
9.3.7 Transfer Counts
Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to
65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit
is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value
set in it ignored.
9.3.8 Address Space
The address space in which data can be transferred by DMA is 64 Kbytes of internal peripheral I/O or RAM space
(H’0080 0000 through H’0080 FFFF) for both source and destination. To set the source and destination addresses on
each DMA channel, use the DMA Source Address Register and DMA Destination Address Register.
9.3.9 Transfer Operation
(1) Dual-address transfer
Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and
one for destination write access. (The transfer data is taken into the DMAC’s internal temporary register
before being transferred.)
(2) Bus protocol and bus timing
Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and
the same bus timing as when peripheral modules are accessed by the CPU.
(3) Transfer rate
Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and
one read and one write cycle to perform one transfer. Therefore, the maximum transfer rate is calculated by
the equation below:
1
Maximum transfer rate [bytes per second] = 2 bytes ×
1/f(BCLK) × 3 cycles
(4) Address count direction and address changes
The direction in which the source and destination addresses are counted as transfer proceeds (“Address
fixed” or “Address incremental”) is set for each channel using the SADSL (source address direction select)
and DADSL (destination address direction select) bits.
When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when
the transfer size is 8 bits, the address is incremented by one.
Table 9.3.11 Address Count Direction and Address Changes
Address Count Direction
Address fixed
Address incremental
Transfer Unit
Address Change for One DMA
8 bits
0
16 bits
0
8 bits
+1
16 bits
+2
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9
9.3 Functional Description of the DMAC
(5) Transfer count value
The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits).
(6) Transfer byte positions
When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination.
(Therefore, in addition to data transfers between even addresses or between odd addresses, data may be
transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the
address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus.
The diagram below shows the valid byte positions in DMA transfer.
<When transfer size = 8 bits>
+0
b0
<When transfer size = 16 bits>
+1
b7 b8
+0
b15
b0
+1
b7 b8
Source
8 bits
8 bits
16 bits
Destination
8 bits
8 bits
16 bits
b15
Figure 9.3.3 Transfer Byte Positions
(7) Ring buffer mode
When ring buffer mode is selected, transfer begins from the transfer start address and after performing
transfers 32 times, control returns to the transfer start address, from which transfer operation is repeated. In
this case, however, the five low-order bits of the ring buffer start address must always be B’00000 (if transfer
size = 16 bits, the six low-order bits must be B’000000).
The following describes how addresses are incremented in ring buffer mode.
[1] When the transfer size is 8 bits
The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented
by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to
B’00000 by the next increment operation, thus returning to the start address again.
[2] When the transfer size is 16 bits
The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented
by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to
B’000000 by the next increment operation, thus returning to the start address again.
If the source address has been set to be incremented, it is the source address that recycles to the start
address; if the destination address has been set to be incremented, it is the destination address that recycles
to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order
bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000).
During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates
in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer).
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9
9.3 Functional Description of the DMAC
<When transfer size = 8 bits>
<When transfer size = 16 bits>
Transfer count
Transfer address
Transfer count
Transfer address
1
2
3
H'0080 1000
H'0080 1001
H'0080 1002
1
2
3
H'0080 1000
H'0080 1002
H'0080 1004
|
|
|
31
32
H'0080 101E
H'0080 101F
31
32
H'0080 103C
H'0080 103E
|
↓
↓
↓
↓
1
2
H'0080 1000
H'0080 1001
1
2
H'0080 1000
H'0080 1002
|
|
|
|
Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode
9.3.10 End of DMA and Interrupt
In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is
generated at completion of transfer. However, if interrupt requests on any channel have been masked by the
DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel.
During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the
transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests are generated
even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.
9.3.11 Each Register Status after Completion of DMA Transfer
When DMA transfer is completed, the status of the source and destination address registers becomes as follows:
(1) Address fixed
• The values set in the address registers before DMA transfer started remain intact (fixed).
(2) Address incremental
• For 8-bit transfer, the values of the address registers are the last transfer address + 1.
• For 16-bit transfer, the values of the address registers are the last transfer address + 2.
The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore, before
another DMA transfer can be performed, the transfer count register must be set newly again, except when trying
to perform transfers 65,536 times (H’FFFF).
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9
9.4 Precautions about the DMAC
9.4 Precautions about the DMAC
• About writing to the DMAC related registers
Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can
only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When
transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer
request flag and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary
to ensure stable DMA operation.
The table below lists the registers that can or cannot be accessed for write.
Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write
Status
Transfer enable bit
Transfer request flag
Other DMAC related registers
Transfer enabled
Can be accessed
Can be accessed
Cannot be accessed
Transfer disabled
Can be accessed
Can be accessed
Can be accessed
Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be
observed:
(1) DMA Channel Control Register 0 transfer enable bit and transfer request flag
For all other bits in this register, be sure to write the same data that those bits had before the write. Note,
however, that only writing "0" is effective for the transfer request flag.
(2) DMA Transfer Count Register
When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored.
(3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer
Although this operation means accessing the DMAC related registers while DMA is enabled, there is no
problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the
currently active channel itself.
• Manipulating the DMAC related registers by DMA transfer
When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related
registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently
active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.)
It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For
example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by
DMA transfer through channel 0.)
• About the DMA Interrupt Request Status Register
When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be
cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write.
• About the stable operation of DMA transfer
To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the channel
control register’s transfer enable bit, unless transfer is disabled. One exception is that even when transfer is
enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer
from one channel to another.
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CHAPTER 10
MULTIJUNCTION TIMERS
10.1
10.2
10.3
10.4
10.5
10.6
Outline of Multijunction Timers
Common Units of Multijunction Timers
TOP (Output-Related 16-Bit Timer)
TIO (Input/Output-Related 16-Bit Timer)
TMS (Input-Related 16-Bit Timer)
TML (Input-Related 32-Bit Timer)
MULTIJUNCTION TIMERS
10
10.1 Outline of Multijunction Timers
10.1 Outline of Multijunction Timers
The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to
being used as a single unit, the timers can be internally connected to each other. This capability allows for highly
flexible timer configuration, making it possible to meet various application needs. It is because the timers are
connected to the internal event buses at multiple points that they are called the “multijunction” timers.
The 32182 has four types of MJT as listed in the table below, providing a total of 37-channel timers.
Table 10.1.1 Outline of MJT
Name
Type
No. of Channels
Description
TOP
Output-related
11
One of three output modes can be selected by software.
(Timer
16-bit timer
OutPut)
<With correction function>
(down-counter)
• Single-shot output mode
• Delayed single-shot output mode
<Without correction function>
• Continuous output mode
TIO
Input/output-related
(Timer
16-bit timer
by software.
(down-counter)
<Input modes>
Input
10
One of three input modes or four output modes can be selected
OutPut)
• Measure clear input mode
• Measure free-run input mode
• Noise processing input mode
<Output modes without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode
TMS
Input-related
(Timer
16-bit timer
Measure
8
16-bit input measure timer
8
32-bit input measure timer
(up-counter)
Small)
TML
Input-related
(Timer
32-bit timer
Measure
(up-counter)
Large)
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MULTIJUNCTION TIMERS
10
10.1 Outline of Multijunction Timers
Table 10.1.2 Interrupt Generation Functions of MJT
Signal Name MJT Interrupt Request Source
Source of Interrupt
No. of ICU Input Sources
IRQ0
TIO0–3 output
TIO0–3 output interrupt
4
IRQ1
TOP6, TOP7 output
TOP6, 7 output interrupt
2
IRQ2
TOP0–5 output
TOP0–5 output interrupt
6
IRQ3
TIO8, TIO9 output
TIO8, 9 output interrupt
2
IRQ4
TIO4–7 output
TIO4–7 output interrupt
4
IRQ5
TOP10 output
TOP10 output interrupt
1
IRQ6
TOP8, TOP9 output
TOP8, 9 output interrupt
2
IRQ7
TMS0, TMS1 output
TMS0, 1 output interrupt
2
IRQ9
TIN0 input
TIN0–2 input interrupt
1
IRQ10
TIN16–TIN19 input
TIN12–19 input interrupt
4
IRQ11
TIN20–TIN23 input
TIN20–29 input interrupt
4
IRQ12
TIN3 input
TIN3–6 input interrupt
1
Table 10.1.3 DMA Transfer Request Generation by MJT
Corresponding DMAC Channel No.
DMA Transfer Request Source
DMA0
TIO8_udf
Input event bus 2
Common transfer request source (see Table 10.1.4)
DMA1
Output event bus 0
TIN3 input signal
Common transfer request source (see Table 10.1.4)
DMA2
Output event bus 1
TIN18 input signal
Common transfer request source (see Table 10.1.4)
DMA3
TIN0 input signal
Common transfer request source (see Table 10.1.4)
DMA4
TIN19 input signal
Common transfer request source (see Table 10.1.4)
DMA5
TIN20 input signal
Common transfer request source (see Table 10.1.4)
DMA6
Common transfer request source (see Table 10.1.4)
DMA7
Common transfer request source (see Table 10.1.4)
DMA8
Input event bus 0
Common transfer request source (see Table 10.1.4)
DMA9
Common transfer request source (see Table 10.1.4)
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MULTIJUNCTION TIMERS
10
10.1 Outline of Multijunction Timers
Table 10.1.4 DMA Transfer Request Generation by MJT (Common)
Corresponding DMAC Channel No.
DMA Transfer Request Source
DMAn
Input event bus 1
Input event bus 3
Output event bus 2
Output event bus 3
TIN0 input signal
TIO8_udf
Table 10.1.5 A-D Conversion Start Request by MJT
Signal Name
AD0TRG
A-D Conversion Start Request Source
A-D Converter
Input event bus 2, input event bus 3,
Can be input to A-D0 conversion start trigger
output event bus 3, TIN23
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10
10.1 Outline of Multijunction Timers
Clock bus
Input event bus
Output event bus
3210 3210
clk
S
TCLK0 (P124)
clk
TCLK0S
IRQ9
TIN0 (P150)
clk
TIN0S
clk
S
DMA3,DMA commom
clk
PRS0
BCLK/2
IRQ2
en
TOP 0
udf
en
TOP 1
udf
0123
F/F0
TO0 (P110)
F/F1
TO1 (P111)
F/F2
TO2 (P112)
F/F3
TO3 (P113)
F/F4
TO4 (P114)
F/F5
TO5 (P115)
S
F/F6
TO6 (P116)
S
F/F7
TO7 (P117)
S
F/F8
TO8 (P100)
S
F/F9
TO9 (P101)
S
F/F10
TO10 (P102)
S
F/F11
TO11 (P103)
S
F/F12
TO12 (P104)
S
F/F13
TO13 (P105)
S
F/F14
TO14 (P106)
S
F/F15
TO15 (P107)
S
F/F16
TO16 (P93)
S
F/F17
TO17 (P94)
S
F/F18
TO18 (P95)
S
F/F19
TO19 (P96)
F/F20
TO20 (P97)
IRQ2
IRQ2
en
TOP 2
udf
en
TOP 3
udf
IRQ2
IRQ2
en
TOP 4
udf
en
TOP 5
udf
PRS1
clk
PRS2
clk
S
S
clk
IRQ2
IRQ1
TOP 6
en
udf
IRQ1
en
TOP 7
udf
en
TOP 8
udf
S
S
clk
S
clk
clk
IRQ12
TIN3 (P153)
TIN3S
S
clk
IRQ6
TOP 9
en
udf
IRQ5
en
TOP 10
udf
TIO 0
udf
IRQ0
en/cap
S
DMA1
clk
IRQ0
TIO 1
en/cap
udf
S
clk
IRQ6
IRQ0
TIO 2
en/cap
udf
S
clk
clk
S
TIO 3
en/cap
udf
IRQ0
IRQ4
TIO 4
en/cap
udf
S
S
TCLK1 (P125)
IRQ4
TCLK1S
clk
S
TIO 5
en/cap
udf
S
TCLK2 (P126)
IRQ4
TCLK2S
clk
S
en/cap
TIO 6
udf
en/cap
TIO 7
udf
en/cap
TIO 8
udf
en/cap
TIO 9
udf
S
IRQ4
clk
S
S
clk
S
DMA0
DMA
common
IRQ3
S
clk
S
IRQ3
S
3210 3210
PRS0-5 : Prescalers
0123
F/F
: Output flip-flop
S : Selector
Notes: • IRQ0-18 denotes interrupt signals, of which the same number represents the same group of interrupts.
• DMA0-9 and DMA common denote DMA request signals to the DMAC.
• AD0TRG denotes trigger signal to the A-D0 converter.
Figure 10.1.1 Block Diagram of MJT (1/3)
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MULTIJUNCTION TIMERS
10
10.1 Outline of Multijunction Timers
Clock bus
Input event bus
Output event bus
3210 3210
TCLK3 (P127)
TCLK3S
0123
TMS 0
cap2 cap1
clk
S
cap3
cap0
ovf
IRQ7
S
S
S
S
cap3
IRQ10
TIN16(P130)
TIN16S
TIN17(P131)
TIN17S
TIN18 (P132)
TIN18S
TMS 1
cap2 cap1
clk
S
cap0
ovf
IRQ7
S
IRQ10
S
IRQ10
S
DMA2
IRQ10
TIN19 (P133)
S
TIN19S
DMA4
clk
S
BCLK/2
cap3
IRQ11
TIN20 (P134)
TML 0 (32-bit)
cap2 cap1
cap0
S
TIN20S
DMA5
IRQ11
TIN21 (P135)
TIN21S
TIN22 (P136)
TIN22S
TIN23 (P137)
TIN23S
S
IRQ11
S
IRQ11
S
(To A-D0 converter) AD0TRG
(To A-D1 converter)AD1TRG
clk
S
BCLK/2
cap3
TML 1 (32-bit)
cap2 cap1
cap0
S
S
S
AD0TRG
(to A-D0
converter)
S
AD0TRG (to A-D0 converter)
AD0TRG (to A-D0 converter)
3210 3210
0123
Figure 10.1.2 Block Diagram of MJT (2/3)
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MULTIJUNCTION TIMERS
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10.1 Outline of Multijunction Timers
Input event bus
Output event bus
3 2 1 0
0 1 2 3
AD0 conversion
completed
TIO8_udf
TIN0S
AD0 conversion
completed
TIO8_udf
S
S
DMA0
udf
end
DMA1
udf
end
DMA2
udf
end
DMA3
udf
end
DMA4
udf
end
Software start
CAN0_S0/S15
TIN3S
S
Software start
S
CAN0_S1/S14
S
TIN18S
Software start
S
TIN0S
S
SIO0_TXD
SIO1_RXD
Software start
S
SIO0_RXD
Software start
S
TIN19S
SIO0_TXD
S
TIN20S
DMA0–4
interrupt
Software start
S
SIO1_RXD
S
SIO2_RXD
S
SIO1_TXD
Software start
S
DMA5
udf
end
DMA6
udf
end
DMA7
udf
end
DMA8
udf
end
DMA9
udf
end
SIO3_TXD
S
S
S
SIO2_TXD
Software start
SIO3_RXD
Software start
SIO3_TXD
Software start
3 2 1 0
S
S
S
DMA5–9
interrupt
0 1 2 3
Figure 10.1.3 Block Diagram of MJT (3/3)
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10.2 Common Units of Multijunction Timers
10.2 Common Units of Multijunction Timers
The common units of MJT include the following:
• Prescaler Unit
• Clock Bus and Input/Output Event Bus Control Unit
• Input Processing Control Unit
• Output Flip-flop Control Unit
• Interrupt Control Unit
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10.2 Common Units of Multijunction Timers
10.2.1 MJT Common Unit Register Map
The table below shows a common unit register map of MJT.
MJT Common Unit Register Map
Address
+0 address
+1 address
b0
b7 b8
H'0080 0200
(Use inhibited area)
H'0080 0202
Prescaler Register 0
(PRS0)
Prescaler Register 2
(PRS2)
H'0080 0204
|
H'0080 0210
H'0080 0212
|
H'0080 0218
H'0080 021A
|
H'0080 0220
H'0080 0222
H'0080 0224
H'0080 0226
H'0080 0228
H'0080 022A
|
H'0080 0230
H'0080 0232
H'0080 0234
H'0080 0236
H'0080 0238
H'0080 023A
H'0080 023C
H'0080 023E
See pages
b15
Clock Bus & Input Event Bus Control Register
(CKIEBCR)
Prescaler Register 1
(PRS1)
Output Event Bus Control Register
(OEBCR)
(Use inhibited area)
10-14
10-10
10-10
10-15
TCLK Input Processing Control Register
(TCLKCR)
TIN0–4 Input Processing Control Register
(TIN04CR)
(Use inhibited area)
10-18
TIN12–19 Input Processing Control Register
(TIN1219CR)
TIN20–23, TIN30–33 Input Processing Control Register
(TIN2023_3033CR)
(Use inhibited area)
10-20
10-19
F/F6–15 Source Select Register
(FF615S)
(Use inhibited area)
F/F16–19 Source Select Register
(FF1619S)
F/F0–15 Protect Register
(FF015P)
F/F0–15 Data Register
(FF015D)
(Use inhibited area)
F/F16–20 Protect Register
(FF1620P)
(Use inhibited area)
F/F16–20 Data Register
(FF1620D)
(Use inhibited area)
TOP0–5 Interrupt Request Status Register
TOP0–5 Interrupt Request Mask Register
(TOP05IST)
(TOP05IMA)
TOP6,7 Interrupt Request Mask & Status Register
TOP8,9 Interrupt Request Mask & Status Register
(TOP67IMS)
(TOP89IMS)
TIO0–3 Interrupt Request Mask & Status Register
TIO4–7 Interrupt Request Mask & Status Register
(TIO03IMS)
(TIO47IMS)
TIO8,9 Interrupt Request Mask & Status Register
TMS0,1 Interrupt Request Mask & Status Register
(TIO89IMS)
(TMS01IMS)
TIN0–2 Interrupt Request Mask & Status Register
TIN3–6 Interrupt Request Mask & Status Register
(TIN02IMS)
(TIN36IMS)
(Use inhibited area)
TIN12–19 Interrupt Request Status Register
(TIN1219IST)
TIN20–23 Interrupt Request Mask & Status Register
(TIN2023IMS)
10-9
TIN12–19 Interrupt Request Mask Register
(TIN1219IMA)
(Use inhibited area)
10-20
10-22
10-23
10-24
10-25
10-24
10-25
10-30
10-32
10-33
10-34
10-35
10-36
10-37
10-38
10-39
10-40
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10.2 Common Units of Multijunction Timers
10.2.2 Prescaler Unit
The Prescalers PRS0–2 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS
and TML) from the internal peripheral clock (BCLK) divided by 2 (10 MHz when f(BCLK) = 20 MHz).
The values of prescaler registers are initialized to H’00 immediately after reset. When the set value of any
prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has
underflowed.
Values H’00 to H’FF can be set in the prescaler register. The prescaler’s divide-by ratio is given by the equation
below:
1
Prescaler divide-by ratio =
prescaler set value + 1
Prescaler Register 0 (PRS0)
Prescaler Register 1 (PRS1)
Prescaler Register 2 (PRS2)
b0
b8
1
9
2
10
0
0
0
3
11
<Address: H’0080 0202>
<Address: H’0080 0203>
<Address: H’0080 0204>
4
12
5
13
6
14
b7
b15
0
0
0
PRS0–PRS5
0
0
<After reset: H’00>
b
Bit Name
0–7
PRS0–PRS2
(8–15)
Prescaler
Function
Set the prescaler divide-by value
R
W
R
W
Prescaler Registers 0–2 start counting immediately after reset.
If the prescaler register is accessed for read during operation, the value written into it, not the current count, is
read out.
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10.2 Common Units of Multijunction Timers
10.2.3 Clock Bus and Input/Output Event Bus Control Unit
(1) Clock bus
The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3.
Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can
be fed into the clock bus.
Table 10.2.1 Acceptable Clock Bus Signals
Clock Bus
Acceptable Signal
3
TCLK0 input
2
Internal prescaler (PRS2) or TCLK3 input
1
Internal prescaler (PRS1)
0
Internal prescaler (PRS0)
(2) Input event bus
The input event bus is provided for supplying a count enable signal or measure capture signal to each timer,
and is comprised of four lines of input event bus 0–3. Each timer can use these input event bus signals as
enable (or capture) input. Furthermore, they can also be used as request signals to start A-D conversion or
DMA transfer.
The table below lists the signals that can be fed into the input event bus.
Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals
Input Event Bus
Connectable (Acceptable) Signal (Note 1)
3
TIN3 input, output event bus 2 or TIO7 underflow signal
2
TIN0 input
1
TIO6 underflow signal
0
TIO5 underflow signal
Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.”
(3) Output event bus
The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines
of output event bus 0–3. Output event bus signals are connected to output flip-flops, and can also be connected to the A-D converter and DMAC. Furthermore, output event bus 2 can be connected to input event
bus 3.
The table below lists the signals that can be connected to the output event bus.
Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals
Input Event Bus
Connectable (Acceptable) Signal (Note 1)
3
TOP8, TIO3, TIO4 or TIO8 underflow signal
2
TOP9 or TIO2 underflow signal
1
TOP7 or TIO1 underflow signal
0
TOP6 or TIO0 underflow signal
Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.”
Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are
generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer
to the output flip-flop.
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10.2 Common Units of Multijunction Timers
Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer
Timer
Mode
TOP
Single-shot output mode
When the counter underflows
Delayed single-shot output mode
When the counter underflows
Continuous output mode
When the counter underflows
TIO(Note 1)
Timing at which signals are generated to the output event bus
Measure clear input mode
When the counter underflows
Measure free-run input mode
When the counter underflows
Noise processing input mode
When the counter underflows
PWM output mode
When the counter underflows
Single-shot output mode
When the counter underflows
Delayed single-shot output mode
When the counter underflows
Continuous output mode
When the counter underflows
TMS
(16-bit measure input)
No signals generated
TML
(32-bit measure input)
No signals generated
Note 1: TIO5–7 output an underflow signal to the input event bus.
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10.2 Common Units of Multijunction Timers
Clock bus
3210
TCLK0 (P124)
TIN0 (P150)
TCLK0S
0123
clk
clk
TIN0S
PRS0
BCLK/2
Output event bus
Input event bus
3210
clk
PRS1
en
TOP 6
udf
en
TOP 7
udf
en
TOP 8
udf
en
TOP 9
udf
TIO 0
udf
TIO 1
udf
TIO 2
udf
TIO 3
udf
TIO 4
udf
PRS2
clk
TIN3 (P153)
TIN3S
S
TCLK3 (P127)
TIO 5
udf
TIO 6
udf
TIO 7
udf
TIO 8
udf
TCLK3S
3210
3210
0123
PRS0-2
: Prescaler
S : Selector
Figure 10.2.1 Conceptual Diagram of the Clock Bus and Input/Output Event Bus
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10.2 Common Units of Multijunction Timers
The Clock Bus and Input/Output Event Bus Control Unit has the following registers:
• Clock Bus & Input Event Bus Control Register (CKIEBCR)
• Output Event Bus Control Register (OEBCR)
Clock Bus & Input Event Bus Control Register (CKIEBCR)
b8
9
10
IEB3S
0
11
IEB2S
0
0
0
12
13
IEB1S
IEB0S
0
0
14
<Address: H’0080 0201>
b15
CKB2S
0
0
<After reset: H’00>
b
Bit Name
R
W
8, 9
IEB3S
Input event bus 3 input select bit
00: Select external input 3 (TIN3)
01: – ditto –
10: Select output event bus 2
11: Select TIO7 output
R
W
10, 11
IEB2S
Input event bus 2 input select bit
00: Select external input 0 (TIN0)
01: Select external input 2 (TIN2) (Note 1)
10: Select external input 4 (TIN4) (Note 1)
11: – ditto –
(Note 1)
R
W
R
W
R
W
0
0
R
W
12
Function
IEB1S
0: Select external input 5 (TIN5) (Note 1)
Input event bus 1 input select bit
1: Select TIO6 output
13
IEB0S
Input event bus 0 input select bit
0: Select external input 6 (TIN6) (Note 1)
1: Select TIO5 output
14
No function assigned. Fix to "0".
15
CKB2S
Clock bus 2 input select bit
0: Select prescaler 2
1: Select external clock 3 (TCLK3)
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus
and the count enable/capture signal (external input or output event bus) supplied to the input event bus.
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10.2 Common Units of Multijunction Timers
Output Event Bus Control Register (OEBCR)
b8
9
10
OEB3S
0
11
12
OEB2S
0
0
0
13
14
OEB1S
0
0
<Address: H’0080 0205>
b15
OEB0S
0
0
<After reset: H’00>
b
Bit Name
8, 9
OEB3S
Output event bus 3 input select bit
Function
00: Select TOP8 output
01: Select TIO3 output
10: Select TIO4 output
R
W
R
W
11: Select TIO8 output
10
No function assigned. Fix to "0".
11
OEB2S
Output event bus 2 input select bit
12
No function assigned. Fix to "0".
13
OEB1S
Output event bus 1 input select bit
14
No function assigned. Fix to "0".
15
0: Select TOP9 output
1: Select TIO2 output
0: Select TOP7 output
1: Select TIO1 output
OEB0S
0: Select TOP6 output
Output event bus 0 input select bit
1: Select TIO0 output
0
0
R
W
0
0
R
W
0
0
R
W
The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output
event bus.
10.2.4 Input Processing Control Unit
The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input processing,
it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or
level (high or low) of the signal, at which to generate the clock signal supplied to the clock bus.
In TIN input processing, the unit selects the active edge (rising or falling or both) or level (high or low) of the
signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to
each event bus.
Following input processing registers are included:
• TLCK Input Processing Control Register (TCLKCR)
• TIN0–4 Input Processing Control Register (TIN04CR)
• TIN12–19 Input Processing Control Register (TIN1219CR)
• TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR)
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10.2 Common Units of Multijunction Timers
(1) Functions of TCLK Input Processing Control Registers
Item
Function
BCLK/2
BCLK/2
Count clock
Rising edge
TCLK
Count clock
Falling edge
TCLK
Count clock
Both edges
TCLK
Count clock
Low level
TCLK
BCLK/2
Count clock
High level
TCLK
BCLK/2
Count clock
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10.2 Common Units of Multijunction Timers
(2) Functions of TIN Input Processing Control Registers
Item
Function
Rising edge
TIN
Internal edge
signal
Falling edge
TIN
Internal edge
signal
Both edges
TIN
Internal edge
signal
Low level
TIN
Prescaler output period or TCLK input period
Internal edge
signal
High level
TIN
Prescaler output period or TCLK input period
Internal edge
signal
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10.2 Common Units of Multijunction Timers
TLCK Input Processing Control Register (TCLKCR)
b0
1
2
3
4
5
TCLK3S
0
0
0
0
6
<Address: H’0080 0210>
7
8
9
TCLK2S
0
0
0
10
11
12
13
0
0
0
0
14
b15
TCLK0S
TCLK1S
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
0, 1
No function assigned. Fix to "0".
2, 3
TCLK3S
TCLK3 input processing select bit
4
No function assigned. Fix to "0".
5–7
TCLK2S
TCLK2 input processing select bit
8
No function assigned. Fix to "0".
9–11
TCLK1S
TCLK1 input processing select bit
12,13
No function assigned. Fix to "0".
14,15
TCLK0S
TCLK0 input processing select bit
Function
R
0
0
00: BCLK/2
01: Rising edge
10: Falling edge
11: Both edges
R
W
0
0
000: Disable input
001: Rising edge
010: Falling edge
011: Both edges
100: Low level
101: Low level
110: High level
111: High level
R
W
0
0
000: Disable input
001: Rising edge
010: Falling edge
011: Both edges
100: Low level
101: Low level
110: High level
111: High level
R
W
0
0
R
W
00: BCLK/2
01: Rising edge
10: Falling edge
11: Both edges110
W
Note: • This register must always be accessed in halfwords.
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10.2 Common Units of Multijunction Timers
TIN0–4 Input Processing Control Register (TIN04CR)
b0
1
2
3
4
5
TIN4S
0
0
0
6
<Address: H’0080 0212>
7
8
9
10
TIN3S
0
0
0
0
11
12
TIN2S
0
0
0
0
13
14
TIN1S
0
0
b15
TIN0S
0
0
0
<After reset: H’0000>
b
Bit Name
R
W
0
No function assigned. Fix to "0".
Function
0
0
1–3
Fix to "0".
0
0
4
No function assigned. Fix to "0".
5–7
TIN3S
TIN3 input processing select bit
8,9
10,11
0
0
R
W
No function assigned. Fix to "0".
0
0
Fix to "0".
0
0
12,13
Fix to "0".
14,15
TIN0S
TIN0 input processing select bit
000: Disable input
001: Rising edge
010: Falling edge
011: Both edges
100: Low level
101: Low level
110: High level
111: High level
00: Disable input
01: Rising edge
10: Falling edge
11: Both edges
0
0
R
W
Note: • This register must always be accessed in halfwords.
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10.2 Common Units of Multijunction Timers
TIN12–19 Input Processing Control Register (TIN1219CR)
b0
1
2
TIN19S
0
3
4
TIN18S
0
0
5
6
TIN17S
0
0
7
<Address: H’0080 0218>
8
TIN16S
0
0
9
10
TIN15S
0
0
11
12
TIN14S
0
0
13
14
TIN13S
0
0
b15
TIN12S
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0, 1
TIN19S (TIN19 input processing select bit)
00: Disable input
R
W
2, 3
TIN18S (TIN18 input processing select bit)
01: Rising edge
4, 5
TIN17S (TIN17 input processing select bit)
10: Falling edge
6, 7
TIN16S (TIN16 input processing select bit)
11: Both edges
8-15
Fix to "0".
0
0
Note: • This register must always be accessed in halfwords.
TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR)
b0
1
2
TIN33S
0
3
4
TIN32S
0
0
5
6
TIN31S
0
0
7
8
TIN30S
0
0
9
10
TIN23S
0
0
<Address: H’0080 021A>
11
12
TIN22S
0
0
13
14
TIN21S
0
0
b15
TIN20S
0
0
0
<After reset: H’0000>
b
Bit Name
0-7
Fix to "0".
Function
8, 9
TIN23S (TIN23 input processing select bit)
00: Disable input
10, 11
TIN22S (TIN22 input processing select bit)
01: Rising edge
12, 13
TIN21S (TIN21 input processing select bit)
10: Falling edge
14, 15
TIN20S (TIN20 input processing select bit)
11: Both edges
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords.
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10.2 Common Units of Multijunction Timers
10.2.5 Output Flip-flop Control Unit
The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control
registers are included:
• F/F6–15 Source Select Register (FF615S)
• F/F16–19 Source Select Register (FF1619S)
• F/F0–15 Protect Register (FF015P)
• F/F16–20 Protect Register (FF1620P)
• F/F0–15 Data Register (FF015D)
• F/F16–20 Data Register (FF1620D)
The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note
that this timing is different from one at which signals are output from the timer to the output event bus.)
10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer
Timer
Mode
Timing at which signals are generated to the output flip-flop
TOP
Single-shot output mode
When count is enabled or underflows
Delayed single-shot output mode
When counter underflows
Continuous output mode
When count is enabled or underflows
TIO
Measure clear input mode
When counter underflows
Measure free-run input mode
When counter underflows
Noise processing input mode
When counter underflows
PWM output mode
When count is enabled or underflows
Single-shot output mode
When count is enabled or underflows
Delayed single-shot output mode
When counter underflows
Continuous output mode
When count is enabled or underflows
TMS
(16-bit measure input)
No signals generated
TML
(32-bit measure input)
No signals generated
F/F source selection (FSn)
Port operation mode register (PnMOD)
F/F
TOP/TIO
Output event bus 0
Output event bus 1
Output event bus 2
Output event bus 3
Internal edge signal
F/Fn output data (FDn)
Data bus
F/F
TOn
Output control (ON/OFF)
WR
F/F protect (FPn)
Data bus
F/F
Figure 10.2.2 Configuration of the F/F Output Circuit Table
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10.2 Common Units of Multijunction Timers
F/F6–15 Source Select Register (FF615S)
b0
0
1
0
2
0
<Address: H’0080 0220>
3
4
5
6
7
FS15
FS14
FS13
FS12
FS11
0
0
0
0
0
8
9
10
FS10
0
11
12
FS9
0
0
13
FS8
0
0
0
14
b15
FS7
FS6
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0–2
No function assigned. Fix to "0".
0
0
3
FS15
F/F15 source select bit
0: TIO4 output
1: Output event bus 0
R
W
4
FS14
F/F14 source select bit
0: TIO3 output
1: Output event bus 0
R
W
5
FS13
F/F13 source select bit
0: TIO2 output
1: Output event bus 3
R
W
6
FS12
F/F12 source select bit
0: TIO1 output
1: Output event bus 2
R
W
7
FS11
F/F11 source select bit
0: TIO0 output
1: Output event bus 1
R
W
8, 9
FS10
F/F10 source select bit
00: TOP10 output
01: TOP10 output
10: Output event bus 0
R
W
11: Output event bus 1
10, 11
FS9
F/F9 source select bit
00:
01:
10:
11:
TOP9 output
TOP9 output
Output event bus 0
Output event bus 1
R
W
12, 13
FS8
F/F8 source select bit
00:
01:
10:
11:
TOP8 output
Output event bus 0
Output event bus 1
Output event bus 2
R
W
14
FS7
F/F7 source select bit
0: TOP7 output
1: Output event bus 0
R
W
FS6
0: TOP6 output
R
W
F/F6 source select bit
1: Output event bus 1
15
Note: • This register must always be accessed in halfwords.
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10.2 Common Units of Multijunction Timers
F/F16–19 Source Select Register (FF1619S)
b8
9
10
FS19
0
11
12
FS18
0
0
13
14
FS17
0
0
<Address: H’0080 0223>
b15
FS16
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
8, 9
FS19
F/F19 source select bit
00: TIO8 output
01: TIO8 output
10: Output event bus 0
R
W
11: Output event bus 1
10, 11
FS18
F/F18 source select bit
00:
01:
10:
11:
TIO7 output
TIO7 output
Output event bus 0
Output event bus 1
R
W
12, 13
FS17
F/F17 source select bit
00:
01:
10:
11:
TIO6 output
TIO6 output
Output event bus 0
Output event bus 1
R
W
14, 15
FS16
F/F16 source select bit
00:
01:
10:
11:
TIO5 output
Output event bus 0
Output event bus 1
Output event bus 3
R
W
These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a
signal from the internal output bus or an underflow output from each timer.
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10.2 Common Units of Multijunction Timers
F/F0–15 Protect Register (FF015P)
<Address: H’0080 0224>
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
FP15 (F/F15 protect bit)
0: Enable write to F/F output bit
R
W
1
FP14 (F/F14 protect bit)
1: Disable write to F/F output bit
2
FP13 (F/F13 protect bit)
3
FP12 (F/F12 protect bit)
4
FP11 (F/F11 protect bit)
5
FP10 (F/F10 protect bit)
6
FP9 (F/F9 protect bit)
7
FP8 (F/F8 protect bit)
8
FP7 (F/F7 protect bit)
9
FP6 (F/F6 protect bit)
10
FP5 (F/F5 protect bit)
11
FP4 (F/F4 protect bit)
12
FP3 (F/F3 protect bit)
13
FP2 (F/F2 protect bit)
14
FP1 (F/F1 protect bit)
15
FP0 (F/F0 protect bit)
Note: • This register must always be accessed in halfwords.
F/F16–20 Protect Register (FF1620P)
b8
0
9
0
10
0
<Address: H’0080 0229>
11
12
13
14
b15
FP20
FP19
FP18
FP17
FP16
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–10
No function assigned. Fix to "0".
Function
11
FP20 (F/F20 protect bit)
0: Enable write to F/F output bit
12
FP19 (F/F19 protect bit)
1: Disable write to F/F output bit
13
FP18 (F/F18 protect bit)
14
FP17 (F/F17 protect bit)
15
FP16 (F/F16 protect bit)
R
W
0
0
R
W
This register enables or disables write to each output F/F (flip-flop). If write to any output F/F is disabled, writing
to the corresponding F/F data register has no effect.
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10.2 Common Units of Multijunction Timers
F/F0–15 Data Register (FF015D)
<Address: H’0080 0226>
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FD15
FD14
FD13
FD12
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
b15
FD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
FD15 (F/F15 output data bit)
0: F/F output data = 0
R
W
1
FD14 (F/F14 output data bit)
1: F/F output data = 1
2
FD13 (F/F13 output data bit)
3
FD12 (F/F12 output data bit)
4
FD11 (F/F11 output data bit)
5
FD10 (F/F10 output data bit)
6
FD9 (F/F9 output data bit)
7
FD8 (F/F8 output data bit)
8
FD7 (F/F7 output data bit)
9
FD6 (F/F6 output data bit)
10
FD5 (F/F5 output data bit)
11
FD4 (F/F4 output data bit)
12
FD3 (F/F3 output data bit)
13
FD2 (F/F2 output data bit)
14
FD1 (F/F1 output data bit)
15
FD0 (F/F0 output data bit)
Note: • This register must always be accessed in halfwords.
F/F16–20 Data Register (FF1620D)
b8
0
9
0
10
0
<Address: H’0080 022B>
11
12
13
14
b15
FD20
FD19
FD18
FD17
FD16
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–10
No function assigned. Fix to "0".
Function
11
FD20 (F/F20 output data bit)
0: F/F output data = 0
12
FD19 (F/F19 output data bit)
1: F/F output data = 1
13
FD18 (F/F18 output data bit)
14
FD17 (F/F17 output data bit)
15
FD16 (F/F16 output data bit)
R
W
0
0
R
W
This register is used to set the data for each output F/F (flip-flop). Although the F/F outputs normally change
state depending on timer outputs, the F/F outputs can be set to 1 or cleared to 0 as necessary by writing to this
register. The F/F data register can only be operated on when the F/F protect register described above is enabled
for write.
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10.2 Common Units of Multijunction Timers
10.2.6 Interrupt Control Unit
The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer.
Following timer interrupt control registers are provided for each timer:
• TOP0–5 Interrupt Request Status Register (TOP05IST)
• TOP0–5 Interrupt Request Mask Register (TOP05IMA)
• TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS)
• TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS)
• TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS)
• TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS)
• TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS)
• TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS)
• TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS)
• TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS)
• TIN12–19 Interrupt Request Status Register (TIN1219IST)
• TIN12–19 Interrupt Request Mask Register (TIN1219IMA)
• TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS)
For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control
registers are included in the timer, and the interrupt request status flags are automatically managed within the
Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.”
• TOP10
TOP10 Output Interrupt Request (IRQ5)
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10.2 Common Units of Multijunction Timers
For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers
are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in
the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and
cannot be accessed for write.
(1) Interrupt request status bit
This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs,
this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has
no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt
request mask bit, it can be used to inspect the operating status of peripheral functions.
In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the
interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been
serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit.
(2) Interrupt request mask bit
This bit is used to disable unnecessary interrupts within the grouped interrupt request. Set this bit to "0" to
enable interrupt requests or "1" to disable interrupt requests.
Group interrupt
Timer or TIN input
interrupt request
Set
Data bus
Data = 0
clear
Interrupt request status
F/F
To the Interrupt
Controller
F/F
Interrupt request enabled
Figure 10.2.3 Interrupt Request Status and Mask Registers
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10.2 Common Units of Multijunction Timers
Example for clearing interrupt request status
Interrupt request status
Initial state
b4
5
6
b7
0
0
0
0
Interrupt request
Event occurs on bit 6
0
0
1
0
Event occurs on bit 4
1
0
1
0
1
0
0
0
Write to the interrupt request status
b4
5
6
b7
1
1
0
1
Only bit 6 cleared
Bit 4 data retained
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
Event occurs on bit 6
b4
5
6
b7
0
0
1
0
Read
0
Event occurs on bit 4
1
0
1
0
0
1
0
0
Clear bit 6 (ANDing with 1101)
0
0
0
0
0
0
0
Write
Only bit 6 cleared
Bit 4 also cleared
Figure 10.2.4 Example for Clearing Interrupt Request Status
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10.2 Common Units of Multijunction Timers
The table below shows the relationship between the interrupt request signals generated by multijunction timers
and the interrupt sources input to the Interrupt Controller (ICU).
Table 10.2.6 Interrupt Request Signals Generated by MJT
Signal Name
Generated by
Interrupt Request Source (Note 1)
No. of ICU Input Sources
IRQ0
TIO0, TIO1, TIO2, TIO3
TIO0–3 output interrupt
4
IRQ1
TOP6, TOP7
TOP6, 7 output interrupt
2
IRQ2
TOP0, TOP1, TOP2, TOP3, TOP4, TOP5
TOP0–5 output interrupt
6
IRQ3
TIO8, TIO9
TIO8, 9 output interrupt
2
IRQ4
TIO4, TIO5, TIO6, TIO7
TIO4–7 output interrupt
4
IRQ6
TOP8, TOP9
TOP8, 9 output interrupt
2
IRQ7
TMS0, TMS1
TMS0, 1 output interrupt
2
IRQ9
TIN0
TIN0–2 input interrupt
1
IRQ10
TIN16, TIN17, TIN18, TIN19
TIN12–19 input interrupt
4
IRQ11
TIN20, TIN21, TIN22, TIN23
TIN20–29 input interrupt
4
IRQ12
TIN3
TIN3–6 input interrupt
1
Note 1: See Chapter 5, “Interrupt Controller (ICU).”
Note: • TOP10 has only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent
in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.)
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10.2 Common Units of Multijunction Timers
TOP0–5 Interrupt Request Status Register (TOP05IST)
b0
1
2
3
4
5
6
<Address: H’0080 0230>
b7
TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0, 1
No function assigned. Fix to "0".
2
TOPIS5 (TOP5 interrupt request status bit)
0: Interrupt not requested
3
TOPIS4 (TOP4 interrupt request status bit)
1: Interrupt requested
4
TOPIS3 (TOP3 interrupt request status bit)
5
TOPIS2 (TOP2 interrupt request status bit)
6
TOPIS1 (TOP1 interrupt request status bit)
7
TOPIS0 (TOP0 interrupt request status bit)
R
W
0
0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TOP0–5 Interrupt Request Mask Register (TOP05IMA)
b8
9
10
11
12
13
14
<Address: H’0080 0231>
b15
TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8, 9
No function assigned. Fix to "0".
Function
10
TOPIM5 (TOP5 interrupt request mask bit)
0: Enable interrupt request
11
TOPIM4 (TOP4 interrupt request mask bit)
1: Mask (disable) interrupt request
12
TOPIM3 (TOP3 interrupt request mask bit)
13
TOPIM2 (TOP2 interrupt request mask bit)
14
TOPIM1 (TOP1 interrupt request mask bit)
15
TOPIM0 (TOP0 interrupt request mask bit)
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10.2 Common Units of Multijunction Timers
TOP05IST <H'0080 0230>
TOP05IMA <H'0080 0231>
TOP5udf
Data bus
b2
TOPIS5
F/F
b10
TOPIM5
F/F
6-source inputs
(Level)
TOP0-5 output interrupt request
IRQ2
TOP4udf
b3
TOPIS4
F/F
b11
TOPIM4
F/F
TOP3udf
b4
TOPIS3
F/F
b12
TOPIM3
F/F
TOP2udf
b5
TOPIS2
F/F
b13
TOPIM2
F/F
TOP1udf
b6
TOPIS1
F/F
b14
TOPIM1
F/F
TOP0udf
b7
TOPIS0
F/F
b15
TOPIM0
F/F
Figure 10.2.5 Block Diagram of TOP0–5 Output Interrupt Request
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10.2 Common Units of Multijunction Timers
TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS)
b0
1
2
3
4
5
TOPIS7 TOPIS6
0
0
0
0
6
<Address: H’0080 0232>
b7
TOPIM7 TOPIM6
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0, 1
No function assigned. Fix to "0".
2
TOPIS7 (TOP7 interrupt request status bit)
0: Interrupt not requested
3
TOPIS6 (TOP6 interrupt request status bit)
1: Interrupt requested
4, 5
No function assigned. Fix to "0".
R
W
0
0
R(Note 1)
6
TOPIM7 (TOP7 interrupt request mask bit)
0: Enable interrupt request
7
TOPIM6 (TOP6 interrupt request mask bit)
1: Mask (disable) interrupt request
0
0
R
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TOP67IMS <H'0080 0232>
TOP7udf
Data bus
b2
TOPIS7
F/F
b6
TOPIM7
F/F
2-source inputs
(Level)
TOP6,7 output interrupt request
IRQ1
TOP6udf
b3
TOPIS6
F/F
b7
TOPIM6
F/F
Figure 10.2.6 Block Diagram of TOP6,7 Output Interrupt Request
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10.2 Common Units of Multijunction Timers
TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS)
b8
9
10
11
12
13
TOPIS9 TOPIS8
0
0
0
0
14
<Address: H’0080 0233>
b15
TOPIM9 TOPIM8
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
8,9
No function assigned. Fix to "0".
10
TOPIS9 (TOP9 interrupt request status bit)
0: Interrupt not requested
11
TOPIS8 (TOP8 interrupt request status bit)
1: Interrupt requested
12,13
No function assigned. Fix to "0".
R
W
0
0
R(Note 1)
14
TOPIM9 (TOP9 interrupt request mask bit)
0: Enable interrupt request
15
TOPIM8 (TOP8 interrupt request mask bit)
1: Mask (disable) interrupt request
0
0
R
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
Note: • TOP10 has only one interrupt source in the interrupt group, so that its status and mask registers are nonexistent in the MJT
interrupt control registers. (They are controlled directly by the Interrupt Controller.)
TOP89IMS <H'0080 0233>
TOP9udf
Data bus
2-source inputs
TOPIS9
b10
b14
F/F
(Level)
TOPIM9
F/F
TOP8,9 output interrupt request
IRQ6
TOP8udf
b11
TOPIS8
F/F
b15
TOPIM8
F/F
Figure 10.2.7 Block Diagram of TOP8,9 Output Interrupt Request
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10.2 Common Units of Multijunction Timers
TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS)
b0
1
2
3
4
5
6
<Address: H’0080 0234>
b7
TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
TIOIS3 (TIO3 interrupt request status bit)
0: Interrupt not requested
R(Note 1)
1
TIOIS2 (TIO2 interrupt request status bit)
1: Interrupt requested
2
TIOIS1 (TIO1 interrupt request status bit)
3
TIOIS0 (TIO0 interrupt request status bit)
4
TIOIM3 (TIO3 interrupt request mask bit)
0: Enable interrupt request
5
TIOIM2 (TIO2 interrupt request mask bit)
1: Mask (disable) interrupt request
6
TIOIM1 (TIO1 interrupt request mask bit)
7
TIOIM0 (TIO0 interrupt request mask bit)
R
W
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIO03IMS <H'0080 0234>
TIO3udf
Data bus
b0
TIOIS3
F/F
b4
TIOIM3
F/F
4-source inputs
(Level)
TIO0–3 output interrupt request
IRQ0
TIO2udf
b1
TIOIS2
F/F
b5
TIOIM2
F/F
TIO1udf
b2
TIOIS1
F/F
b6
TIOIM1
F/F
TIO0udf
b3
TIOIS0
F/F
TIOIM0
b7
F/F
Figure 10.2.8 Block Diagram of TIO0–3 Output Interrupt Request
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10.2 Common Units of Multijunction Timers
TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS)
b8
9
10
11
12
13
14
<Address: H’0080 0235>
b15
TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
8
TIOIS7 (TIO7 interrupt request status bit)
0: Interrupt not requested
R(Note 1)
9
TIOIS6 (TIO6 interrupt request status bit)
1: Interrupt requested
10
TIOIS5 (TIO5 interrupt request status bit)
11
TIOIS4 (TIO4 interrupt request status bit)
12
TIOIM7 (TIO7 interrupt request mask bit)
0: Enable interrupt request
13
TIOIM6 (TIO6 interrupt request mask bit)
1: Mask (disable) interrupt request
14
TIOIM5 (TIO5 interrupt request mask bit)
15
TIOIM4 (TIO4 interrupt request mask bit)
R
W
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIO47IMS <H'0080 0235>
TIO7udf
Data bus
b8
TIOIS7
F/F
b12
TIOIM7
F/F
4-source inputs
(Level)
TIO4–7 output interrupt request
IRQ4
TIO6udf
b9
TIOIS6
F/F
b13
TIOIM6
F/F
TIO5udf
b10
TIOIS5
F/F
b14
TIOIM5
F/F
TIO4udf
b11
TIOIS4
F/F
b15
TIOIM4
F/F
Figure 10.2.9 Block Diagram of TIO4–7 Output Interrupt Request
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10.2 Common Units of Multijunction Timers
TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS)
b0
1
2
3
4
5
TIOIS9 TIOIS8
0
0
0
6
<Address: H’0080 0236>
b7
TIOIM9 TIOIM8
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
0
R(Note 1)
0, 1
No function assigned. Fix to "0".
2
TIOIS9 (TIO9 interrupt request status bit)
0: Interrupt not requested
3
TIOIS8 (TIO8 interrupt request status bit)
1: Interrupt requested
4, 5
No function assigned. Fix to "0".
6
TIOIM9 (TIO9 interrupt request mask bit)
0: Enable interrupt request
7
TIOIM8 (TIO8 interrupt request mask bit)
1: Mask (disable) interrupt request
0
0
R
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIO89IMS <H'0080 0236>
TIO9udf
Data bus
2-source inputs
TIOIS9
b2
F/F
TIOIM9
b6
(Level)
TIO8, 9 output interrupt request
IRQ3
F/F
TIO8udf
TIOIS8
b3
b7
F/F
TIOIM8
F/F
Figure 10.2.10 Block Diagram of TIO8,9 Output Interrupt Request
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10
10.2 Common Units of Multijunction Timers
TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS)
b8
9
10
11
12
13
TMSIS1 TMSIS0
0
0
0
0
14
<Address: H’0080 0237>
b15
TMSIM1 TMSIM0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
8, 9
No function assigned. Fix to "0".
10
TMSIS1 (TMS1 interrupt request status bit)
0: Interrupt not requested
11
TMSIS0 (TMS0 interrupt request status bit)
1: Interrupt requested
12, 13
No function assigned. Fix to "0".
R
W
0
0
R(Note 1)
14
TMSIM1 (TMS1 interrupt request mask bit)
0: Enable interrupt request
15
TMSIM0 (TMS0 interrupt request mask bit)
1: Mask (disable) interrupt request
0
0
R
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TMS01IMS <H'0080 0237>
TMS1ovf
Data bus
2-source inputs
TMSIS1
b10
F/F
TMSIM1
b14
(Level)
TMS0, 1 output interrupt request
IRQ7
F/F
TMS0ovf
TMSIS0
b11
b15
F/F
TMSIM0
F/F
Figure 10.2.11 Block Diagram of TMS0,1 Output Interrupt Request
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10
10.2 Common Units of Multijunction Timers
TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS)
b0
1
2
3
4
TINIS2 TINIS1 TINIS0
0
0
0
0
5
6
<Address: H’0080 0238>
b7
TINIM2 TINIM1 TINIM0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0
No function assigned. Fix to "0".
1
TINIS2 (TIN2 interrupt request status bit) (Note 2)
0: Interrupt not requested
2
TINIS1 (TIN1 interrupt request status bit) (Note 2)
1: Interrupt requested
3
TINIS0 (TIN0 interrupt request status bit)
4
No function assigned. Fix to "0".
5
TINIM2 (TIN2 interrupt request mask bit) (Note 2)
0: Enable interrupt request
6
TINIM1 (TIN1 interrupt request mask bit) (Note 2)
1: Mask (disable) interrupt request
7
TINIM0 (TIN0 interrupt request mask bit)
R
W
0
0
R(Note 1)
0
0
R
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
TIN02IMS <H'0080 0238>
Data bus
TIN2edge
(Note 1)
b1
b5
TIN1edge
(Note 1)
b2
b6
3-source inputs
TINIS2
F/F
(Level)
TINIM2
F/F
TIN0–2 input interrupt request
IRQ9
TINIS1
F/F
TINIM1
F/F
TIN0edge
b3
TINIS0
F/F
b7
TINIM0
F/F
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins
and the selected function therefore has no effect.
Figure 10.2.12 Block Diagram of TIN0–2 Input Interrupt Request
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10
10.2 Common Units of Multijunction Timers
TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS)
b8
9
10
11
12
13
14
<Address: H’0080 0239>
b15
TINIS6 TINIS5 TINIS4 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
8
TINIS6 (TIN6 interrupt request status bit) (Note 2)
0: Interrupt not requested
R(Note 1)
9
TINIS5 (TIN5 interrupt request status bit) (Note 2)
1: Interrupt requested
10
TINIS4 (TIN4 interrupt request status bit) (Note 2)
11
TINIS3 (TIN3 interrupt request status bit)
12
TINIM6 (TIN6 interrupt request mask bit) (Note 2)
0: Enable interrupt request
13
TINIM5 (TIN5 interrupt request mask bit) (Note 2)
1: Mask (disable) interrupt request
R
14
TINIM4 (TIN4 interrupt request mask bit) (Note 2)
15
TINIM3 (TIN3 interrupt request mask bit)
W
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
TIN36IMS <H'0080 0239>
Data bus
TIN6edge
(Note 1)
b8
b12
TIN5edge
(Note 1)
b9
b13
TIN4edge
(Note 1)
b10
b14
4-source inputs
TINIS6
F/F
TINIM6
F/F
(Level)
TIN3–6 input interrupt request
IRQ12
TINIS5
F/F
TINIM5
F/F
TINIS4
F/F
TINIM4
F/F
TIN3edge
b11
TINIS3
F/F
TINIM3
b15
F/F
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins
and the selected function therefore has no effect.
Figure 10.2.13 Block Diagram of TIN3–6 Input Interrupt Request
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10
10.2 Common Units of Multijunction Timers
TIN12–19 Interrupt Request Status Register (TIN1219IST)
b0
1
2
3
4
5
6
<Address: H’0080 023C>
b7
TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
TINIS19 (TIN19 interrupt request status bit)
0: Interrupt not requested
R(Note 1)
1
TINIS18 (TIN18 interrupt request status bit)
1: Interrupt requested
2
TINIS17 (TIN17 interrupt request status bit)
3
TINIS16 (TIN16 interrupt request status bit)
4
TINIS15 (TIN15 interrupt request status bit) (Note 2)
5
TINIS14 (TIN14 interrupt request status bit) (Note 2)
6
TINIS13 (TIN13 interrupt request status bit) (Note 2)
7
TINIS12 (TIN12 interrupt request status bit) (Note 2)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
TIN12–19 Interrupt Request Mask Register (TIN1219IMA)
b8
9
10
11
12
13
14
<Address: H’0080 023D>
b15
TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
TINIM19 (TIN19 interrupt request mask bit)
0: Enable interrupt request
R
W
9
TINIM18 (TIN18 interrupt request mask bit)
1: Mask (disable) interrupt request
10
TINIM17 (TIN17 interrupt request mask bit)
11
TINIM16 (TIN16 interrupt request mask bit)
12
TINIM15 (TIN15 interrupt request mask bit) (Note 1)
13
TINIM14 (TIN14 interrupt request mask bit) (Note 1)
14
TINIM13 (TIN13 interrupt request mask bit) (Note 1)
15
TINIM12 (TIN12 interrupt request mask bit) (Note 1)
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
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10
10.2 Common Units of Multijunction Timers
TIN1219IST <H'0080 023C>
TIN1219IMA <H'0080 023D>
TIN19edge
Data bus
8-source inputs
TINIS19
b0
b8
F/F
TINIM19
F/F
(Level)
TIN12–19 input interrupt request
IRQ10
TIN18edge
TINIS18
b1
b9
F/F
TINIM18
F/F
TIN17edge
b2
TINIS17
F/F
b10
TINIM17
F/F
TIN16edge
b3
TINIS16
F/F
TINIM16
b11
F/F
TIN15edge
(Note 1)
TINIS15
b4
F/F
TINIM15
b12
TIN14edge
(Note 1)
b5
b13
TIN13edge
(Note 1)
b6
b14
F/F
TINIS14
F/F
TINIM14
F/F
TINIS13
F/F
TINIM13
F/F
TIN12edge
(Note 1)
TINIS12
b7
F/F
b15
TINIM12
F/F
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins
and the selected function therefore has no effect.
Figure 10.2.14 Block Diagram of TIN12–19 Input Interrupt Request
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10
10.2 Common Units of Multijunction Timers
TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS)
b0
1
2
3
4
5
6
<Address: H’0080 023E>
b7
TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
TINIS23 (TIN23 interrupt request status bit)
0: Interrupt not requested
R(Note 1)
1
TINIS22 (TIN22 interrupt request status bit)
1: Interrupt requested
2
TINIS21 (TIN21 interrupt request status bit)
3
TINIS20 (TIN20 interrupt request status bit)
4
TINIM23 (TIN23 interrupt request mask bit)
0: Enable interrupt request
5
TINIM22 (TIN22 interrupt request mask bit)
1: Mask (disable) interrupt request
6
TINIM21 (TIN21 interrupt request mask bit)
7
TINIM20 (TIN20 interrupt request mask bit)
R
W
W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIN2023IMS <H'0080 023E>
TIN23edge
Data bus
TINIS23
b0
b4
29-source inputs
F/F
TINIM23
F/F
(Level)
TIN20-29 input interrupt request
IRQ11
TIN22edge
TINIS22
b1
b5
F/F
TINIM22
F/F
TIN21edge
b2
TINIS21
F/F
b6
TINIM21
F/F
TIN20edge
b3
TINIS20
F/F
TINIM20
b7
F/F
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins
and the selected function therefore has no effect.
Figure 10.2.15 Block Diagram of TIN20-29 Input Interrupt Request
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3 TOP (Output-Related 16-Bit Timer)
10.3.1 Outline of TOP
TOP (Timer OutPut) is an output-related 16-bit timer, whose operation mode can be selected from the following
by mode switching in software:
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode
The table below shows specifications of TOP. The diagram in the next page shows a block diagram of TOP.
Table 10.3.1 Specifications of TOP (Output-Related 16-Bit Timer)
Item
Specification
Number of channels
11 channels
Counter
16-bit down-counter
Reload register
16-bit reload register
Correction register
16-bit correction register
Timer startup
Started by writing to the enable bit in software or enabled by external input (rising or
falling edge or both)
Operation mode
<With correction function>
• Single-shot output mode
• Delayed single-shot output mode
<Without correction function>
• Continuous output mode
Interrupt request generation
Can be generated by a counter underflow
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10
10.3 TOP (Output-Related 16-Bit Timer)
Clock bus
Input event bus
Output event bus
3210 3210
0123
TOP 0
Reload register
clk
Down-counter
udf
IRQ2
F/F0
TO 0 (P110)
F/F1
TO 1 (P111)
F/F2
TO 2 (P112)
F/F3
TO 3 (P113)
F/F4
TO 4 (P114)
F/F5
TO 5 (P115)
S
F/F6
TO 6 (P116)
S
F/F7
TO 7 (P117)
S
F/F8
TO 8 (P100)
S
F/F9
TO 9 (P101)
S
F/F10
TO 10 (P102)
Correction register
S
(16-bit)
en
IRQ2
TCLK0 (P124)
clk
TCLK0S
TOP 1
udf
IRQ2
IRQ9
TIN0 (P150)
en
clk
en
TOP 2
udf
IRQ2
TIN0S
clk
S
en
TOP 3
udf
IRQ2
DRQ7
clk
en
TOP 4
udf
IRQ2
clk
en
TOP 5
udf
IRQ1
clk
S
S
clk
en
TOP 6
udf
en
TOP 7
udf
IRQ1
S
S
S
IRQ6
clk
clk
clk
en
TOP 8
udf
IRQ6
en
TOP 9
udf
IRQ5
en
TOP 10
udf
3210 3210
0123
F/F
:Output flip-flop
S
: Selector
Figure 10.3.1 Block Diagram of TOP (Output-Related 16-Bit Timer)
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10.3 TOP (Output-Related 16-Bit Timer)
10.3.2 Outline of Each Mode of TOP
Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected.
(1) Single-shot output mode
In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload
register, the counter is loaded with the content of the reload register and starts counting synchronously with
the count clock. The counter counts down and stops when it underflows after reaching the minimum count.
The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a
single-shot pulse waveform in width of (reload register set value + 1) only once. An interrupt request can be
generated when the counter underflows.
(2) Delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the count
clock. The first time the counter underflows, it is loaded with the reload register value and continues counting
down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first
time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) after a finite
time equal to (first set value of counter + 1) only once.
An interrupt request can be generated when the counter underflows first time and next.
(3) Continuous output mode
In continuous output mode, the timer counts down starting from the set value of the counter and when the
counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each
time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of
(reload register set value + 1).
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the count
clock and when the minimum count is reached, generates an underflow. This underflow causes the counter
to be loaded with the content of the reload register and start counting over again. Thereafter, this operation is
repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in
software.
The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a
waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each
time the counter underflows.
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10
10.3 TOP (Output-Related 16-Bit Timer)
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output
is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is
inverted.
Write to the enable bit
BCLK
Count clock period
Count clock
Enable
Count clock-dependent
delay
F/F operation (Note 1)
Inverted
Note 1: This applies to the case where F/F output is inverted when the timer is enabled.
Figure 10.3.2 Count Clock Dependent Delay
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.3 TOP Related Register Map
Shown below is a TOP related register map.
TOP Related Register Map (1/2)
Address
+0 address
b0
H'0080 0240
H'0080 0242
H'0080 0244
H'0080 0246
|
H'0080 0250
H'0080 0252
H'0080 0254
H'0080 0256
|
H'0080 0260
H'0080 0262
H'0080 0264
H'0080 0266
|
H'0080 0270
H'0080 0272
H'0080 0274
H'0080 0276
|
H'0080 0280
H'0080 0282
H'0080 0284
H'0080 0286
|
H'0080 0290
H'0080 0292
H'0080 0294
H'0080 0296
H'0080 0298
+1 address
b7 b8
TOP0 Counter
(TOP0CT)
TOP0 Reload Register
(TOP0RL)
(Use inhibited area)
See pages
b15
10-54
10-55
TOP0 Correction Register
(TOP0CC)
(Use inhibited area)
10-56
TOP1 Counter
(TOP1CT)
TOP1 Reload Register
(TOP1RL)
(Use inhibited area)
10-54
10-55
TOP1 Correction Register
(TOP1CC)
(Use inhibited area)
10-56
TOP2 Counter
(TOP2CT)
TOP2 Reload Register
(TOP2RL)
(Use inhibited area)
10-54
10-55
TOP2 Correction Register
(TOP2CC)
(Use inhibited area)
10-56
TOP3 Counter
(TOP3CT)
TOP3 Reload Register
(TOP3RL)
(Use inhibited area)
10-54
10-55
TOP3 Correction Register
(TOP3CC)
(Use inhibited area)
10-56
TOP4 Counter
(TOP4CT)
TOP4 Reload Register
(TOP4RL)
(Use inhibited area)
10-54
10-55
TOP4 Correction Register
(TOP4CC)
(Use inhibited area)
10-56
TOP5 Counter
(TOP5CT)
TOP5 Reload Register
(TOP5RL)
(Use inhibited area)
10-54
TOP5 Correction Register
(TOP5CC)
(Use inhibited area)
10-47
10-55
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10
10.3 TOP (Output-Related 16-Bit Timer)
TOP Related Register Map (2/2)
Address
+0 address
+1 address
b0
b7 b8
TOP0–5 Control Register 0
(TOP05CR0)
H'0080 029A
H'0080 029C
|
H'0080 02A0
H'0080 02A2
H'0080 02A4
H'0080 02A6
H'0080 02A8
H'0080 02AA
|
H'0080 02B0
H'0080 02B2
H'0080 02B4
H'0080 02B6
|
H'0080 02C0
H'0080 02C2
H'0080 02C4
H'0080 02C6
|
H'0080 02D0
H'0080 02D2
H'0080 02D4
H'0080 02D6
|
H'0080 02E0
H'0080 02E2
H'0080 02E4
H'0080 02E6
H'0080 02E8
H'0080 02EA
|
H'0080 02FA
H'0080 02FC
H'0080 02FE
(Use inhibited area)
See pages
b15
10-50
TOP0–5 Control Register 1
(TOP05CR1)
10-50
(Use inhibited area)
TOP6 Counter
(TOP6CT)
TOP6 Reload Register
(TOP6RL)
(Use inhibited area)
10-54
10-55
TOP6 Correction Register
(TOP6CC)
(Use inhibited area)
10-56
TOP6,7 Control Register
(TOP67CR)
(Use inhibited area)
10-52
TOP7 Counter
(TOP7CT)
TOP7 Reload Register
(TOP7RL)
(Use inhibited area)
10-54
10-55
TOP7 Correction Register
(TOP7CC)
(Use inhibited area)
10-56
TOP8 Counter
(TOP8CT)
TOP8 Reload Register
(TOP8RL)
(Use inhibited area)
10-54
10-55
TOP8 Correction Register
(TOP8CC)
(Use inhibited area)
10-56
TOP9 Counter
(TOP9CT)
TOP9 Reload Register
(TOP9RL)
(Use inhibited area)
10-54
10-55
TOP9 Correction Register
(TOP9CC)
(Use inhibited area)
10-56
TOP10 Counter
(TOP10CT)
TOP10 Reload Register
(TOP10RL)
(Use inhibited area)
10-54
10-55
TOP10 Correction Register
(TOP10CC)
(Use inhibited area)
10-56
TOP8–10 Control Register
(TOP810CR)
(Use inhibited area)
10-53
TOP External Enable Permit Register
(TOPEEN)
TOP Enable Protect Register
(TOPPRO)
TOP Count Enable Register
(TOPCEN)
10-57
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10-57
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MULTIJUNCTION TIMERS
10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.4 TOP Control Registers
The TOP control registers are used to select operation modes of TOP0–10 (single-shot output, delayed singleshot output or continuous output mode), as well as select the count enable and count clock sources. Following
four TOP control registers are provided for each timer group.
• TOP0–5 Control Register 0 (TOP05CR0)
• TOP0–5 Control Register 1 (TOP05CR1)
• TOP6,7 Control Register (TOP67CR)
• TOP8–10 Control Register (TOP810CR)
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10.3 TOP (Output-Related 16-Bit Timer)
TOP0–5 Control Register 0 (TOP05CR0)
b0
1
2
TOP3M
0
3
4
TOP2M
0
0
<Address: H’0080 029A>
5
6
TOP1M
0
0
7
8
9
TOP0M
0
0
10
11
12
13
TOP05ENS
0
0
0
0
14
b15
TOP05CKS
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
0, 1
TOP3M (TOP3 operation mode select bit)
00: Single-shot output mode
2, 3
TOP2M (TOP2 operation mode select bit)
01: Delayed single-shot output mode
4, 5
TOP1M (TOP1 operation mode select bit)
10: Continuous output mode
6, 7
TOP0M (TOP0 operation mode select bit)
11: – ditto –
8
No function assigned. Fix to "0".
9–11
TOP05ENS
TOP0–5 enable source select bit
000:
001:
010:
011:
100:
101:
110:
External TIN0 input
– ditto –
– ditto –
– ditto –
Input event bus 0
Input event bus 1
Input event bus 2
R
W
R
W
0
0
R
W
0
0
R
W
111: Input event bus 3
12, 13
No function assigned. Fix to "0".
14, 15
TOP05CKS
TOP0–5 clock source select bit
00:
01:
10:
11:
Clock
Clock
Clock
Clock
bus
bus
bus
bus
0
1
2
3
Notes: • This register must always be accessed in halfwords.
• Operation mode can only be set or changed while the counter is inactive.
TOP0–5 Control Register 1 (TOP05CR1)
b8
9
10
11
12
13
<Address: H’0080 029D>
14
TOP5M
0
0
0
0
0
b15
TOP4M
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
8–11
No function assigned. Fix to "0".
12, 13
TOP5M (TOP5 operation mode select bit)
00: Single-shot output mode
14, 15
TOP4M (TOP4 operation mode select bit)
01: Delayed single-shot output mode
10: Continuous output mode
11: – ditto –
W
0
0
R
W
Note: • Operation mode can only be set or changed while the counter is inactive.
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MULTIJUNCTION TIMERS
10
10.3 TOP (Output-Related 16-Bit Timer)
Clock bus
3210
Input event bus
3210
S
clk
clk
clk
clk
clk
clk
TIN0 (P150)
TIN0S
en
TOP 0
en
TOP 1
en
TOP 2
en
TOP 3
en
TOP 4
en
TOP 5
S
S : Selector
Note: • This diagram only illustrates TOP control registers and is partly omitted.
Figure 10.3.3 Outline Diagram of TOP0–5 Clock and Enable Inputs
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10.3 TOP (Output-Related 16-Bit Timer)
TOP6,7 Control Register (TOP67CR)
b0
1
2
TOP7
ENS
0
0
3
4
<Address: H’0080 02AA>
5
6
7
8
9
TOP7M
0
10
11
12
13
TOP67ENS
0
0
0
0
0
0
0
0
14
b15
TOP67CKS
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
0
No function assigned. Fix to "0".
0
0
1
TOP7ENS
TOP7 enable source select bit
0: Result selected by TOP67ENS bit
1: TOP6 output
R
W
2, 3
TOP7M
TOP7 operation mode select bit
00:
01:
10:
11:
R
W
4, 5
No function assigned. Fix to "0".
0
0
6, 7
TOP6M
TOP6 operation mode select bit
R
W
8
No function assigned. Fix to "0".
0
0
9–11
TOP67ENS
TOP6, TOP7 enable source select bit
R
W
00:
01:
10:
11:
R
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
– ditto –
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
– ditto –
000: External TIN1 input
001: – ditto –
010: – ditto –
011: – ditto –
100: Input event bus 0
101: Input event bus 1
110: Input event bus 2
(Note 1)
(Note 1)
(Note 1)
(Note 1)
W
111: Input event bus 3
12, 13
No function assigned. Fix to "0".
14, 15
TOP67CKS
TOP6, TOP7 clock source select bit
00: Clock
01: Clock
10: Clock
11: Clock
bus
bus
bus
bus
0
1
2
3
0
0
R
W
Note 1:Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Notes: • This register must always be accessed in halfwords.
• Operation mode can only be set or changed while the counter is inactive.
Clock bus
Input event bus
3210 3210
clk
S
clk
S
en
TOP 6
udf
en
TOP 7
udf
S
S : Selector
Note: • This diagram only illustrates TOP control registers and is partly omitted.
Figure 10.3.4 Outline Diagram of TOP6, TOP7 Clock and Enable Inputs
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10
10.3 TOP (Output-Related 16-Bit Timer)
TOP8–10 Control Register (TOP810CR)
b0
1
2
3
4
TOP10M
0
0
0
<Address: H’0080 02EA>
5
6
7
8
9
10
11
0
TOP810
ENS
0
TOP9M
0
0
0
0
0
0
0
12
13
14
b15
TOP810CKS
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
0, 1
No function assigned. Fix to "0".
2, 3
TOP10M (TOP10 operation mode select bit)
00: Single-shot output mode
4, 5
TOP9M (TOP9 operation mode select bit)
01: Delayed single-shot output mode
6, 7
TOP8M (TOP8 operation mode select bit)
10: Continuous output mode
W
0
0
R
W
11: – ditto –
8–10
No function assigned. Fix to "0".
11
TOP810ENS
TOP8–10 enable source select bit
12, 13
No function assigned. Fix to "0".
14, 15
TOP810CKS
TOP8–10 clock source select bit
0: External TIN2 input (Note 1)
1: Input event bus 3
00: Clock bus 0
01: Clock bus 1
10: Clock bus 2
0
0
R
W
0
0
R
W
11: Clock bus 3
Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Notes: • This register must always be accessed in halfwords.
• Operation mode can only be set or changed while the counter is inactive.
Clock bus
3210
Input event bus
3210
S
clk
clk
clk
en
TOP 8
en
TOP 9
en
TOP 10
S
S : Selector
Note: • This diagram only illustrates TOP control registers and is partly omitted.
Figure 10.3.5 Outline Diagram of TOP8–10 Clock and Enable Inputs
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.5 TOP Counters (TOP0CT–TOP10CT)
TOP0 Counter (TOP0CT)
TOP1 Counter (TOP1CT)
TOP2 Counter (TOP2CT)
TOP3 Counter (TOP3CT)
TOP4 Counter (TOP4CT)
TOP5 Counter (TOP5CT)
TOP6 Counter (TOP6CT)
TOP7 Counter (TOP7CT)
TOP8 Counter (TOP8CT)
TOP9 Counter (TOP9CT)
TOP10 Counter (TOP10CT)
<Address: H’0080 0240>
<Address: H’0080 0250>
<Address: H’0080 0260>
<Address: H’0080 0270>
<Address: H’0080 0280>
<Address: H’0080 0290>
<Address: H’0080 02A0>
<Address: H’0080 02B0>
<Address: H’0080 02C0>
<Address: H’0080 02D0>
<Address: H’0080 02E0>
b0
1
2
3
4
5
6
?
?
?
?
?
?
?
7
8
9
10
11
12
13
14
?
?
?
?
?
?
b15
TOP0CT–TOP10CT
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
TOP0CT–TOP10CT
16-bit counter value
R
W
Note: • This register must always be accessed in halfwords.
The TOP counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software
or by external input), the counter starts counting synchronously with the count clock.
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)
TOP0 Reload Register (TOP0RL)
TOP1 Reload Register (TOP1RL)
TOP2 Reload Register (TOP2RL)
TOP3 Reload Register (TOP3RL)
TOP4 Reload Register (TOP4RL)
TOP5 Reload Register (TOP5RL)
TOP6 Reload Register (TOP6RL)
TOP7 Reload Register (TOP7RL)
TOP8 Reload Register (TOP8RL)
TOP9 Reload Register (TOP9RL)
TOP10 Reload Register (TOP10RL)
<Address: H’0080 0242>
<Address: H’0080 0252>
<Address: H’0080 0262>
<Address: H’0080 0272>
<Address: H’0080 0282>
<Address: H’0080 0292>
<Address: H’0080 02A2>
<Address: H’0080 02B2>
<Address: H’0080 02C2>
<Address: H’0080 02D2>
<Address: H’0080 02E2>
b0
1
2
3
4
5
6
?
?
?
?
?
?
?
7
8
9
10
11
12
13
14
b15
?
?
?
?
?
?
?
TOP0RL–TOP10RL
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
TOP0RL–TOP10RL
16-bit reload register value
R
W
Note: • This register must always be accessed in halfwords.
The TOP reload registers are used to load data into the TOP counter registers (TOP0CT–TOP10CT). The
content of the reload register is loaded into the counter in the following cases:
• When the counter is enabled in single-shot output mode
• When the counter underflowed in delayed single-shot or continuous output mode
Simply because data is written to the reload register does not mean that the data is loaded into the counter. The
counter is loaded with data in only the above cases.
Note that reloading of data after an underflow is performed synchronously with a clock pulse at which the
counter underflowed.
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.7 TOP Correction Registers (TOP0CC–TOP10CC)
TOP0 Correction Register (TOP0CC)
TOP1 Correction Register (TOP1CC)
TOP2 Correction Register (TOP2CC)
TOP3 Correction Register (TOP3CC)
TOP4 Correction Register (TOP4CC)
TOP5 Correction Register (TOP5CC)
TOP6 Correction Register (TOP6CC)
TOP7 Correction Register (TOP7CC)
TOP8 Correction Register (TOP8CC)
TOP9 Correction Register (TOP9CC)
TOP10 Correction Register (TOP10CC)
<Address: H’0080 0246>
<Address: H’0080 0256>
<Address: H’0080 0266>
<Address: H’0080 0276>
<Address: H’0080 0286>
<Address: H’0080 0296>
<Address: H’0080 02A6>
<Address: H’0080 02B6>
<Address: H’0080 02C6>
<Address: H’0080 02D6>
<Address: H’0080 02E6>
b0
1
2
3
4
5
6
?
?
?
?
?
?
?
7
8
9
10
11
12
13
14
?
?
?
?
?
?
b15
TOP0CC–TOP10CC
?
?
?
(Acceptable range of values: +32,767 to –32,768)
<After reset: Undefined>
b
Bit Name
0–15
TOP0CC–TOP10CC
Function
16-bit correction register value
R
W
R
W
Note: • This register must always be accessed in halfwords.
The TOP correction registers are used to correct the TOP counter value by adding or subtracting in the middle
of operation. To increase or reduce the counter value, write to this correction register a value by which the
counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the
correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the
correction register.
The counter is corrected synchronously with a clock pulse next to one at which the correction value was written
to the TOP correction register. If the counter is corrected this way, note that because one down count in that
clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example,
if the initial counter value is 10 and the value 3 is written to the correction register when the counter has counted
down to 5, then the counter counts a total of 15 before it underflows.
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.8 TOP Enable Control Registers
TOP External Enable Permit Register (TOPEEN)
b0
1
0
2
0
3
0
<Address: H’0080 02FA>
4
5
6
7
8
9
0
TOP10
EEN
0
TOP9
EEN
0
TOP8
EEN
0
TOP7
EEN
0
TOP6
EEN
0
10
11
12
TOP5
EEN
0
TOP4
EEN
0
TOP3
EEN
0
13
14
TOP2
EEN
0
TOP1
EEN
0
b15
TOP0
EEN
0
<After reset: H’0000>
b
Bit Name
Function
0–4
No function assigned. Fix to "0".
5
TOP10EEN (TOP10 external enable permit bit)
0: Disable external enable
6
TOP9EEN (TOP9 external enable permit bit)
1: Enable external enable
7
TOP8EEN (TOP8 external enable permit bit)
8
TOP7EEN (TOP7 external enable permit bit)
9
TOP6EEN (TOP6 external enable permit bit)
10
TOP5EEN (TOP5 external enable permit bit)
11
TOP4EEN (TOP4 external enable permit bit)
12
TOP3EEN (TOP3 external enable permit bit)
13
TOP2EEN (TOP2 external enable permit bit)
14
TOP1EEN (TOP1 external enable permit bit)
15
TOP0EEN (TOP0 external enable permit bit)
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords.
The TOP External Enable Permit Register controls enable operation on TOP counters from external devices by
enabling or disabling it.
TOP Enable Protect Register (TOPPRO)
b0
1
0
2
0
3
0
<Address: H’0080 02FC>
4
5
6
7
8
9
10
11
12
13
14
b15
0
TOP10
PRO
0
TOP9
PRO
0
TOP8
PRO
0
TOP7
PRO
0
TOP6
PRO
0
TOP5
PRO
0
TOP4
PRO
0
TOP3
PRO
0
TOP2
PRO
0
TOP1
PRO
0
TOP0
PRO
0
<After reset: H’0000>
b
Bit Name
0–4
No function assigned. Fix to "0".
Function
5
TOP10PRO (TOP10 enable protect bit)
0: Enable for rewriting
6
TOP9PRO (TOP9 enable protect bit)
1: Protect against rewriting
7
TOP8PRO (TOP8 enable protect bit)
8
TOP7PRO (TOP7 enable protect bit)
9
TOP6PRO (TOP6 enable protect bit)
10
TOP5PRO (TOP5 enable protect bit)
11
TOP4PRO (TOP4 enable protect bit)
12
TOP3PRO (TOP3 enable protect bit)
13
TOP2PRO (TOP2 enable protect bit)
14
TOP1PRO (TOP1 enable protect bit)
15
TOP0PRO (TOP0 enable protect bit)
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords.
The TOP Enable Protect Register controls rewriting of the TOP count enable bit by enabling for or protecting it
against rewriting.
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10
10.3 TOP (Output-Related 16-Bit Timer)
TOP Count Enable Register (TOPCEN)
b0
1
0
2
0
3
0
<Address: H’0080 02FE>
4
5
6
7
8
9
10
11
12
13
14
b15
0
TOP10
CEN
0
TOP9
CEN
0
TOP8
CEN
0
TOP7
CEN
0
TOP6
CEN
0
TOP5
CEN
0
TOP4
CEN
0
TOP3
CEN
0
TOP2
CEN
0
TOP1
CEN
0
TOP0
CEN
0
<After reset: H’0000>
b
Bit Name
Function
0–4
No function assigned. Fix to "0".
5
TOP10CEN (TOP10 count enable bit)
0: Stop counting
6
TOP9CEN (TOP9 count enable bit)
1: Enable counting
7
TOP8CEN (TOP8 count enable bit)
8
TOP7CEN (TOP7 count enable bit)
9
TOP6CEN (TOP6 count enable bit)
10
TOP5CEN (TOP5 count enable bit)
11
TOP4CEN (TOP4 count enable bit)
12
TOP3CEN (TOP3 count enable bit)
13
TOP2CEN (TOP2 count enable bit)
14
TOP1CEN (TOP1 count enable bit)
15
TOP0CEN (TOP0 count enable bit)
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords.
The TOP Count Enable Register controls operation of TOP counters. To enable any TOP counter in software,
enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TOP
counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0".
In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable
bit is automatically reset to "0". Therefore, the TOP0-10 Count Enable Register when accessed for read serves
as a status register indicating whether the counter is operating or idle.
TOPm external enable
(TOPmEEN)
F/F
TINn
Input processing
selection
TINnS
EN-ON
Event bus
TOPm count enable
(TOPmCEN)
TOP enable control
F/F
Dn
TOPm enable protect
(TOPmPRO)
WR
F/F
WR
Figure 10.3.6 Configuration of the TOP Enable Circuit
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)
(1) Outline of TOP single-shot output mode
In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload
register, the counter is loaded with the content of the reload register and starts counting synchronously with
the count clock. The counter counts down and stops when it underflows after reaching the minimum count.
The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high or
vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. An interrupt request can be generated when the counter underflows. The count
value is (reload register set value + 1).
For example, if the initial reload register value is 7, then the count value is 8.
Count value = 8
1
2
3
4
5
6
8
7
Count clock
Enable
(Note 1)
(7)
6
Counter
Reload
register
H'FFFF
5
4
3
2
1
0
7
F/F output
Interrupt request
* A count clock dependent delay is included before
F/F output changes state after the timer is enabled.
Underflow
Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7.
Note: • This diagram does not show detailed timing information.
Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode
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10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined,
and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter,
letting it start counting. Thereafter, it continues counting down until it underflows after reaching the minimum
count.
Enabled
(by writing to the enable bit
or by external input)
Disabled
(by underflow)
Count clock
Enable bit
H'FFFF
H'FFFF
Indeterminate
value
H'A000
Starts counting down from
the reload register set value
H'(A000-1)
Counter
H'0000
Reload register
Correction register
H'A000
(Unused)
F/F output
Data inverted
by enable
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode
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10.3 TOP (Output-Related 16-Bit Timer)
(2) Correction function of TOP single-shot output mode
To change the counter value while in progress, write to the TOP correction register a value by which the
counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the
correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the
correction register.
The counter is corrected synchronously with a count clock pulse next to one at which the correction value was
written to the TOP correction register. If the counter is corrected this way, note that because one down count in
that clock period is canceled, the counter value actually is corrected by (correction register value + 1).
For example, if the initial counter value is 7 and the value 3 is written to the correction register when the
counter has counted down to 3, then the counter counts a total of 12 before it underflows.
Count value = (7 + 1) + (3 + 1) = 12
1
2
3
4
5
6
7
8
9
10
11
12
Count clock
Count clock
dependent delay
Enable
(Note 1)
(7)
Counter
Reload
register
H'FFFF
6
5
6
4
3
+3
5
4
3
2
1
0
7
Correction
register
3
Interrupt request
Underflow
Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7.
Note: • This diagram does not show detailed timing information.
Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode When Count is Corrected
When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter
overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow.
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10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the reload register is initially set to H’8000. When the timer starts, the reload register
value is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is
written to the correction register when the counter has counted down to H’5000. As a result of this correction,
the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 + H’4000 + 1)
before it stops.
Enabled
(by writing to the enable bit
or by external input)
Disabled
(by underflow)
Count clock
Enable bit
Write to the
correction register
H'FFFF
H'FFFF
Undefined
value
Counter
H'8000
H'5000+H'4000
H'(8000-1)
H'5000
H'0000
Reload register
Correction register
H'8000
H'4000
Undefined
F/F output
Data inverted
by enable
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected
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10.3 TOP (Output-Related 16-Bit Timer)
(3) Precautions on using TOP single-shot output mode
The following describes precautions to be observed when using TOP single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
• When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter
overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow.
Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count.
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10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the reload register is initially set to H’FFF8. When the timer starts, the reload register
value is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is
written to the correction register when the counter has counted down to H’FFF0. As a result of this correction,
the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request is generated
for an erroneous overflowed count.
Enabled
Disabled
(by writing to the enable bit
(by underflow)
or by external input)
Count clock
Enable bit
Write to the
correction register
Overflow occurs
H'(FFF0+0014)
H'FFFF
H'FFFF
H'FFF8
H'(FFF8-1)
Undefined
value
H'FFF0
Counter
H'0004
Actual count after overflow
H'0000
Reload register
Correction register
H'FFF8
H'0014
Undefined
F/F output
Data inverted
by enable
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction
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10
10.3 TOP (Output-Related 16-Bit Timer)
10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)
(1) Outline of TOP delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the count
clock. The first time the counter underflows, it is loaded with the reload register value and continues counting
down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low to high
or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width
of (reload register set value + 1) after a finite time equal to (first set value of counter + 1) only once.
An interrupt request can be generated when the counter underflows first time and next.
The (counter set value + 1) and (reload register set value + 1) are effective as count values.
For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as
shown below.
Count value = (4 + 1) + (5 + 1) = 11
1
2
3
4
6
5
8
7
9
10
11
Count clock
Count clock
dependent delay
Enable
Counter
4
(Note 1)
(5)
3
2
1
Reload
register
0
H'FFFF
4
3
2
1
0
5
F/F output
Interrupt request
Underflow
Underflow
Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 5.
Note: • This diagram does not show detailed timing information.
Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode
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10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively.
When the timer is enabled, the counter starts counting down and when it underflows after reaching the
minimum count, the counter is loaded with the content of the reload register and continues counting down.
The counter stops when it underflows second time.
Enabled
(by writing to the enable bit
or by external input)
Underflow
(second time)
Underflow
(first time)
Count clock
Enable bit
H'FFFF
H'FFFF
H'F000
H'A000
H'(F000-1)
Count down from the
counter's set value
Counter
Count down from the
reload register's
set value
H'0000
H'F000
Reload register
Correction register
(Unused)
F/F output
Data inverted
by underflow
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.13 Typical Operation in TOP Delayed Single-shot Output Mode
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10.3 TOP (Output-Related 16-Bit Timer)
(2) Correction function of TOP delayed single-shot output mode
To change the counter value while in progress, write to the TOP correction register a value by which the
counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the
correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the
correction register.
The counter is corrected synchronously with a count clock pulse next to one at which the correction value was
written to the TOP correction register. If the counter is corrected this way, note that because one down count in
that clock period is canceled, the counter value actually is corrected by (correction register value + 1).
For example, if the reload register value is 7 and the value 3 is written to the correction register when the
counter has counted down to 3 after being reloaded, then the counter counts a total of 12 after being reloaded
before it underflows.
Count value after being reloaded = (7 + 1) + (3 + 1) = 12
1
2
3
4
5
6
7
8
9
10
11
12
Count clock
Enable = "H"
(Note 1)
(7)
6
Counter
H'FFFF
5
6
4
3
0
5
4
3
2
1
0
+3
Reload
register
7
Correction
register
3
Interrupt request
Underflow
Note 1: What actually is seen in the cycle immediately after reload is the H'FFFF (underflow value), and not 7.
Note: • This diagram does not show detailed timing information.
Figure 10.3.14 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected
When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter
overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow.
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10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively.
When the timer is enabled, the counter starts counting down and when it underflows first time after reaching
the minimum count, the counter is loaded with the content of the reload register and continues counting
down. In the diagram below, the value H’0008 is written to the correction register when the counter has
counted down to H’9000. As a result of this correction, the counter has its count value increased to H’9008
and counts (H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.
Enabled
(by writing to the enable bit
or by external input)
Underflow
(first time)
Underflow
(second time)
Count clock
Enable bit
Write to the
correction register
H'FFFF
H'(F000+0008+1)
H'F000
H'9000+H'0008
Counter
H'A000
H'9000
H'0000
Reload register
Correction register
H'F000
H'0008
Undefined
F/F output
Data inverted
by underflow
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected
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10.3 TOP (Output-Related 16-Bit Timer)
(3) Precautions on using TOP delayed single-shot output mode
The following describes precautions to be observed when using TOP delayed single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of
an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false
interrupt request is generated for an underflow that includes the overflowed count.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
Reload due to underflow
Count clock
Enable bit
"H"
Count down from the
reload register value
Reload cycle
Counter value
Reload register
H'0001
H'0000
H'FFFF
H'AAA9
H'AAA8
H'(AAAA-1)
H'(AAAA-2)
H'AAAA
What is seen during reload cycle is always H'FFFF,
and not the reload register value (in this case, H'AAAA).
Figure 10.3.16 Counter Value Immediately after Underflow
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10.3 TOP (Output-Related 16-Bit Timer)
10.3.11 Operation in TOP Continuous Output Mode (without Correction Function)
(1) Outline of TOP continuous output mode
In continuous output mode, the timer counts down starting from the set value of the counter and when the
counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each
time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of
(reload register set value + 1).
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the count
clock and when the minimum count is reached, generates an underflow. This underflow causes the counter
to be loaded with the content of the reload register and start counting over again. Thereafter, this operation is
repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in
software.
The F/F output waveform in continuous output mode is inverted (F/F output level changes from low to high or
vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops
counting. An interrupt request can be generated each time the counter underflows.
The (counter set value + 1) and (reload register set value + 1) are effective as count values.
For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as
shown below.
Count value = 5
1
2
3
Count value = 6
4
5
1
2
3
4
5
Count value = 6
6
1
2
3
4
5
6
Count clock
Count clock
dependent delay
Enable
Counter
(Note 1)
(4)
3
(Note 2)
(5)
4
2
Reload
register
1
3
0
(Note 2)
(5)
4
2
1
0
(Note 2)
(5)
3
2
1
0
5
F/F output
Interrupt request
Underflow
Underflow
Underflow
Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 4.
Note 2: What actually is seen in the cycle immediately after reload is H'FFFF (underflow value), and not 5.
Note: • This diagram does not show detailed timing information.
Figure 10.3.17 Example of Counting in TOP Continuous Output Mode
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10.3 TOP (Output-Related 16-Bit Timer)
In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively.
When the timer is enabled, the counter starts counting down and when it underflows after reaching the
minimum count, the counter is loaded with the content of the reload register and continues counting down.
Enabled
(by writing to the enable bit
or by external input)
Underflow
(first time)
Underflow
(second time)
Count clock
Enable bit
H'FFFF
H'FFFF
H'(E000-1)
H'E000
H'A000
Count down from the
counter's set value
Counter
H'FFFF
H'(E000-1)
Count down from the
reload register's
set value
Count down from the
reload register's
set value
H'0000
H'E000
Reload register
Correction register
(Unused)
F/F output
Data inverted by
enable
Data inverted
by underflow
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.18 Typical Operation in TOP Continuous Output Mode
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10.3 TOP (Output-Related 16-Bit Timer)
(2) Precautions on using TOP continuous output mode
The following describes precautions to be observed when using TOP continuous output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.1 Outline of TIO
TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the
following by mode switching in software, one at a time:
<Input modes>
• Measure clear input mode
• Measure free-run input mode
• Noise processing input mode
<Output modes without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode
The table below shows specifications of TIO. The diagram in the next page shows a block diagram of TIO.
Table 10.4.1 Specifications of TIO (Input/Output-Related 16-Bit Timer)
Item
Specification
Number of channels
10 channels
Counter
16-bit down-counter
Reload register
16-bit reload register
Measure register
16-bit capture register
Timer startup
Started by writing to the enable bit in software or enabled by external input (rising or falling
or both edges or high or low level)
Operation mode
<Input modes>
• Measure clear input mode
• Measure free-run input mode
• Noise processing input mode
<Output modes without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode
Interrupt request generation
Can be generated by a counter underflow
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10.4 TIO (Input/Output-Related 16-Bit Timer)
Clock bus
Input event bus
Output event bus
3210 3210
0123
TIO 0
Reload 0/measure register
IRQ0
clk
S
Down-counter
udf
S
F/F11
TO 11 (P103)
S
F/F12
TO 12 (P104)
S
F/F13
TO 13 (P105)
S
F/F14
TO 14 (P106)
S
F/F15
TO 15 (P107)
S
F/F16
TO 16 (P93)
S
F/F17
TO 17 (P94)
S
F/F18
TO 18 (P95)
F/F19
TO 19 (P96)
F/F20
TO 20 (P97)
Reload 1 register (Note 1)
IRQ12
(16-bit)
en/cap
TIN3S
TIN3 (P153)
S
IRQ0
clk
en/cap
TIO 1
udf
IRQ0
S
clk
en/cap
TIO 2
udf
IRQ0
S
clk
en/cap
TIO 3
udf
en/cap
TIO 4
udf
IRQ4
S
clk
S
PRS0
BCLK/2
PRS1
S
PRS2
IRQ4
TCLK1 (P125)
TCLK1S
S
clk
en/cap
TIO 5
udf
en/cap
TIO 6
udf
en/cap
TIO 7
udf
S
IRQ4
TCLK2 (P126)
TCLK2S
S
clk
S
IRQ4
S
clk
IRQ3
S
DMA0
clk
S
en/cap
TIO 8
udf
S
S
IRQ3
clk
S
en/cap
TIO 9
udf
S
3210
0123
3210
PRS0–2
: Prescaler
F/F : Flip-flop
S : Selector
Note 1: The reload 1 register is used in only PWM output mode.
Figure 10.4.1 Block Diagram of TIO (Input/Output-Related 16-Bit Timer)
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.2 Outline of Each Mode of TIO
Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected.
(1) Measure clear/free-run input modes
In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter
starts counting till when an external capture signal is entered.
After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at
that point in time is written into a register called the “measure register.”
In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter
starts counting down again. In measure free-run input mode, the counter continues counting down even after
capture and upon underflow, recycles to H’FFFF, from which it starts counting down again.
To stop the counter, disable count by writing to the enable bit in software. An interrupt request can be generated by a counter underflow or execution of a measure operation.
(2) Noise processing input mode
In noise processing input mode, the timer is used to detect that the input signal remained in the same state for
over a predetermined time.
In noise processing input mode, a high or low level on external input activates the counter and if the input
signal remains in the same state for over a predetermined time before the counter underflows, the counter
generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level
before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, the counter is reloaded with the initial count and restarts counting.
The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An
interrupt request can be generated by a counter underflow.
(3) PWM output mode (without correction function)
In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial
values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts
counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the
reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload
1 register values alternately each time an underflow occurs.
The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it
underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in
synchronism with PWM output period). An interrupt request can be generated at an even underflow after the
counter being enabled.
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MULTIJUNCTION TIMERS
10.4 TIO (Input/Output-Related 16-Bit Timer)
(4) Single-shot output mode (without correction function)
In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload
0 register, the counter is loaded with the reload 0 register value and starts counting synchronously with the
count clock. The counter counts down and when the minimum count is reached, stops upon underflow.
The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a
single-shot pulse waveform in width of (reload 0 register set value + 1) only once. An interrupt request can be
generated when the counter underflows.
(5) Delayed single-shot output mode (without correction function)
In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock. The first time the counter underflows, it is loaded with the reload 0 register value and continues
counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first
time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) after a
finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the
counter underflows first time and next.
(6) Continuous output mode (without correction function)
In continuous output mode, the timer counts down starting from the set value of the counter and when the
counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each
time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1).
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock and when the minimum count is reached, generates an underflow. This underflow causes the
counter to be loaded with the content of the reload 0 register and start counting over again. Thereafter, this
operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the
enable bit in software.
The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a
waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each
time the counter underflows.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output
is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is
inverted.
Write to the enable bit
BCLK
Count clock period
Count clock
Enable
Count clock-dependent
delay
F/F operation (Note 1)
Inverted
Note 1: This applies to the case where F/F output is inverted when the timer is enabled.
Figure 10.4.2 Count Clock Dependent Delay
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.3 TIO Related Register Map
Shown below is a TIO related register map.
TIO Related Register Map (1/2)
Address
+0 address
b0
H'0080 0300
H'0080 0302
H'0080 0304
|
H'0080 0310
H'0080 0312
H'0080 0314
H'0080 0316
H'0080 0318
H'0080 031A
H'0080 0322
H'0080 0324
H'0080 0326
|
H'0080 0330
H'0080 0332
H'0080 0334
H'0080 0336
|
H'0080 0340
H'0080 0342
H'0080 0344
H'0080 0346
H'0080 0348
|
10-90
10-89
10-88
TIO1 Reload 1 Register
(TIO1RL1)
TIO1 Reload 0/Measure Register
(TIO1RL0)
(Use inhibited area)
10-90
10-89
TIO0–3 Control Register 0
(TIO03CR0)
10-81
TIO0–3 Control Register 1
(TIO03CR1)
10-82
(Use inhibited area)
H'0080 0320
H'0080 034A
10-88
TIO1 Counter
(TIO1CT)
(Use inhibited area)
(Use inhibited area)
|
See pages
b15
TIO0 Reload 1 Register
(TIO0RL1)
TIO0 Reload 0/Measure Register
(TIO0RL0)
(Use inhibited area)
H'0080 0306
H'0080 031C
+1 address
b7 b8
TIO0 Counter
(TIO0CT)
(Use inhibited area)
TIO2 Counter
(TIO2CT)
(Use inhibited area)
10-88
TIO2 Reload 1 Register
(TIO2RL1)
TIO2 Reload 0/Measure Register
(TIO2RL0)
(Use inhibited area)
10-90
10-89
TIO3 Counter
(TIO3CT)
(Use inhibited area)
10-88
TIO3 Reload 1 Register
(TIO3RL1)
TIO3 Reload 0/Measure Register
(TIO3RL0)
(Use inhibited area)
10-90
10-89
TIO4 Counter
(TIO4CT)
(Use inhibited area)
10-88
TIO4 Reload 1 Register
(TIO4RL1)
TIO4 Reload 0/Measure Register
(TIO4RL0)
(Use inhibited area)
10-90
TIO4 Control Register
(TIO4CR)
10-89
TIO5 Control Register
(TIO5CR)
10-83
10-85
(Use inhibited area)
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10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO Related Register Map (2/2)
Address
+0 address
b0
H'0080 0350
H'0080 0352
H'0080 0354
|
H'0080 0360
H'0080 0362
H'0080 0364
H'0080 0366
H'0080 0368
H'0080 0372
H'0080 0374
H'0080 0376
|
H'0080 0380
H'0080 0382
H'0080 0384
H'0080 0386
H'0080 0388
|
H'0080 0390
H'0080 0392
H'0080 0394
H'0080 0396
|
H'0080 03BC
H'0080 03BE
10-90
10-89
10-88
TIO6 Reload 1 Register
(TIO6RL1)
TIO6 Reload 0/Measure Register
(TIO6RL0)
(Use inhibited area)
10-90
10-89
TIO7 Control Register
(TIO7CR)
10-86
10-87
(Use inhibited area)
H'0080 0370
H'0080 038A
10-88
TIO6 Counter
(TIO6CT)
(Use inhibited area)
TIO6 Control Register
(TIO6CR)
|
See pages
b15
TIO5 Reload 1 Register
(TIO5RL1)
TIO5 Reload 0/Measure Register
(TIO5RL0)
(Use inhibited area)
H'0080 0356
H'0080 036A
+1 address
b7 b8
TIO5 Counter
(TIO5CT)
(Use inhibited area)
TIO7 Counter
(TIO7CT)
(Use inhibited area)
10-88
TIO7 Reload 1 Register
(TIO7RL1)
TIO7 Reload 0/Measure Register
(TIO7RL0)
(Use inhibited area)
10-90
10-89
TIO8 Counter
(TIO8CT)
(Use inhibited area)
10-88
TIO8 Reload 1 Register
(TIO8RL1)
TIO8 Reload 0/Measure Register
(TIO8RL0)
(Use inhibited area)
10-90
TIO8 Control Register
(TIO8CR)
10-89
TIO9 Control Register
(TIO9CR)
10-87
10-88
(Use inhibited area)
TIO9 Counter
(TIO9CT)
(Use inhibited area)
10-88
TIO9 Reload 1 Register
(TIO9RL1)
TIO9 Reload 0/Measure Register
(TIO9RL0)
(Use inhibited area)
10-90
TIO Enable Protect Register
(TIOPRO)
TIO Count Enable Register
(TIOCEN)
10-79
10-89
10-91
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.4 TIO Control Registers
The TIO control registers are used to select operation modes of TIO0–9 (measure input, noise processing input,
PWM output, single-shot output, delayed single-shot output or continuous output mode), as well as select the
count enable and count clock sources.
Following TIO control registers are provided for each timer group.
• TIO0–3 Control Register 0 (TIO03CR0)
• TIO0–3 Control Register 1 (TIO03CR1)
• TIO4 Control Register (TIO4CR)
• TIO5 Control Register (TIO5CR)
• TIO6 Control Register (TIO6CR)
• TIO7 Control Register (TIO7CR)
• TIO8 Control Register (TIO8CR)
• TIO9 Control Register (TIO9CR)
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10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO0–3 Control Register 0 (TIO03CR0)
b0
1
TIO3EEN
0
2
3
TIO3M
0
0
4
<Address: H’0080 031A>
5
TIO2ENS
0
0
6
7
TIO2M
0
8
9
TIO1ENS
0
0
0
10
11
TIO1M
0
0
12
13
TIO0ENS
0
0
14
b15
TIO0M
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
TIO3EEN (Note 1)
0: Disable external input
TIO3 external input enable bit
1: Enable external input
R
W
1–3
TIO3M
TIO3 operation mode select bit
000:
001:
010:
011:
100:
101:
110:
111:
R
W
4
TIO2ENS
TIO2 enable/measure input source select bit
0: No selection
1: External input TIN5 (Note 2)
R
W
5–7
TIO2M
TIO2 operation mode select bit
000:
001:
010:
011:
100:
101:
110:
111:
R
W
8
TIO1ENS
0: No selection
TIO1 enable/measure input source select bit
1: External input TIN4 (Note 2)
R
W
9–11
TIO1M
TIO1 operation mode select bit
000:
001:
010:
011:
100:
101:
110:
111:
R
W
12
TIO0ENS
TIO0 enable/measure input source select bit
0: No selection
1: External input TIN3
R
W
13–15
TIO0M
TIO0 operation mode select bit
000:
001:
010:
011:
100:
101:
110:
111:
R
W
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
PWM output mode
Measure clear input mode
Measure free-run input mode
Noise processing input mode
– ditto –
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
PWM output mode
Measure clear input mode
Measure free-run input mode
Noise processing input mode
– ditto –
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
PWM output mode
Measure clear input mode
Measure free-run input mode
Noise processing input mode
– ditto –
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
PWM output mode
Measure clear input mode
Measure free-run input mode
Noise processing input mode
– ditto –
Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is
entered from an external device, the counter value at that point in time is written into the measure register. In measure clear
input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and,
therefore, this bit should be set to "1" (external input enabled).
Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Notes: • This register must always be accessed in halfwords.
• Operation mode can only be set or changed while the counter is inactive.
• To select TIO3 enable/measure input sources, use the TIO4 Control Register TIO34ENS (TIO3, TIO4 enable/measure
input source select) bits.
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
Clock bus
Input event bus
3210 3210
S
clk
TIN3 (P153)
TIN3S
en/cap
TIO 0
en/cap
TIO 1
en/cap
TIO 2
en/cap
TIO 3
en/cap
TIO 4
S
clk
S
clk
S
clk
clk
S
S
3210
3210
S : Selector
Note: • This diagram only illustrates TIO control registers and is partly omitted.
Figure 10.4.3 Outline Diagram of TIO0–4 Clock and Enable Inputs
TIO0–3 Control Register 1 (TIO03CR1)
b8
9
10
11
12
13
<Address: H’0080 031D>
14
b15
TIO03CKS
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–13
No function assigned. Fix to "0".
14, 15
TIO03CKS
TIO0–3 clock source select bit
Function
00:
01:
10:
11:
10-82
Clock
Clock
Clock
Clock
bus
bus
bus
bus
0
1
2
3
R
W
0
0
R
W
32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO4 Control Register (TIO4CR)
b0
1
TIO4CKS
0
0
2
TIO4EEN
0
3
4
<Address: H’0080 034A>
5
TIO34ENS
0
0
6
b7
TIO4M
0
0
0
<After reset: H’00>
b
Bit Name
0, 1
TIO4CKS
TIO4 clock source select bit
Function
00: Clock bus 0
01: Clock bus 1
10: Clock bus 2
R
W
R
W
11: Clock bus 3
2
TIO4EEN (Note 1)
TIO4 external input enable bit
0: Disable external input
1: Enable external input
R
W
3, 4
TIO34ENS
TIO3,4 enable/measure input source select bit
00: External input TIN6 (Note 2)
01: – ditto –
(Note 2)
10: Input event bus 2
11: Input event bus 3
R
W
5–7
TIO4M
TIO4 operation mode select bit
000:
001:
010:
011:
100:
101:
110:
111:
R
W
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
PWM output mode
Measure clear input mode
Measure free-run input mode
Noise processing input mode
– ditto –
Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is
entered from an external device, the counter value at that point in time is written into the measure register. In measure clear
input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture
and, therefore, this bit should be set to "1" (external input enabled).
Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Note: • Operation mode can only be set or changed while the counter is inactive.
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
Clock bus
Input event bus
3210 3210
TCLK1 (P125)
TCLK1S
clk
S
en/cap
TIO 5
en/cap
TIO 6
en/cap
TIO 7
en/cap
TIO 8
en/cap
TIO 9
S
TCLK2 (P126)
TCLK2S
S
clk
S
clk
S
S
clk
S
S
S
clk
S
3210
3210
S : Selector
Note: • This diagram only illustrates TIO control registers and is partly omitted.
Figure 10.4.4 Outline Diagram of TIO5–9 Clock and Enable Inputs
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO5 Control Register (TIO5CR)
b8
9
10
TIO5CKS
0
0
11
12
<Address: H’0080 034B>
13
TIO5ENS
0
0
0
14
b15
TIO5M
0
0
0
<After reset: H’00>
b
Bit Name
8–10
TIO5CKS
TIO5 clock source select bit
Function
000: External input TCLK1
001: – ditto –
010: – ditto –
011: – ditto –
100: Clock bus 0
101: Clock bus 1
110: Clock bus 2
R
W
R
W
R
W
111: Clock bus 3
11, 12
TIO5ENS
TIO5 enable/measure input source select bit
13–15
TIO5M
TIO5 operation mode select bit
00:
01:
10:
11:
No selection
– ditto –
External input TIN7 (Note 1)
Input event bus 3
000: Single-shot output mode
R W
001: Delayed single-shot output mode
010: Continuous output mode
011: PWM output mode
100: Measure clear input mode
101: Measure free-run input mode
110: Noise processing input mode
111: – ditto –
Note 1 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Note: • Operation mode can only be set or changed while the counter is inactive.
10-85
32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO6 Control Register (TIO6CR)
b0
1
2
TIO6CKS
0
0
3
4
<Address: H’0080 036A>
5
TIO6ENS
0
0
0
6
b7
TIO6M
0
0
0
<After reset: H’00>
b
Bit Name
0–2
TIO6CKS
TIO6 clock source select bit
3, 4
TIO6ENS
TIO6 enable/measure input source select bit
5–7
TIO6M
TIO6 operation mode select bit
Function
R
W
000: External input TCLK2
001: – ditto –
010: – ditto –
011: – ditto –
100: Clock bus 0
101: Clock bus 1
110: Clock bus 2
111: Clock bus 3
R
W
00: No selection
01: External input TIN8 (Note 1)
10: Input event bus 2
11: Input event bus 3
R
W
000: Single-shot output mode
R W
001: Delayed single-shot output mode
010: Continuous output mode
011: PWM output mode
100: Measure clear input mode
101: Measure free-run input mode
110: Noise processing input mode
111: – ditto –
Note 1 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Note: • Operation mode can only be set or changed while the counter is inactive.
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO7 Control Register (TIO7CR)
b8
0
9
10
11
12
TIO7CKS
TIO7ENS
0
0
0
<Address: H’0080 036B>
13
0
14
b15
TIO7M
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
8
No function assigned. Fix to "0".
9, 10
TIO7CKS
TIO7 clock source select bit
00: Clock
01: Clock
10: Clock
11: Clock
11, 12
TIO7ENS
TIO7 enable/measure input source select bit
00: No selection
01: External input TIN9 (Note 1)
10: Input event bus 0
11: Input event bus 3
13–15
TIO7M
TIO7 operation mode select bit
bus
bus
bus
bus
0
1
2
3
W
0
0
R
W
R
W
000: Single-shot output mode
R W
001: Delayed single-shot output mode
010: Continuous output mode
011: PWM output mode
100: Measure clear input mode
101: Measure free-run input mode
110: Noise processing input mode
111: – ditto –
Note 1 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Note: • Operation mode can only be set or changed while the counter is inactive.
TIO8 Control Register (TIO8CR)
b0
1
2
TIO8CKS
0
0
3
4
<Address: H’0080 038A>
5
TIO8ENS
0
0
6
b7
TIO8M
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0, 1
TIO8CKS
TIO8 clock source select bit
00:
01:
10:
11:
Clock
Clock
Clock
Clock
2–4
TIO8ENS
TIO8 enable/measure input source select bit
000:
001:
010:
011:
100:
101:
110:
111:
No selection
– ditto –
– ditto –
– ditto –
External input TIN10 (Note 1)
Input event bus 1
Input event bus 2
Input event bus 3
5–7
TIO8M
TIO8 operation mode select bit
bus
bus
bus
bus
0
1
2
3
R
W
R
W
R
W
000: Single-shot output mode
R W
001: Delayed single-shot output mode
010: Continuous output mode
011: PWM output mode
100: Measure clear input mode
101: Measure free-run input mode
110: Noise processing input mode
111: – ditto –
Note 1 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Note: • Operation mode can only be set or changed while the counter is inactive.
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO9 Control Register (TIO9CR)
b8
9
0
10
11
12
TIO9CKS
TIO9ENS
0
0
0
<Address: H’0080 038B>
13
14
b15
TIO9M
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
8
No function assigned. Fix to "0".
9, 10
TIO9CKS
TIO9 clock source select bit
00:
01:
10:
11:
11, 12
TIO9ENS
TIO9 enable/measure input source select bit
00: No selection
01: External input TIN11 (Note 1)
10: Input event bus 1
11: Input event bus 3
13–15
TIO9M
TIO9 operation mode select bit
Clock
Clock
Clock
Clock
bus
bus
bus
bus
0
1
2
3
R
W
0
0
R
W
R
W
000: Single-shot output mode
R W
001: Delayed single-shot output mode
010: Continuous output mode
011: PWM output mode
100: Measure clear input mode
101: Measure free-run input mode
110: Noise processing input mode
111: – ditto –
Note 1 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
Note: • Operation mode can only be set or changed while the counter is inactive.
10.4.5 TIO Counters (TIO0CT–TIO9CT)
TIO0
TIO1
TIO2
TIO3
TIO4
TIO5
TIO6
TIO7
TIO8
TIO9
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
b0
(TIO0CT)
(TIO1CT)
(TIO2CT)
(TIO3CT)
(TIO4CT)
(TIO5CT)
(TIO6CT)
(TIO7CT)
(TIO8CT)
(TIO9CT)
1
2
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
3
4
5
6
7
8
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
9
10
11
12
13
14
?
?
?
?
?
?
0300>
0310>
0320>
0330>
0340>
0350>
0360>
0370>
0380>
0390>
b15
TIO0CT–TIO9CT
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–15
TIO0CT–TIO9CT
Function
R
16-bit reload counter value
W
R(Note 1)
Note 1: Protected against write during PWM output mode.
Note: • This register must always be accessed in halfwords.
The TIO counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by
external input), the counter starts counting synchronously with the count clock.
These counters are protected against write during PWM output mode.
10-88
32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)
TIO0
TIO1
TIO2
TIO3
TIO4
TIO5
TIO6
TIO7
TIO8
TIO9
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
b0
0/
0/
0/
0/
0/
0/
0/
0/
0/
0/
Measure
Measure
Measure
Measure
Measure
Measure
Measure
Measure
Measure
Measure
1
2
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
3
4
(TIO0RL0)
(TIO1RL0)
(TIO2RL0)
(TIO3RL0)
(TIO4RL0)
(TIO5RL0)
(TIO6RL0)
(TIO7RL0)
(TIO8RL0)
(TIO9RL0)
5
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
6
7
8
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
9
10
11
12
13
14
?
?
?
?
?
?
0306>
0316>
0326>
0336>
0346>
0356>
0366>
0376>
0386>
0396>
b15
TIO0RL0–TIO9RL0
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–15
TIO0RL0–TIO9RL0
Function
R
16-bit reload register value
W
R(Note 1)
Note 1: This register is protected against write during measure input mode.
Note: • This register must always be accessed in halfwords.
The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading data into the TIO Count
Registers (TIO0CT–TIO9CT) and as a measure register during measure input mode. These registers are protected against write during measure input mode.
The content of the reload 0 register is loaded into the counter in the following cases:
• When after the counter started counting in noise processing input mode, the input signal is inverted and a
valid-level signal is entered again before the counter underflows
• When the counter is enabled in single-shot output mode
• When the counter underflowed in delayed single-shot output or continuous output mode
• When the counter is enabled in PWM output mode and when the counter value set by the reload 1 register
underflowed
Simply because data is written to the reload 0 register does not mean that the data is loaded into the counter.
If this register is used as a measure register, the counter value is latched into that measure register by event
input.
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1)
TIO0
TIO1
TIO2
TIO3
TIO4
TIO5
TIO6
TIO7
TIO8
TIO9
b0
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
1
1
1
1
1
1
1
1
1
1
1
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
2
3
(TIO0RL1)
(TIO1RL1)
(TIO2RL1)
(TIO3RL1)
(TIO4RL1)
(TIO5RL1)
(TIO6RL1)
(TIO7RL1)
(TIO8RL1)
(TIO9RL1)
4
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
5
6
7
8
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
9
10
11
12
13
14
?
?
?
?
?
?
0304>
0314>
0324>
0334>
0344>
0354>
0364>
0374>
0384>
0394>
b15
TIO0RL1–TIO9RL1
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–15
TIO0RL1–TIO9RL1
Note: • This register must always be accessed in halfwords.
Function
16-bit reload register value
R
W
R
W
The TIO Reload 1 Registers are used to reload data into the TIO Count Registers (TIO0CT–TIO9CT).
The content of the reload 1 register is loaded into the counter in the following cases:
• When the count value set by the reload 0 register underflowed in PWM output mode
Simply because data is written to the reload 1 register does not mean that the data is loaded into the counter.
10-90
32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.8 TIO Enable Control Registers
TIO Enable Protect Register (TIOPRO)
b0
1
2
3
4
5
<Address: H’0080 03BC>
6
7
8
9
10
11
12
13
14
b15
TIO9PRO TIO8PRO TIO7PRO TIO6PRO TIO5PRO TIO4PRO TIO3PRO TIO2PRO TIO1PRO TIO0PRO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
0–5
No function assigned. Fix to "0".
6
TIO9PRO (TIO9 enable protect bit)
0: Enable rewrite
7
TIO8PRO (TIO8 enable protect bit)
1: Disable rewrite
8
TIO7PRO (TIO7 enable protect bit)
9
TIO6PRO (TIO6 enable protect bit)
10
TIO5PRO (TIO5 enable protect bit)
11
TIO4PRO (TIO4 enable protect bit)
12
TIO3PRO (TIO3 enable protect bit)
13
TIO2PRO (TIO2 enable protect bit)
14
TIO1PRO (TIO1 enable protect bit)
15
TIO0PRO (TIO0 enable protect bit)
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords.
The TIO Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by
enabling or disabling it.
10-91
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
TIO Count Enable Register (TIOCEN)
b0
1
2
3
4
5
<Address: H’0080 03BE>
6
7
8
9
10
11
12
13
14
b15
TIO9CEN TIO8CEN TIO7CEN TIO6CEN TIO5CEN TIO4CEN TIO3CEN TIO2CEN TIO1CEN TIO0CEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
0–5
No function assigned. Fix to "0".
6
TIO9CEN (TIO9 count enable bit)
0: Stop count
7
TIO8CEN (TIO8 count enable bit)
1: Enable count
8
TIO7CEN (TIO7 count enable bit)
9
TIO6CEN (TIO6 count enable bit)
10
TIO5CEN (TIO5 count enable bit)
11
TIO4CEN (TIO4 count enable bit)
12
TIO3CEN (TIO3 count enable bit)
13
TIO2CEN (TIO2 count enable bit)
14
TIO1CEN (TIO1 count enable bit)
15
TIO0CEN (TIO0 count enable bit)
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords
The TIO Count Enable Register controls operation of the TIO counters. To enable any TIO counter in software,
enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TIO
counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0".
In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable
bit is automatically reset to "0". Therefore, the TIO Count Enable Register when accessed for read serves as a
status register indicating whether the counter is operating or idle.
TIOm external enable
(TIOmEEN or TIOmENS)
F/F
Input processing
selection
TINn
EN-ON
TINnS
Event bus
TIOm count enable
(TIOmCEN)
TIO enable control
F/F
Dn
TIOm enable protect
(TIOmPRO)
WR
F/F
WR
Figure 10.4.5 Configuration of the TIO Enable Circuit
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MULTIJUNCTION TIMERS
10
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes
(1) Outline of TIO measure free-run/ clear input modes
In measure free-run/ clear input modes, the timer is used to measure a duration of time from when the
counter starts counting till when an external capture signal is entered. An interrupt request can be generated
by a counter underflow or execution of a measure operation.
After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at
that point in time is written into a register called the “measure register.”
In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter
starts counting down again. When the counter underflows, it starts counting down from H'FFFF.
In measure free-run input mode, the counter continues counting down even after capture and upon underflow, recycles to H’FFFF, from which it starts counting down again.
To stop the counter, disable count by writing to the enable bit in software.
Enabled
(by writing to
the enable bit)
Measure event
(capture) occurs
Measure event
(capture)
Count clock
Enable bit
H'FFFF
Undefined
value
H'9000
Counter
H'7000
H'0000
Measure register
Undefined
H'7000
H'9000
TIN interrupt request
TIN interrupt request due to
external event input
TIN interrupt request due to
external event input
TIO interrupt request
TIO interrupt request due
to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.4.6 Typical Operation in Measure Free-Run Input Mode
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10.4 TIO (Input/Output-Related 16-Bit Timer)
Enabled
(by writing to
the enable bit)
Measure event
(capture) occurs
Count clock
Enable bit
H'FFFF
Undefined
value
Counter
H'7000
H'0000
Measure register
Undefined
H'0008
TIN interrupt request
TIN interrupt request due to
external event input
TIO interrupt request
TIO interrupt request due
to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.4.7 Typical Operation in Measure Clear Input Mode
(2) Precautions on using TIO measure free-run/ clear input modes
The following describes precautions to be observed when using TIO measure free-run/ clear input modes.
• If measure event input and write to the counter occur in the same clock period, the write value is set in the
counter while at the same time latched into the measure register.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.10 Operation in TIO Noise Processing Input Mode
In noise processing input mode, the timer is used to detect that the input signal remained in the same state for
over a predetermined time.
In noise processing input mode, a high or low level on external input activates the counter and if the input signal
remains in the same state for over a predetermined time before the counter underflows, the counter generates
an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the
counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, the
counter is reloaded with the initial count and restarts counting. The effective count width is (reload 0 register set
value + 1).
The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An
interrupt request can be generated by a counter underflow.
Enabled
(by writing to
the enable bit)
Count clock
Disabled by underflow
Enable bit
External input
(noise processing)
Invalid
Invalid
H'FFFF
Effective signal
width
H'A000
Counter
H'0000
Reload 0 register
H'A000
TIO interrupt request
TIO interrupt request due
to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.4.8 Typical Operation in Noise Processing Input Mode
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.11 Operation in TIO PWM Output Mode
(1) Outline of TIO PWM output mode
In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial
values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts
counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the
reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload
1 register values alternately each time an underflow occurs. The (reload 0 register set value + 1) and (reload
1 register set value + 1) respectively are effective as count values. The timer stops at the same time count is
disabled by writing to the enable bit (and not in synchronism with PWM output period).
The F/F output waveform in PWM output mode is inverted (F/F output level changes from low to high or vice
versa) when the counter starts counting and each time it underflows. An interrupt request can be generated
at an even underflow after the counter being enabled.
Note that TIO’s PWM output mode does not have the count correction function.
Enabled
(by writing to the enable bit
or by external input)
Underflow
(first time)
Underflow
(second time)
Count clock
Enable bit
Count down from
the reload 0
register set value
Count down from
the reload 1
register set value
Count down from
the reload 0
register set value
H'FFFF
Undefined
value
H'C000
H'(C000-1)
H'(A000-1)
H'A000
Counter
H'(A000-1)
H'A000
H'0000
Reload 0 register
H'A000
Reload 1 register
H'C000
F/F output
Data inverted by
enable
Data inverted by
underflow
Data inverted by
underflow
TIO interrupt request
due to underflow
PWM output period
Note: • This diagram does not show detailed timing information.
Figure 10.4.9 Typical Operation in PWM Output Mode
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10.4 TIO (Input/Output-Related 16-Bit Timer)
(2) Reload register updates in TIO PWM output mode
In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the
same time data are written to the respective registers. But when the timer is operating, the reload 1 register
is updated by updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for
read, the read values are always the data that have been written to the respective registers.
Internal bus
Reload 1
TIOnRL1
Reload 1 WR
Reload 0 WR
Reload 0
Buffer
TIOnRL0
PWM mode control
Prescaler output
16-bit counter
F/F
TO
Figure 10.4.10 PWM Circuit Diagram
To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first
and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchronously
with PWM period, from which the timer starts operating. This operation can normally be performed collectively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are automatically written to the reload 1 and then the reload 0 registers in succession.)
If the reload 0 and reload 1 registers are updated in the reverse order beginning with reload 0, only the reload
0 register is updated. Note also that if the reload 0 and reload 1 registers are accessed for read, the read
values are always the data that have been written to the respective registers, and not the reload values being
actually used.
When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU
finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the
register is reflected in the next period.
(3) Precautions on using TIO PWM output mode
The following describes precautions to be observed when using TIO PWM output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
(a) When reload register updates take effect in the current period (reflected in the next period)
Write to reload 1
Reload 0 register
H'1000
Reload 1 register
H'2000
Write to reload 0
(Reload 1 data latched)
H'8000
H'9000
New PWM
output period
Old PWM
output period
F/F output
Operation by new reload value written
Enlarged
view
New PWM
output period
Count clock
Counter
H'0001
H'0000
H'FFFF
H'7FFF
H'7FFE
Interrupt due
to underflow
Reload 0 register
H'1000
H'8000
Reload 1 register
H'2000
H'9000
Reload 1 buffer
H'2000
H'9000
F/F output
Timing at which reload 0 and reload 1
registers are updated
PWM period latched
(b) When reload register updates take effect in the next period (reflected one period later)
Write to reload 1
Reload 0 register
H'1000
Reload 1 register
H'2000
Write to reload 0
(Reload 1 data latched)
H'8000
H'9000
Old PWM
output period
Old PWM
output period
F/F output
Operation by old reload value
Enlarged
view
Old PWM
output period
Count clock
Counter H'0001
H'0000
H'FFFF
H'0FFF
H'0FFE
Interrupt due
to underflow
Reload 0 register
Reload 1 register
Reload 1 buffer
H'1000
H'2000
H'8000
H'9000
H'2000
H'9000
F/F output
PWM period latched
Timing at which reload 0 and reload 1
registers are updated
Note: • This diagram does not show detailed timing information.
Figure 10.4.11 Reload 0 and Reload 1 Register Updates in PWM Output Mode
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)
(1) Outline of TIO single-shot output mode
In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload
0 register, the counter is loaded with the content of the reload 0 register and starts counting synchronously
with the count clock. The counter counts down and when the minimum count is reached, stops upon underflow.
The F/F output waveform in single-shot output mode is inverted (F/F output level changes from low to high or
vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0
register set value + 1) only once. An interrupt request can be generated when the counter underflows.
The count value is (reload 0 register set value + 1). (For counting operation, see also Section 10.3.9, “Operation of TOP Single-shot Output Mode.”)
(2) Precautions on using TIO single-shot output mode
The following describes precautions to be observed when using TIO single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the
enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
Enabled
(by writing to the enable bit
or by external input)
Disabled
(by underflow)
Count clock
Enable bit
H'FFFF
Undefined
value
H'A000
Count down from the
reload 0 register set value
H'(A000-1)
Counter
H'0000
Reload 0 register
H'A000
Reload 1 register
(Unused)
F/F output
Data inverted by
enable
Data inverted by
underflow
TIO interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.4.12 Typical Operation in TIO Single-shot Output Mode (without Correction Function)
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MULTIJUNCTION TIMERS
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)
(1) Outline of TIO delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock. The first time the counter underflows, it is loaded with the reload 0 register value and continues
counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low
to high or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) after a finite time equal to (first set value of counter + 1) only
once.
An interrupt request can be generated when the counter underflows first time and next.
The (counter set value + 1) and (reload 0 register set value + 1) are effective as count values. (For counting
operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”)
(2) Precautions on using TIO delayed single-shot output mode
The following describes precautions to be observed when using TIO delayed single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the
enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
Enabled
(by writing to the enable bit
or by external input)
Underflow
(first time)
Underflow
(second time)
Count clock
Enable bit
H'FFFF
H'F000
H'A000
H'EFFF
Count down from the
counter set value
Counter
Count down from the
reload 0 register
set value
H'0000
H'F000
Reload 0 register
Reload 1 register
(Unused)
F/F output
Data inverted by
underflow
Data inverted by
underflow
TIO interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.4.13 Typical Operation in TIO Delayed Single-shot Output Mode (without Correction Function)
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10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)
(1) Outline of TIO continuous output mode
In continuous output mode, the timer counts down starting from the set value of the counter and when the
counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each
time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of
(reload 0 register set value + 1).
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock and when the minimum count is reached, generates an underflow. This underflow causes the
counter to be loaded with the content of the reload 0 register and start counting over again. Thereafter, this
operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the
enable bit in software.
The F/F output waveform in continuous output mode is inverted (F/F output level changes from low to high or
vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops
counting. An interrupt request can be generated each time the counter underflows.
The (counter set value + 1) and (reload 0 register set value + 1) are effective as count values. (For counting
operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”)
(2) Precautions on using TIO continuous output mode
The following describes precautions to be observed when using TIO continuous output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.
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10.4 TIO (Input/Output-Related 16-Bit Timer)
Enabled
(by writing to the enable bit
or by external input)
Underflow
(second time)
Underflow
(first time)
Count clock
Enable bit
H'FFFF
H'E000
H'A000
Counter
Count down from
the counter set
value
H'DFFF
H'DFFF
Count down from the
reload 0 register
set value
Count down from the
reload 0 register
set value
H'0000
Reload 0 register
H'E000
Reload 1 register
(Unused)
F/F output
Data inverted by
enable
Data inverted by
underflow
Data inverted by
underflow
TIO interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.4.14 Typical Operation in TIO Continuous Output Mode (without Correction Function)
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10.5 TMS (Input-Related 16-Bit Timer)
10.5 TMS (Input-Related 16-Bit Timer)
10.5.1 Outline of TMS
TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit
blocks comprising a total of eight channels.
The table below shows specifications of TMS. The diagram in the next page shows a block diagram of TMS.
Table 10.5.1 Specifications of TMS (Input-Related 16-Bit Timer)
Item
Specification
Number of channels
8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total)
Counter
16-bit up-counter × 2
Measure register
16-bit measure register × 8
Timer startup
Started by writing to the enable bit in software
Interrupt request generation
Can be generated by a counter overflow
10.5.2 Outline of TMS Operation
In TMS, when the timer is enabled (by writing to the enable bit in software), the counter starts operating. The
counter is a 16-bit up-counter, where the counter value is latched into each measure register when a measure
signal is entered from an external device.
The counter stops counting at the same time count is disabled by writing to the enable bit in software.
TIN and TMS interrupt requests can be generated by external measure signal input and counter overflow,
respectively.
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10.5 TMS (Input-Related 16-Bit Timer)
Clock bus
3210
Input event bus
Output event bus
3210
0123
TMS 0
ovf
TCLK3 (P127)
TCLK3S
clk
S
Counter
Measure register 3
(16-bit)
Measure register 2
IRQ7
Measure register 1
Measure register 0
cap3
cap2
cap1
cap0
S
S
S
S
TMS 1
ovf
clk
S
Counter
Measure register 3
(16-bit)
Measure register 2
IRQ7
Measure register 1
Measure register 0
cap3
IRQ10
TIN16 (P130)
TIN16S
TIN17 (P131)
TIN17S
cap2
cap1
cap0
S
IRQ10
S
DMA5
IRQ10
TIN18 (P132)
S
TIN18S
DMA6
IRQ10
TIN19 (P133)
S
TIN19S
3210
3210
0123
S : Selector
Figure 10.5.1 Block Diagram of TMS (Input-Related 16-Bit Timer)
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10.5 TMS (Input-Related 16-Bit Timer)
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating.
Write to the enable bit
BCLK
Count clock period
Count clock
Enable
Count clock-dependent
delay
Figure 10.5.2 Count Clock-Dependent Delay
10.5.3 TMS Related Register Map
Shown below is a TMS related register map.
TMS Related Register Map
Address
+0 address
b0
H'0080 03C0
H'0080 03C2
H'0080 03C4
H'0080 03C6
H'0080 03C8
H'0080 03CA
|
H'0080 03D0
H'0080 03D2
H'0080 03D4
H'0080 03D6
H'0080 03D8
+1 address
b7 b8
TMS0 Counter
(TMS0CT)
TMS0 Measure 3 Register
(TMS0MR3)
TMS0 Measure 2 Register
(TMS0MR2)
TMS0 Measure 1 Register
(TMS0MR1)
TMS0 Measure 0 Register
(TMS0MR0)
TMS0 Control Register
(TMS0CR)
See pages
b15
10-109
10-109
10-109
10-109
10-109
TMS1 Control Register
(TMS1CR)
10-108
(Use inhibited area)
TMS1 Counter
(TMS1CT)
TMS1 Measure 3 Register
(TMS1MR3)
TMS1 Measure 2 Register
(TMS1MR2)
TMS1 Measure 1 Register
(TMS1MR1)
TMS1 Measure 0 Register
(TMS1MR0)
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10.5 TMS (Input-Related 16-Bit Timer)
10.5.4 TMS Control Registers
The TMS control registers are used to select TMS0/1 input events and count clock sources, as well as control
count enable. Following two TMS control registers are included:
• TMS0 Control Register (TMS0CR)
• TMS1 Control Register (TMS1CR)
TMS0 Control Register (TMS0CR)
b0
1
2
3
TMS0SS0 TMS0SS1 TMS0SS2 TMS0SS3
0
0
0
0
4
<Address: H’0080 03CA>
5
6
TMS0CKS
0
0
b7
TMS0CEN
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
TMS0SS0
TMS0 measure 0 source select bit
0: External input TIN15 (Note 1)
1: Input event bus 0
R
W
1
TMS0SS1
TMS0 measure 1 source select bit
0: External input TIN14 (Note 1)
1: Input event bus 1
R
W
2
TMS0SS2
TMS0 measure 2 source select bit
0: External input TIN13 (Note 1)
1: Input event bus 2
R
W
3
TMS0SS3
TMS0 measure 3 source select bit
0: External input TIN12 (Note 1)
1: Input event bus 3
R
W
4, 5
TMS0CKS
TMS0 clock source select bit
00: External input TCLK3
01: Clock bus 0
10: Clock bus 1
11: Clock bus 3
R
W
6
No function assigned. Fix to "0".
0
0
7
TMS0CEN
TMS0 count enable bit
R
W
0: Stop count
1: Start count
Note 1 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
TMS1 Control Register (TMS1CR)
b8
9
10
11
12
TMS1SS0 TMS1SS1 TMS1SS2 TMS1SS3
0
0
0
0
<Address: H’0080 03CB>
13
14
TMS1CKS
0
0
b15
TMS1CEN
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
TMS1SS0
TMS1 measure 0 source select bit
0: External input TIN19
1: Input event bus 0
R
W
9
TMS1SS1
TMS1 measure 1 source select bit
0: External input TIN18
1: Input event bus 1
R
W
10
TMS1SS2
TMS1 measure 2 source select bit
0: External input TIN17
1: Input event bus 2
R
W
11
TMS1SS3
TMS1 measure 3 source select bit
0: External input TIN16
1: Input event bus 3
R
W
12
No function assigned. Fix to "0".
0
0
13
TMS1CKS
TMS1 clock source select bit
R
W
14
No function assigned. Fix to "0".
0
0
15
TMS1CEN
TMS1 count enable bit
R
W
0: Clock bus 0
1: Clock bus 3
0: Stop count
1: Start count
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10.5 TMS (Input-Related 16-Bit Timer)
10.5.5 TMS Counters (TMS0CT, TMS1CT)
TMS0 Counter (TMS0CT)
TMS1 Counter (TMS1CT)
b0
1
2
<Address: H’0080 03C0>
<Address: H’0080 03D0>
3
4
5
6
7
8
9
10
11
12
13
14
?
?
?
?
?
?
b15
TMS0CT,TMS1CT
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
TMS0CT, TMS1CT
16-bit counter value
R
W
Note: • This register must always be accessed in halfwords.
The TMS counter is a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable
bit in software). The counters can be read during operation.
10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0)
TMS0
TMS0
TMS0
TMS0
TMS1
TMS1
TMS1
TMS1
Measure 3 Register (TMS0MR3)
Measure 2 Register (TMS0MR2)
Measure 1 Register (TMS0MR1)
Measure 0 Register (TMS0MR0)
Measure 3 Register (TMS1MR3)
Measure 2 Register (TMS1MR2)
Measure 1 Register (TMS1MR1)
Measure 0 Register (TMS1MR0)
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
<Address:
b0
1
2
3
4
5
6
?
?
?
?
?
?
?
7
8
9
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
H’0080
10
11
12
13
14
?
?
?
?
?
03C2>
03C4>
03C6>
03C8>
03D2>
03D4>
03D6>
03D8>
b15
TMS0MR3–0,TMS1MR3–0
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
TMS0MR3-TMS0MR0
TMS1MR3-TMS1MR0
16-bit measured value
R
–
Notes: • This register is a read-only register.
• This register can be accessed in either byte or halfword.
The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers
are a read-only register.
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32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.5 TMS (Input-Related 16-Bit Timer)
10.5.7 Operation of TMS Measure Input
(1) Outline of TMS measure input
In TMS measure input, when the timer is enabled (by writing to the enable bit in software), it starts counting
up synchronously with the count clock. Then when event input to TMS is detected while the timer is operating, the counter value is latched into measure registers 0–3. The timer stops counting at the same time count
is disabled by writing to the enable bit.
A TIN interrupt request can be generated by measure signal input from an external device. A TMS interrupt
request can be generated when the counter overflows.
Enabled
(by writing to the
enable bit)
Measure
event 0
occurs
Measure
event 1 Overflow
occurs occurs
Measure
event 0
occurs
Measure
event 1
occurs
Count clock
Enable bit
H'FFFF
H'D000
H'C000
Counter
H'8000
H'6000
Undefined
value
H'0000
Measure 0 register
Undefined
H'6000
H'8000
TIN19 interrupt request
Measure 1 register
Undefined
H'D000
H'C000
TIN18 interrupt request
TMS interrupt request
due to overflow
Note: • This diagram does not show detailed timing information.
Figure 10.5.3 Typical Operation of TMS Measure Input
(2) Precautions on using TMS measure input
The following describes precautions to be observed when using TMS measure input.
• If measure event input and write to the counter occur in the same clock period, the write value is set in the
counter while at the same time latched into the measure register.
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32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.6 TML (Input-Related 32-Bit Timer)
10.6 TML (Input-Related 32-Bit Timer)
10.6.1 Outline of TML
TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit
blocks comprising a total of eight channels.
The table below shows specifications of TML. The diagram in the next page shows a block diagram of TML.
Table 10.6.1 Specifications of TML (Input-Related 32-Bit Timer)
Item
Specification
Number of channels
8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total)
Input clock
BCLK/2 (10.0 MHz when f(BCLK) = 20 MHz) or clock bus 1 input
Counter
32-bit up-counter × 2
Measure register
32-bit measure register × 8
Timer startup
Start counting immediately after reset
Clock bus
Output event bus
Input event bus
3210 3210
0123
TML0
S
BCLK/2
clk
Counter
(32-bit)
Measure register 3
Measure register 2
Measure register 1
Measure register 0
cap3
IRQ11
TIN20 (P134)
TIN20S
TIN21 (P135)
TIN21S
cap2
cap1
cap0
S
IRQ11
S
IRQ11
TIN22 (P136)
S
TIN22S
IRQ11
TIN23 (P137)
S
TIN23S
TML1
S
clk
Counter
(32-bit)
Measure register 3
Measure register 2
Measure register 1
Measure register 0
cap3
cap2
cap1
cap0
S
S
S
S
3210 3210
0123
S : Selector
Figure 10.6.1 Block Diagram of TML (Input-Related 32-Bit Timer)
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32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.6 TML (Input-Related 32-Bit Timer)
10.6.2 Outline of TML Operation
In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is
a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at
that point in time is stored in each 32-bit measure register.
When the reset input signal is deasserted, the counter starts operating with a BCLK/2 clock, and cannot be
stopped once it has started. The counter is idle only when the microcomputer remains reset.
A TIN interrupt request can be generated by external measure signal input. However, no TML counter overflow
interrupts are available.
10.6.3 TML Related Register Map
Shown below is a TML related register map.
TML Related Register Map
Address
+0 address
b0
+1 address
b7 b8
TML0 Counter
(TML0CT)
H'0080 03E0
H'0080 03E2
(Use inhibited area)
TML0 Measure 3 Register
(TML0MR3)
H'0080 03F2
TML0 Measure 2 Register
(TML0MR2)
H'0080 03F6
TML0 Measure 1 Register
(TML0MR1)
H'0080 03FA
TML0 Measure 0 Register
(TML0MR0)
H'0080 03FE
(Upper)
10-114
(Upper)
10-114
(Upper)
10-114
(Lower)
|
(Use inhibited area)
H'0080 0FE0
TML1 Counter
(TML1CT)
H'0080 0FE2
(Upper)
10-114
(Lower)
|
(Use inhibited area)
(Use inhibited area)
TML1 Control Register
(TML1CR)
10-113
(Upper)
10-114
(Use inhibited area)
TML1 Measure 3 Register
(TML1MR3)
H'0080 0FF2
(Lower)
TML1 Measure 2 Register
(TML1MR2)
H'0080 0FF6
(Upper)
10-114
(Lower)
TML1 Measure 1 Register
(TML1MR1)
H'0080 0FFA
H'0080 0FFC
10-114
(Lower)
H'0080 03FC
H'0080 0FF8
(Upper)
(Lower)
H'0080 03F8
H'0080 0FF4
10-113
(Lower)
H'0080 03F4
H'0080 0FF0
TML0 Control Register
(TML0CR)
(Use inhibited area)
H'0080 03F0
|
10-114
(Use inhibited area)
|
H'0080 0FEA
(Upper)
(Lower)
|
H'0080 03EA
See pages
b15
(Upper)
10-114
(Lower)
TML1 Measure 0 Register
(TML1MR0)
H'0080 0FFE
(Upper)
10-114
(Lower)
10-112
32182 Group User’s Manual (Rev.1.0)
MULTIJUNCTION TIMERS
10
10.6 TML (Input-Related 32-Bit Timer)
10.6.4 TML Control Registers
TML0 Control Register (TML0CR)
b8
9
10
11
12
<Address: H’0080 03EB>
13
14
TML0SS0 TML0SS1 TML0SS2 TML0SS3
0
0
0
0
b15
TML0CKS
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
TML0SS0
TML0 measure 0 source select bit
0: External input TIN23
1: Input event bus 0
R
W
9
TML0SS1
TML0 measure 1 source select bit
0: External input TIN22
1: Input event bus 1
R
W
10
TML0SS2
TML0 measure 2 source select bit
0: External input TIN21
1: Input event bus 2
R
W
11
TML0SS3
TML0 measure 3 source select bit
0: External input TIN20
1: Input event bus 3
R
W
12–14
No function assigned. Fix to "0".
0
0
15
TML0CKS (Note 1)
0: BCLK/2
R
W
TML0 clock source select bit
1: Clock bus 1
Note 1: The counter can only be written normally when BCLK/2 is used as the clock source for the counter. If the selected clock
source is not BCLK/2, do not write to the counter because it cannot be written normally.
TML1 Control Register (TML1CR)
b8
9
10
11
12
<Address: H’0080 0FEB>
13
14
TML1SS0 TML1SS1 TML1SS2 TML1SS3
0
0
0
0
b15
TML1CKS
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
TML1SS0
TML1 measure 0 source select bit
0: External input TIN33 (Note 2)
1: Input event bus 0
R
W
9
TML1SS1
0: External input TIN32 (Note 2)
R
W
TML1 measure 1 source select bit
1: Input event bus 1
10
TML1SS2
TML1 measure 2 source select bit
0: External input TIN31 (Note 2)
1: Input event bus 2
R
W
11
TML1SS3
TML1 measure 3 source select bit
0: External input TIN30 (Note 2)
1: Input event bus 3
R
W
12–14
No function assigned. Fix to "0".
0
0
15
TML1CKS (Note 1)
TML1 clock source select bit
R
W
0: BCLK/2
1: Clock bus 1
Note 1: The counter can only be written normally when BCLK/2 is used as the clock source for the counter. If the selected clock
source is not BCLK/2, do not write to the counter because it cannot be written normally.
Note 2 : Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function
therefore has no effect.
The TML control register is used to select TML input event and count clock.
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MULTIJUNCTION TIMERS
10
10.6 TML (Input-Related 32-Bit Timer)
10.6.5 TML Counters
TML0 Counter (TML0CT)
TML1 Counter (TML1CT)
<Address: H’0080 03E0>
<Address: H’0080 0FE0>
b0
1
2
3
4
5
6
7
8
?
?
?
?
?
?
?
?
?
b16
17
18
19
20
21
22
23
24
?
?
?
?
?
?
?
9
10
11
12
13
14
?
?
?
?
?
?
25
26
27
28
29
30
?
?
?
?
?
?
b15
TML0CT, TML1CT(16 high-order bits)
?
b31
(16 low-order bits)
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–31
TML0CT, TML1CT
32-bit counter value
R(Note 1)
Note 1: If the clock source selected for the counter is not BCLK/2, do not write to this register.
Note: • This register must always be accessed wordwise (in 32 bits) beginning with the word boundary.
The TML counter is a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The
counters can be read during operation.
10.6.6 TML Measure Registers
TML0
TML0
TML0
TML0
TML1
TML1
TML1
TML1
Measure
Measure
Measure
Measure
Measure
Measure
Measure
Measure
b0
1
3
2
1
0
3
2
1
0
Register
Register
Register
Register
Register
Register
Register
Register
2
3
(TML0MR3)
(TML0MR2)
(TML0MR1)
(TML0MR0)
(TML1MR3)
(TML1MR2)
(TML1MR1)
(TML1MR0)
4
5
<Address: H’0080 03F0>
<Address: H’0080 03F4>
<Address: H’0080 03F8>
<Address: H’0080 03FC>
<Address: H’0080 0FF0>
<Address: H’0080 0FF4>
<Address: H’0080 0FF8>
<Address: H’0080 0FFC>
6
7
8
9
10
11
12
13
14
b15
TML0MR3–TML0MR0, TML1MR3–TML1MR0 (16 high-order bits)
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
b16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
?
?
?
?
?
?
?
?
?
?
?
?
?
(16 low-order bits)
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–31
TML0MR3–TML0MR0, TML1MR3–TML1MR0
32-bit measure register value
R
–
Notes: • These registers are a read-only register.
• These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary.
The TML measure register is a 32-bit register, which is used to latch the counter content upon event input. The
TML measure registers can only be read, and cannot be written to.
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MULTIJUNCTION TIMERS
10
10.6 TML (Input-Related 32-Bit Timer)
10.6.7 Operation of TML Measure Input
(1) Outline of TML measure input
In TML measure input, when the reset input signal is deasserted, the counter starts counting up synchronously with the count clock. Upon event input to measure registers 0–3, the counter value is latched into each
measure register.
A TIN interrupt request can be generated by measure signal input from an external device. However, no TML
counter overflow interrupts are available.
Measure
Enabled
(by deassertion event 0
occurs
of reset)
Measure
event 1 Overflow
occurs
occurs
Measure
event 0
occurs
Measure
event 1
occurs
Count clock
Reset
H'FFFF FFFF
H'D000 0000
H'C000 0000
Counter (32-bit)
H'8000 0000
H'6000 0000
Undefined
value
H'0000 0000
Measure 0 register
Undefined
H'6000 0000
H'8000 0000
TIN23 interrupt request
Measure 1 register
Undefined
H'D000 0000
H'C000 0000
TIN22 interrupt request
Note: • This diagram does not show detailed timing information.
Figure 10.6.2 Typical Operation of TML Measure Input
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MULTIJUNCTION TIMERS
10
10.6 TML (Input-Related 32-Bit Timer)
(2) Precautions on using TML measure input
The following describes precautions to be observed when using TML measure input.
• If measure event input and write to the counter occur in the same clock period, the write value is set in the
counter, whereas the up-count value (before being rewritten) is latched into the measure register.
• If clock bus 1 is selected and any clock other than BCLK/2 is used for the timer, the counter cannot be
written normally. Therefore, when using any clock other than BCLK/2, do not write to the counter.
• If clock bus 1 is selected and any clock other than BCLK/2 is used for the timer, the value captured into the
measure register is one count larger the counter value. During the count clock to BCLK/2 period interval,
however, the captured value is exactly the counter value.
The diagram below shows the relationship between counter operation and the valid data that can be captured.
• When BCLK/2 is selected
BCLK/2
Counter
A
B
C
D
E
F
Captured
A
B
C
D
E
F
• When clock bus 1 is selected
BCLK/2
Count clock
Counter
Captured
A
B
B
C
C
D
Figure 10.6.3 Mistimed Counter Value and the Captured Value
10-116
32182 Group User’s Manual (Rev.1.0)
CHAPTER 11
A-D CONVERTER
11.1
11.2
11.3
11.4
11.5
Outline of A-D Converter
A-D Converter Related Registers
Functional Description of A-D Converter
Inflow Current Bypass Circuit
Precautions on Using A-D Converter
A-D Converter
11
11.1 Outline of A-D Converter
11.1 Outline of A-D Converter
The 32182 contains 10-bit A-D Converter of the successive approximation type (A-D0 Converter). In addition to
performing conversion individually on each channel, the A-D Converter can perform conversion successively on
all of N channels (N = 1–12) as a single group. The conversion result can be read out in either 10 or 8 bits.
There are following conversion and operation modes for the A-D conversion:
(1) Conversion Modes
• A-D conversion mode
: Ordinary mode in which analog input voltages are converted into digital quantities.
• Comparator mode (Note 1) : A mode in which analog input voltage is compared with a preset comparison
voltage to find only the relative magnitude of two quantities. (Useful in only
single operation mode)
(2) Operation Modes
• Single mode
• Scan mode
: Analog input voltage on one channel is A-D converted once or comparated
(Note 1) with a given quantity.
: Analog input voltages on two or more selected channels (in N channel units, N =
1–12) are sequentially A-D converted.
Single-shot scan mode
: Scan operation is performed for one cycle.
Continuous scan mode
: Scan operation is repeatedly until stopped.
(3) Special Operation Modes
• Forcible single mode execution during scan mode : Conversion is forcibly executed in single mode (comparator
mode) during scan operation.
• Scan mode start after single mode execution : Scan operation is started subsequently after executing
conversion in single mode.
• Conversion restart
: A-D conversion being executed in single or scan mode is
restarted.
(4) Sample-and-Hold Function
The analog input voltage is sampled when starting A-D conversion, and A-D conversion is performed on the
sampled voltage. This function can be enabled or disabled as necessary.
(5) A-D Disconnection Detection Assist Function
To suppress influences of the analog input voltage leakage from any preceding channel during scan mode
operation, a function is incorporated that helps to fix the electric charge on the chopper amp capacitor to the
given state (AVCC or AVSS) before starting A-D conversion. This function provides a sure and reliable means of
detecting a disconnection in the wiring patterns connecting to the analog input pins.
(6) Inflow Current Bypass Circuit
If an overvoltage or negative voltage is applied to any analog input channel which is currently inactive, a current
flows into or out of the analog input channel currently being A-D converted via the internal circuit, causing the
conversion accuracy to degrade. To solve this problem, the A-D Converter incorporates a circuit that bypasses
such inflow current. This circuit is always enabled.
(7) Conversion Speed
The A-D conversion and comparate speed can be selected from a total of four speeds available: slow mode
(normal or double speed) and fast mode (normal or double speed). The normal speed and double speed in slow
mode are compatible with the 32170 group of Renesas microcomputers.
11-2
32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.1 Outline of A-D Converter
(8) Interrupt and DMA Transfer Request Generation Function
An A-D conversion interrupt or DMA transfer request can be generated each time A-D conversion or comparate
operation in single mode is completed, as well as when a single-shot scan operation or one cycle of continuous
scan operation is completed.
Note 1: To discriminate between the comparison performed internally by the successive approximationtype A-D Converter and that performed in comparator mode using the same A-D Converter as a
comparator, the comparison in comparator mode is referred to in this manual as “comparate.”
Table 11.1.1 outlines the A-D Converter and Figure 11.1.1 shows block diagram of A-D Converter.
Table 11.1.1 Outline of the A-D Converter
Item
Description
Analog input
12 channels
A-D0 Converter: 12-channel analog input-only pins
A-D conversion method Successive approximation method
Resolution
10 bits (Conversion result can be read out in either 8 or 10 bits)
Absolute accuracy (Note 1) During slow mode: ±2 SLB at normal speed, ±2 SLB at double speed
Conditions: Ta = 25°C,
AVCC0 = 5.12 V,
VREF0 = 5.12 V
During fast mode: ±3 SLB at normal speed, ±3 SLB at double speed
Note: • The accuracy when sample-and-hold is enabled is T.B.D.
Conversion mode
A-D conversion mode and comparator mode
Operation mode
Single mode, single-shot scan mode and continuous scan mode
Conversion start trigger Software start
Hardware start
Started by setting the A-D conversion start bit to "1"
A-D0 Converter MJT (input event bus 2), MJT (input event bus 3),
MJT (output event bus 3) and MJT (TIN23S)
Conversion speed
During single mode
BCLK:
(• When sample-and-hold disabled
Slow mode
Internal peripheral clock • When normal sample-and-hold enabled) Fast mode
Normal speed 299BCLK
14.95µs (Note 2)
Double speed 173BCLK
8.65µs
Normal speed 131BCLK
6.55µs
Double speed
During single mode
Slow mode
(When fast sample-and-hold enabled)
Fast mode
During comparator mode
Slow mode
Fast mode
89BCLK
4.45µs
Normal speed 191BCLK
9.55µs
Double speed 101BCLK
5.05µs
Normal speed
95BCLK
4.75µs
Double speed
53BCLK
2.65µs
Normal speed
47BCLK
2.35µs
Double speed
29BCLK
1.45µs
Normal speed
23BCLK
1.15µs
Double speed
17BCLK
0.85µs
Sample-and-hold function Sample-and-hold function can be enabled or disabled as necessary.
A-D disconnection
assist function
Influences of the analog input voltage leakage from any preceding channel during scandetection
mode operation are suppressed.
Interrupt request
Generated when A-D conversion or comparate operation is completed
generation function
Generated when a single-shot scan operation or one cycle of continuous scan operation is completed
DMA transfer request
Generated when A-D conversion or comparate operation is completed
generation function
Generated when a single-shot scan operation or one cycle of continuous scan operation is completed
Note 1: The conversion accuracy stipulated here refers to that of the microcomputer alone, with influences of the power
supply wiring and noise on the board not taken into account.
Note 2: This indicates the conversion time when f(BCLK) = 20 MHz (1 BCLK = 50 ns).
11-3
32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.1 Outline of A-D Converter
Internal data bus
8-bit readout
10-bit readout
Shifter
AD0DT0
10-bit A-D0 Data Register 0
AD0SIM0, 1
A-D0 Single Mode Register
AD0DT1
10-bit A-D0 Data Register 1
AD0SCM0, 1
A-D0 Scan Mode Register
AD0DT2
10-bit A-D0 Data Register 2
AD0DT3
10-bit A-D0 Data Register 3
AD0DT4
10-bit A-D0 Data Register 4
AD0DT5
10-bit A-D0 Data Register 5
AD0DT6
10-bit A-D0 Data Register 6
AD0DT7
10-bit A-D0 Data Register 7
AD0DT8
10-bit A-D0 Data Register 8
AD0DT9
10-bit A-D0 Data Register 9
AD0DT10
10-bit A-D0 Data Register 10
AD0DT11
10-bit A-D0 Data Register 11
AD0CMP
A-D Comparate
Data Register
AD0CTRG1
Input event bus 3
Input event bus 2
Output event bus 3
TIN23S
S
S
AD0STRG1
A-D Control Circuit
AVCC0
AVSS0
10-bit A-D Successive
Approximation Register
(AD0SAR)
Comparator
VREF0
AD0IN0
AD0IN1
AD0IN2
AD0IN3
AD0IN4
AD0IN5
AD0IN6
AD0IN7
AD0IN8
AD0IN9
AD0IN10
AD0IN11
10-bit D-A Converter
• Mode selection
• Channel selection
• Conversion time Interrupt request
selection
• Flag control
DMA transfer request
• Interrupt control
DMA0
DMA common
Sample-and-Hold
Control Circuit
Selector
Successive Approximation-type
A-D Converter Unit
Figure 11.1.1 Block Diagram of the A-D0 Converter
11-4
32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.1 Outline of A-D Converter
11.1.1 Conversion Modes
The A-D Converter has two conversion modes: “A-D Conversion mode” and “Comparator mode.”
(1) A-D Conversion Mode
In A-D conversion mode, the analog input voltage on a specified channel is A-D converted.
In single mode, A-D conversion is performed on a channel selected by the A-D Single Mode Register 1
analog input pin select bit.
In scan mode, A-D conversion is performed on channels selected by A-D Scan Mode Register 1 according to
settings of A-D Scan Mode Register 0.
The conversion result is stored in each channel’s corresponding 10-bit A-D Data Register. There is also an 8bit A-D Data Register for each channel, from which 8-bit A-D conversion results can be read out.
An A-D conversion interrupt or DMA transfer request can be generated when A-D conversion in single mode
is completed, as well as when one cycle of scan loop in scan mode is completed.
(2) Comparator Mode
In comparator mode, the analog input voltage on a specified channel is “comparated” (compared) with the successive approximation register value, and the result (relative magnitude of two values) is returned to a flag.
The channel to be comparated is selected using the A-D Single Mode Register 1 analog input pin select bit.
The result of comparate operation is flagged ("0" or "1") by setting the A-D Comparate Data Register bit that
corresponds to the selected channel.
An A-D conversion interrupt or DMA transfer request can be generated when comparate operation is completed.
11.1.2 Operation Modes
There are two operation modes for the A-D Converter: “Single mode” and “Scan mode.” When comparator mode
is selected as A-D conversion mode, only single mode can be used.
(1) Single Mode
In single mode, the analog input voltage on one selected channel is A-D converted or comparated once. An A-D conversion interrupt or DMA transfer request can be generated when A-D conversion or comparate operation is completed.
A-D conversion interrupt or DMA transfer request
Conversion starts
(Note 1)
ANiINn
Completed
i=1
n=0–11
ADiDTn
10-bit A-Di Data Register
Note 1: A-D0 conversion start: Software trigger → Started by setting the A-D0 conversion start bit to "1"
Hardware trigger → Started by input event bus 3, input event bus 2,
output event bus 3 or TIN23S signal input
Figure 11.1.2 Operation in Single Mode (A-D Conversion)
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A-D Converter
11
11.1 Outline of A-D Converter
A-D Successive Approximation Register
ADiSAR
A-D conversion interrupt
or DMA transfer request
Conversion
starts
ADiINn
i=1
n=0–11
Completed
(Note 1)
ADiCMP
Comparate result
ADiCMP=0 (ANn > ADiSAR)
A-Di Comparate
Data Register
ADiCMP=1 (ANn < ADiSAR)
Note 1: Comparate operation is started by writing a comparison value to the Successive
Approximation Register (ADiSAR)
Figure 11.1.3 Operation in Single Mode (Comparate)
(2) Scan Mode
In scan mode, the analog input voltages from channel 0 (ADiIN0, i = 0) to the channel (channels 0–11)
selected by the A-D Scan Mode Register 1 scan loop select bit are sequentially A-D converted.
There are two types of scan mode: “Single-shot scan mode” in which A-D conversion is completed after
performing one cycle of scan operation, and “Continuous scan mode” in which scan operation is continued
until halted by setting the A-D scan mode register 0’s A-D conversion stop bit to "1".
These types of scan mode are selected using A-D Scan Mode Register 0. The channels to be scanned are
selected using A-D Scan Mode Register 1. The selected channels are scanned sequentially beginning with
channel 0.
An A-D conversion interrupt or DMA transfer request can be generated when one cycle of scan operation is
completed.
<n-channel scan>
i= 1
n=0–11
During continuous scan mode
Conversion
starts
(Note 1)
ADiIN0
10-bit A-Di Data Register
ADiIN1
ADiDT0
ADiINn-1
ADiDT1
Completed here when operating
in single-shot scan mode
ADiINn
ADiDTn-1
ADiDTn
A-D conversion interrupt or DMA transfer request
Note 1: A-D0 conversion start: Software trigger → Started by setting the A-D0 conversion start bit to "1"
Hardware trigger → Started by input event bus 3, input event bus 2,
output event bus 3 or TIN23S signal input
Figure 11.1.4 Operation of A-D Conversion in Scan Mode
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A-D Converter
11
11.1 Outline of A-D Converter
Table 11.1.2 Registers in Which Scan Mode A-D Conversion Results Are Stored
Scan Mode Register 1
Selected channels
Selected channels
A-D conversion result
channel selection
for single-shot scan
for continuous scan
storage register
B'0000:0
ADiIN0
ADiIN0
10-bit A-Di Data Register 0
(ADiIN0)
Completed
ADiIN0
10-bit A-Di Data Register 0
…
…
(Repeated until
forcibly terminated)
B'0001:1
ADiIN0
ADiIN0
10-bit A-Di Data Register 0
(ADiIN1)
ADiIN1
ADiIN1
10-bit A-Di Data Register 1
Completed
ADiIN0
10-bit A-Di Data Register 0
…
…
(Repeated until
forcibly terminated)
B'0010:2
ADiIN0
ADiIN0
10-bit A-Di Data Register 0
(ADiIN2)
ADiIN1
ADiIN1
10-bit A-Di Data Register 1
ADiIN2
ADiIN2
10-bit A-Di Data Register 2
Completed
ADiIN0
10-bit A-Di Data Register 0
…
…
(Repeated until
forcibly terminated)
B'0011:3
ADiIN0
ADiIN0
10-bit A-Di Data Register 0
(ADiIN3)
ADiIN1
ADiIN1
10-bit A-Di Data Register 1
ADiIN2
ADiIN2
10-bit A-Di Data Register 2
ADiIN3
ADiIN3
10-bit A-Di Data Register 3
Completed
ADiIN0
10-bit A-Di Data Register 0
…
…
(Repeated until
forcibly terminated)
B'XXXX:n
ADiIN0
ADiIN0
10-bit A-Di Data Register 0
(ADiINn)
ADiIN1
ADiIN1
10-bit A-Di Data Register 1
ADiIN2
ADiIN2
10-bit A-Di Data Register 2
n≤11
ADiINn
ADiINn
10-bit A-Di Data Register n
Completed
ADiIN0
10-bit A-Di Data Register 0
…
…
(Repeated until
forcibly terminated)
(i=0)
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.1 Outline of A-D Converter
11.1.3 Special Operation Modes
(1) Forcible single mode execution during scan mode
In this special operation mode, single mode conversion (A-D conversion or comparate) is forcibly executed
on a specified channel during scan mode operation. For A-D conversion mode, the conversion result is
stored in the 10-bit A-D Data Register corresponding to the specified channel, whereas for comparate mode,
the conversion result is stored in the 10-bit A-D Comparate Data Register. When the A-D conversion or
comparate operation on a specified channel finishes, scan mode A-D conversion is restarted from where it
was canceled during scan operation.
To start single mode conversion during scan mode operation in software, choose a software trigger using the
A-D Single Mode Register 0 A-D conversion start trigger select bit. Then, for A-D conversion, set the said
register’s A-D conversion start bit to "1". For comparate mode, write a comparison value to the A-D Successive Approximation Register (AD0SAR) during scan mode operation.
To start single mode conversion during scan mode operation in hardware, choose a hardware trigger using
the A-D Single Mode Register 0 A-D conversion start trigger select bit. Then enter the hardware trigger
selected with the said register.
An A-D conversion interrupt or DMA transfer request can be generated when conversion on a specified
channel or one cycle of scan operation is completed.
<To perform single mode conversion on channel ADiIN5
during ADiIN2 conversion in n-channel single-shot scan mode>
i=0
n=0–11
Forcible single mode
execution starts
(Note 1)
ADiIN2
Scan mode
conversion starts
ADiIN0
10-bit A-Di Data Register
ADiIN1
ADiDT0
ADiIN5
ADiDT1
ADiIN2
ADiDT5
ADiINn
ADiDT2
Completed
ADiDTn
A-D conversion interrupt or DMA transfer request
Note 1: The canceled convert operation on channel 2 is reexecuted from the beginning.
Figure 11.1.5 Forcible Single Mode Execution during Scan Mode
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A-D Converter
11
11.1 Outline of A-D Converter
(2) Scan mode start after single mode execution
In this special operation mode, scan operation is started subsequently after executing single mode conversion (A-D conversion or comparate).
To start this mode in software, choose a software trigger using the A-D Scan Mode Register 0 A-D conversion start trigger select bit. Then set the said register’s A-D conversion start bit to "1" during single mode
conversion operation.
To start this mode in hardware, choose a hardware trigger using the A-D Scan Mode Register 0 A-D conversion start trigger select bit. Then enter the hardware trigger selected with the said register during single mode
conversion operation.
If a hardware trigger is selected using the A-D conversion start trigger select bit in both A-D Single Mode
Register 0 and A-D Scan Mode Register 0 and the selected hardware triggers are entered, the A-D Converter
first performs single mode conversion and then scan mode conversion in succession.
An A-D conversion interrupt or DMA transfer request can be generated when single mode conversion on a
specified channel or one cycle of scan operation is completed.
<To start n-channel single-shot scan mode subsequently after single mode conversion on channel ADiIN5>
i=0
n=0–11
Instructed to start
scan mode conversion
Single mode
conversion starts
ADiIN5
10-bit A-Di Data Register
ADiIN0
ADiDT5
ADiIN1
ADiDT0
ADiINn-1
ADiDT1
ADiINn
ADiDTn-1
Completed
ADiDTn
A-D conversion interrupt or DMA transfer request
Figure 11.1.6 Scan Mode Start after Single Mode Execution
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A-D Converter
11
11.1 Outline of A-D Converter
(3) Conversion restart
In this special operation mode, operation being executed in single or scan mode is stopped in the middle and
reexecuted from the beginning.
When in single mode, set the A-D Single Mode Register 0 A-D conversion start bit to "1" again or enter a
hardware trigger during A-D conversion or comparate operation, and the operation being executed is restarted over again.
When in scan mode, set the A-D Scan Mode Register 0 A-D conversion start bit to "1" again or enter a
hardware trigger signal during scan operation, and the channel being converted is canceled and A-D conversion is performed from channel 0 over again.
<To restart single mode ADiIN5 conversion>
i=0
Single mode ADiIN5
restarts
ADiIN5
Single mode
ADiIN5 conversion
starts
Completed
ADiIN5
10-bit A-Di Data Register
ADiDT5
A-D conversion interrupt or DMA transfer request
Figure 11.1.7 Conversion Restart during Single Mode Operation
<To restart during ADiIN2 conversion in n-channel single-shot scan mode>
i=0
n=0–11
Scan mode
restarts
ADiIN2
Scan mode
conversion starts
ADiIN0
10-bit A-Di Data Register
ADiIN1
ADiDT0
ADiIN0
ADiDT1
ADiIN1
ADiDT0
ADiINn-1
ADiDT1
Completed
ADiINn
ADiDTn-1
ADiDTn
A-D conversion interrupt or DMA transfer request
Figure 11.1.8 Conversion Restart during Scan Operation
11-10
32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.1 Outline of A-D Converter
11.1.4 A-D Converter Interrupt and DMA Transfer Requests
The A-D Converter can generate an A-D conversion interrupt or DMA transfer request each time A-D conversion, comparate operation, single-shot scan or one cycle of continuous scan mode is completed. The A-D Single
Mode Register 0 and A-D Scan Mode Register 0 are used to select between A-D conversion interrupt and DMA
transfer requests.
A-Di Scan Mode Register 0
interrupt/DMA transfer request select bit
Scan mode (when one cycle
of scan is completed)
A-Di conversion interrupt request
(To the Interrupt Controller)
DMA transfer request
(To the DMAC)
Single mode (when A-D conversion or
comparate operation is completed)
i=0
A-Di Single Mode Register 0
interrupt/DMA transfer request select bit
Figure 11.1.9 Selecting between Interrupt and DMA Transfer Requests
11.1.5 Sample-and-Hold Function
The analog input voltage that was sampled immediately after A-D conversion started is held on, and A-D conversion is performed on that seized voltage.
The A-D conversion time in “normal” sample-and-hold mode is the same as in conventional A-D conversion
mode of the 32170, etc. The A-D conversion time in “fast” sample-and-hold mode is significantly short, allowing
to obtain conversion results more quickly than ever.
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A-D Converter
11
11.2 A-D Converter Related Registers
11.2 A-D Converter Related Registers
Shown below is an A-D converter related register map.
A-D Converter Related Register Map (1/2)
Address
+0 address
+1 address
b0
H'0080 0080
b7 b8
A-D0 Single Mode Register 0
(AD0SIM0)
H'0080 0082
H'0080 0084
H'0080 0086
H'0080 0088
H'0080 008A
H'0080 008C
H'0080 008E
A-D0 Single Mode Register 1
(AD0SIM1)
See
pages
11-14
11-16
(Use inhibited area)
A-D0 Scan Mode Register 0
A-D0 Scan Mode Register 1
(AD0SCM0)
(AD0SCM1)
A-D0 Disconnection Detection Assist Function Control Register
A-D0 Conversion Speed Control Register
(AD0DDACR)
(AD0CVSCR)
A-D0 Successive Approximation Register
(AD0SAR)
A-D0 Disconnection Detection Assist Method Select Register
(AD0DDASEL)
A-D0 Comparate Data Register
(AD0CMP)
(Use inhibited area)
H'0080 0090
10-bit A-D0 Data Register 0
(AD0DT0)
10-bit A-D0 Data Register 1
(AD0DT1)
10-bit A-D0 Data Register 2
(AD0DT2)
10-bit A-D0 Data Register 3
(AD0DT3)
10-bit A-D0 Data Register 4
(AD0DT4)
10-bit A-D0 Data Register 5
(AD0DT5)
10-bit A-D0 Data Register 6
(AD0DT6)
10-bit A-D0 Data Register 7
(AD0DT7)
10-bit A-D0 Data Register 8
(AD0DT8)
10-bit A-D0 Data Register 9
(AD0DT9)
10-bit A-D0 Data Register 10
(AD0DT10)
10-bit A-D0 Data Register 11
(AD0DT11)
(Use inhibited area)
H'0080 0092
H'0080 0094
H'0080 0096
H'0080 0098
H'0080 009A
H'0080 009C
H'0080 009E
H'0080 00A0
H'0080 00A2
H'0080 00A4
H'0080 00A6
|
H'0080 00D0
(Use inhibited area)
H'0080 00D2
(Use inhibited area)
H'0080 00D4
(Use inhibited area)
H'0080 00D6
b15
H'0080 00D8
(Use inhibited area)
H'0080 00DA
(Use inhibited area)
H'0080 00DC
(Use inhibited area)
H'0080 00DE
(Use inhibited area)
H'0080 00E0
(Use inhibited area)
H'0080 00E2
(Use inhibited area)
11-12
11-24
11-28
11-29
11-29
11-29
11-29
11-29
11-29
11-29
11-29
11-29
11-29
11-29
11-29
8-bit A-D0 Data Register
(AD08DT0)
8-bit A-D0 Data Register
(AD08DT1)
8-bit A-D0 Data Register
(AD08DT2)
8-bit A-D0 Data Register
(AD08DT3)
8-bit A-D0 Data Register
(AD08DT4)
8-bit A-D0 Data Register
(AD08DT5)
8-bit A-D0 Data Register
(AD08DT6)
8-bit A-D0 Data Register
(AD08DT7)
8-bit A-D0 Data Register
(AD08DT8)
8-bit A-D0 Data Register
(AD08DT9)
(Use inhibited area)
11-18
11-20
11-23
11-22
11-27
0
11-30
1
11-30
2
11-30
3
11-30
4
11-30
5
11-30
6
11-30
7
11-30
8
11-30
9
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
A-D Converter Related Register Map (2/2)
Address
+0 address
b0
+1 address
b7 b8
H'0080 00E4
(Use inhibited area)
H'0080 00E6
(Use inhibited area)
b15
8-bit A-D0 Data Register 10
(AD08DT10)
8-bit A-D0 Data Register 11
(AD08DT11)
11-13
See
pages
11-30
11-30
32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
11.2.1 A-D Single Mode Register 0
A-D0 Single Mode Register 0 (AD0SIM0)
b0
1
ADSTRG1
0
0
<Address: H’0080 0080>
2
3
4
5
6
b7
ADSTRG0
ADSSEL
ADSREQ
ADSCMP
ADSSTP
ADSSTT
0
0
0
1
0
0
<After reset: H’04>
b
Bit Name
Function
R
W
0
ADSTRG1 (Note 1)
A-D hardware trigger select 1 bit
Bits 0 and 2 are used to select an A-D hardware trigger.
b0 b2
0 0 : Input event bus 2
0 1 : Input event bus 3
1 0 : Output event bus 3
R
W
1
No function assigned. Fix to "0".
0
0
2
ADSTRG0 (Note 1)
A-D hardware trigger select 0 bit
Bits 0 and 2 are used to select an A-D hardware trigger.
(See the column for bit 0.)
R
W
3
ADSSEL
A-D conversion start trigger select bit
0: Software trigger
1: Hardware trigger (Note 2)
R
W
R
W
1
4
1
: TIN23S signal
ADSREQ
0: A-D conversion interrupt request
Interrupt/DMA transfer request select bit
1: DMA transfer request
5
ADSCMP
A-D conversion/comparate completed bit
0: A-D conversion/comparate in progress
1: A-D conversion/comparate completed
R
–
6
ADSSTP
A-D conversion stop bit
0: No operation
1: Stop A-D conversion
0
W
7
ADSSTT
A-D conversion start bit
0: No operation
1:Start A-D conversion
0
W
Note 1: Two bits—A-D hardware trigger select 1 (bit 0) and A-D hardware trigger select 0 (bit 2)—are used to select an A-D
hardware trigger.
Note 2: During comparator mode, hardware triggers, if any selected, are ignored and operation is started by a software trigger.
A-D Single Mode Register 0 is used to control operation of the A-D Converter during single mode (including
“Forcible single mode execution during scan mode”).
(1) ADSTRG (A-D Hardware Trigger Select) bits (Bits 0 and 2)
These bits select a hardware trigger when A-D conversion by the A-D Converter is to be started in hardware.
Select one from the following hardware trigger sources:
A-D0 Converter: Input event bus 2
Input event bus 3
Output event bus 3
TIN23 edge select output
The contents of these bits are ignored if a software trigger is selected by ADSSEL (A-D conversion start
trigger select bit).
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A-D Converter
11
11.2 A-D Converter Related Registers
(2) ADSSEL (A-D Conversion Start Trigger Select) bit (Bit 3)
This bit selects whether to use a software or hardware trigger to start A-D conversion during single mode.
If a software trigger is selected, A-D conversion is started by setting the ADSSTT (A-D conversion start) bit to
"1". If a hardware trigger is selected, A-D conversion is started by the trigger source selected with the
ADSTRG (hardware trigger select) bits.
(3) ADSREQ (A-D Interrupt/DMA Transfer Request Select) bit (Bit 4)
This bit selects whether to request an A-D conversion interrupt or a DMA transfer when single mode operation (A-D conversion or comparate) is completed. If neither an interrupt nor a DMA transfer are used, choose
to request an A-D conversion interrupt and use the A-D Conversion Interrupt Control Register of the Interrupt
Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control Register to disable DMA transfers to be performed upon completion of A-D conversion.
(4) ADSCMP (A-D Conversion/Comparate Completed) bit (Bit 5)
This is a read-only bit, whose value after reset is "1". This bit is "0" when the A-D Converter is performing
single mode operation (A-D conversion or comparate) and is set to "1" when the operation finishes.
This bit is also set to "1" when A-D conversion or comparate operation is forcibly terminated by setting the
ADSSTP (A-D conversion stop) bit to "1" during A-D conversion or comparate operation.
(5) ADSSTP (A-D Conversion Stop) bit (Bit 6)
Setting this bit to "1" while the A-D Converter is performing single mode operation (A-D conversion or
comparate) causes the operation being performed to stop. Manipulation of this bit is ignored while single
mode operation is idle or scan mode operation is under way.
Operation stops immediately after writing to this bit. If the A-D Successive Approximation Register is read
after being stopped, the content read from the register is the value in the middle of conversion (not transferred to the A-D Data Register).
If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion
stop bit has priority.
If this bit is set to "1" when performing single mode operation in special mode “Forcible single mode execution
during scan mode,” only single mode conversion stops and scan mode operation restarts.
(6) ADSSTT (A-D Conversion Start) bit (Bit 7)
If this bit is set to "1" when a software trigger has been selected with the ADSSEL (A-D conversion start
trigger select) bit, the A-D Converter starts A-D conversion.
If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion
stop bit has priority.
If this bit is set to "1" again while performing single mode conversion, special operation mode “Conversion
restart” is turned on, so that single mode conversion restarts.
If this bit is set to "1" again while performing A-D conversion in scan mode, special operation mode “Forcible
single mode execution during scan mode” is turned on, so that the channel being converted in scan mode is
canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode
A-D conversion restarts beginning with the canceled channel.
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A-D Converter
11
11.2 A-D Converter Related Registers
11.2.2 A-D Single Mode Register 1
A-D0 Single Mode Register 1 (AD0SIM1)
b8
9
ADSMSL
ADSSPD
0
0
10
11
12
13
0
14
b15
0
0
ANSEL
ADSSHSL ADSSHSPD
0
<Address: H’0080 0081>
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
ADSMSL
A-D conversion mode select bit
0: A-D conversion mode
1: Comparator mode
R
W
9
ADSSPD (Note 1)
A-D conversion speed select bit
0: Normal speed
1: Double speed
R
W
10
ADSSHSL
A-D conversion method select bit
0: Disable sample-and-hold
1: Enable sample-and-hold
R
W
11
ADSSHSPD (Note 2)
0: Normal sample-and-hold
R
W
A-D sample-and-hold conversion speed select bit
1: Fast sample-and-hold
ANSEL
A-D analog input pin select bit
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
R
W
12–15
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Select ADiIN0
Select ADiIN1
Select ADiIN2
Select ADiIN3
Select ADiIN4
Select ADiIN5
Select ADiIN6
Select ADiIN7
Select ADiIN8
Select ADiIN9
Select ADiIN10
Select ADiIN11
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
(i = 0)
Note 1: The A-D conversion speed is determined by a combination of ADSSPD, ADSSHSL and ADSSHSPD bits and the A-D
Conversion Speed Control Register ADCVSD bit.
Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADSSHSL bit.
A-D Single Mode Register 1 is used to select operation mode, conversion speed and analog input pins when the
A-D Converter is operating in single mode.
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A-D Converter
11
11.2 A-D Converter Related Registers
(1) ADSMSL (A-D Conversion Mode Select) bit (Bit 8)
This bit selects A-D conversion mode when the A-D Converter is operating in single mode. Setting this bit to
"0" selects A-D conversion mode, and setting this bit to "1" selects comparator mode.
(2) ADSSPD (A-D Conversion Speed Select) bit (Bit 9)
This bit selects the A-D conversion speed when the A-D Converter is operating in single mode. Setting this bit
to "0" selects normal speed, and setting this bit to "1" selects double speed.
(3) ADSSHSL (A-D Conversion Method Select) bit (Bit 10)
This bit enables or disables the sample-and-hold function when the A-D Converter is operating in single
mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the
sample-and-hold function.
Setting of this bit has no effect if comparator mode is selected with the ADSMSL (A-D conversion mode
select) bit.
(4) ADSSHSPD (A-D Sample-and-Hold Speed Select) bit (Bit 11)
When the A-D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When
this bit is "0", the conversion speed is the same as normal A-D conversion speed. When this bit is "1",
conversion is performed at a speed faster than normal A-D conversion speed.
Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADSSHSL (A-D
conversion method select) bit to "0".
For details about the conversion time, see Section 11.3.4, “Calculating the A-D Conversion Time.”
(5) ANSEL (A-D Analog Input Pin Select) bits (Bits 12–15)
These bits select the analog input pins when the A-D Converter is operating in single mode. A-D conversion
or comparate operation is performed on the channels selected with these bits. If these bits are accessed for
read, the value written to them is read out.
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A-D Converter
11
11.2 A-D Converter Related Registers
11.2.3 A-D Scan Mode Register 0
A-D0 Scan Mode Register 0 (AD0SCM0)
<Address: H’0080 0084>
b0
1
2
3
4
5
6
b7
ADCTRG1
ADCMSL
ADCTRG0
ADSHIDE
ADCREQ
ADCCMP
ADCSTP
ADCSTT
0
0
0
0
0
1
0
0
<After reset: H’04>
b
Bit Name
Function
R
W
0
ADCTRG1 (Note 1)
A-D hardware trigger select 1 bit
Bits 0 and 2 are used to select an A-D hardware trigger.
b0 b2
0 0 : Input event bus 2
0 1 : Input event bus 3
1 0 : Output event bus 3
1 1
: TIN23S signal
R
W
1
ADCMSL
A-D scan mode select bit
0: Single-shot mode
1: Continuous mode
R
W
2
ADCTRG0 (Note 1)
A-D hardware trigger select 0 bit
Bits 0 and 2 are used to select an A-D hardware trigger.
(See the column for bit 0.)
R
W
3
ADCSEL
0: Software trigger
R
W
A-D conversion start trigger select bit
1: Hardware trigger
4
ADCREQ
Interrupt/DMA transfer request select bit
0: A-D conversion interrupt request
1: DMA transfer request
R
W
5
ADCCMP
A-D conversion completed bit
0: A-D conversion in progress
1: A-D conversion completed
R
–
6
ADCSTP
A-D conversion stop bit
0: No operation
1: Stop A-D conversion
0
W
7
ADCSTT
0: No operation
0
W
A-D conversion start bit
1: Start A-D conversion
Note 1: Two bits—A-D hardware trigger select 1 (bit 0) and A-D hardware trigger select 0 (bit 2)—are used to select an A-D
hardware trigger.
A-D Scan Mode Register 0 is used to control operation of the A-D Converter during scan mode.
(1) ADCTRG (A-D Hardware Trigger Select) bits (Bits 0 and 2)
These bits select a hardware trigger when A-D conversion by the A-D Converter is to be started in hardware.
Select one from the following hardware trigger sources:
A-D0 Converter: Input event bus 2
Input event bus 3
Output event bus 3
TIN23 edge select output
The contents of these bits are ignored if a software trigger is selected by ADCSEL (A-D conversion start
trigger select bit).
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
(2) ADCMSL (A-D Scan Mode Select) bit (Bit 1)
This bit selects scan mode of the A-D Converter between single-shot scan and continuous scan.
Setting this bit to "0" selects single-shot scan mode, where the channels selected with the ANSCAN (A-D
scan loop select) bits are sequentially A-D converted and when A-D conversion on all selected channels is
completed, the conversion operation stops.
Setting this bit to "1" selects continuous scan mode, where after operation in single-shot scan mode finishes,
A-D conversion is reexecuted beginning with the first channel and continued until stopped by setting the
ADCSTP (A-D conversion stop) bit to "1".
(3) ADCSEL (A-D Conversion Start Trigger Select) bit (Bit 3)
This bit selects whether to use a software or hardware trigger to start A-D conversion during scan mode. If a
software trigger is selected, A-D conversion is started by setting the ADCSTT (A-D conversion start) bit to
"1". If a hardware trigger is selected, A-D conversion is started by the trigger source selected with the
ADCTRG (hardware trigger select) bits.
(4) ADCREQ (A-D Interrupt/DMA Transfer Request Select) bit (Bit 4)
This bit selects whether to request an A-D conversion interrupt or a DMA transfer when one cycle of scan
mode operation is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A-D
conversion interrupt and use the A-D Conversion Interrupt Control Register of the Interrupt Controller (ICU)
to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control
Register to disable DMA transfers to be performed upon completion of A-D conversion.
(5) ADCCMP (A-D Conversion Completed) bit (Bit 5)
This is a read-only bit, whose value after reset is "1". This bit is "0" when the A-D Converter is performing
scan mode A-D conversion and is set to "1" when single-shot scan mode finishes or continuous scan mode
is stopped by setting the ADCSTP (A-D conversion stop) bit to "1".
(6) ADCSTP (A-D Conversion Stop) bit (Bit 6)
Setting this bit to "1" while the A-D Converter is performing scan mode A-D conversion causes the operation
being performed to stop. This bit is effective only for scan mode operation, and does not affect single mode
operation even when single and scan modes both are active during special operation mode.
Operation stops immediately after writing to this bit, and the A-D conversion being performed on any channel
is aborted in the middle, without transferring the result to the A-D data register.
If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion
stop bit has priority.
(7) ADCSTT (A-D Conversion Start) bit (Bit 7)
This bit is used to start scan mode operation of the A-D Converter in software. Only when a software trigger
has been selected with the ADCSEL (A-D conversion start trigger select) bit, setting this bit to "1" causes AD conversion to start.
If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion
stop bit has priority.
If this bit is set to "1" again while performing scan mode conversion, special operation mode “Conversion
restart” is turned on, so that scan mode operation is restarted using the contents set by A-D Scan Mode
Registers 0 and 1.
If this bit is set to "1" again while performing A-D conversion in single mode, special operation mode “Scan
mode start after single mode execution” is turned on, so that scan mode operation starts subsequently after
single mode has finished.
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
11.2.4 A-D Scan Mode Register 1
A-D0 Scan Mode Register 1 (AD0SCM1)
b8
9
10
11
12
13
0
0
ADCSPD ADCSHSL ADCSHSPD
0
0
0
0
<Address: H’0080 0085>
14
b15
ADSCAN
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8
No function assigned. Fix to "0".
0
0
9
ADCSPD (Note 1)
A-D conversion speed select bit
0: Normal speed
1: Double speed
R
W
10
ADCSHSL
A-D conversion method select bit
0: Disable sample-and-hold
1: Enable sample-and-hold
R
W
11
ADCSHSPD (Note 2)
0: Normal sample-and-hold
R
W
A-D sample-and-hold conversion speed select bit
1: Fast sample-and-hold
ANSCAN
A-D scan loop select bit
<For write>
‘B0000–1011 (channels 0–11)
<For read during conversion>
0000: Converting ADiIN0
0001: Converting ADiIN1
0010: Converting ADiIN2
0011: Converting ADiIN3
0100: Converting ADiIN4
0101: Converting ADiIN5
0110: Converting ADiIN6
0111: Converting ADiIN7
1000: Converting ADiIN8
1001: Converting ADiIN9
1010: Converting ADiIN10
1011: Converting ADiIN11
1100: (Note 3)
1101: (Note 3)
1110: (Note 3)
1111: (Note 3)
R
W
12–15
(i = 0)
Note 1: The A-D conversion speed is determined by a combination of ADCSPD, ADCSHSL and ADCSHSPD bits and the A-D
Conversion Speed Control Register ADCVSD bit.
Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADCSHSL bit.
Note 3: Because the 32182 has pins for only AD0IN0–AD0IN11, in no case will this bit pattern be read out, providing that the number
of scan channels is correctly set.
A-D Scan Mode Register 1 is used to select operation mode, conversion speed and scan loop when the A-D
Converter is operating in scan mode. The channels selected with the scan loop select bit are scanned sequentially beginning with channel 0 (n-channel scan).
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A-D Converter
11
11.2 A-D Converter Related Registers
(1) ADCSPD (A-D Conversion Speed Select) bit (Bit 9)
This bit selects an A-D conversion speed when the A-D Converter is operating in scan mode. Setting this bit
to "0" selects normal speed, and setting this bit to "1" selects double speed.
(2) ADCSHSL (A-D Conversion Method Select) bit (Bit 10)
This bit enables or disables the sample-and-hold function when the A-D Converter is operating in scan mode.
Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sampleand-hold function.
(3) ADCSHSPD (A-D Sample-and-Hold Speed Select) bit (Bit 11)
When the A-D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When
this bit is "0", the conversion speed is the same as normal A-D conversion speed. When this bit is "1",
conversion is performed at a speed faster than normal A-D conversion speed.
Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADCSHSL (A-D
conversion method select) bit to "0".
For details about the conversion time, see Section 11.3.4, “Calculating the A-D Conversion Time.”
(4) ANSCAN (A-D Scan Loop Select) bits (Bits 12–15)
The ANSCAN (A-D scan loop select) bits set the channels to be scanned during scan mode of the A-D
Converter.
The ANSCAN (A-D scan loop select) bits when accessed for read during scan operation serve as a status
register indicating the channel being scanned.
The value read from these bits during single mode is always B’0000.
If A-D conversion is stopped by setting A-D Scan Mode Register 0 ADCSTP (A-D conversion stop) bit to "1"
while executing scan mode, the value read from these bits indicates the channel whose A-D conversion has
been canceled.
Also, if read during single mode conversion of special operation mode “Forcible single mode execution during scan mode,” the value of these bits indicates the channel whose A-D conversion has been canceled in
the middle of scan.
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A-D Converter
11
11.2 A-D Converter Related Registers
11.2.5 A-D Conversion Speed Control Register
A-D0 Conversion Speed Control Register (AD0CVSCR)
b8
9
10
11
12
13
14
0
0
0
0
0
0
0
<Address: H’0080 0087>
b15
ADCVSD
0
<After reset: H’00>
b
Bit Name
8–14
No function assigned. Fix to "0".
15
ADCVSD (Note 1)
A-D conversion speed control bit
Function
R
W
0
0
0: Slow mode
1: Fast mode
R
W
Note 1: The A-D conversion speed is determined by a combination of ADCVSD bit and A-D Single Mode Register 1’s relevant bit
during single mode, or a combination of ADCVSD bit and A-D Scan Mode Register 1’s relevant bit during scan mode.
The A-D Conversion Speed Control Register controls the A-D conversion speed during single and scan modes
of the A-D Converter. The A-D conversion speed is determined in combination with A-D Single Mode Register
1's conversion speed select bit (Double/Normal).
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
11.2.6 A-D Disconnection Detection Assist Function Control Register
A-D0 Disconnection Detection Assist Function Control Register (AD0DDACR)
b0
1
2
3
4
5
6
0
0
0
0
0
0
0
<Address: H’0080 0086>
b7
ADDDAEN
0
<After reset: H’00>
b
Bit Name
Function
0–6
No function assigned. Fix to "0".
7
ADDDAEN (Note 1)
A-D disconnection detection assist function enable bit
R
W
0
0
0: Disable A-D disconnection detection assist function R
1: Enable A-D disconnection detection assist function
W
Note 1: For the A-D disconnection detection assist function to be enabled, the conversion start state (discharge or precharge) must
be set using the A-D disconnection detection assist method select register after setting the ADDDAEN bit to "1".
The A-D Disconnection Detection Assist Function Control Register is used to enable or disable the content of
the A-D Disconnection Detection Assist Method Select Register.
Note: • If any analog input wiring is disconnected, the conversion result varies depending on the circuits
fitted external to the chip. This function must be fully evaluated in the actual application system
before it can be used.
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A-D Converter
11
11.2 A-D Converter Related Registers
11.2.7 A-D Disconnection Detection Assist Method Select Register
A-D0 Disconnection Detection Assist Method Select Register (AD0DDASEL)
b0
<Address: H’0080 008A>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADDDA
SEL0
ADDDA
SEL1
ADDDA
SEL2
ADDDA
SEL3
ADDDA
SEL4
ADDDA
SEL5
ADDDA
SEL6
ADDDA
SEL7
ADDDA
SEL8
ADDDA
SEL9
ADDDA
SEL10
ADDDA
SEL11
ADDDA
SEL12
ADDDA
SEL13
ADDDA
SEL14
ADDDA
SEL15
b15
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0
ADDDASEL0
Channel 0 disconnection detection assist method select bit
0: Discharge before conversion
1: Precharge before conversion
R
W
1
ADDDASEL1
Channel 1 disconnection detection assist method select bit
2
ADDDASEL2
Channel 2 disconnection detection assist method select bit
3
ADDDASEL3
Channel 3 disconnection detection assist method select bit
4
ADDDASEL4
Channel 4 disconnection detection assist method select bit
5
ADDDASEL5
Channel 5 disconnection detection assist method select bit
6
ADDDASEL6
Channel 6 disconnection detection assist method select bit
7
ADDDASEL7
Channel 7 disconnection detection assist method select bit
8
ADDDASEL8
Channel 8 disconnection detection assist method select bit
9
ADDDASEL9
Channel 9 disconnection detection assist method select bit
10
ADDDASEL10
Channel 10 disconnection detection assist method select bit
11
ADDDASEL11
Channel 11 disconnection detection assist method select bit
12
ADDDASEL12
Channel 12 disconnection detection assist method select bit
13
ADDDASEL13
Channel 13 disconnection detection assist method select bit
14
ADDDASEL14
Channel 14 disconnection detection assist method select bit
15
ADDDASEL15
Channel 15 disconnection detection assist method select bit
Notes: • This register must always be accessed in halfwords.
• For these bits to be enabled, the ADDDAEN bit (A-D Disconnection Detection Assist Function Control Register bit 7) must
be set to "1" before setting these bits.
In order to prevent the A-D conversion result from being affected by the analog input voltage leakage from any
preceding channel, the A-D Disconnection Detection Assist Method Select Register is used to control the conversion start state by selecting whether to discharge or precharge the chopper amp capacitor before starting
regular conversion operation.
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
Figure 11.2.1 shows an example of A-D disconnection detection assist method in which the conversion start
state is set to the AVCC side (i.e., precharge before conversion is selected). Figure 11.2.2 shows an example
of A-D disconnection detection assist method in which the conversion start state is set to the AVSS side (i.e.,
discharge before conversion is selected).
On
Precharge
control signal
Off
Discharge
control signal
Precharge
Typical external circuit (Note 1)
ADDDAEN
R
Analog input
ADiINn
Chopper amp
capacitor
Broken wire
C
Note 1: In case of broken wire, the conversion result varies with external circuits.
Therefore, careful evaluation is required before this function can be used.
Figure 11.2.1 Example of A-D Disconnection Detection on AVCC Side (Precharge Before Conversion Selected)
ADDDAEN
Off
Precharge
control signal
On
Discharge
control signal
Typical external circuit (Note 1)
Analog input
ADiINn
Broken wire
Discharge
Chopper amp
capacitor
R
C
Note 1: In case of broken wire, the conversion result varies with external circuits.
Therefore, careful evaluation is required before this function can be used.
Figure 11.2.2 Example of A-D Disconnection Detection on AVSS Side (Discharge Before Conversion Selected)
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
Disconnection detection voltage (without sample-and-hold)
2000
1800
Voltage on disconnected port [mV]
Scan mode: Disconnection detection enabled
1600
Scan mode: Disconnection detection disabled
1400
1200
1000
800
600
400
200
0
0
20
40
60
80
100
120
A-D conversion cycle [kHz]
Figure 11.2.3 A-D Disconnection Detection Assist Data (when Discharge Before Conversion Selected)
Disconnection detection voltage (without sample-and-hold)
5100
Voltage on disconnected port [mV]
4900
Scan mode: Disconnection detection enabled
4700
Scan mode: Disconnection detection disabled
4500
4300
4100
3900
3700
3500
3300
3100
2900
0
20
40
60
80
100
120
A-D conversion cycle [kHz]
Figure 11.2.4 A-D Disconnection Detection Assist Data (when Precharge Before Conversion Selected)
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
11.2.8 A-D Successive Approximation Register
A-D0 Successive Approximation Register(AD0SAR)
b0
1
2
3
4
5
6
<Address: H’0080 0088>
7
8
9
10
11
12
13
14
?
?
?
b15
ADSAR
0
0
0
0
0
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–5
No function assigned. Fix to "0".
Function
6–15
ADSAR
A-D successive approximation value/comparison value
• A-D successive approximation value (A-D conversion mode)
• Comparison value (comparator mode)
R
W
0
0
R
W
Note: • This register must always be accessed in halfwords.
The A-D Successive Approximation Register (ADSAR) is used to read the conversion result of the A-D Converter when operating in A-D conversion mode or write a comparison value when operating in comparator mode.
In A-D conversion mode, the successive approximation method is used to perform A-D conversion. With this
method, the reference voltage VREF and analog input voltages are sequentially compared bitwise beginning
with the high-order bit, and the comparison result is set in the A-D Successive Approximation Register (ADSAR)
bits 6–15. When the A-D conversion has finished, the value of this register is transferred to the 10-bit A-D Data
Register (ADDTn) corresponding to each converted channel. When this register is accessed for read in the
middle of A-D conversion, the value read from the register indicates the intermediate result of conversion.
In comparator mode, this register is used to write a comparison value (the voltage with which to “comparate”).
Simultaneously with a write to this register, the A-D Converter starts comparing the voltage on the analog input
pin selected with A-D Single Mode Register 1 and the value written in this register. After comparate operation,
the result is stored in the A-D Comparate Data Register (ADCMP).
Use the calculation formula shown below to find the comparison value to be written to the A-D Successive
Approximation Register (ADSAR) during comparator mode.
Comparison value = H’3FF x
Comparate comparison voltage [V]
VREF0 input voltage [V]
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
11.2.9 A-D Comparate Data Register
A-D0 Comparate Data Register (AD0CMP)
b0
<Address: H’0080 008C>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
AD
CMP0
AD
CMP1
AD
CMP2
AD
CMP3
AD
CMP4
AD
CMP5
AD
CMP6
AD
CMP7
AD
CMP8
AD
CMP9
AD
CMP10
AD
CMP11
AD
CMP12
AD
CMP13
AD
CMP14
AD
CMP15
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–11
ADCMP0–ADCMP11 (Note 1)
A-D comparate result flag
0: Analog input voltage > comparison voltage
1: Analog input voltage < comparison voltage
R
–
12–15
(Note 2)
R
–
Note 1: During comparator mode, the bits in this register correspond one for one to channels 0–11.
Note 2: Because the 32182 does not have the corresponding analog pins, the values read out from these bits are undefined.
Note: • This register must always be accessed in halfwords.
When comparator mode is selected using the A-D Single Mode Register 1 ADSMSL (A-D conversion mode
select) bit, the selected analog input voltage is compared with the value written to the A-D Successive Approximation Register and the result is stored in the corresponding bit of this comparate data register.
The bit or flag in this register is "0" when analog input voltage > comparison voltage, or "1" when analog input
voltage < comparison voltage.
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32182 Group User's Manual (Rev.1.0)
A-D Converter
11
11.2 A-D Converter Related Registers
11.2.10 10-bit A-D Data Registers
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
10-bit
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
b0
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
1
2
0(AD0DT0)
1(AD0DT1)
2(AD0DT2)
3(AD0DT3)
4(AD0DT4)
5(AD0DT5)
6(AD0DT6)
7(AD0DT7)
8(AD0DT8)
9(AD0DT9)
10(AD0DT10)
11(AD0DT11)
3
4
5
<Address: H’0080 0090>
<Address: H’0080 0092>
<Address: H’0080 0094>
<Address: H’0080 0096>
<Address: H’0080 0098>
<Address: H’0080 009A>
<Address: H’0080 009C>
<Address: H’0080 009E>
<Address: H’0080 00A0>
<Address: H’0080 00A2>
<Address: H’0080 00A4>
<Address: H’0080 00A6>
6
7
8
9
10
11
12
13
14
?
?
?
b15
AD0DT0-AD0DT11
0
0
0
0
0
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–5
No function assigned.
6–15
AD0DT0-AD0DT11
10-bit A-D data
Function
10-bit A-D conversion result
R
W
0
–
R
–
Note: • This register must always be accessed in halfwords.
During single mode, the 10-bit A-D Data Registers are used to store the result of A-D conversion performed on
each corresponding channel.
During single-shot or continuous scan mode, the content of the A-D Successive Approximation Register is
transferred to the 10-bit A-D Data Register for the corresponding channel when A-D conversion on each channel
has finished. Each 10-bit A-D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time.
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A-D Converter
11
11.2 A-D Converter Related Registers
11.2.11 8-bit A-D Data Registers
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
A-D0
b8
9
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
10
0(AD08DT0)
1(AD08DT1)
2(AD08DT2)
3(AD08DT3)
4(AD08DT4)
5(AD08DT5)
6(AD08DT6)
7(AD08DT7)
8(AD08DT8)
9(AD08DT9)
10(AD08DT10)
11(AD08DT11)
11
12
<Address: H’0080 00D1>
<Address: H’0080 00D3>
<Address: H’0080 00D5>
<Address: H’0080 00D7>
<Address: H’0080 00D9>
<Address: H’0080 00DB>
<Address: H’0080 00DD>
<Address: H’0080 00DF>
<Address: H’0080 00E1>
<Address: H’0080 00E3>
<Address: H’0080 00E5>
<Address: H’0080 00E7>
13
14
b15
?
?
?
AD08DT0-AD08DT15
?
?
?
?
?
<After reset: Undefined>
b
8–15
Bit Name
Function
R
W
AD08DT0-AD08DT11
8-bit A-D conversion result
R
–
8-bit A-D data
During single mode, the 8-bit A-D Data Registers are used to store the result of A-D conversion performed on
each corresponding channel.
During single-shot or continuous scan mode, the content of the A-D Successive Approximation Register is
transferred to the 8-bit A-D Data Register for the corresponding channel when A-D conversion on each channel
has finished. Each 8-bit A-D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time.
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A-D Converter
11
11.3 Functional Description of A-D Converter
11.3 Functional Description of A-D Converter
11.3.1 How to Find Analog Input Voltages
The A-D Converter performs A-D conversion using a 10-bit successive approximation method. The equation
shown below is used to calculate the actual analog input voltage from the digital value obtained by executing AD conversion.
Analog input voltage [v] =
A-D conversion result x VREF input voltage [V]
1,024
The A-D Converter is a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the
reference voltage for the A-D Converter is the voltage applied to the VREF pin, make sure that an exact and
stable constant-voltage power supply is connected to VREF. Also make sure the analog circuit power supply
and ground (AVCC, AVSS) are separated from those of the digital circuit, with sufficient noise prevention measures incorporated.
For details about the conversion accuracy, see Section 11.3.5, “Accuracy of A-D Conversion.”
10-bit
A-Di Data Register
ADiDT0–11
A-Di Comparate
Data Register
AVCCi
AVSSi
i=0
ADiCMP
10-bit A-Di Successive
Approximation Register
(ADiSAR)
A-D Control Circuit
Vref
VREFi
10-bit D-A Converter
VIN
ADiIN0
ADiIN1
ADiIN2
ADiIN3
ADiIN4
ADiIN5
ADiIN6
ADiIN7
ADiIN8
ADiIN9
ADiIN10
ADiIN11
Comparator
Sample-and-Hold
Control Circuit
Selector
Successive Approximation-type
A-D Converter Unit
Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A-D Converter Unit
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A-D Converter
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11.3 Functional Description of A-D Converter
11.3.2 A-D Conversion by Successive Approximation Method
The A-D Converter use an A-D conversion start trigger (software or hardware) as they start A-D conversion.
Once A-D conversion begins, the following operation is automatically performed.
1. During single mode, A-D Single Mode Register 0’s A-D conversion/comparate completion bit is cleared to "0".
During scan mode, A-D Scan Mode Register 0’s A-D conversion completion bit is cleared to "0".
2. The content of the A-D Successive Approximation Register is cleared to H’0000.
3. The A-D Successive Approximation Register’s most significant bit (bit 6) is set to "1".
4. The comparison voltage, Vref (Note 1), is fed from the D-A Converter into the comparator.
5. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison result
will be stored in bit 6.
If Vref < VIN, then bit 6 = "1"
If Vref > VIN, then bit 6 = "0"
6. Operations in 3 through 5 above are executed for all other bits from bit 7 to bit 15.
7. The value stored in the A-D Successive Approximation Register by the time comparison for bit 15 has finished
is held in it as the A-D conversion result.
A-D Successive Approximation Register (ADiSAR)
b6
7
8
9
10
11
12
13
14 b15
1st comparison
1
0
0
0
0
0
0
0
0
0
2nd comparison
n9
1
0
0
0
0
0
0
0
0
0
0
0
0
i=0
If Vref > VIN, then nX = 0
If Vref < VIN, then nX = 1
Result of 1st comparison
3rd comparison
n9
n8
1
0
0
0
Result of 2nd comparison
10th comparison
n9
n8
n7
n6
n5
n4
n3
n2
n1
1
Conversion
completed
n9
n8
n7
n6
n5
n4
n3
n2
n1
n0
Figure 11.3.2 Changes of the A-D Successive Approximation Register during A-D Convert Operation
Note 1: The comparison voltage, Vref (the voltage fed from the D-A Converter into the comparator), is
determined according to changes of the A-D Successive Approximation Register content. Shown
below are the equations used to calculate the comparison voltage, Vref.
• If the A-D Successive Approximation Register content = 0
Vref [V] = 0
• If the A-D Successive Approximation Register content = 1 to 1,023
Vref [V] = (reference voltage VREF / 1,024) × (A-D Successive Approximation Register content – 0.5)
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11.3 Functional Description of A-D Converter
The conversion result is stored in the 10-bit A-D Data Register (AD0DTn) corresponding to each converted
channel. There is also an 8-bit A-D Data Register (AD08DTn) for each channel, from which the 8 high-order bits
of the 10-bit conversion result can be read out.
The following shows the procedure for A-D conversion by a successive approximation method in each operation mode.
(1) Single mode
The convert operation stops when comparison for the A-D Successive Approximation Register bit 15 is
completed. The content (A-D conversion result) of the A-D Successive Approximation Register is transferred
to the 10-bit A-D Data Registers 0–11 for the converted channel.
(2) Single-shot scan mode
When comparison for the A-D Successive Approximation Register bit 15 on a specified channel is completed, the
content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0–11, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted.
In single-shot scan mode, the convert operation stops when A-D conversion in one specified scan loop is completed.
(3) Continuous scan mode
When comparison for the A-D Successive Approximation Register bit 15 on a specified channel is completed, the
content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0–11, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted.
In continuous scan mode, the convert operation is executed continuously until scan operation is forcibly terminated by setting the A-D conversion stop bit (Scan Mode Register 0 bit 6) to "1".
11.3.3 Comparator Operation
When comparator mode (single mode only) is selected, the A-D Converter functions as a comparator which
compares analog input voltages with the comparison voltage that is set by software.
When a comparison value is written to the successive approximation register, the A-D Converter starts
“comparating” the analog input voltage selected by the Single Mode Register 1 analog input select bit with the
value written into the successive approximation register. Once comparate begins, the following operation is
automatically executed.
1. The A-D Single Mode Register 0 or A-D Scan Mode Register 0 A-D conversion/comparate completion bit
is cleared to "0".
2. The comparison voltage, Vref (Note 1), is fed from the D-A Converter into the comparator.
3. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison
result will be stored in the comparate result flag for the corresponding channel.
If Vref < VIN, then the comparate result flag = 0
If Vref > VIN, then the comparate result flag = 1
4. The comparate operation is stopped after storing the comparison result.
The comparison result is stored in the A-D Comparate Data Register (AD0CMP)’s corresponding bit.
Note 1: The comparison voltage, Vref (the voltage fed from the D-A Converter into the comparator), is
determined according to changes of the A-D Successive Approximation Register content. Shown
below are the equations used to calculate the comparison voltage, Vref.
• If the A-D Successive Approximation Register content = 0
Vref [V] = 0
• If the A-D Successive Approximation Register content = 1 to 1,023
Vref [V] = (reference voltage VREF / 1,024) x (A-D Successive Approximation Register content – 0.5)
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11.3 Functional Description of A-D Converter
11.3.4 Calculating the A-D Conversion Time
The A-D conversion time is expressed by the sum of dummy cycle time and actual execution cycle time. The
following shows each time factor necessary to calculate the conversion time.
1. Start dummy time
A time from when the CPU executed the A-D conversion start instruction to when the A-D Converter
starts A-D conversion
2. A-D conversion execution cycle time
If sample-and-hold is enabled, the sampling time is included in this execution cycle time.
3. Comparate execution cycle time
4. End dummy time
A time from when the A-D Converter has finished A-D conversion to when the CPU can stably read out
the conversion result from the A-D data register.
5. Scan to scan dummy time
A time during single-shot or continuous scan mode from when the A-D Converter has finished A-D
conversion on a channel to when it starts A-D conversion on the next channel.
The equation to calculate the A-D conversion time is as follows:
A-D conversion time = Start dummy time + Execution cycle time
(+ Scan to scan dummy time + Execution cycle time
+ Scan to scan dummy time + Execution cycle time
+ Scan to scan dummy time .... + Execution cycle time)
+ End dummy time
Note: • Enclosed in ( ) are the conversion time required for the second and subsequent channels
to be converted in scan mode.
(1) Calculating the conversion time during A-D conversion mode
The following schematically shows the method for calculating the conversion time during A-D conversion mode.
<Single mode>
Transferred to the
A-D data register
A-D conversion Convert operation
start trigger
starts
Start dummy
Execution cycle
Completed
End dummy
<Scan mode>
(Channel 0)
Start dummy
(Channel 1)
Scan to
scan dummy
Execution cycle
Execution cycle
(Last channel)
Scan to
scan dummy
Execution cycle
End dummy
Figure 11.3.3 Conceptual Diagram of A-D Conversion Time
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11.3 Functional Description of A-D Converter
Table 11.3.1 Conversion Clock Periods in A-D Conversion Mode
Unit: BCLK
Conversion speed
Start dummy (Note 1) Execution cycle
End dummy
Scan to scan dummy (Note 2)
Slow mode
Normal speed
4
294
1
4
Double speed
4
168
1
4
Normal speed
4
126
1
4
Double speed
4
84
1
4
Fast mode
Note 1: The same applies to both software and hardware triggers.
Note 2: Only during scan operation, execution time per channel is added.
(2) Calculating the conversion time when sample-and-hold is enabled
The following schematically shows the method for calculating the conversion time when the sample-and-hold
function is enabled.
A-D conversion
start trigger
Convert operation
starts
Completed
Execution cycle
Start dummy Sampling
time
End dummy
Figure 11.3.4 Conceptual Diagram of A-D Conversion Time when Sample-and-Hold is Enabled
Table 11.3.2 Conversion Clock Periods during Normal Sample-and-Hold Mode
Unit: BCLK
Conversion speed
Start dummy (Note 1) Execution cycle
End dummy
Scan to scan dummy (Note 2)
Slow mode
Normal speed
4
294
1
4
Double speed
4
168
1
4
Normal speed
4
126
1
4
Double speed
4
84
1
4
Fast mode
Note 1: The same applies to both software and hardware triggers.
Note 2: Only during scan operation, execution time per channel is added.
Table 11.3.3 Conversion Clock Periods during Fast Sample-and-Hold Mode
Unit: BCLK
Conversion speed
Start dummy (Note 1) Execution cycle
End dummy
Scan to scan dummy (Note 2)
Slow mode
Normal speed
4
186
1
4
Double speed
4
96
1
4
Normal speed
4
90
1
4
Double speed
4
48
1
4
Fast mode
Note 1: The same applies to both software and hardware triggers.
Note 2: Only during scan operation, execution time per channel is added.
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11.3 Functional Description of A-D Converter
(3) Calculating the conversion time during comparator mode
The following schematically shows the method for calculating the conversion time during comparator mode.
A-D conversion Convert operation
starts
start trigger
Start dummy
Transferred to the
comparate data register
Execution cycle
Completed
End dummy
Figure 11.3.5 Conceptual Diagram of A-D Conversion Time during Comparator Mode
Table 11.3.4 Conversion Clock Periods during Comparator Mode
Conversion speed
Slow mode
Fast mode
Start dummy
Unit: BCLK
Execution cycle
End dummy
Normal speed
4
42
1
Double speed
4
24
1
Normal speed
4
18
1
Double speed
4
12
1
(4) A-D conversion time
A total A-D conversion time in various modes are shown in the table below.
Table 11.3.5 A-D Conversion Time (Total Time)
Conversion start method
Conversion speed
Unit: BCLK
Conversion mode (Note 1)
Conversion time
When fast sampleand-hold enabled
Software and
Normal speed Single mode
hardware triggers
n-channel single-shot scan/
(Note 2)
299
191
(298 × n)+1
(190 × n)+1
47
47
173
101
(172 × n)+1
(100 × n)+1
29
29
131
95
(130 × n)+1
(94 × n)+1
23
23
89
53
(88 × n)+1
(52 × n)+1
17
17
continuous scan mode
Slow
Mode
Comparator mode
Double speed Single mode
n-channel single-shot scan/
continuous scan mode
Comparator mode
Normal speed Single mode
n-channel single-shot scan/
continuous scan mode
Fast
Mode
Comparator mode
Double speed Single mode
n-channel single-shot scan/
continuous scan mode
Comparator mode
Note 1: For single mode and comparator mode, this indicates an A-D conversion or comparate time per channel. For singleshot and continuous scan modes, this indicates an A-D conversion time per scan loop.
Note 2: This indicates a time from when a register write cycle has finished to when an A-D conversion completion interrupt
request is generated, or a time from when an event bus or other MJT event has occurred to when an A-D conversion
completion interrupt request is generated.
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11.3 Functional Description of A-D Converter
11.3.5 Accuracy of A-D Conversion
The accuracy of the A-D Converter is indicated by an absolute accuracy. The absolute accuracy refers to a
difference expressed by LSB between the output code obtained by A-D converting the analog input voltages and
the output code expected for an A-D converter with ideal characteristics. The analog input voltages used during
accuracy measurement are the midpoint values of the voltage width in which an A-D converter with ideal characteristics produces the same output code. If VREF = 5.12 V, for example, the width of 1 LSB for a 10-bit A-D
converter is 5 mV, so that 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV and so on are selected as midpoints of the
analog input voltage.
If an A-D converter is said to have the absolute accuracy of ±2 LSB, it means that if the input voltage is 25 mV,
for example, the output code expected for an A-D converter with ideal characteristics is H’005, and the actual AD conversion result is in the range of H’003 to H’007. Note that the absolute accuracy includes zero and fullscale errors.
→ A-D conversion result (hexadecimal)
When actually using the A-D Converter, the analog input voltages are in the range of AVSS to VREF. Note,
however, that low VREF voltages result in a poor resolution. Note also that output codes for the analog input
voltages from VREF to AVCC are always H’3FF.
H'3FF
H'3FE
Ideal A-D conversion characteristics
H'003
H'002
A-D conversion characteristics with infinite resolution
H'001
H'000
0
VREF
×1
1024
VREF
×2
1024
VREF
×3
1024
VREF
× 1022
1024
VREF
× 1023
1024
VREF
× 1024
1024
→ Analog input voltage [V]
Figure 11.3.6 Ideal A-D Conversion Characteristics Relative to the 10-bit A-D Converter’s Analog Input Voltages
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A-D Converter
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→ Output code (hexadecimal)
11.3 Functional Description of A-D Converter
H'00B
Ideal A-D conversion characteristics
H'00A
H'009
H'008
+2 LSB
H'007
H'006
A-D conversion characteristics
with infinite resolution
H'005
H'004
H'003
-2 LSB
H'002
H'001
H'000
0
5
10
15
20
25
30
35
40
45
50
55
→ Analog input voltage [mV]
Figure 11.3.7 Absolute Accuracy of A-D Converter
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11.4 Inflow Current Bypass Circuit
11.4 Inflow Current Bypass Circuit
If when the A-D Converter is A-D converting a selected analog input an overvoltage exceeding the converter’s
absolute maximum rating is applied to any unselected analog input, the selector for the unselected analog input is
inadvertently turned on by that overvoltage. This causes current to leak to the selected analog input, and the
accuracy of the A-D conversion result is thereby deteriorated.
The Inflow Current Bypass Circuit fixes the internal signals of unselected analog inputs to the GND level, so that
when an overvoltage is applied, this circuit lets the current flow into the GND and prevents it from leaking to the
selected analog input. That way, the accuracy of the A-D conversion result is prevented from being deteriorated by
extreme voltages.
This circuit is always active while the A-D Converter is operating, and does not need to be controlled in software.
OFF
OFF
Fixed to GND level
Unselected
channel
ON
To the internal logic
of the A-D Converter
ON
ON
External input
latched into
Selected
channel
OFF
Assist circuit
Figure 11.4.1 Configuration of the Inflow Current Bypass Circuit
VCCE + 0.7 V or more
Leakage current
generated
Unselected channel
OFF
Leakage current
generated
OFF
ON
Unaffected
by leakage
Sensor input
Selected channel
ON
To the internal logic
of the A-D Converter
ON
OFF
Assist circuit
Figure 11.4.2 Example of an Inflow Current Bypass Circuit where VCCE + 0.7 V or More is Applied
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11.4 Inflow Current Bypass Circuit
Leakage current
generated
Unselected channel
OFF
OFF
Leakage current
generated
ON
Unaffected by
leakage
GND - 0.7V or less
Sensor input
ON
Selected channel
To the internal logic
of the A-D Converter
ON
OFF
Assist circuit
Figure 11.4.3 Example of an Inflow Current Bypass Circuit where GND – 0.7 V or Less is Applied
Table 11.4.1 Accuracy Errors (Actual Performance Values) when Current is Injected into AD0IN0
Accuracy error on overcurrent injected ports (Unit: LSB)
Analog input pin
AD0IN0
Injection
10mA
current
(Note 1)
9mA
AD0IN1
AD0IN2
AD0IN3
AD0IN4
AD0IN5
AD0IN6
AD0IN7
AD0IN8
AD0IN9
AD0IN10
AD0IN11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8mA
0
0
0
0
0
0
0
0
0
0
0
7mA
0
0
0
0
0
0
0
0
0
0
0
6mA
0
0
0
0
0
0
0
0
0
0
0
5mA
0
0
0
0
0
0
0
0
0
0
0
4mA
0
0
0
0
0
0
0
0
0
0
0
3mA
0
0
0
0
0
0
0
0
0
0
0
2mA
0
0
0
0
0
0
0
0
0
0
0
1mA
0
0
0
0
0
0
0
0
0
0
0
0mA
0
0
0
0
0
0
0
0
0
0
0
-1mA
0
0
0
0
0
0
0
0
0
0
0
-2mA
-1
0
0
0
0
0
0
0
0
0
0
-3mA
-1
0
0
0
0
0
0
0
0
0
0
-4mA
-1
0
0
0
0
0
0
0
0
0
0
-5mA
-2
-1
0
0
0
0
0
0
0
0
0
-6mA
-3
-1
0
0
0
0
0
0
0
0
0
-7mA
-3
-1
0
0
0
0
0
0
0
0
0
-8mA
-3
-1
0
0
0
0
0
0
0
0
0
-9mA
-4
-1
0
0
0
0
0
0
0
0
0
-10mA
-5
-1
0
0
0
0
0
0
0
0
0
Note 1: The conversion accuracy is not affected unless the injection current is greater than 1 mA.
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11.5 Precautions on Using A-D Converter
11.5 Precautions on Using A-D Converter
• Forcible termination during scan operation
If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP) to "1" during scan
mode operation and the A-D data register for the channel that was in the middle of conversion is accessed for
read, the read value shows the last conversion result that had been transferred to the data register before the
conversion was forcibly terminated.
• Modification of the A-D converter related registers
If the content of any register—A-D Conversion Interrupt Control Register, Single or Scan Mode Registers or A-D
Successive Approximation Register, except the A-D conversion stop bit—is modified in the middle of A-D conversion, the conversion result cannot be guaranteed. Therefore, do not modify the contents of these registers while AD conversion is in progress, or be sure to restart A-D conversion if register contents have been modified.
• Handling of analog input signals
When using the A-D Converter with its sample-and-hold function disabled, make sure the analog input level is
fixed during A-D conversion.
• A-D conversion completed bit read timing
To read the A-D conversion completed bit (Single Mode Register 0 bit 5 or Scan Mode Register 0 bit 5) immediately after A-D
conversion has started, be sure to adjust the timing 2 BCLK periods by, for example, inserting a NOP instruction before read.
• Regarding the analog input pins
Figure 11.5.1 shows the internal equivalent circuit of the A-D Converter’s analog input part. To obtain accurate
A-D conversion results, make sure the internal capacitor C2 of the A-D conversion circuit is charged up within a
predetermined time (sampling time). To meet this sampling time requirement, it is recommended that a stabilizing capacitor C1 be connected external to the chip.
The method for determining the necessary value of this external stabilizing capacitor with respect to the output
impedance of an analog output device is described below. Also, an explanation is made of the case where the
output impedance of an analog output device is low and the external stabilizing capacitor C1 is unnecessary.
• Rated value of the absolute accuracy
The rated value of the absolute accuracy is the actual performance value of the microcomputer alone, with
influences of the power supply wiring and noise on the board not taken into account. When designing the
application system, use caution for the board layout by, for example, separating the analog circuit power supply
and ground (AVCC, AVSS and VREF) from those of the digital circuit and incorporating measures to prevent the
analog input pins from being affected by noise, etc. from other digital signals.
Inside the microcomputer
10-bit A-D Successive
Approximation Register (ADiSAR)
VREF
10-bit D-A Converter
V2
Analog output device
ADIN n
R1
E
i→
i1
↓
i2→
C2
Cin
R2
Comparator
Selector
C1
C1 : parasitic capacitance of the board
R2 : parasitic resistance of the
+ stabilizing capacitance
selector (1-2 KΩ)
R1 : resistance of analog output device
C2 : comparator capacitance
(approx. 2.9 pF)
Cin : input pin capacitance (approx. 10 pF)
VREF : analog reference voltage
V2 : voltage across C2
E : voltage of analog output device
Figure 11.5.1 Internal Equivalent Circuit of the Analog Input Part
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11.5 Precautions on Using A-D Converter
(a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended)
Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal
capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2
is to be within 0.1 LSB, then what amount of capacitance C1 should have. For a 10-bit A-D Converter where
VREF is 5.12 V, 1 LSB determination voltage = 5.12 V / 1,024 = 5 mV. The potential fluctuation of 0.1 LSB
means a 0.5 mV fluctuation.
The relationship between the capacitance division of C1 and C2 and the potential fluctuation,
Vp, is obtained by the equation below:
C2
Eq. A-1
Vp =
× (E - V2)
C1 + C2
Vp is also obtained by the equation below:
x-1 1
VREF
∑
Vp = Vp1 ×
<
i
2
10
× 2×
i=0
Eq. A-2
where Vp1 = potential fluctuation in the first A-D conversion performed
and x = 10 for a 10-bit resolution A-D converter
When Eq. A-1 and Eq. A-2 are solved, the following results:
E - V2 - 1 }
C1 = C2 {
Vp1
x-1
∴ C1 > C2 {10 × 2× × ∑ 21 i - 1 }
i=0
Eq. A-3
Eq. A-4
Thus, for a 10-bit resolution A-D Converter where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for
reference when setting up C1.
(b) Maximum value of the output impedance R1 when C1 is not added
If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the analog input
device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Figure 11.5.1
does not exist is shown below.
i2 =
C2(E - V2)
Cin×R1+C2(R1+R2)
When sample-and-hold
is disabled
×exp
{
-t
}
------------------------ Eq. B-1
Cin×R1+C2(R1+R2)
Conversion time
for the first bit
Second bit
ADINi
Sampling time
Comparison Sampling time
time
Repeated (10 times) for 10 bits
* When sample-and-hold is enabled, the analog input is sampled for only the first bit.
Figure 11.5.2 A-D Conversion Timing Diagram
Figure 11.5.2 shows an A-D conversion timing diagram. C2 must be charged up within the sampling time
shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the second and
subsequent bits is about half that of the first bit.
The sampling times at the respective conversion speeds are listed in the table 11.5.1. Note that when the
sample-and-hold function is enabled, the analog input is sampled for only the first bit.
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11.5 Precautions on Using A-D Converter
Table 11.5.1 Sampling Time (in Which C2 Needs to Be Charged)
Conversion start method
Conversion speed
Single mode
Slow mode
(when sample-and
-hold disabled)
Single mode
Fast mode
Slow mode
Comparator mode
13.5BCLK
Double speed
15.5BCLK
7.5BCLK
Normal speed
11.5BCLK
5.5BCLK
Double speed
7.5BCLK
3.5BCLK
Normal speed
27.5BCLK
–
Double speed
15.5BCLK
–
Normal speed
11.5BCLK
–
Double speed
7.5BCLK
–
Normal speed
27.5BCLK
–
Double speed
15.5BCLK
–
Normal speed
11.5BCLK
–
Double speed
7.5BCLK
–
Fast mode
Slow mode
Fast mode
Sampling time for the second and subsequent bits
27.5BCLK
(when sample-and
-hold enabled)
Sampling time for the first bit
Normal speed
Therefore, the time in which C2 needs to be charged is found from Eq. B-1, as follows:
Sampling time (in which C2 needs to be charged) > Cin × R1 + C2(R1 + R2) --- Eq. B2
Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that
for single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits
(C2 charging time) must be applied.
R1 <
C2 charging time - C2 × R2
Cin + C2
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A-D Converter
11
11.5 Precautions on Using A-D Converter
This page is blank for reasons of layout.
11-44
32182 Group User's Manual (Rev.1.0)
CHAPTER 12
SERIAL I/O
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Outline of Serial I/O
Serial I/O Related Registers
Transmit Operation in CSIO Mode
Receive Operation in CSIO Mode
Precautions on Using CSIO Mode
Transmit Operation in UART Mode
Receive Operation in UART Mode
Fixed Period Clock Output Function
Precautions on Using UART Mode
Serial I/O
12
12.1 Outline of Serial I/O
12.1 Outline of Serial I/O
The 32182 contains a total of four serial I/O channels, SIO0–SIO3. Channels SIO0 and SIO1 can be selected
between CSIO mode (clock-synchronous serial I/O) and UART mode (clock-asynchronous serial I/O). Channels
SIO2 and SIO3 are UART mode only.
• CSIO mode (clock-synchronous serial I/O)
Communication is performed synchronously with a transfer clock, using the same clock on both transmit and
receive sides. The transfer data is 8 bits long (fixed).
• UART mode (clock-asynchronous serial I/O)
Communication is performed at any transfer rate in any transfer data format. The transfer data length can be
selected from 7, 8 and 9 bits.
Channels SIO0–SIO3 each have a transmit DMA transfer and a receive DMA transfer request. These serial
I/Os, when combined with the internal DMA Controller (DMAC), allow serial communication to be performed
at high speed, as well as reduce the data communication load of the CPU.
Serial I/O is outlined below.
Table 12.1.1 Outline of Serial I/O
Item
Description
Number of channels
CSIO mode/UART mode : 2 channels (SIO0, SIO1)
UART only
Clock
: 2 channels (SIO2, SIO3)
During CSIO mode : Internal clock or external clock as selected (Note 1)
During UART mode : Internal clock only
Transfer mode
Transmit half-duplex, receive half-duplex, transmit/receive full-duplex
BRG count source
f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2)
(when internal clock selected)
f(BCLK): Peripheral clock operating frequency
Data format
CSIO mode : Data length = 8 bits (fixed)
Order of transfer = LSB first (fixed)
UART mode : Start bit = 1 bit
Character length = 7, 8 or 9 bits
Parity bit = Added (odd, even) or not added
Stop bit = 1 or 2 bits
Order of transfer = LSB first (fixed)
Baud rate
CSIO mode : 152 bits/sec to 2 Mbits/sec (when f(BCLK) = 20 MHz)
UART mode : 19 bits/sec to 156 Kbits/sec (when f(BCLK) = 20 MHz)
Error detection
CSIO mode : Overrun error only
UART mode : Overrun, parity and framing errors
(Occurrence of any of these errors is indicated by an error sum bit)
Fixed period clock output function
When using SIO0 and SIO1 as UART, this function outputs a divided-by-2 BRG clock
from the SCLK pin.
Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16.
Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations.
12-2
32182 Group User's Manual (Rev.1.0)
Serial I/O
12
12.1 Outline of Serial I/O
Table 12.1.2 Interrupt Generation Functions of Serial I/O
Serial I/O Interrupt Request Source
ICU Interrupt Sources
SIO0 transmit buffer empty or transmission finished
SIO0 transmit interrupt
SIO0 reception finished or receive error
SIO0 receive interrupt
SIO1 transmit buffer empty or transmission finished
SIO1 transmit interrupt
SIO1 reception finished or receive error
SIO1 receive interrupt
SIO2 transmit buffer empty or transmission finished
SIO2,3 transmit/receive interrupt (group interrupt)
SIO2 reception finished or receive error
SIO2,3 transmit/receive interrupt (group interrupt)
SIO3 transmit buffer empty or transmission finished
SIO2,3 transmit/receive interrupt (group interrupt)
SIO3 reception finished or receive error
SIO2,3 transmit/receive interrupt (group interrupt)
Note: • The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode.
Table 12.1.3 DMA Transfer Request Generation Functions of Serial I/O
Serial I/O DMA Transfer Request
DMAC Input Channels
SIO0 transmit buffer empty
DMA3, DMA4
SIO0 reception finished
DMA4
SIO1 transmit buffer empty
DMA6
SIO1 reception finished
DMA3, DMA6
SIO2 transmit buffer empty
DMA7
SIO2 reception finished
DMA5
SIO3 transmit buffer empty
DMA7, DMA9
SIO3 reception finished
DMA8
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32182 Group User's Manual (Rev.1.0)
Serial I/O
12
12.1 Outline of Serial I/O
SIO0
SIO0 Transmit Buffer Register
Transmit interrupt request
TXD0
SIO0 Transmit Shift Register
RXD0
SIO0 Receive Shift Register
To the Interrupt
Controller (ICU)
Receive interrupt request
Transmit/
Receive
Control
Circuit
Transmit DMA transfer request
To DMA3, DMA4
Receive DMA transfer request
To DMA4
SIO0 Receive Buffer Register
UART
mode
CSIO
mode
When external clock selected
When internal clock selected
BCLK
1/16
1
(set value + 1)
Clock
Divider
Baud Rate
Generator
(BRG)
CSIO mode
When internal clock selected
When UART mode selected
SIO1
TXD1
RXD1
SIO1 Transmit Shift Register
SIO1 Receive Shift Register
SCLKI0/SCLKO0
1/2
Transmit/
Receive
Control
Circuit
Internal data bus
BCLK,
BCLK/8,
BCLK/32,
BCLK/256
Transmit interrupt request
Receive interrupt request
Transmit DMA transfer request
Receive DMA transfer request
To the Interrupt
Controller (ICU)
To DMA6
To DMA3, DMA6
SCLKI1/SCLKO1
SIO2
TXD2
RXD2
SIO2 Transmit Shift Register
SIO2 Receive Shift Register
Transmit interrupt request
Transmit/
Receive
Control
Circuit
Receive interrupt request
Transmit DMA transfer request
Receive DMA transfer request
To DMA7
To DMA5
SIO3
TXD3
SIO3 Transmit Shift Register
RXD3
SIO3 Receive Shift Register
Transmit/
Receive
Control
Circuit
Transmit interrupt request
Receive interrupt request
Transmit DMA transfer request
Receive DMA transfer request
To the Interrupt
Controller (ICU)
To DMA7, DMA9
To DMA8
Notes: • When BCLK is selected, the BRG set value is subject to limitations.
• SIO2 and SIO3 do not have the SCLKI/SCLKO function.
Figure 12.1.1 Block Diagram of SIO0–SIO3
12-4
32182 Group User's Manual (Rev.1.0)
Serial I/O
12
12.2 Serial I/O Related Registers
12.2 Serial I/O Related Registers
Shown below is a serial I/O related register map.
Serial I/O Related Register Map
Address
+0 address
b0
H'0080 0100
H'0080 0102
|
H'0080 0110
H'0080 0112
H'0080 0114
H'0080 0116
|
H'0080 0120
H'0080 0122
H'0080 0124
H'0080 0126
|
H'0080 0130
H'0080 0132
H'0080 0134
H'0080 0136
|
H'0080 0140
H'0080 0142
H'0080 0144
H'0080 0146
+1 address
b7 b8
b15
SIO23 Interrupt Request Status Register
SIO03 Interrupt Request Enable Register
(SI23STAT)
(SI03EN)
SIO03 Interrupt Source Select Register
(Use inhibited area)
(SI03SEL)
(Use inhibited area)
See
pages
12-9
12-10
12-11
SIO0 Transmit Control Register
SIO0 Transmit/Receive Mode Register
(S0TCNT)
(S0MOD)
SIO0 Transmit Buffer Register
(S0TXB)
SIO0 Receive Buffer Register
(S0RXB)
SIO0 Receive Control Register
SIO0 Baud Rate Register
(S0RCNT)
(S0BAUR)
(Use inhibited area)
12-13
12-14
12-17
SIO1 Transmit Control Register
SIO1 Transmit/Receive Mode Register
(S1TCNT)
(S1MOD)
SIO1 Transmit Buffer Register
(S1TXB)
SIO1 Receive Buffer Register
(S1RXB)
SIO1 Receive Control Register
SIO1 Baud Rate Register
(S1RCNT)
(S1BAUR)
(Use inhibited area)
12-13
12-14
12-17
SIO2Transmit Control Register
SIO2 Transmit/Receive Mode Register
(S2TCNT)
(S2MOD)
SIO2 Transmit Buffer Register
(S2TXB)
SIO2 Receive Buffer Register
(S2RXB)
SIO2 Receive Control Register
SIO2 Baud Rate Register
(S2RCNT)
(S2BAUR)
(Use inhibited area)
12-13
12-14
12-17
SIO3 Transmit Control Register
SIO3 Transmit/Receive Mode Register
(S3TCNT)
(S3MOD)
SIO3 Transmit Buffer Register
(S3TXB)
SIO3 Receive Buffer Register
(S3RXB)
SIO3 Receive Control Register
SIO3 Baud Rate Register
(S3RCNT)
(S3BAUR)
12-13
12-14
12-17
12-5
12-18
12-19
12-22
12-18
12-19
12-22
12-18
12-19
12-22
12-18
12-19
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32182 Group User's Manual (Rev.1.0)
Serial I/O
12
12.2 Serial I/O Related Registers
12.2.1 SIO Interrupt Related Registers
The SIO interrupt related registers are used to control the interrupt request signals output from SIO to the
Interrupt Controller (ICU), as well as select the source of each interrupt request.
(1) Interrupt request status bit
This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this
bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no
effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request
enable bit, it can also be used to inspect the operating status of peripheral functions.
In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the
interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been
serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit.
(2) Interrupt request enable bit
This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to
"1" to enable interrupt requests or "0" to disable interrupt requests.
• Group interrupt
Interrupt request from
each peripheral function
Set
Data bus
Data=0
clear
Interrupt request status
F/F
F/F
To the Interrupt Controller
Interrupt request enable
Figure 12.2.1 Interrupt Request Status and Enable Registers
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Serial I/O
12
12.2 Serial I/O Related Registers
Example for clearing interrupt request status
Interrupt request status
Initial state
b4
5
6
b7
0
0
0
0
Interrupt request
Bit 6 event occurs
0
0
1
0
Bit 4 event occurs
1
0
1
0
1
0
0
0
Write to the interrupt request status
b4
5
6
b7
1
1
0
1
Only bit 6 cleared
Bit 4 data retained
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1: ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
Bit 6 event occurs
b4
5
6
b7
0
0
1
0
Read
0
Bit 4 event occurs
1
0
1
0
0
1
0
0
Clear bit 6 (ANDing with 1101)
0
0
0
0
0
0
0
Write
Only bit 6 cleared
Bit 4 also cleared
Figure 12.2.2 Example for Clearing Interrupt Request Status
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Serial I/O
12
12.2 Serial I/O Related Registers
(3) Selecting the source of an interrupt request
The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are classified into transmit
interrupts and receive interrupts. Transmit interrupt requests can be generated when the transmit buffer is
empty or transmission is finished, and the receive interrupt requests can be generated when reception is
finished or an receive error is detected, as selected by the Interrupt Source Select Register (SI03SEL).
Notes: • No interrupt request signals are generated unless interrupts are generated by the SIO Interrupt
Request Enable Register after enabling the TEN (Transmit Enable) bit or REN (Receive Enable) bit
for the corresponding SIO.
• SIO2 and SIO3 together comprise one interrupt group.
• The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode.
(4) Notes on using transmit interrupts
While the SIO Interrupt Request Enable Register is set to enable interrupts, a transmit interrupt request is
generated upon enabling the corresponding TEN (Transmit Enable) bit.
(5) About DMA transfer requests from SIO
Each SIO can generate a transmit DMA transfer and a reception-finished DMA transfer request. These DMA
transfer requests can be generated by enabling each SIO’s corresponding TEN (Transmit Enable) bit or REN
(Receive Enable) bit. When using DMA transfers to communicate with external devices, be sure to set the
DMA Controller (DMAC) before enabling the TEN or REN bit. No reception-finished DMA transfer requests
are generated if a receive error occurs.
• Transmit DMA transfer request
Generated when the transmit buffer is empty and the TEN bit is enabled.
TEN
(Transmit Enable bit)
TBE
(Transmit Buffer
Empty bit)
Transmit DMA
transfer request
Figure 12.2.3 Transmit DMA Transfer Request
• Reception-finished DMA transfer request
A DMA transfer request is generated when the receive buffer is filled.
RFIN
(Reception Finished bit)
Receive
DMA transfer request
Note: • No reception-finished DMA transfer requests are generated if a receive error occurs.
Figure 12.2.4 Reception-finished DMA Transfer Request
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32182 Group User's Manual (Rev.1.0)
Serial I/O
12
12.2 Serial I/O Related Registers
SIO23 Interrupt Request Status Register (SI23STAT)
b0
0
1
0
2
0
3
0
4
5
6
b7
IRQT2
IRQR2
IRQT3
IRQR3
0
0
0
0
<Address: H’0080 0100>
<After reset: H’00>
b
Bit Name
0–3
No function assigned. Fix to "0".
4
IRQT2
SIO2 transmit interrupt request status bit
0: Interrupt not requested
1: Interrupt requested
R (Note 1)
5
IRQR2
SIO2 receive interrupt request status bit
0: Interrupt not requested
1: Interrupt requested
R (Note 1)
6
IRQT3
0: Interrupt not requested
R (Note 1)
SIO3 transmit interrupt request status bit
1: Interrupt requested
IRQR3
SIO3 receive interrupt request status bit
0: Interrupt not requested
1: Interrupt requested
7
Function
R
W
0
0
R (Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
The register indicates the transmit/receive interrupt requests from each SIO.
[Setting the interrupt request status bit]
This bit can only be set in hardware, and cannot be set in software.
[Clearing the interrupt request status bit]
This bit is cleared by writing "0" in software.
Note: • If the status bit is set in hardware at the same time it is cleared in software, the former has
priority and the status bit is set.
When writing to the SIO Interrupt Request Status Register, make sure only the bits to be cleared are set to "0"
and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and
retain the value they had before the write.
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Serial I/O
12
12.2 Serial I/O Related Registers
SIO03 Interrupt Request Enable Register (SI03EN)
b8
9
10
11
12
13
14
b15
T0EN
R0EN
T1EN
R1EN
T2EN
R2EN
T3EN
R3EN
0
0
0
0
0
0
0
0
<Address: H’0080 0101>
<After reset: H’00>
b
Bit Name
Function
R
W
8
T0EN
SIO0 transmit interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
9
R0EN
SIO0 receive interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
10
T1EN
SIO1 transmit interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
11
R1EN
0: Mask (disable) interrupt request
R
W
SIO1 receive interrupt request enable bit
1: Enable interrupt request
12
T2EN
SIO2 transmit interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
13
R2EN
SIO2 receive interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
14
T3EN
SIO3 transmit interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
15
R3EN
SIO3 receive interrupt request enable bit
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
These registers enable or disable the interrupt requests generated by each SIO. Interrupt requests from any SIO
are enabled by setting its corresponding interrupt request enable bit to "1".
12-10
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Serial I/O
12
12.2 Serial I/O Related Registers
SIO03 Interrupt Request Source Select Register (SI03SEL)
b0
1
2
3
4
5
6
b7
IST0
IST1
IST2
IST3
ISR0
ISR1
ISR2
ISR3
0
0
0
0
0
0
0
0
<Address: H’0080 0102>
<After reset: H’00>
b
Bit Name
Function
R
W
0
IST0
SIO0 transmit interrupt request source select bit
0: Transmit buffer empty interrupt
1: Transmission finished interrupt
R
W
1
IST1
SIO1 transmit interrupt request source select bit
0: Transmit buffer empty interrupt
1: Transmission finished interrupt
R
W
2
IST2
SIO2 transmit interrupt request source select bit
0: Transmit buffer empty interrupt
1: Transmission finished interrupt
R
W
3
IST3
0: Transmit buffer empty interrupt
R
W
SIO3 transmit interrupt request source select bit
1: Transmission finished interrupt
4
ISR0
SIO0 receive interrupt request source select bit
0: Reception finished interrupt
1: Receive error interrupt
R
W
5
ISR1
SIO1 receive interrupt request source select bit
0: Reception finished interrupt
1: Receive error interrupt
R
W
6
ISR2
SIO2 receive interrupt request source select bit
0: Reception finished interrupt
1: Receive error interrupt
R
W
7
ISR3
SIO3 receive interrupt request source select bit
0: Reception finished interrupt
1: Receive error interrupt
R
W
These registers select the source of interrupt requests generated by each SIO when transmit or receive operation is completed.
(1) SIOn transmit interrupt request source select bit
[When set to "0"]
The transmit buffer empty interrupt is selected. A transmit buffer empty interrupt request is generated
when data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit
buffer empty interrupt request is generated when the TEN (Transmit Enable) bit is set to "1" (interrupt
enabled).
[When set to "1"]
The transmission finished (transmit shift buffer empty) interrupt is selected. A transmission finished
interrupt request is generated when all of the data in the transmit shift register has been transferred.
Note: • Do not select the transmission finished interrupt when an external clock is selected in CSIO
mode.
(2) SIOn receive interrupt request source select bit
[When set to "0"]
The reception finished (receive buffer full) interrupt is selected. A reception finished interrupt request is
also generated when a receive error (except overrun error) occurs.
[When set to "1"]
The receive error interrupt is selected. Following types of errors constitute a receive error:
• CSIO mode: Overrun error
• UART mode: Overrun, parity and framing errors
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Serial I/O
12
12.2 Serial I/O Related Registers
<SI03SEL : H'0080 0102>
<SI23STAT : H'0080 0100>
<SI03EN : H'0080 0101>
Data bus
SIO2 transmit
buffer empty
SIO2 transmission
finished
IST2
b2
F/F
b4
IRQT2
F/F
b12
T2EN
F/F
b5
IRQR2
F/F
b13
R2EN
F/F
b6
IRQT3
F/F
b14
T3EN
F/F
b7
IRQR3
F/F
b15
R3EN
F/F
SIO2 reception
finished
4-source inputs
(Level)
SIO2, 3
transmit/receive
interrupt requests
SIO2 receive error
ISR2
b6
F/F
SIO3 transmit
buffer empty
SIO3 transmission
finished
IST3
b3
F/F
SIO3 reception
finished
SIO3 receive error
ISR3
b7
F/F
Figure 12.2.5 Block Diagram of SIO2,3 Transmit Interrupt Requests
12-12
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Serial I/O
12
12.2 Serial I/O Related Registers
12.2.2 SIO Transmit Control Registers
SIO0
SIO1
SIO2
SIO3
b0
Transmit
Transmit
Transmit
Transmit
1
Control
Control
Control
Control
2
Register
Register
Register
Register
3
(S0TCNT)
(S1TCNT)
(S2TCNT)
(S3TCNT)
4
CDIV
0
0
0
1
0
<Address:
<Address:
<Address:
<Address:
5
6
b7
TSTAT
TBE
TEN
0
1
0
H'0080
H'0080
H'0080
H'0080
0110>
0120>
0130>
0140>
<After reset: H’12>
b
Bit Name
0, 1
No function assigned. Fix to "0".
2, 3
CDIV
BRG count source select bit
Function
R
0
0
b2
0
0
1
1
R
W
0
0
0:Transmission stopped and no data in transmit buffer register
1:Transmitting now or data present in transmit buffer register
R
–
R
–
R
W
b3
0: Select
1: Select
0: Select
1: Select
f(BCLK)
f(BCLK) divided by 8
f(BCLK) divided by 32
f(BCLK) divided by 256
4
No function assigned. Fix to "0".
5
TSTAT
Transmit status bit
6
TBE
0:Data present in transmit buffer register
Transmit buffer empty bit
1: No data in transmit buffer register
TEN
Transmit enable bit
0: Disable transmission
1: Enable transmission
7
W
(1) CDIV (baud rate generator count source select) bits (Bits 2–3)
These bits select the count source for the Baud Rate Generator (BRG).
Note: • If f(BCLK) is selected as the count source for the BRG, care must be taken when setting the
BRG so that the baud rate will not exceed the maximum transfer speed. For details, see the
section in which the BRG register is explained.
(2) TSTAT (Transmit Status) bit (Bit 5)
[Set condition]
This bit is set to "1" by a write to the transmit buffer register while transmission is enabled.
[Clear condition]
This bit is cleared to "0" when transmission is idle (no data in the transmit shift register) and no data
exists in the transmit buffer register. This bit is also cleared by clearing the transmit enable bit.
(3) TBE (Transmit Buffer Empty) bit (Bit 6)
[Set condition]
This bit is set to "1" when data is transferred from the transmit buffer register to the transmit shift register
and the transmit buffer register is thereby emptied. This bit is also set by clearing the transmit enable bit
to "0".
[Clear condition]
This bit is cleared to "0" by writing data to the lower byte of the transmit buffer register while transmission
is enabled (TEN = "1").
(4) TEN (Transmit Enable) bit (Bit 7)
Transmission is enabled by setting this bit to "1" and disabled by clearing this bit to "0". If this bit is cleared to
"0" while transmitting data, the transmit operation stops.
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Serial I/O
12
12.2 Serial I/O Related Registers
12.2.3 SIO Transmit/Receive Mode Registers
SIO0
SIO1
SIO2
SIO3
b8
Transmit/Receive
Transmit/Receive
Transmit/Receive
Transmit/Receive
9
10
SMOD
0
0
0
Mode
Mode
Mode
Mode
Register
Register
Register
Register
(S0MOD)
(S1MOD)
(S2MOD)
(S3MOD)
<Address:
<Address:
<Address:
<Address:
11
12
13
14
b15
CKS
STB
PSEL
PEN
SEN
0
0
0
0
0
H'0080
H'0080
H'0080
H'0080
0111>
0121>
0131>
0141>
<After reset: H’00>
b
Bit Name
Function
R
W
8–10
SMOD
Serial I/O mode select bit
(Note 1)
b8 b9 b10
0
0 0 : 7-bit UART
0
0 1 : 8-bit UART
0
1 X : 9-bit UART
1
X X : 8-bit clock-synchronous serial I/O
R
W
11
CKS
Internal/external clock select bit
0: Internal clock
1: External clock
R W
(Note 2)
12
STB
Stop bit length select bit, UART mode only
0: One stop bit
1: Two stop bits
R W
(Note 3)
13
PSEL
Odd/even parity select bit, UART mode only
0: Odd parity
1: Even parity
R W
(Note 3)
R
14
15
PEN
0: Disable parity
Parity enable bit, UART mode only
1: Enable parity
SEN
Sleep select bit, UART mode only
0: Disable sleep function
1: Enable sleep function
W
(Note 3)
R W
(Note 3)
Note 1: For SIO2 and 3, bit 8 is fixed to "0" in hardware. This bit cannot be set to "1" in software (to select clock-synchronous serial I/O).
Note 2: Has no effect when UART mode selected.
Note 3: Bits 12–15 have no effect during clock-synchronous mode.
The SIO Mode Registers consist of bits to set the serial I/O operation mode, data format and the functions used
during communication.
The SIO Transmit/Receive Mode Registers must always be set before the serial I/O starts operating. To change
register settings before the serial I/O starts sending or receiving data, first confirm that transmit and receive
operations have finished and then disable transmit/receive operations (by clearing the SIO Transmit Control
Register transmit enable bit and SIO Receive Control Register receive enable bit to "0") before making changes.
(1) SMOD (Serial I/O Mode Select) bits (Bits 8–10)
These bits select the operation mode of serial I/O.
(2) CKS (Internal/External Clock Select) bit (Bit 11)
This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode is selected,
in which case the serial I/O is clocked by the internal clock.
(3) STB (Stop Bit Length Select) bit (Bit 12)
This bit is effective during UART mode. Use this bit to select the stop bit length that indicates the end of data
to transmit. Setting this bit to "0" selects one stop bit, and setting this bit to "1" selects two stop bits.
During clock-synchronous mode, the content of this bit has no effect.
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12.2 Serial I/O Related Registers
(4) PSEL (Odd/Even Parity Select) bit (Bit 13)
This bit is effective during UART mode. When parity is enabled (bit 14 = "1"), use this bit to select the parity
attribute (whether odd or even). Setting this bit to "0" selects an odd parity, and setting this bit to "1" selects
an even parity.
When parity is disabled (bit 14 = "0") and during clock-synchronous mode, the content of this bit has no effect.
(5) PEN (Parity Enable) bit (Bit 14)
This bit is effective during UART mode. When this bit is set to "1", a parity bit is added immediately after the
data bits of the transmit data, and the received data is checked for parity.
The parity bit added to the transmit data is automatically determined to be "0" or "1" so that the attribute (odd/
even) derived by adding the number of 1’s in data bits and the content of the parity bit agrees with one that
was selected with the odd/even parity select bit (bit 13).
Figure 12.2.6 shows an example of a data format when parity is enabled.
(6) SEN (Sleep Select) bit (Bit 15)
This bit is effective during UART mode. If the sleep function is enabled by setting this bit to "1", data is latched
into the UART Receive Buffer Register only when the most significant bit (MSB) of the received data is "1".
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12.2 Serial I/O Related Registers
ST : Start bit
b : Data bits
PAR : Parity bit
SP : Stop bit
: One frame equivalent
Direction of transfer
• Clock-synchronous mode
b7
b6
b5
b4
b3
b2
b1
b0
(Note 1) (Note 2)
•
7-bit UART mode
ST
b6
b5
b4
b3
b2
b1
b0
PAR
•
8-bit UART mode
ST
b7
b6
b5
b4
b3
b2
b1
b0
PAR
•
9-bit UART mode
ST
b8
b7
b6
b5
b4
b3
b2
b1
b0
SP
(Note 1) (Note 2)
SP
(Note 1) (Note 2)
PAR
SP
Note 1: Whether or not to add a parity bit is selectable.
Note 2: The stop bit can be chosen to be one bit or two bits long.
• When transmitting
• When receiving
If the attribute (odd/even) represented by the
number of 1's in data bits agrees with the selected
parity attribute, a parity bit "0" is added. If the
attribute (odd/even) represented by the number of 1's
in data bits does not agree with the selected parity
attribute, a parity bit "1" is added.
LSB
ST
b7
The received data is checked to see if the number of
1's included in its data and parity bits agrees with
the parity attribute (known as parity check).
b5
b4
b3
b2
b1
b0
MSB
LSB
MSB
b6
ST
PAR SP
Attribute derived from b7 + b6 + ... + b0
b7
b6
b5
b4
b3
b2
b1
b0
PAR SP
If the result of b7 + b6 + ... + b0 + PAR does not agree
with the selected parity attribute, a parity error is assumed
If it agrees with the selected
parity attribute, PAR = "0" is added.
If it does not agree with the selected
parity attribute, PAR = "1" is added.
Notes : • Shown above is an example of a data format in 8-bit UART mode.
• The data bit numbers (bn) above indicate bit numbers in a data list, and not the register bit numbers (bn).
Figure 12.2.6 Data Format When Parity is Enabled
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12.2 Serial I/O Related Registers
12.2.4 SIO Transmit Buffer Registers
SIO0
SIO1
SIO2
SIO3
Transmit
Transmit
Transmit
Transmit
b0
Buffer
Buffer
Buffer
Buffer
1
2
Register
Register
Register
Register
3
(S0TXB)
(S1TXB)
(S2TXB)
(S3TXB)
4
<Address:
<Address:
<Address:
<Address:
5
6
7
8
9
10
11
H'0080
H'0080
H'0080
H'0080
12
13
14
?
?
?
0112>
0122>
0132>
0142>
b15
TDATA
?
?
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–6
No function assigned. Fix to "0".
7–15
TDATA
Transmit data
Function
Transmit data is set in these bits.
R
W
?
0
?
W
The SIO Transmit Buffer Registers are used to set transmit data. These registers are a write-only register, and
the contents of these registers cannot be read out. Data must be LSB-aligned when set in these registers.
Therefore, write transmit data to bits 9–15 for the 7-bit data format (UART mode only), bits 8–15 for the 8-bit data
format, or bits 7–15 for the 9-bit data format (UART mode only).
Before setting transmit data in these registers, enable the Transmit Control Register TEN (Transmit Enable) bit
by setting it to "1". Writing data to these registers while the TEN bit is disabled (cleared to "0") has no effect.
When data is written to the SIO Transmit Buffer Register while transmission is enabled, the data is transferred
from that register to the SIO Transmit Shift Register, upon which the serial I/O starts sending data.
Note: For the 7-bit and 8-bit data formats, the register can be accessed bytewise.
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12.2 Serial I/O Related Registers
12.2.5 SIO Receive Buffer Registers
SIO0
SIO1
SIO2
SIO3
Receive
Receive
Receive
Receive
b0
Buffer
Buffer
Buffer
Buffer
1
Register
Register
Register
Register
2
3
(S0RXB)
(S1RXB)
(S2RXB)
(S3RXB)
4
<Address:
<Address:
<Address:
<Address:
5
6
7
8
9
10
11
H'0080
H'0080
H'0080
H'0080
0114>
0124>
0134>
0144>
12
13
14
b15
?
?
?
?
RDATA
?
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–6
No function assigned.
8–15
RDATA
Received data
Function
Received data is stored in these bits.
R
W
0
–
R
–
The SIO Receive Buffer Registers are used to store the received data. When the serial I/O has finished receiving
data, the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register. These
registers are a read-only register.
For the 7-bit data format (UART mode only), data is set in bits 9–15, with bits 8 and 7 always set to "0". For the
8-bit data format, data is set in bits 8–15, with bit 7 always set to "0".
When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial I/O
finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subsequent received data are not transferred to the Receive Buffer Register.
To restart normal receive operation, clear the Receive Control Register REN (Receive Enable) bit to "0".
Note: For the 7-bit and 8-bit data formats, the register can be accessed bytewise.
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12.2 Serial I/O Related Registers
12.2.6 SIO Receive Control Registers
SIO0
SIO1
SIO2
SIO3
b0
0
Receive
Receive
Receive
Receive
Control
Control
Control
Control
Register
Register
Register
Register
(S0RCNT)
(S1RCNT)
(S2RCNT)
(S3RCNT)
<Address:
<Address:
<Address:
<Address:
1
2
3
4
5
6
b7
RSTAT
RFIN
REN
OVR
PTY
FLM
ERS
0
0
0
0
0
0
0
H'0080
H'0080
H'0080
H'0080
0116>
0126>
0136>
0146>
<After reset: H’00>
b
Bit Name
0
No function assigned. Fix to "0".
1
2
3
Function
R
W
0
0
RSTAT
Receive status bit
0: Reception stopped
1: Reception in progress
R
–
RFIN
Reception finished bit
0: No data in receive buffer register
1: Data present in receive buffer register
R
–
R
W
REN
0: Disable reception
Receive enable bit
1: Enable reception
4
OVR
Overrun error bit
0: No overrun error
1: Overrun error occurred
R
–
5
PTY
Parity error bit, UART mode only
0: No parity error
1: Parity error occurred
R
–
6
FLM
0: No framing error
R
–
Framing error bit, UART mode only
1: Framing error occurred
ERS
Error sum bit
0: No error
1: Error occurred
R
–
7
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12.2 Serial I/O Related Registers
(1) RSTAT (Receive Status) bit (Bit 1)
[Set condition]
This bit is set to "1" by a start of receive operation. When this bit = "1", the serial I/O is receiving data.
[Clear condition]
This bit is cleared to "0" upon completion of receive operation or by clearing the REN (Receive Enable) bit.
(2) RFIN (Reception Finished) bit (Bit 2)
[Set condition]
This bit is set to "1" when all data bits have been received in the Receive Shift Register and whose
content is transferred to the Receive Buffer Register.
[Clear condition]
This bit is cleared to "0" by reading out the lower byte of the Receive Buffer Register or by clearing the
REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out
the lower byte of the Receive Buffer Register. In this case, clear REN (Receive Enable) bit to "0".
(3) REN (Receive Enable) bit (Bit 3)
Reception is enabled by setting this bit to "1", and is disabled by clearing this bit to "0", in which case the
receiver unit is initialized. Accordingly, the receive status and reception finished flags, as well as the overrun
error, framing error, parity error and error sum flags all are cleared.
The receive operation stops if the Receive Enable bit is cleared to "0" while receiving data.
(4) OVR (Overrun Error) bit (Bit 4)
[Set condition]
This bit is set to "1" when all bits of the next received data have been set in the Receive Shift Register
while the Receive Buffer Register still contains the previous received data. In this case, the received
data is not stored in the Receive Buffer Register. Although receive operation continues even when the
overrun error flag = "1", the received data is not stored in the Receive Buffer Register. This error bit must
be cleared before normal reception can be restarted.
[Clear condition]
This bit is cleared to "0" by only clearing the REN (Receive Enable) bit.
(5) PTY (Parity Error) bit (Bit 5)
This bit is effective in only UART mode. It is fixed to "0" during CSIO mode.
[Set condition]
The PTY (Parity Error) bit is set to "1" when the SIO Transmit/Receive Mode Register PEN (Parity
Enable/Disable) bit is enabled and the parity (even or odd) of the received data does not agree with one
that was set by the said register’s PSEL (Parity Select) bit.
[Clear condition]
The PTY bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by
clearing the SIO Receive Control Register REN (Receive Enable) bit. However, if an overrun error
occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this
case, clear the REN (Receive Enable) bit.
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12.2 Serial I/O Related Registers
(6) FLM (Framing Error) bit (Bit 6)
This bit is effective in only UART mode. It is fixed to "0" during CSIO mode.
[Set condition]
The FLM (Framing Error) bit is set to "1" when the number of received bits does not agree with one that
was set by the SIO Transmit/Receive Mode Register.
[Clear condition]
The FLM bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by
clearing the SIO Receive Control Register REN (Receive Enable) bit.
However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the
Receive Buffer Register. In this case, clear the REN (Receive Enable) bit to "0".
(7) ERS (Error Sum) bit (Bit 7)
[Set condition]
This flag is set to "1" when any of overrun, framing or parity errors is detected at completion of reception.
[Clear condition]
If the detected error was an overrun error, this flag is cleared by clearing the REN (Receive Enable) bit
to "0". Otherwise, this flag is cleared by reading out the lower byte of the SIO Receive Buffer Register or
by clearing the SIO Receive Control Register REN (Receive Enable) bit.
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12.2 Serial I/O Related Registers
12.2.7 SIO Baud Rate Registers
SIO0
SIO1
SIO2
SIO3
Baud
Baud
Baud
Baud
b8
9
Rate
Rate
Rate
Rate
Register
Register
Register
Register
10
(S0BAUR)
(S1BAUR)
(S2BAUR)
(S3BAUR)
11
<Address:
<Address:
<Address:
<Address:
12
13
14
b15
?
?
?
?
H'0080
H'0080
H'0080
H'0080
0117>
0127>
0137>
0147>
BRG
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
8–15
BRG
Baud rate divide value
The baud rate count source selected by SIO Mode Register
is divided by (n + 1) where n = BRG set value.
R
W
(1) BRG (baud rate divide value) (Bits 8–15)
The SIO Baud Rate Registers are used to set a baud rate divide value, so that the baud rate count source
selected by SIO Mode Register is divided by (n + 1) where n = BRG set value.
Because the BRG value initially is undefined, be sure to set the divide value before the serial I/O starts
operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after
the BRG counter has finished counting.
When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial I/O divides the internal
BCLK using a clock divider and then divides the resulting clock by (n + 1) where n = BRG set value and
further by 2, thereby generating a transmit/receive shift clock.
When using an external clock in CSIO mode, the serial I/O does not use the BRG. (Transmit/receive operations are synchronized to the externally supplied clock.)
During UART mode, the serial I/O divides the internal BCLK using a clock divider and then divides the
resulting clock by (n + 1) where n = BRG set value and further by 16, thereby generating a transmit/receive
shift clock.
When using SIO0 or SIO1 in UART mode, set the relevant port (P84 or P87) to function as an SCLKO pin, so
that a BRG output clock divided by 2 can be output from that SCLKO pin.
When using the internal clock (internally clocked CSIO mode or UART mode), if f(BCLK) is selected as the
BRG count source, make sure the transfer rate does not exceed 2 Mbits/second during CSIO mode, and that
BRG is equal to or greater than 7 during UART mode.
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12.3 Transmit Operation in CSIO Mode
12.3 Transmit Operation in CSIO Mode
12.3.1 Setting the CSIO Baud Rate
The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock
source from which a transmit/receive shift clock derives is selected from the internal clock f(BCLK) or external
clock. The CKS (Internal/External Clock Select) bit (SIO Transmit/Receive Mode Register bit 11) is used to
select the clock source.
The equation used to calculate the transmit/receive baud rate differs depending on whether an internal or external clock is selected.
(1) When internal clock is selected in CSIO mode
When the internal clock is selected, f(BCLK) is divided by a clock divider before being supplied to the Baud
Rate Generator (BRG).
The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the CDIV (baud rate generator
count source select) bits (Transmit Control Register bits 2–3).
The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by
2, thus generating a transmit/receive shift clock.
When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below.
f(BCLK)
Baud rate =
Clock divider’s divide-by value x (baud rate register set value + 1) x 2
[bps]
Baud rate register set value = H’00 to H’FF (Note 1)
Clock divider’s divide-by value = 1, 8, 32 or 256
Note 1: If divide-by-1 (i.e., f(BCLK) itself) is selected as the baud rate generator count source, use
caution when setting the baud rate register so that the transfer rate will not exceed 2 Mbps.
(2) When external clock is selected in CSIO mode
In this case, the Baud Rate Generator is not used, and the input clock from the SCLKI pin serves directly as
a transmit/receive shift clock for CSIO.
The maximum frequency of the SCLKI pin input clock is f(BCLK)/16.
Baud rate = SCLKI pin input clock
[bps]
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12.3 Transmit Operation in CSIO Mode
12.3.2 Initializing CSIO Transmission
To transmit data in CSIO mode, initialize the serial I/O following the procedure described below.
(1) Setting SIO Transmit/Receive Mode Register
• Set the register to CSIO mode.
• Select the internal or an external clock.
(2) Setting SIO Transmit Control Register
• Select the clock divider’s divide-by ratio (when internal clock selected).
(3) Setting SIO Baud Rate Register
When the internal clock is selected, set a baud rate generator value. (See Section 12.3.1, “Setting the CSIO
Baud Rate.”)
(4) Setting the SIO interrupt related registers
• Select the source of transmit interrupt request (transmit buffer empty or transmission finished) (SIO Interrupt
Request Source Select Register).
• Enable or disable transmit interrupt requests (SIO Interrupt Request Enable Register).
Note: • Transmission finished interrupt requests are effective only when the internal clock is selected.
(5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register)
To use transmit interrupts, set their priority levels.
(6) Setting the DMAC
To issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set up the DMAC.
(See Chapter 9, “DMAC.”)
(7) Selecting pin functions
Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/
output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)
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12.3 Transmit Operation in CSIO Mode
Initialize CSIO transmission
• Set the register to CSIO mode
• Select the internal or external clock
Set SIO Transmit/Receive Mode Register
Set SIO Transmit Control Register
• Select the clock divider divide-by ratio (Note 1)
Serial I/O
related registers
• Divide-by ratio = H'00 to H'FF (Note 2)
Set SIO Baud Rate Register
• Select the source of transmit interrupt request (Note 3)
• Enable or disable transmit interrupt requests
Set SIO interrupt related registers
Set Interrupt Controller
(When using interrupts)
Set DMAC
(When using the DMAC)
Set Input/Output Port
Operation Mode Register
End of CSIO transmit initialization
Note 1: Necessary when the internal clock is selected.
Note 2: If the internal clock and a divide-by ratio = 1 are selected, caution must be used when setting the baud rate register
so that the transfer rate will not exceed 2 Mbps.
Note 3: Transmission finished interrupts are effective only when the internal clock is selected.
Figure 12.3.1 Procedure for Initializing CSIO Transmission
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12.3 Transmit Operation in CSIO Mode
12.3.3 Starting CSIO Transmission
The serial I/O starts a transmit operation when all of the following conditions are met after being initialized.
(1) Transmit conditions when CSIO mode internal clock is selected
• The SIO Transmit Control Register transmit enable bit is set to "1".
• Transmit data (8 bits) is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer
empty bit = "0")
(2) Transmit conditions when CSIO mode external clock is selected
• The SIO Transmit Control Register transmit enable bit is set to "1".
• Transmit data is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = "0")
• A falling edge of transmit clock on the SCLKI pin is detected.
Note 1: While the transmit enable bit is cleared to "0", writes to the transmit buffer register are ignored.
Always set the transmit enable bit to "1" before writing to the transmit buffer register.
Note 2: When the internal clock is selected, a write to the lower byte of the transmit buffer register in
above triggers transmission to start.
Note 3: The transmit status bit is set to "1" at the time data is set in the lower byte of the SIO Transmit
Buffer Register.
When transmission starts, the serial I/O sends data following the procedure described below.
• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.
• Set the transmit buffer empty bit to "1" (Note 1).
• Start sending data synchronously with the shift clock beginning with the LSB.
Note 1: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or
transmission has finished. Also, a DMA transfer request can be generated when the transmit
buffer is empty. No DMA transfer requests can be generated for reasons that transmission has
finished.
12.3.4 Successive CSIO Transmission
Once data has been transferred from the transmit buffer register to the transmit shift register, the next data can
be written to the transmit buffer register even when the serial I/O has not finished sending the previous data. If
the next data is written to the transmit buffer register before transmission has finished, the previous and the next
data are transmitted successively.
Check the SIO Transmit Control Register’s Status Register’s transmit buffer empty flag to see if data has been
transferred from the transmit buffer register to the transmit shift register.
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12.3 Transmit Operation in CSIO Mode
12.3.5 Processing at End of CSIO Transmission
When data transmission finishes, the following operation is automatically performed in hardware.
(1) When not transmitting successively
• The transmit status bit is cleared to "0".
(2) When transmitting successively
• When transmission of the last data in a consecutive data train finishes, the transmit status bit is cleared to "0".
12.3.6 Transmit Interrupts
(1) Transmit buffer empty interrupt
If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select Register, a
transmit buffer empty interrupt request is generated when data has been transferred from the transmit buffer
register to the transmit shift register. A transmit buffer empty interrupt request is also generated when the
TEN (Transmit Enable) bit is set to "1" (disabled → enabled) while the transmit buffer empty interrupt has
been enabled.
(2) Transmission finished interrupt
If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a
transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at
which the last bit of data in the transmit shift register has been transmitted or when the transmit enable bit is
cleared.
The SIO Interrupt Request Enable Register and the Interrupt Controller (ICU) must be set before these
transmit interrupts can be used.
12.3.7 Transmit DMA Transfer Request
When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA
transfer request for the corresponding SIO channel is output to the DMAC. A transmit DMA transfer request is
also output when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled).
The DMAC must be set before DMA transfers can be used during data transmission.
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12.3 Transmit Operation in CSIO Mode
The following processing is
automatically performed in hardware.
CSIO transmit
operation starts
Transmit
conditions met?
N
Y
(Note 1)
• Transfer the content of the transmit
Transmit interrupt request
• Set the transmit buffer empty bit to "1"
Transmit DMA transfer request
buffer to the transmit shift register
Transmit data
Y (Successive transmission)
Transmit
conditions met?
N
Clear the transmit status bit to "0"
End of CSIO
transmit operation
Note 1: This applies when the transmit interrupt request was enabled using the SIO Interrupt Request Enable Register
after selecting the transmit buffer empty interrupt with the SIO Interrupt Request Source Select Register.
Figure 12.3.2 Transmit Operation during CSIO Mode (Hardware Processing)
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12.3 Transmit Operation in CSIO Mode
12.3.8 Example of CSIO Transmit Operation
The following shows a typical transmit operation in CSIO mode.
<CSIO on transmit side>
<CSIO on receive side>
SCLKO
SCLKI
TXD
RXD
<CSIO on transmit side>
External clock selected
Internal clock selected
(Internal transfer clock)
Transmit clock
(SCLKO)
Set
Transmit enable bit
Write to the
transmit buffer
register
Cleared
Transmit buffer empty bit
Set by a write to the
transmit buffer
Content of the transmit buffer register
is transferred to the transmit shift register
Cleared by completion
of transmission
Transmit status bit
b7
TXD
SIO transmit interrupt request
(Note 1)
(When transmit buffer empty
interrupt is selected)
Transmit interrupt request
(Note 2) (Note 5)
b6
b5
b4
b3
b2
b1
b0
Transmit interrupt request
(Note 2) (Note 6)
Transmit interrupt request
(Note 3) (Note 7)
Interrupt request accepted (Note 4)
(When transmission finished
interrupt is selected)(Note 8)
Interrupt request accepted
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt
request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when
the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse
at which transmission of the transmit shift register data has finished or when the transmit enable bit is cleared.
Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected.
Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once)
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12.3 Transmit Operation in CSIO Mode
<CSIO on transmit side>
<CSIO on receive side>
SCLKO
SCLKI
TXD
RXD
<CSIO on transmit side>
Internal clock selected
External clock selected
(Internal transfer clock)
Transmit clock
(SCLKO)
Set
Transmit enable bit
Write to the
transmit buffer
register
Write to the
transmit buffer
register
(First data)
Transmit buffer empty bit
Cleared
(Next data)
Transmit status bit
Next data
First data
b7
TXD
SIO transmit interrupt request
(Note 1)
(When transmit buffer empty
interrupt is selected)
b6
b5
b0
b7
b6
b5
b0
Next data is written at a transmit
buffer empty interrupt
(Note 2)(Note 6)
(Note 2)
(Note 2)
(Note 5)
Transmit interrupt request
(Note 3)(Note 7)
Interrupt request accepted (Note 4)
(Note 3)
(When transmission finished
interrupt is selected) (Note 8)
Interrupt request accepted (Note 4)
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which
transmission of the transmit shift register data has finished or when the transmit enable bit is cleared.
Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected.
Figure 12.3.4 Example of CSIO Transmission (Transmitted Successively)
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12.4 Receive Operation in CSIO Mode
12.4 Receive Operation in CSIO Mode
12.4.1 Initialization for CSIO Reception
To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however,
that because the receive shift clock is derived by an operation of the transmit circuit, transmit operation must
always be executed even when the serial I/O is used for only receiving data.
(1) Setting SIO Transmit/Receive Mode Register
• Set the register to CSIO mode.
• Select the internal or an external clock.
(2) Setting SIO Transmit Control Register
• Select the clock divider’s divide-by ratio (when internal clock selected).
(3) Setting SIO Baud Rate Register
When the internal clock is selected, set a baud rate generator value. (See Section 12.3.1, “Setting the CSIO
Baud Rate.”)
(4) Setting SIO interrupt related registers
• Select the source of receive interrupt request (reception finished or error) (SIO Interrupt Request Source
Select Register).
• Enable or disable receive interrupts (SIO Interrupt Request Enable Register).
(5) Setting SIO Receive Control Register
• Set the receive enable bit.
(6) Setting Interrupt Controller (SIO Transmit Interrupt Control Register)
To use receive interrupts, set their priority levels.
(7) Setting DMAC
Set up the DMAC when the DMA transfer is requested to the internal DMAC on completion of the transmission.
(See Chapter 9, “DMAC.”)
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12.4 Receive Operation in CSIO Mode
(8) Selecting pin functions
Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/
output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)
Initialize CSIO reception
Set SIO Transmit/Receive Mode Register
Set SIO Transmit Control Register
• Set the register to CSIO mode
• Select the internal or external clock
• Select the clock divider divide-by ratio
(Note 1)
Serial I/O
related registers
Set SIO Baud Rate Register
• Divide-by ratio = H'00 to H'FF
(Note 2)
Set SIO interrupt related registers
• Select the source of receive interrupt request
• Enable or disable receive interrupt requests
Set SIO Receive Control Register
• Set the receive enable bit
Set Interrupt Controller
(When using interrupts)
Set DMAC
(When using the DMAC)
Set Input/Output Port
Operation Mode Register
End of CSIO receive initialization
Note 1: Necessary when the internal clock is selected.
Note 2: If the internal clock and a divide-by ratio = 1 are selected, caution must be used when setting the baud rate
register so that the transfer rate will not exceed 2 Mbps.
Figure 12.4.1 Procedure for Initializing CSIO Reception
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12.4 Receive Operation in CSIO Mode
12.4.2 Starting CSIO Reception
The serial I/O starts receive operation when all of the following conditions are met after being initialized.
(1) Receive conditions when CSIO mode internal clock is selected
• The SIO Receive Control Register receive enable bit is set to "1".
• Transmit conditions are met. (See Section 12.3.3, “Starting CSIO Transmission.”)
(2) Receive conditions when CSIO mode external clock is selected
• The SIO Receive Control Register receive enable bit is set to "1".
• Transmit conditions are met. (See Section 12.3.3, “Starting CSIO Transmission.”)
Note: • The receive status bit is set to "1" at the time dummy data is set in the lower byte of the SIO
Transmit Buffer Register.
When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first) synchronously with
the receive shift clock.
12.4.3 Processing at End of CSIO Reception
When data reception finishes, the following operation is automatically performed in hardware.
(1) When reception is completed normally
The reception finished (receive buffer full) bit is set to "1".
Notes: • An interrupt request is generated if the reception finished (receive buffer full) interrupt has been enabled.
• A DMA transfer request is generated.
(2) When an error occurred during reception
If an error (only overrun error in CSIO mode) occurred during reception, the overrun error bit and receive
error sum bit are set to "1".
Notes: • If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source Select
Register), neither a reception finished interrupt request nor a DMA transfer request is generated.
• If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source
Select Register), a receive error interrupt request is generated when interrupt requests are
enabled. No DMA transfer requests are generated.
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12.4 Receive Operation in CSIO Mode
12.4.4 About Successive Reception
If the following conditions are met when data reception has finished, data may be received successively.
• The receive enable bit is set to "1".
• Transmit conditions are met.
• No overrun error has occurred.
CSIO receive operation
starts
Receive conditions
met?
N
Y
Receive data
Y
Overrun error ?
N
Set the SIO Receive Control Register
overrun error and receive error sum bits to "1"
Set the SIO Receive Control Register
reception finished bit to "1"
Store the received data
in the receive buffer register
End of CSIO receive
operation
Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing)
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12.4 Receive Operation in CSIO Mode
12.4.5 Flags Showing the Status of CSIO Receive Operation
There are following flags that indicate the status of receive operation during CSIO mode:
• SIO Receive Control Register receive status bit
• SIO Receive Control Register reception finished bit
• SIO Receive Control Register receive error sum bit
• SIO Receive Control Register overrun error bit
When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial I/O
finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subsequent received data are not transferred to the receive buffer register.
Before receive operation can be restarted, the receive enable bit must temporarily be cleared to "0" to initialize
the receiver control unit.
The above reception finished bit, if no receive errors occurred (Note 1), may be cleared by reading out the lower
byte of the SIO Receive Buffer Register or clearing the REN (Receive Enable) bit.
However, if any receive error occurred, the reception finished bit can only be cleared by clearing the REN
(Receive Enable) bit, and cannot be cleared by reading out the lower byte of the SIO Receive Buffer Register.
Note 1: Overrun errors are the only error that can be detected during reception in CSIO mode.
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12.4 Receive Operation in CSIO Mode
12.4.6 Example of CSIO Receive Operation
The following shows a typical receive operation in CSIO mode.
<CSIO on transmit side>
<CSIO on receive side>
SCLKO
SCLKI
TXD
RXD
<CSIO on receive side>
Internal clock selected
External clock selected
Receive clock
(SCLKO)
Clock stops
Set
Receive enable bit
Cleared
b7
RXD
b6
b5
b4
b3
b2
b1
b0
Set by a write to
the transmit buffer
Receive status bit
Automatically cleared for each
receive operation performed
Reception finished bit
Read from the
receive buffer
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
Reception finished interrupt request
(Note 2)
Interrupt request accepted (Note 3)
(When receive error
interrupt is selected)
No interrupt request
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register
interrupt request bit cleared
Figure 12.4.3 Example of CSIO Reception (When Received Normally)
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12.4 Receive Operation in CSIO Mode
<CSIO on receive side>
<CSIO on transmit side>
SCLKO
SCLKI
RXD
TXD
Internal clock selected
External clock selected
<CSIO on receive side>
Receive clock
(SCLKI)
Set
Cleared
Receive enable bit
RXD
First data reception
completed
b7
b0
b6
b7
Next data reception
completed
b6
b0
Receive buffer not read
out during this interval
Reception finished bit
Set
Overrun error bit
Overrun error bit cleared
(Note 4)
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
Reception finished
interrupt request
(Note 2)
Interrupt request accepted (Note 5)
Receive error interrupt request
(Note 3)
(When receive error
interrupt is selected)
Interrupt request accepted (Note 5)
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled
Note 3: When receive error interrupt is enabled
Note 4: The receive enable bit is cleared
Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt
request bit cleared
Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred)
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12.5 Precautions on Using CSIO Mod
12.5 Precautions on Using CSIO Mode
• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register
The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s
BRG count source select bit must always be set before the serial I/O starts operating. If these settings need
to be changed after a transmit or receive operation has started, first check to see that transmit and receive
operations have finished and then clear the transmit and receive enable bits before making changes.
• Settings of BRG (Baud Rate Register)
If f(BCLK) is selected with the BRG clock source select bit, use caution when setting the BRG register so that
the transfer rate will not exceed 2 Mbps.
• About successive transmission
To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer Register
before the current data transmission finishes.
• About reception
Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, transmit
operation must always be executed (by sending dummy data) even when the serial I/O is used for only
receiving data. In this case, be aware that if the port function is set for the TXD pin (by setting the operation
mode register to "1"), dummy data may actually be output from the pin.
• About successive reception
To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer Register
before a transmit operation on the transmitter side starts.
• Transmission/reception using DMA
To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the
DMA Mode Register) before serial communication starts.
• About reception finished bit
If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the receive
enable bit, and cannot be cleared by reading out the receive buffer register.
• About overrun error
If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO
Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer
register, with the previous received data retained in it. Although a receive operation continues thereafter, the
subsequent received data is not stored in the receive buffer register (receive status bit = "1").
Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared to "0".
And this is the only way that the overrun error flag can be cleared.
• About DMA transfer request generation during SIO transmission
If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit enable bit
remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer request is generated.
• About DMA transfer request generation during SIO reception
If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer request
is generated. Be aware, however, that if an overrun error occurred during reception, this DMA transfer request is not generated.
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12.6 Transmit Operation in UART Mode
12.6 Transmit Operation in UART Mode
12.6.1 Setting the UART Baud Rate
The baud rate (data transfer rate) in UART mode is determined by a transmit/receive shift clock. During UART
mode, the source for this transmit/receive shift clock is always the internal clock no matter how the internal/
external clock select bit (SIO Transmit/Receive Mode Register bit 11) is set.
(1) Calculating the UART mode baud rate
After being divided by a clock divider, f(BCLK) is supplied to the Baud Rate Generator (BRG), after which it
is further divided by 16 to produce a transmit/receive shift clock.
The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the SIO Transmit Control Register CDIV (baud rate generator count source select) bits (bits 2–3).(Note 1)
The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by
16, thus generating a transmit/receive shift clock.
When the internal clock is selected in UART mode, the baud rate is calculated using the equation below.
Baud rate =
[bps]
f(BCLK)
Clock divider’s divide-by value x (baud rate register set value + 1) x 16
Baud rate register set value = H’00 to H’FF (Note 1)
Clock divider’s divide-by value = 1, 8, 32 or 256
Note 1: If divide-by-1 (i.e., f(BCLK) itself) is selected as the baud rate generator count source,
make sure the value set in the baud rate register is equal to or greater than 7.
12.6.2 UART Transmit/Receive Data Formats
The transmit/receive data format during UART mode is determined by setting the SIO Transmit/Receive Mode
Register. Shown below is the transmit/receive data format that can be used in UART mode.
Next
data
Transmit data
Data bits (8 bits)
LSB
ST
b7
MSB
b6
b5
b4
b3
b2
b1
b0
Start
bit
PAR
Parity
bit
SP
SP
ST
Stop
bit
Figure 12.6.1 Example of a Transfer Data Format during UART Mode
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12.6 Transmit Operation in UART Mode
Table 12.6.1 Transfer Data in UART Mode
Bit Name
Content
ST (start bit)
Indicates the beginning of data transmission. This is a low-level signal of a one bit
period, which is added immediately preceding the transmit data.
Bits 0–8 (character bits)
Transmit/receive data transferred via serial I/O. In UART mode, 7, 8 or 9 bits of data
can be transmitted/received.
PAR (parity bit)
Added to the transmit/receive character. When parity is enabled, parity is
automatically set in such a way that the number of 1’s in the character including the
parity bit itself is always even or odd as selected by the even/odd parity select bit.
SP (stop bit)
Indicates the end of data transmission, which is added immediately following the
character (or if parity is enabled, immediately following the parity bit). The stop bit
can be chosen to be one bit or two bits long.
LSB
MSB
ST
b7
b6
b5
b4
b3
b2
b1
SP
ST
b7
b6
b5
b4
b3
b2
b1
SP
SP
ST
b7
b6
b5
b4
b3
b2
b1
PAR
SP
ST
b7
b6
b5
b4
b3
b2
b1
PAR
SP
SP
7-bit character
LSB
MSB
ST
b7
b6
b5
b4
b3
b2
b1
b0
SP
ST
b7
b6
b5
b4
b3
b2
b1
b0
SP
SP
ST
b7
b6
b5
b4
b3
b2
b1
b0
PAR
SP
ST
b7
b6
b5
b4
b3
b2
b1
b0
PAR
SP
SP
8-bit character
LSB
MSB
ST
b8
b7
b6
b5
b4
b3
b2
b1
b0
SP
ST
b8
b7
b6
b5
b4
b3
b2
b1
b0
SP
SP
ST
b8
b7
b6
b5
b4
b3
b2
b1
b0
PAR
SP
ST
b8
b7
b6
b5
b4
b3
b2
b1
b0
PAR
SP
SP
9-bit character
SIO Transmit Buffer Register
SIO Receive Buffer Register
b0
b7 b8
b15
ST: Start bit
Bits 0-7: Character (data) bits
PAR: Parity bit
SP: Stop bit
7-bit character
8-bit character
9-bit character
Notes: • The high-order bits of the selected character length in the SIO Receive Buffer Register are fixed to "0".
• The data bit numbers (bn) above indicate bit numbers in a data list, and not the register bit numbers (bn).
Figure 12.6.2 Selectable Data Formats during UART Mode
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12.6 Transmit Operation in UART Mode
12.6.3 Initializing UART Transmission
To transmit data in UART mode, initialize the serial I/O following the procedure described below.
(1) Setting SIO Transmit/Receive Mode Register
• Set the register to UART mode.
• Set parity (when enabled, select odd/even).
• Set the stop bit length.
• Set the character length (Note 1).
Note 1: During UART mode, settings of the internal/external clock select bit have no effect (only the
internal clock is useful).
(2) Setting SIO Transmit Control Register
• Select the clock divider’s divide-by ratio.
(3) Setting SIO Baud Rate Register
Set a baud rate generator value. (See Section 12.6.1, “Setting the UART Baud Rate.”)
(4) Setting SIO interrupt related registers
• Select the source of transmit interrupt request (transmit buffer empty or transmission finished)
(SIO Interrupt Request Source Select Register).
• Enable or disable SIO transmit interrupt requests (SIO Interrupt Request Enable Register).
(5) Setting Interrupt Controller (SIO Transmit Interrupt Control Register)
To use transmit interrupts, set their priority levels.
(6) Setting DMAC
To issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set up the DMAC.
(See Chapter 9, “DMAC.”)
(7) Selecting pin functions
Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/
output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)
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12.6 Transmit Operation in UART Mode
Initialize UART transmission
Set SIO Transmit/Receive Mode Register
Serial I/O
related registers
• Set the register to UART mode
• Set parity (when enabled, select odd/even)
• Set the stop bit length
• Set the character length
Set SIO Transmit Control Register
• Select the clock divider divide-by ratio
Set SIO Baud Rate Register
• Divide-by ratio = H'00 to H'FF (Note 1)
Set SIO interrupt related registers
• Select the source of transmit interrupt request
• Enable or disable transmit interrupt requests
Set Interrupt Controller
(When using interrupts)
Set DMAC related registers
(When using the DMAC)
Set Input/Output Port
Operation Mode Register
End of UART transmit initialization
Note 1: If f(BCLK) is selected for BRG count source (CDVI), it is necessary that the value set in the baud rate
register be equal to or greater than 7.
Figure 12.6.3 Procedure for Initializing UART Transmission
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12.6 Transmit Operation in UART Mode
12.6.4 Starting UART Transmission
The serial I/O starts a transmit operation when all of the following conditions are met after being initialized.
• SIO Transmit Control Register TEN (Transmit Enable) bit is set to "1" (Note 1).
• Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = "0").
Note 1: While the transmit enable bit is cleared to "0", writes to the transmit buffer are ignored. Always be
sure to set the transmit enable bit to "1" before writing to the transmit buffer register.
When transmission starts, the serial I/O sends data following the procedure described below.
• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.
• Set the transmit buffer empty bit to "1" (Note 2).
• Start sending data synchronously with the shift clock beginning with the LSB.
Note 2: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or
transmission has finished. Also, a DMA transfer request can be generated when the transmit
buffer is empty. No DMA transfer requests can be generated for reasons that transmission has
finished.
12.6.5 Successive UART Transmission
Once data has been transferred from the transmit buffer register to the transmit shift register, the next data can
be written to the transmit buffer register even when the serial I/O has not finished sending the previous data. If
the next data is written to the transmit buffer before transmission has finished, the previous and the next data are
transmitted successively.
Check the SIO Transmit Control Register’s transmit buffer empty flag to see if data has been transferred from
the transmit buffer register to the transmit shift register.
12.6.6 Processing at End of UART Transmission
When data transmission finishes, the following operation is automatically performed in hardware.
(1) When not transmitting successively
• The transmit status bit is cleared to "0".
(2) When transmitting successively
• When transmission of the last data in a consecutive data train finishes, the transmit status bit is cleared to "0".
12.6.7 Transmit Interrupts
(1) Transmit buffer empty interrupt
If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select Register, a
transmit buffer empty interrupt request is generated when data has been transferred from the transmit buffer
register to the transmit shift register. A transmit buffer empty interrupt request is also generated when the
TEN (Transmit Enable) bit is set to "1" (reenabled after being disabled) while the transmit buffer empty
interrupt has been enabled.
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12.6 Transmit Operation in UART Mode
(2) Transmission finished interrupt
If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a
transmission finished interrupt request is generated when data in the transmit shift register has all been
transmitted.
The SIO Interrupt Request Enable Register and the Interrupt Controller (ICU) must be set before these transmit
interrupts can be used.
12.6.8 Transmit DMA Transfer Request
When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA
transfer request for the corresponding SIO channel is output to the DMAC. A transmit DMA transfer request is
also output when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled).
The DMAC must be set before DMA transfers can be used during data transmission.
The following processing is automatically performed in hardware.
UART transmit
operation starts
Transmit conditions
met ?
N
Y
Transmit interrupt request (Note 1)
the content of the transmit buffer
• Transfer
to the transmit shift register
• Set the transmit buffer empty bit to "1"
Transmit DMA transfer request
Transmit data
Y (Successive transmission)
Transmit conditions
met ?
N
Clear the transmit status bit to "0"
End of UART
transmit operation
Note 1: This applies when the transmit interrupt was enabled using the SIO Interrupt Request Enable Register
after selecting the transmit buffer empty interrupt with the SIO Interrupt Request Source Select Register.
Figure 12.6.4 Transmit Operation during UART Mode (Hardware Processing)
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12.6 Transmit Operation in UART Mode
12.6.9 Example of UART Transmit Operation
The following shows a typical transmit operation in UART mode.
<UART on transmit side>
<UART on receive side>
TXD
RXD
Set
<UART on transmit side>
Transmit enable bit
Write to the
transmit buffer
register
Cleared
Set
Transmit buffer
empty bit
Transferred from the transmit buffer
to the transmit shift register
(transmission starts)
Cleared
Transmit status bit
TXD
Transmit
interrupt request
SIO transmit interrupt request (Note 1)
(When transmit buffer empty
interrupt is selected)
(Note 2)
(Note 5)
ST
b7
b0
b6
PAR
SP
SP
Transmit interrupt request
(Note 2)(Note 6)
Transmit interrupt request
(Note 3)(Note 7)
Interrupt request accepted (Note 4)
(When transmission finished
interrupt is selected)
Interrupt request accepted (Note 4)
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.
Figure 12.6.5 Example of UART Transmission (Transmitted Only Once)
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12.6 Transmit Operation in UART Mode
<UART on transmit side>
<UART on receive side>
TXD
RXD
<UART on transmit side>
Set
Transmit enable bit
Transmit buffer
empty bit
Cleared
Write to the
transmit buffer
register
Write to the
transmit buffer
register
(First data)
(Next data)
Cleared when transfer of
the last data is completed
Transferred from the
transmit buffer to the
transmit shift register
(transmission starts)
Transmit status bit
First data
ST
TXD
SIO transmit interrupt request
(Note 1)
(When transmit buffer empty
interrupt is selected)
(Note 5)
(Note 2)
b7
b0
Next data
SP
ST
b0
b7
SP
Next data is written
upon transmit interrupt
(Note 2)
Interrupt request accepted (Note 4)
(Note 2)(Note 6)
(Note 3)
(Note 3)(Note 7)
(When transmission finished
interrupt is selected)
Interrupt request accepted (Note 4)
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.
Figure 12.6.6 Example of UART Transmission (Transmitted Successively)
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12.7 Receive Operation in UART Mode
12.7 Receive Operation in UART Mode
12.7.1 Initialization for UART Reception
To receive data in UART mode, initialize the serial I/O following the procedure described below.
(1) Setting SIO Transmit/Receive Mode Register
• Set the register to UART mode.
• Set parity (when enabled, select odd/even).
• Set the stop bit length.
• Set the character length.
Note: • During UART mode, settings of the internal/external clock select bit have no effect (only the
internal clock is useful).
(2) Setting SIO Transmit Control Register
• Set the clock divider’s divide-by ratio.
(3) Setting SIO Baud Rate Register
Set a baud rate generator value. (See Section 12.6.1, “Setting the UART Baud Rate.”)
(4) Setting SIO interrupt related registers
• Select the source of receive interrupt request (reception finished or receive error) (Interrupt Request
Source Select Register).
• Enable or disable receive interrupts (Interrupt Request Enable Register).
(5) Setting Interrupt Controller
To use receive interrupt, set their priority levels.
(6) Setting DMAC
To issue DMA transfer requests to the internal DMAC when reception has finished, set up the DMAC. (See
Chapter 9, “DMAC.”)
(7) Selecting pin functions
Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/
output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)
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12.7 Receive Operation in UART Mode
Initialize UART reception
Set SIO Transmit/Receive Mode Register
Serial I/O
related registers
• Set the register to UART mode
• Set parity (when enabled, select odd/even)
• Set the stop bit length
• Set the character length
Set SIO Transmit Control Register
• Select the clock divider divide-by ratio
Set SIO Baud Rate Register
• Divide-by ratio = H'00 to H'FF (Note 1)
Set SIO interrupt related registers
• Select the source of receive interrupt reques
• Enable or disable receive interrupt requests
Set Interrupt Controller's
SIO Receive Interrupt Control Register
(When using interrupts)
Set DMAC related registers
(When using the DMAC)
Set Input/Output Port
Operation Mode Register
End of UART receive initialization
Note 1: If clock divider divide-by ratio = 1 is selected, it is necessary that the value set in the baud rate
register be equal to or greater than 7.
Figure 12.7.1 Procedure for Initializing UART Reception
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12.7 Receive Operation in UART Mode
12.7.2 Starting UART Reception
The serial I/O starts receive operation when all of the following conditions are met after being initialized.
• SIO Receive Control Register receive enable bit is set to "1"
• Start bit (falling edge signal) is applied to the RXD pin
When the above conditions are met, the serial I/O enters UART receive operation. However, the start bit is
checked again at the first rise of the internal receive shift clock and if it is detected high for reasons of noise, etc.,
the serial I/O stops receive operation and waits for the start bit again.
12.7.3 Processing at End of UART Reception
When data reception finishes, the following operation is automatically performed in hardware.
(1) When reception is completed normally
The reception finished (receive buffer full) bit is set to "1".
Notes: • An interrupt request is generated if the reception finished (receive buffer full) interrupt has been
enabled.
• A DMA transfer request is generated.
(2) When a receive error occurred
If an error occurred, the corresponding error bit (OE, FE or PE) and the receive error sum bit are set to "1".
Notes: • If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source
Select Register), a reception finished interrupt request is generated when interrupt requests
are enabled. However, this does not apply when the detected error is an overrun error, in which
case no reception finished interrupt requests are generated.
• If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source
Select Register), a receive error interrupt request is generated when interrupt requests are
enabled.
• No DMA transfer requests are generated.
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12.7 Receive Operation in UART Mode
The following processing is automatically performed in hardware.
UART receive
operation starts
Receive conditions
met ?
N
Y
Start bit detected
normally ?
N
Y
Set the receive status bit to "1"
Receive data
Y
Overrun error ?
N
Transfer data from the SIO Receive Shift
Register to the SIO Receive Buffer Register
Set the SIO Receive Control
Register overrun error bit
and error sum bit to "1"
Parity error
or
framing error ?
Y
N
Set the SIO Receive Control
Register's corresponding error bit
and receive error sum bit to "1"
Set the SIO Receive Control Register
reception finished bit to "1"
End of UART reception
Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing)
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12.7 Receive Operation in UART Mode
12.7.4 Example of UART Receive Operation
The following shows a typical receive operation in UART mode.
<UART on receive side>
<UART on transmit side>
TXD
RXD
Internal clock selected
<UART on receive side>
Set
Receive enable bit
(SIO Receive Control Register)
Cleared
RXD
ST
b7
b6
b0
PAR
SP SP
Receive status bit
Automatically cleared for
each receive operation
performed
Reception finished bit
Read from the
receive buffer
SIO receive interrupt
request (Note 1)
Reception finished
interrupt request
(Note 2)
(When reception finished
interrupt is selected)
Interrupt request accepted (Note 3)
(When receive error
interrupt is selected)
No interrupt request
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt
request bit cleared
Figure 12.7.3 Example of UART Reception (When Received Normally)
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12.7 Receive Operation in UART Mode
<UART on receive side>
<UART on transmit side>
TXD
RXD
<UART on receive side>
Set
Receive enable bit
(SIO Receive Control Register)
RXD
First data reception
completed
ST
b7
SP
ST
Next data reception
completed
SP
b7
Receive buffer not read
during this interval
Reception finished bit
Set
(Note 5)
Overrun error bit
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
Overrun error bit
cleared (Note 4)
Reception finished
interrupt request
(Note 2)
Interrupt request accepted (Note 5)
(When receive error
interrupt is selected)
Receive error interrupt request
(Note 3)
Interrupt request accepted (Note 5)
: Processing by software
: Interrupt request generated
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled
Note 3: When receive error interrupt is enabled
Note 4: This is done by clearing the receive enable bit to "0".
Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt
request bit cleared
Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred)
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12.7 Receive Operation in UART Mode
12.7.5 Start Bit Detection during UART Reception
The start bit is sampled synchronously with the internal BRG output. If the received signal remains low for 8
BRG output cycles after the falling edge of the start bit, the CPU recognizes that part of the received signal as
the start bit and starts latching the received data another 8 cycles after that, beginning with the LSB (first bit). If
some sampled part of the received signal is high before being determined to be the start bit, the CPU starts
detecting the falling edge of the received signal again. Because the start bit is sampled synchronously with the
internal BRG output, there is a delay equivalent to one BRG output cycle at maximum. The subsequent received
data is latched into the internal circuit with that delayed timing.
16 cycles
Internal BRG output
8 cycles
8 cycles
LSB data
RXD
Note: • This diagram does not show detailed timing information.
Figure 12.7.5 Start Bit Detection
Internal BRG output
8 cycles
RXD
Note: • This diagram does not show detailed timing information.
Figure 12.7.6 Example of an Invalid Start Bit (Not Received)
Internal BRG output
Delay equivalent to one BRG output cycle at maximum
RXD
Internal RXD
Figure 12.7.7 Delay in Receive Timing
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12.8 Fixed Period Clock Output Function
12.8 Fixed Period Clock Output Function
When using SIO0 or SIO1 in UART mode, the relevant port (P84 or P87) can be switched for use as an SCLKO0
or SCLKO1 pin, respectively. That way, a BRG output clock divided by 2 can be output from the SCLKO pin.
Note: • This clock is output not just during data transfer.
1. Configuration when using BRG/2 clock
TXD
RXD
SCLKO
UART
transmission/reception
ST
Data
SP
ST
Data
SP
Clock output to
peripheral circuits
2. Operation timing
Internal BRG
output
BRG period
SCLKO output
50%
50%
Figure 12.8.1 Example of Fixed Period Clock Output
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12.9 Precautions on Using UART Mode
12.9 Precautions on Using UART Mode
• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register
The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control
Register’s BRG count source select bit must always be set before the serial I/O starts operating. If these
settings need to be changed after a transmit or receive operation has started, first check to see that
transmit and receive operations have finished and then clear the transmit and receive enable bits before
making changes.
• Settings of BRG (Baud Rate Register)
If f(BCLK) is selected with the BRG clock source select bit, make sure the value set in the BRG register
is equal to or greater than 7.
Writes to the SIO Baud Rate Register take effect in the next cycle after the BRG counter has finished
counting. However, if the register is accessed for write while transmission and reception are disabled,
the written value takes effect at the same time it is written.
• Transmission/reception using DMA
To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting
the DMA Mode Register) before serial communication starts.
• About overrun error
If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the
SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the
receive buffer register, with the previous received data retained in it. Once an overrun error occurs,
although a receive operation continues, the subsequent received data is not stored in the receive buffer
register. Before normal receive operation can be restarted, the receive enable bit must be temporarily
cleared. And this is the only way that the overrun error flag can be cleared.
• Flags showing the status of UART receive operation
There are following flags that indicate the status of receive operation during UART mode:
• SIO Receive Control Register receive status bit
• SIO Receive Control Register reception finished bit
• SIO Receive Control Register receive error sum bit
• SIO Receive Control Register overrun error bit
• SIO Receive Control Register parity error bit
• SIO Receive Control Register framing error bit
The manner in which the reception finished bit and various error flags are cleared differs depending on
whether an overrun error occurred, as described below.
[When an overrun error did not occur]
Cleared by reading out the lower byte of the receive buffer register or by clearing the receive enable bit.
[When an overrun error occurred]
Cleared by only clearing the receive enable bit.
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12.9 Precautions on Using UART Mode
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CHAPTER 13
CAN MODULE
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
Outline of the CAN Module
CAN Module Related Registers
CAN Protocol
Initializing the CAN Module
Transmitting Data Frames
Receiving Data Frames
Transmitting Remote Frames
Receiving Remote Frames
Precautions about CAN Module
CAN MODULE
13
13.1 Outline of the CAN Module
13.1 Outline of the CAN Module
The 32182 contains two-channel Full CAN modules compliant with CAN (Controller Area Network) Specification
V2.0 B Active. These CAN modules each have 16 message slots and three mask registers, effective use of which
helps to reduce the data processing load of the CPU.
The CAN modules are outlined below.
Table 13.1.1 Outline of the CAN Module
Item
Description
Protocol
CAN Specification V2.0 B Active
Number of message slots
Total 16 slots (14 global slots, two local slots)
Polarity
0: Dominant
1: Recessive
Acceptance filter
Global mask: 1
(Function to receive only a range
Local mask: 2
of IDs specified by receive ID filter)
Baud rate
1 time quantum (Tq) = (BRP + 1) / (CPU clock/2)
(BRP: Baud Rate Prescaler set value)
Baud rate =
1
Tq period × number of Tq’s for one bit
..... Max 1 Mbps (Note 1)
BRP: 1–255 (0: inhibited)
Number of Tq’s for one bit = Synchronization Segment + Propagation Segment
+ Phase Segment 1 + Phase Segment 2
Propagation Segment: 1–8Tq
Phase Segment 1: 1–8Tq
Phase Segment 2: 1–8Tq (IPT = "1")
Remote frame automatic
The slot that received a remote frame responds by automatically sending a data frame.
response function
Timestamp function
This function is implemented using a 16-bit counter. The count period is derived from the
CAN bus bit period by dividing it by 1, 2, 3 or 4.
BasicCAN mode
BasicCAN function is materialized using two local slots.
Transmit abort function
Transmit requests can be canceled.
Loopback function
The CAN module receives the data transmitted by itself.
Return bus off function
Error active mode is forcibly entered into after clearing the error counter.
Single shot function
Transmission is not retried even when it failed due to arbitration-lost or a transmit error.
DMA transfer function
DMA transfer request is generated when transmission failed or transmit/receive operation
finished (CAN0 only).
Self-diagnostic function
Communication module is diagnosed by communicating internally in the CAN module.
Note 1: The maximum allowable error of oscillation depends on the system configuration (e.g., bus length, clock error, CAN
bus transceiver, sampling position and bit configuration).
Table 13.1.2 DMA Transfer Requests Generated by CAN
DMA Transfer Request by CAN
DMAC Input Channel
CAN0: Slot 0 transmission failed or slot 15 transmit/receive operation finished
DMA0
CAN1: Slot 1 transmission failed or slot 14 transmit/receive operation finished
DMA2
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13.1 Outline of the CAN Module
Table 13.1.3 Interrupt Requests Generated by CAN Modules
CAN Module Interrupt Request Source
ICU Input Interrupt Source
CAN0 transmission completed
CAN0 transmit/receive & error interrupt
CAN1 transmission completed
CAN1 transmit/receive & error interrupt
CAN0 reception completed
CAN0 transmit/receive & error interrupt
CAN1 reception completed
CAN1 transmit/receive & error interrupt
CAN0 bus error
CAN0 transmit/receive & error interrupt
CAN1 bus error
CAN1 transmit/receive & error interrupt
CAN0 error passive
CAN0 transmit/receive & error interrupt
CAN1 error passive
CAN1 transmit/receive & error interrupt
CAN0 bus off
CAN0 transmit/receive & error interrupt
CAN1 bus off
CAN1 transmit/receive & error interrupt
CAN0 single shot
CAN0 transmit/receive & error interrupt
CAN1 single shot
CAN1 transmit/receive & error interrupt
Internal data bus
CAN0
CPUCLK
Baud Rate
Prescaler
CTX0
Selfdiagnosis
Control
Acceptance
Filter
CRX0
CAN
Protocol
Controller
Interrupt
DAM Request
Message
Slot × 16
Transmit/receive
completed,
error or single shot
DMA0, 2
CAN1
CPUCLK
Baud Rate
Prescaler
CTX1
Selfdiagnosis
Control
CRX1
Acceptance
Filter
CAN
Protocol
Controller
Interrupt
Message
Slot × 16
Transmit/receive
completed,
error or single shot
Figure 13.1.1 Block Diagram of the CAN Modules
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13
13.2 CAN Module Related Registers
13.2 CAN Module Related Registers
Shown below is a CAN module related register map.
CAN Module Related Register Map (1/11)
Address
+0 address
b0
H'0080 1000
H'0080 1002
H'0080 1004
H'0080 1006
H'0080 1008
H'0080 100A
H'0080 100C
H'0080 100E
H'0080 1010
H'0080 1012
H'0080 1014
H'0080 1016
H'0080 1018
|
H'0080 1028
H'0080 102A
H'0080 102C
H'0080 102E
H'0080 1030
H'0080 1032
H'0080 1034
H'0080 1036
H'0080 1038
H'0080 103A
H'0080 103C
H'0080 103E
H'0080 1040
H'0080 1042
H'0080 1044
H'0080 1046
H'0080 1048
|
+1 address
b7 b8
CAN0 Control Register
(CAN0CNT)
CAN0 Status Register
(CAN0STAT)
CAN0 Frame Format Select Register
(CAN0FFS)
CAN0 Configuration Register
(CAN0CONF)
CAN0 Timestamp Count Register
(CAN0TSTMP)
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
(CAN0REC)
(CAN0TEC)
CAN0 Slot Interrupt Request Status Register
(CAN0SLIST)
(Use inhibited area)
See pages
b15
13-15
13-18
13-21
13-22
13-24
13-25
13-29
CAN0 Slot Interrupt Request Enable Register
(CAN0SLIEN)
(Use inhibited area)
13-30
CAN0 Error Interrupt Request Status Register
CAN0 Error Interrupt Request Enable Register
(CAN0ERIST)
(CAN0ERIEN)
CAN0 Baud Rate Prescaler
CAN0 Cause of Error Register
(CAN0BRP)
(CAN0EF)
CAN0 Mode Register
CAN0 DMA Transfer Request Select Register
(CAN0MOD)
(CAN0DMARQ)
(Use inhibited area)
13-31
13-32
13-26
13-45
13-46
13-47
CAN0 Global Mask Register Standard ID0
CAN0 Global Mask Register Standard ID1
(C0GMSKS0)
(C0GMSKS1)
CAN0 Global Mask Register Extended ID0
CAN0 Global Mask Register Extended ID1
(C0GMSKE0)
(C0GMSKE1)
CAN0 Global Mask Register Extended ID2
(Use inhibited area)
(C0GMSKE2)
(Use inhibited area)
13-48
13-49
13-50
CAN0 Local Mask Register A Standard ID0
CAN0 Local Mask Register A Standard ID1
(C0LMSKAS0)
(C0LMSKAS1)
CAN0 Local Mask Register A Extended ID0
CAN0 Local Mask Register A Extended ID1
(C0LMSKAE0)
(C0LMSKAE1)
CAN0 Local Mask Register A Extended ID2
(Use inhibited area)
(C0LMSKAE2)
(Use inhibited area)
13-48
CAN0 Local Mask Register B Standard ID0
CAN0 Local Mask Register B Standard ID1
(C0LMSKBS0)
(C0LMSKBS1)
CAN0 Local Mask Register B Extended ID0
CAN0 Local Mask Register B Extended ID1
(C0LMSKBE0)
(C0LMSKBE1)
CAN0 Local Mask Register B Extended ID2
(Use inhibited area)
(C0LMSKBE2)
(Use inhibited area)
13-48
CAN0 Single-Shot Mode Control Register
(CAN0SSMODE)
(Use inhibited area)
13-52
CAN0 Single-Shot Interrupt Request Status Register
(CAN0SSIST)
(Use inhibited area)
13-33
CAN0 Single-Shot Interrupt Request Enable Register
(CAN0SSIEN)
13-34
13-49
13-50
13-49
13-50
(Use inhibited area)
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13
13.2 CAN Module Related Registers
CAN Module Related Register Map (2/11)
Address
+0 address
b0
H'0080 1050
H'0080 1052
H'0080 1054
H'0080 1056
H'0080 1058
H'0080 105A
H'0080 105C
H'0080 105E
|
H'0080 1100
H'0080 1102
H'0080 1104
H'0080 1106
H'0080 1108
H'0080 110A
H'0080 110C
H'0080 110E
H'0080 1110
H'0080 1112
H'0080 1114
H'0080 1116
H'0080 1118
H'0080 111A
H'0080 111C
H'0080 111E
H'0080 1120
H'0080 1122
H'0080 1124
H'0080 1126
H'0080 1128
H'0080 112A
H'0080 112C
H'0080 112E
+1 address
b7 b8
CAN0 Message Slot 0 Control Register
CAN0 Message Slot 1 Control Register
(C0MSL0CNT)
(C0MSL1CNT)
CAN0 Message Slot 2 Control Register
CAN0 Message Slot 3 Control Register
(C0MSL2CNT)
(C0MSL3CNT)
CAN0 Message Slot 4 Control Register
CAN0 Message Slot 5 Control Register
(C0MSL4CNT)
(C0MSL5CNT)
CAN0 Message Slot 6 Control Register
CAN0 Message Slot 7 Control Register
(C0MSL6CNT)
(C0MSL7CNT)
CAN0 Message Slot 8 Control Register
CAN0 Message Slot 9 Control Register
(C0MSL8CNT)
(C0MSL9CNT)
CAN0 Message Slot 10 Control Register
CAN0 Message Slot 11 Control Register
(C0MSL10CNT)
(C0MSL11CNT)
CAN0 Message Slot 12 Control Register
CAN0 Message Slot 13 Control Register
(C0MSL12CNT)
(C0MSL13CNT)
CAN0 Message Slot 14 Control Register
CAN0 Message Slot 15 Control Register
(C0MSL14CNT)
(C0MSL15CNT)
(Use inhibited area)
CAN0 Message Slot 0 Standard ID0
CAN0 Message Slot 0 Standard ID1
(C0MSL0SID0)
(C0MSL0SID1)
CAN0 Message Slot 0 Extended ID0
CAN0 Message Slot 0 Extended ID1
(C0MSL0EID0)
(C0MSL0EID1)
CAN0 Message Slot 0 Extended ID2
CAN0 Message Slot 0 Data Length Register
(C0MSL0EID2)
(C0MSL0DLC)
CAN0 Message Slot 0 Data 0
CAN0 Message Slot 0 Data 1
(C0MSL0DT0)
(C0MSL0DT1)
CAN0 Message Slot 0 Data 2
CAN0 Message Slot 0 Data 3
(C0MSL0DT2)
(C0MSL0DT3)
CAN0 Message Slot 0 Data 4
CAN0 Message Slot 0 Data 5
(C0MSL0DT4)
(C0MSL0DT5)
CAN0 Message Slot 0 Data 6
CAN0 Message Slot 0 Data 7
(C0MSL0DT6)
(C0MSL0DT7)
CAN0 Message Slot 0 Timestamp
(C0MSL0TSP)
CAN0 Message Slot 1 Standard ID0
CAN0 Message Slot 1 Standard ID1
(C0MSL1SID0)
(C0MSL1SID1)
CAN0 Message Slot 1 Extended ID0
CAN0 Message Slot 1 Extended ID1
(C0MSL1EID0)
(C0MSL1EID1)
CAN0 Message Slot 1 Extended ID2
CAN0 Message Slot 1 Data Length Register
(C0MSL1EID2)
(C0MSL1DLC)
CAN0 Message Slot 1 Data 0
CAN0 Message Slot 1 Data 1
(C0MSL1DT0)
(C0MSL1DT1)
CAN0 Message Slot 1 Data 2
CAN0 Message Slot 1 Data 3
(C0MSL1DT2)
(C0MSL1DT3)
CAN0 Message Slot 1 Data 4
CAN0 Message Slot 1 Data 5
(C0MSL1DT4)
(C0MSL1DT5)
CAN0 Message Slot 1 Data 6
CAN0 Message Slot 1 Data 7
(C0MSL1DT6)
(C0MSL1DT7)
CAN0 Message Slot 1 Timestamp
(C0MSL1TSP)
CAN0 Message Slot 2 Standard ID0
CAN0 Message Slot 2 Standard ID1
(C0MSL2SID0)
(C0MSL2SID1)
CAN0 Message Slot 2 Extended ID0
CAN0 Message Slot 2 Extended ID1
(C0MSL2EID0)
(C0MSL2EID1)
CAN0 Message Slot 2 Extended ID2
CAN0 Message Slot 2 Data Length Register
(C0MSL2EID2)
(C0MSL2DLC)
CAN0 Message Slot 2 Data 0
CAN0 Message Slot 2 Data 1
(C0MSL2DT0)
(C0MSL2DT1)
CAN0 Message Slot 2 Data 2
CAN0 Message Slot 2 Data 3
(C0MSL2DT2)
(C0MSL2DT3)
CAN0 Message Slot 2 Data 4
CAN0 Message Slot 2 Data 5
(C0MSL2DT4)
(C0MSL2DT5)
CAN0 Message Slot 2 Data 6
CAN0 Message Slot 2 Data 7
(C0MSL2DT6)
(C0MSL2DT7)
CAN0 Message Slot 2 Timestamp
(C0MSL2TSP)
13-5
See pages
b15
13-53
13-53
13-53
13-53
13-53
13-53
13-53
13-53
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (3/11)
Address
+0 address
b0
H'0080 1130
H'0080 1132
H'0080 1134
H'0080 1136
H'0080 1138
H'0080 113A
H'0080 113C
H'0080 113E
H'0080 1140
H'0080 1142
H'0080 1144
H'0080 1146
H'0080 1148
H'0080 114A
H'0080 114C
H'0080 114E
H'0080 1150
H'0080 1152
H'0080 1154
H'0080 1156
H'0080 1158
H'0080 115A
H'0080 115C
H'0080 115E
H'0080 1160
H'0080 1162
H'0080 1164
H'0080 1166
H'0080 1168
H'0080 116A
H'0080 116C
H'0080 116E
+1 address
b7 b8
CAN0 Message Slot 3 Standard ID0
CAN0 Message Slot 3 Standard ID1
(C0MSL3SID0)
(C0MSL3SID1)
CAN0 Message Slot 3 Extended ID0
CAN0 Message Slot 3 Extended ID1
(C0MSL3EID0)
(C0MSL3EID1)
CAN0 Message Slot 3 Extended ID2
CAN0 Message Slot 3 Data Length Register
(C0MSL3EID2)
(C0MSL3DLC)
CAN0 Message Slot 3 Data 0
CAN0 Message Slot 3 Data 1
(C0MSL3DT0)
(C0MSL3DT1)
CAN0 Message Slot 3 Data 2
CAN0 Message Slot 3 Data 3
(C0MSL3DT2)
(C0MSL3DT3)
CAN0 Message Slot 3 Data 4
CAN0 Message Slot 3 Data 5
(C0MSL3DT4)
(C0MSL3DT5)
CAN0 Message Slot 3 Data 6
CAN0 Message Slot 3 Data 7
(C0MSL3DT6)
(C0MSL3DT7)
CAN0 Message Slot 3 Timestamp
(C0MSL3TSP)
CAN0 Message Slot 4 Standard ID0
CAN0 Message Slot 4 Standard ID1
(C0MSL4SID0)
(C0MSL4SID1)
CAN0 Message Slot 4 Extended ID0
CAN0 Message Slot 4 Extended ID1
(C0MSL4EID0)
(C0MSL4EID1)
CAN0 Message Slot 4 Extended ID2
CAN0 Message Slot 4 Data Length Register
(C0MSL4EID2)
(C0MSL4DLC)
CAN0 Message Slot 4 Data 0
CAN0 Message Slot 4 Data 1
(C0MSL4DT0)
(C0MSL4DT1)
CAN0 Message Slot 4 Data 2
CAN0 Message Slot 4 Data 3
(C0MSL4DT2)
(C0MSL4DT3)
CAN0 Message Slot 4 Data 4
CAN0 Message Slot 4 Data 5
(C0MSL4DT4)
(C0MSL4DT5)
CAN0 Message Slot 4 Data 6
CAN0 Message Slot 4 Data 7
(C0MSL4DT6)
(C0MSL4DT7)
CAN0 Message Slot 4 Timestamp
(C0MSL4TSP)
CAN0 Message Slot 5 Standard ID0
CAN0 Message Slot 5 Standard ID1
(C0MSL5SID0)
(C0MSL5SID1)
CAN0 Message Slot 5 Extended ID0
CAN0 Message Slot 5 Extended ID1
(C0MSL5EID0)
(C0MSL5EID1)
CAN0 Message Slot 5 Extended ID2
CAN0 Message Slot 5 Data Length Register
(C0MSL5EID2)
(C0MSL5DLC)
CAN0 Message Slot 5 Data 0
CAN0 Message Slot 5 Data 1
(C0MSL5DT0)
(C0MSL5DT1)
CAN0 Message Slot 5 Data 2
CAN0 Message Slot 5 Data 3
(C0MSL5DT2)
(C0MSL5DT3)
CAN0 Message Slot 5 Data 4
CAN0 Message Slot 5 Data 5
(C0MSL5DT4)
(C0MSL5DT5)
CAN0 Message Slot 5 Data 6
CAN0 Message Slot 5 Data 7
(C0MSL5DT6)
(C0MSL5DT7)
CAN0 Message Slot 5 Timestamp
(C0MSL5TSP)
CAN0 Message Slot 6 Standard ID0
CAN0 Message Slot 6 Standard ID1
(C0MSL6SID0)
(C0MSL6SID1)
CAN0 Message Slot 6 Extended ID0
CAN0 Message Slot 6 Extended ID1
(C0MSL6EID0)
(C0MSL6EID1)
CAN0 Message Slot 6 Extended ID2
CAN0 Message Slot 6 Data Length Register
(C0MSL6EID2)
(C0MSL6DLC)
CAN0 Message Slot 6 Data 0
CAN0 Message Slot 6 Data 1
(C0MSL6DT0)
(C0MSL6DT1)
CAN0 Message Slot 6 Data 2
CAN0 Message Slot 6 Data 3
(C0MSL6DT2)
(C0MSL6DT3)
CAN0 Message Slot 6 Data 4
CAN0 Message Slot 6 Data 5
(C0MSL6DT4)
(C0MSL6DT5)
CAN0 Message Slot 6 Data 6
CAN0 Message Slot 6 Data 7
(C0MSL6DT6)
(C0MSL6DT7)
CAN0 Message Slot 6 Timestamp
(C0MSL6TSP)
13-6
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (4/11)
Address
+0 address
b0
H'0080 1170
H'0080 1172
H'0080 1174
H'0080 1176
H'0080 1178
H'0080 117A
H'0080 117C
H'0080 117E
H'0080 1180
H'0080 1182
H'0080 1184
H'0080 1186
H'0080 1188
H'0080 118A
H'0080 118C
H'0080 118E
H'0080 1190
H'0080 1192
H'0080 1194
H'0080 1196
H'0080 1198
H'0080 119A
H'0080 119C
H'0080 119E
H'0080 11A0
H'0080 11A2
H'0080 11A4
H'0080 11A6
H'0080 11A8
H'0080 11AA
H'0080 11AC
H'0080 11AE
+1 address
b7 b8
CAN0 Message Slot 7 Standard ID0
CAN0 Message Slot 7 Standard ID1
(C0MSL7SID0)
(C0MSL7SID1)
CAN0 Message Slot 7 Extended ID0
CAN0 Message Slot 7 Extended ID1
(C0MSL7EID0)
(C0MSL7EID1)
CAN0 Message Slot 7 Extended ID2
CAN0 Message Slot 7 Data Length Register
(C0MSL7EID2)
(C0MSL7DLC)
CAN0 Message Slot 7 Data 0
CAN0 Message Slot 7 Data 1
(C0MSL7DT0)
(C0MSL7DT1)
CAN0 Message Slot 7 Data 2
CAN0 Message Slot 7 Data 3
(C0MSL7DT2)
(C0MSL7DT3)
CAN0 Message Slot 7 Data 4
CAN0 Message Slot 7 Data 5
(C0MSL7DT4)
(C0MSL7DT5)
CAN0 Message Slot 7 Data 6
CAN0 Message Slot 7 Data 7
(C0MSL7DT6)
(C0MSL7DT7)
CAN0 Message Slot 7 Timestamp
(C0MSL7TSP)
CAN0 Message Slot 8 Standard ID0
CAN0 Message Slot 8 Standard ID1
(C0MSL8SID0)
(C0MSL8SID1)
CAN0 Message Slot 8 Extended ID0
CAN0 Message Slot 8 Extended ID1
(C0MSL8EID0)
(C0MSL8EID1)
CAN0 Message Slot 8 Extended ID2
CAN0 Message Slot 8 Data Length Register
(C0MSL8EID2)
(C0MSL8DLC)
CAN0 Message Slot 8 Data 0
CAN0 Message Slot 8 Data 1
(C0MSL8DT0)
(C0MSL8DT1)
CAN0 Message Slot 8 Data 2
CAN0 Message Slot 8 Data 3
(C0MSL8DT2)
(C0MSL8DT3)
CAN0 Message Slot 8 Data 4
CAN0 Message Slot 8 Data 5
(C0MSL8DT4)
(C0MSL8DT5)
CAN0 Message Slot 8 Data 6
CAN0 Message Slot 8 Data 7
(C0MSL8DT6)
(C0MSL8DT7)
CAN0 Message Slot 8 Timestamp
(C0MSL8TSP)
CAN0 Message Slot 9 Standard ID0
CAN0 Message Slot 9 Standard ID1
(C0MSL9SID0)
(C0MSL9SID1)
CAN0 Message Slot 9 Extended ID0
CAN0 Message Slot 9 Extended ID1
(C0MSL9EID0)
(C0MSL9EID1)
CAN0 Message Slot 9 Extended ID2
CAN0 Message Slot 9 Data Length Register
(C0MSL9EID2)
(C0MSL9DLC)
CAN0 Message Slot 9 Data 0
CAN0 Message Slot 9 Data 1
(C0MSL9DT0)
(C0MSL9DT1)
CAN0 Message Slot 9 Data 2
CAN0 Message Slot 9 Data 3
(C0MSL9DT2)
(C0MSL9DT3)
CAN0 Message Slot 9 Data 4
CAN0 Message Slot 9 Data 5
(C0MSL9DT4)
(C0MSL9DT5)
CAN0 Message Slot 9 Data 6
CAN0 Message Slot 9 Data 7
(C0MSL9DT6)
(C0MSL9DT7)
CAN0 Message Slot 9 Timestamp
(C0MSL9TSP)
CAN0 Message Slot 10 Standard ID0
CAN0 Message Slot 10 Standard ID1
(C0MSL10SID0)
(C0MSL10SID1)
CAN0 Message Slot 10 Extended ID0
CAN0 Message Slot 10 Extended ID1
(C0MSL10EID0)
(C0MSL10EID1)
CAN0 Message Slot 10 Extended ID2
CAN0 Message Slot 10 Data Length Register
(C0MSL10EID2)
(C0MSL10DLC)
CAN0 Message Slot 10 Data 0
CAN0 Message Slot 10 Data 1
(C0MSL10DT0)
(C0MSL10DT1)
CAN0 Message Slot 10 Data 2
CAN0 Message Slot 10 Data 3
(C0MSL10DT2)
(C0MSL10DT3)
CAN0 Message Slot 10 Data 4
CAN0 Message Slot 10 Data 5
(C0MSL10DT4)
(C0MSL10DT5)
CAN0 Message Slot 10 Data 6
CAN0 Message Slot 10 Data 7
(C0MSL10DT6)
(C0MSL10DT7)
CAN0 Message Slot 10 Timestamp
(C0MSL10TSP)
13-7
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (5/11)
Address
+0 address
b0
H'0080 11B0
H'0080 11B2
H'0080 11B4
H'0080 11B6
H'0080 11B8
H'0080 11BA
H'0080 11BC
H'0080 11BE
H'0080 11C0
H'0080 11C2
H'0080 11C4
H'0080 11C6
H'0080 11C8
H'0080 11CA
H'0080 11CC
H'0080 11CE
H'0080 11D0
H'0080 11D2
H'0080 11D4
H'0080 11D6
H'0080 11D8
H'0080 11DA
H'0080 11DC
H'0080 11DE
H'0080 11E0
H'0080 11E2
H'0080 11E4
H'0080 11E6
H'0080 11E8
H'0080 11EA
H'0080 11EC
H'0080 11EE
+1 address
b7 b8
CAN0 Message Slot 11 Standard ID0
CAN0 Message Slot 11 Standard ID1
(C0MSL11SID0)
(C0MSL11SID1)
CAN0 Message Slot 11 Extended ID0
CAN0 Message Slot 11 Extended ID1
(C0MSL11EID0)
(C0MSL11EID1)
CAN0 Message Slot 11 Extended ID2
CAN0 Message Slot 11 Data Length Register
(C0MSL11EID2)
(C0MSL11DLC)
CAN0 Message Slot 11 Data 0
CAN0 Message Slot 11 Data 1
(C0MSL11DT0)
(C0MSL11DT1)
CAN0 Message Slot 11 Data 2
CAN0 Message Slot 11 Data 3
(C0MSL11DT2)
(C0MSL11DT3)
CAN0 Message Slot 11 Data 4
CAN0 Message Slot 11 Data 5
(C0MSL11DT4)
(C0MSL11DT5)
CAN0 Message Slot 11 Data 6
CAN0 Message Slot 11 Data 7
(C0MSL11DT6)
(C0MSL11DT7)
CAN0 Message Slot 11 Timestamp
(C0MSL11TSP)
CAN0 Message Slot 12 Standard ID0
CAN0 Message Slot 12 Standard ID1
(C0MSL12SID0)
(C0MSL12SID1)
CAN0 Message Slot 12 Extended ID0
CAN0 Message Slot 12 Extended ID1
(C0MSL12EID0)
(C0MSL12EID1)
CAN0 Message Slot 12 Extended ID2
CAN0 Message Slot 12 Data Length Register
(C0MSL12EID2)
(C0MSL12DLC)
CAN0 Message Slot 12 Data 0
CAN0 Message Slot 12 Data 1
(C0MSL12DT0)
(C0MSL12DT1)
CAN0 Message Slot 12 Data 2
CAN0 Message Slot 12 Data 3
(C0MSL12DT2)
(C0MSL12DT3)
CAN0 Message Slot 12 Data 4
CAN0 Message Slot 12 Data 5
(C0MSL12DT4)
(C0MSL12DT5)
CAN0 Message Slot 12 Data 6
CAN0 Message Slot 12 Data 7
(C0MSL12DT6)
(C0MSL12DT7)
CAN0 Message Slot 12 Timestamp
(C0MSL12TSP)
CAN0 Message Slot 13 Standard ID0
CAN0 Message Slot 13 Standard ID1
(C0MSL13SID0)
(C0MSL13SID1)
CAN0 Message Slot 13 Extended ID0
CAN0 Message Slot 13 Extended ID1
(C0MSL13EID0)
(C0MSL13EID1)
CAN0 Message Slot 13 Extended ID2
CAN0 Message Slot 13 Data Length Register
(C0MSL13EID2)
(C0MSL13DLC)
CAN0 Message Slot 13 Data 0
CAN0 Message Slot 13 Data 1
(C0MSL13DT0)
(C0MSL13DT1)
CAN0 Message Slot 13 Data 2
CAN0 Message Slot 13 Data 3
(C0MSL13DT2)
(C0MSL13DT3)
CAN0 Message Slot 13 Data 4
CAN0 Message Slot 13 Data 5
(C0MSL13DT4)
(C0MSL13DT5)
CAN0 Message Slot 13 Data 6
CAN0 Message Slot 13 Data 7
(C0MSL13DT6)
(C0MSL13DT7)
CAN0 Message Slot 13 Timestamp
(C0MSL13TSP)
CAN0 Message Slot 14 Standard ID0
CAN0 Message Slot 14 Standard ID1
(C0MSL14SID0)
(C0MSL14SID1)
CAN0 Message Slot 14 Extended ID0
CAN0 Message Slot 14 Extended ID1
(C0MSL14EID0)
(C0MSL14EID1)
CAN0 Message Slot 14 Extended ID2
CAN0 Message Slot 14 Data Length Register
(C0MSL14EID2)
(C0MSL14DLC)
CAN0 Message Slot 14 Data 0
CAN0 Message Slot 14 Data 1
(C0MSL14DT0)
(C0MSL14DT1)
CAN0 Message Slot 14 Data 2
CAN0 Message Slot 14 Data 3
(C0MSL14DT2)
(C0MSL14DT3)
CAN0 Message Slot 14 Data 4
CAN0 Message Slot 14 Data 5
(C0MSL14DT4)
(C0MSL14DT5)
CAN0 Message Slot 14 Data 6
CAN0 Message Slot 14 Data 7
(C0MSL14DT6)
(C0MSL14DT7)
CAN0 Message Slot 14 Timestamp
(C0MSL14TSP)
13-8
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (6/11)
Address
+0 address
b0
H'0080 11F0
H'0080 11F2
H'0080 11F4
H'0080 11F6
H'0080 11F8
H'0080 11FA
H'0080 11FC
H'0080 11FE
|
H'0080 1400
H'0080 1402
H'0080 1404
H'0080 1406
H'0080 1408
H'0080 140A
H'0080 140C
H'0080 140E
H'0080 1410
H'0080 1412
H'0080 1414
H'0080 1416
H'0080 1418
|
H'0080 1428
H'0080 142A
H'0080 142C
H'0080 142E
H'0080 1430
H'0080 1432
H'0080 1434
H'0080 1436
H'0080 1438
H'0080 143A
H'0080 143C
H'0080 143E
+1 address
b7 b8
See pages
b15
CAN0 Message Slot 15 Standard ID0
CAN0 Message Slot 15 Standard ID1
(C0MSL15SID0)
(C0MSL15SID1)
CAN0 Message Slot 15 Extended ID0
CAN0 Message Slot 15 Extended ID1
(C0MSL15EID0)
(C0MSL15EID1)
CAN0 Message Slot 15 Extended ID2
CAN0 Message Slot 15 Data Length Register
(C0MSL15EID2)
(C0MSL15DLC)
CAN0 Message Slot 15 Data 0
CAN0 Message Slot 15 Data 1
(C0MSL15DT0)
(C0MSL15DT1)
CAN0 Message Slot 15 Data 2
CAN0 Message Slot 15 Data 3
(C0MSL15DT2)
(C0MSL15DT3)
CAN0 Message Slot 15 Data 4
CAN0 Message Slot 15 Data 5
(C0MSL15DT4)
(C0MSL15DT5)
CAN0 Message Slot 15 Data 6
CAN0 Message Slot 15 Data 7
(C0MSL15DT6)
(C0MSL15DT7)
CAN0 Message Slot 15 Timestamp
(C0MSL15TSP)
(Use inhibited area)
CAN1 Control Register
(CAN1CNT)
CAN1 Status Register
(CAN1STAT)
CAN1 Frame Format Select Register
(CAN1FFS)
CAN1 Configuration Register
(CAN1CONF)
CAN1 Timestamp Count Register
(CAN1TSTMP)
CAN1 Receive Error Count Register
CAN1 Transmit Error Count Register
(CAN1REC)
(CAN1TEC)
CAN1 Slot Interrupt Request Status Register
(CAN1SLIST)
(Use inhibited area)
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-15
13-18
13-21
13-22
13-24
13-25
13-29
CAN1 Slot Interrupt Request Enable Register
(CAN1SLIEN)
(Use inhibited area)
13-30
CAN1 Error Interrupt Request Status Register
CAN1 Error Interrupt Request Enable Register
(CAN1ERIST)
(CAN1ERIEN)
CAN1 Baud Rate Prescaler
CAN1 Cause of Error Register
(CAN1BRP)
(CAN1EF)
CAN1 Mode Register
(Use inhibited area)
(CAN1MOD)
(Use inhibited area)
13-31
13-32
13-26
13-45
13-46
CAN1 Global Mask Register Standard ID0
CAN1 Global Mask Register Standard ID1
(C1GMSKS0)
(C1GMSKS1)
CAN1 Global Mask Register Extended ID0
CAN1 Global Mask Register Extended ID1
(C1GMSKE0)
(C1GMSKE1)
CAN1 Global Mask Register Extended ID2
(Use inhibited area)
(C1GMSKE2)
(Use inhibited area)
13-48
13-49
13-50
CAN1 Local Mask Register A Standard ID0
CAN1 Local Mask Register A Standard ID1
(C1LMSKAS0)
(C1LMSKAS1)
CAN1 Local Mask Register A Extended ID0
CAN1 Local Mask Register A Extended ID1
(C1LMSKAE0)
(C1LMSKAE1)
CAN1 Local Mask Register A Extended ID2
(Use inhibited area)
(C1LMSKAE2)
(Use inhibited area)
13-48
CAN1 Local Mask Register B Standard ID0
CAN1 Local Mask Register B Standard ID1
(C1LMSKBS0)
(C1LMSKBS1)
CAN1 Local Mask Register B Extended ID0
CAN1 Local Mask Register B Extended ID1
(C1LMSKBE0)
(C1LMSKBE1)
CAN1 Local Mask Register B Extended ID2
(Use inhibited area)
(C1LMSKBE2)
(Use inhibited area)
13-48
13-9
13-49
13-50
13-49
13-50
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (7/11)
Address
+0 address
b0
H'0080 1440
H'0080 1442
H'0080 1444
H'0080 1446
H'0080 1448
|
H'0080 1450
H'0080 1452
H'0080 1454
H'0080 1456
H'0080 1458
H'0080 145A
H'0080 145C
H'0080 145E
|
H'0080 1500
H'0080 1502
H'0080 1504
H'0080 1506
H'0080 1508
H'0080 150A
H'0080 150C
H'0080 150E
H'0080 1510
H'0080 1512
H'0080 1514
H'0080 1516
H'0080 1518
H'0080 151A
H'0080 151C
H'0080 151E
+1 address
b7 b8
CAN1 Single-Shot Mode Control Register
(CAN1SSMODE)
(Use inhibited area)
See pages
b15
13-52
CAN1 Single-Shot Interrupt Request Status Register
(CAN1SSIST)
(Use inhibited area)
13-33
CAN1 Single-Shot Interrupt Request Enable Register
(CAN1SSIEN)
(Use inhibited area)
13-34
CAN1 Message Slot 0 Control Register
CAN1 Message Slot 1 Control Register
(C1MSL0CNT)
(C1MSL1CNT)
CAN1 Message Slot 2 Control Register
CAN1 Message Slot 3 Control Register
(C1MSL2CNT)
(C1MSL3CNT)
CAN1 Message Slot 4 Control Register
CAN1 Message Slot 5 Control Register
(C1MSL4CNT)
(C1MSL5CNT)
CAN1 Message Slot 6 Control Register
CAN1 Message Slot 7 Control Register
(C1MSL6CNT)
(C1MSL7CNT)
CAN1 Message Slot 8 Control Register
CAN1 Message Slot 9 Control Register
(C1MSL8CNT)
(C1MSL9CNT)
CAN1 Message Slot 10 Control Register
CAN1 Message Slot 11 Control Register
(C1MSL10CNT)
(C1MSL11CNT)
CAN1 Message Slot 12 Control Register
CAN1 Message Slot 13 Control Register
(C1MSL12CNT)
(C1MSL13CNT)
CAN1 Message Slot 14 Control Register
CAN1 Message Slot 15 Control Register
(C1MSL14CNT)
(C1MSL15CNT)
(Use inhibited area)
13-53
CAN1 Message Slot 0 Standard ID0
CAN1 Message Slot 0 Standard ID1
(C1MSL0SID0)
(C1MSL0SID1)
CAN1 Message Slot 0 Extended ID0
CAN1 Message Slot 0 Extended ID1
(C1MSL0EID0)
(C1MSL0EID1)
CAN1 Message Slot 0 Extended ID2
CAN1 Message Slot 0 Data Length Register
(C1MSL0EID2)
(C1MSL0DLC)
CAN1 Message Slot 0 Data 0
CAN1 Message Slot 0 Data 1
(C1MSL0DT0)
(C1MSL0DT1)
CAN1 Message Slot 0 Data 2
CAN1 Message Slot 0 Data 3
(C1MSL0DT2)
(C1MSL0DT3)
CAN1 Message Slot 0 Data 4
CAN1 Message Slot 0 Data 5
(C1MSL0DT4)
(C1MSL0DT5)
CAN1 Message Slot 0 Data 6
CAN1 Message Slot 0 Data 7
(C1MSL0DT6)
(C1MSL0DT7)
CAN1 Message Slot 0 Timestamp
(C1MSL0TSP)
CAN1 Message Slot 1 Standard ID0
CAN1 Message Slot 1 Standard ID1
(C1MSL1SID0)
(C1MSL1SID1)
CAN1 Message Slot 1 Extended ID0
CAN1 Message Slot 1 Extended ID1
(C1MSL1EID0)
(C1MSL1EID1)
CAN1 Message Slot 1 Extended ID2
CAN1 Message Slot 1 Data Length Register
(C1MSL1EID2)
(C1MSL1DLC)
CAN1 Message Slot 1 Data 0
CAN1 Message Slot 1 Data 1
(C1MSL1DT0)
(C1MSL1DT1)
CAN1 Message Slot 1 Data 2
CAN1 Message Slot 1 Data 3
(C1MSL1DT2)
(C1MSL1DT3)
CAN1 Message Slot 1 Data 4
CAN1 Message Slot 1 Data 5
(C1MSL1DT4)
(C1MSL1DT5)
CAN1 Message Slot 1 Data 6
CAN1 Message Slot 1 Data 7
(C1MSL1DT6)
(C1MSL1DT7)
CAN1 Message Slot 1 Timestamp
(C1MSL1TSP)
13-10
13-53
13-53
13-53
13-53
13-53
13-53
13-53
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (8/11)
Address
+0 address
b0
H'0080 1520
H'0080 1522
H'0080 1524
H'0080 1526
H'0080 1528
H'0080 152A
H'0080 152C
H'0080 152E
H'0080 1530
H'0080 1532
H'0080 1534
H'0080 1536
H'0080 1538
H'0080 153A
H'0080 153C
H'0080 153E
H'0080 1540
H'0080 1542
H'0080 1544
H'0080 1546
H'0080 1548
H'0080 154A
H'0080 154C
H'0080 154E
H'0080 1550
H'0080 1552
H'0080 1554
H'0080 1556
H'0080 1558
H'0080 155A
H'0080 155C
H'0080 155E
+1 address
b7 b8
CAN1 Message Slot 2 Standard ID0
CAN1 Message Slot 2 Standard ID1
(C1MSL2SID0)
(C1MSL2SID1)
CAN1 Message Slot 2 Extended ID0
CAN1 Message Slot 2 Extended ID1
(C1MSL2EID0)
(C1MSL2EID1)
CAN1 Message Slot 2 Extended ID2
CAN1 Message Slot 2 Data Length Register
(C1MSL2EID2)
(C1MSL2DLC)
CAN1 Message Slot 2 Data 0
CAN1 Message Slot 2 Data 1
(C1MSL2DT0)
(C1MSL2DT1)
CAN1 Message Slot 2 Data 2
CAN1 Message Slot 2 Data 3
(C1MSL2DT2)
(C1MSL2DT3)
CAN1 Message Slot 2 Data 4
CAN1 Message Slot 2 Data 5
(C1MSL2DT4)
(C1MSL2DT5)
CAN1 Message Slot 2 Data 6
CAN1 Message Slot 2 Data 7
(C1MSL2DT6)
(C1MSL2DT7)
CAN1 Message Slot 2 Timestamp
(C1MSL2TSP)
CAN1 Message Slot 3 Standard ID0
CAN1 Message Slot 3 Standard ID1
(C1MSL3SID0)
(C1MSL3SID1)
CAN1 Message Slot 3 Extended ID0
CAN1 Message Slot 3 Extended ID1
(C1MSL3EID0)
(C1MSL3EID1)
CAN1 Message Slot 3 Extended ID2
CAN1 Message Slot 3 Data Length Register
(C1MSL3EID2)
(C1MSL3DLC)
CAN1 Message Slot 3 Data 0
CAN1 Message Slot 3 Data 1
(C1MSL3DT0)
(C1MSL3DT1)
CAN1 Message Slot 3 Data 2
CAN1 Message Slot 3 Data 3
(C1MSL3DT2)
(C1MSL3DT3)
CAN1 Message Slot 3 Data 4
CAN1 Message Slot 3 Data 5
(C1MSL3DT4)
(C1MSL3DT5)
CAN1 Message Slot 3 Data 6
CAN1 Message Slot 3 Data 7
(C1MSL3DT6)
(C1MSL3DT7)
CAN1 Message Slot 3 Timestamp
(C1MSL3TSP)
CAN1 Message Slot 4 Standard ID0
CAN1 Message Slot 4 Standard ID1
(C1MSL4SID0)
(C1MSL4SID1)
CAN1 Message Slot 4 Extended ID0
CAN1 Message Slot 4 Extended ID1
(C1MSL4EID0)
(C1MSL4EID1)
CAN1 Message Slot 4 Extended ID2
CAN1 Message Slot 4 Data Length Register
(C1MSL4EID2)
(C1MSL4DLC)
CAN1 Message Slot 4 Data 0
CAN1 Message Slot 4 Data 1
(C1MSL4DT0)
(C1MSL4DT1)
CAN1 Message Slot 4 Data 2
CAN1 Message Slot 4 Data 3
(C1MSL4DT2)
(C1MSL4DT3)
CAN1 Message Slot 4 Data 4
CAN1 Message Slot 4 Data 5
(C1MSL4DT4)
(C1MSL4DT5)
CAN1 Message Slot 4 Data 6
CAN1 Message Slot 4 Data 7
(C1MSL4DT6)
(C1MSL4DT7)
CAN1 Message Slot 4 Timestamp
(C1MSL4TSP)
CAN1 Message Slot 5 Standard ID0
CAN1 Message Slot 5 Standard ID1
(C1MSL5SID0)
(C1MSL5SID1)
CAN1 Message Slot 5 Extended ID0
CAN1 Message Slot 5 Extended ID1
(C1MSL5EID0)
(C1MSL5EID1)
CAN1 Message Slot 5 Extended ID2
CAN1 Message Slot 5 Data Length Register
(C1MSL5EID2)
(C1MSL5DLC)
CAN1 Message Slot 5 Data 0
CAN1 Message Slot 5 Data 1
(C1MSL5DT0)
(C1MSL5DT1)
CAN1 Message Slot 5 Data 2
CAN1 Message Slot 5 Data 3
(C1MSL5DT2)
(C1MSL5DT3)
CAN1 Message Slot 5 Data 4
CAN1 Message Slot 5 Data 5
(C1MSL5DT4)
(C1MSL5DT5)
CAN1 Message Slot 5 Data 6
CAN1 Message Slot 5 Data 7
(C1MSL5DT6)
(C1MSL5DT7)
CAN1 Message Slot 5 Timestamp
(C1MSL5TSP)
13-11
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (9/11)
Address
+0 address
b0
H'0080 1560
H'0080 1562
H'0080 1564
H'0080 1566
H'0080 1568
H'0080 156A
H'0080 156C
H'0080 156E
H'0080 1570
H'0080 1572
H'0080 1574
H'0080 1576
H'0080 1578
H'0080 157A
H'0080 157C
H'0080 157E
H'0080 1580
H'0080 1582
H'0080 1584
H'0080 1586
H'0080 1588
H'0080 158A
H'0080 158C
H'0080 158E
H'0080 1590
H'0080 1592
H'0080 1594
H'0080 1596
H'0080 1598
H'0080 159A
H'0080 159C
H'0080 159E
+1 address
b7 b8
CAN1 Message Slot 6 Standard ID0
CAN1 Message Slot 6 Standard ID1
(C1MSL6SID0)
(C1MSL6SID1)
CAN1 Message Slot 6 Extended ID0
CAN1 Message Slot 6 Extended ID1
(C1MSL6EID0)
(C1MSL6EID1)
CAN1 Message Slot 6 Extended ID2
CAN1 Message Slot 6 Data Length Register
(C1MSL6EID2)
(C1MSL6DLC)
CAN1 Message Slot 6 Data 0
CAN1 Message Slot 6 Data 1
(C1MSL6DT0)
(C1MSL6DT1)
CAN1 Message Slot 6 Data 2
CAN1 Message Slot 6 Data 3
(C1MSL6DT2)
(C1MSL6DT3)
CAN1 Message Slot 6 Data 4
CAN1 Message Slot 6 Data 5
(C1MSL6DT4)
(C1MSL6DT5)
CAN1 Message Slot 6 Data 6
CAN1 Message Slot 6 Data 7
(C1MSL6DT6)
(C1MSL6DT7)
CAN1 Message Slot 6 Timestamp
(C1MSL6TSP)
CAN1 Message Slot 7 Standard ID0
CAN1 Message Slot 7 Standard ID1
(C1MSL7SID0)
(C1MSL7SID1)
CAN1 Message Slot 7 Extended ID0
CAN1 Message Slot 7 Extended ID1
(C1MSL7EID0)
(C1MSL7EID1)
CAN1 Message Slot 7 Extended ID2
CAN1 Message Slot 7 Data Length Register
(C1MSL7EID2)
(C1MSL7DLC)
CAN1 Message Slot 7 Data 0
CAN1 Message Slot 7 Data 1
(C1MSL7DT0)
(C1MSL7DT1)
CAN1 Message Slot 7 Data 2
CAN1 Message Slot 7 Data 3
(C1MSL7DT2)
(C1MSL7DT3)
CAN1 Message Slot 7 Data 4
CAN1 Message Slot 7 Data 5
(C1MSL7DT4)
(C1MSL7DT5)
CAN1 Message Slot 7 Data 6
CAN1 Message Slot 7 Data 7
(C1MSL7DT6)
(C1MSL7DT7)
CAN1 Message Slot 7 Timestamp
(C1MSL7TSP)
CAN1 Message Slot 8 Standard ID0
CAN1 Message Slot 8 Standard ID1
(C1MSL8SID0)
(C1MSL8SID1)
CAN1 Message Slot 8 Extended ID0
CAN1 Message Slot 8 Extended ID1
(C1MSL8EID0)
(C1MSL8EID1)
CAN1 Message Slot 8 Extended ID2
CAN1 Message Slot 8 Data Length Register
(C1MSL8EID2)
(C1MSL8DLC)
CAN1 Message Slot 8 Data 0
CAN1 Message Slot 8 Data 1
(C1MSL8DT0)
(C1MSL8DT1)
CAN1 Message Slot 8 Data 2
CAN1 Message Slot 8 Data 3
(C1MSL8DT2)
(C1MSL8DT3)
CAN1 Message Slot 8 Data 4
CAN1 Message Slot 8 Data 5
(C1MSL8DT4)
(C1MSL8DT5)
CAN1 Message Slot 8 Data 6
CAN1 Message Slot 8 Data 7
(C1MSL8DT6)
(C1MSL8DT7)
CAN1 Message Slot 8 Timestamp
(C1MSL8TSP)
CAN1 Message Slot 9 Standard ID0
CAN1 Message Slot 9 Standard ID1
(C1MSL9SID0)
(C1MSL9SID1)
CAN1 Message Slot 9 Extended ID0
CAN1 Message Slot 9 Extended ID1
(C1MSL9EID0)
(C1MSL9EID1)
CAN1 Message Slot 9 Extended ID2
CAN1 Message Slot 9 Data Length Register
(C1MSL9EID2)
(C1MSL9DLC)
CAN1 Message Slot 9 Data 0
CAN1 Message Slot 9 Data 1
(C1MSL9DT0)
(C1MSL9DT1)
CAN1 Message Slot 9 Data 2
CAN1 Message Slot 9 Data 3
(C1MSL9DT2)
(C1MSL9DT3)
CAN1 Message Slot 9 Data 4
CAN1 Message Slot 9 Data 5
(C1MSL9DT4)
(C1MSL9DT5)
CAN1 Message Slot 9 Data 6
CAN1 Message Slot 9 Data 7
(C1MSL9DT6)
(C1MSL9DT7)
CAN1 Message Slot 9 Timestamp
(C1MSL9TSP)
13-12
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (10/11)
Address
+0 address
b0
H'0080 15A0
H'0080 15A2
H'0080 15A4
H'0080 15A6
H'0080 15A8
H'0080 15AA
H'0080 15AC
H'0080 15AE
H'0080 15B0
H'0080 15B2
H'0080 15B4
H'0080 15B6
H'0080 15B8
H'0080 15BA
H'0080 15BC
H'0080 15BE
H'0080 15C0
H'0080 15C2
H'0080 15C4
H'0080 15C6
H'0080 15C8
H'0080 15CA
H'0080 15CC
H'0080 15CE
H'0080 15D0
H'0080 15D2
H'0080 15D4
H'0080 15D6
H'0080 15D8
H'0080 15DA
H'0080 15DC
H'0080 15DE
+1 address
b7 b8
CAN1 Message Slot 10 Standard ID0
CAN1 Message Slot 10 Standard ID1
(C1MSL10SID0)
(C1MSL10SID1)
CAN1 Message Slot 10 Extended ID0
CAN1 Message Slot 10 Extended ID1
(C1MSL10EID0)
(C1MSL10EID1)
CAN1 Message Slot 10 Extended ID2
CAN1 Message Slot 10 Data Length Register
(C1MSL10EID2)
(C1MSL10DLC)
CAN1 Message Slot 10 Data 0
CAN1 Message Slot 10 Data 1
(C1MSL10DT0)
(C1MSL10DT1)
CAN1 Message Slot 10 Data 2
CAN1 Message Slot 10 Data 3
(C1MSL10DT2)
(C1MSL10DT3)
CAN1 Message Slot 10 Data 4
CAN1 Message Slot 10 Data 5
(C1MSL10DT4)
(C1MSL10DT5)
CAN1 Message Slot 10 Data 6
CAN1 Message Slot 10 Data 7
(C1MSL10DT6)
(C1MSL10DT7)
CAN1 Message Slot 10 Timestamp
(C1MSL10TSP)
CAN1 Message Slot 11 Standard ID0
CAN1 Message Slot 11 Standard ID1
(C1MSL11SID0)
(C1MSL11SID1)
CAN1 Message Slot 11 Extended ID0
CAN1 Message Slot 11 Extended ID1
(C1MSL11EID0)
(C1MSL11EID1)
CAN1 Message Slot 11 Extended ID2
CAN1 Message Slot 11 Data Length Register
(C1MSL11EID2)
(C1MSL11DLC)
CAN1 Message Slot 11 Data 0
CAN1 Message Slot 11 Data 1
(C1MSL11DT0)
(C1MSL11DT1)
CAN1 Message Slot 11 Data 2
CAN1 Message Slot 11 Data 3
(C1MSL11DT2)
(C1MSL11DT3)
CAN1 Message Slot 11 Data 4
CAN1 Message Slot 11 Data 5
(C1MSL11DT4)
(C1MSL11DT5)
CAN1 Message Slot 11 Data 6
CAN1 Message Slot 11 Data 7
(C1MSL11DT6)
(C1MSL11DT7)
CAN1 Message Slot 11 Timestamp
(C1MSL11TSP)
CAN1 Message Slot 12 Standard ID0
CAN1 Message Slot 12 Standard ID1
(C1MSL12SID0)
(C1MSL12SID1)
CAN1 Message Slot 12 Extended ID0
CAN1 Message Slot 12 Extended ID1
(C1MSL12EID0)
(C1MSL12EID1)
CAN1 Message Slot 12 Extended ID2
CAN1 Message Slot 12 Data Length Register
(C1MSL12EID2)
(C1MSL12DLC)
CAN1 Message Slot 12 Data 0
CAN1 Message Slot 12 Data 1
(C1MSL12DT0)
(C1MSL12DT1)
CAN1 Message Slot 12 Data 2
CAN1 Message Slot 12 Data 3
(C1MSL12DT2)
(C1MSL12DT3)
CAN1 Message Slot 12 Data 4
CAN1 Message Slot 12 Data 5
(C1MSL12DT4)
(C1MSL12DT5)
CAN1 Message Slot 12 Data 6
CAN1 Message Slot 12 Data 7
(C1MSL12DT6)
(C1MSL12DT7)
CAN1 Message Slot 12 Timestamp
(C1MSL12TSP)
CAN1 Message Slot 13 Standard ID0
CAN1 Message Slot 13 Standard ID1
(C1MSL13SID0)
(C1MSL13SID1)
CAN1 Message Slot 13 Extended ID0
CAN1 Message Slot 13 Extended ID1
(C1MSL13EID0)
(C1MSL13EID1)
CAN1 Message Slot 13 Extended ID2
CAN1 Message Slot 13 Data Length Register
(C1MSL13EID2)
(C1MSL13DLC)
CAN1 Message Slot 13 Data 0
CAN1 Message Slot 13 Data 1
(C1MSL13DT0)
(C1MSL13DT1)
CAN1 Message Slot 13 Data 2
CAN1 Message Slot 13 Data 3
(C1MSL13DT2)
(C1MSL13DT3)
CAN1 Message Slot 13 Data 4
CAN1 Message Slot 13 Data 5
(C1MSL13DT4)
(C1MSL13DT5)
CAN1 Message Slot 13 Data 6
CAN1 Message Slot 13 Data 7
(C1MSL13DT6)
(C1MSL13DT7)
CAN1 Message Slot 13 Timestamp
(C1MSL13TSP)
13-13
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN Module Related Register Map (11/11)
Address
+0 address
b0
H'0080 15E0
H'0080 15E2
H'0080 15E4
H'0080 15E6
H'0080 15E8
H'0080 15EA
H'0080 15EC
H'0080 15EE
H'0080 15F0
H'0080 15F2
H'0080 15F4
H'0080 15F6
H'0080 15F8
H'0080 15FA
H'0080 15FC
H'0080 15FE
+1 address
b7 b8
CAN1 Message Slot 14 Standard ID0
CAN1 Message Slot 14 Standard ID1
(C1MSL14SID0)
(C1MSL14SID1)
CAN1 Message Slot 14 Extended ID0
CAN1 Message Slot 14 Extended ID1
(C1MSL14EID0)
(C1MSL14EID1)
CAN1 Message Slot 14 Extended ID2
CAN1 Message Slot 14 Data Length Register
(C1MSL14EID2)
(C1MSL14DLC)
CAN1 Message Slot 14 Data 0
CAN1 Message Slot 14 Data 1
(C1MSL14DT0)
(C1MSL14DT1)
CAN1 Message Slot 14 Data 2
CAN1 Message Slot 14 Data 3
(C1MSL14DT2)
(C1MSL14DT3)
CAN1 Message Slot 14 Data 4
CAN1 Message Slot 14 Data 5
(C1MSL14DT4)
(C1MSL14DT5)
CAN1 Message Slot 14 Data 6
CAN1 Message Slot 14 Data 7
(C1MSL14DT6)
(C1MSL14DT7)
CAN1 Message Slot 14 Timestamp
(C1MSL14TSP)
CAN1 Message Slot 15 Standard ID0
CAN1 Message Slot 15 Standard ID1
(C1MSL15SID0)
(C1MSL15SID1)
CAN1 Message Slot 15 Extended ID0
CAN1 Message Slot 15 Extended ID1
(C1MSL15EID0)
(C1MSL15EID1)
CAN1 Message Slot 15 Extended ID2
CAN1 Message Slot 15 Data Length Register
(C1MSL15EID2)
(C1MSL15DLC)
CAN1 Message Slot 15 Data 0
CAN1 Message Slot 15 Data 1
(C1MSL15DT0)
(C1MSL15DT1)
CAN1 Message Slot 15 Data 2
CAN1 Message Slot 15 Data 3
(C1MSL15DT2)
(C1MSL15DT3)
CAN1 Message Slot 15 Data 4
CAN1 Message Slot 15 Data 5
(C1MSL15DT4)
(C1MSL15DT5)
CAN1 Message Slot 15 Data 6
CAN1 Message Slot 15 Data 7
(C1MSL15DT6)
(C1MSL15DT7)
CAN1 Message Slot 15 Timestamp
(C1MSL15TSP)
13-14
See pages
b15
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
13-65
13-66
13-67
13-68
13-69
13-70
13-71
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
13.2.1 CAN Control Registers
CAN0 Control Register (CAN0CNT)
CAN1 Control Register (CAN1CNT)
b0
0
1
0
2
0
3
0
<Address: H’0080 1000>
<Address: H’0080 1400>
4
5
RBO
TSR
0
0
6
7
8
9
10
TSP
0
0
0
0
0
11
12
FRST
BCM
1
0
13
0
14
b15
LBM
RST
0
1
<After reset: H’0011>
b
Bit Name
0–3
No function assigned. Fix to "0".
Function
R
W
0
0
4
RBO
Return bus off bit
0: Enable normal operation
1: Request clearing of error counter
R(Note 1)
5
TSR
Timestamp counter reset bit
0: Enable count operation
1: Initialize count (to H’0000)
R(Note 1)
6–7
TSP
Timestamp prescaler bit
00: Select CAN bus bit clock
01: Select CAN bus bit clock divided by 2
10: Select CAN bus bit clock divided by 3
R
W
0
0
0: Negate reset
1: Forcibly reset
R
W
BCM
0: Disable BasicCAN mode
R
W
BasicCAN mode bit
1: BasicCAN mode
0
0
11: Select CAN bus bit clock divided by 4
8-10
No function assigned. Fix to "0".
11
FRST
Forcible reset bit
12
13
No function assigned. Fix to "0".
14
LBM
Loopback mode bit
0: Disable loopback function
1: Enable loopback function
R
W
15
RST
CAN reset bit
0: Negate reset
1: Request reset
R
W
Note 1: Only writing "1" is effective. Automatically cleared to "0" in hardware.
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13
13.2 CAN Module Related Registers
(1) RBO (Return Bus Off) bit (Bit 4)
Setting this bit to "1" clears the CAN Receive Error Count Register (CANnREC) and CAN Transmit Error
Count Register (CANnTEC) to H'00 and forcibly places the CAN module into an error active state. This bit is
cleared when the CAN module goes to an error active state.
Note: • Communication becomes possible when 11 consecutive recessive bits are detected on the
CAN bus after clearing the error counters.
(2) TSR (Timestamp Counter Reset) bit (Bit 5)
Setting this bit to "1" clears the value of the CAN Timestamp Count Register (CANnTSTMP) to H’0000. This
bit is cleared after the value of the CAN Timestamp Count Register (CANnTSTMP) is cleared to H’0000.
(3) TSP (Timestamp Prescaler) bits (Bits 6–7)
These bits select the count clock source for the timestamp counter.
Note: • Do not change settings of the TSP bits while CAN is operating (CAN Status Register CRS bit = "0").
(4) FRST (Forcible Reset) bit (Bit 11)
When the FRST bit is set to "1", the CAN module is separated from the CAN bus and the protocol control unit
is reset regardless of whether the CAN module currently is communicating. Up to 5 BCLK periods are required before the protocol control unit is reset after setting the FRST bit.
Notes: • In order for CAN communication to start, the FRST and RST bits must be cleared to "0".
• If the FRST bit is set to "1" during communication, the CTX pin output goes high immediately
after that. Therefore, setting the FRST bit to "1" while sending CAN frame may cause a CAN
bus error.
• The CAN Message Slot Control Register’s transmit/receive requests are not cleared for reasons that the FRST or RST bits are set.
• When the protocol control unit is reset by setting the FRST bit to "1", the CAN Timestamp
Count and CAN Transmit/Receive Error Count Registers are initialized to "0".
(5) BCM (BasicCAN Mode) bit (Bit 12)
By setting this bit to "1", the CAN module can be operated in BasicCAN mode.
• Operation during BasicCAN mode
During BasicCAN mode, two local slots—slots 14 and 15—are used as dual buffers, and the received
frames with matching ID are stored alternately in slots 14 and 15 by acceptance filtering. Used for this
acceptance filtering when slot 14 is active (next received frame to be stored in slot 14) are the ID set in
slot 14 and local mask A, and those when slot 15 is active are the ID set in slot 15 and local mask B. Two
types of frames—data frame and remote frame—can be received in this mode. By setting the same ID
and the same mask register value for the two slots, the possibility of loosing messages when, for
example, receiving frames which have many IDs may be reduced.
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13
13.2 CAN Module Related Registers
• Procedure for entering BasicCAN mode
Follow the procedure below during initialization:
1) Set the ID for slots 14 and 15 and the local mask registers A and B. (We recommend setting the same
value.)
2) Set the frame types to be handled by slots 14 and 15 (standard or extended) in the CAN Extended ID
Register. (We recommend setting the same type.)
3) Set the Message Slot Control Registers for slots 14 and 15 for data frame reception.
4) Set the BCM bit to "1".
Notes: • Do not change settings of the BCM bit while CAN is operating (CAN Status Register CRS
bit = "0").
• The first slot that is active after clearing the RST bit is slot 14.
• Even during BasicCAN mode, slots 0 to 13 can be used the same way as in normal
operation.
(6) LBM (Loopback Mode) bit (Bit 14)
When the LBM bit is set to "1", if a receive slot exists whose ID matches that of the frame sent by the CAN
module itself, then the frame can be received.
Notes: • ACK is not returned for the transmit frame.
• Do not change settings of the LBM bit while CAN is operating (CAN Status Register CRS bit = "0").
(7) RST (CAN Reset) bit (Bit 15)
When the RST bit is cleared to "0", the CAN module is connected to the CAN bus and becomes ready to
communicate after detecting 11 consecutive recessive bits. Also, the CAN Timestamp Count Register
thereby starts counting. When the RST bit is set to "1", the bus will enter an idle state after sending frames
from the slots which have transmit requests set by that time, then the protocol control unit is reset and the
CAN module is disconnected from the CAN bus. Frames received during this time are processed normally.
Notes: • It is inhibited to set a new transmit request until the CAN Status Register CRS bit is set to "1"
and the protocol control unit is reset after setting the RST bit to "1".
• When the protocol control unit is reset by setting the RST bit to "1", the CAN Timestamp Count
and CAN Transmit/Receive Error Count Registers are initialized to "0".
• In order for CAN communication to start, the FRST and RST bits must be cleared to "0".
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13
13.2 CAN Module Related Registers
13.2.2 CAN Status Registers
CAN0 Status Register (CAN0STAT)
CAN1 Status Register (CAN1STAT)
b0
0
1
2
3
4
BOS
EPS
CBS
BCS
0
0
0
0
<Address: H’0080 1002>
<Address: H’0080 1402>
5
0
6
7
8
9
10
11
LBS
CRS
RSB
TSB
RSC
TSC
0
1
0
0
0
0
12
13
14
b15
MSN
0
0
0
0
<After reset: H’0100>
b
Bit Name
0
No function assigned. Fix to "0".
1
BOS
Bus off status bit
2
3
Function
R
W
0
0
0: Not bus off
1: Bus off state
R
–
EPS
Error passive status bit
0: Not error passive
1: Error passive state
R
–
CBS
0: No error occurred
R
–
CAN bus error bit
1: Error occurred
4
BCS
BasicCAN mode status bit
0: Normal mode
1: BasicCAN mode
R
–
5
No function assigned. Fix to "0".
0
0
6
LBS
0: Normal mode
R
–
Loopback status bit
1: Loopback mode
7
CRS
CAN reset status bit
0: Operating
1: Reset
R
–
8
RSB
Receive status bit
0: Not receiving
1: Receiving
R
–
9
TSB
Transmit status bit
0: Not sending
1: Sending
R
–
10
RSC
0: Reception not completed
R
–
Reception completed status bit
1: Reception completed
11
TSC
Transmission completed status bit
0: Transmission not completed
1: Transmission completed
R
–
12–15
MSN
Message slot number bit
Number of the message slot which has finished
sending or receiving
0000: Slot 0
0001: Slot 1
0010: Slot 2
0011: Slot 3
0100: Slot 4
0101: Slot 5
0110: Slot 6
0111: Slot 7
1000: Slot 8
1001: Slot 9
1010: Slot 10
1011: Slot 11
1100: Slot 12
1101: Slot 13
1110: Slot 14
1111: Slot 15
R
–
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13
13.2 CAN Module Related Registers
(1) BOS (Bus Off Status) bit (Bit 1)
When BOS bit = "1", it means that the CAN module is in a bus off state.
[Set condition]
This bit is set to "1" when the transmit error count register value exceeded 255 and a bus off state is
entered.
[Clear condition]
This bit is cleared when restored from the bus off state.
(2) EPS (Error Passive Status) bit (Bit 2)
When EPS bit = "1", it means that the CAN module is in an error passive state.
[Set condition]
This bit is set to "1" when the transmit or receive error count register value exceeded 127 and an error
passive state is entered.
[Clear condition]
This bit is cleared when restored from the error passive state.
(3) CBS (CAN Bus Error) bit (Bit 3)
[Set condition]
This bit is set to "1" when an error is detected on the CAN bus.
[Clear condition]
This bit is cleared when the CAN module finished sending or receiving normally.
(4) BCS (BasicCAN Status) bit (Bit 4)
When BCS bit = "1", it means that the CAN module is operating in BasicCAN mode.
[Set condition]
This bit is set to "1" when the CAN module is operating in BasicCAN mode. BasicCAN mode is useful
when the following conditions are met:
• CAN Control Register BCM bit = "1"
• Slots 14 and 15 both are set for data frame reception
[Clear condition]
This bit is cleared by clearing the BCM bit to "0".
(5) LBS (Loopback Status) bit (Bit 6)
When LBS bit = "1", it means that the CAN module is operating in loopback mode.
[Set condition]
This bit is set to "1" by setting the CAN Control Register LBM (loopback mode) bit to "1".
[Clear condition]
This bit is cleared by clearing the LBM bit to "0".
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13.2 CAN Module Related Registers
(6) CRS (CAN Reset Status) bit (Bit 7)
When CRS bit = "1", it means that the protocol control unit is in a reset state.
[Set condition]
This bit is set to "1" when the CAN protocol control unit is in a reset state.
[Clear condition]
This bit is cleared by clearing the CAN Control Register RST (CAN reset) and FRST bits to "0".
(7) RSB (Receive Status) bit (Bit 8)
[Set condition]
This bit is set to "1" when the CAN module is operating as a receive node.
[Clear condition]
This bit is cleared when the CAN module starts operating as a transmit node or enters a bus idle state.
(8) TSB (Transmit Status) bit (Bit 9)
[Set condition]
This bit is set to "1" when the CAN module is operating as a transmit node.
[Clear condition]
This bit is cleared when the CAN module starts operating as a receive node or enters a bus idle state.
(9) RSC (Reception Completed Status) bit (Bit 10)
[Set condition]
This bit is set to "1" when the CAN module has finished receiving normally (regardless of whether there
is any slot that meets receive conditions).
[Clear condition]
This bit is cleared when the CAN module has finished sending normally.
(10) TSC (Transmission Completed Status) bit (Bit 11)
[Set condition]
This bit is set to "1" when the CAN module has finished sending normally.
[Clear condition]
This bit is cleared when the CAN module has finished receiving normally.
(11) MSN (Message Slot Number) bits (Bits 12–15)
These bits indicate the relevant slot number when the CAN module has finished sending or finished storing
the received data. These bits cannot be cleared to "0" in software.
Note: • When CAN module receives the frame that is transmitted by the CAN module itself during
loopback mode, the MSN bits indicate the transmit slot number.
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13
13.2 CAN Module Related Registers
13.2.3 CAN Frame Format Select Registers
CAN0 Frame Format Select Register (CAN0FFS)
CAN1 Frame Format Select Register (CAN1FFS)
b0
FFE0
0
<Address: H’0080 1004>
<Address: H’0080 1404>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
FFE1
FFE2
FFE3
FFE4
FFE5
FFE6
FFE7
FFE8
FFE9
FFE10
FFE11
FFE12
FFE13
FFE14
FFE15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
FFE0 (slot 0 extended format bit)
0: Standard ID format
R
W
1
FFE1 (slot 1 extended format bit)
1: Extended ID format
2
FFE2 (slot 2 extended format bit)
3
FFE3 (slot 3 extended format bit)
4
FFE4 (slot 4 extended format bit)
5
FFE5 (slot 5 extended format bit)
6
FFE6 (slot 6 extended format bit)
7
FFE7 (slot 7 extended format bit)
8
FFE8 (slot 8 extended format bit)
9
FFE9 (slot 9 extended format bit)
10
FFE10 (slot 10 extended format bit)
11
FFE11 (slot 11 extended format bit)
12
FFE12 (slot 12 extended format bit)
13
FFE13 (slot 13 extended format bit)
14
FFE14 (slot 14 extended format bit)
15
FFE15 (slot 15 extended format bit)
This register selects the format of frames handled by message slots corresponding to the respective bits in the
register. Setting any bit in this register to "0" selects the standard ID format, and setting any bit in this register to
"1" selects the extended ID format.
Note: • Settings of any bit in this register can only be changed when the corresponding slot does not
have transmit or receive requests set.
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13
13.2 CAN Module Related Registers
13.2.4 CAN Configuration Registers
CAN0 Configuration Register (CAN0CONF)
CAN1 Configuration Register (CAN1CONF)
b0
1
2
SJW
0
3
4
5
PH2
0
0
0
<Address: H'0080 1006>
<Address: H'0080 1406>
6
7
8
9
PH1
0
0
0
10
11
PRB
0
0
0
12
13
14
0
0
0
b15
SAM
0
0
0
<After reset: H’0000>
b
Bit Name
Function
0–1
SJW
reSynchronization Jump Width setting bit
00:
01:
10:
11:
R
W
R
W
2–4
PH2
Phase Segment2 setting bit
000: Phase Segment2
001: Phase Segment2
010: Phase Segment2
011: Phase Segment2
100: Phase Segment2
101: Phase Segment2
110: Phase Segment2
111: Phase Segment2
=
=
=
=
=
=
=
=
1Tq
2Tq
3Tq
4Tq
5Tq
6Tq
7Tq
8Tq
R
W
5–7
PH1
Phase Segment1 setting bit
000: Phase Segment1
001: Phase Segment1
010: Phase Segment1
011: Phase Segment1
100: Phase Segment1
101: Phase Segment1
110: Phase Segment1
=
=
=
=
=
=
=
1Tq
2Tq
3Tq
4Tq
5Tq
6Tq
7Tq
R
W
8–10
PRB
Propagation Segment setting bit
000: Propagation Segment = 1Tq
001: Propagation Segment = 2Tq
010: Propagation Segment = 3Tq
011: Propagation Segment = 4Tq
100: Propagation Segment = 5Tq
101: Propagation Segment = 6Tq
110: Propagation Segment = 7Tq
111: Propagation Segment = 8Tq
R
W
11
SAM
Sampling count select bit
0: Sampled one time
1: Sampled three times
R
W
12–15
No function assigned. Fix to "0".
0
0
SJW
SJW
SJW
SJW
=
=
=
=
1Tq
2Tq
3Tq
4Tq
111: Phase Segment1 = 8Tq
Notes: • Do not change settings of the CAN Configuration Register (CAN0CONF or CAN1CONF) during CAN operation (CAN
Status Register CRS bit = "0").
• When setting the bits in this register, make sure the conditions given below are met:
• Number of Tq’s for one bit: 8–25 Tq’s
• SJW ≤ min (Phase Segment1, Phase Segment2)
• Phase Segment2 = max (Phase Segment1, IPT) where IPT = 1 for the internal CAN modules of the 32182
min() is the function that returns the smaller of two values; max() is the function that returns the maximum value.
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13.2 CAN Module Related Registers
(1) SJW bits (Bits 0–1)
These bits set the reSynchronization Jump Width.
(2) PH2 bits (Bits 2–4)
These bits set the width of Phase Segment2.
(3) PH1 bits (Bits 5–7)
These bits set the width of Phase Segment1.
(4) PRB bits (Bits 8–10)
These bits set the width of Propagation Segment.
(5) SAM bit (Bit 11)
This bit sets the number of times each bit is sampled. When SAM = "0", the value sampled at the end of
Phase Segment1 is assumed to be the value of the bit. When SAM = "1", the value of the bit is determined by
a majority circuit from three sampled values, each sampled 2 Tq’s before, 1 Tq before, and at the end of
Phase Segment1.
Table 13.2.1 Typical Settings of Bit Timing when CPU Clock = 80 MHz
Baud Rate
BRP Set Value
1M bps
1
500K bps
Tq Period (ns)
No. of Tq’s in 1 Bit
PROP + PH1
PH2
Sampling Point
50
20
13
6
70%
3
100
10
7
2
80%
3
100
10
6
3
70%
3
100
10
5
4
60%
4
125
8
5
2
75%
4
125
8
4
3
63%
4
125
16
13
2
88%
4
125
16
12
3
81%
4
125
16
11
4
75%
7
200
10
7
2
80%
7
200
10
6
3
70%
7
200
10
5
4
60%
9
250
8
5
2
75%
9
250
8
4
3
63%
Table 13.2.2 Typical Settings of Bit Timing when CPU Clock = 64 MHz
Baud Rate
BRP Set Value
1M bps
1
500K bps
Tq Period (ns)
62.5
No. of Tq’s in 1 Bit
PROP + PH1
PH2
Sampling Point
16
10
5
69%
3
125
8
5
2
75%
3
125
8
4
3
63%
3
125
16
13
2
88%
3
125
16
11
4
75%
7
250
8
5
2
75%
7
250
8
4
3
63%
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13
13.2 CAN Module Related Registers
13.2.5 CAN Timestamp Count Registers
CAN0 Timestamp Count Register (CAN0TSTMP)
CAN1 Timestamp Count Register (CAN1TSTMP)
b0
1
2
3
4
5
6
<Address: H’0080 1008>
<Address: H’0080 1408>
7
8
9
10
11
12
13
14
0
0
0
0
0
0
b15
CANTSTMP
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0–15
CANTSTMP
16-bit timestamp count value
R
–
The CAN module contains a 16-bit up-count register. The count period can be selected from the CAN bus bit period
divided by 1, 2, 3 or 4 by setting the CAN Control Register (CANnCNT) TSP (Timestamp Prescaler) bits.
When the CAN module finishes sending or receiving, it captures the count register value and stores the value in a
message slot. The counter is made to start counting by clearing the CAN Control Register (CANnCNT) RST bit to "0".
Notes: • The CAN protocol control unit can be reset and the counter initialized to H’0000 by setting the
CAN Control Register (CANnCNT) RST (CAN Reset) bit to "1". Or the counter can be initialized
to H’0000 while the CAN module remains operating by setting the TSR (Timestamp Counter
Reset) bit to "1".
• If any slot with the matching ID exists during loopback mode, the CAN module stores the
timestamp value in that slot when it finished receiving. (No timestamp values are stored this
way when the CAN module finished sending.)
• The count period of the CAN Timestamp Count Register varies with the CAN resynchronization
function.
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13
13.2 CAN Module Related Registers
13.2.6 CAN Error Count Registers
CAN0 Receive Error Count Register (CAN0REC)
CAN1 Receive Error Count Register (CAN1REC)
b0
1
2
3
<Address: H’0080 100A>
<Address: H’0080 140A>
4
5
6
b7
0
0
0
0
REC
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0–7
REC
Receive error count value
R
–
During an error active/error passive state, a receive error count value is stored in this register.
The count is decremented when frames are received normally or incremented when an error occurred. If the
CAN module finished receiving normally when REC ≥ 128 (error passive), REC is set to 127. During a bus off
state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active
state.
CAN0 Transmit Error Count Register (CAN0TEC)
CAN1 Transmit Error Count Register (CAN1TEC)
b8
9
10
11
<Address: H’0080 100B>
<Address: H’0080 140B>
12
13
14
b15
0
0
0
0
TEC
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8–15
TEC
Transmit error count value
R
–
During an error active/error passive state, a transmit error count value is stored in this register.
The count is decremented when frames are transmitted normally or incremented when an error occurred. During a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an
error active state.
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13
13.2 CAN Module Related Registers
13.2.7 CAN Baud Rate Prescalers
CAN0 Baud Rate Prescaler (CAN0BRP)
CAN1 Baud Rate Prescaler (CAN1BRP)
b0
1
2
3
<Address: H’0080 1016>
<Address: H’0080 1416>
4
5
6
b7
0
0
0
1
BRP
0
0
0
0
<After reset: H’01>
b
Bit Name
Function
R
W
0–7
BRP
Baud rate prescaler value
R
W
This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq’s in one bit).
Tq period = (BRP + 1) / (CPU clock/2)
CAN transfer baud rate =
1
Tq period × number of Tq’s in one bit
Number of Tq’s in one bit = Synchronization Segment + Propagation Segment
+ Phase Segment 1 + Phase Segment 2
Notes: • Setting H’00 (divide by 1) is inhibited.
• Do not change settings of the CAN Baud Rate Prescaler (CANnBRP) during CAN operation
(CAN Status Register CRS bit = "0").
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13
13.2 CAN Module Related Registers
13.2.8 CAN Interrupt Related Registers
The CAN interrupt related registers are used to control the interrupt request signals output to the Interrupt Controller by CAN.
(1) Interrupt request status bit
This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this
bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no
effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request
enable bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling,
make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has
been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the
pending interrupt request is cleared simultaneously with its status bit.
(2) Interrupt request enable bit
This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to
"1" to enable interrupt requests or "0" to disable interrupt requests.
• Group interrupt
Interrupt request from
each peripheral function
Set
Data bus
Data = 0
clear
Interrupt request status
F/F
F/F
To the Interrupt Controller
Interrupt request enable
Figure 13.2.1 Interrupt Request Status and Enable Registers
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13
13.2 CAN Module Related Registers
Example for clearing interrupt request status
Interrupt request status
Initial state
b4
5
6
b7
0
0
0
0
Interrupt request
Event occurs on bit 6
0
0
1
0
Event occurs on bit 4
1
0
1
0
1
0
0
0
Write to the interrupt request status
b4
5
6
b7
1
1
0
1
Only bit 6 cleared
Bit 4 data retained
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
Event occurs on bit 6
b4
5
6
b7
0
0
1
0
Read
0
Event occurs on bit 4
1
0
1
0
0
1
0
Clear bit 6 (AND'ing with 1101)
0
0
0
0
0
0
0
Write
0
Only bit 6 cleared
Bit 4 also cleared
Figure 13.2.2 Example for Clearing Interrupt Request Status
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13
13.2 CAN Module Related Registers
CAN0 Slot Interrupt Request Status Register (CAN0SLIST)
CAN1 Slot Interrupt Request Status Register (CAN1SLIST)
b0
<Address: H’0080 100C>
<Address: H’0080 140C>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
SSB0
SSB1
SSB2
SSB3
SSB4
SSB5
SSB6
SSB7
SSB8
SSB9
SSB10
SSB11
SSB12
SSB13
SSB14
SSB15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
SSB0 (slot 0 interrupt request status bit)
0: Interrupt not requested
R(Note 1)
1
SSB1 (slot 1 interrupt request status bit)
1: Interrupt requested
2
SSB2 (slot 2 interrupt request status bit)
3
SSB3 (slot 3 interrupt request status bit)
4
SSB4 (slot 4 interrupt request status bit)
5
SSB5 (slot 5 interrupt request status bit)
6
SSB6 (slot 6 interrupt request status bit)
7
SSB7 (slot 7 interrupt request status bit)
8
SSB8 (slot 8 interrupt request status bit)
9
SSB9 (slot 9 interrupt request status bit)
10
SSB10 (slot 10 interrupt request status bit)
11
SSB11 (slot 11 interrupt request status bit)
12
SSB12 (slot 12 interrupt request status bit)
13
SSB13 (slot 13 interrupt request status bit)
14
SSB14 (slot 14 interrupt request status bit)
15
SSB15 (slot 15 interrupt request status bit)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write.
When using CAN interrupts, this register helps to know which slot requested an interrupt.
• Slots set for transmission
The corresponding bit is set to "1" when the CAN module finished sending. This bit is cleared by writing "0" in
software.
• Slots set for reception
The corresponding bit is set to "1" when the CAN module finished receiving and finished storing the received
message in the message slot. This bit is cleared by writing "0" in software.
When writing to the CAN slot interrupt request status, make sure only the bits to be cleared are set to "0" and all
other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the
value they had before the write.
Notes: • If the automatic response function is enabled for remote frame receive slots, the request status
is set after the CAN module finished receiving a remote frame and after it finished sending a
data frame.
• For remote frame transmit slots, the request status is set after the CAN module finished sending
a remote frame and after it finished receiving a data frame.
• If the request status is set by an interrupt request at the same time it is cleared in software, the
former has priority so that the request status is set.
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13
13.2 CAN Module Related Registers
CAN0 Slot Interrupt Request Enable Register (CAN0SLIEN)
CAN1 Slot Interrupt Request Enable Register (CAN1SLIEN)
b0
<Address: H’0080 1010>
<Address: H’0080 1410>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
IRB0
IRB1
IRB2
IRB3
IRB4
IRB5
IRB6
IRB7
IRB8
IRB9
IRB10
IRB11
IRB12
IRB13
IRB14
IRB15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
1
IRB0 (slot 0 interrupt request enable bit)
0: Mask (disable) interrupt request
R
W
IRB1 (slot 1 interrupt request enable bit)
1: Enable interrupt request
2
IRB2 (slot 2 interrupt request enable bit)
3
IRB3 (slot 3 interrupt request enable bit)
4
IRB4 (slot 4 interrupt request enable bit)
5
IRB5 (slot 5 interrupt request enable bit)
6
IRB6 (slot 6 interrupt request enable bit)
7
IRB7 (slot 7 interrupt request enable bit)
8
IRB8 (slot 8 interrupt request enable bit)
9
IRB9 (slot 9 interrupt request enable bit)
10
IRB10 (slot 10 interrupt request enable bit)
11
IRB11 (slot 11 interrupt request enable bit)
12
IRB12 (slot 12 interrupt request enable bit)
13
IRB13 (slot 13 interrupt request enable bit)
14
IRB14 (slot 14 interrupt request enable bit)
15
IRB15 (slot 15 interrupt request enable bit)
This register is used to enable or disable the interrupt requests that will be generated when data transmission or
reception in each corresponding slot is completed. Setting IRBn (n = 0–15) to "1" enables the interrupt request
to be generated when data transmission or reception in the corresponding slot is completed. The CAN Slot
Interrupt Request Status Register (CANnSLIST) helps to know which slot requested the interrupt.
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13
13.2 CAN Module Related Registers
CAN0 Error Interrupt Request Status Register (CAN0ERIST)
CAN1 Error Interrupt Request Status Register (CAN1ERIST)
b0
0
1
0
2
0
3
0
4
5
6
b7
BEIS
EPIS
EOIS
0
0
0
0
<Address: H’0080 1014>
<Address: H’0080 1414>
<After reset: H’00>
b
Bit Name
0–4
No function assigned. Fix to "0".
5
BEIS
CAN bus error interrupt request status bit
6
EPIS
Error passive interrupt request status bit
7
Function
0: Interrupt not requested
1: Interrupt requested
R
W
0
0
R(Note 1)
EOIS
Bus off interrupt request status bit
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write.
When using CAN interrupts, if the interrupt request sources are associated with errors, this register helps to
know which source generated the interrupt.
(1) BEIS (CAN Bus Error Interrupt Request Status) bit (Bit 5)
The BEIS bit is set to "1" when a communication error is detected. This bit is cleared by writing "0" in software.
(2) EPIS (Error Passive Interrupt Request Status) bit (Bit 6)
The EPIS bit is set to "1" when the CAN module goes to an error passive state. This bit is cleared by writing
"0" in software.
(3) EOIS (Bus Off Interrupt Request Status) bit (Bit 7)
The EOIS bit is set to "1" when the CAN module goes to a bus off passive state. This bit is cleared by writing
"0" in software.
When writing to the CAN error interrupt request status, make sure only the bits to be cleared are set to "0" and
all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain
the value they had before the write.
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13
13.2 CAN Module Related Registers
CAN0 Error Interrupt Request Enable Register (CAN0ERIEN)
CAN1 Error Interrupt Request Enable Register (CAN1ERIEN)
b8
9
10
11
12
13
BEIEN
0
0
0
0
0
14
<Address: H’0080 1015>
<Address: H’0080 1415>
b15
EPIEN EOIEN
0
0
0
<After reset: H’00>
b
Bit Name
8–12
No function assigned. Fix to "0".
13
BEIEN
CAN bus error interrupt request enable bit
14
EPIEN
Error passive interrupt request enable bit
15
Function
0: Mask (disable) interrupt request
1: Enable interrupt request
R
W
0
0
R
W
EOIEN
Bus off interrupt request enable bit
(1) BEIEN (CAN Bus Error Interrupt Request Enable) bit (Bit 5)
The BEIEN bit enables or disables the interrupt requests to be generated when CAN bus errors occurred.
CAN bus error interrupt requests are enabled by setting this bit to "1".
(2) EPIEN (Error Passive Interrupt Request Enable) bit (Bit 6)
The EPIEN bit enables or disables the interrupt requests to be generated when the CAN module entered an
error passive state. Error passive interrupt requests are enabled by setting this bit to "1".
(3) EOIEN (Bus Off Interrupt Request Enable) bit (Bit 7)
The EOIEN bit enables or disables the interrupt requests to be generated when the CAN module entered a
bus off state. Bus off interrupt requests are enabled by setting this bit to "1".
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13
13.2 CAN Module Related Registers
CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST)
CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST)
b0
<address: H’0080 1044>
<Address: H’0080 1444>
1
2
3
4
5
6
7
8
9
SSIST0
SSIST1
SSIST2
SSIST3
SSIST4
SSIST5
SSIST6
SSIST7
SSIST8
SSIST9
0
0
0
0
0
0
0
0
0
0
10
11
12
13
14
b15
SSIST10 SSIST11 SSIST12 SSIST13 SSIST14 SSIST15
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
SSIST0
Slot 0 single-shot interrupt request status
0: No arbitration-lost or transmit error
1: Arbitration-lost or transmit error occurred
R(Note 1)
1
SSIST1
Slot 1 single-shot interrupt request status
2
SSIST2
Slot 2 single-shot interrupt request status
3
SSIST3
Slot 3 single-shot interrupt request status
4
SSIST4
Slot 4 single-shot interrupt request status
5
SSIST5
Slot 5 single-shot interrupt request status
6
SSIST6
Slot 6 single-shot interrupt request status
7
SSIST7
Slot 7 single-shot interrupt request status
8
SSIST8
Slot 8 single-shot interrupt request status
9
SSIST9
Slot 9 single-shot interrupt request status
10
SSIST10
Slot 10 single-shot interrupt request status
11
SSIST11
Slot 11 single-shot interrupt request status
12
SSIST12
Slot 12 single-shot interrupt request status
13
SSIST13
Slot 13 single-shot interrupt request status
14
SSIST14
Slot 14 single-shot interrupt request status
15
SSIST15
Slot 15 single-shot interrupt request status
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write.
If transmission in any slot failed for reasons of a detection of arbitration-lost or a transmit error, the corresponding bit in this register is set to "1". The bit is cleared by writing "0" in software.
Furthermore, if the corresponding bit in the CAN single-shot interrupt request enable register has been set to "1",
an interrupt request can be generated when transmission failed.
When writing to the CAN single-shot interrupt request status, make sure only the bits to be cleared are set to "0"
and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and
retain the value they had before the write.
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13
13.2 CAN Module Related Registers
CAN0 Single-Shot Interrupt Request Enable Register (CAN0SSIEN)
CAN1 Single-Shot Interrupt Request Enable Register (CAN1SSIEN)
1
2
3
4
5
6
7
8
SSIEN0
b0
SSIEN1
SSIEN2
SSIEN3
SSIEN4
SSIEN5
SSIEN6
SSIEN7
SSIEN8
0
0
0
0
0
0
0
0
0
9
<Address: H’0080 1048>
<Address: H’0080 1448>
10
11
12
13
14
b15
SSIEN9 SSIEN10 SSIEN11 SSIEN12 SSIEN13 SSIEN14 SSIEN15
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
SSIEN0
Slot 0 single-shot interrupt request enable bit
0: Disable interrupt request
1: Enable interrupt request
R
W
1
SSIEN1
Slot 1 single-shot interrupt request enable bit
2
SSIEN2
Slot 2 single-shot interrupt request enable bit
3
SSIEN3
Slot 3 single-shot interrupt request enable bit
4
SSIEN4
Slot 4 single-shot interrupt request enable bit
5
SSIEN5
Slot 5 single-shot interrupt request enable bit
6
SSIEN6
Slot 6 single-shot interrupt request enable bit
7
SSIEN7
Slot 7 single-shot interrupt request enable bit
8
SSIEN8
Slot 8 single-shot interrupt request enable bit
9
SSIEN9
Slot 9 single-shot interrupt request enable bit
10
SSIEN10
Slot 10 single-shot interrupt request enable bit
11
SSIEN11
Slot 11 single-shot interrupt request enable bit
12
SSIEN12
Slot 12 single-shot interrupt request enable bit
13
SSIEN13
Slot 13 single-shot interrupt request enable bit
14
SSIEN14
Slot 14 single-shot interrupt request enable bit
15
SSIEN15
Slot 15 single-shot interrupt request enable bit
This register is used to enable or disable the interrupt requests that will be generated when transmission in each
corresponding slot has failed. Setting any bit in this register to "1" enables the interrupt request to be generated
when transmission in the corresponding slot (in single-shot mode only) has failed. The CAN Single-Shot Interrupt Request Status Register helps to know which slot requested the interrupt.
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13
13.2 CAN Module Related Registers
CAN0SLIST (H'0080 100C)
CAN0SLIEN (H'0080 1010)
Slot 0 transmission/reception completed
Data bus
b0
SSB0
F/F
b0
IRB0
F/F
35-source inputs
(Level)
CAN0 transmit/receive &
error interrupt request
Slot 1 transmission/reception completed
b1
SSB1
F/F
b1
IRB1
F/F
Slot 2 transmission/reception completed
b2
SSB2
F/F
b2
IRB2
F/F
Slot 3 transmission/reception completed
b3
SSB3
F/F
b3
IRB3
F/F
Slot 4 transmission/reception completed
b4
SSB4
F/F
b4
IRB4
F/F
Slot 5 transmission/reception completed
b5
SSB5
F/F
b5
IRB5
F/F
Slot 6 transmission/reception completed
b6
SSB6
F/F
b6
IRB6
F/F
Slot 7 transmission/reception completed
b7
SSB7
F/F
b7
IRB7
F/F
To the remaining 27-source inputs in the next page
Figure 13.2.3 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (1/5)
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13
13.2 CAN Module Related Registers
CAN0SLIST (H'0080 100C)
CAN0SLIEN (H'0080 1010)
Slot 8 transmission/reception completed
Data bus
b8
SSB8
F/F
b8
IRB8
F/F
27-source inputs
(Level)
To the preceding page
Slot 9 transmission/reception completed
b9
SSB9
F/F
b9
IRB9
F/F
Slot 10 transmission/reception completed
b10
SSB10
F/F
b10
IRB10
F/F
Slot 11 transmission/reception completed
b11
SSB11
F/F
b11
IRB11
F/F
Slot 12 transmission/reception completed
b12
SSB12
F/F
b12
IRB12
F/F
Slot 13 transmission/reception completed
b13
SSB13
F/F
b13
IRB13
F/F
Slot 14 transmission/reception completed
b14
SSB14
F/F
b14
IRB14
F/F
Slot 15 transmission/reception completed
b15
SSB15
F/F
b15
IRB15
F/F
To the remaining 19-source inputs in the next page
Figure 13.2.4 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (2/5)
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13
13.2 CAN Module Related Registers
CAN0ERIST (H'0080 1014)
CAN0ERIEN (H'0080 1015)
CAN bus error occurs
Data bus
b5
BEIS
F/F
b13
BEIEN
F/F
19-source inputs
(Level)
To the preceding page
Go to error passive state
b6
EPIS
F/F
b14
EPIEN
F/F
Go to bus off state
b7
EOIS
F/F
b15
EOIEN
F/F
To the remaining 16-source inputs in the next page
Figure 13.2.5 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (3/5)
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13
13.2 CAN Module Related Registers
CAN0SSIST (H'0080 1044)
CAN0SSIEN (H'0080 1048)
Slot 0 arbitration-lost/transmit error occurs
Data bus
b0
SSIST0
F/F
b0
SSIEN0
F/F
16-source inputs
(Level)
To the preceding page
Slot 1 arbitration-lost/transmit error occurs
b1
SSIST1
F/F
b1
SSIEN1
F/F
Slot 2 arbitration-lost/transmit error occurs
b2
SSIST2
F/F
b2
SSIEN2
F/F
Slot 3 arbitration-lost/transmit error occurs
b3
SSIST3
F/F
b3
SSIEN3
F/F
Slot 4 arbitration-lost/transmit error occurs
b4
SSIST4
F/F
b4
SSIEN4
F/F
Slot 5 arbitration-lost/transmit error occurs
b5
SSIST5
F/F
b5
SSIEN5
F/F
Slot 6 arbitration-lost/transmit error occurs
b6
SSIST6
F/F
b6
SSIEN6
F/F
Slot 7 arbitration-lost/transmit error occurs
b7
SSIST7
F/F
b7
SSIEN7
F/F
To the remaining 8-source inputs in the next page
Figure 13.2.6 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (4/5)
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13
13.2 CAN Module Related Registers
CAN0SSIST (H'0080 1044)
CAN0SSIEN (H'0080 1048)
Slot 8 arbitration-lost/transmit error occurs
Data bus
b8
SSIST8
F/F
b8
SSIEN8
F/F
8-source inputs
(Level)
To the preceding page
Slot 9 arbitration-lost/transmit error occurs
b9
SSIST9
F/F
b9
SSIEN9
F/F
Slot 10 arbitration-lost/transmit error occurs
b10
SSIST10
F/F
b10
SSIEN10
F/F
Slot 11 arbitration-lost/transmit error occurs
b11
SSIST11
F/F
b11
SSIEN11
F/F
Slot 12 arbitration-lost/transmit error occurs
b12
SSIST12
F/F
b12
SSIEN12
F/F
Slot 13 arbitration-lost/transmit error occurs
b13
SSIST13
F/F
b13
SSIEN13
F/F
Slot 14 arbitration-lost/transmit error occurs
b14
SSIST14
F/F
b14
SSIEN14
F/F
Slot 15 arbitration-lost/transmit error occurs
b15
SSIST15
F/F
b15
SSIEN15
F/F
Figure 13.2.7 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (5/5)
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13
13.2 CAN Module Related Registers
CAN1SLIST (H'0080 140C)
CAN1SLIEN (H'0080 1410)
Slot 0 transmission/reception completed
Data bus
b0
SSB0
F/F
b0
IRB0
F/F
35-source inputs
(Level)
CAN1 transmit/receive &
error interrupt request
Slot 1 transmission/reception completed
b1
SSB1
F/F
b1
IRB1
F/F
Slot 2 transmission/reception completed
b2
SSB2
F/F
b2
IRB2
F/F
Slot 3 transmission/reception completed
b3
SSB3
F/F
b3
IRB3
F/F
Slot 4 transmission/reception completed
b4
SSB4
F/F
b4
IRB4
F/F
Slot 5 transmission/reception completed
b5
SSB5
F/F
b5
IRB5
F/F
Slot 6 transmission/reception completed
b6
SSB6
F/F
b6
IRB6
F/F
Slot 7 transmission/reception completed
b7
SSB7
F/F
b7
IRB7
F/F
To the remaining 27-source inputs in the next page
Figure 13.2.8 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (1/5)
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13
13.2 CAN Module Related Registers
CAN1SLIST (H'0080 140C)
CAN1SLIEN (H'0080 1410)
Slot 8 transmission/reception completed
Data bus
SSB8
b8
27-source inputs
F/F
IRB8
b8
(Level)
To the preceding page
F/F
Slot 9 transmission/reception completed
SSB9
b9
F/F
IRB9
b9
F/F
Slot 10 transmission/reception completed
SSB10
b10
F/F
IRB10
b10
F/F
Slot 11 transmission/reception completed
SSB11
b11
F/F
IRB11
b11
F/F
Slot 12 transmission/reception completed
b12
SSB12
F/F
b12
IRB12
F/F
Slot 13 transmission/reception completed
SSB13
b13
F/F
b13
IRB13
F/F
Slot 14 transmission/reception completed
b14
SSB14
F/F
b14
IRB14
F/F
Slot 15 transmission/reception completed
b15
SSB15
F/F
b15
IRB15
F/F
To the remaining 19-source inputs in the next page
Figure 13.2.9 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (2/5)
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13
13.2 CAN Module Related Registers
CAN1ERIST (H'0080 1414)
CAN1ERIEN (H'0080 1415)
CAN bus error occurs
Data bus
b5
BEIS
F/F
b13
BEIEN
F/F
19-source inputs
(Level)
To the preceding page
Go to error passive state
b6
EPIS
F/F
b14
EPIEN
F/F
Go to bus off state
b7
EOIS
F/F
b15
EOIEN
F/F
To the remaining 16-source inputs in the next page
Figure 13.2.10 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (3/5)
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13
13.2 CAN Module Related Registers
CAN1SSIST (H'0080 1444)
CAN1SSIEN (H'0080 1488)
Slot 0 arbitration-lost/transmit error occurs
Data bus
b0
SSIST0
F/F
b0
SSIEN0
F/F
16-source inputs
To the preceding page
(Level)
Slot 1 arbitration-lost/transmit error occurs
b1
SSIST1
F/F
b1
SSIEN1
F/F
Slot 2 arbitration-lost/transmit error occurs
b2
SSIST2
F/F
b2
SSIEN2
F/F
Slot 3 arbitration-lost/transmit error occurs
b3
SSIST3
F/F
b3
SSIEN3
F/F
Slot 4 arbitration-lost/transmit error occurs
b4
SSIST4
F/F
b4
SSIEN4
F/F
Slot 5 arbitration-lost/transmit error occurs
b5
SSIST5
F/F
b5
SSIEN5
F/F
Slot 6 arbitration-lost/transmit error occurs
b6
SSIST6
F/F
b6
SSIEN6
F/F
Slot 7 arbitration-lost/transmit error occurs
b7
SSIST7
F/F
b7
SSIEN7
F/F
To the remaining 8-source inputs in the next page
Figure 13.2.11 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (4/5)
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13
13.2 CAN Module Related Registers
CAN1SSIST (H'0080 1444)
CAN1SSIEN (H'0080 1488)
Slot 8 arbitration-lost/transmit error occurs
Data bus
b8
SSIST8
F/F
b8
SSIEN8
F/F
8-source inputs
(Level)
To the preceding page
Slot 9 arbitration-lost/transmit error occurs
b9
SSIST9
F/F
b9
SSIEN9
F/F
Slot 10 arbitration-lost/transmit error occurs
b10
SSIST10
F/F
b10
SSIEN10
F/F
Slot 11 arbitration-lost/transmit error occurs
b11
SSIST11
F/F
b11
SSIEN11
F/F
Slot 12 arbitration-lost/transmit error occurs
b12
SSIST12
F/F
b12
SSIEN12
F/F
Slot 13 arbitration-lost/transmit error occurs
b13
SSIST13
F/F
b13
SSIEN13
F/F
Slot 14 arbitration-lost/transmit error occurs
b14
SSIST14
F/F
b14
SSIEN14
F/F
Slot 15 arbitration-lost/transmit error occurs
b15
SSIST15
F/F
b15
SSIEN15
F/F
Figure 13.2.12 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (5/5)
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13
13.2 CAN Module Related Registers
13.2.9 CAN Cause of Error Registers
CAN0 Cause of Error Register (CAN0EF)
CAN1 Cause of Error Register (CAN1EF)
b8
0
9
10
11
ETR
BITE
0
0
0
12
13
<Address: H’0080 1017>
<Address: H’0080 1417>
14
STFE FORME CRCE
0
0
b15
ACKE
0
0
<After reset: H’00>
b
Bit Name
8–9
No function assigned. Fix to "0".
10
ETR
Transmit/receive error judgment bit
11
12
Function
R
W
0
0
0: Error detected when sending
1: Error detected when receiving
R
–
BITE
Bit error detection bit
0: Bit error not detected
1: Bit error detected
R
–
R
–
STFE
0: Stuff error not detected
Stuff error detection bit
1: Stuff error detected
13
FORME
Form error detection bit
0: Form error not detected
1: Form error detected
R
–
14
CRCE
CRC error detection bit
0: CRC error not detected
1: CRC error detected
R
–
ACKE
0: ACK error not detected
R
–
ACK error detection bit
1: ACK error detected
15
This register indicates error information when a communication error occurred.
(1) ETR (Transmit/Receive Error Judgement) bit (Bit 10)
This bit is set to "1" if the CAN module was operating as a reception node when a communication error
occurred. The bit is cleared to "0" by a read of this register.
(2) BITE (Bit Error Detection) bit (Bit 11)
This bit is set to "1" when a bit error was detected. The bit is cleared to "0" by a read of this register.
(3) STFE (Stuff Error Detection) bit (Bit 12)
This bit is set to "1" when a stuff error was detected. The bit is cleared to "0" by a read of this register.
(4) FORME (Form Error Detection) bit (Bit 13)
This bit is set to "1" when a form error was detected. The bit is cleared to "0" by a read of this register.
(5) CRCE (CRC Error Detection) bit (Bit 14)
This bit is set to "1" when a CRC error was detected. The bit is cleared to "0" by a read of this register.
(6) ACKE (ACK Error Detection) bit (Bit 15)
This bit is set to "1" when an ACK error was detected. The bit is cleared to "0" by a read of this register.
Note: • Depending on the error status, two or more bits may be set at the same time.
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13
13.2 CAN Module Related Registers
13.2.10 CAN Mode Registers
CAN0 Mode Register (CAN0MOD)
CAN1 Mode Register (CAN1MOD)
b0
1
2
3
4
<Address: H’0080 1018>
<Address: H’0080 1418>
5
6
b7
CMOD
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0–5
No function assigned. Fix to "0".
6–7
CMOD
CAN operation mode select bit
00:
01:
10:
11:
Normal mode
Bus monitor mode
Self-diagnostic mode
Settings inhibited
R
W
0
0
R
W
(1) CMOD (CAN Operation Mode Select) bits (Bit 6, Bit 7)
These bits select the CAN operation mode.
• Normal operation mode
Normal transmit/receive operations can be performed.
• Bus monitor mode
Only receive operation is performed. During bus monitor mode, the CTX output is fixed high and neither
ACK nor an error frame can be returned.
Note: • During bus monitor mode, issuing transmit requests is inhibited. The ACK bit is handled as
“Don’t care” during bus monitor mode. Therefore, if all bits of data including the CRC delimiter are received normally, it is assumed that data has been received normally no matter
whether the ACK bit is high.
• Self-diagnostic mode
CTX and CRX are connected together internally in the CAN module. When combined with loopback
mode, this mode allows communication to be performed within the CAN module alone. During selfdiagnostic mode, the CTX pin output is fixed high even when transmitting.
M32R/ECU CAN module
Self-diagnostic mode
CRX pin
Rx
Ack signal
generating
circuit
Tx
CTX pin
Figure 13.2.13 Conceptual Diagram of Self-Diagnostic Mode
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13.2 CAN Module Related Registers
13.2.11 CAN DMA Transfer Request Select Register
CAN0 DMA Transfer Request Select Register (CAN0DMARQ)
b8
9
10
11
12
13
14
<Address: H’0080 1019>
b15
CDMSEL1 CDMSEL0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8–13
No function assigned. Fix to "0".
0
0
14
CDMSEL1
CAN DMA1 transfer request source select bit
0: Slot 1 transmission failed
1: Slot 14 transmission/reception completed
R
W
15
CDMSEL0
CAN DMA0 transfer request source select bit
0: Slot 0 transmission failed
1: Slot 15 transmission/reception completed
R
W
CAN0 can generate DMA transfer requests. This register is used to select the cause or source of that request.
(1) CDMSEL1 (CAN DMA1 Transfer Request Source Select) bit (Bit 14)
This bit selects one of the following two as the cause or source of a transfer request to DMA2.
• Slot 1 transmission failed
If the CDMSEL1 bit is set to "0", a transfer request is generated when transmission in slot 1 has failed for
reasons of arbitration-lost or transmit error.
• Slot 14 transmission/reception completed
If the CDMSEL1 bit is set to "1", a transfer request is generated when transmission/reception in slot 14
is completed.
Notes: • If slot 14 has been set for remote frame transmission, a DMA transfer request is generated
when remote frame transmission is completed as well as when data frame reception is
completed.
• If slot 14 has been set for remote frame reception (automatic response), a DMA transfer
request is generated when remote frame reception is completed as well as when data
frame transmission is completed.
Note: • CAN1 does not have the DMA transfer request function.
(2) CDMSEL0 (CAN DMA0 Transfer Request Source Select) bit (Bit 15)
This bit selects one of the following two as the cause or source of a transfer request to DMA0.
• Slot 0 transmission failed
If the CDMSEL0 bit is set to "0", a transfer request is generated when transmission in slot 0 has failed for
reasons of arbitration-lost or transmit error.
• Slot 15 transmission/reception completed
If the CDMSEL0 bit is set to "1", a transfer request is generated when transmission/reception in slot 15
is completed.
Notes: • If slot 15 has been set for remote frame transmission, a DMA transfer request is generated
when remote frame transmission is completed as well as when data frame reception is
completed.
• If slot 15 has been set for remote frame reception (automatic response), a DMA transfer
request is generated when remote frame reception is completed as well as when data
frame transmission is completed.
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13.2 CAN Module Related Registers
13.2.12 CAN Mask Registers
CAN0 Global Mask Register Standard ID0 (C0GMSKS0)
CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0)
CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0)
<Address: H’0080 1028>
<Address: H’0080 1030>
<Address: H’0080 1038>
CAN1 Global Mask Register Standard ID0 (C1GMSKS0)
CAN1 Local Mask Register A Standard ID0 (C1LMSKAS0)
CAN1 Local Mask Register B Standard ID0 (C1LMSKBS0)
<Address: H’0080 1428>
<Address: H’0080 1430>
<Address: H’0080 1438>
b0
1
2
3
4
5
6
b7
SID0M SID1M SID2M SID3M SID4M
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0–2
No function assigned. Fix to "0".
3–7
SID0M–SID4M
(Standard mask ID0–standard mask ID4)
Function
R
W
0
0
0: ID not checked
1: ID checked
R
W
CAN0 Global Mask Register Standard ID1 (C0GMSKS1)
CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1)
CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1)
<Address: H’0080 1029>
<Address: H’0080 1031>
<Address: H’0080 1039>
CAN1 Global Mask Register Standard ID1 (C1GMSKS1)
CAN1 Local Mask Register A Standard ID1 (C1LMSKAS1)
CAN1 Local Mask Register B Standard ID1 (C1LMSKBS1)
<Address: H’0080 1429>
<Address: H’0080 1431>
<Address: H’0080 1439>
b8
9
10
11
12
13
14
b15
SID5M SID6M SID7M SID8M SID9M SID10M
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
8–9
No function assigned. Fix to "0".
10–15
SID5M–SID10M
(Standard mask ID5–standard mask ID10)
Function
0: ID not checked
1: ID checked
R
W
0
0
R
W
Three mask registers are used in acceptance filtering: global mask register, local mask register A and local
mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during
acceptance filtering.
• If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during
acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it.
Notes: • SID0M corresponds to the MSB of the standard ID.
• The global mask register can only be modified when none of slots 0-13 have receive requests set.
• The local mask register A can only be modified when slot 14 does not have a receive request set.
• The local mask register B can only be modified when slot 15 does not have a receive request set.
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13.2 CAN Module Related Registers
CAN0 Global Mask Register Extended ID0 (C0GMSKE0)
CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0)
CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0)
<Address: H’0080 102A>
<Address: H’0080 1032>
<Address: H’0080 103A>
CAN1 Global Mask Register Extended ID0 (C1GMSKE0)
CAN1 Local Mask Register A Extended ID0 (C1LMSKAE0)
CAN1 Local Mask Register B Extended ID0 (C1LMSKBE0)
<Address: H’0080 142A>
<Address: H’0080 1432>
<Address: H’0080 143A>
b0
1
2
3
4
EID0M
0
0
0
0
5
6
b7
EID1M EID2M EID3M
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
0–3
No function assigned. Fix to "0".
4–7
EID0M–EID3M
(Extended mask ID0–extended mask ID3)
0: ID not checked
1: ID checked
R
W
0
0
R
W
CAN0 Global Mask Register Extended ID1 (C0GMSKE1)
CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1)
CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1)
<Address: H’0080 102B>
<Address: H’0080 1033>
<Address: H’0080 103B>
CAN1 Global Mask Register Extended ID1 (C1GMSKE1)
CAN1 Local Mask Register A Extended ID1 (C1LMSKAE1)
CAN1 Local Mask Register B Extended ID1 (C1LMSKBE1)
<Address: H’0080 142B>
<Address: H’0080 1433>
<Address: H’0080 143B>
b8
9
10
11
12
13
14
b15
EID4M EID5M EID6M EID7M EID8M EID9M EID10M EID11M
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
8–15
EID4M–EID11M
0: ID not checked
R
W
(Extended mask ID4–extended mask ID11)
1: ID checked
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13
13.2 CAN Module Related Registers
CAN0 Global Mask Register Extended ID2 (C0GMSKE2)
CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2)
CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2)
<Address: H’0080 102C>
<Address: H’0080 1034>
<Address: H’0080 103C>
CAN1 Global Mask Register Extended ID2 (C1GMSKE2)
CAN1 Local Mask Register A Extended ID2 (C1LMSKAE2)
CAN1 Local Mask Register B Extended ID2 (C1LMSKBE2)
<Address: H’0080 142C>
<Address: H’0080 1434>
<Address: H’0080 143C>
b0
1
2
3
4
5
6
B7
EID12M EID13M EID14M EID15M EID16M EID17M
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
0,1
No function assigned. Fix to "0".
2–7
EID12M–EID17M
(Extended mask ID12–extended mask ID17)
Function
0: ID not checked
1: ID checked
R
W
0
0
R
W
Three mask registers are used in acceptance filtering: global mask register, local mask register A and local
mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during
acceptance filtering.
• If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during
acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it.
Notes: • EID0M corresponds to the MSB of the extended ID.
• The global mask register can only be modified when none of slots 0-13 have receive requests set.
• The local mask register A can only be modified when slot 14 does not have a receive request set.
• The local mask register B can only be modified when slot 15 does not have a receive request set.
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13
13.2 CAN Module Related Registers
Slot 0
Slot 1
Slots controlled by
the global mask register
Slot 2
Slot 13
Slot 14
Slot controlled by local mask register A
Slot 15
Slot controlled by local mask register B
Figure 13.2.14 Relationship between the Mask Registers and the Controlled Slots
Mask bit value
ID of received
frame
ID set in slot
Mask register
set value
0: The received message and slot IDs are
not checked for matching and handled as
"Don't care" (masked)
1: The received message and slot IDs are
checked for matching
Acceptance judgment signal
Acceptance judgment signal
0: The received message is ignored
(not stored in any slot)
1: The received message is stored in
the slot that has the matching ID
Figure 13.2.15 Concept of Acceptance Filtering
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13
13.2 CAN Module Related Registers
13.2.13 CAN Single-Shot Mode Control Registers
CAN0 Single-Shot Mode Control Register (CAN0SSMODE)
CAN1 Single-Shot Mode Control Register (CAN1SSMODE)
b0
1
2
3
4
5
6
7
<Address: H’0080 1040>
<Address: H’0080 1440>
8
9
10
11
12
13
14
b15
SSCNT0 SSCNT1 SSCNT2 SSCNT3 SSCNT4 SSCNT5 SSCNT6 SSCNT7 SSCNT8 SSCNT9 SSCNT10 SSCNT11 SSCNT12 SSCNT13 SSCNT14 SSCNT15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
W
0
SSCNT0 (Slot 0 single-shot mode bit)
0: Normal mode
R
W
1
SSCNT1 (Slot 1 single-shot mode bit)
1: Single-shot mode
2
SSCNT2 (Slot 2 single-shot mode bit)
3
SSCNT3 (Slot 3 single-shot mode bit)
4
SSCNT4 (Slot 4 single-shot mode bit)
5
SSCNT5 (Slot 5 single-shot mode bit)
6
SSCNT6 (Slot 6 single-shot mode bit)
7
SSCNT7 (Slot 7 single-shot mode bit)
8
SSCNT8 (Slot 8 single-shot mode bit)
9
SSCNT9 (Slot 9 single-shot mode bit)
10
SSCNT10 (Slot 10 single-shot mode bit)
11
SSCNT11 (Slot 11 single-shot mode bit)
12
SSCNT12 (Slot 12 single-shot mode bit)
13
SSCNT13 (Slot 13 single-shot mode bit)
14
SSCNT14 (Slot 14 single-shot mode bit)
15
SSCNT15 (Slot 15 single-shot mode bit)
Normally in CAN, if transmission has failed for reasons of arbitration-lost or transmit error, the transmit operation
is continued until successfully transmitted. This register is used to specify for each slot whether or not to retry a
transmit operation in such a case.
In single-shot mode, if transmission fails for reasons of arbitration-lost or transmit error, the transmit operation is
not retried. If any bit in this register is set to "1", the corresponding slot operates in single-shot mode.
Note: • Settings of this register can only be changed when the message slot control register for the slot
whose corresponding bit is to be modified is in the H’00 state.
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13
13.2 CAN Module Related Registers
13.2.14 CAN Message Slot Control Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Control Register (C0MSL0CNT)
Slot 1 Control Register (C0MSL1CNT)
Slot 2 Control Register (C0MSL2CNT)
Slot 3 Control Register (C0MSL3CNT)
Slot 4 Control Register (C0MSL4CNT)
Slot 5 Control Register (C0MSL5CNT)
Slot 6 Control Register (C0MSL6CNT)
Slot 7 Control Register (C0MSL7CNT)
Slot 8 Control Register (C0MSL8CNT)
Slot 9 Control Register (C0MSL9CNT)
Slot 10 Control Register (C0MSL10CNT)
Slot 11 Control Register (C0MSL11CNT)
Slot12 Control Register (C0MSL12CNT)
Slot 13 Control Register (C0MSL13CNT)
Slot 14 Control Register (C0MSL14CNT)
Slot 15 Control Register (C0MSL15CNT)
<Address: H’0080 1050>
<Address: H’0080 1051>
<Address: H’0080 1052>
<Address: H’0080 1053>
<Address: H’0080 1054>
<Address: H’0080 1055>
<Address: H’0080 1056>
<Address: H’0080 1057>
<Address: H’0080 1058>
<Address: H’0080 1059>
<Address: H’0080 105A>
<Address: H’0080 105B>
<Address: H’0080 105C>
<Address: H’0080 105D>
<Address: H’0080 105E>
<Address: H’0080 105F>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
<Address: H’0080 1450>
<Address: H’0080 1451>
<Address: H’0080 1452>
<Address: H’0080 1453>
<Address: H’0080 1454>
<Address: H’0080 1455>
<Address: H’0080 1456>
<Address: H’0080 1457>
<Address: H’0080 1458>
<Address: H’0080 1459>
<Address: H’0080 145A>
<Address: H’0080 145B>
<Address: H’0080 145C>
<Address: H’0080 145D>
<Address: H’0080 145E>
<Address: H’0080 145F>
0 Control Register (C1MSL0CNT)
1 Control Register (C1MSL1CNT)
2 Control Register (C1MSL2CNT)
3 Control Register (C1MSL3CNT)
4 Control Register (C1MSL4CNT)
5 Control Register (C1MSL5CNT)
6 Control Register (C1MSL6CNT)
7 Control Register (C1MSL7CNT)
8 Control Register (C1MSL8CNT)
9 Control Register (C1MSL9CNT)
10 Control Register (C1MSL10CNT)
11 Control Register (C1MSL11CNT)
12 Control Register (C1MSL12CNT)
13 Control Register (C1MSL13CNT)
14 Control Register (C1MSL14CNT)
15 Control Register (C1MSL15CNT)
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13.2 CAN Module Related Registers
b0(b8)
1
2
3
4
5
TR
RR
RM
RL
RA
ML
0
0
0
0
0
0
6
b7(b15)
TRSTAT TRFIN
0
0
<After reset: H’00>
b
Bit Name
Function
R
W
0
TR
Transmit request bit
0: Do not use the message slot as transmit slot
1: Use the message slot as transmit slot
R
W
1
RR
Receive request bit
0: Do not use the message slot as receive slot
1: Use the message slot as receive slot
R
W
R
W
2
RM
0: Transmit/receive data frame
Remote bit
1: Transmit/receive remote frame
3
RL
Automatic response inhibit bit
0: Enable automatic response for remote frame
1: Disable automatic response for remote frame
R
W
4
RA
Remote active bit
During BasicCAN mode
0: Receive data frame (status)
1: Receive remote frame (status)
During normal mode
0: Data frame
1: Remote frame
R
–
5
ML
Message lost bit
0: No message was lost
1: Message was lost
R(Note 1)
6
TRSTAT
Transmit/receive status bit
During a transmit slot
0: Transmission idle
1: Transmit request accepted
During a receive slot
0: Reception idle
1: Storing received data
R
7
TRFIN
Transmission/reception finished bit
During a transmit slot
0: Not transmitted yet
1: Finished transmitting
During a receive slot
0: Not received yet
1: Finished receiving
R(Note 1)
–
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write.
Notes: • If a transmit request is written to this register while the CAN module is reset (CANnCNT FRST
or RST bit = "1"), it starts sending upon detecting 11 consecutive recessive bits on the CAN bus
after exiting the reset state.
• If data/remote frame transmit requests are issued for two or more slots, the slot with the smallest slot number sends a frame. If data/remote frame receive requests are issued for two or
more slots, the slot with the smallest slot number among the slots satisfying the receive condition receives a frame.
• If transmission failed when single-shot mode is selected, this register is cleared to H’00.
(1) TR (Transmit Request) bit (Bit 0)
To use the message slot as a transmit slot, set this bit to "1". To use the message slot as a data frame or
remote frame receive slot, set this bit to "0".
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13.2 CAN Module Related Registers
(2) RR (Receive Request) bit (Bit 1)
To use the message slot as a receive slot, set this bit to "1". To use the message slot as a data frame or
remote frame transmit slot, set this bit to "0".
If TR (Transmit Request) bit and RR (Receive Request) bit both are set to "1", device operation is undefined.
(3) RM (Remote) bit (Bit 2)
To handle remote frames in the message slot, set this bit to "1". There are following two methods of settings
to handle remote frames:
• Set for remote frame transmission
The data set in the message slot is transmitted as a remote frame. When the CAN module finished
sending, the slot automatically changes to a data frame receive slot. However, if a data frame is received
before the CAN module finished sending a remote frame, the received data is stored in the message slot
and the remote frame is not transmitted.
• Set for remote frame reception
Remote frames are received. The processing to be performed after receiving a remote frame is selected
by RL (automatic response inhibit) bit.
(4) RL (Automatic Response Inhibit) bit (Bit 3)
This bit is effective when the message slot has been set as a remote frame receive slot. It selects the
processing to be performed after receiving a remote frame. If this bit is set to "0", the message slot automatically changes to a transmit slot after receiving a remote frame and transmits the data set in it as a data frame.
If this bit is set to "1", the message slot stops operating after receiving a remote frame.
Note: • Always set this bit to "0" unless the message slot is set for remote frame reception.
(5) RA (Remote Active) bit (Bit 4)
This bit functions differently for slots 0-13 and slots 14 and 15.
• Slots 0–13
This bit is set to "1" when the message slot is set for remote frame transmission (reception). Then, when
remote frame transmission (reception) is completed, the bit is cleared to "0".
• Slots 14 and 15
The function of this bit differs depending on how the CAN Control Register BCM (BasicCAN Mode) bit is
set. If BCM = "0" (normal operation), this bit is set to "1" when the message slot is set for remote frame
transmission (reception). If BCM = "1" (BasicCAN), this bit indicates which type of frame is received.
During BasicCAN mode, the received data is stored in slots 14 and 15 for both data and remote frames.
If RA = "0", it means that the frame stored in the slot is a data frame. If RA = "1", it means that the frame
stored in the slot is a remote frame.
(6) ML (Message Lost) bit (Bit 5)
This bit is effective for receive slots. It is set to "1" when unread received data contained in the message slot
is overwritten by reception. This bit is cleared by writing "0" in software.
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13.2 CAN Module Related Registers
(7) TRSTAT (Transmit/Receive Status) bit (Bit 6)
This bit indicates that the CAN module is sending or receiving and is accessing the message slot. This bit is
set to "1" when the CAN module is accessing, and set to "0" when not accessing.
• During a transmit slot
This bit is set to "1" when a transmit request for the message slot is accepted. It is cleared to "0" when
the CAN module lost in bus arbitration, when a CAN bus error occurs, or when transmission is
completed.
• During a receive slot
This bit is set to "1" while the CAN module is receiving data, with the received data being stored in the
message slot. Note that the value read from the message slot while the TRSTAT bit remains set is
undefined.
(8) TRFIN (Transmit/Receive Finished) bit (Bit 7)
This bit indicates that the CAN module finished sending or receiving.
• When set for a transmit slot
This bit is set to "1" when the CAN module finished sending the data stored in the message slot.
This bit is cleared by writing "0" in software. However, it cannot be cleared when the TRSTAT (Transmit/
Receive Status) bit = "1".
• When set for a receive slot
This bit is set to "1" when the CAN module finished receiving normally the data to be stored in the
message slot. This bit is cleared by writing "0" in software. However, it cannot be cleared when the
TRSTAT (Transmit/Receive Status) bit = "1".
Notes: • Before reading the received data out of the message slot, be sure to clear the TRFIN
(Transmit/Receive Finished) bit to "0". If the TRFIN (Transmit/Receive Finished) bit happens to be set to "1" after a read, it means that new received data was stored while
reading and the read data contains an undefined value. In that case, discard the read
data, clear the TRFIN bit to "0" and read out data again.
• When sending/receiving remote frames, the TRFIN bit is automatically cleared to "0" by
hardware. Therefore, the TRFIN bit cannot be used as a transmission/reception-finished
flag.
13-56
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
13.2.15 CAN Message Slots
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Standard ID0 (C0MSL0SID0)
Slot 1 Standard ID0 (C0MSL1SID0)
Slot 2 Standard ID0 (C0MSL2SID0)
Slot 3 Standard ID0 (C0MSL3SID0)
Slot 4 Standard ID0 (C0MSL4SID0)
Slot 5 Standard ID0 (C0MSL5SID0)
Slot 6 Standard ID0 (C0MSL6SID0)
Slot 7 Standard ID0 (C0MSL7SID0)
Slot 8 Standard ID0 (C0MSL8SID0)
Slot 9 Standard ID0 (C0MSL9SID0)
Slot 10 Standard ID0 (C0MSL10SID0)
Slot 11 Standard ID0 (C0MSL11SID0)
Slot 12 Standard ID0 (C0MSL12SID0)
Slot 13 Standard ID0 (C0MSL13SID0)
Slot 14 Standard ID0 (C0MSL14SID0)
Slot 15 Standard ID0 (C0MSL15SID0)
<Address: H’0080 1100>
<Address: H’0080 1110>
<Address: H’0080 1120>
<Address: H’0080 1130>
<Address: H’0080 1140>
<Address: H’0080 1150>
<Address: H’0080 1160>
<Address: H’0080 1170>
<Address: H’0080 1180>
<Address: H’0080 1190>
<Address: H’0080 11A0>
<Address: H’0080 11B0>
<Address: H’0080 11C0>
<Address: H’0080 11D0>
<Address: H’0080 11E0>
<Address: H’0080 11F0>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Standard ID0 (C1MSL0SID0)
Slot 1 Standard ID0 (C1MSL1SID0)
Slot 2 Standard ID0 (C1MSL2SID0)
Slot 3 Standard ID0 (C1MSL3SID0)
Slot 4 Standard ID0 (C1MSL4SID0)
Slot 5 Standard ID0 (C1MSL5SID0)
Slot 6 Standard ID0 (C1MSL6SID0)
Slot 7 Standard ID0 (C1MSL7SID0)
Slot 8 Standard ID0 (C1MSL8SID0)
Slot 9 Standard ID0 (C1MSL9SID0)
Slot 10 Standard ID0 (C1MSL10SID0)
Slot 11 Standard ID0 (C1MSL11SID0)
Slot 12 Standard ID0 (C1MSL12SID0)
Slot 13 Standard ID0 (C1MSL13SID0)
Slot 14 Standard ID0 (C1MSL14SID0)
Slot 15 Standard ID0 (C1MSL15SID0)
<Address: H’0080 1500>
<Address: H’0080 1510>
<Address: H’0080 1520>
<Address: H’0080 1530>
<Address: H’0080 1540>
<Address: H’0080 1550>
<Address: H’0080 1560>
<Address: H’0080 1570>
<Address: H’0080 1580>
<Address: H’0080 1590>
<Address: H’0080 15A0>
<Address: H’0080 15B0>
<Address: H’0080 15C0>
<Address: H’0080 15D0>
<Address: H’0080 15E0>
<Address: H’0080 15F0>
b0
?
1
?
2
?
3
4
5
6
b7
SID0
SID1
SID2
SID3
SID4
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–2
No function assigned. Fix to "0".
3–7
SID0–SID4
(Standard ID0–standard ID4)
Function
R
W
0
0
Standard ID0–standard ID4
R
W
These registers are the memory space for transmit and receive frames.
13-57
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Standard ID1 (C0MSL0SID1)
Slot 1 Standard ID1 (C0MSL1SID1)
Slot 2 Standard ID1 (C0MSL2SID1)
Slot 3 Standard ID1 (C0MSL3SID1)
Slot 4 Standard ID1 (C0MSL4SID1)
Slot 5 Standard ID1 (C0MSL5SID1)
Slot 6 Standard ID1 (C0MSL6SID1)
Slot 7 Standard ID1 (C0MSL7SID1)
Slot 8 Standard ID1 (C0MSL8SID1)
Slot 9 Standard ID1 (C0MSL9SID1)
Slot 10 Standard ID1 (C0MSL10SID1)
Slot 11 Standard ID1 (C0MSL11SID1)
Slot 12 Standard ID1 (C0MSL12SID1)
Slot 13 Standard ID1 (C0MSL13SID1)
Slot 14 Standard ID1 (C0MSL14SID1)
Slot 15 Standard ID1 (C0MSL15SID1)
<Address: H’0080 1101>
<Address: H’0080 1111>
<Address: H’0080 1121>
<Address: H’0080 1131>
<Address: H’0080 1141>
<Address: H’0080 1151>
<Address: H’0080 1161>
<Address: H’0080 1171>
<Address: H’0080 1181>
<Address: H’0080 1191>
<Address: H’0080 11A1>
<Address: H’0080 11B1>
<Address: H’0080 11C1>
<Address: H’0080 11D1>
<Address: H’0080 11E1>
<Address: H’0080 11F1>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Standard ID1 (C1MSL0SID1)
Slot 1 Standard ID1 (C1MSL1SID1)
Slot 2 Standard ID1 (C1MSL2SID1)
Slot 3 Standard ID1 (C1MSL3SID1)
Slot 4 Standard ID1 (C1MSL4SID1)
Slot 5 Standard ID1 (C1MSL5SID1)
Slot 6 Standard ID1 (C1MSL6SID1)
Slot 7 Standard ID1 (C1MSL7SID1)
Slot 8 Standard ID1 (C1MSL8SID1)
Slot 9 Standard ID1 (C1MSL9SID1)
Slot 10 Standard ID1 (C1MSL10SID1)
Slot 11 Standard ID1 (C1MSL11SID1)
Slot 12 Standard ID1 (C1MSL12SID1)
Slot 13 Standard ID1 (C1MSL13SID1)
Slot 14 Standard ID1 (C1MSL14SID1)
Slot 15 Standard ID1 (C1MSL15SID1)
<Address: H’0080 1501>
<Address: H’0080 1511>
<Address: H’0080 1521>
<Address: H’0080 1531>
<Address: H’0080 1541>
<Address: H’0080 1551>
<Address: H’0080 1561>
<Address: H’0080 1571>
<Address: H’0080 1581>
<Address: H’0080 1591>
<Address: H’0080 15A1>
<Address: H’0080 15B1>
<Address: H’0080 15C1>
<Address: H’0080 15D1>
<Address: H’0080 15E1>
<Address: H’0080 15F1>
b8
?
9
10
11
12
13
14
b15
SID5
SID6
SID7
SID8
SID9
SID10
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
8, 9
No function assigned. Fix to "0".
10–15
SID5–SID10
Function
Standard ID5–standard ID10
R
W
0
0
R
W
(Standard ID5–standard ID10)
These registers are the memory space for transmit and receive frames.
13-58
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Extended ID0 (C0MSL0EID0)
1 Extended ID0 (C0MSL1EID0)
2 Extended ID0 (C0MSL2EID0)
3 Extended ID0 (C0MSL3EID0)
4 Extended ID0 (C0MSL4EID0)
5 Extended ID0 (C0MSL5EID0)
6 Extended ID0 (C0MSL6EID0)
7 Extended ID0 (C0MSL7EID0)
8 Extended ID0 (C0MSL8EID0)
9 Extended ID0 (C0MSL9EID0)
10 Extended ID0 (C0MSL10EID0)
11 Extended ID0 (C0MSL11EID0)
12 Extended ID0 (C0MSL12EID0)
13 Extended ID0 (C0MSL13EID0)
14 Extended ID0 (C0MSL14EID0)
15 Extended ID0 (C0MSL15EID0)
<Address: H’0080 1102>
<Address: H’0080 1112>
<Address: H’0080 1122>
<Address: H’0080 1132>
<Address: H’0080 1142>
<Address: H’0080 1152>
<Address: H’0080 1162>
<Address: H’0080 1172>
<Address: H’0080 1182>
<Address: H’0080 1192>
<Address: H’0080 11A2>
<Address: H’0080 11B2>
<Address: H’0080 11C2>
<Address: H’0080 11D2>
<Address: H’0080 11E2>
<Address: H’0080 11F2>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Extended ID0 (C1MSL0EID0)
1 Extended ID0 (C1MSL1EID0)
2 Extended ID0 (C1MSL2EID0)
3 Extended ID0 (C1MSL3EID0)
4 Extended ID0 (C1MSL4EID0)
5 Extended ID0 (C1MSL5EID0)
6 Extended ID0 (C1MSL6EID0)
7 Extended ID0 (C1MSL7EID0)
8 Extended ID0 (C1MSL8EID0)
9 Extended ID0 (C1MSL9EID0)
10 Extended ID0 (C1MSL10EID0)
11 Extended ID0 (C1MSL11EID0)
12 Extended ID0 (C1MSL12EID0)
13 Extended ID0 (C1MSL13EID0)
14 Extended ID0 (C1MSL14EID0)
15 Extended ID0 (C1MSL15EID0)
<Address: H’0080 1502>
<Address: H’0080 1512>
<Address: H’0080 1522>
<Address: H’0080 1532>
<Address: H’0080 1542>
<Address: H’0080 1552>
<Address: H’0080 1562>
<Address: H’0080 1572>
<Address: H’0080 1582>
<Address: H’0080 1592>
<Address: H’0080 15A2>
<Address: H’0080 15B2>
<Address: H’0080 15C2>
<Address: H’0080 15D2>
<Address: H’0080 15E2>
<Address: H’0080 15F2>
b0
?
1
?
2
?
3
?
4
5
6
b7
EID0
EID1
EID2
EID3
?
?
?
?
<After reset: Undefined>
b
Bit Name
0–3
No function assigned. Fix to "0".
4–7
EID0–EID3
Function
Extended ID0–extended ID3
R
W
0
0
R
W
(Extended ID0–extended ID3)
These registers are the memory space for transmit and receive frames.
Note: • If the message slot is set for the receive slot standard ID format, an undefined value is written to
the EID bits when storing received data.
13-59
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Extended ID1 (C0MSL0EID1)
1 Extended ID1 (C0MSL1EID1)
2 Extended ID1 (C0MSL2EID1)
3 Extended ID1 (C0MSL3EID1)
4 Extended ID1 (C0MSL4EID1)
5 Extended ID1 (C0MSL5EID1)
6 Extended ID1 (C0MSL6EID1)
7 Extended ID1 (C0MSL7EID1)
8 Extended ID1 (C0MSL8EID1)
9 Extended ID1 (C0MSL9EID1)
10 Extended ID1 (C0MSL10EID1)
11 Extended ID1 (C0MSL11EID1)
12 Extended ID1 (C0MSL12EID1)
13 Extended ID1 (C0MSL13EID1)
14 Extended ID1 (C0MSL14EID1)
15 Extended ID1 (C0MSL15EID1)
<Address: H’0080 1103>
<Address: H’0080 1113>
<Address: H’0080 1123>
<Address: H’0080 1133>
<Address: H’0080 1143>
<Address: H’0080 1153>
<Address: H’0080 1163>
<Address: H’0080 1173>
<Address: H’0080 1183>
<Address: H’0080 1193>
<Address: H’0080 11A3>
<Address: H’0080 11B3>
<Address: H’0080 11C3>
<Address: H’0080 11D3>
<Address: H’0080 11E3>
<Address: H’0080 11F3>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Extended ID1 (C1MSL0EID1)
1 Extended ID1 (C1MSL1EID1)
2 Extended ID1 (C1MSL2EID1)
3 Extended ID1 (C1MSL3EID1)
4 Extended ID1 (C1MSL4EID1)
5 Extended ID1 (C1MSL5EID1)
6 Extended ID1 (C1MSL6EID1)
7 Extended ID1 (C1MSL7EID1)
8 Extended ID1 (C1MSL8EID1)
9 Extended ID1 (C1MSL9EID1)
10 Extended ID1 (C1MSL10EID1)
11 Extended ID1 (C1MSL11EID1)
12 Extended ID1 (C1MSL12EID1)
13 Extended ID1 (C1MSL13EID1)
14 Extended ID1 (C1MSL14EID1)
15 Extended ID1 (C1MSL15EID1)
<Address: H’0080 1503>
<Address: H’0080 1513>
<Address: H’0080 1523>
<Address: H’0080 1533>
<Address: H’0080 1543>
<Address: H’0080 1553>
<Address: H’0080 1563>
<Address: H’0080 1573>
<Address: H’0080 1583>
<Address: H’0080 1593>
<Address: H’0080 15A3>
<Address: H’0080 15B3>
<Address: H’0080 15C3>
<Address: H’0080 15D3>
<Address: H’0080 15E3>
<Address: H’0080 15F3>
b8
9
10
11
12
13
14
b15
EID4
EID5
EID6
EID7
EID8
EID9
EID10
EID11
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
8–15
EID4–EID11
(Extended ID4–extended ID11)
Extended ID4–extended ID11
R
W
These registers are the memory space for transmit and receive frames.
Note: • If the message slot is set for the receive slot standard ID format, an undefined value is written to
the EID bits when storing received data.
13-60
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Extended ID2 (C0MSL0EID2)
1 Extended ID2 (C0MSL1EID2)
2 Extended ID2 (C0MSL2EID2)
3 Extended ID2 (C0MSL3EID2)
4 Extended ID2 (C0MSL4EID2)
5 Extended ID2 (C0MSL5EID2)
6 Extended ID2 (C0MSL6EID2)
7 Extended ID2 (C0MSL7EID2)
8 Extended ID2 (C0MSL8EID2)
9 Extended ID2 (C0MSL9EID2)
10 Extended ID2 (C0MSL10EID2)
11 Extended ID2 (C0MSL11EID2)
12 Extended ID2 (C0MSL12EID2)
13 Extended ID2 (C0MSL13EID2)
14 Extended ID2 (C0MSL14EID2)
15 Extended ID2 (C0MSL15EID2)
<Address: H’0080 1104>
<Address: H’0080 1114>
<Address: H’0080 1124>
<Address: H’0080 1134>
<Address: H’0080 1144>
<Address: H’0080 1154>
<Address: H’0080 1164>
<Address: H’0080 1174>
<Address: H’0080 1184>
<Address: H’0080 1194>
<Address: H’0080 11A4>
<Address: H’0080 11B4>
<Address: H’0080 11C4>
<Address: H’0080 11D4>
<Address: H’0080 11E4>
<Address: H’0080 11F4>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Extended ID2 (C1MSL0EID2)
1 Extended ID2 (C1MSL1EID2)
2 Extended ID2 (C1MSL2EID2)
3 Extended ID2 (C1MSL3EID2)
4 Extended ID2 (C1MSL4EID2)
5 Extended ID2 (C1MSL5EID2)
6 Extended ID2 (C1MSL6EID2)
7 Extended ID2 (C1MSL7EID2)
8 Extended ID2 (C1MSL8EID2)
9 Extended ID2 (C1MSL9EID2)
10 Extended ID2 (C1MSL10EID2)
11 Extended ID2 (C1MSL11EID2)
12 Extended ID2 (C1MSL12EID2)
13 Extended ID2 (C1MSL13EID2)
14 Extended ID2 (C1MSL14EID2)
15 Extended ID2 (C1MSL15EID2)
<Address: H’0080 1504>
<Address: H’0080 1514>
<Address: H’0080 1524>
<Address: H’0080 1534>
<Address: H’0080 1544>
<Address: H’0080 1554>
<Address: H’0080 1564>
<Address: H’0080 1574>
<Address: H’0080 1584>
<Address: H’0080 1594>
<Address: H’0080 15A4>
<Address: H’0080 15B4>
<Address: H’0080 15C4>
<Address: H’0080 15D4>
<Address: H’0080 15E4>
<Address: H’0080 15F4>
b0
?
1
2
3
4
5
6
b7
EID12
EID13
EID14
EID15
EID16
EID17
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
0, 1
No function assigned. Fix to "0".
2–7
EID12–EID17
Function
Extended ID12–extended ID17
R
W
0
0
R
W
(Extended ID12–extended ID17)
These registers are the memory space for transmit and receive frames.
Note: • If the message slot is set for the receive slot standard ID format, an undefined value is written to
the EID bits when storing received data.
13-61
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data Length Register (C0MSL0DLC)
Slot 1 Data Length Register (C0MSL1DLC)
Slot 2 Data Length Register (C0MSL2DLC)
Slot 3 Data Length Register (C0MSL3DLC)
Slot 4 Data Length Register (C0MSL4DLC)
Slot 5 Data Length Register (C0MSL5DLC)
Slot 6 Data Length Register (C0MSL6DLC)
Slot 7 Data Length Register (C0MSL7DLC)
Slot 8 Data Length Register (C0MSL8DLC)
Slot 9 Data Length Register (C0MSL9DLC)
Slot 10 Data Length Register (C0MSL10DLC)
Slot 11 Data Length Register (C0MSL11DLC)
Slot 12 Data Length Register (C0MSL12DLC)
Slot 13 Data Length Register (C0MSL13DLC)
Slot 14 Data Length Register (C0MSL14DLC)
Slot 15 Data Length Register (C0MSL15DLC)
<Address: H’0080 1105>
<Address: H’0080 1115>
<Address: H’0080 1125>
<Address: H’0080 1135>
<Address: H’0080 1145>
<Address: H’0080 1155>
<Address: H’0080 1165>
<Address: H’0080 1175>
<Address: H’0080 1185>
<Address: H’0080 1195>
<Address: H’0080 11A5>
<Address: H’0080 11B5>
<Address: H’0080 11C5>
<Address: H’0080 11D5>
<Address: H’0080 11E5>
<Address: H’0080 11F5>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data Length Register (C1MSL0DLC)
Slot 1 Data Length Register (C1MSL1DLC)
Slot 2 Data Length Register (C1MSL2DLC)
Slot 3 Data Length Register (C1MSL3DLC)
Slot 4 Data Length Register (C1MSL4DLC)
Slot 5 Data Length Register (C1MSL5DLC)
Slot 6 Data Length Register (C1MSL6DLC)
Slot 7 Data Length Register (C1MSL7DLC)
Slot 8 Data Length Register (C1MSL8DLC)
Slot 9 Data Length Register (C1MSL9DLC)
Slot 10 Data Length Register (C1MSL10DLC)
Slot 11 Data Length Register (C1MSL11DLC)
Slot 12 Data Length Register (C1MSL12DLC)
Slot 13 Data Length Register (C1MSL13DLC)
Slot 14 Data Length Register (C1MSL14DLC)
Slot 15 Data Length Register (C1MSL15DLC)
<Address: H’0080 1505>
<Address: H’0080 1515>
<Address: H’0080 1525>
<Address: H’0080 1535>
<Address: H’0080 1545>
<Address: H’0080 1555>
<Address: H’0080 1565>
<Address: H’0080 1575>
<Address: H’0080 1585>
<Address: H’0080 1595>
<Address: H’0080 15A5>
<Address: H’0080 15B5>
<Address: H’0080 15C5>
<Address: H’0080 15D5>
<Address: H’0080 15E5>
<Address: H’0080 15F5>
b8
?
9
?
10
?
11
?
12
13
14
b15
DLC0
DLC1
DLC2
DLC3
?
?
?
?
<After reset: Undefined>
b
Bit Name
8–11
No function assigned. Fix to "0".
12–15
DLC0–DLC3
Data length setting bit
Function
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
|
0
1
2
3
4
5
6
7
8
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
|
R
W
0
0
R
W
1111: 8 bytes
These registers are the memory space for transmit and receive frames. When sending, the register is used to
set the transmit data length. When receiving, the register is used to store the receive frame DLC.
13-62
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 0 (C0MSL0DT0)
1 Data 0 (C0MSL1DT0)
2 Data 0 (C0MSL2DT0)
3 Data 0 (C0MSL3DT0)
4 Data 0 (C0MSL4DT0)
5 Data 0 (C0MSL5DT0)
6 Data 0 (C0MSL6DT0)
7 Data 0 (C0MSL7DT0)
8 Data 0 (C0MSL8DT0)
9 Data 0 (C0MSL9DT0)
10 Data 0 (C0MSL10DT0)
11 Data 0 (C0MSL11DT0)
12 Data 0 (C0MSL12DT0)
13 Data 0 (C0MSL13DT0)
14 Data 0 (C0MSL14DT0)
15 Data 0 (C0MSL15DT0)
<Address: H’0080 1106>
<Address: H’0080 1116>
<Address: H’0080 1126>
<Address: H’0080 1136>
<Address: H’0080 1146>
<Address: H’0080 1156>
<Address: H’0080 1166>
<Address: H’0080 1176>
<Address: H’0080 1186>
<Address: H’0080 1196>
<Address: H’0080 11A6>
<Address: H’0080 11B6>
<Address: H’0080 11C6>
<Address: H’0080 11D6>
<Address: H’0080 11E6>
<Address: H’0080 11F6>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 0 (C1MSL0DT0)
1 Data 0 (C1MSL1DT0)
2 Data 0 (C1MSL2DT0)
3 Data 0 (C1MSL3DT0)
4 Data 0 (C1MSL4DT0)
5 Data 0 (C1MSL5DT0)
6 Data 0 (C1MSL6DT0)
7 Data 0 (C1MSL7DT0)
8 Data 0 (C1MSL8DT0)
9 Data 0 (C1MSL9DT0)
10 Data 0 (C1MSL10DT0)
11 Data 0 (C1MSL11DT0)
12 Data 0 (C1MSL12DT0)
13 Data 0 (C1MSL13DT0)
14 Data 0 (C1MSL14DT0)
15 Data 0 (C1MSL15DT0)
<Address: H’0080 1506>
<Address: H’0080 1516>
<Address: H’0080 1526>
<Address: H’0080 1536>
<Address: H’0080 1546>
<Address: H’0080 1556>
<Address: H’0080 1566>
<Address: H’0080 1576>
<Address: H’0080 1586>
<Address: H’0080 1596>
<Address: H’0080 15A6>
<Address: H’0080 15B6>
<Address: H’0080 15C6>
<Address: H’0080 15D6>
<Address: H’0080 15E6>
<Address: H’0080 15F6>
D0
1
2
3
4
5
6
D7
C0MSL0DT0–C0MSL15DT0, C1MSL0DT0–C1MSL15DT0
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–7
C0MSL0DT0–C0MSL15DT0,
C1MSL0DT0–C1MSL15DT0
Message slot data 0
R
W
These registers are the memory space for transmit and receive frames.
Notes: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) = "0".
• The first byte of the CAN frame data field corresponds to message slot n data 0. Data is transmitted or received beginning with the MSB side of the register.
13-63
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 1 (C0MSL0DT1)
1 Data 1 (C0MSL1DT1)
2 Data 1 (C0MSL2DT1)
3 Data 1 (C0MSL3DT1)
4 Data 1 (C0MSL4DT1)
5 Data 1 (C0MSL5DT1)
6 Data 1 (C0MSL6DT1)
7 Data 1 (C0MSL7DT1)
8 Data 1 (C0MSL8DT1)
9 Data 1 (C0MSL9DT1)
10 Data 1 (C0MSL10DT1)
11 Data 1 (C0MSL11DT1)
12 Data 1 (C0MSL12DT1)
13 Data 1 (C0MSL13DT1)
14 Data 1 (C0MSL14DT1)
15 Data 1 (C0MSL15DT1)
<Address: H’0080 1107>
<Address: H’0080 1117>
<Address: H’0080 1127>
<Address: H’0080 1137>
<Address: H’0080 1147>
<Address: H’0080 1157>
<Address: H’0080 1167>
<Address: H’0080 1177>
<Address: H’0080 1187>
<Address: H’0080 1197>
<Address: H’0080 11A7>
<Address: H’0080 11B7>
<Address: H’0080 11C7>
<Address: H’0080 11D7>
<Address: H’0080 11E7>
<Address: H’0080 11F7>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 1 (C1MSL0DT1)
1 Data 1 (C1MSL1DT1)
2 Data 1 (C1MSL2DT1)
3 Data 1 (C1MSL3DT1)
4 Data 1 (C1MSL4DT1)
5 Data 1 (C1MSL5DT1)
6 Data 1 (C1MSL6DT1)
7 Data 1 (C1MSL7DT1)
8 Data 1 (C1MSL8DT1)
9 Data 1 (C1MSL9DT1)
10 Data 1 (C1MSL10DT1)
11 Data 1 (C1MSL11DT1)
12 Data 1 (C1MSL12DT1)
13 Data 1 (C1MSL13DT1)
14 Data 1 (C1MSL14DT1)
15 Data 1 (C1MSL15DT1)
<Address: H’0080 1507>
<Address: H’0080 1517>
<Address: H’0080 1527>
<Address: H’0080 1537>
<Address: H’0080 1547>
<Address: H’0080 1557>
<Address: H’0080 1567>
<Address: H’0080 1577>
<Address: H’0080 1587>
<Address: H’0080 1597>
<Address: H’0080 15A7>
<Address: H’0080 15B7>
<Address: H’0080 15C7>
<Address: H’0080 15D7>
<Address: H’0080 15E7>
<Address: H’0080 15F7>
b8
9
10
11
12
13
14
b15
C0MSL0DT1–C0MSL15DT1, C1MSL0DT1–C1MSL15DT1
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
8–15
C0MSL0DT1–C0MSL15DT1,
C1MSL0DT1–C1MSL15DT1
Message slot data 1
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 1.
13-64
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 2 (C0MSL0DT2)
1 Data 2 (C0MSL1DT2)
2 Data 2 (C0MSL2DT2)
3 Data 2 (C0MSL3DT2)
4 Data 2 (C0MSL4DT2)
5 Data 2 (C0MSL5DT2)
6 Data 2 (C0MSL6DT2)
7 Data 2 (C0MSL7DT2)
8 Data 2 (C0MSL8DT2)
9 Data 2 (C0MSL9DT2)
10 Data 2 (C0MSL10DT2)
11 Data 2 (C0MSL11DT2)
12 Data 2 (C0MSL12DT2)
13 Data 2 (C0MSL13DT2)
14 Data 2 (C0MSL14DT2)
15 Data 2 (C0MSL15DT2)
<Address: H’0080 1108>
<Address: H’0080 1118>
<Address: H’0080 1128>
<Address: H’0080 1138>
<Address: H’0080 1148>
<Address: H’0080 1158>
<Address: H’0080 1168>
<Address: H’0080 1178>
<Address: H’0080 1188>
<Address: H’0080 1198>
<Address: H’0080 11A8>
<Address: H’0080 11B8>
<Address: H’0080 11C8>
<Address: H’0080 11D8>
<Address: H’0080 11E8>
<Address: H’0080 11F8>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 2 (C1MSL0DT2)
1 Data 2 (C1MSL1DT2)
2 Data 2 (C1MSL2DT2)
3 Data 2 (C1MSL3DT2)
4 Data 2 (C1MSL4DT2)
5 Data 2 (C1MSL5DT2)
6 Data 2 (C1MSL6DT2)
7 Data 2 (C1MSL7DT2)
8 Data 2 (C1MSL8DT2)
9 Data 2 (C1MSL9DT2)
10 Data 2 (C1MSL10DT2)
11 Data 2 (C1MSL11DT2)
12 Data 2 (C1MSL12DT2)
13 Data 2 (C1MSL13DT2)
14 Data 2 (C1MSL14DT2)
15 Data 2 (C1MSL15DT2)
<Address: H’0080 1508>
<Address: H’0080 1518>
<Address: H’0080 1528>
<Address: H’0080 1538>
<Address: H’0080 1548>
<Address: H’0080 1558>
<Address: H’0080 1568>
<Address: H’0080 1578>
<Address: H’0080 1588>
<Address: H’0080 1598>
<Address: H’0080 15A8>
<Address: H’0080 15B8>
<Address: H’0080 15C8>
<Address: H’0080 15D8>
<Address: H’0080 15E8>
<Address: H’0080 15F8>
b0
1
2
3
4
5
6
b7
C0MSL0DT2–C0MSL15DT2, C1MSL0DT2–C1MSL15DT2
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–7
C0MSL0DT2–C0MSL15DT2,
C1MSL0DT2–C1MSL15DT2
Message slot data 2
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 2.
13-65
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 3 (C0MSL0DT3)
1 Data 3 (C0MSL1DT3)
2 Data 3 (C0MSL2DT3)
3 Data 3 (C0MSL3DT3)
4 Data 3 (C0MSL4DT3)
5 Data 3 (C0MSL5DT3)
6 Data 3 (C0MSL6DT3)
7 Data 3 (C0MSL7DT3)
8 Data 3 (C0MSL8DT3)
9 Data 3 (C0MSL9DT3)
10 Data 3 (C0MSL10DT3)
11 Data 3 (C0MSL11DT3)
12 Data 3 (C0MSL12DT3)
13 Data 3 (C0MSL13DT3)
14 Data 3 (C0MSL14DT3)
15 Data 3 (C0MSL15DT3)
<Address: H’0080 1109>
<Address: H’0080 1119>
<Address: H’0080 1129>
<Address: H’0080 1139>
<Address: H’0080 1149>
<Address: H’0080 1159>
<Address: H’0080 1169>
<Address: H’0080 1179>
<Address: H’0080 1189>
<Address: H’0080 1199>
<Address: H’0080 11A9>
<Address: H’0080 11B9>
<Address: H’0080 11C9>
<Address: H’0080 11D9>
<Address: H’0080 11E9>
<Address: H’0080 11F9>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
0 Data 3 (C1MSL0DT3)
1 Data 3 (C1MSL1DT3)
2 Data 3 (C1MSL2DT3)
3 Data 3 (C1MSL3DT3)
4 Data 3 (C1MSL4DT3)
5 Data 3 (C1MSL5DT3)
6 Data 3 (C1MSL6DT3)
7 Data 3 (C1MSL7DT3)
8 Data 3 (C1MSL8DT3)
9 Data 3 (C1MSL9DT3)
10 Data 3 (C1MSL10DT3)
11 Data 3 (C1MSL11DT3)
12 Data 3 (C1MSL12DT3)
13 Data 3 (C1MSL13DT3)
14 Data 3 (C1MSL14DT3)
15 Data 3 (C1MSL15DT3)
<Address: H’0080 1509>
<Address: H’0080 1519>
<Address: H’0080 1529>
<Address: H’0080 1539>
<Address: H’0080 1549>
<Address: H’0080 1559>
<Address: H’0080 1569>
<Address: H’0080 1579>
<Address: H’0080 1589>
<Address: H’0080 1599>
<Address: H’0080 15A9>
<Address: H’0080 15B9>
<Address: H’0080 15C9>
<Address: H’0080 15D9>
<Address: H’0080 15E9>
<Address: H’0080 15F9>
b8
9
10
11
12
13
14
b15
C0MSL0DT3–C0MSL15DT3, C1MSL0DT3–C1MSL15DT3
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
8–15
C0MSL0DT3–C0MSL15DT3,
C1MSL0DT3–C1MSL15DT3
Message slot data 3
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 3.
13-66
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data 4 (C0MSL0DT4)
Slot 1 Data 4 (C0MSL1DT4)
Slot 2 Data 4 (C0MSL2DT4)
Slot 3 Data 4 (C0MSL3DT4)
Slot 4 Data 4 (C0MSL4DT4)
Slot 5 Data 4 (C0MSL5DT4)
Slot 6 Data 4 (C0MSL6DT4)
Slot 7 Data 4 (C0MSL7DT4)
Slot 8 Data 4 (C0MSL8DT4)
Slot 9 Data 4 (C0MSL9DT4)
Slot 10 Data 4 (C0MSL10DT4)
Slot 11 Data 4 (C0MSL11DT4)
Slot 12 Data 4 (C0MSL12DT4)
Slot 13 Data 4 (C0MSL13DT4)
Slot 14 Data 4 (C0MSL14DT4)
Slot 15 Data 4 (C0MSL15DT4)
<Address: H’0080 110A>
<Address: H’0080 111A>
<Address: H’0080 112A>
<Address: H’0080 113A>
<Address: H’0080 114A>
<Address: H’0080 115A>
<Address: H’0080 116A>
<Address: H’0080 117A>
<Address: H’0080 118A>
<Address: H’0080 119A>
<Address: H’0080 11AA>
<Address: H’0080 11BA>
<Address: H’0080 11CA>
<Address: H’0080 11DA>
<Address: H’0080 11EA>
<Address: H’0080 11FA>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data 4 (C1MSL0DT4)
Slot 1 Data 4 (C1MSL1DT4)
Slot 2 Data 4 (C1MSL2DT4)
Slot 3 Data 4 (C1MSL3DT4)
Slot 4 Data 4 (C1MSL4DT4)
Slot 5 Data 4 (C1MSL5DT4)
Slot 6 Data 4 (C1MSL6DT4)
Slot 7 Data 4 (C1MSL7DT4)
Slot 8 Data 4 (C1MSL8DT4)
Slot 9 Data 4 (C1MSL9DT4)
Slot 10 Data 4 (C1MSL10DT4)
Slot 11 Data 4 (C1MSL11DT4)
Slot 12 Data 4 (C1MSL12DT4)
Slot 13 Data 4 (C1MSL13DT4)
Slot 14 Data 4 (C1MSL14DT4)
Slot 15 Data 4 (C1MSL15DT4)
<Address: H’0080 150A>
<Address: H’0080 151A>
<Address: H’0080 152A>
<Address: H’0080 153A>
<Address: H’0080 154A>
<Address: H’0080 155A>
<Address: H’0080 156A>
<Address: H’0080 157A>
<Address: H’0080 158A>
<Address: H’0080 159A>
<Address: H’0080 15AA>
<Address: H’0080 15BA>
<Address: H’0080 15CA>
<Address: H’0080 15DA>
<Address: H’0080 15EA>
<Address: H’0080 15FA>
b0
1
2
3
4
5
6
b7
C0MSL0DT4–C0MSL15DT4, C1MSL0DT4–C1MSL15DT4
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–7
C0MSL0DT4–C0MSL15DT4,
C1MSL0DT4–C1MSL15DT4
Message slot data 4
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 4.
13-67
32182 Group User’s Manual (Rev.1.0)
CAN MODULE
13
13.2 CAN Module Related Registers
CAN0 Message Slot 0 Data 5 (C0MSL0DT5)
CAN0 Message Slot 1 Data 5 (C0MSL1DT5)
CAN0 Message Slot 2 Data 5 (C0MSL2DT5)
CAN0 Message Slot 3 Data 5 (C0MSL3DT5)
CAN0 Message Slot 4 Data 5 (C0MSL4DT5)
CAN0 Message Slot 5 Data 5 (C0MSL5DT5)
CAN0 Message Slot 6 Data 5 (C0MSL6DT5)
CAN0 Message Slot 7 Data 5 (C0MSL7DT5)
CAN0 Message Slot 8 Data 5 (C0MSL8DT5)
CAN0 Message Slot 9 Data 5 (C0MSL9DT5)
CAN0 Message Slot 10 Data 5 (C0MSL10DT5)
CAN0 Message Slot 11 Data 5 (C0MSL11DT5)
CAN0 Message Slot 12 Data 5 (C0MSL12DT5)
CAN0 Message Slot 13 Data 5 (C0MSL13DT5)
CAN0 Message Slot 14 Data 5 (C0MSL14DT5)
CAN0 Message Slot 15 Data 5 (C0MSL15DT5)
<Address: H’0080 110B>
<Address: H’0080 111B>
<Address: H’0080 112B>
<Address: H’0080 113B>
<Address: H’0080 114B>
<Address: H’0080 115B>
<Address: H’0080 116B>
<Address: H’0080 117B>
<Address: H’0080 118B>
<Address: H’0080 119B>
<Address: H’0080 11AB>
<Address: H’0080 11BB>
<Address: H’0080 11CB>
<Address: H’0080 11DB>
<Address: H’0080 11EB>
<Address: H’0080 11FB>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
<Address: H’0080 150B>
<Address: H’0080 151B>
<Address: H’0080 152B>
<Address: H’0080 153B>
<Address: H’0080 154B>
<Address: H’0080 155B>
<Address: H’0080 156B>
<Address: H’0080 157B>
<Address: H’0080 158B>
<Address: H’0080 159B>
<Address: H’0080 15AB>
<Address: H’0080 15BB>
<Address: H’0080 15CB>
<Address: H’0080 15DB>
<Address: H’0080 15EB>
<Address: H'0080 15FB>
Message Slot 0 Data 5 (C1MSL0DT5)
Message Slot 1 Data 5 (C1MSL1DT5)
Message Slot 2 Data 5 (C1MSL2DT5)
Message Slot 3 Data 5 (C1MSL3DT5)
Message Slot 4 Data 5 (C1MSL4DT5)
Message Slot 5 Data 5 (C1MSL5DT5)
Message Slot 6 Data 5 (C1MSL6DT5)
Message Slot 7 Data 5 (C1MSL7DT5)
Message Slot 8 Data 5 (C1MSL8DT5)
Message Slot 9 Data 5 (C1MSL9DT5)
Message Slot 10 Data 5 (C1MSL10DT5)
Message Slot 11 Data 5 (C1MSL11DT5)
Message Slot 12 Data 5 (C1MSL12DT5)
Message Slot 13 Data 5 (C1MSL13DT5)
Message Slot 14 Data 5 (C1MSL14DT5)
Message Slot 15 Data 5 (C1MSL15DT5)
b8
9
10
11
12
13
14
b15
C0MSL0DT5–C0MSL15DT5, C1MSL0DT5–C1MSL15DT5
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
8–15
C0MSL0DT5–C0MSL15DT5,
C1MSL0DT5–C1MSL15DT5
Message slot data 5
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 5.
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13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data 6 (C0MSL0DT6)
Slot 1 Data 6 (C0MSL1DT6)
Slot 2 Data 6 (C0MSL2DT6)
Slot 3 Data 6 (C0MSL3DT6)
Slot 4 Data 6 (C0MSL4DT6)
Slot 5 Data 6 (C0MSL5DT6)
Slot 6 Data 6 (C0MSL6DT6)
Slot 7 Data 6 (C0MSL7DT6)
Slot 8 Data 6 (C0MSL8DT6)
Slot 9 Data 6 (C0MSL9DT6)
Slot 10 Data 6 (C0MSL10DT6)
Slot 11 Data 6 (C0MSL11DT6)
Slot 12 Data 6 (C0MSL12DT6)
Slot 13 Data 6 (C0MSL13DT6)
Slot 14 Data 6 (C0MSL14DT6)
Slot 15 Data 6 (C0MSL15DT6)
<Address: H’0080 110C>
<Address: H’0080 111C>
<Address: H’0080 112C>
<Address: H’0080 113C>
<Address: H’0080 114C>
<Address: H’0080 115C>
<Address: H’0080 116C>
<Address: H’0080 117C>
<Address: H’0080 118C>
<Address: H’0080 119C>
<Address: H’0080 11AC>
<Address: H’0080 11BC>
<Address: H’0080 11CC>
<Address: H’0080 11DC>
<Address: H’0080 11EC>
<Address: H’0080 11FC>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data 6 (C1MSL0DT6)
Slot 1 Data 6 (C1MSL1DT6)
Slot 2 Data 6 (C1MSL2DT6)
Slot 3 Data 6 (C1MSL3DT6)
Slot 4 Data 6 (C1MSL4DT6)
Slot 5 Data 6 (C1MSL5DT6)
Slot 6 Data 6 (C1MSL6DT6)
Slot 7 Data 6 (C1MSL7DT6)
Slot 8 Data 6 (C1MSL8DT6)
Slot 9 Data 6 (C1MSL9DT6)
Slot 10 Data 6 (C1MSL10DT6)
Slot 11 Data 6 (C1MSL11DT6)
Slot 12 Data 6 (C1MSL12DT6)
Slot 13 Data 6 (C1MSL13DT6)
Slot 14 Data 6 (C1MSL14DT6)
Slot 15 Data 6 (C1MSL15DT6)
<Address: H’0080 150C>
<Address: H’0080 151C>
<Address: H’0080 152C>
<Address: H’0080 153C>
<Address: H’0080 154C>
<Address: H’0080 155C>
<Address: H’0080 156C>
<Address: H’0080 157C>
<Address: H’0080 158C>
<Address: H’0080 159C>
<Address: H’0080 15AC>
<Address: H’0080 15BC>
<Address: H’0080 15CC>
<Address: H’0080 15DC>
<Address: H’0080 15EC>
<Address: H’0080 15FC>
b0
1
2
3
4
5
6
b7
C0MSL0DT6–C0MSL15DT6, C1MSL0DT6–C1MSL15DT6
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–7
C0MSL0DT6–C0MSL15DT6,
C1MSL0DT6–C1MSL15DT6
Message slot data 6
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 6.
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13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data 7 (C0MSL0DT7)
Slot 1 Data 7 (C0MSL1DT7)
Slot 2 Data 7 (C0MSL2DT7)
Slot 3 Data 7 (C0MSL3DT7)
Slot 4 Data 7 (C0MSL4DT7)
Slot 5 Data 7 (C0MSL5DT7)
Slot 6 Data 7 (C0MSL6DT7)
Slot 7 Data 7 (C0MSL7DT7)
Slot 8 Data 7 (C0MSL8DT7)
Slot 9 Data 7 (C0MSL9DT7)
Slot 10 Data 7 (C0MSL10DT7)
Slot 11 Data 7 (C0MSL11DT7)
Slot 12 Data 7 (C0MSL12DT7)
Slot 13 Data 7 (C0MSL13DT7)
Slot 14 Data 7 (C0MSL14DT7)
Slot 15 Data 7 (C0MSL15DT7)
<Address: H’0080 110D>
<Address: H’0080 111D>
<Address: H’0080 112D>
<Address: H’0080 113D>
<Address: H’0080 114D>
<Address: H’0080 115D>
<Address: H’0080 116D>
<Address: H’0080 117D>
<Address: H’0080 118D>
<Address: H’0080 119D>
<Address: H’0080 11AD>
<Address: H’0080 11BD>
<Address: H’0080 11CD>
<Address: H’0080 11DD>
<Address: H’0080 11ED>
<Address: H’0080 11FD>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Message
Slot 0 Data 7 (C1MSL0DT7)
Slot 1 Data 7 (C1MSL1DT7)
Slot 2 Data 7 (C1MSL2DT7)
Slot 3 Data 7 (C1MSL3DT7)
Slot 4 Data 7 (C1MSL4DT7)
Slot 5 Data 7 (C1MSL5DT7)
Slot 6 Data 7 (C1MSL6DT7)
Slot 7 Data 7 (C1MSL7DT7)
Slot 8 Data 7 (C1MSL8DT7)
Slot 9 Data 7 (C1MSL9DT7)
Slot 10 Data 7 (C1MSL10DT7)
Slot 11 Data 7 (C1MSL11DT7)
Slot 12 Data 7 (C1MSL12DT7)
Slot 13 Data 7 (C1MSL13DT7)
Slot 14 Data 7 (C1MSL14DT7)
Slot 15 Data 7 (C1MSL15DT7)
<Address: H’0080 150D>
<Address: H’0080 151D>
<Address: H’0080 152D>
<Address: H’0080 153D>
<Address: H’0080 154D>
<Address: H’0080 155D>
<Address: H’0080 156D>
<Address: H’0080 157D>
<Address: H’0080 158D>
<Address: H’0080 159D>
<Address: H’0080 15AD>
<Address: H’0080 15BD>
<Address: H’0080 15CD>
<Address: H’0080 15DD>
<Address: H’0080 15ED>
<Address: H’0080 15FD>
b8
9
10
11
12
13
14
b15
C0MSL0DT7–C0MSL15DT7, C1MSL0DT7–C1MSL15DT7
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–7
C0MSL0DT7–C0MSL15DT7,
C1MSL0DT7–C1MSL15DT7
Message slot data 7
R
W
These registers are the memory space for transmit and receive frames.
Note: • During a receive slot, an undefined value is written to the register if the data length of the data
frame being stored (DLC value) is equal to or less than 7.
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13.2 CAN Module Related Registers
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Message Slot 0 Timestamp (C0MSL0TSP)
Message Slot 1 Timestamp (C0MSL1TSP)
Message Slot 2 Timestamp (C0MSL2TSP)
Message Slot 3 Timestamp (C0MSL3TSP)
Message Slot 4 Timestamp (C0MSL4TSP)
Message Slot 5 Timestamp (C0MSL5TSP)
Message Slot 6 Timestamp (C0MSL6TSP)
Message Slot 7 Timestamp (C0MSL7TSP)
Message Slot 8 Timestamp (C0MSL8TSP)
Message Slot 9 Timestamp (C0MSL9TSP)
Message Slot 10 Timestamp (C0MSL10TSP)
Message Slot 11 Timestamp (C0MSL11TSP)
Message Slot 12 Timestamp (C0MSL12TSP)
Message Slot 13 Timestamp (C0MSL13TSP)
Message Slot 14 Timestamp (C0MSL14TSP)
Message Slot 15 Timestamp (C0MSL15TSP)
<Address: H’0080 110E>
<Address: H’0080 111E>
<Address: H’0080 112E>
<Address: H’0080 113E>
<Address: H’0080 114E>
<Address: H’0080 115E>
<Address: H’0080 116E>
<Address: H’0080 117E>
<Address: H’0080 118E>
<Address: H’0080 119E>
<Address: H’0080 11AE>
<Address: H’0080 11BE>
<Address: H’0080 11CE>
<Address: H’0080 11DE>
<Address: H’0080 11EE>
<Address: H’0080 11FE>
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
CAN1
Message Slot 0 Timestamp (C1MSL0TSP)
Message Slot 1 Timestamp (C1MSL1TSP)
Message Slot 2 Timestamp (C1MSL2TSP)
Message Slot 3 Timestamp (C1MSL3TSP)
Message Slot 4 Timestamp (C1MSL4TSP)
Message Slot 5 Timestamp (C1MSL5TSP)
Message Slot 6 Timestamp (C1MSL6TSP)
Message Slot 7 Timestamp (C1MSL7TSP)
Message Slot 8 Timestamp (C1MSL8TSP)
Message Slot 9 Timestamp (C1MSL9TSP)
Message Slot 10 Timestamp (C1MSL10TSP)
Message Slot 11 Timestamp (C1MSL11TSP)
Message Slot 12 Timestamp (C1MSL12TSP)
Message Slot 13 Timestamp (C1MSL13TSP)
Message Slot 14 Timestamp (C1MSL14TSP)
Message Slot 15 Timestamp (C1MSL15TSP)
<Address: H’0080 150E>
<Address: H’0080 151E>
<Address: H’0080 152E>
<Address: H’0080 153E>
<Address: H’0080 154E>
<Address: H’0080 155E>
<Address: H’0080 156E>
<Address: H’0080 157E>
<Address: H’0080 158E>
<Address: H’0080 159E>
<Address: H’0080 15AE>
<Address: H’0080 15BE>
<Address: H’0080 15CE>
<Address: H’0080 15DE>
<Address: H’0080 15EE>
<Address: H’0080 15FE>
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
?
?
?
?
b15
C0MSL0TSP–C0MSL15TSP, C1MSL0TSP–C1MSL15TSP
?
?
?
?
?
?
?
?
?
?
?
?
<After reset: Undefined>
b
Bit Name
Function
R
W
0–15
C0MSL0TSP–C0MSL15TSP,
C1MSL0TSP–C1MSL15TSP
Message slot timestamp
R
W
These registers are the memory space for transmit and receive frames. When transmission/reception has finished, the CAN timestamp count register value is written to the register.
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13.3 CAN Protocol
13.3 CAN Protocol
13.3.1 CAN Protocol Frames
There are four types of frames that are handled by CAN protocol:
(1) Data frame
(2) Remote frame
(3) Error frame
(4) Overload frame
Frames are separated from each other by an interframe space.
Data frame
Standard format
1
11
1
6
0–64
16
2
7
Extended format
1
11
1
1
18
1
6
0–64
16
2
SOF
7
EOF
Arbitration field
ACK field
CRC field
Data field
Control field
Remote frame
Standard format
1
11
1
6
16
2
7
Extended format
1
11
1
1
18
1
6
16
2
7
SOF
EOF
Arbitration field
ACK field
CRC field
Control field
Note: • The number in each field denotes the number of bits.
Figure 13.3.1 CAN Protocol Frames (1)
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13.3 CAN Protocol
Error frame
6–12
8
Error flag
Interframe space or overload flag
Error delimiter
Overload frame
6–12
8
Interframe space or overload flag
Overload flag
Overload delimiter
Interframe space
For the case of an error active state
0–
3
1
SOF of the next frame
Bus idle
Intermission
For the case of an error passive state
0–
8
3
1
SOF of the next frame
Bus idle
Suspend transmission
Intermission
Note: • The number in each field denotes the number of bits.
Figure 13.3.2 CAN Protocol Frames (2)
13.3.2 Data Formats during CAN Transmission/Reception
Figure 13.3.3 shows an example of the transmit/receive transfer data format that can be used in CAN. Data is
transmitted/received sequentially beginning with the MSB side of the CAN message slot .
Arbitration field
CAN frame
MSB
Arbitration field
SOF
SID0
SID1
SID2
SID3
b3
b4
Data field
MSB
Data field
b0
b1
b2
Figure 13.3.3 Example of a CAN Transmit/Receive Transfer Data Format
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13.3 CAN Protocol
13.3.3 CAN Controller Error States
The CAN controller assumes one of the following three error states depending on the transmit error and receive
error counter values.
(1) Error active state
• This is a state where almost no errors have occurred.
• When an error is detected, an active error flag is transmitted.
• The CAN controller is in the state immediately after being initialized.
(2) Error passive state
• This is a state where many errors have occurred.
• When an error is detected, a passive error flag is transmitted.
(3) Bus off state
• This is a state where a very large number of errors have occurred.
• CAN communication with other nodes cannot be performed until the CAN module returns to an error active state.
Error Status of the Unit
Transmit Error Counter
Receive Error Counter
Error active state
0–127
AND
0–127
Error passive state
128–255
OR
128 and over
Bus off state
256 and over
–
Initial setting
Error active
state
Transmit error counter ≥ 128
OR
receive error counter ≥ 128
11 consecutive recessive bits
detected on CAN bus 128 times
or reset by software
Transmit error counter < 128
AND
receive error counter < 128
Error passive
state
Bus off state
Transmit error counter > 255
Figure 13.3.4 CAN Controller Error States
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13.4 Initializing the CAN Module
13.4 Initializing the CAN Module
13.4.1 Initializing the CAN Module
Before performing communication, set up the CAN module as described below.
(1) Selecting pin functions
The CAN transmit data output pin (CTX) and CAN data receive input pin (CRX) are shared with input/output
ports. Be sure to select the functions of these pins. (See Chapter 8, “Input/Output Ports and Pin Functions.”
(2) Setting the Interrupt Controller (ICU)
To use CAN module interrupts, set their interrupt priority levels.
(3) Setting the CAN Error, CAN Single-Shot and CAN Slot Interrupt Request Enable Registers
To use CAN bus error, CAN error passive, CAN error bus off, CAN single-shot or CAN slot interrupts, set
each corresponding bit to "1" to enable the interrupt request.
(4) Setting the DMAC
To use DMA transfers by CAN, be sure to set the DMAC.
(5) Setting the CAN DMA transfer request select register
To use DMA transfers by CAN, set the CAN DMA transfer request select register to choose the cause of
transfer request.
(6) Setting the bit timing and the number of times sampled
Using the CAN Configuration Register and CAN Baud Rate Prescaler, set the bit timing and the number of
times the CAN bus is sampled.
1) Setting the bit timing
Determine the period Tq that is the base of bit timing, the configuration of Propagation Segment, Phase
Segment1 and Phase Segment2, and reSynchronization Jump Width. The equation to calculate Tq is
given below.
Tq = (BRP + 1) / (CPU clock/2)
The baud rate is determined by the number of Tq’s that comprise one bit. The equation to calculate the
baud rate is given below.
1
Baud rate (bps) =
Tq period × number of Tq’s in one bit
Number of Tq’s in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1
+ Phase Segment 2
2) Setting the number of times sampled
Select the number of times the CAN bus is sampled from “one time” and “three times.”
• If one-time sampling is selected, the value sampled at only the end of Phase Segment1 is assumed to
be the value of the bit.
• If three-time sampling is selected, the value of the bit is determined by majority from three sampled
values, one sampled at the end of Phase Segment1 and the other sampled 1 Tq before and 2 Tq’s
before that.
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13.4 Initializing the CAN Module
1 Bit
Synchronization
Segment
Propagation Segment
Phase Segment1
Phase Segment2
1Tq
(3)
(2)
(1)
Sampling Point
• This diagram shows the bit timing when one bit consists of 8 Tq's.
• If one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the
value of the bit.
• If three-time sampling is selected, the value of the bit is determined by majority from CAN bus
values sampled at Sampling Points (1), (2) and (3).
Figure 13.4.1 Example of Bit Timing
(7) Setting the ID mask registers
Set the values of ID mask registers (Global Mask Register, Local Mask Register A and Local Mask Register
B) that are used in acceptance filtering of received messages.
(8) Settings for use in BasicCAN mode
• Set the CAN Extended ID Register IDE14 and IDE15 bits. (We recommend setting the same value in these bits.)
• Set IDs in message slots 14 and 15.
• Set the Message Control Registers 14 and 15 for data frame reception (H’40).
(9) Settings for use in single-shot mode
Using the CAN Mode Register (CANnMODE) and CAN Control Register (CANnCNT), select CAN module
operation mode (BasicCAN, loopback mode) and the clock source for the timestamp counter.
(10) Setting CAN module operation mode
In the CAN Single-Shot Mode Control Register, set the slot that is to be operated in single-shot mode.
(11) Releasing the CAN module from reset
When settings (1) through (10) above are finished, clear the CAN Control Register (CANnCNT)’s forcible
reset (FRST) and reset (RST) bits to "0". Then, after detecting 11 consecutive recessive bits on the CAN bus,
the CAN module becomes ready to communicate.
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13.4 Initializing the CAN Module
Initialize the CAN module
Set the Input/Output Port
Operation Mode Register
Set the Interrupt Controller
Set the CAN related interrupt
request enable registers
Set the DMAC
Set the CAN DMA transfer
request select register
Set the CAN
Configuration Register
Set the ID Mask Register
Set interrupt priority
Set the CAN Error Interrupt Request
Enable Register
• Enable/disable CAN bus error
interrupt request
• Enable/disable CAN error
passive interrupt request
• Enable/disable CAN bus off
interrupt request
Set the DMAC
Set the CAN Slot Interrupt
Request Enable Register
• Enable/disable the interrupt
request to be generated when
transmission or reception in
the relevant slot has finished
Set the CAN Single-shot Interrupt
Request Enable Regiter
• Enable/disable the interrupt request
to be generated when single-shot
transission in the relevant slot has failed.
Select the DMA transfer request source
• Set the bit timing (baud rate)
• Set the number of times sampled
Set the ID mask bit
Set loopback mode
Set the CAN operation mode
Set BasicCAN mode
• Set the CAN Extended ID Register
• Set IDs in message slots 14 and 15
• Set the Message Slot Control Register
Release the CAN module from reset
Negate CAN reset
• Clear the CAN Control Register (CANnCNT)'s
FRST and RST bits
CAN module initialization
completed
Figure 13.4.2 Initializing the CAN Module
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13.5 Transmitting Data Frames
13.5 Transmitting Data Frames
13.5.1 Data Frame Transmit Procedure
The following describes the procedure for transmitting data frames.
(1) Initializing the CAN Message Slot Control Register
Initialize the CAN Message Slot Control Register for the slot to be transmitted by writing H’00 to the register.
(2) Confirming that transmission is idle
Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/
Receive Status) bit to see that transmission/reception has stopped and remains idle. If this bit = "1", it means
that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to "0".
(3) Setting transmit data
Set the transmit ID and transmit data in the message slot.
(4) Setting the Extended ID Register
Set the corresponding bit in the Extended ID Register to "0" if the data is to be transmitted as a standard
frame, or "1" if the data is to be transmitted as an extended frame.
(5) Setting the CAN Message Slot Control Register
Write H’80 (Note 1) to the CAN Message Slot Control Register to set the TR (Transmit Request) bit to "1".
Note 1: Always be sure to write H’80 when transmitting data frames.
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13.5 Transmitting Data Frames
Data frame transmit procedure
Initialize the CAN Message
Slot Control Register
Write H'00
Read the CAN Message Slot
Control Register
NO
TRSTAT bit = 0
Confirm that transmission is idle
YES
Set ID and data in the
message slot
Set the Extended ID Register
Set the CAN Message Slot
Control Register
Standard ID or extended ID
Write H'80 (transmit request)
End of setting
Figure 13.5.1 Data Frame Transmit Procedure
13.5.2 Data Frame Transmit Operation
The following describes data frame transmit operation. The operations described below are automatically performed in hardware.
(1) Selecting a transmit frame
The CAN module checks slots which have transmit requests (including remote frame transmit slots) every
intermission to determine the frame to transmit. If two or more transmit slots exist, frames are transmitted in
order of slot numbers beginning with the smallest.
(2) Transmitting a data frame
After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit to "1" and starts transmitting.
(3) If lost in CAN bus arbitration or a CAN bus error occurs
If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission, the
CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0".
If the CAN module requested a transmit abort, the transmit abort is accepted and the message slot is enabled
for write.
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13.5 Transmitting Data Frames
(4) Completion of data frame transmission
When data frame transmission has finished, the CAN Message Slot Control Register’s TRFIN (Transmit/
Receive Finished) bit and the CAN Slot Interrupt Request Status Register are set to "1". Also, a timestamp
count value at which transmission has finished is written to the CAN Message Slot Timestamp (C0MSLnTSP,
C1MSLnTSP), and the transmit operation is thereby completed.
If the CAN slot interrupt request has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive
(neither transmit nor receive) until it is newly set in software.
Bit arrangement in the CAN Message Slot Control Register
b0(b8)
1
2
3
4
5
TR
RR
RM
RL
RA
ML
0
0
0
0
0
0
6
b7(b15)
TRSTAT TRFIN
0
0
L
a ost
C in
AN C
bu AN
s b
er us
ro a
r o rb
cc itra
ur tio
s n
or
B'0000 0000
(Note 1)
Write H'80
Transmission aborted
d
pte
ce
ac
Wait for transmission
st r ted
B'1000 0000
e
qu abo
e
r
t ion
mi
ns iss
Tra nsm
Transmit request
Lost in CAN bus arbitration
Tra
accepted
or a CAN bus error occurs
Transmission
aborted
B'0000 0010
B'0000 0001
(Note 1)
B'1000 0010
d
r te d
bo plete
a
ion com
ss
mi sion
s
n
is
Tra nsm
Tra
Transmission completed
B'1000 0001
Note 1: When in this state, data can be written to the message slot.
Figure 13.5.2 Operation of the CAN Message Slot Control Register during Data Frame Transmission
13.5.3 Transmit Abort Function
The transmit abort function is used to cancel a transmit request that has once been set. This is accomplished by
writing H’0F to the CAN Message Slot Control Register for the slot to be canceled. When transmit abort is
accepted, the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0", allowing for data to be written to the message slot. The following shows the conditions under which
transmit abort is accepted.
[Conditions]
• When the target message is waiting for transmission
• When a CAN bus error occurs during transmission
• When lost in CAN bus arbitration
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13.6 Receiving Data Frames
13.6 Receiving Data Frames
13.6.1 Data Frame Receive Procedure
The following describes the procedure for receiving data frames.
(1) Initializing the CAN Message Slot Control Register
Initialize the CAN Message Slot Control Register for the slot to be received by writing H’00 to the register.
(2) Confirming that reception is idle
Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/
Receive Status) bit to see that reception has stopped and remains idle. If this bit = "1", it means that the CAN
module is accessing the message slot. Therefore, wait until the bit is cleared to "0".
(3) Setting the receive ID
Set the desired receive ID in the message slot.
(4) Setting the Extended ID Register
Set the corresponding bit in the Extended ID Register to "0" if a standard frame is to be received, or "1" if an
extended frame is to be received.
(5) Setting the CAN Message Slot Control Register
Write H’40 to the CAN Message Slot Control Register to set the RR (Receive Request) bit to "1".
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13.6 Receiving Data Frames
Data frame receive procedure
Initialize the CAN Message Slot
Control Register
Write H'00
Read the CAN Message Slot
Control Register
NO
Confirm that reception is idle
TRSTAT bit = 0
YES
Set ID in the message slot
Set the Extended ID Register
Standard ID or extended ID
Set the CAN Message Slot
Control Register
Write H'40 (receive request)
End of setting
Figure 13.6.1 Data Frame Receive Procedure
13.6.2 Data Frame Receive Operation
The following describes data frame receive operation. The operations described below are automatically performed in hardware.
(1) Acceptance filtering
When the CAN module finished receiving data, it starts searching for the slot that satisfies the conditions for
receiving the received message, sequentially from slot 0 (up to slot 15). The following shows receive conditions for the slots that have been set for data frame reception.
[Conditions]
• The received frame is a data frame.
• The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to "0" are “Don’t care.”
• The standard and extended frame types are the same.
Note: • In BasicCAN mode, slots 14 and 15 while being set for data frame reception can also
receive remote frames.
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13.6 Receiving Data Frames
(2) When the receive conditions are met
When the receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at
the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is
already set to "1" at this time, the CAN module also sets the ML (Message Lost) bit to "1", indicating that the
message slot has been overwritten. The message slot has both of its ID and DLC fields entirely overwritten
and has an undefined value written in its unused area (e.g., extended ID field during standard frame reception and an unused data field).
Furthermore, a timestamp count value at which the message was received is written to the CAN Message
Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along with the received data. When the CAN module finished
writing to the message slot, it sets the CAN Slot Interrupt Request Status bit to "1". If the interrupt request for
the slot has been enabled, the CAN module generates an interrupt request and enters a wait state for the
next reception.
(3) When the receive conditions are not met
The received frame is discarded, and the CAN module goes to the next transmit/receive operation without
writing to the message slot.
Bit arrangement in the CAN Message Slot Control Register
b0(b8)
1
2
3
4
5
TR
RR
RM
RL
RA
ML
0
0
0
0
0
0
6
b7(b15)
TRSTAT TRFIN
0
B'0000 0000
0
Set a receive
request
Clear the receive request
Wait for the received data
Finished storing
the received data
B'0000 0001
B'0000 0111
Finished storing
the received data
B'0000 0101
st
the
ue
ing
req
tor a
s
e
ed dat eiv
ish ed rec
Fin ceiv r the
re lea Clear the receive
C
request
ata st
d d que
e
v
e
ei r
rec eive
he rec
t
ore he
St ear t
Cl
Clear the receive
request
Store the received data
B'0100 0011
Finished storing the received data
B'0100 0001
Store the received data
B'0100 0111
t
he
es
gt
qu
rin
e
o
r
t
s a e
Finished storing
ed dat eiv
the received
ish ed rec
Fin ceiv the
data
re lear
C
Clear the receive
request
CPU read
B'0000 0011
Clear the receive
request
B'0100 0000
CPU read
ata st
d d ue
ive e req
e
rec eiv
the e rec
e
r
h
t
o
St lear
C
Store the received data
Wait for the
received data
B'0100 0101
Figure 13.6.2 Operation of the CAN Message Slot Control Register during Data Frame Reception
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13.6 Receiving Data Frames
13.6.3 Reading Out Received Data Frames
The following shows the procedure for reading out received data frames from the slot.
(1) Clearing the TRFIN (Transmit/Receive Finished) bit
Write H’4E, H’40 or H’00 to the CAN Message Slot Control Register (C0MSLnCNT, C1MSLnCNT) to clear
the TRFIN bit to "0". After this write, the slot operates as follows:
Values Written to CnMSLnCNT
Slot Operation after Write
H’4E
Operates as a data frame receive slot. Whether overwritten can be verified by ML bit.
H’40
Operates as a data frame receive slot. Whether overwritten cannot be verified by ML bit.
H’00
The slot stops transmit/receive operation.
Notes: • If message-lost check by the ML bit is needed, write H’4E to clear the TRFIN bit.
• If the TRFIN bit was cleared by writing H’4E, H’40 or H’00, it is possible that new data will be stored in the slot while
still reading out a message from it.
(2) Reading out from the message slot
Read out a message from the message slot.
(3) Checking the TRFIN (Transmit/Receive Finished) bit
Read the CAN Message Slot Control Register to check the TRFIN (Transmit/Receive Finished) bit.
1) If TRFIN (Transmit/Receive Finished) bit = "1"
It means that new data was stored in the slot while still reading out a message from it in (2) above. In this
case, the data read out in (2) may contain an undefined value. Therefore, reexecute the above
procedure beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1).
2) If TRFIN (Transmit/Receive Finished) bit = "0"
It means that the CAN module finished reading out from the slot normally.
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13.6 Receiving Data Frames
Reading out received data
Clear the TRFIN bit to 0
Write H'4E, H'40 or H'00
Read out from the message slot
Read the CAN Message Slot
Control Register
NO
TRFIN bit = 0
YES
Finished reading out
received data
Figure 13.6.3 Procedure for Reading Out Received Data
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13.7 Transmitting Remote Frames
13.7 Transmitting Remote Frames
13.7.1 Remote Frame Transmit Procedure
The following describes the procedure for transmitting remote frames.
(1) Initializing the CAN Message Slot Control Register
Initialize the CAN Message Slot Control Register for the slot to be transmitted by writing H’00 to the register.
(2) Confirming that transmission is idle
Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/
Receive Status) bit to see that transmission/reception has stopped and remains idle. If this bit = "1", it means
that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to "0".
(3) Setting transmit ID
Set the ID to be transmitted in the message slot.
(4) Setting the Extended ID Register
Set the corresponding bit in the Extended ID Register to "0" if the data is to be transmitted as a standard
frame, or "1" if the data is to be transmitted as an extended frame.
(5) Setting the CAN Message Slot Control Register
Write H’A0 to the CAN Message Slot Control Register to set the TR (Transmit Request) bit and RM (Remote)
bit to "1".
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13.7 Transmitting Remote Frames
Remote frame
transmit procedure
Initialize the CAN Message Slot
Control Register
Write H'00
Read the CAN Message Slot
Control Register
NO
Confirm that transmission is idle
TRSTAT bit = 0
YES
Set ID in the message slot
Set the Extended ID Register
Set the CAN Message Slot
Control Register
Standard ID or extended ID
Write H'A0 (transmit request, remote)
End of setting
Figure 13.7.1 Remote Frame Transmit Procedure
13.7.2 Remote Frame Transmit Operation
The following describes remote frame transmit operation. The operations described below are automatically
performed in hardware.
(1) Setting the RA (Remote Active) bit
The RA (Remote Active) bit is set to "1" at the same time H’A0 (Transmit Request, Remote) is written to the
CAN Message Slot Control Register, indicating that the corresponding slot is to handle remote frames.
(2) Selecting a transmit frame
The CAN module checks slots which have transmit requests (including data frame transmit slots) every
intermission to determine the frame to transmit. If two or more transmit slots exist, frames are transmitted in
order of slot numbers beginning with the smallest.
(3) Transmitting a remote frame
After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit to "1" and starts transmitting.
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13.7 Transmitting Remote Frames
(4) If lost in CAN bus arbitration or a CAN bus error occurs
If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission, the
CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0".
If the CAN module requested a transmit abort, the transmit abort is accepted and the message slot is enabled
for write.
(5) Completion of remote frame transmission
When remote frame transmission finishes, the timestamp count value at which transmission finished is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP) and the CAN Message Slot Control
Register’s RA (Remote Active) bit is cleared to "0". In addition, the CAN Slot Interrupt Request Status bit is
set to "1" by completion of transmission, but the CAN Message Slot Control Register’s TRFIN (Transmit/
Receive Finished) bit is not set to "1". If the CAN slot interrupt request has been enabled, an interrupt request
is generated when transmission has finished.
(6) Receiving a data frame
When remote frame transmission finishes, the slot automatically starts functioning as a data frame receive slot.
(7) Acceptance filtering
When the CAN module finished receiving data, it starts searching for the slot that satisfies the conditions for
receiving the received message, sequentially from slot 0 (up to slot 15). The following shows receive conditions for the slots that have been set for data frame reception.
[Conditions]
• The received frame is a data frame.
• The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to "0" are “Don’t care.”
• The standard and extended frame types are the same.
Note: • In BasicCAN mode, slots 14 and 15 cannot be used as a transmit slot.
(8) When the receive conditions are met
When the receive conditions in (7) above are met, the CAN module sets the CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at
the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is
already set to "1" at this time, the CAN module also sets the ML (Message Lost) bit to "1", indicating that the
message slot has been overwritten. The message slot has both of its ID and DLC fields entirely overwritten
and has an undefined value written in its unused area (e.g., extended ID field during standard frame reception and an unused data field).
Furthermore, a timestamp count value at which the message was received is written to the CAN Message
Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along with the received data. When the CAN module finished
writing to the message slot, it sets the CAN Slot Interrupt Request Status bit to "1". If the interrupt request for
the slot has been enabled, the CAN module generates an interrupt request and enters a wait state for the
next reception.
Note: • If the CAN module receives a corresponding data frame before sending a remote frame, it stores the
received data frame in the slot and does not transmit the remote frame.
(9) When the receive conditions are not met
The received frame is discarded, and the CAN module goes to the next transmit/receive operation without
writing to the message slot.
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13.7 Transmitting Remote Frames
Bit arrangement in the CAN Message Slot Control Register
b0(b8)
1
2
3
4
5
TR
RR
RM
RL
RA
ML
0
0
0
0
0
0
6
b7(b15)
TRSTAT TRFIN
0
0
B'0000 0000
Store the
received data
B'0000 1000
Clear the transmit
request
B'1010 1000
B'1010 1011
Finished storing
the received data
Finished storing
the received data
CAN bus error
occurred
B'0000 1011
Clear the transmit
request
B'1010 1010
B'0000 1010
Finished sending
a remote frame
s
bu CAN
N
CA or a rred
n
i
ion ccu it
st
Lo itrat or o ansm
arb s err he tr
bu ear t t
Cl ues
req
B'0000 0000
Finished sending
a remote frame
Wait for
received data
B'1010 0000
Store the received data
Clear the receive request
B'0000 0011
the
ing a
tor dat eive
s
ed ved rec
ish cei he
Fin re ear t uest
Cl req
B'0000 0001
Finished storing
the received data
Finished sending
a remote frame
B'1010 0001
Store the received data
B'1010 0111
the the
ing ar
tor Cle st Finished
s
ed ata que sending
ish d d re
a remote
Fineive eive
frame
c
c
e
re r
B'0000 0101
Store the received data
B'1010 0011
Store the received data
Clear the receive request
B'0000 0111
B'0000 0001
Store the received data
B'1010 0101
Wait for
received data
CPU read
Figure 13.7.2 Operation of the CAN Message Slot Control Register during Remote Frame Transmission
13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission
The following shows the procedure for reading out the data frames that have been received in the slot when it is
set for remote frame transmission.
(1) Clearing the TRFIN (Transmit/Receive Finished) bit
Write H’AE or H’00 to the CAN Message Slot Control Register (C0MSLnCNT, C1MSLnCNT) to clear the
TRFIN bit to "0". After this write, the slot operates as follows:
Values Written to CnMSLnCNT
Slot Operation after Write
H’AE
Operates as a data frame receive slot. Whether overwritten can be verified by ML bit.
H’00
The slot stops transmit/receive operation.
Notes: • If message-lost check by the ML bit is needed, write H’AE to clear the TRFIN bit.
• If the TRFIN bit was cleared by writing H’AE or H’00, it is possible that new data will be stored in the slot while still
reading out a message from it.
• The received data frame cannot be read out by writing H’A0 to the register. If the TRFIN bit is cleared by writing
H’A0, the slot performs remote frame transmit operation.
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13.7 Transmitting Remote Frames
(2) Reading out from the message slot
Read out a message from the message slot.
(3) Checking the TRFIN (Transmit/Receive Finished) bit
Read the CAN Message Slot Control Register to check the TRFIN (Transmit/Receive Finished) bit.
1) If TRFIN (Transmit/Receive Finished) bit = "1"
It means that new data was stored in the slot while still reading out a message from it in (2) above. In this
case, the data read out in (2) may contain an undefined value. Therefore, reexecute the above
procedure beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1).
2) If TRFIN (Transmit/Receive Finished) bit = "0"
It means that the CAN module finished reading out from the slot normally.
Reading out received data
Clear the TRFIN bit to 0
Write H'AE or H'00
Read out from the message slot
Read the CAN Message Slot
Control Register
NO
TRFIN bit = 0
YES
Finished reading out
received data
Figure 13.7.3 Procedure for Reading Out Received Data when Set for Remote Frame Transmission
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13.8 Receiving Remote Frames
13.8 Receiving Remote Frames
13.8.1 Remote Frame Receive Procedure
The following describes the procedure for receiving remote frames.
(1) Initializing the CAN Message Slot Control Register
Initialize the CAN Message Slot Control Register for the slot to be received by writing H’00 to the register.
(2) Confirming that reception is idle
Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/
Receive Status) bit to see that reception has stopped and remains idle. If this bit = "1", it means that the CAN
module is accessing the message slot. Therefore, wait until the bit is cleared to "0".
(3) Setting the receive ID
Set the desired receive ID in the message slot.
(4) Setting the Extended ID Register
Set the corresponding bit in the Extended ID Register to "0" if a standard frame is to be received, or "1" if an
extended frame is to be received.
(5) Setting the CAN Message Slot Control Register
1) When automatic response (data frame transmission) for remote frame reception is desired
Write H’60 to the CAN Message Slot Control Register to set the RR (Receive Request) bit and RM
(Remote) bit to "1".
2) When automatic response (data frame transmission) for remote frame reception is to be disabled
Write H’70 to the CAN Message Slot Control Register to set the RR (Receive Request) bit, RM (Remote)
bit and RL (Automatic Response Enable) bit to "1".
Note: • During BasicCAN mode, slots 14 and 15, although capable of receiving remote frames,
cannot automatically respond to remote frame reception.
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13.8 Receiving Remote Frames
Remote frame
receive procedure
Initialize the CAN Message Slot
Control Register
Write H'00
Read the CAN Message Slot
Control Register
NO
Confirm that reception is idle
TRSTAT bit = 0
YES
Set ID in the message slot
Standard ID or extended ID
Set the Extended ID Register
Write H'60
(receive request, remote and automatic response enable)
Write H'70
(receive request, remote and automatic response disable)
Set the CAN Message Slot
Control Register
End of setting
Figure 13.8.1 Remote Frame Receive Procedure
13.8.2 Remote Frame Receive Operation
The following describes remote frame receive operation. The operations described below are automatically
performed in hardware.
(1) Setting the RA (Remote Active) bit
The RA (Remote Active) bit indicating that the corresponding slot is to handle remote frames is set to "1" at
the same time H’60 (Receive Request, Remote) or H’70 (Receive Request, Remote, Automatic Response
Disable) is written to the CAN Message Slot Control Register.
(2) Acceptance filtering
When the CAN module finished receiving data, it starts searching for the slot that satisfies the conditions for
receiving the received message, sequentially from slot 0 (up to slot 15). The following shows receive conditions for the slots that have been set for data frame reception.
[Conditions]
• The received frame is a remote frame.
• The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to "0" are “Don’t care.”
• The standard and extended frame types are the same.
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13.8 Receiving Remote Frames
(3) When the receive conditions are met
When the receive conditions in (2) above are met, the CAN module sets the CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at
the same time writing the received data to the message slot. In addition, a timestamp count value at which the
message was received is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along
with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot
Interrupt Request Status bit to "1". If the interrupt request for the slot has been enabled, the CAN module
generates an interrupt request.
Notes: • The ID field and DLC value are written to the message slot.
• An undefined value is written to the extended ID area when receiving standard format frames.
• The data field is not written to.
• The RA and TRFIN bits are cleared to "0" after writing the received remote frame data.
(4) When the receive conditions are not met
The received data is discarded, and the CAN module waits for the next receive frame. No data is written to
the message slot.
(5) Operation after receiving a remote frame
The operation performed after receiving a remote frame differs depending on how automatic response is set.
1) When automatic response is disabled
The slot which has had reception completed goes to an inactive state and remains inactive (neither
transmit nor receive) until it is newly set in software.
2) When automatic response is enabled
After receiving a remote frame, the slot automatically changes to a data frame transmit slot and performs
the transmit operation described below. In this case, the transmitted data conforms to the ID and DLC of
the received remote frame.
• Selecting a transmit frame
The CAN module checks slots which have transmit requests (including remote frame transmit slots)
every intermission to determine the frame to transmit. If two or more transmit slots exist, frames are
transmitted in order of slot numbers beginning with the smallest.
• Transmitting a data frame
After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit to "1" and starts transmitting.
• If lost in CAN bus arbitration or a CAN bus error occurs
If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission,
the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status)
bit to "0". If the CAN module requested a transmit abort, the transmit abort is accepted and the message
slot is enabled for write.
• Completion of data frame transmission
When data frame transmission has finished, the CAN Message Slot Control Register’s TRFIN (Transmit/
Receive Finished) bit and the CAN Slot Interrupt Request Status Register are set to "1". Also, a
timestamp count value at which transmission has finished is written to the CAN Message Slot
Timestamp (C0MSLnTSP, C1MSLnTSP), and the transmit operation is thereby completed.
If the CAN slot interrupt request has been enabled, an interrupt request is generated at completion of
transmit operation. The slot which has had transmission completed goes to an inactive state and
remains inactive (neither transmit nor receive) until it is newly set in software.
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13.8 Receiving Remote Frames
Bit arrangement in the CAN Message Slot Control Register
b0(b8)
1
2
3
4
5
TR
RR
RM
RL
RA
ML
0
0
0
0
0
0
6
b7(b15)
TRSTAT TRFIN
0
0
B'0000 0000
Write H'70
(automatic response
disabled)
Write H'60
(automatic response
enabled)
Clear the
receive request
Wait for reception
B'0110 1000
Store the
received data
B'0111 1000
Store the
received data
Store the received data
Clear the receive
request
B'0000 1010
B'0110 1011
Finished storing
Finished storing the received data
the received data
Finished storing
the received data
B'0000 0000
B'0111
B'0110 0000
Finished storing the received data
Clear the receive request
Store the received data
Clear the receive
request
1011
B'0000
Fin
is
Cle reched s
e
ar ive tor
reqthe re d daing th
ue ce ta e
st ive
B'0111 0000
1010
B'0000 0000
Send a data frame
Send a data frame
Clear the receive
request
B'0000 0010
Finished sending
a data frame
B'0000 0001
B'0110 0010
Finished sending a d