Mitsubishi M34280M1 Single-chip 4-bit cmos microcomputer for infrared remote control transmitter Datasheet

MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
DESCRIPTION
The 4280 Group is a 4-bit single-chip microcomputer designed
with CMOS technology for remote control transmitters. The 4280
Group has 7 carrier waves and enables fabrication of 8 × 7 key
matrix.
FEATURES
• Number of basic instructions ............................................. 62
• Minimum instruction execution time ............................ 8.0 µs
(at f(X IN) = 4.0 MHz, system clock = f(XIN )/8, VDD=3.0 V)
• Supply voltage ................................................. 1.8 V to 3.6 V
• Subroutine nesting ..................................................... 4 levels
• Timer
Timer 1 ................................................................... 8-bit timer
with a reload register and carrier wave output auto-control
function
Product
M34280M1-XXXFP
M34280M1-XXXGP
M34280E1FP
M34280E1GP
• Carrier wave output function (port CARR)
f(X IN), f(XIN)/4, f(XIN )/8, f(XIN)/12
f(X IN)/64, f(XIN)/96, “H” output fixed
• Logic operation function (XOR, OR, AND)
• RAM back-up function
• Key-on wakeup function (ports D 7, E 0–E2, G 0–G3) ............. 8
• I/O port (ports D, E, G, CARR) .......................................... 16
• Oscillation circuit ..................................... Ceramic resonance
• Watchdog timer
• Power-on reset circuit
• Voltage drop detection circuit ......................... Typical:1.50 V
APPLICATION
Various remote control transmitters
ROM (PROM) size
RAM size
(× 9 bits)
1024 words
(× 4 bits)
32 words
Package
ROM type
20P2N-A
Mask ROM
1024 words
1024 words
32 words
32 words
20P2E/F-A
20P2N-A
Mask ROM
One Time PROM
1024 words
32 words
20P2E/F-A
One Time PROM
PIN CONFIGURATION (TOP VIEW)
M34280M1-XXXFP/GP
1
20
VDD
E2
2
19
CARR
E1
3
18
D0
XIN
4
17
D1
XOUT
5
16
D2
E0
6
15
D3
G0
7
14
D4
G1
8
13
D5
G2
9
12
D6
G3
10
11
D7
M34280M1-XXXFP/GP
VSS
Outline 20P2N-A
20P2E/F-A
2
Port E
2
Timer
Timer 1 (8 bits)
Port G
4
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Register A (4 bits) Register B (4 bits)
Register D (3 bits) Register E (8 bits)
Stack register SK (4 levels)
ALU (4 bits)
720 Series
CPU core
7
Port D
1
Note: PROM 1024 words × 9 bits
32 words × 4 bits
RAM
1024 words × 9 bits
ROM (Note)
Memory
XIN–XOUT
System clock generating circuit
Remote control carrier wave output
Internal peripheral functions
I/O port
1
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Function
62
Minimum instruction execution time 8.0 µs (at 4.0 MHz system clock frequency)
(f(XIN ) = 4.0 MHz, system clock = f(XIN )/8, VDD = 3 V)
M34280M1/ 1024 words ✕ 9 bits
Memory sizes ROM
Input/Output
ports
32 words ✕ 4 bits
RAM
D0–D6
E1
Output
D7
E0–E2
I/O
Seven independent output ports
1-bit I/O port with the pull-down function
E0, E1
Input
Output
3-bit input port with the pull-down function
2-bit output port (E0, E1)
G0–G3
CARR
I/O
Output
4-bit I/O port with the pull-down function
Timer 1
1-bit output port; CMOS output
8-bit timer with a reload register
Subroutine nesting
Device structure
4 levels (However, only 3 levels can be used when the TABP p instruction is executed)
CMOS silicon gate
Package
Operating temperature range
20-pin plastic molded SOP (20P2N-A)/SSOP (20P2E/F-A)
Supply voltage
Power
dissipation
Active mode
–20 °C to 85 °C
1.8 V to 3.6 V
400 µA
(f(XIN ) = 4.0 MHz, system clock = f(XIN )/8, VDD = 3 V)
(typical value) RAM back-up mode 0.1 µA (at room temperature, VDD = 3 V)
PIN DESCRIPTION
Pin
Name
VDD
Power supply
VSS
XIN
Ground
System clock input
XOUT
D0–D6
D7
Function
Input/Output
—
Connected to a plus power supply.
—
Input
Connected to a 0 V power supply.
I/O pins of the system clock generating circuit. Connect a ceramic resonator
System clock output
Output
between pins XIN and X OUT. The feedback resistor is built-in between pins XIN
and XOUT.
Output port D
Output
Each pin of port D has an independent 1-bit wide output function. The output
I/O
structure is P-channel open-drain.
1-bit I/O port. For input use, turn on the built-in pull-down transistor and set the
I/O port D
latch of the specified bit to “0.” In addition, key-on wakeup function using “H”
level sense becomes valid. The output structure is P-channel open-drain.
E0–E2
I/O port E
Output
Input
2-bit (E0, E 1) output port. The output structure is P-channel open-drain.
3-bit input port. For input use (E0, E1), turn on the built-in pull-down transistor and
set the latch of the specified bit to “0.” In addition, key-on wakeup function using
“H” level sense becomes valid. Port E2 has an input-only port and has a key-on
wakeup function using “H” level sense and pull-down transistor.
G0–G3
I/O port G
I/O
4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output
structure is P-channel open-drain. Port G has a key-on wakeup function using
“H” level sense and pull-down transistor.
CARR
Carrier wave output
Output
Carrier wave output pin for remote control. The output structure is CMOS circuit.
for remote control
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
CONNECTIONS OF UNUSED PINS
Pin
Connection
Open or connect to VDD pin (Note 1).
D 0–D7
E 0, E1
Set the output latch to “1” and open, or
connect to VDD pin (Note 2).
E2
G 0–G3
Open or connect to VSS pin.
Set the output latch to “0” and open, or
connect to VSS pin.
Notes 1: Port D7: Set the bit 2 (PU02) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF.
2: Set the corresponding bits (PU00, PU01) of the pull-down control register PU0 to “0” by software and turn the pull-down
transistor OFF.
(Note in order to set the output latch to “0” to make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Port
Port D
Pin
D0–D6
Input/
Output
Output P-channel open-drain
(7)
D7
Port E
Port G
Output structure
Control
Control
Control
bits
1 bit
instructions
SD
registers
RD
CLD
I/O
SD
(1)
RD
CLD
SZD
Output: OEA
E0
E1
I/O
(2)
2 bits
IAE
E2
Input
Input:
3 bits
IAE
4 bits
OGA
(1)
I/O
G0–G3
P-channel open-drain
P-channel open-drain
(4)
Port CARR
CARR
1 bit
DEFINITION OF CLOCK AND CYCLE
• System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the CCK
instruction.
4
PU0
CCK instruction
System clock
Instruction clock
When not using
When using
f(X IN)/8
f(XIN)
f(XIN)/32
f(XIN)/4
Pull-down function and key-on
wakeup function
(programmable)
PU0
Pull-down function and key-on
wakeup function
(programmable)
Pull-down function and key-on
wakeup function
IAG
Output CMOS
(1)
Remark
OCRA
C
• Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
• Machine cycle
The machine cycle is the cycle required to execute the
instruction.
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
PORT BLOCK DIAGRAMS
Register Y
Decoder
(Note 1)
S
SD instruction
Q
Ports D0–D6
R
RD instruction
CLD instruction
Register Y
Decoder
(Note 1)
S Q
SD instruction
RD instruction
R
Port D7 (Note 4)
CLD instruction
Pull-down
transistor
Skip decision (SZD instruction)
Key-on wakeup input
PU02
Register A
A0
(Note 1)
D Q
OEA
instruction
T
IAE instruction
Port E0 (Note 4)
A0
Pull-down
transistor
Key-on wakeup input
PU00
Register A
(Note 1)
D Q
A1
A1
OEA
instruction
T
IAE instruction
Port E1 (Note 4)
Pull-down
transistor
Key-on wakeup input
PU01
IAE instruction
Register A
A2
Port E2 (Note 4)
(Note 1)
Key-on wakeup input
Pull-down
transistor
Register A
D Q
Ai
(Note 2)
OGA
instruction
T
(Note 1)
Ports G0–G3 (Note 4)
IAG instruction
Ai
Pull-down
transistor
Key-on wakeup input
Register A
Aj (Note 3)
TCA instruction
Register A
Aj (Note 3)
Register C
TAC instruction
To timer 1
CARRY
(Note 1)
Carrier wave
output circuit
Register A
A3
OCRA instruction
Timer 1 underflow signal
Port CARR
D Q
T R
TCA
instruction
D Q
V12
T R
Carrier wave
output control
signal
V10
Notes 1:
This symbol represents a parasitic diode.
2: i represents bits 0 to 3.
3: j represents bits 0 to 2.
4: Applied voltage must be less than VDD.
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, and bit manipulation.
(M(DP))
Addition
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A 0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
ALU
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
TAB instruction
Register B
B3 B2 B1 B0
Register A
A3 A2 A1 A0
TEAB instruction
Register E ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
TABE instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
TBA instruction Register A
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
4
8
Specifying address
0
Low-order 4 bits
p3
PCH
p2 p1 p0
PCL
DR2 DR1 DR0 A3 A2 A1 A0
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents
of register D
The contents
of register A
Most significant 1 bit
Carry flag CY (1)
URS flag (1)
URSC instruction
Fig. 4 TABP p instruction execution example
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4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(5) Most significant ROM code reference enable flag (URS)
URS flag controls whether to refer to the contents of the most
significant 1 bit (bit 8) of ROM code when executing the TABP
p instruction. If URS flag is “0,” the contents of the most
significant 1 bit of ROM code is not referred even when
executing the TABP p instruction. However, if URS flag is “1,”
the contents of the most significant 1 bit of ROM code is set to
flag CY when executing the TABP p instruction (Figure 4).
URS flag is “0” after system is released from reset and returned
from RAM back-up mode. It can be set to “1” with the URSC
instruction, but cannot be cleared to “0.”
(6) Stack registers (SKs) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents
of program counter (PC) just before branching until returning
to the original routine when;
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contents of registers SKs are destroyed when 4 levels are
exceeded.
The register SK nesting level is pointed automatically by 2-bit
stack pointer (SP).
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions.
Note : The 4280 Group just invalidates the next instruction
when a skip is performed. The contents of program
counter is not increased by 2. Accordingly, the number
of cycles does not change even if skip is not performed.
However, the cycle count becomes “1” if the TABP p,
RT, or RTS instruction is skipped.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
Stack pointer (SP) points “3” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after four
stack registers are used ((SP) = 3), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP)
(SK0)
(PC)
0
000116
SUB1
Subroutine
Main program
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC)
(SP)
(SK0)
3
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not exceed after the last page of
the built-in ROM.
Program counter (PC)
p3 p2 p1 p0
PCH
Specifying
page
a6 a5 a4 a3 a2 a1 a0
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and
consists of registers X and Y. Register X specifies a file and
register Y specifies a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure
9).
Register Y (4)
Specifying
RAM digit
Specifying RAM file
Register X (2)
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D7
0
1 0 1
Register Y (4)
D5
1
Port D output latch
Fig. 9 SD instruction execution example
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4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is
composed of 9 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127).
Table 1 ROM size and pages
Product
M34280M1
ROM size (✕ 9 bits)
Pages
1024 words
8 (0 to 7)
M34280E1
Page 2 (addresses 0100 16 to 017F16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern of all addresses can be used as data areas with
the TABP p instruction.
8
000016
007F16
008016
00FF16
010016
017F16
018016
7
6
5
4
3
2
1 0
Page 0
Page 1
Subroutine special page
Page 2
Page 3
Page 7
03FF16
Fig. 10 ROM map of M34280M1
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers X and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
M34280M1
M34280E1
Register X 0
Register Y
Table 2 RAM size
Product
RAM 32 words × 4 bits (128 bits)
RAM size
32 words ✕ 4 bits (128 bits)
1
2
3
0
1
2
3
4
5
6
7
32 words
Fig. 11 RAM map
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
TIMERS
The 4280 Group has the programmable timer.
• Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer 1
underflow flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 underflow flag
A skip instruction is executed.
Fig. 12 Auto-reload function
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4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
The 4280 Group timer consists of the following circuit.
• Timer 1 : 8-bit programmable timer
This timer can be controlled with the timer control register V1.
Timer 1 function is described below.
Table 3 Function related timer
Circuit
Structure
Timer 1
Frequency
dividing ratio
Count source
8-bit programmable
binary down counter
• Carrier generating circuit 1 to 256
Use of output signal
• Carrier wave output control
Control
register
V1
output (CARRY)
• Bit 5 of watchdog timer
V11
CARRY
SNZT1 instruction
V10 (Note 1)
0
Timer 1 (8)
0
T1F
1
1
D Q
Reload register R1 (8)
(TAB1)
(T1AB)(Note 2)
Register B Register A
Frequency
divider
(divided by 4)
XIN
CCK instruction
S Q
R
T R
V10
STCK (System clock)
Frequency
divider
(divided by 8)
Initializing signal
(Note 3)
V12
Carrier wave output control signal
INSTCK
(Instruction clock)
Synchronous
circuit
Initializing signal (Note 3)
System reset
14-bit timer (WDT)
INSTCK
0
5
13
WDF1 WDF2
WRST instruction
Initializing signal
(Note 3)
Notes 1: Counting is stopped by clearing to “0.”
2: When the T1AB instruction is executed after V10 is set to “1,”
writing is performed only to reload register R1.
3: The initializing signal is output at reset or RAM back-up mode.
: Data is automatically set from a reload register
when timer 1 underflows (auto-reload function).
Fig. 13 Timers structure
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
Table 4 Control registers related to timer
Timer control register V1
V12
Carrier wave output auto-control bit
V11
Timer 1 count source selection bit
V10
Timer 1 control bit
at reset : 0002
at RAM back-up : 0002
0
1
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
0
Carrier output (CARRY)
1
0
Bit 5 of watchdog timer (WDT)
Stop (Timer 1 state retained)
1
Operating
W
Note: “W” represents write enabled.
(1) Control register related to timer
• Timer control register V1
Register V1 controls the timer 1 count source and autocontrol function of carrier wave output from port CARR by
timer 1. Set the contents of this register through register A
with the TV1A instruction.
(4) Timer 1 underflow flag (T1F)
Timer 1 underflow flag is set to “1” when the timer 1 underflows.
The state of this flag can be examined with the skip instruction
(SNZT1).
T1F flag is cleared to “0” when the next instruction is skipped
with a skip instruction.
(2) Precautions
Note the following for the use of timers.
• Count source
Stop timer 1 counting to change its count source.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
(3) Timer 1
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1).
When timer is stopped, data can be set simultaneously in timer
1 and the reload register (R1) with the T1AB instruction.
When timer is operating, data can be set to only reload register
R1 with the T1AB instruction.
When setting the next count data to reload register R1 at
operating, set data before timer 1 underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1,
➁ select the count source with the bit 1 of register V1, and
➂ set the bit 0 of register V1 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 underflow flag (T1F) is set to “1,” new data is loaded
from reload register R1, and count continues (auto-reload
function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B. When
reading the data, stop the counter and then execute the TAB1
instruction.
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
WATCHDOG TIMER
Watchdog timer provides a method to reset and restart the system
when a program runs wild. Watchdog timer consists of 14-bit
timer (WDT) and watchdog timer flags (WDF1, WDF2).
Watchdog timer downcounts the instruction clock (INSTCK) as
the count source. When the timer WDT count value becomes
0000 16 and underflow occurs, the WDF1 flag is set to “1.” Then,
when the WRST instruction is not executed before the timer WDT
counts 16383, WDF2 flag is set to “1” and internal reset signal is
generated and system reset is performed.
When using the watchdog timer, execute the WRST instruction
at period of 16383 machine cycle or less to keep the
microcomputer operation normal.
Timer WDT is also used for generation of oscillation stabilization
time. When system is returned from reset and from RAM backup mode by key-input, software starts after the stabilization
oscillation time until timer WDT downcounts to 3E00 16 elapses.
Software
start
Software
start
Software
start
3FFF16
3E0016
Value of timer WDT
0000 16
WDF1 flag
WDF2 flag
“1”
“0”
“1”
“0”
“H”
Internal reset signal
“L”
System reset
POF
instruction
execution
Return
WRST
instruction
execution
System reset
Fig. 14 Watchdog timer function
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
CARRIER GENERATING CIRCUIT
The 4280 Group can output the various carrier waveforms by
the carrier wave selection register C.
Set the contents of this register through register A with the TCA
instruction. The TAC instruction can be used to transfer the
contents of register C to register A. When the TCA instruction is
executed, the output latch of port CARR is cleared to “0.”
The carrier waveform selected by setting register C can be output
from port CARR by setting port CARR output latch to “1.” When
the CARR output latch is cleared to “0,” carrier wave output is
stopped and port CARR output is fixed to “L” level. The CARR
output latch can be set through bit 3 (A 3) of register A with the
OCRA instruction.
The relationship between the setting value of register C and
selected waveform is described below.
Also, timer 1 can auto-control the carrier wave output from port
CARR by setting the timer control register V1.
Carrier wave selection register C (at reset: 1112, at RAM back-up: 1112)
Register C
setting value
Output waveform
LA
8
O CRA
(TC A)
LA
0
O CRA
Frequency
C2 C 1 C0
0
0
0
Carrier wave
Duty
1/3
“H”
“L”
System clock/
12
0
0
1
1/2
“H”
“L”
0
1
0
1/4
“H”
“L”
0
1
1
“H”
1
0
0
“H”
1
0
1
1
1
0
System clock/
8
1/2
“L”
System clock
No carrier wave
“H”
“L”
f(XIN)/4
(Note)
“H”
“L”
1
1
1
“H”
1/2
“L” level fixed
“L”
Note: This carrier wave can be used only when system clock f(XIN)/8 is selected.
The carrier wave output is fixed to “L” level when system clock f(XIN) is selected.
Fig. 15 Carrier wave selection register
14
1/2
“L”
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4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
Timer 1 start
(V10)←1
Timer 1 underflow
“1”
“0”
Port CARR output
a
c
b
d
“H”
“L”
a
Set the interval “a” to timer 1.
Select count source CARRY
(V11)←0
c
b
d
Set the interval “b” Set the interval “c”
Set the interval “d”
to reload register R1. to reload register R1. to reload register R1.
Auto-control valid
(V12)←1
Carrier wave output start
Timer 1 stop
(V10)←0
Timer 1 underflow
CARRY
“1”
“0”
“H”
“L”
(Note)
Port CARR output
“H”
“L”
“1”
Register V12 “0”
Auto-control invalid
Auto-control invalid
Carrier wave output start
Carrier wave output stop
(V12)←0
(V12)←1
(V12)←0
(V12)←1
Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1.
Fig. 16 Port CARR output auto-control by timer 1
LOGIC OPERATION FUNCTION
The 4280 Group has the 4-bit logic operation function. The logic
operation between the contents of register A and the low-order 4
bits of register E is performed and its result is stored in register
A.
Each logic operation can be selected by setting logic operation
selection register LO.
Set the contents of this register through register A with the TLOA
instruction. The logic operation selected by register LO is
executed with the LGOP instruction.
Table 5 shows the logic operation selection register LO.
Table 5 Logic operation selection register LO
Logic operation selection register LO
at reset : 002
at RAM back-up : 002
W
LO1 LO0
0
1
Logic operation function
0 Exclusive logic OR operation (XOR)
1 OR operation (OR)
0 AND operation (AND)
1
1 Not available
0
LO1
Logic operation selection bits
LO0
Note: “W” represents write enabled.
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
RESET FUNCTION
The 4280 Group has the power-on reset circuit, though it does
not have RESET pin. System reset is performed automatically
at power-on, and software starts program from address 0 in page
0.
In order to make the built-in power-on reset circuit operate
efficiently, set the voltage rising time until VDD= 0 to 2.2 V is
obtained at power-on 1ms or less.
f(XIN)
“H”
Internal reset signal
“L”
Software starts
(address 0 in page 0)
f(XIN) 16384 pulses
Fig. 17 Reset release timing
VDD
Power-on reset circuit
output voltage
Internal reset signal
Power-on reset circuit
Reset state
Voltage drop detection circuit
Watchdog timer output
Internal reset signal
Reset released
Power-on
Fig. 18 Power-on reset circuit example
16
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4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(1) Internal state at reset
Table 6 shows port state at reset, and Figure 19 shows internal
state at reset (they are retained after system is released from
reset).
The contents of timers, registers, flags and RAM except shown
in Figure 19 are undefined, so set the initial value to them.
• Program counter (PC) .............................................................. 0
0
0
0
• Timer 1 underflow flag (T1F) ................................................... 0
• Timer control register V1 .......................................................... 0
• Carrier wave selection register C ............................................ 1
0
1
0
1
• Pull-down control register PU0 ................................................ 0
• Logic operation selection register LO ...................................... 0
0
0
0
• Most significant ROM code reference enable flag (URS)
0
• Carry flag (CY) ......................................................................... 0
• Register A ................................................................................. 1
1
1
1
• Register B ................................................................................. 1
• Stack pointer (SP) .................................................................... 1
1
1
1
1
0
0
0
0
0
0
Address 0 in page 0 is set to program counter.
• Power down flag (P) ................................................................. 0
Fig. 19 Internal state at reset
Table 6 Port state at reset
Name
“H” output
D0–D6
State at reset
State after system is released from reset
High impedance state
“H” output
Input port (Pull-down transistor ON)
G0–G3, E2
Input circuit OFF (Pull-down transistor OFF)
E0, E1
Note: The contents of all output latch is initialized to “0.”
D7
VOLTAGE DROP DETECTION CIRCUIT
The built-in drop detection circuit is designed to detect a drop in
voltage at operating and to reset the microcomputer if the supply
voltage drops below the specified value (Typ. 1.50 V) or less.
Input circuit OFF (Pull-down transistor OFF)
Input port (Pull-down transistor ON)
Input port (Pull-down transistor OFF)
The voltage drop detection circuit is stopped and power
dissipation is reduced at the RAM back-up mode, when the
functions except the RAM and pull-down control register (PU0)
are initialized.
VDD
Reset voltage
Microcomputer starts operation
after f(XIN) is counted to 16384 times.
Internal reset signal
Fig. 20 Voltage drop detection circuit operation waveform
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
RAM BACK-UP MODE
Table 7 Functions and states retained at RAM back-up
The 4280 Group has the RAM back-up mode.
When the POF instruction is executed, system enters the RAM
back-up state.
As oscillation stops retaining RAM, the function of reset circuit
and states at RAM back-up mode, power dissipation can be
reduced without losing the contents of RAM. Table 7 shows the
function and states retained at RAM back-up. Figure 21 shows
the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
(2) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF
instruction, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the software from address 0 in page
0 when any of the following conditions is satisfied .
• reset by power-on reset circuit is performed
• reset by watchdog timer is performed
• reset by voltage drop detection circuit is performed
In this case, the P flag is “0.”
18
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port E0
Port E1
✕
O
✕ (“H” output)
Ports D0–D6 (Note 3)
Port D7
RAM back-up
(PU02)=0 (Note 3) ✕ (“H” output)
(PU02)=1
✕ (input)
(PU00)=0 (Note 4) ✕ (input cut-off)
(PU00)=1
✕ (input)
(PU01)=0 (Note 4) ✕ (input cut-off)
(PU01)=1
✕ (input)
Port G
Timer control register V1
Pull-down control register PU0
Logic operation selection register LO
Timer 1 function
Timer 1 underflow flag (T1F)
Watchdog timer (WDT)
Watchdog timer flag 1 (WDF1)
✕ (input)
✕
O
✕
✕
✕
✕
Watchdog timer flag 2 (WDF2)
✕
✕
Most significant ROM code reference enable flag (URS)
✕
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “112” at RAM back-up.
3: The contents of port output latch is initialized to “0.”
However, port continues to output “H” level.
4: The state of this bit is equal to the state at reset.
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(4) Return signal
An external wakeup signal is used to return from the RAM
back-up mode. Table 8 shows the return condition for each
return source.
Table 8 Return source and return condition
Return source
Return condition
Remarks
Ports D7, E0, E1
Return by an external “H” level Only key-on wakeup function of the port whose pull-down transistor is
input.
turned ON is valid.
Ports G, E2
Return by an external “H” level Key-on wakeup function is always valid.
input.
(5) Pull-down control register PU0
• Pull-down control register PU0
Register PU0 controls the ON/OFF of pull-down transistor,
input, key-on wakeup function of ports E0, E1 and D7.
Set the contents of this register through register A with the
TPU0A instruction.
Table 9 Pull-down control register
Pull-down control register PU0
PU0 2
Port D7 pull-down control bit
PU0 1
Port E1 pull-down control bit
PU0 0
Port E0 pull-down control bit
at reset : 0002
at RAM back-up : state retained
W
0
Pull-down transistor OFF, input circuit OFF, key-on wakeup invalid
1
0
Pull-down transistor ON, input circuit ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
1
0
Pull-down transistor ON, key-on wakeup valid
1
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Note: “W” represents write enabled.
POF instruction
is executed
A
B
f(XIN) stop
(Stabilizing time a )
Reset
f(XIN) oscillation
Return input
(Stabilizing time a )
(RAM back-up
mode)
Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times.
Fig. 21 State transition
Power down flag P
POF instruction
S
Reset input
R
Software start
Q
P = “1”
?
Yes
No
● Set source
● Clear source
Cold start
POF instruction is executed
Reset input
Fig. 22 Set source and clear source of the P flag
Warm start
Fig. 23 Start condition identified example using the SNZP
instruction
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to return from the RAM back-up state
CCK instruction
XIN
XOUT
OSC
Frequency
divider
(divided by 8)
Internal clock
generating circuit
(divided by 4)
Multiplexer
INSTCK
STCK
Internal power-on reset circuit
POF instruction
R
S
Q
Pull-down control
register PU0
Port D7
Ports E0, E1
Ports E2, G0–G3
Fig. 24 Clock control circuit structure
Clock signal f(XIN) is obtained by externally connecting a ceramic
resonator. Connect this external circuit to pins XIN and XOUT at
the shortest distance as shown Figure 26.
A feedback resistor is built-in between XIN pin and XOUT pin.
4280
XIN
4
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) Mask ROM Order Confirmation Form................................. 1
(2) Data to be written into mask ROM .......................... EPROM
(three sets containing the identical data)
(3) Mark Specification Form .................................................... 1
CIN
Use the resonator
manufacturer’s
recommended value
because constants
such as capacitance
depend on the
resonator.
XOUT
5
COUT
Fig. 25 Ceramic resonator external circuit
20
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.01 µF) between pins
V DD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the One Time PROM version, port E2 is also used as VPP
pin. Connect this pin to V SS through the resistor about 5 kΩ
which is assigned to E 2/V PP pin as close as possible at the
shortest distance.
➁ Notes on unused pins
(Note in order to set the output latch to “0” to make pins open)
• After system is released from reset, a port is in a highimpedance state until the output latch of the port is set to
“0” by software.
Accordingly, the voltage level of pins is undefined and the
excess of the supply current may occur.
• To set the output latch periodically is recommended
because the value of output latch may change by noise or
a program run away (caused by noise).
(Note when connecting to V SS and VDD)
• Connect the unused pins to V SS and VDD at the shortest
distance and use the thick wire against noise.
➂ Timer
• Count source
Stop timer 1 counting to change its count source.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
➃ Program counter
Make sure that the program counter does not specify after the
last page of the built-in ROM.
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Contents
Symbol
A
B
DR
ER
C
V1
PU0
LO
X
Y
DP
PC
PCH
PCL
SK
SP
CY
R1
T1
T1F
WDT
WDF1
WDF2
URS
P
STCK
INSTCK
Contents
Symbol
Register A (4 bits)
D
E
Register B (4 bits)
Register D (3 bits)
G
CARR
Register E (8 bits)
Carrier wave selection register C (3 bits)
Timer control register V1 (3 bits)
Pull-down control register PU0 (3 bits)
Logic operation selection register LO (2 bits)
x
y
p
n
Port D (8 bits)
Port E (3 bits)
Port G (4 bits)
Port CARR (1 bit)
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant which represents the
Register X (2 bits)
Register Y (4 bits)
j
immediate value
Hexadecimal constant which represents the
Data pointer (6 bits)
(It consists of registers X and Y)
A 3A 2A1A0
immediate value
Binary notation of hexadecimal variable A
(same for others)
Program counter (10 bits)
High-order 3 bits of program counter
Low-order 7 bits of program counter
Stack register (10 bits ✕ 4)
Stack pointer (2 bits)
Carry flag
←
↔
?
( )
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Timer 1 reload register
Timer 1
—
Negate, Flag unchanged after executing
instruction
Timer 1 underflow flag
M(DP)
RAM address pointed by the data pointer
Watchdog timer
Watchdog timer flag 1
a
p, a
Label indicating address a6 a5 a 4 a 3 a2 a1 a 0
Label indicating address a6 a5 a 4 a 3 a2 a1 a 0
Watchdog timer flag 2
Most significant ROM code reference enable flag C
Power down flag
+
System clock
Instruction clock
in page p3 p2 p1 p 0
Hex. number C + Hex. number x (also same for
others)
x
Note : The 4280 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
22
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
LIST OF INSTRUCTION FUNCTION
(B) ← (A)
LA n
Function
(A) ← n
Register to register transfer
n = 0 to 15
TABP p
TAY
(A) ← (Y)
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p p=0 to 7
TYA
(Y) ← (A)
(PC L ) ← (DR 2 –DR 0 ,
A 3–A0)
TEAB
(ER7–ER4) ← (B)
When URS=0
(ER3–ER0) ← (A)
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
TABE
(B) ← (ER 7–ER4)
(A) ← (ER 3–ER0)
When URS=1
(CY) ← (ROM(PC)) 8
Grouping Mnemonic
operation
TBA
Grouping Mnemonic
Comparison
Function
(A) ← (B)
SEAM
Function
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
Ba
Branch operation
TAB
Grouping Mnemonic
BL p, a
BA a
BLA p, a
INY
(Y) ← (Y) + 1
DEY
(A) ← (ROM(PC))3 to 0
(PC) ← (SK(SP))
XAM j
AM
(A) ← (A) + (M(DP))
(PCL) ← a 6–a 0
AMC
(A) ← (A) + (M(DP))
+ (CY)
(A) ← (M(DP))
(A) ← (A) + n
n = 0 to 15
(X) ← (X) EXOR(j)
j = 0 to 3
An
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
SC
(CY) ← 1
j = 0 to 3
RC
(CY) ← 0
(A) ←→ (M(DP))
SZC
(CY) = 0 ?
(X) ← (X) EXOR(j)
j = 0 to 3
CMA
(A) ← (A)
RAR
→ CY → A3A2A 1A 0
LGOP
Logic operation
instruction
(Y) ← (Y) – 1
XAMI j
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(Y) ← (Y) – 1
BML p, a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p p= 0 to 7
(PCL) ← a 6–a 0
BMLA p, (SP) ← (SP) + 1
(SK(SP)) ← (PC)
a
(PCH) ← p p= 0 to 7
(PCL) ← (a6–a4, A 3–A0)
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
XOR, OR, AND
SB j
(Mj(DP)) ← 1
j = 0 to 3
Bit operation
RAM to register transfer
XAMD j
(PCH) ← p
(SP) ← (SP) – 1
(CY) ← Carry
TAM j
BM a
Subroutine operation
(X) ← x, x = 0 to 3
(Y) ← y, y = 0 to 15
(PCL) ← (a6–a4, A 3–A0)
(PCL) ← (a6–a4, A 3–A0)
Return operation
LXY x, y
Arithmetic operation
RAM addresses
(DR2–DR0) ← (A2–A0)
(PCH) ← p
(PCL) ← a 6–a 0
(B) ← (ROM(PC))7 to 4
TDA
(PCL) ← a 6–a 0
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
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MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Grouping Mnemonic
TV1A
Function
(V12–V10) ← (A2–A0)
TAB1
(B) ← (T17–T14)
Grouping Mnemonic
NOP
Function
(PC) ← (PC) + 1
POF
RAM back-up
SNZP
(P) = 1 ?
CCK
STCK changes to f(XIN)
TLOA
(LO1, LO0) ← (A1, A0)
URSC
(URS) ← 1
TPU0A
(PU0 2–PU00) ← (A2–A0)
WRST
(WDF1) ← 0
(A) ← (T13–T10)
at timer 1 stop (V10=0):
Timer operation
(R17–R1 4) ← (B)
(T17–T14) ← (B)
(R13–R1 0) ← (A)
(T13–T10) ← (A)
at timer 1 operating:
(V10=1)
(R17–R1 4) ← (B)
Other operation
T1AB
(R13–R1 0) ← (A)
SNZ1
(T1F) = 1 ?
After skipping the next
instruction
Carrier wave
Input/Output operation
control operation
(T1F) ← 0
24
TCA
(C 2–C0) ← (A2–A0)
(CARR) ← 0
TAC
(A 2–A 0) ← (C2–C0)
OCRA
(CARR) ← (A3)
CLD
(D) ← 1
RD
(D(Y)) ← 0
(Y) = 0 to 7
SD
(D(Y)) ← 1
(Y) = 0 to 7
SZD
(D(Y)) = 0 ?
(Y) = 7
OEA
(E 1, E 0) ← (A1, A0)
IAE
(A 2–A 0) ← (E2–E0)
OGA
(G) ← (A)
IAG
(A) ← (G)
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
INSTRUCTION CODE TABLE
D8–D4
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
D3–
D0
Hex.
notation
00
0000
0
NOP
0001
1
BA
0010
2
0011
3
0100
06
07
TAC BMLA
XAM
0
BML
BL
LGOP
XAM
1
SZB
2
BL
SNZT1
INY
SZB
3
BL
4
RD
SZD
BL
0101
5
SD
SEAn
BL
0110
6
RC
SEAM
BL
0111
7
SC
1000
8
1001
9
1010
A
AM
1011
B
AMC
1100
C
TYA
CMA
1101
D
POF
1110
E
TBA
1111
F
SNZP
01
02
03
BLA
SZB
0
BL
CLD
SZB
1
0B
0C
0D
0E
0F
OGA TABP
0
A
0
LA
0
LXY
0,0
LXY
1,0
LXY
2,0
LXY
3,0
BM
B
BML
TABP
1
A
1
LA
1
LXY
0,1
LXY
1,1
LXY
2,1
LXY
3,1
BM
B
XAM
2
BML
URSC TABP
2
A
2
LA
2
LXY
0,2
LXY
1,2
LXY
2,2
LXY
3,2
BM
B
XAM
3
BML
TABP
3
A
3
LA
3
LXY
0,3
LXY
1,3
LXY
2,3
LXY
3,3
BM
B
RT
TAM
0
BML
OEA TABP
4
A
4
LA
4
LXY
0,4
LXY
1,4
LXY
2,4
LXY
3,4
BM
B
RTS
TAM
1
BML
TABP
5
A
5
LA
5
LXY
0,5
LXY
1,5
LXY
2,5
LXY
3,5
BM
B
TAM
2
BML OCRA
TABP
6
A
6
LA
6
LXY
0,6
LXY
1,6
LXY
2,6
LXY
3,6
BM
B
T1AB TAB1
TAM
3
BML
TABP
7
A
7
LA
7
LXY
0,7
LXY
1,7
LXY
2,7
LXY
3,7
BM
B
IAG
TLOA
XAMI
0
A
8
LA
8
LXY
0,8
LXY
1,8
LXY
2,8
LXY
3,8
BM
B
TDA
CCK
XAMI
1
A
9
LA
9
LXY
0,9
LXY
1,9
LXY
2,9
LXY
3,9
BM
B
TCA
XAMI
2
A
10
LA
10
LXY
0,10
LXY
1,10
LXY
2,10
LXY
3,10
BM
B
TV1A
XAMI
3
A
11
LA
11
LXY
011
LXY
1,11
LXY
2,11
LXY
3,11
BM
B
RB
0
SB
0
XAMD
0
A
12
LA
12
LXY
0,12
LXY
1,12
LXY
2,12
LXY
3,12
BM
B
RAR
RB
1
SB
1
XAMD
1
A
13
LA
13
LXY
0,13
LXY
1,13
LXY
2,13
LXY
3,13
BM
B
TAB
RB
2
SB
2
XAMD
2
A
14
LA
14
LXY
0,14
LXY
1,14
LXY
2,14
LXY
3,14
BM
B
RB
3
SB
3
XAMD
3
A
15
LA
15
LXY
0,15
LXY
1,15
LXY
2,15
LXY
3,15
BM
B
BL
IAE
TEAB TABE
WRST TAY
SZC
05
08
09
10111 11111
0A
DEY
04
10000 11000
TPU0A
10–17 18–1F
The above table shows the relationship between machine language codes and machine language instructions. D3–D0
show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language
code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word
instructions, but only the first word of each instruction is shown. Do not use the code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
BL
BML
BA
BLA
BMLA
SEA
SZD
1
1
1
1
1
0
0
1aaa
0aaa
1aaa
1aaa
0aaa
1011
0010
aaaa
aaaa
aaaa
0ppp
0ppp
nnnn
1011
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Number of
words
Number of
cycles
TAB
0
0
0
0
1
1
1
1
0
0 1
E
1
1
(A) ← (B)
–
–
Transfers the contents of register B to register A.
TBA
0
0
0
0
0
1
1
1
0
0 0
E
1
1
(B) ← (A)
–
–
Transfers the contents of register A to register B.
TAY
0
0
0
0
1
1
1
1
1
0 1
F
1
1
(A) ← (Y)
–
–
Transfers the contents of register Y to register A.
TYA
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
–
–
Transfers the contents of register A to register Y.
TEAB
0
0
0
0
1
1
0
1
0
0 1
A
1
1
(ER7–ER 4) ← (B) (ER3–ER0) ← (A)
–
–
Transfers the contents of registers A and B to register E.
TABE
0
0
0
1
0
1
0
1
0
0 2
A
1
1
(B) ← (ER7–ER 4) (A) ← (ER3–ER 0)
–
–
Transfers the contents of register E to registers A and B.
TDA
0
0
0
1
0
1
0
0
1
0 2
9
1
1
(DR2–DR 0) ← (A2–A0)
–
–
Transfers the contents of register A to register D.
LXY x, y
0
1
1
x1 x0 y3 y2 y1 y0
0 C y
1
1
(X) ← x, x = 0 to 3
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
Y.
Instruction code
Parameter
Mnemonic
D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0
Register to register transfer
Type of
instructions
Hexadecimal
notation
Function
(Y) ← y, y = 0 to 15
+x
RAM addresses
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
Detailed description
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
INY
0
0
0
0
1
0
0
1
1
0 1
DEY
0
0
0
0
1
0
1
1
1
0 1 7
3
1
1
(Y) ← (Y) + 1
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
1
1
(Y) ← (Y) – 1
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
TAM j
0
0
1
1
0
0
1
j1
j0
0 6
4
1
1
+j
(A) ← (M(DP))
(X) ← (X) EXOR(j)
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
j = 0 to 3
RAM to register transfer
XAM j
0
0
1
1
0
0
0
j1
j0
0 6
j
1
1
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(X) ← (X) EXOR(j)
j = 0 to 3
XAMD j
0
0
1
1
0
1
1
j1
j0
0 6 C
+j
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
(Y) ← (Y) – 1
XAMI j
0
0
1
1
0
1
0
j1
j0
0 6
8
1
1
+j
26
(A) ←→ (M(DP))
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(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
j = 0 to 3
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
(Y) ← (Y) + 1
next instruction is skipped.
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Number of
cycles
0 B n
1
1
Instruction code
Parameter
Mnemonic
D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0
Type of
instructions
LA n
TABP p
0
0
1
1
0
0
1
0
1
1
n3 n 2 n 1 n 0
0
p2 p1 p0
0 9
p
1
3
Skip condition
Carry flag CY
Hexadecimal
notation
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
(A) ← n
Continuous
–
n = 0 to 15
description
Function
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
–
(PCH) ← p, p=0 to 7
(PCL) ← (DR2–DR 0, A3–A0)
Detailed description
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits
7 to 0 are the ROM pattern in address (DR2 DR 1 DR 0 A3 A2 A1 A0) specified by registers A and D in
page p.
0/1 When this instruction is executed, 1 stage of stack register is used.
When URS=0,
Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
instruction is executed).
One of stack is used when the TABP p instruction is executed.
When URS=1,
(CY) ← (ROM(PC))8
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(SP) ← (SP) – 1
(PC) ← (SK(SP))
Arithmetic operation
AM
0
0
0
0
0
1
0
1
0
0 0
A
1
1
(A) ← (A) + (M(DP))
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
AMC
0
0
0
0
0
1
An
0
1
0
1
0
n3 n 2 n 1 n 0
0
1
1
B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
0 A n
1
1
(A) ← (A) + n
n = 0 to 15
0 0
–
Overflow = 0
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
SC
0
0
0
0
0
0
1
1
1
0 0
7
1
1
(CY) ← 1
–
1
Sets (1) to carry flag CY.
RC
0
0
0
0
0
0
1
1
0
0 0
6
1
1
(CY) ← 0
–
0
Clears (0) to carry flag CY.
SZC
0
0
0
1
0
1
1
1
1
0 2
F
1
1
(CY) = 0 ?
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
CMA
0
0
0
0
1
1
1
0
0
0 1
C
1
1
(A) ← (A)
–
–
Stores the one‘s complement for register A‘s contents in register A.
RAR
0
0
0
0
1
1
1
0
1
0 1
D
1
1
→ CY → A 3A 2A1A 0
–
LGOP
0
0
1
0
0
0
0
0
1
0 4
1
1
1
Logic operation instruction XOR, OR, AND
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
Execute the logic operation selected by logic operation selection register LO between the contents of
register A and register E, and stores the result in register A.
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D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0
SB j
0
0
1
0
1
1
1
j1
j0
Hexadecimal
notation
0 5
C
1
1
Bit operation
operation
Comparison
SZB j
0
0
0
0
1
0
0
1
0
0
1
0
1
0
j1
j1
j0
j0
0 4
0 2
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0 ?
j = 0 to 3
(Mj(DP)) = 0
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Function
(Mj(DP)) ← 1
C
+j
1
j
1
1
(Mj(DP)) ← 0
j = 0 to 3
1
SEAM
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
n = 0 to 15
0
1
0
1
1
n3 n 2 n 1 n 0
1
1
a 6 a 5 a4 a3 a 2 a 1 a 0
Ba
Detailed description
j = 0 to 3
+j
RB j
Skip condition
Carry flag CY
Mnemonic
Type of
instructions
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
j = 0 to 3
of M(DP) is “0.”
n = 0 to 15
0 B n
1
8
a
1
1
p
2
2
(PCL) ← a6–a0
–
–
Branch within a page : Branches to address a in the identical page.
(PCH) ← p
–
–
Branch out of a page : Branches to address a in page p.
–
–
+a
BL p, a
0
0
0
1
1
p3 p 2 p 1 p 0
0 3
Branch operation
(PCL) ← a6–a0
(Note)
BA a
1
1
a 6 a 5 a4 a3 a 2 a 1 a 0
1 8 a
+a
0
0
0
0 0
0
0
0
0
0
1
1
2
2
(PCL) ← (a6–a4, A3–A0)
Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in the identical page with register A.
BLA p, a
1
1
a 6 a 5 a4 a3 a 2 a 1 a 0
1 8 a
+a
0
0
0
0 1
1
1
0
1
0
0
0
0
a 6 a 5 a4 p3 p 2 p 1 p 0
0
2
2
1 8 p
+a
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
–
–
Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in page p with register A.
(Note)
Note : p is 0 to 7 for M34280E1, and p is 0 to 7 for M34280M1.
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BM a
D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0
Hexadecimal
notation
1
1
0
a 6 a 5 a4 a3 a 2 a 1 a 0
a
a
1
1
Function
(SK(SP)) ← (PC)
Skip condition
Carry flag CY
Mnemonic
Type of
instructions
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the
low-order 4 bits of address a in page p with register A.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
–
–
Transfers the contents of timer 1 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 1.
–
–
Transfers the contents of register A to registers V1.
(T1F) = 1
–
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears (0) to T1F flag.
Detailed description
(SP) ← (SP) + 1
(PCH) ← 2
(PCL) ← a 6–a0
Subroutine operation
BML p, a
0
0
1
1
1
p3 p 2 p 1 p 0
0 7
p
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
1
0
a 6 a 5 a4 a3 a 2 a 1 a 0
1 a a
BMLA p, a 0
0
1
0 5
0
1
0
a 6 a 5 a4 p3 p 2 p 1 p 0
1 a
p
0
1
0
0
0
0
(PCL) ← a 6–a0
(Note)
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
(PCL) ← (a 6–a4, A3–A0)
(Note)
Return operation
RT
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
TAB1
0
0
1
0
1
0
1
1
1
0 5 7
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
Timer operation
T1AB
0
0
1
0
0
0
1
1
1
0 4 7
1
1
at timer 1 stop (V10=0)
(R17–R1 4) ← (B), (R1 3–R10) ← (A)
(T17–T14) ← (B), (T13–T10) ← (A)
at timer 1 operating (V1 0=1)
(R17–R1 4) ← (B), (R1 3–R10) ← (A)
TV1A
0
0
1
0
1
1
0
1
1
0 5 B
1
1
(V12–V10) ← (A2–A0)
SNZ1
0
0
1
0
0
0
0
1
0
0 4 2
1
1
(T1F) = 1 ?
After skipping the next instruction
Carrier wave
control operation
(T1F) ← 0
TAC
0
0
1
0
0
0
0
0
0
0 4 0
1
1
(A 2–A 0) ← (C2–C0)
–
–
Transfers the contents of register A to register C.
TCA
0
0
1
0
1
1
0
1
0
0 5 A
1
1
(C 2–C0) ← (A2–A0), (CARR) ← 0
–
–
Transfers the contents of register C to register A. In this case, port CARR output latch is cleared to “0.”
OCRA
0
1
0
0
0
0
1
1
0
0 8 6
1
1
(CARR) ← (A3)
–
–
Transfers the contents of bit 3 (A3) of register A to port CARR output latch.
Note : p is 0 to 7 for M34280E1, and p is 0 to 7 for M34280M1.
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Number of
words
Number of
cycles
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS (CONTINUED)
CLD
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 0
–
–
Clears (0) to port D (high-impedance state).
RD
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
–
–
Clears (0) to a bit of port D specified by register Y (high-impedance state).
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
(Y) = 7
–
Skips the next instruction when a bit of port D specified by register Y is “0.”
Instruction code
Parameter
Mnemonic
D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0
Type of
instructions
Hexadecimal
notation
Function
Detailed description
(Y) = 0 to 7
Input/Output operation
SD
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
1
0
0
1
0
0
0 2 4
2
2
(D(Y)) = 0 ?
(Y) = 7
0
0
0
1
0
1
0
1
1
0 2 B
OEA
0
1
0
0
0
0
1
0
0
0 8 4
1
1
(E 1, E0) ← (A1, A 0)
–
–
Outputs the contents of register A to port E.
IAE
0
0
1
0
1
0
1
1
0
0 5 6
1
1
(A 2–A0) ← (E2–E0)
–
–
Transfers the contents of port E to register A.
OGA
0
1
0
0
0
0
0
0
0
0 8 0
1
1
(G) ← (A)
–
–
Outputs the contents of register A to port G.
IAG
0
0
0
1
0
1
0
0
0
0 2 8
1
1
(A) ← (G)
–
–
Transfers the contents of port G to register A.
NOP
0
0
0
0
0
0
0
0
0
0 0
0
1
1
(PC) ← (PC) + 1
–
–
No operation
POF
0
0
0
0
0
1
1
0
1
0 0
D
1
1
RAM back-up
–
–
Puts the system in RAM back-up state.
SNZP
0
0
0
0
0
0
0
1
1
0 0
3
1
1
(P) = 1 ?
(P) = 1
–
Skips the next instruction when P flag is “1.”
Other operation
After skipping, P flag remains unchanged.
34
CCK
0
0
1
0
1
1
0
0
1
0 5
9
1
1
STCK changes to f(X IN)
–
–
System clock (STCK) changes to f(XIN) from f(XIN)/8. Execute this CCK instruction at address 0 in page
0.
TLOA
0
0
1
0
1
1
0
0
0
0 5
8
1
1
(LO1, LO0) ← (A1, A0)
–
–
Transfers the contents of register A to the logic operation selection register LO.
URSC
0
1
0
0
0
0
0
1
0
0 8
2
1
1
(URS) ← 1
–
–
Sets the most significant ROM code reference enable flag (URS) to “1.”
TPU0A
0
1
0
0
0
1
1
1
1
0 8
F
1
1
(PU0 2–PU00) ← (A2–A0)
–
–
Transfers the contents of register A to register PU0.
WRST
0
0
0
0
0
1
1
1
1
0 0
F
1
1
(WDF1) ← 0
–
–
Initializes the watchdog timer flag (WDF1).
MITSUBISHI
ELECTRIC
MITSUBISHI
ELECTRIC
35
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
CONTROL REGISTERS
Timer control register V1
V12
Carrier wave output auto-control bit
V11
Timer 1 count source selection bit
V10
Timer 1 control bit
at reset : 0002
0
1
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
0
Carrier output (CARRY)
1
0
Bit 5 of watchdog timer (WDT)
Stop (Timer 1 state retained)
1
Operating
Pull-down control register PU0
at reset : 0002
Port E 1 pull-down control bit
0
1
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Port E 0 pull-down control bit
0
1
Pull-down transistor OFF, key-on wakeup invalid
PU0 1
PU0 0
Carrier wave selection register C
Pull-down transistor ON, key-on wakeup valid
at reset : 1112
C2 C1 C0
C2
Carrier wave selection bits
C0
LO1
Logic operation selection bits
R/W
Carrier wave
0 0 0
Duty
1/3
0 0 1
0 1 0
System clock/12
System clock/8
1/2
1/4
0 1 1
System clock/8
1/2
1 0 0
1 0 1
System clock
1 1 0
1 1 1
f(XIN)/4 (Note 2)
1/2
No carrier wave
at reset : 002
1/2
“L” level fixed
at RAM back-up : 002
LO1 LO0
Logic operation function
0
0 Exclusive logic OR operation (XOR)
0
1 OR operation (OR)
1
0 AND operation (AND)
1
1 Not available
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: f(XIN ) is valid only when f(XIN)/8 is selected as the system clock.
36
at RAM back-up : 1112
Frequency
System clock/12
Logic operation selection register LO
LO0
W
Pull-down transistor OFF, input circuit OFF, key-on wakeup invalid
Pull-down transistor ON, input circuit ON, key-on wakeup valid
Port D7 pull-down control bit
0
at RAM back-up : state retained
W
1
PU0 2
C1
at RAM back-up : 0002
MITSUBISHI
ELECTRIC
W
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDD
VI
VO
Pd
Conditions
Supply voltage
Input voltage
Output voltage
Topr
Power dissipation
Operating temperature range
Tstg
Storage temperature range
Ta = 25 °C
Unit
Ratings
–0.3 to 5
–0.3 to VDD+0.3
V
V
–0.3 to VDD+0.3
300
V
mW
–20 to 85
°C
–40 to 125
°C
RECOMMENDED OPERATING CONDITIONS
(Ta = –20 °C to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted)
Symbol
VDD
VRAM
Supply voltage
RAM back-up voltage (at RAM back-up mode)
VSS
Supply voltage
“H” level input voltage Ports D7, E, G
VIH
VIH
VIL
VIL
Limits
Parameter
Conditions
Min.
Typ.
1.8
1.4
Max.
3.6
V
3.6
V
V
V
0
“H” level input voltage XIN
“L” level input voltage Ports D7, E, G
“L” level input voltage XIN
IOH(peak) “H” level peak output current Ports D, E1, G
IOH(peak) “H” level peak output current Port E0
VDD = 3 V
VDD = 3 V
0.7VDD
0.8VDD
VDD
VDD
VDD = 3 V
VDD = 3 V
0
0
0.2VDD
V
V
0.2VDD V
–4
mA
–24
mA
–20
mA
VDD = 3 V
VDD = 3 V
VDD = 3 V
IOH(peak) “H” level peak output current CARR
Unit
VDD = 3 V
4
mA
IOH (avg) “H” level average output current Port E0
VDD = 3 V
VDD = 3 V
–2
–12
mA
mA
IOH (avg) “H” level average output current CARR
IOL (avg) “L” level average output current CARR
VDD = 3 V
VDD = 3 V
–10
mA
2
4
mA
MHz
500
1.80
kHz
IOL(peak) “L” level peak output current CARR
IOH (avg) “H” level average output current Ports D, E1, G
f(XIN)
System clock frequency
when STCK = f(XIN)/8 selected Ceramic resonance
when STCK = f(XIN ) selected Ceramic resonance
1.10
VDET
Voltage drop detection circuit detection voltage
TDET
Voltage drop detection circuit low voltage
determination time
TPON
Power-on reset circuit valid power source rising time
Ta=25 °C
Supply voltage is -10V/s and
drops under detected voltage.
VDD = 0 to 2.2 V
1.40
V
1.50
1.56
0.16
1.2
ms
1
ms
Note: The average output current ratings are the average current value during 100 ms.
MITSUBISHI
ELECTRIC
37
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
ELECTRICAL CHARACTERISTICS
(Ta = –20 °C to 85 °C, VDD = 3 V, unless otherwise noted)
Symbol
Parameter
Test conditions
V OL
“L” level output voltage Port CARR
IOL = 2 mA
V OH
“H” level output voltage Ports D, E1, G
IOH = –2 mA
V OH
V OH
“H” level output voltage Port E0
“H” level output voltage CARR
IOH = –12 mA
IOH = –10 mA
IIL
“L” level input current Ports D7, E, G
IIH
“H” level input current Ports E0, E1
V I = V SS
V I = V DD
IOZ
Output current at off-state Ports D, E0, E1
Limits
Min.
Max.
0.9
2.1
1.5
Pull-down transistor in off-state
V O = V SS
f(XIN ) = 4.0 MHz
V
µA
1
µA
–1
µA
400
800
f(XIN ) = 500 kHz
Supply current (at RAM back-up)
350
1
700
3
Ta = 25 °C
0.1
150
0.5
300
Pull-down resistor value Ports D7, E, G
R OSC
Feedback resistor value between XIN–X OUT
V DD = 3 V, VI = 3 V
75
700
BASIC TIMING DIAGRAM
Parameter
Machine cycle
Pin name
System clock
STCK
Ports D, E0, E1, G
output
D0–D7,E0,E1
G0–G3
Ports D7, E, G input
Mi
D7
E0–E2
G0–G3
MITSUBISHI
ELECTRIC
Mi+1
V
–1
Supply current (when operating)
R PH
Unit
V
V
1.0
IDD
38
Typ.
3200
µA
µA
µA
kΩ
kΩ
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4280 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing
to built-in PROM.
Table 10 Product of built-in PROM version
PROM size
Product
(✕ 9 bits)
M34280E1FP
1024 words
M34280E1GP
1024 words
RAM size
Table 10 shows the product of built-in PROM version. Figure 26
and 27 show the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
Package
(✕ 4 bits)
ROM type
20P2N-A
20P2E/F-A
32 words
32 words
One Time PROM [shipped in blank]
One Time PROM [shipped in blank]
PIN CONFIGURATION (TOP VIEW)
1
20
VDD
E2
2
19
CARR
E1
3
18
D0
XIN
4
17
D1
XOUT
5
16
D2
E0
6
15
D3
G0
7
14
D4
G1
8
13
D5
G2
9
12
D6
G3
10
11
D7
M34280E1FP/GP
VSS
Outline 20P2N-A
20P2E/F-A
Fig. 26 Pin configuration of built-in PROM version
MITSUBISHI
ELECTRIC
39
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(1) PROM mode (serial input/output)
The M34280E1FP/GP has a PROM mode in addition to a
normal operation mode. It has a function to serially input/output
the command codes, addresses, and data required for
operation (e.g., read and program) on the built-in PROM using
only a few pins. This mode can be selected by setting pins
SDA (serial data input/output), SCLK (serial clock input), PGM
and VPP to “H” after connecting wires as shown in Figure 1
and powering on the VDD pin, and then applying 12.5V to the
VPP pin.
In the PROM mode, three types of software commands (read,
program, and program verify) can be used. Clock-synchronous
serial I/O is used, beginning from the LSB (LSB first).
Refer to the Mitsubishi Data Book “DEVELOPMENT
SUPPORT TOOLS FOR MICROCOMPUTERS” about the
serial programmer for the Mitsubishi single-chip
microcomputers.
PIN CONFIGURATION (TOP VIEW)
VSS
1
20 VDD
Vpp
E2
2
19 CARR
E1
3
18 D0
XIN
4
XOUT
5
SCLK
E0
6
SDA
G0 7
PGM
G1 8
∗
G2 9
M34280E1FP/GP
Vss
VDD
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
G3 10
Outline 20P2N-A
20P2E/F-A
∗ : connected to the ceramic resonance circuit
Note: The state of disconnected pins are the same as that at reset.
Fig. 27 Pin configuration of built-in PROM version (continued)
40
MITSUBISHI
ELECTRIC
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(2) Functional outline
In the PROM mode, data is transferred with the clocksynchronous serial input/output. The input data is read through
the SDA pin into the internal circuit synchronously with the
rising edge of the serial clock pulse. The output data is output
from the SDA pin synchronously with the falling edge of the
serial clock pulse. Data is transferred in units of 8 bits.
Table 11 Software command
Number of transfer
First command
Command
code input
1516
Read
Program
2516
Program verify
3516
Number of transfer
Command
Read
In the first transfer, the command code is input. Then, address
input or data input/output is performed according to the
contents of the command code. Table 11 shows the software
command used in the PROM mode. The following explains
each software command.
Second
Third
Fourth
Read address L (input)
Read address H (input)
Read data L (output)
Program address L (input)
Program address L (input)
Program address H (input)
Program address H (input)
Program data L (input)
Program data L (input)
Fifth
Program
Read data H (output)
Program data H (input)
Program verify
Program data H (input)
Sixth
Seventh
Verify data L (output)
Verify data H (output)
(3) Read
Input the command code 1516 in the first transfer. Proceed
and input the low-order 8 bits and the high-order 8 bits of the
address and pull the PGM pin to “L.” When this is done, the
contents of input address is read and stored into the internal
data latch.
tCH
When the PGM pin is released back to “H” and serial clock is
input to the SCLK pin, the low-order 8 bits and high-order 8
bits of read data which have been stored into the data latch,
are serially output from the SDA pin.
tCH
tCH
SCLK
A0
SDA
A7
1 0 1 0 1 0 0 0
Command code
input (1516)
Read address
input (L)
D0
A8 A9
0 0 0 0 0 0
Read address
input (H)
D8
D7
0 0 0 0 0 0 0
tCR
tWR
tRC
Read data output
(L)
Read data output
(H)
PGM
Read
Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit).
Fig. 28 Timing at reading
MITSUBISHI
ELECTRIC
41
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(4) Program
Input command code 25 16 in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
tCH
tCH
and pull the PGM pin to “L.” When this is done, the program
data is programmed to the specified address.
tCH
tCH
SCLK
A0
SDA
Program address
input (L)
Command code
input (2516)
D0
A8 A9
0 0 0 0 0 0
A7
1 0 1 0 0 1 0 0
D8
D7
0 0 0 0 0 0 0
Program address
input (H)
Program data
input (L)
Program data
input (H)
tCP
tWP
PGM
Program
Fig. 29 Timing at programming
(5) Program verify
Input command code 35 16 in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
and pull the PGM pin to “L.” When this is done, the program
data is programmed to the specified address. Then, when the
PGM pin is pulled to “L” again after it is released back to “H,”
the address programmed with the program command is read
tCH
and verified and stored into the internal data latch. When the
PGM pin is released back to “H” and serial clock is input to the
SCLK pin, the verify data that has been stored into the data
latch is serially output from the SDA pin.
tCH
tCH
tCH
SCLK
A0
SDA
A8 A9
0 0 0 0 0 0
A7
1 0 1 0 1 1 0 0
Program address
input (L)
Command code
input (3516)
D0
Program address
input (H)
D7
D8
0 0 0 0 0 0 0
Program data
input (L)
Program data
input (H)
tCP
tWP
PGM
Program
tCH
SCLK
D0
D7
D8
SDA
0 0 0 0 0 0 0
tCR
tWR
tRC
Verify data output (L) Verify data output (H)
PGM
Verify
Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit).
Fig. 30 Timing at program verifying
42
MITSUBISHI
ELECTRIC
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
PROGRAM ALGORITHM FLOW CHART
START
VDD = 4V,VPP = 4V
VDD = 4V,VPP = 12.5V
ADRS = first location
X=0
WRITE PROGRAM-VERIFY
COMMAND
3516
WRITE PROGRAM
DATA
DIN
PROGRAM ONE PULSE
OF 0.2ms
X=X+1
X = 25?
YES
NO
FAIL
VERIFY
BYTE?
PASS
PASS
WRITE PROGRAM
COMMAND
2516
WRITE PROGRAM
DATA
DIN
VERIFY
BYTE?
FAIL
PROGRAM PULSE OF
0.2Xms DURATION
INC ADRS
NO
LAST
ADRS?
YES
READ COMMAND
VERIFY
ALL BYTE?
FAIL
1516
DEVICE
FAILED
PASS
DEVICE
PASSED
MITSUBISHI
ELECTRIC
43
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS
(Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V)
Symbol
tCH
tCR
Limits
Min. Max.
Parameter
Serial transfer width time
2.0
2.0
Read wait time after transfer
Read pulse width
500
tCP
Transfer wait time after read
Program wait time after transfer
2.0
2.0
tWP
Program pulse width
tOWP
Added program pulse width
SCLK input cycle time
0.19
0.19
tWR
tRC
tC(CK)
tW(CKH)
tW(CKL)
tr(CK)
tf(CK)
td(C–Q)
th(C–Q)
th(C–E)
tsu(D–C)
th(C–D)
0.21
5.25
1.0
SCLK “H” pulse width
SCLK “L” pulse width
450
450
SCLK rising time
40
40
SCLK falling time
SDA output delay time
180
0
SDA output hold time
SDA output hold time (only for 16th bit)
0
100
SDA input set-up time
60
180
SDA input hold time
Unit
µs
µs
ns
µs
µs
ms
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAM
tC(CK)
tf(CK)
tW(CKL)
tW(CKH)
tr(CK)
SCLK
td(C-Q)
th(C-E)
th(C-Q)
SDA output
tsu(D-C)
th(C-D)
SDA input
Measurement condition
Output timing voltage: VOL = 0.8 V, VOH = 2.0 V
Input timing voltage: VIL = 0.2 VDD, VIH = 0.8 VDD
44
MITSUBISHI
ELECTRIC
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
(6) Notes on handling
➀ A high-voltage is used for writing. Take care that overvoltage
is not applied. Take care especially at turning on the power.
➁ For the M34280E1FP/GP, Mitsubishi Electric corp. does
not perform PROM writing test and screening in the
assembly process and following processes. In order to
improve reliability after writing, performing writing and test
according to the flow shown in Figure 31 before using is
recommended.
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 31 Flow of writing and test of the product shipped in
blank
MITSUBISHI
ELECTRIC
45
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
GZZ-SH54-86B <91A0>
Mask ROM number
720 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34280M1-XXXFP/GP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
Company
name
TEL (
)
Date:
Issuance
signature
Responsible
Supervisor
officer
✽ Customer
Date
issued
Section head S u p e r v i s o r
signature
signature
✽ 1. Confirmation
Specify the name of the product being ordered (check in the approximate box).
Three sets of EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by floppy disk.
Microcomputer name:
M34280M1-XXXFP
M34280M1-XXXGP
Ordering by the EPROMs
Specify the type of EPROMs submitted (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C128
27C64
27C256
27C512
Low-order
8-bit data
0000 16
1.00K
03FF 16
Low-order
8-bit data
0000 16
1.00K
03FF 16
Low-order
8-bit data
000016
1.00K
03FF16
Low-order
8-bit data
000016
1.00K
03FF16
Most significant
bit data
1000 16
1.00K
13FF 16
Most significant
bit data
1000 16
1.00K
13FF 16
Most significant
bit data
100016
1.00K
13FF16
Most significant
bit data
100016
1.00K
13FF16
1FFF 16
7FFF16
3FFF 16
Set “FF 16” in the shaded area.
46
MITSUBISHI
ELECTRIC
FFFF16
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
GZZ-SH54-86B <91A0>
Mask ROM number
720 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34280M1-XXXFP/GP
MITSUBISHI ELECTRIC
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted
floppy disk.
The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the
mask files must be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
₎
2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (20P2N-A for M34280M1-XXXFP, 20P2E/F-A for
M34280M1-XXXGP) and attach to the Mask ROM Order Confirmation Form.
₎
3. Comments
MITSUBISHI
ELECTRIC
47
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
PACKAGE OUTLINE
20P2N-A
Plastic 20pin 300mil SOP
EIAJ Package Code
SOP20-P-300-1.27
Weight(g)
0.26
JEDEC Code
–
e
b2
11
E
HE
e1
I2
20
Lead Material
Cu Alloy
Recommended Mount Pad
Symbol
1
F
10
A
D
G
A2
b
e
x
A1
M
L
L1
y
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
c
z
Detail F
Detail G
Z1
b2
e1
I2
20P2E/F-A
Dimension in Millimeters
Min
Nom
Max
2.1
–
–
0.2
0.1
0
–
1.8
–
0.5
0.4
0.35
0.25
0.2
0.18
12.7
12.6
12.5
5.4
5.3
5.2
–
1.27
–
8.1
7.8
7.5
0.8
0.6
0.4
–
1.25
–
–
0.585
–
–
–
0.735
–
–
0.25
0.1
–
–
0°
–
8°
–
0.76
–
–
7.62
–
–
1.27
–
Plastic 20pin 225mil SSOP
EIAJ Package Code
SSOP20-P-225-0.65
Weight(g)
0.08
JEDEC Code
–
e
b2
11
E
HE
e1
I2
20
Lead Material
Alloy 42/Cu Alloy
F
Recommended Mount Pad
Symbol
1
10
A
D
G
b
e
x
A2
M
A1
L
L1
y
c
z
Z1
48
Detail G
Detail F
MITSUBISHI
ELECTRIC
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
1.45
–
–
0.2
0.1
0
–
1.15
–
0.32
0.22
0.17
0.2
0.15
0.13
6.6
6.5
6.4
4.5
4.4
4.3
–
0.65
–
6.6
6.4
6.2
0.7
0.5
0.3
–
1.0
–
–
0.325
–
–
–
0.475
–
–
0.13
0.1
–
–
0°
–
10°
–
0.35
–
–
5.8
–
–
1.0
–
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
20P2N-A (20-PIN SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
20
11
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
1
Mitsubishi IC catalog name
10
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
20
11
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name and Mitsubishi lot number
Mask ROM number (3-digit)
Mitsubishi lot number (6-digit or 7-digit)
1
10
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi
type.
3 : Customer’s Parts Number can be up to 13 characters: Only
0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are
usable.
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
C. Special Mark Required
20
11
Mask ROM number (3-digit)
Mitsubishi lot number (6-digit or 7-digit)
1
Note 1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be duplicated as close as possible.
Mitsubishi lot number (6-digit, or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
Special logo required
10
Special Mark (Customer’s Trade Mark)
Mitsubishi IC catalog name
MITSUBISHI
ELECTRIC
49
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
20P2E/F-A (20-PIN SSOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
20
11
Mitsubishi IC catalog name
Mitsubishi lot number
(4-digit or 5-digit)
1
Mitsubishi IC catalog name
10
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
20
11
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name and Mitsubishi lot number
ROM number
(3-digit)
Mitsubishi lot number
(4-digit or 5-digit)
1
50
10
Mitsubishi IC catalog name and Mitsubishi lot number
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi
type.
3 : Customer’s Parts Number can be up to 4 characters: Only 0
to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are
usable.
MITSUBISHI
ELECTRIC
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1999 MITSUBISHI ELECTRIC CORP.
Effective June. 1999.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
4280 GROUP DATA SHEET
Revision Description
Rev.
date
1.0
First Edition
980420
2.0
• 20P2E/F-A package added
990611
• Figure XA-2: A resistor is added
(1/1)