MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER DESCRIPTION The 4513/4514 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D converter. The various microcomputers in the 4513/4514 Group include variations of the built-in memory type and package as shown in the table below. FEATURES ●Minimum instruction execution time ................................ 0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0 V to 5.5 V) ●Supply voltage • Middle-speed mode ...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) • High-speed mode ...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) Product M34513M2-XXXSP/FP * M34513M4-XXXSP/FP * M34513E4SP/FP * (Note) M34513M6-XXXFP ** M34513M8-XXXFP ** M34513E8FP ** (Note) M34514M6-XXXFP * M34514M8-XXXFP * M34514E8FP * (Note) Note: shipped in blank * : Under development **: Under planning ROM (PROM) size (✕ 10 bits) 2048 words 4096 words 4096 words 6144 words 8192 words 8192 words 6144 words 8192 words 8192 words ●Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 4 ...................................... 8-bit timer with a reload register ●Interrupt ........................................................................ 8 sources ●Serial I/O ....................................................................... 8 bit-wide ●A-D converter .................. 10-bit successive comparison method ●Voltage comparator ........................................................ 2 circuits ●Watchdog timer ................................................................. 16 bits ●Voltage drop detection circuit ●Clock generating circuit (ceramic resonator) ●LED drive directly enabled (port D) APPLICATION Microwave oven, rice cooker, audio, telephone, office equipment RAM size (✕ 4 bits) 128 words 256 words 256 words 384 words 384 words 384 words 384 words 384 words 384 words Package ROM type SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A 32P6B-A 32P6B-A 32P6B-A 42P2R-A 42P2R-A 42P2R-A Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) 4513 Group 1 32 P13 D1 2 31 P12 D2 3 30 P11 D3 4 29 P10 D4 5 28 P03 D5 6 27 P02 D6/CNTR0 7 26 P01 D7/CNTR1 8 25 P00 P20/SCK 9 24 AIN3/CMP1+ 23 AIN2/CMP1- 22 AIN1/CMP0+ 21 AIN0/CMP0- 20 P31/INT1 10 P22/SIN 11 M34513E4SP P21/SOUT M34513Mx-XXXSP D0 RESET 12 CNVSS 13 XOUT 14 19 P30/INT0 XIN 15 18 VDCE VSS 16 17 VDD 25 P03 27 P11 26 P10 28 P12 30 D0 29 P13 32 D2 31 D1 Outline 32P4B D3 1 24 P02 D4 D5 3 23 P01 2 D6/CNTR0 4 M34513Mx-XXXFP D7/CNTR1 5 P20/SCK 6 M34513ExFP P21/SOUT P22/SIN 8 7 21 AIN3/CMP1+ 20 AIN2/CMP119 AIN1/CMP0+ 18 AIN0/CMP0- P30/INT0 16 VDD 14 VDCE 15 VSS 13 11 XIN 12 XOUT RESET 9 CNVSS 10 17 P31/INT1 Outline 32P6B-A 2 22 P00 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) 4514 Group 42 P12 D0 2 41 P11 D1 3 40 P10 D2 4 39 P03 D3 5 38 P02 D4 6 D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK 14 P21/SOUT 15 P22/SIN 16 M34514E8FP D5 7 M34514Mx-XXXFP P13 1 RESET 17 CNVSS 18 XOUT 37 P01 36 P00 35 P43/AIN7 34 P42/AIN6 33 P41/AIN5 32 P40/AIN4 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP027 P33 26 P32 25 P31/INT1 24 P30/INT0 19 XIN 20 23 VDCE 22 VDD VSS 21 Outline 42P2R-A 3 4 Port P0 | [ Port g o P1 1 4 Serial I/O (8 bits ✕ 1) A-D converter (10 bits ✕ 4 ch) Watchdog timer (16 bits) Timer 4 (8 bits) Timer 3 (8 bits) Timer 2 (8 bits) Timer 1 (8 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU (4 bits) 4500 Series CPU core Voltage comparator (2 circuits) Port P2 3 Port D 8 . 128, 256, 384 words × 4 bits RAM words × 10 bits 2048, 4096,6144, 8192 ROM Memory Voltage drop detection circuit XIN–XOUT System clock generating circuit Port P3 2 ion cat o cifi t spe bject l a su fin ot a its are n lim s is Thi etric m ice: Not e para Somnge. cha Timer Internal peripheral functions I/O port 4 RY A N IMI L E PR MITSUBISHI MICROCOMPUTERS 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BLOCK DIAGRAM (4513 Group) Port P0 Port P1 4 Port P2 3 4 Port P4 Port D 8 Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU (4 bits) 384 words × 4 bits RAM 6144, 8192 words × 10 bits ROM . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha Serial I/O (8 bits ✕ 1) A-D converter (10 bits ✕ 8 ch) Memory Watchdog timer (16 bits) XIN—XOUT System clock generating circuit Port P5 4 Voltage drop detection circuit 4500 Series CPU core Voltage comparator (2 circuits) Port P3 4 Timer 4 (8 bits) Timer 3 (8 bits) Timer 2 (8 bits) Timer 1 (8 bits) Timer Internal peripheral functions I/O port 4 RY A N IMI L E PR MITSUBISHI MICROCOMPUTERS 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BLOCK DIAGRAM (4514 Group) 5 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PERFORMANCE OVERVIEW Parameter 4513 Group Number of 4514 Group basic instructions Minimum instruction execution time M34513M2 Memory sizes ROM M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 RAM M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 I/O (Input is Input/Output D0–D7 examined by ports skip decision) P00–P03 I/O P10–P13 I/O P20–P22 Input P30–P33 I/O Timers P40–P43 P50–P53 CNTR0 CNTR1 INT0 INT1 Timer 1 Timer 2 Timer 3 Timer 4 I/O I/O I/O I/O Input Input A-D converter Voltage comparator Serial I/O Sources Interrupt Nesting Subroutine nesting Device structure 4513 Group Package 4514 Group Operating temperature range Supply voltage Active mode Power dissipation (typical value) RAM back-up mode 6 Function 123 128 0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode) 2048 words ✕ 10 bits 4096 words ✕ 10 bits 6144 words ✕ 10 bits 8192 words ✕ 10 bits 6144 words ✕ 10 bits 8192 words ✕ 10 bits 128 words ✕ 4 bits 256 words ✕ 4 bits 384 words ✕ 4 bits 384 words ✕ 4 bits 384 words ✕ 4 bits 384 words ✕ 4 bits Eight independent I/O ports; ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. 4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port; The 4513 Group does not have this port. 4-bit I/O port with a direction register; The 4513 Group does not have this port. 1-bit I/O; CNTR0 pin is also used as port D6. 1-bit I/O; CNTR1 pin is also used as port D7. 1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function. 1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 10-bit wide, This is equipped with an 8-bit comparator function. 2 circuits (CMP0, CMP1) 8-bit ✕ 1 8 (two for external, four for timer, one for A-D, and one for serial I/O) 1 level 8 levels CMOS silicon gate 32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A) 42-pin plastic molded SSOP (42P2R-A) –20 °C to 85 °C 2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the electrical characteristics because the supply voltage depends on the oscillation frequency.) 1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transistors in the cut-off state) 3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state) MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin VDD VSS VDCE CNVSS RESET Name Power supply Ground Voltage drop detection circuit enable Input/Output — — Input Function Connected to a plus power supply. Connected to a 0 V power supply. VDCE pin is used to control the operation/stop of the voltage drop detection circuit. When “H” level is input to this pin, the circuit is operating. When “L” level is inpu to this pin, the circuit is stopped. CNVSS — Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly. Reset input I/O An N-channel open-drain I/O pin for a system reset. When the watchdog timer causes the system to be reset or system reset is performed by the voltage drop detection circuit, the RESET pin outputs “L” level. I/O pins of the system clock generating circuit. XIN and XOUT can be connected to ceramic resonator. A feedback resistor is built-in between them. XIN XOUT D0–D7 System clock input System clock output I/O port D (Input is examined by skip decision.) P00–P03 I/O port P0 I/O P10–P13 I/O port P1 I/O P20–P22 Input port P2 P30–P33 Input Output I/O Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Input 3-bit input port. Ports P20, P21 and P22 are also used as SCK, S OUT and SIN, respectively. I/O port P3 I/O 4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. P40–P43 I/O port P4 I/O 4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports P40–P43 are also used as analog input pins AIN4–AIN7, respectively. The 4513 Group does not have port P4. P50–P53 I/O port P5 I/O AIN0–AIN7 Analog input 4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O function. For input use, set the direction register to “0.” For output use, set the direction regiser to “1.” The output structure is CMOS. The 4513 Group does not have port P5. Analog input pins for A-D converter. AIN0–AIN3 are also used as comparator input pins and AIN4–AIN7 are also used as port P4. The 4513 Group does not have AIN4–AIN7. CNTR0 Timer input/output I/O CNTR0 pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 underflow signal divided by 2. CNTR0 pin is also used as port D6. CNTR1 Timer input/output I/O CNTR1 pin has the function to input the clock for the timer 4 event counter, and to output the timer 3 underflow signal divided by 2. CNTR1 pin is also used as port D7. INT0, INT1 Interrupt input Input INT0, INT1 pins accept external interrupts. They also accept the input signal to return the system from the RAM back-up state. INT0, INT1 pins are also used as ports P30 and P31, respectively. SIN Serial data input Input SIN pin is used to input serial data signals by software. SIN pin is also used as port P22. SOUT Serial data output SCK Serial I/O clock input/output CMP0CMP0+ Voltage comparator input Input CMP0-, CMP0+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software. CMP0-, CMP0+ pins are also used as AIN0 and AIN1. CMP1CMP1+ Voltage comparator input Input CMP1-, CMP1+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software. CMP1-, CMP1+ pins are also used as AIN2 and AIN3. Input Output I/O SOUT pin is used to output serial data signals by software. SOUT pin is also used as port P21. SCK pin is used to input and output synchronous clock signals for serial data transfer by software. SCK pin is also used as port P20. 7 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MULTIFUNCTION Pin D6 D7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Pin CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Multifunction D6 D7 P20 P21 P22 P30 P31 Pin AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Multifunction CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Pin CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Multifunction AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Notes 1: Pins except above have just single function. 2: The input of D6, D7, P20–P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40–P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, and AIN0–AIN7 are selected. 3: The 4513 Group does not have P40/AIN4–P43/AIN7. CONNECTIONS OF UNUSED PINS Pin XOUT 8 Connection Open (when using an external clock). Notes 1: After system is released from reset, port P5 is in a input mode (direction register FR0 = 00002) 2: When the P00 –P03 and P1 0–P1 3 are connected to VSS, turn off their pull-up transistors (register PU0i=“0”) and also invalidate the key-on wakeup functions (register K0i=“0”) by software. When these pins are connected to V SS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i=“1”) by software, or set the output latch to “0.” Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.) VDCE D0–D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4–P43/AIN7 Connect to VSS. P50–P53 (Note 1) When the input mode is selected by software, pull-up to VDD through a resistor or pull-down to VDD. When selecting the output mode, open. AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P00–P03 P10–P13 Connect to VSS. (Note when the output latch is set to “0” and pins are open) ● After system is released from reset, port is in a high-impedance state until it is set the output latch to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state. ● To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise). Open or connect to VSS (Note 2) (Note when connecting to VSS and VDD) ● Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Connect to VSS, or set the output latch to “0” and open. Connect to VSS. Connect to VSS, or set the output latch to “0” and open. Connect to VSS, or set the output latch to “0” and open. Open or connect to VSS (Note 2) MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT FUNCTION Port Port D Pin Port P0 D0–D5 D6/CNTR0 D7/CNTR1 P00–P03 Port P1 Port P2 Port P3 (Note 1) Port P4 (Note 2) Port P5 (Note 2) Input Output I/O (8) Output structure N-channel open-drain I/O unit 1 Control instructions SD, RD SZD CLD OP0A IAP0 Control registers Remark W6 I/O (4) N-channel open-drain 4 PU0, K0 P10–P13 I/O (4) N-channel open-drain 4 OP1A IAP1 PU0, K0 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 Input (3) 3 IAP2 J1 I/O (4) N-channel open-drain 4 OP3A IAP3 I1, I2 P40/AIN4 –P43/AIN7 P50–P53 I/O (4) I/O (4) N-channel open-drain 4 Q2 CMOS 4 OP4A IAP4 OP5A IAP5 Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in key-on wakeup function (P30/INT0, P31/INT1) FR0 Notes 1: The 4513 Group does not have P32 and P33. 2: The 4513 Group does not have these ports. DEFINITION OF CLOCK AND CYCLE ● System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control register MR. Table Selection of system clock Register MR MR3 0 1 System clock f(XIN) f(XIN)/2 Note: f(XIN)/2 is selected after system is released from reset. ● Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. ● Machine cycle The machine cycle is the standard cycle required to execute the instruction. 9 Y NAR MI ELI MITSUBISHI MICROCOMPUTERS 4513/4514 Group . n atio cific to spe bject l a su fin ot a its are is n his tric lim T : me ice Not e para Som ge. n cha PR SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS K00 Pull-up transistor Key-on wakeup input PU00 IAP0 instruction Register A P00,P01 Ai D Q OP0A instruction T K01 Pull-up transistor Key-on wakeup input PU01 IAP0 instruction Register A P02,P03 Ai D Q OP0A instruction T K02 Pull-up transistor Key-on wakeup input PU02 IAP1 instruction P10,P11 Register A Ai D Q OP1A instruction T K03 Pull-up transistor Key-on wakeup input PU03 IAP1 instruction Register A Ai P12,P13 D Q OP1A instruction T • •i 10 This symbol represents a parasitic diode on the port. represents 0, 1, 2, or 3. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS (continued) IAP2 instruction Register A Synchronous clock input for serial transfer J11 P20/SCK 0 Synchronous clock output for serial transfer 1 J10 IAP2 instruction Register A J11 P21/SOUT 0 Serial data output 1 Serial data input IAP2 instruction Register A P22/SIN Key-on wakeup input External interrupt circuit IAP3 instruction Register A P30/INT0,P31/INT1 Ai D OP3A instruction Q T IAP3 instruction Register A Ai OP3A instruction P32,P33 D Q T This symbol represents a parasitic diode on the port. • • Applied potential to ports P20—P22 must be VDD. • i represents 0, 1, 2, or 3. • The 4513 Group does not have ports P32, P33. 11 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS (continued) Q1 Decoder Analog input Q30 CMP0 AIN0/CMP0- + Q32 Q1 Decoder AIN1/CMP0+ Analog input Q1 Decoder Analog input Q31 CMP1 AIN2/CMP1- + Q33 Q1 Decoder AIN3/CMP1+ Analog input IAP4 instruction P40/AIN4–P43/AIN7 Register A Ai OP4A instruction D Q T Q1 Decoder Analog input This symbol represents a parasitic diode on the port. • • i represents 0, 1, 2, or 3. • The 4513 Group does not have port P4. 12 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS (continued) Direction register FR0i Ai D OP5A instruction T P50–P53 Q Register A IAP5 instruction Register Y Decoder Skip decision (SZD instruction) D0–D5 SD instruction S RD instruction R Q Skip decision (SZD instruction) Clock input for timer 2 event count Register Y Decoder SD instruction S RD instruction R Q W60 0 1/2 Timer 1 underflow signal output D6/CNTR0 1 Skip decision (SZD instruction) Clock input for timer 4 event count Register Y Decoder SD instruction RD instruction Timer 3 underflow signal output S R Q 1/2 W62 0 D7/CNTR1 1 This symbol represents a parasitic diode on the port. • • Applied potential to ports D0–D7 must be 12 V. • i represents 0, 1, 2, or 3. • The 4513 Group does not have port P5. 13 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER I12 Falling One-sided edge detection circuit 0 I1 1 0 P30/INT0 1 EXF0 External 0 interrupt EXF1 External 1 interrupt 1 Both edges detection circuit Rising Wakeup Skip SNZI0 I22 Falling 0 One-sided edge detection circuit I21 0 P31/INT1 1 1 Rising Both edges detection circuit Wakeup Skip SNZI1 External interrupt circuit structure 14 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER FUNCTION BLOCK OPERATIONS CPU <Carry> (CY) (1) Arithmetic logic unit (ALU) (M(DP)) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. Addition ALU (A) <Result> (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. Fig. 1 AMC instruction execution example <Set> SC instruction <Clear> RC instruction CY A3 A2 A1 A0 (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). <Rotation> RAR instruction A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example (4) Register D Register B Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). B3 B2 B1 B0 TAB instruction Register A A3 A 2 A1 A0 TEAB instruction Register E E 7 E6 E5 E4 E3 E2 E 1 E0 TABE instruction A3 A2 A1 A0 B3 B2 B1 B0 TBA instruction Register B Register A Fig. 3 Registers A, B and register E TABP p instruction ROM Specifying address p6 p5 PCH p4 p3 p2 p 1 p0 PCL DR2 DR1DR0 A3 A2 A1 A0 8 4 0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) Immediate field value p The contents of The contents of register D register A Fig. 4 TABP p instruction execution example 15 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Program counter (PC) Executing BM instruction Executing RT instruction SK0 (SP) = 0 SK1 (SP) = 1 SK2 (SP) = 2 SK3 (SP) = 3 SK4 (SP) = 4 SK5 SK6 (SP) = 5 (SP) = 6 SK7 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Subroutine Main program Address SUB1 : 000016 NOP NOP · · · RT 000116 BM SUB1 000216 NOP (PC) ← (SK0) (SP) ← 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call 16 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. Program counter p6 p5 p 4 p 3 p2 p 1 p0 a6 a5 a4 a3 a 2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). Specifying RAM digit Register Y (4) Register X (4) Register Z (2) Specifying RAM file Specifying RAM file group Fig. 8 Data pointer (DP) structure Specifying bit position Set D7 0 1 0 D6 1 Register Y (4) D5 D4 D0 1 Port D output latch Fig. 9 SD instruction execution example 17 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34514M8/E8. Table 1 ROM size and pages Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 ROM size (✕ 10 bits) 2048 words 4096 words 6144 words 8192 words 6144 words 8192 words 9 8 000016 007F16 008016 00FF16 010016 017F16 018016 7 6 5 4 3 2 1 0 Page 0 Interrupt address page Page 1 Subroutine special page Page 2 Page 3 Pages 16 (0 to 15) 32 (0 to 31) 48 (0 to 47) 64 (0 to 63) 48 (0 to 47) 64 (0 to 63) A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. 0FFF16 Page 31 1FFF16 Page 63 Fig. 10 ROM map of M34514M8/E8 008016 9 8 7 6 5 4 3 02 1 External 0 interrupt address 008216 External 1 interrupt address 008416 Timer 1 interrupt address 008616 Timer 2 interrupt address 008816 Timer 3 interrupt address 008A16 Timer 4 interrupt address 008C16 A-D interrupt address 008E16 Serial I/O interrupt address 00FF16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure 18 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER DATA MEMORY (RAM) Table 2 RAM size 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 128 words 256 words 384 words 384 words 384 words 384 words RAM size ✕ 4 bits (512 bits) ✕ 4 bits (1024 bits) ✕ 4 bits (1536 bits) ✕ 4 bits (1536 bits) ✕ 4 bits (1536 bits) ✕ 4 bits (1536 bits) RAM 384 words ✕ 4 bits (1536 bits) Register Z 0 1 15 0 1 2 3 4 5 6 7 Register Y Register X 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M34513M6 M34513M8/E8 15 M34514M6 Z=0, X=0 to 15 M34514M8/E8 Z=1, X=0 to 7 384 words 256 words M34513M4/E4 Z=0, X=0 to 15 M34513M2 Z=0, X=0 to 7 128 words Fig. 12 RAM map 19 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt Activated condition 2 External 1 interrupt 3 Timer 1 interrupt Level change of INT0 pin Level change of INT1 pin Timer 1 underflow 4 Timer 2 interrupt Timer 2 underflow 5 Timer 3 interrupt Timer 3 underflow 6 Timer 4 interrupt Timer 4 underflow 7 A-D interrupt 8 Serial I/O interrupt Completion of A-D conversion Completion of serial I/O transfer Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1 (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. 20 Table 4 Interrupt request flag, interrupt enable bit and skip instruction Request flag EXF0 EXF1 External 1 interrupt T1F Timer 1 interrupt T2F Timer 2 interrupt T3F Timer 3 interrupt T4F Timer 4 interrupt ADF A-D interrupt SIOF Serial I/O interrupt Interrupt name External 0 interrupt Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Enable bit V10 V11 V12 V13 V20 V21 V22 V23 Table 5 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.” • Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Main rouine • Stack register (SK) The address of main routine to be .................................................................................................... executed when returning • Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 • Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs INT0 pin (L→H or H→L input) • • • • EI RTI Interrupt is enabled EXF0 Address 0 in page 1 V10 INT1 pin (L→H or H→L input) Timer 1 underflow Timer 2 underflow Interrupt service routine Interrupt occurs • Program counter (PC) .............................................................. Each interrupt address Timer 3 underflow Timer 4 underflow Completion of A-D conversion Completion of serial I/O transfer Activated condition EXF1 V11 T1F V12 T2F V13 T3F V20 T4F V21 ADF V22 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 SIOF V23 INTE Request flag (state retained) Enable bit Enable flag Address E in page 1 Fig. 15 Interrupt system diagram : Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing 21 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. • Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 External 1 interrupt enable bit V10 External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register V2 V23 Serial I/O interrupt enable bit V22 A-D interrupt enable bit V21 Timer 4 interrupt enable bit V20 Timer 3 interrupt enable bit Note: “R” represents read enabled, and “W” represents write enabled. 22 R/W Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 at RAM back-up : 00002 Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/W MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V13 and V20 –V23 ), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc- curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). When an interrupt request flag is set after its interrupt is enabled (Note 1) f (XIN) (middle-speed mode) f (XIN) (high-speed mode) 1 machine cycle T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 System clock Interrupt enable flag (INTE) EI instruction execution cycle Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. INT0, INT1 External interrupt EXF0, EXF1 Timer 1, Timer 2, Timer 3, Timer 4, A-D, and Serial I/O interrupts Interrupt activated condition is satisfied. T1F, T2F, T3F, T4F, ADF,SIOF Flag cleared The program starts from the interrupt address. 2 to 3 machine cycles (Notes 2, 3) Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset. 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. Fig. 16 Interrupt sequence 23 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER EXTERNAL INTERRUPTS The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin P30/INT0 Valid waveform selection bit I11 I12 Activated condition When the next waveform is input to P30/INT0 pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms External 1 interrupt P31/INT1 I21 I22 When the next waveform is input to P31/INT1 pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms I12 Falling One-sided edge detection circuit 0 I1 1 0 P30/INT0 1 EXF0 External 0 interrupt EXF1 External 1 interrupt 1 Both edges detection circuit Rising Wakeup Skip SNZI0 I22 Falling 0 One-sided edge detection circuit I21 0 P31/INT1 1 1 Rising Both edges detection circuit Wakeup Skip SNZI1 Fig. 17 External interrupt circuit structure 24 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) External 0 interrupt request flag (EXF0) (2) External 1 interrupt request flag (EXF1) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P30/INT0 pin need not be selected the external interrupt input INT0 function or the normal I/O port P30 function. However, the EXF0 flag is set to “1” when a valid waveform is input even if it is used as an I/O port P30. External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P31/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P31/INT1 pin need not be selected the external interrupt input INT1 function or the normal I/O port P3 1 function. However, the EXF1 flag is set to “1” when a valid waveform is input even if it is used as an I/O port P31. • External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. • External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. ➀ Select the valid waveform with the bits 1 and 2 of register I1. ➁ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➂ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➃ Set both the external 0 interrupt enable bit (V10) and the INTE flag to “1.” ➀ Select the valid waveform with the bits 1 and 2 of register I2. ➁ Clear the EXF1 flag to “0” with the SNZ1 instruction. ➂ Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. ➃ Set both the external 1 interrupt enable bit (V11) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs. 25 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (3) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. • Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 8 External interrupt control registers Interrupt control register I1 I13 I12 I11 I10 Not used Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register I2 I23 Not used I22 Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) I21 I20 INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit 0 1 0 1 0 1 R/W This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 0 1 at RAM back-up : state retained at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. 26 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TIMERS The 4513/4514 Group has the programmable timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). • Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. FF16 n : Counter initial value Count starts Reload Reload The contents of counter n 1st underflow 2nd underflow 0016 Time n+1 count n+1 count “1” Timer interrupt “0” request flag An interrupt occurs or a skip instruction is executed. Fig. 18 Auto-reload function 27 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER The 4513/4514 Group timer consists of the following circuits. • Prescaler : frequency divider • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 8-bit programmable timer • Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively) • 16-bit timer Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below. Table 9 Function related timers Circuit Prescaler Timer 1 Timer 2 Structure Frequency divider 8-bit programmable • Instruction clock Frequency dividing ratio 4, 16 • Timer 1, 2, 3 and 4 count sources • Prescaler output (ORCLK) 1 to 256 Count source Use of output signal Control register W1 • Timer 2 count source W1 binary down counter • CNTR0 output W6 (link to EXF0) • Timer 1 interrupt 8-bit programmable • Timer 1 underflow binary down counter • Prescaler output (ORCLK) 1 to 256 • Timer 3 count source • Timer 2 interrupt • CNTR0 output • CNTR0 input W2 W6 • 16-bit counter underflow Timer 3 8-bit programmable binary down counter • Timer 2 underflow • Prescaler output (ORCLK) 1 to 256 (link to EXF1) Timer 4 8-bit programmable • Timer 3 underflow binary down counter • Prescaler output (ORCLK) 1 to 256 • Timer 4 count source W3 • Timer 3 interrupt W6 • CNTR1 output • Timer 4 interrupt W4 • CNTR1 output W6 • CNTR1 input 16-bit timer 16-bit fixed dividing frequency • Instruction clock 65536 • Watchdog timer (The 15th bit is counted twice) • Timer 2 count source (16-bit counter underflow) 28 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction clock Prescaler W13 Division circuit (divided by 2) MR3 1 0 XIN Internal clock generation circuit (divided by 3) W12 0 1/4 0 1 1/16 1 ORCLK W10 I12 P30/INT0 0 1 I10 SQ 1 R 0 W11 (Note) 0 Timer 1 (8) T1F Timer 1 interrupt T2F Timer 2 interrupt 1 Reload register R1 (8) T1AB (TAB1) (TR1AB) T1AB Register B Register A Timer 1 underflow signal W21,W20 W23(Note) 00 01 0 10 1 Timer 2 (8) 11 Reload register R2 (8) (T2AB) (TAB2) Register B Register A I22 P31/INT1 Timer 2 underflow signal W32 0 1 I20 SQ 1 R 0 W31,W30 00 W33(Note) 01 0 11 Timer 3 (8) 1 10 Timer 3 interrupt Reload register R3 (8) Not available T3AB (TAB3) (TR3AB) T3AB Register B Register A Timer 3 underflow signal W41,W40 W43(Note) 00 01 0 10 1 11 T3F Not available Timer 4 (8) Not available T4F Timer 4 interrupt Reload register R4 (8) (T4AB) (TAB4) W60 D6/CNTR0 0 D6 output 1 Register B Register A W61 1/2 0 1 W62 D7/CNTR1 0 D7 output 1 1/2 W63 0 1/2 1 1/2 Data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (autoreload function) Note: Count source is stopped by clearing to “0.” Instruction clock Timer 2 underflow signal Timer 4 underflow signal 16-bit timer (WDT) 1 - - - - - - - - - - - 15 16 System reset WRST instruction S Reset signal R WEF Q WDF1 WDF2 Fig. 19 Timers structure 29 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 10 Timer control registers Timer control register W1 W13 Prescaler control bit W12 Prescaler dividing ratio selection bit W11 Timer 1 control bit W10 Timer 1 count start synchronous circuit control bit Timer 2 control bit W22 Not used at reset : 00002 0 1 0 1 Timer 2 count source selection bits W20 0 0 1 1 W33 Timer 3 control bit W32 Timer 3 count start synchronous circuit control bit W31 Timer 3 count source selection bits W30 Timer 4 control bit W42 Not used W41 Timer 4 count source selection bits W40 CNTR1 output control bit W62 D7/CNTR1 function selection bit W61 CNTR0 output control bit W60 D6/CNTR0 output control bit R/W Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected W31 W30 Count source 0 Timer 2 underflow signal 0 0 Prescaler output 1 1 Not available 0 1 Not available 1 at reset : 00002 0 1 0 1 R/W This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained Stop (state retained) Operating W41 W40 0 0 0 1 1 0 1 1 Note: “R” represents read enabled, and “W” represents write enabled. 30 at RAM back-up : state retained 0 1 0 1 Timer control register W6 W63 Count source Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal at reset : 00002 Timer control register W4 W43 R/W This bit has no function, but read/write is enabled. 0 1 0 1 Timer control register W3 at RAM back-up : state retained Stop (state retained) Operating W21 W20 W21 R/W Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected 0 1 0 1 0 1 0 1 Timer control register W2 W23 at RAM back-up : 00002 at reset : 00002 at RAM back-up : state retained R/W Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input) MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) Timer control registers (3) Prescaler • Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. • Timer control register W2 Register W2 controls the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. • Timer control register W3 Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. • Timer control register W4 Register W4 controls the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. • Timer control register W6 Register W6 controls the D 6/CNTR0 pin and D 7 /CNTR1 functions, the selection and operation of the CNTR0 and CNTR1 output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A. Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to “0.” (4) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process; ➀ set data in timer 1, and ➁ set the bit 1 of register W1 to “1.” However, P30/INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction. Timer 1 underflow signal divided by 2 can be output from D6/CNTR0 pin. (2) Precautions Note the following for the use of timers. • Prescaler Stop the prescaler operation to change its frequency dividing ratio. • Count source Stop timer 1, 2, 3, or 4 counting to change its count source. • Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. • Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. (5) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 3 of register W2 to “1.” Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction. The output from D 6 /CNTR0 pin by timer 2 underflow signal divided by 2 can be controlled. 31 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Timer 3 (interrupt function) (8) Timer I/O pin (D6/CNTR0, D7/CNTR1) Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. When writing data to reload register R3 with the TR3AB instruction, the downcount after the underflow is started from the setting value of reload register R3. Timer 3 starts counting after the following process; ➀ set data in timer 3, ➁ select the count source with the bits 0 and 1 of register W3, and ➂ set the bit 3 of register W3 to “1.” However, P31/INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 2 of register W3 to “1.” Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function). When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 3 with the TAB3 instruction. When reading the data, stop the counter and then execute the TAB3 instruction. Timer 3 underflow signal divided by 2 can be output from D7/CNTR1 pin. D6/CNTR0 pin has functions to input the timer 2 count source, and to output the timer 1 and timer 2 underflow signals divided by 2. D7/CNTR1 pin has functions to input the timer 4 count source, and to output the timer 3 and timer 4 underflow signals divided by 2. The selection of D6/CNTR0 pin function can be controlled with the bit 0 of register W6. The selection of D7/CNTR1 pin function can be controlled with the bit 2 of register W6. The following signals can be selected for the CNTR0 output signal with the bit 1 of register W6. • timer 1 underflow signal divided by 2 • the signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divide by 2 The following signals can be selected for the CNTR1 output signal with the bit 3 of register W6. • timer 3 underflow signal divided by 2 • the signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divide by 2 Timer 2 counts the rising waveform of CNTR0 input when the CNTR0 input is selected as the count source. Timer 4 counts the rising waveform of CNTR1 input when the CNTR1 input is selected as the count source. (7) Timer 4 (interrupt function) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, and SNZT4). Use the interrupt control registers V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. Timer 4 is an 8-bit binary down counter with the timer 4 reload register (R4). Data can be set simultaneously in timer 4 and the reload register (R4) with the T4AB instruction. Timer 4 starts counting after the following process; ➀ set data in timer 4, ➁ select the count source with the bits 0 and 1 of register W4, and ➂ set the bit 3 of register W4 to “1.” Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4, and count continues (auto-reload function). When a value set in reload register R4 is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 4 with the TAB4 instruction. When reading the data, stop the counter and then execute the TAB4 instruction. The output from D 7 /CNTR1 pin by timer 4 underflow signal divided by 2 can be controlled. 32 (9) Timer interrupt request flags (T1F, T2F, T3F, and T4F) (10) Count start synchronization circuit (timer 1, timer 3) Each timer 1 and timer 3 has the count start synchronization circuit which synchronize P30/INT0 pin and P31/INT1 pin, respectively, and can start the timer count operation. Timer 1 count start synchronization circuit function is selected by setting the bit 0 of register W1 to “1.” The control by P30/INT0 pin input can be performed by setting the bit 0 of register I1 to “1.” P30/INT0 pin input level can be selected by the bit 2 of register I1 as follows; • I12 = “0”: The count start synchronizes the “L” level of P30/INT0 pin • I12 = “1”: The count start synchronizes the “H” level of P30/INT0 pin Timer 3 count start synchronization circuit function is selected by setting the bit 2 of register W3 to “1.” The control by P31/INT1 pin input can be performed by setting the bit 0 of register I2 to “1.” P31/INT1 pin input level can be selected by the bit 2 of register I2 as follows; • I22 = “0”: The count start synchronizes the “L” level of P31/INT1 pin • I22 = “1”: The count start synchronizes the “H” level of P31/INT1 pin When timer 1 and timer 3 count start synchronization circuits are used, the count start synchronization circuits are set, the count source is input to each timer by inputting valid levels to P30/INT0 pin and P31/INT1 pin. Once set, the count start synchronization circuit is cleared by clearing the bit I10 or I20 to “0” or reset. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source. The underflow signal is generated when the count value reaches “000016.” This underflow signal can be used as the timer 2 count source. When the WRST instruction is executed after system is released from reset, the WEF flag is set to “1”. At this time, the watchdog timer starts operating. When the count value of timer WDT reaches “BFFF16” or “3FFF16,” the WDF1 flag is set to “1.” If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. To prevent the WDT stopping in the event of misoperation, WEF flag is designed not to initialize once the WRST instruction has been executed. Note also that, if the WRST instruction is never executed, the watchdog timer does not start. FFFF16 BFFF16 3FFF16 The value of timer (WDT) 0000 16 WEF flag WDF1 flag WDF2 flag RESET pin output WRST instruction executed WRST instruction executed System reset Fig. 20 Watchdog timer function The contents of WEF, WDF1 and WDF2 flags and timer WDT are initialized at the RAM back-up mode. If WDF2 flag is set to “1” at the same time that the microcomputer enters the RAM back-up state, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 21) •• ••• • WRST EPOF ; WDF1 flag reset ; POF instruction enabled POF Oscillation stop (RAM back-up state) Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer 33 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SERIAL I/O Table 11 Serial I/O pins The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; • serial I/O register SI • serial I/O mode register J1 • serial I/O transmission/reception completion flag (SIOF) • serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1. Division circuit (divided by 2) Pin P20/SCK P21/SOUT P22/SIN Note: Input ports P2 0–P22 can be used regardless of register J1. MR3 Internal clock generation circuit (divided by 3) 1 XIN 0 Instruction clock J12 1/4 1/8 P20/SCK P21/SOUT P22/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN) Serial I/O mode register J1 1 J13 J12 J11 J10 0 Synchronous circuit SCK Serial I/O counter (3) SIOF Serial I/O interrupt SOUT SIN MSB Serial I/O register SI (8) TSIAB J11 J10 Register B (4) LSB TABSI Register A (4) Note: The output structure of SCK and SOUT pins is N-channel open-drain. Fig. 22 Serial I/O structure Table 12 Serial I/O mode register Serial I/O mode register J1 J13 Not used J12 Serial I/O internal clock dividing ratio selection bit J11 Serial I/O port selection bit J10 Serial I/O synchronous clock selection bit at reset : 00002 0 1 0 1 0 1 0 1 Note: “R” represents read enabled, and “W” represents write enabled. 34 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8) MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER When transmitting (D7–D0 : transfer data) Serial I/O register (SI) When receiving SIN pin SOUT pin SOUT pin SIN pin D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ∗ D7 D6 D5 D4 D3 D2 D1 ∗ ∗ Transfer data to be set Transfer started D7 D6 D5 D4 D3 D2 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Serial I/O register (SI) ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ D0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ D1 D0 Transfer completed ∗ ∗ ∗ ∗ ∗ ∗ D7 D6 D5 D4 D3 D2 D1 D0 Fig. 23 Serial I/O register state when transferring (1) Serial I/O register SI (3) Serial I/O start instruction (SST) Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, pull up the SCK pin or set the pin function to an input port P20. When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial I/O transmission/reception is started. (4) Serial I/O mode register J1 Register J1 controls the synchronous clock, P2 0/S CK, P21 /SOUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. (2) Serial I/O transmission/reception completion flag (SIOF) Serial I/O transmission/reception completion flag (SIOF) is set to “1” when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. 35 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (5) How to use serial I/O Figure 24 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the Slave (external clock) Master (clock control) D5 ✕ ✕ (Bit 3) 0 ✕ 1 ✕ 1 SRDY signal D5 SCK SCK SOUT SIN SIN SOUT (Bit 0) (Bit 3) wiring between each pin with a resistor. Figure 25 shows the data transfer timing and Table 13 shows the data transfer sequence. Serial I/O mode register J1 (Bit 3) ✕ ✕ 1 (Bit 0) 0 Serial I/O mode register J1 Internal clock selected as a synchronous clock External clock selected as a synchronous clock Serial I/O port SCK,SOUT,SIN Serial I/O port SCK,SOUT,SIN Instruction clock divided by 8 or 4 selected as a transfer clock This bit is not valid when J1 0=“0” (Bit 0) Interrupt control register V2 ✕ Serial I/O interrupt enable bit (SNZSI instruction is valid) (Bit 3) 0 ✕ ✕ (Bit 0) ✕ Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction is valid) ✕ : Set an arbitrary value. Fig. 24 Serial I/O connection example 36 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Master SOUT M7’ SIN S7’ S0 M3 M2 M1 M0 S1 S2 M4 S3 M5 S4 M6 S5 M7 S6 S7 SST instruction SCK Slave SST instruction SRDY signal SOUT SIN S1 S0 S7’ M7’ M0 S2 M1 S3 M2 S4 M3 S5 M4 S6 M5 S7 M6 M7 M0–M7 : the contents of master serial I/O S0–S7 : the contents of slave serial I/O register Rising of SCK : serial input Falling of SCK : serial output Fig. 25 Timing of serial I/O data transfer 37 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 13 Processing sequence of data transfer from master to slave • Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 24. Slave (reception) [Initial setting] • Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions • Setting the port received the reception enable signal (SRDY) to the input mode. TJ1A and TV2A instructions • Setting the port received the reception enable signal (SRDY) and outputting “H” level (reception impossible). Master (transmission) [Initial setting] (Port D5 is used in this example) SD instruction * [Transmission enable state] • Storing transmission data to serial I/O register SI. TSIAB instruction [Transmission] (Port D5 is used in this example) SD instruction *[Reception enable state] • The SIOF flag is cleared to “0.” SST instruction • “L” level (reception possible) is output from port D5. RD instruction [Reception] •Check port D5 is “L” level. SZD instruction •Serial transfer starts. SST instruction •Check transmission completes. • Check reception completes. SNZSI instruction •Wait (timing when continuously transferring) SNZSI instruction • “H” level is output from port D5. SD instruction [Data processing] 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to “1” when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to “H.” 38 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER A-D CONVERTER Table 14 A-D converter characteristics Characteristics Parameter Successive comparison method Conversion format The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. Table 14 shows the characteristics of this A-D converter. This AD converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values. Resolution Absolute accuracy 10 bits Linearity error: ±2LSB Non-linearity error: ±0.9LSB Conversion speed Analog input pin 46.5 µs (High-speed mode at 4.0 MHz oscillation frequency) 4 for 4513 Group 8 for 4514 Group Register B (4) Register A (4) 4 TAQ2 TQ2A IAP4 (P40—P43) TAQ1 TQ1A Q23 Q22 Q21 Q20 4 4 Q13 Q12 Q11 Q10 4 2 8 TALA TABAD 8 TADAB Instruction clock OP4A (P40—P43) 1/6 3 Q23 AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P40/AIN8 P41/AIN9 P42/AIN10 P43/AIN11 8-channel multi-plexed analog switch 0 (Note 3) AIN0/CMP0- ADF (1) A-D control circuit 1 A-D interrupt 1 Successive comparison register (AD) (10) Comparator 0 Q23 Q23 DAC operation signal 0 8 10 10 0 1 1 1 Q23 8 8 DA converter (Note 1) 8 VDD VSS Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1). The value of the comparator register is retained even when the mode is switched to the A-D conversion mode (Q23=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. 3: The 4513 Group does not have ports P40/AIN4–P43/AIN7 and the IAP4 and OP4A instructions. Fig. 26 A-D conversion circuit structure 39 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 15 A-D control registers A-D control register Q1 Q13 Not used Q12 Q11 Analog input pin selection bits (Note 2) Q10 at reset : 00002 0 1 Q12Q11 Q10 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A-D control register Q2 Q23 A-D operation mode selection bit Q22 P43/AIN7 and P42/AIN6 pin function selection bit (Not used for the 4513 Group) Q21 P41/AIN5 pin function selection bit (Not used for the 4513 Group) Q20 P40/AIN4 pin function selection bit (Not used for the 4513 Group) at RAM back-up : state retained This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at reset : 00002 0 1 0 1 0 1 0 1 R/W at RAM back-up : state retained R/W A-D conversion mode Comparator mode (read/write enabled for the 4513 Group) P43, P42 AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 (read/write enabled for the 4513 Group) P40 (read/write enabled for the 4513 Group) AIN4/P40 (read/write enabled for the 4513 Group) Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Select AIN4–AIN7 with register Q1 after setting register Q2. (1) Operating at A-D conversion mode (4) A-D conversion start instruction (ADST) The A-D conversion mode is set by setting the bit 3 of register Q2 to “0.” A-D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (2) Successive comparison register AD Register AD stores the A-D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute this instruction during AD conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref = V DD ✕n 1024 n: The value of register AD (n = 0 to 1023) (3) A-D conversion completion flag (ADF) A-D conversion completion flag (ADF) is set to “1” when A-D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. 40 (5) A-D control register Q1 Register Q1 is used to select one of analog input pins. The 4513 Group does not have AIN4–AIN7. Accordingly, do not select these pins with register Q1. (6) A-D control register Q2 Register Q2 is used to select the pin function of P40 /A IN4, P41/ AIN5 , P4 2/A IN6, and P4 3 /A IN7. The A-D conversion mode is selected when the bit 3 of register Q2 is “0,” and the comparator mode is selected when the bit 3 of register Q2 is “1.” After set this register, select the analog input with register Q1. Even when register Q2 is used to set the pins for analog input, P40/AIN4–P43 /AIN7 continue to function as P40–P4 3 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, for the port input, the port input function of the pin functions as analog input is undefined. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (7) Operation description A-D conversion is started with the A-D conversion start instruction (ADST). The internal operation during A-D conversion is as follows: ➀ When A-D conversion starts, the register AD is cleared to “00016.” ➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage Vref is compared with the analog input voltage VIN. ➂ When the comparison result is V ref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4513/4514 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A-D conversion stops after 62 machine cycles (46.5 µs when f(XIN) = 4.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A-D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A-D conversion completes (Figure 27). Table 16 Change of successive comparison register AD during A-D conversion At starting conversion ------------- 1st comparison 2nd comparison 3rd comparison After 10th comparison completes ✼1: 1st comparison result ✼3: 3rd comparison result ✼9: 9th comparison result Comparison voltage (Vref) value Change of successive comparison register AD 1 ✼1 ✼1 0 1 ✼2 0 0 ----- 0 0 0 ------------- 2 ------------- VDD ----- ------------- 0 0 0 2 ------------- 1 ----- ------------- 0 0 0 VDD ------------- ✼2 ✼3 ----- ------------- VDD 2 A-D conversion result ✼1 VDD ✼8 ✼9 ✼A 2 VDD ± 4 VDD ± ± ± 4 ○ ○ ○ ○ ± VDD 8 VDD 1024 ✼2: 2nd comparison result ✼8: 8th comparison result ✼A: Ath comparison result 41 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (8) A-D conversion timing chart Figure 27 shows the A-D conversion timing chart. ADST instruction 62 machine cycles A-D conversion completion flag (ADF) DAC operation signal Fig. 27 A-D conversion timing chart (9) How to use A-D conversion How to use A-D conversion is explained using as example in which the analog input from P40/AIN4 pin is A-D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A-D interrupt is not used in this example. ➀ After selecting the AIN4 pin function with the bit 0 of the register Q2, select AIN4 pin and A-D conversion mode with the register Q1 (refer to Figure 28). ➁ Execute the ADST instruction and start A-D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A-D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). (Bit 3) (Bit 0) ✕ 0 ✕ 1 A IN4 function selected A-D conversion mode (Bit 3) ✕ (Bit 0) 1 0 0 A-D control register Q1 A IN4 pin selected ✕ : Set an arbitrary value Fig. 28 Setting registers 42 A-D control register Q2 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (10) Operation at comparator mode (12) Comparison result store flag (ADF) The A-D converter is set to comparator mode by setting bit 3 of the register Q2 to “1.” Below, the operation at comparator mode is described. In comparator mode, the ADF flag, which shows completion of A-D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (11) Comparator register In comparator mode, the built-in DA comparator is connected to the comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A-D conversion mode to comparator mode, the result of A-D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A-D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage V ref Vref = VDD 256 ✕n n: The value of register AD (n = 0 to 255) (13) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (6 µs at f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” (14) Notes for the use of A-D conversion 1 Note the following when using the analog input pins also for I/O port P4 functions: • Even when P40/AIN4–P43/AIN7 are set to pins for analog input, they continue to function as P40–P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined. • TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal → Comparator operation completed. (The value of ADF is determined) Fig. 29 Comparator operation timing chart 43 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (15) Notes for the use of A-D conversion 2 (16) Definition of A-D converter accuracy Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with bit 3 of register Q2 while A-D converter is operating. When the operating mode of A-D converter is changed from the comparator mode to A-D conversion mode with the bit 3 of register Q2, note the following; • Clear bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the comparator mode to A-D conversion mode with the bit 3 of register Q2. • The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. The A-D conversion accuracy is defined below (refer to Figure 30). • Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A-D conversion output data changes from “0” to “1.” ➁ Full-scale transition voltage (VFST) This means an analog input voltage when the actual A-D conversion output data changes from “1023” to ”1022.” ➂ Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. ➃ Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. • Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A-D conversion characteristics. Output data Full-scale transition voltage (VFST) 1023 1022 Differential non-linearity error = b–a [LSB] a Linearity error = c [LSB] a b a n+1 n Actual A-D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1–Vn c: Difference between ideal Vn and actual Vn Ideal line of A-D conversion between V0–V1022 1 0 V0 V1 Vn Vn+1 Zero transition voltage (V0T) Fig. 30 Definition of A-D conversion accuracy Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022) • 1LSB at relative accuracy → VFST–V0T (V) 1022 • 1LSB at absolute accuracy → 44 VDD 1024 (V) V1022 VDD Analog voltage MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER VOLTAGE COMPARATOR The 4513/4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins. Table 17 shows the characteristics of this voltage comparison. Table 17 Voltage comparator characteristics Characteristics Parameter Voltage comparator function 2 circuits (CMP0, CMP1) Input pin CMP0-, CMP0+ (also used as AIN0, AIN1) CMP1-, CMP1+ Supply voltage Input voltage Comparison check error Response time CMP0–/AIN0 CMP0+/AIN1 CMP1–/AIN2 CMP1+/AIN3 (also used as AIN2, AIN3) 3.0 V to 5.5 V 0.3 VDD to 0.7 VDD Typ. 20 mV, Max.100 mV Max. 20 µs – CMP0 + – CMP1 + Q33 Q32 Q31 Q30 Voltage comparator control register Q3 (4) TQ3A TAQ3 Register A (4) Note: Bits 0 and 1 of register Q3 can be only read. Fig. 31 Voltage comparator structure 45 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 18 Voltage comparator control register Q3 Voltage comparator control register Q3 (Note 2) Q33 Voltage comparator (CMP1) control bit Q32 Voltage comparator (CMP0) control bit Q31 CMP1 comparison result store bit Q30 CMP0 comparison result store bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W Voltage comparator (CMP1) invalid Voltage comparator (CMP1) valid Voltage comparator (CMP0) invalid Voltage comparator (CMP0) valid CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+ Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Bits 0 and 1 of register Q3 can be only read. (1) Voltage comparator control register Q3 (3) Precautions Register Q3 controls the function of the voltage comparator. The function of the voltage comparator CMP0 becomes valid by setting bit 2 of register Q3 to “1,” and becomes invalid by setting bit 2 of register Q3 to ”0.” The comparison result of the voltage comparator CMP0 is stored into bit 0 of register Q3. The function of the voltage comparator CMP1 becomes valid by setting bit 3 of register Q3 to “1,” and becomes invalid by setting bit 3 of register Q3 to ”0.” The comparison result of the voltage comparator CMP1 is stored into bit 1 of register Q3. When the voltage comparator is used, note the following; • Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator by software when it is unused. (2) Operation description of voltage comparator The voltage comparator function becomes valid by setting each control bit of register Q3 to “1” and compares the voltage of the input pin. The comparison result is stored into each comparison result store bit of register Q3. The comparison result is as follows; • When CMP0- > CMP0+, Q30 = “0” When CMP0- < CMP0+, Q30 = “1” • When CMP1- > CMP1+, Q31 = “0” When CMP1- < CMP1+, Q31 = “1” 46 • Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. • Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 µ s) is passed from the voltage comparator function becomes valid. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. f(XIN) (Note) f(XIN) is counted 16892 to RESET Software starts (address 0 in page 0) 16895 times. Note: It depends on the internal state of the microcomputer when reset is performed. Fig. 32 Reset release timing = Reset input 1 machine cycle or more f(XIN) is counted 16892 to 16895 times. 0.85VDD Software starts (address 0 in page 0) RESET 0.3VDD (Note) Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 33 RESET pin input waveform and reset operation 47 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) Power-on reset Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance. VDD VDD RESET pin voltage Internal reset signal RESET pin (Note) Reset state Voltage drop detection circuit Watchdog timer output Internal reset signal WEF Reset released Power-on Note: This symbol represents a parasitic diode. Applied potential to RESET pin must be VDD or less. Fig. 34 Power-on reset circuit example (2) Internal state at reset Table 19 shows port state at reset, and Figure 35 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 35 are undefined, so set the initial value to them. Table 19 Port state at reset Name State Function D0–D5 D0–D5 D6/CNTR0, D7/CNTR1 D 6, D 7 High impedance (Note) P00–P03 P00–P03 P10–P13 P10–P13 P20/SCK, P21/SOUT, P22/SIN P30/INT0, P31/INT1 P20–P22 High impedance P32, P33 (Note 4) P30, P31 P32, P33 High impedance (Note 1) P40/AIN4–P43/AIN7 (Note 4) P40–P43 High impedance (Note 1) P50–P53 (Note 4) P50–P53 High impedance (Note 3) High impedance (Notes 1, 2) Notes 1: Output latch is set to “1.” 2: Pull-up transistor is turned OFF. 3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 00002) 4: The 4513 Group does not have these ports. 48 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER • Program counter (PC) .......................................................................................................... 0 0 0 0 0 0 Address 0 in page 0 is set to program counter. 0 0 0 0 0 • Interrupt enable flag (INTE) .................................................................................................. 0 • Power down flag (P) ............................................................................................................. 0 (Interrupt disabled) 0 0 0 • External 0 interrupt request flag (EXF0) .............................................................................. 0 • External 1 interrupt request flag (EXF1) .............................................................................. 0 • Interrupt control register V1 .................................................................................................. 0 0 0 0 • Interrupt control register V2 .................................................................................................. 0 0 0 0 • Interrupt control register I1 ................................................................................................... 0 0 0 0 (Interrupt disabled) (Interrupt disabled) • Interrupt control register I2 ................................................................................................... 0 0 0 0 • Timer 1 interrupt request flag (T1F) ..................................................................................... 0 • Timer 2 interrupt request flag (T2F) ..................................................................................... 0 • Timer 3 interrupt request flag (T3F) ..................................................................................... 0 • Timer 4 interrupt request flag (T4F) ..................................................................................... 0 • Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 • Watchdog timer enable flag (WEF) ...................................................................................... 0 • Timer control register W1 ..................................................................................................... 0 0 0 0 (Prescaler and timer 1 stopped) • Timer control register W2 ..................................................................................................... 0 0 0 0 (Timer 2 stopped) • Timer control register W3 ..................................................................................................... 0 0 0 0 • Timer control register W4 ..................................................................................................... 0 0 0 0 • Timer control register W6 ..................................................................................................... 0 0 0 0 (Timer 3 stopped) (Timer 4 stopped) • Clock control register MR ..................................................................................................... 1 0 0 0 • Serial I/O transmission/reception completion flag (SIOF) ................................................... 0 • Serial I/O mode register J1 .................................................................................................. 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ • Serial I/O register SI ............................................................................................................. • A-D conversion completion flag (ADF) ................................................................................. 0 (External clock selected and serial I/O port not selected) • A-D control register Q1 ......................................................................................................... 0 0 0 0 • A-D control register Q2 ......................................................................................................... 0 0 0 0 • Voltage comparator control register Q3 ............................................................................... 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ • Successive comparison register AD .................................................................................... ✕ ✕ ✕ ✕ ✕ ✕ .✕ • Comparator register .......................................................................................................... ... ✕ • Key-on wakeup control register K0 ...................................................................................... 0 0 0 0 • Pull-up control register PU0 ................................................................................................. 0 0 0 0 • Direction register FR0 .......................................................................................................... 0 0 0 0 (Port P5: input mode) • Carry flag (CY) ...................................................................................................................... 0 • Register A ............................................................................................................................. 0 0 0 0 • Register B ............................................................................................................................. 0 0 0 0 • Register D ............................................................................................................................. ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ • Register E ............................................................................................................................. • Register X ............................................................................................................................. 0 0 0 0 • Register Y ............................................................................................................................. 0 0 0 0 • Register Z ............................................................................................................................. ✕ ✕ • Stack pointer (SP) ................................................................................................................ 1 1 1 “✕” represents undefined. Fig. 35 Internal state at reset 49 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. RESET pin Internal reset signal Voltage drop detection circuit Watchdog timer output WEF Note: The output structure of RESET pin is N-channel open-drain. Fig. 36 Voltage drop detection reset circuit VDD VRST (detection voltage) Voltage drop detection circuit output The microcomputer starts operation after f(XIN) is counted 16892 to 16895 times. RESET pin Notes 1: Pull-up RESET pin externally. 2: Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST (detection voltage). Fig. 37 Voltage drop detection circuit operation waveform 50 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha RAM BACK-UP MODE SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 20 Functions and states retained at RAM back-up The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 20 shows the function and states retained at RAM back-up. Figure 38 shows the state transition. Function Program counter (PC), registers A, B, (1) Identification of the start condition Timer 1 function ✕ Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. Timer 2 function (Note 3) Timer 3 function Timer 4 function (Note 3) carry flag (CY), stack pointer (SP) (Note 2) RAM back-up ✕ Contents of RAM O Port level O Timer control register W1 ✕ Timer control registers W2 to W4, W6 Clock control register MR O Interrupt control registers V1, V2 ✕ ✕ Interrupt control registers I1, I2 O A-D conversion function (Note 3) ✕ (2) Warm start condition A-D control registers Q1, Q2 O When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” Voltage comparator function O (Note 5) (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when; • reset pulse is input to RESET pin, or • reset by watchdog timer is performed, or • voltage drop detection circuit detects the voltage drop. In this case, the P flag is “0.” Voltage comparator control register Q3 Serial I/O function Serial I/O mode register J1 O ✕ Pull-up control register PU0 O O Key-on wakeup control register K0 O Direction register FR0 O External 0 interrupt request flag (EXF0) ✕ External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) ✕ Timer 2 interrupt request flag (T2F) ✕ (Note 3) Timer 3 interrupt request flag (T3F) (Note 3) Timer 4 interrupt request flag (T4F) (Note 3) Watchdog timer flags (WDF1, WDF2) ✕ (Note 4) Watchdog timer enable flag (WEF) 16-bit timer (WDT) ✕ (Note 4) A-D conversion completion flag (ADF) ✕ (Note 4) ✕ Serial I/O transmission/reception completion flag (SIOF) ✕ Interrupt enable flag (INTE) ✕ Notes 1:“O” represents that the function can be retained, and “✕” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The state is retained when the voltage comparator function is selected with the voltage comparator control register Q3. 51 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 21 shows the return condition for each return source. (5) Ports P0 and P1 control registers • Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. • Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. External wakeup signal Table 21 Return source and return condition Return condition Return source Return by an external falling Ports P0, P1 edge input (“H”→“L”). 52 Remarks Set the port using the key-on wakeup function selected with register K0 to “H” level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Port P30/INT0 Return by an external “H” level or “L” level input. The EXF0 flag is not set. Select the return level (“L” level or “H” level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state. Port P31/INT1 Return by an external “H” level or “L” level input. The EXF1 flag is not set. Select the return level (“L” level or “H” level) with the bit 2 of register I2 according to the external state before going into the RAM back-up state. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER A (Stabilizing time a ) Reset B POF instruction is executed f(XIN) stop f(XIN) oscillation Return input (Stabilizing time a ) (RAM back-up mode) Stabilizing time a : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware. Fig. 38 State transition Power down flag P POF instruction Reset input or voltage drop detection circuit output S Q Software start R P = “1” ? No ● Set source • • • • • • • POF instruction is executed ● Clear source • • • • • • Reset input Cold start Fig. 39 Set source and clear source of the P flag Yes Warm start Fig. 40 Start condition identified example using the SNZP instruction 53 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register at reset : 00002 Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup 0 1 Key-on wakeup not used control bit Pins P10 and P11 key-on wakeup 0 control bit 1 Key-on wakeup not used Key-on wakeup used Pins P02 and P03 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used Pins P00 and P01 key-on wakeup 0 1 Key-on wakeup not used control bit Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and P13 pull-up transistor I12 I11 I10 0 1 Pull-up transistor OFF Pins P10 and P11 pull-up transistor 0 Pull-up transistor OFF control bit 1 Pull-up transistor ON Pins P02 and P03 pull-up transistor 0 control bit 1 Pull-up transistor OFF Pull-up transistor ON Pins P00 and P01 pull-up transistor 0 1 Not used Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit 0 1 0 1 0 1 0 1 I22 I21 I20 Not used Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit 0 1 0 1 0 1 R/W at RAM back-up : state retained R/W Pull-up transistor OFF Pull-up transistor ON This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 0 1 at RAM back-up : state retained Pull-up transistor ON at reset : 00002 Interrupt control register I2 I23 Key-on wakeup used control bit control bit R/W Key-on wakeup used at reset : 00002 Interrupt control register I1 I13 at RAM back-up : state retained at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. 54 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CLOCK CONTROL • Control circuit to switch the middle-speed mode and high-speed mode • Control circuit to return from the RAM back-up state The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation Division circuit (divided by 2) XIN XOUT Oscillation circuit System clock MR3 Internal clock generation circuit (divided by 3) 1 0 Instruction clock Counter Wait time (Note) control circuit POF instruction R S Software start signal RESET Key-on wake up control register K00,K01,K02,K03 Ports P00, P01 MultiPorts P02, P03 Falling detected Ports P10, P11 plexer Ports P12, P13 I12 Q “L” level 0 P30/INT0 1 “H” level I22 “L” level 0 P31/INT1 1 “H” level Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation. Fig. 41 Clock control circuit structure Table 23 Clock control register MR Clock control register MR MR3 System clock selection bit MR2 Not used MR1 Not used MR0 Not used at reset : 10002 0 1 0 1 0 1 0 1 at RAM back-up : 10002 R/W f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Note : “R” represents read enabled, and “W” represents write enabled. 55 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. When an external clock signal is input, connect the clock source to XIN and leave XOUT open. When using an external clock, the maximum value of external clock oscillating frequency is shown in Table 24. 4513/4514 Note: Externally connect a damping resistor Rd depending on the oscillation XOUT frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer’s recommended value because constants COUT such as capacitance depend on the resonator. XIN CIN Fig. 42 Ceramic resonator external circuit 4513/4514 XIN XOUT VDD VSS External oscillation circuit Fig. 43 External clock input circuit Table 24 Maximum value of external clock oscillation frequency Middle-speed mode Mask ROM version High-speed mode Middle-speed mode One Time PROM version High-speed mode ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form ..................................... 1 (2) Data to be written into mask ROM ............................... EPROM (three sets containing the identical data) (3) Mark Specification Form .......................................................... 1 56 Supply voltage VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V Oscillation frequency (duty ratio) 3.0 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 1.0 MHz (40 % to 60 %) 0.8 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 1.0 MHz (40 % to 60 %) MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha LIST OF PRECAUTIONS ➀Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance, • equalize its wiring in width and length, and • use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ in series at the shortest distance. ➁Prescaler Stop the prescaler operation to change its frequency dividing ratio. ➂Timer count source Stop timer 1, 2, 3, or 4 counting to change its count source. ➃Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ➆P31/INT1 pin When the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. • Clear the bit 1 of register V1 to “0” before the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 (refer to Figure 45➂). • Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I2 and execute the SNZ1 instruction to clear the EXF1 flag after executing at least one instruction (refer to Figure 45➃). ... LA 8 TV1A LA 8 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ...........➂ ; Change of the interrupt valid waveform ........................................................... ➃ ; The SNZ1 instruction is executed ... ✕ : this bit is not related to the setting of INT1. ➄Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. ➅P30/INT0 pin When the interrupt valid waveform of the P3 0 /INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Clear the bit 0 of register V1 to “0” before the interrupt valid waveform of P30/INT0 pin is changed with the bit 2 of register I1 (refer to Figure 44➀). • Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 44➁) Fig. 45 External 1 interrupt program example ➇One Time PROM version The operating power voltage of the One Time PROM version is 2.5 V to 5.5 V. ➈Multifunction The input of D6, D7, P20–P22, I/O of P30 and P31, input of CMP0-, CMP0+, CMP1-, CMP1+, and I/O of P40–P43 can be used even when CNTR0, CNTR1, S CK, S OUT, S IN , INT0, INT1, A IN0–AIN3 and AIN4–AIN7 are selected. ... LA 4 TV1A LA 4 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ...........➀ ; ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed ... ✕ : this bit is not related to the setting of INT0 pin. Fig. 44 External 0 interrupt program example 57 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha ➉ A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. • Clear the bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46➄). • The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with the bit 3 of register Q2 during operating the A-D converter. SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Sensor AIN Apply the voltage withiin the specifications to an analog input pin. Fig. 47 Analog input external circuit example-1 ... LA 8 TV2A LA 0 TQ2A ; (✕0✕✕2) ; The SNZAD instruction is valid ........ ➄ ; (0✕✕✕2) ; Change of the operating mode of the A-D converter from the comparator mode to the A-D conversion mode SNZAD NOP ... About 1kΩ Sensor Fig. 48 Analog input external circuit example-2 ✕: this bit is not related to the change of the operating mode of the A-D conversion. 12 Fig. 46 A-D converter operating mode program example 11 A-D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 47). When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48. In addition, test the application products sufficiently. 58 AIN POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction. Analog input pins Note the following when using the analog input pins also for I/O port P4 functions: • Even when P40/AIN4–P43/AIN7 are set to pins for analog input, they continue to function as P40–P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined. • TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” 13 14 Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. 15 Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 16 Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator when it is unused by software. 17 Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. 18 Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 µ s) is passed from the voltage comparator function become valid. 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 59 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SYMBOL The symbols shown below are used in the following instruction function table and instruction list. Contents Symbol Symbol T1F Contents Timer 1 interrupt request flag T2F Timer 2 interrupt request flag Timer 3 interrupt request flag Register E (8 bits) T3F T4F Q1 A-D control register Q1 (4 bits) WDF1 Timer 4 interrupt request flag Watchdog timer flag Q2 A-D control register Q2 (4 bits) WEF Watchdog timer enable flag Q3 Voltage comparator control register Q3 (4 bits) INTE Interrupt enable flag AD Successive comparison register AD (10 bits) Serial I/O mode register J1 (4 bits) EXF0 External 0 interrupt request flag External 1 interrupt request flag Serial I/O register SI (8 bits) EXF1 P V1 Interrupt control register V1 (4 bits) ADF Power down flag A-D conversion completion flag V2 Interrupt control register V2 (4 bits) SIOF Serial I/O transmission/reception completion flag I1 Interrupt control register I1 (4 bits) I2 Interrupt control register I2 (4 bits) Timer control register W1 (4 bits) D Port D (8 bits) Port P0 (4 bits) Timer control register W2 (4 bits) P0 P1 W3 Timer control register W3 (4 bits) P2 Port P1 (4 bits) Port P2 (3 bits) W4 Timer control register W4 (4 bits) P3 Port P3 (4 bits) W6 Timer control register W6 (4 bits) P4 Port P4 (4 bits) MR Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) P5 Port P5 (4 bits) A Register A (4 bits) B Register B (4 bits) Register D (3 bits) DR E J1 SI W1 W2 K0 PU0 Pull-up control register PU0 (4 bits) x FR0 Direction register FR0 (4 bits) y Hexadecimal variable Hexadecimal variable X Register X (4 bits) z Hexadecimal variable Y p Hexadecimal variable Z Register Y (4 bits) Register Z (2 bits) n Hexadecimal constant DP Data pointer (10 bits) Hexadecimal constant (It consists of registers X, Y, and Z) i j PC Program counter (14 bits) A 3A 2A 1A 0 PCH High-order 7 bits of program counter PCL Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Hexadecimal constant Binary notation of hexadecimal variable A (same for others) ← Direction of data movement Data exchange between a register and memory Carry flag ↔ ? R1 Timer 1 reload register ( ) Decision of state shown before “?” Contents of registers and memories R2 Timer 2 reload register — Negate, Flag unchanged after executing instruction R3 Timer 3 reload register Timer 4 reload register M(DP) RAM address pointed by the data pointer a Label indicating address a6 a5 a4 a3 a2 a1 a0 T1 T2 Timer 1 p, a Label indicating address a6 a5 a4 a3 a2 a1 a0 T3 Timer 3 C in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) T4 Timer 4 + SK SP CY Stack pointer (3 bits) R4 Timer 2 x Note : The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. 60 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION TAY (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) XAMI j (E3–E0) ← (A) Function (A) ← → (M(DP)) j = 0 to 15 (Y) ← (Y) + 1 TMA j (M(DP)) ← (A) (X) ← (X)EXOR(j) (A) ← n TABP p (SP) ← (SP) + 1 Function (Mj(DP)) ← 1 j = 0 to 3 RB j (Mj(DP)) ← 0 j = 0 to 3 SZB j j = 0 to 15 LA n (B) ← (E7–E4) (A) ← (E3–E0) SB j (X) ← (X)EXOR(j) n = 0 to 15 TABE GroupMnemonic ing Bit operation (B) ← (A) TEAB (Mj(DP)) = 0 ? j = 0 to 3 SEAM (A) = (M(DP)) ? SEA n (A) = n ? n = 0 to 15 Ba (PCL) ← a6–a0 (SK(SP)) ← (PC) TDA (DR2–DR0) ← (A2–A0) (PCH) ← p (PCL) ← (DR2–DR0, TAD TAZ (A2–A0) ← (DR2–DR0) A3–A0) (A3) ← 0 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (A1, A0) ← (Z1, Z0) (PC) ← (SK(SP)) (A3, A2) ← 0 (SP) ← (SP) – 1 Branch operation Register to register transfer (A) ← (B) TBA TYA GroupMnemonic ing Comparison operation TAB Function RAM to register transfer GroupMnemonic ing BL p, a (PCH) ← p (PCL) ← a6–a0 BLA p (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) TAX (A) ← (X) AM (A) ← (A) + (M(DP)) TASP (A2–A0) ← (SP2–SP0) AMC (A) ← (A) + (M(DP)) + (SK(SP)) ← (PC) (CY) (PCH) ← 2 (CY) ← Carry (PCL) ← a6–a0 LXY x, y (X) ← x, x = 0 to 15 LZ z (Z) ← z, z = 0 to 3 INY (Y) ← (Y) + 1 DEY (Y) ← (Y) – 1 TAM j RAM to register transfer (A) ← (A) + n n = 0 to 15 AND (A) ← (A) AND (M(DP)) OR (A) ← (A) OR (M(DP)) SC (CY) ← 1 (SK(SP)) ← (PC) (PCH) ← p RC (CY) ← 0 A3–A0) SZC (CY) = 0 ? CMA (A) ← (A) BML p, a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6–a0 BMLA p (A) ← (M(DP)) (X) ← (X)EXOR(j) (SP) ← (SP) + 1 An (SP) ← (SP) + 1 (PCL) ← (DR2–DR0, j = 0 to 15 XAM j (A) ← → (M(DP)) (X) ← (X)EXOR(j) RAR (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 j = 0 to 15 XAMD j RTI → CY → A3A2A1A0 Return operation RAM addresses (Y) ← y, y = 0 to 15 Arithmetic operation (A3) ← 0 Subroutine operation BM a RT (PC) ← (SK(SP)) (SP) ← (SP) – 1 RTS (PC) ← (SK(SP)) (SP) ← (SP) – 1 61 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (continued) GroupMnemonic ing DI Function GroupMnemonic ing (INTE) ← 0 TAW4 Function GroupMnemonic ing (A) ← (W4) SNZT1 Function (T1F) = 1 ? After skipping (INTE) ← 1 TW4A (W4) ← (A) SNZ0 (EXF0) = 1 ? TAW6 (A) ← (W6) After skipping (EXF0) ← 0 TW6A (W6) ← (A) (EXF1) = 1 ? TAB1 (B) ← (T17–T14) SNZ1 (A) ← (T13–T10) After skipping (EXF1) ← 0 Interrupt operation SNZI1 SNZT2 (T2F) = 1 ? After skipping (T2F) ← 0 SNZT3 (T3F) = 1 ? After skipping (T3F) ← 0 I12 = 1 : (INT0) = “H” ? (R17–R14) ← (B) (T17–T14) ← (B) I12 = 0 : (INT0) = “L” ? (R13–R10) ← (A) After skipping (T13–T10) ← (A) (T4F) ← 0 T1AB SNZI0 (T1F) ← 0 Timer operation EI SNZT4 (T4F) = 1 ? I22 = 1 : (INT1) = “H” ? I22 = 0 : (INT1) = “L” ? TAB2 (B) ← (T27–T24) IAP0 (A) ← (P0) OP0A (P0) ← (A) IAP1 (A) ← (P1) (T23–T20) ← (A) OP1A (P1) ← (A) (B) ← (T37–T34) IAP2 (A2–A0) ← (P22–P20) (A) ← (T23–T20) TAV1 (A) ← (V1) T2AB TV1A (V1) ← (A) (R27–R24) ← (B) (T27–T24) ← (B) (A) ← (V2) TV2A (V2) ← (A) TAB3 (A) ← (T33–T30) TAI1 (A) ← (I1) TI1A (I1) ← (A) (T37–T34) ← (B) (R33–R30) ← (A) TAI2 (A) ← (I2) (T33–T30) ← (A) TI2A (I2) ← (A) TAW1 (A) ← (W1) TW1A (W1) ← (A) TAW2 (A) ← (W2) TW2A (W2) ← (A) TAW3 (A) ← (W3) TW3A (W3) ← (A) T3AB TAB4 (R37–R34) ← (B) (B) ← (T47–T44) (A) ← (T43–T40) T4AB (R47–R44) ← (B) IAP3 (A) ← (P3) OP3A (P3) ← (A) IAP4* (A) ← (P4) OP4A* (P4) ← (A) IAP5* (A) ← (P5) OP5A* (P5) ← (A) CLD (D) ← 1 RD (D(Y)) ← 0 (T47–T44) ← (B) (R43–R40) ← (A) Timer operation (A3) ← 0 Input/Output operation TAV2 Timer operation (R23–R20) ← (A) (T43–T40) ← (A) TR1AB (R17–R14) ← (B) (R13–R10) ← (A) (Y) = 0 to 7 TR3AB (R37–R34) ← (B) (R33–R30) ← (A) SD (D(Y)) ← 1 (Y) = 0 to 7 SZD (D(Y)) = 0 ? (Y) = 0 to 7 *: The 4513 Group does not have these instructions. 62 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (continued) Function TK0A (K0) ← (A) TAK0 (A) ← (K0) TPU0A (PU0) ← (A) TAPU0 (A) ← (PU0) TFR0A* TABSI (A) ← (SI3–SI0) Serial I/O control operation (SI3–SI0) ← (A) (SI7–SI4) ← (B) TAJ1 TABAD (A) ← (J1) Function (A) ← (AD5–AD2) (B) ← (AD9–AD6) However, in the comparator mode, (A) ← (AD3–AD0) (B) ← (AD7–AD4) TALA (A) ← (AD1, AD0, 0, 0) TADAB (AD3–AD0) ← (A) (AD7–AD4) ← (B) TAQ1 (A) ← (Q1) TQ1A (Q1) ← (A) ADST (ADF) ← 0 (FR0) ← (A) (B) ← (SI7–SI4) TSIAB Grouping Mnemonic A-D conversion operation Input/Output operation Grouping Mnemonic A-D conversion starting TJ1A (J1) ← (A) SNZAD SST After skipping (SIOF) ← 0 (ADF) ← 0 Serial I/O starting SNZSI (ADF) = 1 ? (SIOF) = 1 ? TAQ2 (A) ← (Q2) TQ2A (Q2) ← (A) NOP (PC) ← (PC) + 1 POF RAM back-up EPOF POF instruction valid SNZP (P) = 1 ? WRST (WDF1) ← 0, (WEF) ← 1 TAMR (A) ← (MR) TMRA (MR) ← (A) TAQ3 (A) ← (Q3) After skipping Other operation (SIOF) ← 0 TQ3A (Q33, Q32) ← (A3, A2) (Q3 1 ) ← (CMP1 comparison result) (Q3 0 ) ← (CMP0 comparison result) *: The 4513 Group does not have these instructions. 63 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE (for 4513 Group) D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 010000 011000 010111 011111 Hex. D3–D0 notation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10–17 18–1F 0000 0 NOP BLA SZB BMLA 0 – TASP A 0 LA 0 TABP TABP TABP TABP BML BML*** BL 0 16*** 32** 48* BL*** BM B 0001 1 – CLD SZB 1 – – TAD A 1 LA 1 TABP TABP TABP TABP BML BML*** BL 1 17*** 33** 49* BL*** BM B 0010 2 POF – SZB 2 – – TAX A 2 LA 2 TABP TABP TABP TABP BML BML*** BL 2 18*** 34** 50* BL*** BM B 0011 3 SZB 3 – – TAZ A 3 LA 3 TABP TABP TABP TABP BML BML*** BL 3 19*** 35** 51* BL*** BM B 0100 4 DI RD SZD – RT TAV1 A 4 LA 4 TABP TABP TABP TABP BML BML*** BL 4 20*** 36** 52* BL*** BM B 0101 5 EI SD SEAn – RTS TAV2 A 5 LA 5 TABP TABP TABP TABP BML BML*** BL 5 21*** 37** 53* BL*** BM B 0110 6 RC – SEAM – RTI – A 6 LA 6 TABP TABP TABP TABP BML BML*** BL 6 22*** 38** 54* BL*** BM B 0111 7 SC DEY – – – – A 7 LA 7 TABP TABP TABP TABP BML BML*** BL 7 23*** 39** 55* BL*** BM B 1000 8 – AND – SNZ0 LZ 0 – A 8 LA 8 TABP TABP TABP TABP BML BML*** BL 8 24*** 40** 56* BL*** BM B 1001 9 – OR TDA SNZ1 LZ 1 – A 9 LA 9 TABP TABP TABP TABP BML BML*** BL 9 25*** 41** 57* BL*** BM B 1010 A AM TEAB TABE SNZI0 LZ 2 – A 10 LA 10 TABP TABP TABP TABP BML BML*** BL 10 26*** 42** 58* BL*** BM B 1011 B AMC – – SNZI1 LZ 3 EPOF A 11 LA 11 TABP TABP TABP TABP BML BML*** BL 11 27*** 43** 59* BL*** BM B 1100 C TYA CMA – – RB 0 SB 0 A 12 LA 12 TABP TABP TABP TABP BML BML*** BL 12 28*** 44** 60* BL*** BM B 1101 D – RAR – – RB 1 SB 1 A 13 LA 13 TABP TABP TABP TABP BML BML*** BL 13 29*** 45** 61* BL*** BM B 1110 E TBA TAB – TV2A RB 2 SB 2 A 14 LA 14 TABP TABP TABP TABP BML BML*** BL 14 30*** 46** 62* BL*** BM B 1111 F – TAY SZC TV1A RB 3 SB 3 A 15 LA 15 TABP TABP TABP TABP BML BML*** BL 15 31*** 47** 63* BL*** BM B SNZP INY The above table shows the relationship between machine language codes and machine language instructions. D 3–D0 show the low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD 64 The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 • *, **, and *** cannot be used in the M34513M2-XXXSP/FP. • * and ** cannot be used in the M34513M4-XXXSP/FP. • * and ** cannot be used in the M34513E4FP. • * cannot be used in the M34513M6-XXXFP. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE (continued) (for 4513 Group) D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 110000 111111 Hex. D3–D0 notation 20 21 22 23 24 25 26 27 28 29 2A 2B – WRST TMA 0 TAM XAM XAMI XAMD LXY 0 0 0 0 IAP1 TAB2 SNZT2 – – TMA 1 TAM XAM XAMI XAMD LXY 1 1 1 1 2D 2E 2F 30–3F T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 – – TMA 2 TAM XAM XAMI XAMD LXY 2 2 2 2 – – TMA 3 TAM XAM XAMI XAMD LXY 3 3 3 3 0000 0 – TW3A OP0A T1AB – 0001 1 – TW4A OP1A T2AB – 0010 2 TJ1A 0011 3 – 0100 4 TQ1A – – – TAQ1 TAI2 – – – – – TMA 4 TAM XAM XAMI XAMD LXY 4 4 4 4 0101 5 TQ2A – – – TAQ2 – – – – – TMA 5 TAM XAM XAMI XAMD LXY 5 5 5 5 0110 6 TQ3A TMRA – – TAQ3 TAK0 – – – – – TMA 6 TAM XAM XAMI XAMD LXY 6 6 6 6 0111 7 – TI1A – – – TAPU0 – – SNZAD – – TMA 7 TAM XAM XAMI XAMD LXY 7 7 7 7 1000 8 – TI2A – TSIAB – – – TABSI SNZSI – – TMA 8 TAM XAM XAMI XAMD LXY 8 8 8 8 1001 9 – – – TADAB TALA – – TABAD – – – TMA 9 TAM XAM XAMI XAMD LXY 9 9 9 9 1010 A – – – – – – – – – TMA 10 TAM XAM XAMI XAMD LXY 10 10 10 10 1011 B – TK0A – – – – – – – TMA 11 TAM XAM XAMI XAMD LXY 11 11 11 11 1100 C – – – – TAW2 – – – – – – TMA 12 TAM XAM XAMI XAMD LXY 12 12 12 12 1101 D – – TPU0A – TAW3 – – – – – – TMA 13 TAM XAM XAMI XAMD LXY 13 13 13 13 1110 E TW1A – – – TAW4 – – – – SST – TMA 14 TAM XAM XAMI XAMD LXY 14 14 14 14 1111 F TW2A – – TR1AB – – – – – ADST – TMA 15 TAM XAM XAMI XAMD LXY 15 15 15 15 – – TW6A OP3A T4AB – – – TR3AB TAW1 TAW6 IAP0 TAB1 SNZT1 2C – TAI1 – IAP3 TAB4 SNZT4 The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 65 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE (for 4514 Group) D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 010000 011000 010111 011111 Hex. D3–D0 notation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10–17 18–1F 0000 0 NOP BLA SZB BMLA 0 – TASP A 0 LA 0 TABP TABP TABP TABP BML 0 16 32 48* BML BL BL BM B 0001 1 – CLD SZB 1 – – TAD A 1 LA 1 TABP TABP TABP TABP BML 1 17 33 49* BML BL BL BM B 0010 2 POF – SZB 2 – – TAX A 2 LA 2 TABP TABP TABP TABP BML 2 18 34 50* BML BL BL BM B 0011 3 SZB 3 – – TAZ A 3 LA 3 TABP TABP TABP TABP BML 3 19 35 51* BML BL BL BM B 0100 4 DI RD SZD – RT TAV1 A 4 LA 4 TABP TABP TABP TABP BML 4 20 36 52* BML BL BL BM B 0101 5 EI SD SEAn – RTS TAV2 A 5 LA 5 TABP TABP TABP TABP BML 5 21 37 53* BML BL BL BM B 0110 6 RC – SEAM – RTI – A 6 LA 6 TABP TABP TABP TABP BML 6 22 38 54* BML BL BL BM B 0111 7 SC DEY – – – – A 7 LA 7 TABP TABP TABP TABP BML 7 23 39 55* BML BL BL BM B 1000 8 – AND – SNZ0 LZ 0 – A 8 LA 8 TABP TABP TABP TABP BML 8 24 40 56* BML BL BL BM B 1001 9 – OR TDA SNZ1 LZ 1 – A 9 LA 9 TABP TABP TABP TABP BML 9 25 41 57* BML BL BL BM B 1010 A AM TEAB TABE SNZI0 LZ 2 – A 10 LA 10 TABP TABP TABP TABP BML 10 26 42 58* BML BL BL BM B 1011 B AMC – – SNZI1 LZ 3 EPOF A 11 LA 11 TABP TABP TABP TABP BML 11 27 43 59* BML BL BL BM B 1100 C TYA CMA – – RB 0 SB 0 A 12 LA 12 TABP TABP TABP TABP BML 12 28 44 60* BML BL BL BM B 1101 D – RAR – – RB 1 SB 1 A 13 LA 13 TABP TABP TABP TABP BML 13 29 45 61* BML BL BL BM B 1110 E TBA TAB – TV2A RB 2 SB 2 A 14 LA 14 TABP TABP TABP TABP BML 14 30 46 62* BML BL BL BM B 1111 F – TAY SZC TV1A RB 3 SB 3 A 15 LA 15 TABP TABP TABP TABP 15 31 47 63* BML BML BL BL BM B SNZP INY The above table shows the relationship between machine language codes and machine language instructions. D 3–D0 show the low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD 66 The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 • * cannot be used in the M34514M6-XXXFP. MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE (continued) (for 4514 Group) D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Hex. D3–D0 notation 20 21 22 23 24 25 26 27 28 2D 2E 2F 111111 29 2A 2B – WRST TMA 0 TAM XAM XAMI XAMD LXY 0 0 0 0 IAP1 TAB2 SNZT2 – – TMA 1 TAM XAM XAMI XAMD LXY 1 1 1 1 30–3F T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 – – TMA 2 TAM XAM XAMI XAMD LXY 2 2 2 2 – – TMA 3 TAM XAM XAMI XAMD LXY 3 3 3 3 0000 0 – TW3A OP0A T1AB – 0001 1 – TW4A OP1A T2AB – 0010 2 TJ1A 0011 3 – 0100 4 TQ1A – OP4A – TAQ1 TAI2 IAP4 – – – – TMA 4 TAM XAM XAMI XAMD LXY 4 4 4 4 0101 5 TQ2A – OP5A – TAQ2 IAP5 – – – – TMA 5 TAM XAM XAMI XAMD LXY 5 5 5 5 0110 6 TQ3A TMRA – – TAQ3 TAK0 – – – – – TMA 6 TAM XAM XAMI XAMD LXY 6 6 6 6 0111 7 – TI1A – – – SNZAD – – TMA 7 TAM XAM XAMI XAMD LXY 7 7 7 7 1000 8 – TI2A TFR0A TSIAB 1001 9 – – – 1010 A – – – 1011 B – TK0A – 1100 C – – – – 1101 D – – TPU0A 1110 E TW1A – 1111 F TW2A – – – TW6A OP3A T4AB – TAW6 IAP0 TAB1 SNZT1 2C 110000 – TAI1 IAP3 TAB4 SNZT4 – – TAPU0 – – – – TABSI SNZSI – – TMA 8 TAM XAM XAMI XAMD LXY 8 8 8 8 – – TABAD – – – TMA 9 TAM XAM XAMI XAMD LXY 9 9 9 9 – – – – – – TMA 10 TAM XAM XAMI XAMD LXY 10 10 10 10 – – – – – – TMA 11 TAM XAM XAMI XAMD LXY 11 11 11 11 TAW2 – – – – – – TMA 12 TAM XAM XAMI XAMD LXY 12 12 12 12 – TAW3 – – – – – – TMA 13 TAM XAM XAMI XAMD LXY 13 13 13 13 – – TAW4 – – – – SST – TMA 14 TAM XAM XAMI XAMD LXY 14 14 14 14 – TR1AB – – – – – ADST – TMA 15 TAM XAM XAMI XAMD LXY 15 15 15 15 TADAB TALA – – TR3AB TAW1 The above table shows the relationship between machine language codes and machine language instructions. D 3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 67 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS Number of words Number of cycles Instruction code TAB 0 0 0 0 0 1 1 1 1 0 0 1 E 1 1 (A) ← (B) TBA 0 0 0 0 0 0 1 1 1 0 0 0 E 1 1 (B) ← (A) TAY 0 0 0 0 0 1 1 1 1 1 0 1 F 1 1 (A) ← (Y) TYA 0 0 0 0 0 0 1 1 0 0 0 0 C 1 1 (Y) ← (A) TEAB 0 0 0 0 0 1 1 0 1 0 0 1 A 1 1 (E7–E4) ← (B) (E3–E0) ← (A) TABE 0 0 0 0 1 0 1 0 1 0 0 2 A 1 1 (B) ← (E7–E4) (A) ← (E3–E0) TDA 0 0 0 0 1 0 1 0 0 1 0 2 9 1 1 (DR2–DR0) ← (A2–A0) TAD 0 0 0 1 0 1 0 0 0 1 0 5 1 1 1 (A2–A0) ← (DR2–DR0) (A3) ← 0 TAZ 0 0 0 1 0 1 0 0 1 1 0 5 3 1 1 (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 TAX 0 0 0 1 0 1 0 0 1 0 0 5 2 1 1 (A) ← (X) TASP 0 0 0 1 0 1 0 0 0 0 0 5 0 1 1 (A2–A0) ← (SP2–SP0) (A3) ← 0 LXY x, y 1 1 x3 x2 x1 x0 y3 y2 y1 y0 3 x y 1 1 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 LZ z 0 0 0 1 0 0 1 0 z1 z0 0 4 8 +z 1 1 (Z) ← z, z = 0 to 3 INY 0 0 0 0 0 1 0 0 1 1 0 1 3 1 1 (Y) ← (Y) + 1 DEY 0 0 0 0 0 1 0 1 1 1 0 1 7 1 1 (Y) ← (Y) – 1 TAM j 1 0 1 1 0 0 j j j j 2 C j 1 1 XAM j 1 0 1 1 0 1 j j j j 2 D j 1 1 XAMD j 1 0 1 1 1 1 j j j j 2 F j 1 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 XAMI j 1 0 1 1 1 0 j j j j 2 E j 1 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 TMA j 1 0 1 0 1 1 j j j j 2 B j 1 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Parameter Mnemonic RAM to register transfer RAM addresses Register to register transfer Type of instructions 68 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecimal notation Function MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha Skip condition Carry flag CY SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER – – Transfers the contents of register B to register A. – – Transfers the contents of register A to register B. – – Transfers the contents of register Y to register A. – – Transfers the contents of register A to register Y. – – Transfers the contents of registers A and B to register E. – – Transfers the contents of register E to registers A and B. – – Transfers the contents of register A to register D. – – Transfers the contents of register D to register A. – – Transfers the contents of register Z to register A. – – Transfers the contents of register X to register A. – – Transfers the contents of stack pointer (SP) to register A. Continuous description – Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. – – Loads the value z in the immediate field to register Z. (Y) = 0 – Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. (Y) = 15 – Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. – – After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. – – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. (Y) = 15 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. (Y) = 0 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. – – After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Datailed description 69 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (continued) Arithmetic operation Bit operation Comparison operation D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 n n n n notation Number of cycles Mnemonic Type of instructions Number of words Instruction code Parameter 0 7 n 1 1 (A) ← n n = 0 to 15 Hexadecimal Function LA n 0 0 0 1 1 TABP p 0 0 1 0 p5 p4 p3 p2 p1 p0 0 8 p +p 1 3 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (Note) AM 0 0 0 0 0 0 1 0 1 0 0 0 A 1 1 (A) ← (A) + (M(DP)) AMC 0 0 0 0 0 0 1 0 1 1 0 0 B 1 1 (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry An 0 0 0 1 1 0 n n n n 0 6 n 1 1 (A) ← (A) + n n = 0 to 15 AND 0 0 0 0 0 1 1 0 0 0 0 1 8 1 1 (A) ← (A) AND (M(DP)) OR 0 0 0 0 0 1 1 0 0 1 0 1 9 1 1 (A) ← (A) OR (M(DP)) SC 0 0 0 0 0 0 0 1 1 1 0 0 7 1 1 (CY) ← 1 RC 0 0 0 0 0 0 0 1 1 0 0 0 6 1 1 (CY) ← 0 SZC 0 0 0 0 1 0 1 1 1 1 0 2 F 1 1 (CY) = 0 ? CMA 0 0 0 0 0 1 1 1 0 0 0 1 C 1 1 (A) ← (A) RAR 0 0 0 0 0 1 1 1 0 1 0 1 D 1 1 → CY → A3A2A1A0 SB j 0 0 0 1 0 1 1 1 j j 0 5 C +j 1 1 (Mj(DP)) ← 1 j = 0 to 3 RB j 0 0 0 1 0 0 1 1 j j 0 4 C +j 1 1 (Mj(DP)) ← 0 j = 0 to 3 SZB j 0 0 0 0 1 0 0 0 j j 0 2 j 1 1 (Mj(DP)) = 0 ? j = 0 to 3 SEAM 0 0 0 0 1 0 0 1 1 0 0 2 6 1 1 (A) = (M(DP)) ? SEA n 0 0 0 0 1 0 0 1 0 1 0 2 5 2 2 (A) = n ? n = 0 to 15 0 0 0 1 1 1 n n n n 0 7 n Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8. 70 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR Skip condition Carry flag CY . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Datailed description Continuous description – Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. – – Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used. – – Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. – 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Overflow = 0 – Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. – – Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. – – Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. – 1 Sets (1) to carry flag CY. – 0 Clears (0) to carry flag CY. (CY) = 0 – Skips the next instruction when the contents of carry flag CY is “0.” – – Stores the one’s complement for register A’s contents in register A. – 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). – – Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). (Mj(DP)) = 0 j = 0 to 3 – Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” (A) = (M(DP)) – Skips the next instruction when the contents of register A is equal to the contents of M(DP). (A) = n – Skips the next instruction when the contents of register A is equal to the value n in the immediate field. 71 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code Ba 0 1 1 a6 a5 a4 a3 a2 a1 a0 1 8 a +a 1 1 (PCL) ← a6–a0 BL p, a 0 0 1 1 p4 p3 p2 p1 p0 0 E p +p 2 2 (PCH) ← p (PCL) ← a6–a0 (Note) 1 0 p5 a6 a5 a4 a3 a2 a1 a0 2 p a +a 0 0 0 0 1 0 0 1 0 2 2 1 0 p5 p4 0 0 p3 p2 p1 p0 2 p p (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (Note) BM a 0 1 0 a6 a5 a4 a3 a2 a1 a0 1 a a 1 1 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 BML p, a 0 0 1 1 p4 p3 p2 p1 p0 0 C p +p 2 2 1 0 p5 a6 a5 a4 a3 a2 a1 a0 2 p a +a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6–a0 (Note) 0 0 0 1 1 0 0 3 0 2 2 1 0 p5 p4 0 0 p3 p2 p1 p0 2 p p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0,A3–A0) (Note) RTI 0 0 0 1 0 0 0 1 1 0 0 4 6 1 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 RT 0 0 0 1 0 0 0 1 0 0 0 4 4 1 2 (PC) ← (SK(SP)) (SP) ← (SP) – 1 RTS 0 0 0 1 0 0 0 1 0 1 0 4 5 1 2 (PC) ← (SK(SP)) (SP) ← (SP) – 1 DI 0 0 0 0 0 0 0 1 0 0 0 0 4 1 1 (INTE) ← 0 EI 0 0 0 0 0 0 0 1 0 1 0 0 5 1 1 (INTE) ← 1 SNZ0 0 0 0 0 1 1 1 0 0 0 0 3 8 1 1 (EXF0) = 1 ? After skipping (EXF0) ← 0 SNZ1 0 0 0 0 1 1 1 0 0 1 0 3 9 1 1 (EXF1) = 1 ? After skipping (EXF1) ← 0 Parameter Mnemonic Interrupt operation Return operation Subroutine operation Branch operation Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BLA p BMLA p 0 0 1 0 0 0 0 0 0 0 Hexadecimal notation Function Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8. 72 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha – – Branch within a page : Branches to address a in the identical page. – – Branch out of a page : Branches to address a in page p. – – Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p. – – Call the subroutine : Calls the subroutine at address (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. – – Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. – – Returns from subroutine to the routine called the subroutine. Skip at uncondition – Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. – – Clears (0) to the interrupt enable flag INTE, and disables the interrupt. – – Sets (1) to the interrupt enable flag INTE, and enables the interrupt. (EXF0) = 1 – Skips the next instruction when the contents of EXF0 flag is “1.” After skipping, clears (0) to the EXF0 flag. (EXF1) = 1 – Skips the next instruction when the contents of EXF1 flag is “1.” After skipping, clears (0) to the EXF1 flag. Datailed description 73 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (continued) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZI0 0 0 0 0 1 1 1 0 1 0 notation Number of cycles Mnemonic Type of instructions Number of words Instruction code Parameter 0 3 A 1 1 Hexadecimal Function I12 = 1 : (INT0) = “H” ? I12 = 0 : (INT0) = “L” ? SNZI1 0 0 0 0 1 1 1 0 1 1 0 3 B 1 1 I22 = 1 : (INT1) = “H” ? Timer operation Interrupt operation I22 = 0 : (INT1) = “L” ? 74 TAV1 0 0 0 1 0 1 0 1 0 0 0 5 4 1 1 (A) ← (V1) TV1A 0 0 0 0 1 1 1 1 1 1 0 3 F 1 1 (V1) ← (A) TAV2 0 0 0 1 0 1 0 1 0 1 0 5 5 1 1 (A) ← (V2) TV2A 0 0 0 0 1 1 1 1 1 0 0 3 E 1 1 (V2) ← (A) TAI1 1 0 0 1 0 1 0 0 1 1 2 5 3 1 1 (A) ← (I1) TI1A 1 0 0 0 0 1 0 1 1 1 2 1 7 1 1 (I1) ← (A) TAI2 1 0 0 1 0 1 0 1 0 0 2 5 4 1 1 (A) ← (I2) TI2A 1 0 0 0 0 1 1 0 0 0 2 1 8 1 1 (I2) ← (A) TAW1 1 0 0 1 0 0 1 0 1 1 2 4 B 1 1 (A) ← (W1) TW1A 1 0 0 0 0 0 1 1 1 0 2 0 E 1 1 (W1) ← (A) TAW2 1 0 0 1 0 0 1 1 0 0 2 4 C 1 1 (A) ← (W2) TW2A 1 0 0 0 0 0 1 1 1 1 2 0 F 1 1 (W2) ← (A) TAW3 1 0 0 1 0 0 1 1 0 1 2 4 D 1 1 (A) ← (W3) TW3A 1 0 0 0 0 1 0 0 0 0 2 1 0 1 1 (W3) ← (A) TAW4 1 0 0 1 0 0 1 1 1 0 2 4 E 1 1 (A) ← (W4) TW4A 1 0 0 0 0 1 0 0 0 1 2 1 1 1 1 (W4) ← (A) TAW6 1 0 0 1 0 1 0 0 0 0 2 5 0 1 1 (A) ← (W6) TW6A 1 0 0 0 0 1 0 0 1 1 2 1 3 1 1 (W6) ← (A) MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR Skip condition Carry flag CY . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Datailed description (INT0) = “H” However, I12 = 1 – When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.” (INT0) = “L” However, I12 = 0 – When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.” (INT1) = “H” However, I22 = 1 – When bit 2 (I22) of register I2 is “1” : Skips the next instruction when the level of INT1 pin is “H.” (INT1) = “L” However, I22 = 0 – When bit 2 (I22) of register I2 is “0” : Skips the next instruction when the level of INT1 pin is “L.” – – Transfers the contents of interrupt control register V1 to register A. – – Transfers the contents of register A to interrupt control register V1. – – Transfers the contents of interrupt control register V2 to register A. – – Transfers the contents of register A to interrupt control register V2. – – Transfers the contents of interrupt control register I1 to register A. – – Transfers the contents of register A to interrupt control register I1. – – Transfers the contents of interrupt control register I2 to register A. – – Transfers the contents of register A to interrupt control register I2. – – Transfers the contents of timer control register W1 to register A. – – Transfers the contents of register A to timer control register W1. – – Transfers the contents of timer control register W2 to register A. – – Transfers the contents of register A to timer control register W2. – – Transfers the contents of timer control register W3 to register A. – – Transfers the contents of register A to timer control register W3. – – Transfers the contents of timer control register W4 to register A. – – Transfers the contents of register A to timer control register W4. – – Transfers the contents of timer control register W6 to register A. – – Transfers the contents of register A to timer control register W6. 75 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code TAB1 1 0 0 1 1 1 0 0 0 0 2 7 0 1 1 (B) ← (T17–T14) (A) ← (T13–T10) T1AB 1 0 0 0 1 1 0 0 0 0 2 3 0 1 1 (R17–R14) ← (B) (T17–T14) ← (B) (R13–R10) ← (A) (T13–T10) ← (A) TAB2 1 0 0 1 1 1 0 0 0 1 2 7 1 1 1 (B) ← (T27–T24) (A) ← (T23–T20) T2AB 1 0 0 0 1 1 0 0 0 1 2 3 1 1 1 (R27–R24) ← (B) (T27–T24) ← (B) (R23–R20) ← (A) (T23–T20) ← (A) TAB3 1 0 0 1 1 1 0 0 1 0 2 7 2 1 1 (B) ← (T37–T34) (A) ← (T33–T30) T3AB 1 0 0 0 1 1 0 0 1 0 2 3 2 1 1 (R37–R34) ← (B) (T37–T34) ← (B) (R33–R30) ← (A) (T33–T30) ← (A) TAB4 1 0 0 1 1 1 0 0 1 1 2 7 3 1 1 (B) ← (T47–T44) (A) ← (T43–T40) T4AB 1 0 0 0 1 1 0 0 1 1 2 3 3 1 1 (R47–R44) ← (B) (T47–T44) ← (B) (R43–R40) ← (A) (T43–T40) ← (A) TR1AB 1 0 0 0 1 1 1 1 1 1 2 3 F 1 1 (R17–R14) ← (B) (R13–R10) ← (A) TR3AB 1 0 0 0 1 1 1 0 1 1 2 3 B 1 1 (R37–R34) ← (B) (R33–R30) ← (A) SNZT1 1 0 1 0 0 0 0 0 0 0 2 8 0 1 1 (T1F) = 1 ? After skipping (T1F) ← 0 SNZT2 1 0 1 0 0 0 0 0 0 1 2 8 1 1 1 (T2F) = 1 ? After skipping (T2F) ← 0 SNZT3 1 0 1 0 0 0 0 0 1 0 2 8 2 1 1 (T3F) = 1 ? After skipping (T3F) ← 0 SNZT4 1 0 1 0 0 0 0 0 1 1 2 8 3 1 1 (T4F) = 1 ? After skipping (T4F) ← 0 Parameter Mnemonic Timer operation Type of instructions 76 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecimal notation Function MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha Skip condition Carry flag CY SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER – – Transfers the contents of timer 1 to registers A and B. – – Transfers the contents of registers A and B to timer 1 and timer 1 reload register. – – Transfers the contents of timer 2 to registers A and B. – – Transfers the contents of registers A and B to timer 2 and timer 2 reload register. – – Transfers the contents of timer 3 to registers A and B. – – Transfers the contents of registers A and B to timer 3 and timer 3 reload register. – – Transfers the contents of timer 4 to registers A and B. – – Transfers the contents of registers A and B to timer 4 and timer 4 reload register. – – Transfers the contents of registers A and B to timer 1 reload register. – – Transfers the contents of registers A and B to timer 3 reload register. (T1F) = 1 – Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. (T2F) =1 – Skips the next instruction when the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag. (T3F) = 1 – Skips the next instruction when the contents of T3F flag is “1.” After skipping, clears (0) to T3F flag. (T4F) = 1 – Skips the next instruction when the contents of T4F flag is “1.” After skipping, clears (0) to T4F flag. Datailed description 77 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code IAP0 1 0 0 1 1 0 0 0 0 0 2 6 0 1 1 (A) ← (P0) OP0A 1 0 0 0 1 0 0 0 0 0 2 2 0 1 1 (P0) ← (A) IAP1 1 0 0 1 1 0 0 0 0 1 2 6 1 1 1 (A) ← (P1) OP1A 1 0 0 0 1 0 0 0 0 1 2 2 1 1 1 (P1) ← (A) IAP2 1 0 0 1 1 0 0 0 1 0 2 6 2 1 1 (A2–A0) ← (P22–P20) (A3) ← 0 IAP3 1 0 0 1 1 0 0 0 1 1 2 6 3 1 1 (A) ← (P3) OP3A 1 0 0 0 1 0 0 0 1 1 2 2 3 1 1 (P3) ← (A) IAP4* 1 0 0 1 1 0 0 1 0 0 2 6 4 1 1 (A) ← (P4) OP4A* 1 0 0 0 1 0 0 1 0 0 2 2 4 1 1 (P4) ← (A) IAP5* 1 0 0 1 1 0 0 1 0 1 2 6 5 1 1 (A) ← (P5) OP5A* 1 0 0 0 1 0 0 1 0 1 2 2 5 1 1 (P5) ← (A) CLD 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 (D) ← 1 RD 0 0 0 0 0 1 0 1 0 0 0 1 4 1 1 (D(Y)) ← 0 (Y) = 0 to 7 SD 0 0 0 0 0 1 0 1 0 1 0 1 5 1 1 (D(Y)) ← 1 (Y) = 0 to 7 SZD 0 0 0 0 1 0 0 1 0 0 0 2 4 2 2 (D(Y)) = 0 ? (Y) = 0 to 7 0 0 0 0 1 0 1 0 1 1 0 2 B TK0A 1 0 0 0 0 1 1 0 1 1 2 1 B 1 1 (K0) ← (A) TAK0 1 0 0 1 0 1 0 1 1 0 2 5 6 1 1 (A) ← (K0) TPU0A 1 0 0 0 1 0 1 1 0 1 2 2 D 1 1 (PU0) ← (A) TAPU0 1 0 0 1 0 1 0 1 1 1 2 5 7 1 1 (A) ← (PU0) TFR0A* 1 0 0 0 1 0 1 0 0 0 2 2 8 1 1 (FR0) ← (A) Parameter Mnemonic Input/Output operation Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 *: The 4513 Group does not have these instructions. 78 Hexadecimal notation Function MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha Skip condition Carry flag CY SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER – – Transfers the input of port P0 to register A. – – Outputs the contents of register A to port P0. – – Transfers the input of port P1 to register A. – – Outputs the contents of register A to port P1. – – Transfers the input of port P2 to register A. – – Transfers the input of port P3 to register A. – – Outputs the contents of register A to port P3. – – Transfers the input of port P4 to register A. – – Outputs the contents of register A to port P4. – – Transfers the input of port P5 to register A. – – Outputs the contents of register A to port P5. – – Sets (1) to port D. – – Clears (0) to a bit of port D specified by register Y. – – Sets (1) to a bit of port D specified by register Y. (D(Y)) = 0 (Y) = 0 to 7 – Skips the next instruction when a bit of port D specified by register Y is “0.” – – Transfers the contents of register A to key-on wakeup control register K0. – – Transfers the contents of key-on wakeup control register K0 to register A. – – Transfers the contents of register A to pull-up control register PU0. – – Transfers the contents of pull-up control register PU0 to register A. – – Transfers the contents of register A to direction register FR0. Datailed description 79 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code TABSI 1 0 0 1 1 1 1 0 0 0 2 7 8 1 1 (A) ← (SI3–SI0) (B) ← (SI7–SI4) TSIAB 1 0 0 0 1 1 1 0 0 0 2 3 8 1 1 (SI3–SI0) ← (A) (SI7–SI4) ← (B) TAJ1 1 0 0 1 0 0 0 0 1 0 2 4 2 1 1 (A) ← (J1) TJ1A 1 0 0 0 0 0 0 0 1 0 2 0 2 1 1 (J1) ← (A) SST 1 0 1 0 0 1 1 1 1 0 2 9 E 1 1 (SIOF) ← 0 Serial I/O starting SNZSI 1 0 1 0 0 0 1 0 0 0 2 8 8 1 1 (SIOF) = 1 ? After skipping (SIOF) ← 0 TABAD 1 0 0 1 1 1 1 0 0 1 2 7 9 1 1 (A) ← (AD5–AD2) (B) ← (AD9–AD6) However, in the comparator mode, (A) ← (AD3–AD0) (B) ← (AD7–AD4) TALA 1 0 0 1 0 0 1 0 0 1 2 4 9 1 1 (A) ← (AD1, AD0, 0, 0) TADAB 1 0 0 0 1 1 1 0 0 1 2 3 9 1 1 (AD3–AD0) ← (A) (AD7–AD4) ← (B) TAQ1 1 0 0 1 0 0 0 1 0 0 2 4 4 1 1 (A) ← (Q1) TQ1A 1 0 0 0 0 0 0 1 0 0 2 0 4 1 1 (Q1) ← (A) ADST 1 0 1 0 0 1 1 1 1 1 2 9 F 1 1 (ADF) ← 0 A-D conversion starting SNZAD 1 0 1 0 0 0 0 1 1 1 2 8 7 1 1 (ADF) = 1 ? After skipping (ADF) ← 0 TAQ2 1 0 0 1 0 0 0 1 0 1 2 4 5 1 1 (A) ← (Q2) TQ2A 1 0 0 0 0 0 0 1 0 1 2 0 5 1 1 (Q2) ← (A) NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 (PC) ← (PC) + 1 POF 0 0 0 0 0 0 0 0 1 0 0 0 2 1 1 RAM back-up EPOF 0 0 0 1 0 1 1 0 1 1 0 5 B 1 1 POF instruction valid SNZP 0 0 0 0 0 0 0 0 1 1 0 0 3 1 1 (P) = 1 ? WRST 1 0 1 0 1 0 0 0 0 0 2 A 0 1 1 (WDF1) ← 0 (WEF) ← 1 TAMR 1 0 0 1 0 1 0 0 1 0 2 5 2 1 1 (A) ← (MR) TMRA 1 0 0 0 0 1 0 1 1 0 2 1 6 1 1 (MR) ← (A) TAQ3 1 0 0 1 0 0 0 1 1 0 2 4 6 1 1 (A) ← (Q3) TQ3A 1 0 0 0 0 0 0 1 1 0 2 0 6 1 1 (Q33, Q32) ← (A3, A2) (Q31) ← (CMP1 comparison result) (Q30) ← (CMP0 comparison result) Parameter Mnemonic Other operation A-D conversion operation Serial I/O control operation Type of instructions 80 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecimal notation Function MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha – – Transfers the contents of serial I/O register SI to registers A and B. – – Transfers the contents of registers A and B to serial I/O register SI. – – Transfers the contents of serial I/O mode register J1 to register A. – – Transfers the contents of register A to serial I/O mode register J1. – – Clears (0) to SIOF flag and starts serial I/O. (SIOF) = 1 – Skips the next instruction when the contents of SIOF flag is “1.” After skipping, clears (0) to SIOF flag. – – Transfers the high-order 8 bits of the contents of register AD to registers A and B. – – Transfers the low-order 2 bits of the contents of register AD to the high-order 2 bits of the contents of register A. Simultaneously, the low-order 2 bits of the contents of the register A is “0.” – – Transfers the contents of registers A and B to the comparator register at the comparator mode. – – Transfers the contents of the A-D control register Q1 to register A. – – Transfers the contents of register A to the A-D control register Q1. – – Clears the ADF flag, and the A-D conversion at the A-D conversion mode or the comparator operation at the comparator mode is started. (ADF) = 1 – Skips the next instruction when the contents of ADF flag is “1”. After skipping, clears (0) the contents of ADF flag. – – Transfers the contents of the A-D control register Q2 to register A. – – Transfers the contents of register A to the A-D control register Q2. – – No operation – – Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. – – Makes the immediate POF instruction valid by executing the EPOF instruction. (P) = 1 – Skips the next instruction when P flag is “1”. After skipping, P flag remains unchanged. – – Operates the watchdog timer and initializes the watchdog timer flag WDF1. – – Transfers the contents of the clock control register MR to register A. – – Transfers the contents of register A to the clock control register MR. – – Transfers the contents of the voltage comparator control register Q3 to register A. – – Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits of the register Q3. Datailed description 81 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CONTROL REGISTERS Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 External 1 interrupt enable bit V10 External 0 interrupt enable bit 0 1 0 1 0 1 0 1 Interrupt control register V2 V23 Serial I/O interrupt enable bit V22 A-D interrupt enable bit V21 Timer 4 interrupt enable bit V20 Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 I12 Not used Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) I11 INT0 pin edge detection circuit control bit I10 INT0 pin timer 1 control enable bit 0 1 0 1 0 1 Interrupt control register I2 I23 I22 I21 I20 Not used Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit at RAM back-up : 00002 0 1 0 1 0 1 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 0 1 R/W Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) at reset : 00002 0 1 R/W Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 Interrupt control register I1 I13 at RAM back-up : 00002 at reset : 00002 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. 82 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Timer control register W1 W13 Prescaler control bit W12 Prescaler dividing ratio selection bit W11 Timer 1 control bit W10 Timer 1 count start synchronous circuit control bit Timer 2 control bit W22 Not used at reset : 00002 0 1 0 1 at RAM back-up : state retained Timer 2 count source selection bits W20 0 0 1 1 This bit has no function, but read/write is enabled. 0 1 0 1 Timer control register W3 W33 Timer 3 control bit W32 Timer 3 count start synchronous circuit control bit W31 Timer 3 count source selection bits W30 Timer 4 control bit W42 Not used W41 Timer 4 count source selection bits W40 CNTR1 output control bit W62 D7/CNTR1 function selection bit W61 CNTR0 output control bit W60 D6/CNTR0 output control bit Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal at RAM back-up : state retained R/W 0 1 0 1 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected W31 W30 Count source 0 Timer 2 underflow signal 0 0 Prescaler output 1 1 Not available 0 1 Not available 1 at reset : 00002 0 1 0 1 R/W This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained Stop (state retained) Operating W41 W40 0 0 0 1 1 0 1 1 Timer control register W6 W63 Count source Timer 1 underflow signal at reset : 00002 Timer control register W4 W43 R/W Stop (state retained) Operating W21 W20 W21 R/W Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected 0 1 0 1 0 1 0 1 Timer control register W2 W23 at RAM back-up : 00002 at reset : 00002 at RAM back-up : state retained R/W Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input) Note: “R” represents read enabled, and “W” represents write enabled. 83 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Serial I/O mode register J1 J13 Not used J12 Serial I/O internal clock dividing ratio selection bit J11 Serial I/O port selection bit J10 Serial I/O synchronous clock selection bit at reset : 00002 0 1 0 1 0 1 0 1 Note used Q12 Q11 Analog input pin selection bits (Note 2) Q10 Q23 A-D operation mode selection bit Q22 P43/AIN7 and P4 2/A IN6 pin function selection bit (Not used for the 4513 Group) Q21 Q20 Q32 P41/AIN5 pin function selection bit (Not used for the 4513 Group) P40/AIN4 pin function selection bit (Not used for the 4513 Group) Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit Q31 CMP1 comparison result store bit Q30 CMP0 comparison reslut store bit 0 1 0 1 0 1 0 1 System clock selection bit MR2 Not used MR1 Not used MR0 Not used Notes 1: “R” represents read enabled, “W” represents write enabled. 2: Select AIN4–AIN7 with register Q1 after setting register Q2. 3: Bits 0 and 1 of register Q3 can be only read. 84 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8) at RAM back-up : state retained Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at RAM back-up : state retained Comparator mode P43, P42 (read/write enabled for the 4513 Group) AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 (read/write enabled for the 4513 Group) P40 (read/write enabled for the 4513 Group) AIN4/P40 (read/write enabled for the 4513 Group) at RAM back-up : state retained Voltage comparator (CMP1) invalid 1 Voltage comparator (CMP1) valid 0 Voltage comparator (CMP0) invalid 1 Voltage comparator (CMP0) valid 0 CMP1- > CMP1+ 1 0 CMP1- < CMP1+ CMP0- > CMP0+ 1 CMP0- < CMP0+ at reset : 10002 at RAM back-up : 10002 0 f(XIN) (high-speed mode) 1 0 f(XIN)/2 (middle-speed mode) 0 1 0 1 R/W A-D conversion mode 0 1 R/W This bit has no function, but read/write is enabled. at reset : 00002 Clock control register MR MR3 Instruction clock signal divided by 4 at reset : 00002 Comparator control register Q3 (Note 3) Q33 Instruction clock signal divided by 8 0 1 Q12Q11 Q10 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A-D control register Q2 R/W This bit has no function, but read/write is enabled. at reset : 00002 A-D control register Q1 Q13 at RAM back-up : state retained This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. R/W R/W MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Key-on wakeup control register K0 K03 K02 K01 K00 at reset : 00002 Pins P12 and P13 key-on wakeup 0 Key-on wakeup not used control bit Pins P10 and P11 key-on wakeup 1 Key-on wakeup used 0 Key-on wakeup not used control bit 1 Key-on wakeup used Pins P02 and P03 key-on wakeup Key-on wakeup not used control bit 0 1 Pins P00 and P01 key-on wakeup 0 Key-on wakeup used Key-on wakeup not used control bit 1 Key-on wakeup used at reset : 00002 Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and P13 pull-up transistor 0 Pull-up transistor OFF control bit 1 Pins P10 and P11 pull-up transistor 0 Pull-up transistor ON Pull-up transistor OFF control bit 1 0 Pull-up transistor ON control bit Pins P00 and P01 pull-up transistor 1 Pull-up transistor ON 0 Pull-up transistor OFF control bit 1 Pull-up transistor ON Pins P02 and P03 pull-up transistor FR03 Port P53 input/output control bit FR02 Port P52 input/output control bit FR00 Port P51 input/output control bit Port P50 input/output control bit 0 1 at RAM back-up : state retained R/W at RAM back-up : state retained W Port P53 input Port P53 output 0 1 Port P52 input 0 Port P51 input 1 Port P51 output 0 Port P50 input Port P50 output 1 R/W Pull-up transistor OFF at reset : 00002 Direction register FR0 (Note 2) FR01 at RAM back-up : state retained Port P52 output Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: The 4513 Group does not have the direction register FR0. 85 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Parameter Unit –0.3 to VDD+0.3 V –0.3 to 13 V –0.3 to VDD+0.3 V Supply voltage VI Input voltage P0, P1, P2, P3, P4, P5, RESET, XIN, VDCE VI Input voltage D0–D7 VI Input voltage AIN0–AIN7 VO Output voltage P0, P1, P3, P4, P5, RESET –0.3 to VDD+0.3 VO Output voltage D0–D7 Output voltage XOUT –0.3 to 13 V V –0.3 to VDD+0.3 V Package: 32P6B 300 300 mW Package: 32P4B 1100 VO Conditions Ratings –0.3 to 7.0 Symbol VDD Output transistors in cut-off state Package: 42P2R Pd Power dissipation Ta = 25 °C Topr Operating temperature range –20 to 85 Tstg Storage temperature range –40 to 125 86 V °C °C MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RECOMMENDED OPERATING CONDITIONS 1 (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Mask ROM version f(XIN) ≤ 4.2 MHz Middle-speed mode f(XIN) ≤ 3.0 MHz 2.0 5.5 f(XIN) ≤ 4.2 MHz 4.0 5.5 f(XIN) ≤ 2.0 MHz 2.5 5.5 f(XIN) ≤ 1.5 MHz 2.0 5.5 f(XIN) ≤ 4.2 MHz 2.5 5.5 One Time PROM version f(XIN) ≤ 4.2 MHz f(XIN) ≤ 2.0 MHz High-speed mode 4.0 5.5 5.5 Mask ROM version VDD Supply voltage Limits Min. 2.5 High-speed mode One Time PROM version Middle-speed mode Typ. Max. Unit 5.5 V RAM back-up voltage Mask ROM version 2.5 1.8 (at RAM back-up mode) One Time PROM version 2.0 VIH Supply voltage “H” level input voltage P0, P1, P2, P3, P4, P5, XIN, VDCE 0.8VDD VDD V VIH “H” level input voltage D0–D7 0.8VDD V VIH VIH “H” level input voltage RESET “H” level input voltage CNTR0, CNTR1, SIN, SCK, INT0, INT1 0.85VDD 0.85VDD 12 VDD VIL “L” level input voltage P0, P1, P2, P3, P4, P5, D0–D7, XIN, VDCE VIL “L” level input voltage “L” level input voltage RESET CNTR0, CNTR1, SIN, SCK, INT0, INT1 VDD = 5.0 V P5 VDD = 3.0 V –20 –10 VDD = 5.0 V –10 VDD = 3.0 V –5 VRAM VSS VIL 0 IOH(peak) “H” level peak output current IOH(avg) “H” level average output current P5 (Note) IOL(peak) “L” level peak output current P3, RESET IOL(peak) “L” level peak output current D 6 , D7 IOL(peak) “L” level peak output current D0–D5 IOL(peak) “L” level peak output current IOL(avg) “L” level average output current P3, RESET (Note) IOL(avg) “L” level average output current D6, D7 (Note) IOL(avg) “L” level average output current D0–D5 (Note) IOL(avg) “L” level average output current P0, P1, P4, P5, SCK, SOUT (Note) ΣIOH(avg) “H” level total average current P5 ΣIOL(avg) “L” level total average current V V VDD V V 0 0.2VDD V 0 0.3VDD V 0 0.15VDD V mA mA VDD = 5.0 V 10 VDD = 3.0 V VDD = 5.0 V 4 40 VDD = 3.0 V 30 VDD = 5.0 V 24 VDD = 3.0 V 12 P0, P1, P4, P5, SCK, VDD = 5.0 V 24 SOUT VDD = 3.0 V VDD = 5.0 V 12 5 VDD = 3.0 V 2 VDD = 5.0 V 30 VDD = 3.0 V 15 VDD = 5.0 V 15 VDD = 3.0 V VDD = 5.0 V 7 12 VDD = 3.0 V 6 mA mA mA mA mA mA mA mA –30 P5, D, RESET, SCK, SOUT 80 P0, P1, P3, P4 80 mA Note: The average output current (IOH, IOL) is the average value during 100 ms. 87 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RECOMMENDED OPERATING CONDITIONS 2 (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Conditions (with external clock input) VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V 4.2 3.0 One Time PROM version Middle-speed mode VDD = 2.5 V to 5.5 V 4.2 VDD = 4.0 V to 5.5 V 4.2 High-speed mode VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V 2.0 One Time PROM version VDD = 4.0 V to 5.5 V 4.2 High-speed mode VDD = 2.5 V to 5.5 V 2.0 VDD = 2.0 V to 5.5 V 3.0 VDD = 2.5 V to 5.5 V 3.0 VDD = 4.0 V to 5.5 V 3.0 High-speed mode VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V 1.0 One Time PROM version VDD = 4.0 V to 5.5 V 3.0 High-speed mode VDD = 2.5 V to 5.5 V Mask ROM version One Time PROM version Middle-speed mode Mask ROM version Serial I/O external clock period (“H” and “L” pulse width) VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V 3.0 One Time PROM version VDD = 4.0 V to 5.5 V 1.5 Middle-speed mode VDD = 2.5 V to 5.5 V 3.0 VDD = 4.0 V to 5.5 V 750 1.5 750 High-speed mode VDD = 2.5 V to 5.5 V 1.5 VDD = 4.0 V to 5.5 V 1.5 VDD = 2.5 V to 5.5 V 3.0 4.0 One Time PROM version Timer external input period (“H” and “L” pulse width) Middle-speed mode Mask ROM version High-speed mode 88 2.0 One Time PROM version Middle-speed mode tw(CNTR) 4.0 VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V Mask ROM version VDD = 2.0 V to 5.5 V MHz 1.0 Middle-speed mode VDD = 2.5 V to 5.5 V MHz 0.8 1.5 Mask ROM version High-speed mode Unit 1.5 VDD = 4.0 V to 5.5 V Mask ROM version tw(SCK) Max. Middle-speed mode Middle-speed mode f(XIN) Limits Typ. Mask ROM version Mask ROM version Oscillation frequency Min. µs ns µs ns µs µs VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V 1.5 VDD = 4.0 V to 5.5 V 750 ns VDD = 2.5 V to 5.5 V 1.5 VDD = 2.0 V to 5.5 V µs 3.0 One Time PROM version VDD = 4.0 V to 5.5 V 2.0 750 High-speed mode VDD = 2.5 V to 5.5 V 1.5 ns µs MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter VOH “H” level output voltage P5 VOL “L” level output voltage P0, P1, P4, P5 VOL “L” level output voltage P3, RESET VOL Test conditions VDD = 5 V VDD = 5 V IOL = 12 mA VDD = 3 V VDD = 5 V IOL = 6 mA IOL = 5 mA 2 VDD = 3 V IOL = 2 mA 0.9 VDD = 5 V IOL = 30 mA IOL = 10 mA 0.9 “L” level output voltage D6, D7 IOL = 15 mA 2 IOL = 3 mA 0.9 IIH “H” level input current D0–D7 “L” level input current VI = 12 V VI = 0 V No pull-up of ports P0 and P1, P0, P1, P2, P3, P4, P5, RESET, VDCE port P4 selected, port P5: input state “L” level input current D0–D7 VI = 0 V at RAM back-up mode 2 0.9 VDD = 3 V VI = VDD, port P4 selected, Supply current 2 VDD = 5 V “H” level input current P0, P1, P2, P3, P4, P5, RESET, VDCE IDD 2 0.9 IOL = 5 mA IIH port P5: input state VT+ – VT– Hysteresis INT0, INT1, CNTR0, CNTR1, SIN, SCK VT+ – VT– Hysteresis RESET V µA µA –1 1.8 5.5 Middle-speed mode VDD = 3 V f(XIN) = 400 kHz f(XIN) = 4.0 MHz 0.5 0.9 1.5 Middle-speed mode f(XIN) = 400 kHz 0.2 VDD = 5 V f(XIN) = 4.0 MHz 3.0 0.6 9.0 High-speed mode f(XIN) = 400 kHz 0.6 1.8 VDD = 3 V f(XIN) = 2.0 MHz 0.9 2.7 High-speed mode Ta = 25 °C f(XIN) = 400 kHz 0.3 0.1 0.9 2.7 20 50 125 40 100 250 VDD = 5 V VDD = 3 V 0.3 0.3 VDD = 5 V 1.5 VDD = 3 V 0.6 mA 1 10 6 VI = 0 V V 1 f(XIN) = 4.0 MHz VDD = 3 V V µA VDD = 5 V VDD = 5 V V µA VDD = 3 V Pull-up resistor value V 1 –1 VDD = 5 V RPU Unit V IOL = 15 mA “L” level output voltage D0–D5 at active mode Max. IOH = –10 mA IOH = –5 mA VOL IIL Typ. VDD = 3 V VDD = 3 V IIL Limits Min. 3 2 µA kΩ V V 89 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER A-D CONVERTER RECOMMENDED OPERATING CONDITIONS (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol Parameter Conditions Min. Limits Typ. Max. VDD Supply voltage 2.7 5.5 VIA Analog input voltage VDD Middle-speed mode, VDD ≥ 2.7 V 0 0.8 High-speed mode, VDD ≥ 2.7 V 0.4 f(XIN) Oscillation frequency Unit V V MHz MHz A-D CONVERTER CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol – Test conditions Parameter Min. Limits Typ. Resolution – Linearity error – Differential non-linearity error V0T Zero transition voltage VFST Full-scale transition voltage IADD A–D operating current TCONV A-D conversion time – Comparator resolution – Comparator error (Note) – Comparator comparison time Ta = 25 °C, VDD = 2.7 V to 5.5 V Ta = –25 °C to 85 ° C, VDD = 3.0 V to 5.5 V Ta = 25 °C, VDD = 2.7 V to 5.5 V Ta = –25 °C to 85 ° C, VDD = 3.0 V to 5.5 V VDD = 5.12 V 0 VDD = 3.072 V 0 VDD = 5.12 V VDD = 3.072 V 5105 3060 f(XIN) = 0.4 MHz to 4.0 MHz f(XIN) = 0.4 MHz to 2.0 MHz VDD = 5.0 V VDD = 3.0 V Max. 10 bits ±2 LSB ±0.9 LSB 5 3 20 5115 5125 3069 3075 0.7 2.0 0.4 0.2 15 f(XIN) = 4.0 MHz, Middle-speed mode 93.0 f(XIN) = 4.0 MHz, High-speed mode 46.5 Comparator mode VDD = 5.12 V f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode mV mV mA µs 8 bits ±20 mV ±15 12 VDD = 3.072 V Unit 6 µs Note: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula. Logic value of comparison voltage V ref Vref = VDD 256 ✕n n = Value of register AD (n = 0 to 255) VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VRST Detection voltage IRST Operation current of voltage drop detection circuit 90 Test conditions Parameter Ta = 25 °C VDD = 5.0 V Min. 2.7 3.3 Limits Typ. Max. 4.1 3.5 3.7 50 100 Unit V µA MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER VOLTAGE COMPARATOR RECOMMENDED OPERATING CONDITION (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol Conditions Parameter VDD Supply voltage VINCMP tCMP Voltage comparator input voltage VDD = 3.0 V to 5.5 V VDD = 3.0 V to 5.5 V Voltage comparator response time Min. 3.0 0.3VDD Limits Typ. Max. 5.5 0.7VDD 20 Unit V V µs VOLTAGE COMPARATOR CHARACTERISTICS (Ta = –20 °C to 85 °C, VDD = 3.0 V to 5.5 V, unless otherwise noted) Symbol Test conditions Parameter – Comparison decision voltage error ICMP Voltage comparator operation current CMP0- > CMP0+, CMP0- < CMP0+ CMP1- > CMP1+, CMP1- < CMP1+ VDD = 5.0 V Min. Limits Typ. Max. 20 100 mV 15 50 µA Unit BASIC TIMING DIAGRAM Machine cycle Parameter Clock Pin name XIN System clock = f(XIN) Mi Mi+1 XIN System clock = f(XIN)/2 Port D output D0–D7 Port D input D0–D7 Ports P0, P1, P3, P4, P5 output P00–P03 P10–P13 P30–P33 P40–P43 P50–P53 Ports P0, P1, P2, P3, P00–P03 P10–P13 P4, P5 input P20–P22 P30–P33 P40–P43 P50–P53 Interrupt input INT0,INT1 91 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4513/4514 Group has programmable ROM version software compatible with mask ROM. The built-in PROM of One Time PROM version can be written to and not be erased. The built-in PROM versions have functions similar to those of the mask ROM versions, but they have PROM mode that enables writing to built-in PROM. Table 25 shows the product of built-in PROM version. Figure 49 and 50 show the pin configurations of built-in PROM versions. Table 25 Product of built-in PROM version PROM size RAM size (✕ 10 bits) (✕ 4 bits) M34513E4SP/FP 4096 words 256 words M34513E8FP M34514E8FP 8192 words 8192 words 384 words SP: 32P4B FP: 32P6B-A 32P6B-A 384 words 42P2R-A Product ROM type Package One Time PROM version [shipped in blank] D0 1 32 P13 D1 2 31 P12 P13 1 42 P12 2 41 P11 30 P11 D0 D3 4 29 P10 D1 3 40 P10 D4 5 28 P03 D2 4 39 P03 D3 5 38 P02 D4 6 37 P01 D5 7 36 P00 D5 D6/CNTR0 D7/CNTR1 6 7 8 9 P20/SCK P21/SOUT 10 P22/SIN 11 27 26 25 24 23 22 21 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+ AIN0/CMP0- RESET 12 CNVSS 13 XOUT 14 19 P30/INT0 XIN 15 18 VDCE VSS 16 17 VDD 20 P31/INT1 Outline 32P4B D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK 14 P21/SOUT 15 M34514E8FP 3 M34513E4SP D2 25 P03 27 P11 26 P10 28 P12 30 D0 29 P13 32 D2 31 D1 23 P01 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP0- 26 P32 25 P31/INT1 24 P30/INT0 19 23 VDCE 22 VDD Outline 42P2R-A 22 P00 D6/CNTR0 4 21 D7/CNTR1 5 P20/SCK 6 20 AIN3/CMP1+ AIN2/CMP1- 19 AIN1/CMP0+ P21/SOUT 7 P22/SIN 8 18 M34513ExFP P30/INT0 16 VDCE 15 VSS 13 VDD 14 11 XIN 12 XOUT RESET 9 CNVSS 10 AIN0/CMP017 P31/INT1 Outline 32P6B-A Fig. 49 Pin configuration of built-in PROM version of 4513 Group 92 32 P40/AIN4 27 P33 VSS 21 D4 2 D5 3 33 P41/AIN5 RESET 17 CNVSS 18 XIN 20 24 P02 34 P42/AIN6 P22/SIN 16 XOUT D3 1 35 P43/AIN7 Fig. 50 Pin configuration of built-in PROM version of 4514 Group MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha (1) PROM mode The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapters are listed in Table 26.Contact addresses at the end of this sheet for the appropriate PROM programmer. • Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 51. (2) Notes on handling ➀A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 52 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped). 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 26 Programming adapters Programming adapter Microcomputer M34513E4SP PCA7442SP M34513E4FP, M34513E8FP PCA7442FP M34514E8FP PCA7441 Address 000016 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA 1 1 1 D2 D1 D0 Low-order 5 bits 1FFF16 400016 D4 D3 1 1 1 D4 D3 D2 D1 D0 High-order 5 bits 5FFF16 7FFF16 Set “FF16” to the shaded area. Fig. 51 PROM memory map Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Fig. 52 Flow of writing and test of the product shipped in blank 93 MITSUBISHI MICROCOMPUTERS ARY N I LIM E R P ion cat o cifi t spe bject l a u n a fi are s t o s n it lim s is Thi etric m ice: Not e para Somnge. cha 4513/4514 Group . SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER GZZ-SH52-45B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M2-XXXSP/FP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M2-XXXSP M34513M2-XXXFP Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C512 27C256 ,,, ,,, ,,, Low-order 5-bit data 000016 ,,,,,, , , ,,,,, , High-order 5-bit data 2.00K 07FF16 400016 2.00K 47FF16 7FFF ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 0000 16 2.00K 07FF16 4000 16 2.00K 47FF16 FFFF Set “FF 16 ” in the shaded area. Set “111 2 ” in the area of low-order and high-order 5-bit data. ✽ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M2-XXXSP, 32P6B-A for M34513M2-XXXFP) and attach to the Mask ROM Order Confirmation Form. ✽ 3. Comments 94 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR ion cat o cifi t spe bject l a su fin ot a its are n lim s is Thi etric m ice: Not e para Somnge. cha 4513/4514 Group . SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER GZZ-SH52-44B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M4-XXXSP/FP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M4-XXXSP M34513M4-XXXFP Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C512 27C256 ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 000016 4.00K 0FFF16 400016 4.00K 4FFF16 7FFF16 ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 0000 16 4.00K 0FFF16 4000 16 4.00K 4FFF16 FFFF16 Set “FF 16 ” in the shaded area. Set “111 2 ” in the area of low-order and high-order 5-bit data. ✽ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M4-XXXSP, 32P6B-A for M34513M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. ✽ 3. Comments 95 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR ion cat o cifi t spe bject l a su fin ot a its are n lim s is Thi etric m ice: Not e para Somnge. cha 4513/4514 Group . SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER GZZ-SH53-01B <85A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M6-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C512 27C256 ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 000016 6.00K 17FF16 400016 6.00K 57FF16 7FFF16 ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 0000 16 6.00K 17FF16 4000 16 6.00K 57FF16 FFFF16 Set “FF 16 ” in the shaded area. Set “111 2 ” in the area of low-order and high-order 5-bit data. ✽ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. ✽ 3. Comments 96 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR ion cat o cifi t spe bject l a su fin ot a its are n lim s is Thi etric m ice: Not e para Somnge. cha 4513/4514 Group . SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER GZZ-SH52-99B <85A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M8-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C512 27C256 Low-order 5-bit data High-order 5-bit data 000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16 Low-order 5-bit data High-order 5-bit data 0000 16 8.00K 1FFF16 4000 16 8.00K 5FFF16 FFFF16 Set “FF 16 ” in the shaded area. Set “111 2 ” in the area of low-order and high-order 5-bit data. ✽ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. ✽ 3. Comments 97 MITSUBISHI MICROCOMPUTERS ARY N I LIM E R P ion cat o cifi t spe bject l a u n a fi are s t o s n it lim s is Thi etric m ice: Not e para Somnge. cha 4513/4514 Group . SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER GZZ-SH52-41B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M6-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C512 27C256 ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 000016 6.00K 17FF16 400016 6.00K 57FF16 7FFF16 ,,, ,,, ,,, Low-order 5-bit data High-order 5-bit data 0000 16 6.00K 17FF16 4000 16 6.00K 57FF16 FFFF16 Set “FF 16 ” in the shaded area. Set “111 2 ” in the area of low-order and high-order 5-bit data. ✽ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. ✽ 3. Comments 98 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR ion cat o cifi t spe bject l a su fin ot a its are n lim s is Thi etric m ice: Not e para Somnge. cha 4513/4514 Group . SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER GZZ-SH52-40B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M8-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C512 27C256 Low-order 5-bit data High-order 5-bit data 000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16 Low-order 5-bit data High-order 5-bit data 0000 16 8.00K 1FFF16 4000 16 8.00K 5FFF16 FFFF16 Set “FF 16 ” in the shaded area. Set “111 2 ” in the area of low-order and high-order 5-bit data. ✽ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. ✽ 3. Comments 99 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 17 32 Mitsubishi lot number (6-digit or 7-digit) Mitsubishi IC catalog name 1 16 B. Customer’s Parts Number + Mitsubishi catalog name 17 32 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 1 Note1 : 2: 3: 4: 16 The mark field should be written right aligned. The fonts and size of characters are standard Mitsubishi type. Customer’s Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, , (periods), and (commas) are usable. If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required . , C. Special Mark Required 32 17 1 16 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the Special logo required box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo. 100 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 32P6B (32-PIN LQFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 17 24 16 25 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (4-digit or 5-digit) 32 9 1 8 B. Customer’s Parts Number + Mitsubishi catalog name 24 17 16 25 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 7 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, , (periods), (commas) are usable. . 32 , 9 1 8 101 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 42 22 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 21 1 B. Customer’s Parts Number + Mitsubishi catalog name 42 22 Mitsubishi lot number (6-digit or 7-digit) 1 21 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 11 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, , (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required . , C. Special Mark Required 42 22 1 21 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required 102 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 32P4B Plastic 32pin 400mil SDIP EIAJ Package Code SDIP32-P-400-1.78 Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy 17 1 16 E 32 e1 c JEDEC Code – D Symbol L A1 A A2 A A1 A2 b b1 b2 c D E e e1 L e b1 b b2 SEATING PLANE 32P6B-A Dimension in Millimeters Min Nom Max – – 5.08 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 – 1.778 – – 10.16 – 3.0 – – 0° – 15° Plastic 32pin 7✕7mm body LQFP EIAJ Package Code LQFP32-P-77-0.80 Weight(g) Lead Material Alloy 42 MD e JEDEC Code – b2 ME HD D 32 25 I2 1 24 E HE Recommended Mount Pad Symbol 17 8 9 16 A L1 e y b A1 c A2 F L Detail F A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max – – 1.7 0.1 0.2 0 1.4 – – 0.3 0.35 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 – – 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 – – 0.1 – – 0° 10° – 0.5 – – – – 1.0 – – 7.4 – – 7.4 103 MITSUBISHI MICROCOMPUTERS RY A N IMI L E PR 4513/4514 Group . ion cat cifi ct to e p je ls fina re sub a ot a is n limits s i Th etric m ice: Not e para m o S nge. cha SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 42P2R-A Plastic 42pin 450mil SSOP EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code – Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy e 42 b2 E HE e1 I2 22 F Recommended Mount Pad Symbol 1 21 A D b L y A1 L1 e A2 c Detail F 104 A A1 A2 b c D E e HE L L1 y b2 e1 I2 Dimension in Millimeters Min Nom Max – – 2.4 0.05 – – – 2.0 – 0.35 0.4 0.5 0.13 0.15 0.2 17.3 17.5 17.7 8.2 8.4 8.6 – 0.8 – 11.63 11.93 12.23 0.3 0.5 0.7 – 1.765 – – – 0.15 0° – 10° – 0.5 – – 11.43 – – 1.27 – Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • © 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Aug. 1998. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 4513/4514 GROUP DATA SHEET Revision Description First Edition Rev. date 980807 (1/1)