Mitsubishi M35500BGP Fld(vfd) controller Datasheet

MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
DESCRIPTION/FEATURES
• Serial I/O ..................................... 4 (CS controller, external clock)
• High-breakdown-voltage output port ......................................... 26
•
• Segment output ............................................ 8 to 18
• Digit output ................................................... 7 to 10
(Ports P0 to P7 are also used as ordinary output ports)
• Output breakdown .................................. Vcc – 45 V
• Output current .................. –18 mA (DIG0 to DIG17),
–7 mA (SEG0 to SEG7)
• Pull-down resistor ........................................ build-in
• Dimmer switch ............................................ 4 levels
A-D converter ................................................... 8-bit ✕ 6 channels
• Absolute accuracy ....................................... ±3 LSB
•
•
•
• Noise filter .................................................... build-in
(in serial input pin and clock pin, 2 MHz sampling)
• FLD display data ............................................. input
• A-D conversion data ..................................... output
• Command ....................................................... input
Package ................................................................. 44P6N/44P6X
Oscillating circuit ........... RC oscillating cirucit (external capacitor)
• Oscillating frequency ..................................... 4 MHz
Power source voltage .................................................. 4.0 to 5.5 V
DIG16/SEG9
DIG6/P6
DIG5/P5
24
23
DIG9/SEG16
27
25
DIG10/SEG15
28
DIG8/SEG17
DIG11/SEG14
29
DIG7/P7
DIG13/SEG12
DIG12/SEG13
31
26
DIG14/SEG11
32
30
DIG15/SEG10
33
PIN CONFIGURATION (TOP VIEW)
34
22
DIG4/P4
DIG17/SEG8
35
21
DIG3/P3
SEG7
36
20
DIG2/P2
SEG6
37
19
DIG1/P1
SEG5
38
18
DIG0/P0
SEG4
39
17
VEE
M35500AFP
M35500BGP
7
8
9
10
11
AN2
AN1
AN0
CS
AN3
12
AN4
44
6
VDD
5
SOUT
S IN
4
13
X IN
14
43
RESET
AN5
42
SEG0
3
SEG1
2
SCLK
VSS
VEE
15
XOUT
16
41
1
40
SEG2
VDD
SEG3
Package type: 44P6N-A/44P6X
Fig. 1. Pin configuration of M35500AFP/BGP
1
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
FUNCTIONAL BLOCK
DIG8/SEG17 – DIG17/SEG8
SEG7 – SEG0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DIG7/P7 25
DIG6/P6 24
DIG5/P5 23
Mode
register
DIG4/P4 22
Display control circuit
DIG3/P3 21
DIG2/P2 20
Memory
address
DIG1/P1 19
Display RAM
DIG0/P0 18
Transfer
counter
VEE 17
FUNCTIONAL BLOCK DIAGRAM (Package: 44P6N-A)
VEE 16
Command
analytic circuit
CS 12
SIN 13
Noise filter
Serial I/O
SOUT 14
SCLK 15
Noise filter
VDD 44
Trigger
VDD 1
VSS 3
Selector/A-D
control circuit
Clock generating
circuit
RESET 5
Fig. 2. Functional block diagram
2
Byte end
2
4
XOUT
XIN
6
7
8
9
10 11
AN5 – AN0
A-D
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
PIN DESCRIPTION
Table. 1. Pin description
Pin
Name
Output
Input
Function
VCC, VSS
Power source
• Apply voltage of 5 V to VCC, and 0 V to VSS.
VEE
Pull-down
power source
• Applies voltage supplied to pull-down resistors.
XIN
Clock input
XOUT
Clock output
______
______
RESET
• RC oscillator pins for system clock.
Input
Output
RESET input
CMOS input
• Reset input pin for active “L”.
• Internal pull-up resistors connected between the RESET and VCC pins.
CS
Chip select
CMOS input
• Serial transfer is possible by inputting “L” signal.
SCLK
Serial clock
CMOS input
Noise filter
• Clock for serial transfer is input.
• Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
SOUT
Serial output
SIN
Serial input
DIG0/P0 –
DIG7/P7
Digit/Port
P-channel
open-drain
• Pin for ordinary output or digit output.
• At reset this port is set to VEE level through a pull-down resistor.
DIG8/SEG17 –
DIG17/SEG8
Digit/Segment
P-channel
open-drain
• Pin for digit output or segment output.
• At reset this port is set to VEE level through a pull-down resistor.
SEG0 – SEG7
Segment
P-channel
open-drain
• Pin for segment output.
• At reset this port is set to VEE level through a pull-down resistor.
____
N-channel
open-drain
• Serial data is output.
• During reset it is in high-impedance state.
• Serial data is input.
• Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
CMOS input
Noise filter
PORT BLOCK
(1) Digit/Port pin
Digit/Segment pin
(4) SOUT pin
Shift signal from high-order
Dimmer signal
(Note)
Data bus
Segment data
latch
Shift signal to low-order
SOUT signal
✽
(5) CS pin
VEE
CS input
Noise filter
(2) Digit pin
Shift signal from high-order
Dimmer signal
(Note)
latch
✽
(6) SIN, SCLK pin
Serial input
Serial clock input
Shift signal to low-order
VEE
(3) Segment pin
(7) A-D input
Dimmer signal
(Note)
Segment data
Noise filter
latch
A-D conversion input
✽
VEE
✽ High-breakdown-voltage P-channel transistor
Note: Dimmer signal is for setting the Toff time.
Fig. 3. Port block diagram
3
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
COMMAND STYLE
Display data setting
(Command 0)
b7
b6
b5
b4
1
1
1
—
b3
b2
b1
b0
Number of segment setting
0 0 : 16 or less
0 1 : 17 or more
Number of digit setting
00:7
01:8
10:9
1 1 : 10
Display state setting
(Command 1)
1
1
0
—
—
Display ON or OFF setting
1 : ON
0 : OFF
Display duty setting
1 1 : 15/16
1 0 : 14/16
0 1 : 6/16
0 0 : 5/16
Digit selection
(Command 2)
1
0
1
—
Digit start pin setting
0 0 0 0 : D17
0 0 0 1 : D16
0 0 1 0 : D15
0 0 1 1 : D14
0 1 0 0 : D13
0 1 0 1 : D12
0 1 1 0 : D11
0 1 1 1 : D10
1 0 0 0 : D9
1 0 0 1 : D8
1 0 1 0 : D7
Port data setting
(Command 3)
1
0
0
P3 – P0/P7 – P4 output data
Port selection (Note)
0 : P3 – P0
1 : P7 – P4
Note: When a digit or a port has to be selected, a digit output is selected for having higher priority.
Fig. 4. Command style
4
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
SERIAL I/O PROTOCOL
Byte protocol
CS
CLK
b0
SIN
SOUT
X
b0
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
b6
b6
b7
b7
Note: SOUT is in high-impedance state during CS signal is “H”.
Command protocol
Display data setting
(Command 0)
CS
CLK
SIN
SOUT
Command 0
X
Data 1
Data 2
Data i
X
A-D
data 0
A-D
data j
Note 1: The serial data which is transmitted after executing command 0
is recognized as a display data.
“A-D data 6 or more” data is defined as an undefined “X”.
Note 2: Set the CS signal to “H” level after transferring a display data.
Other setting except
display data setting
(Command 1 to 3)
CS
CLK
SIN
SOUT
Command
X
Fig. 5. Serial I/O protocol
5
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
SERIAL COMMUNICATION FORMAT (DISPLAY DATA, A-D OUTPUT)
17 or more segments (3-byte transfer)
CS
CLK
SIN
Command 0
SEG
0-7
SEG
8-15
SEG
16-17
SEG
0-7
DIG n
X
SOUT
AD
0
X
SEG
8-15
SEG
16-17
SEG
0-7
DIG n-1
AD
1
AD
2
AD
3
SEG SEG
8-15 16-17
SEG
0-7
DIG n-2
AD
4
AD
5
X
SEG
8-15
SEG
16-17
DIG 0
X
X
X
X
SEG
0-7
SEG
8-15
AD valid data
Note: 2 bytes “X” data is output before outputting AD valid data.
16 or less segments (2-byte transfer)
CS
CLK
SIN
Command 0
SEG
0-7
SEG
8-15
DIG n
SOUT
X
X
AD
0
SEG
0-7
SEG
8-15
DIG n-1
AD
1
AD
2
SEG
0-7
SEG
8-15
DIG n-2
AD
3
AD
4
SEG
0-7
SEG
8-15
SEG
0-7
DIG 0
DIG n-3
AD
5
X
X
X
X
X
AD valid data
Note: 2 bytes “X” data is output before outputting AD valid data.
8 or less segments (2-byte transfer)
CS
CLK
SIN
Command 0
SEG dummy SEG dummy SEG dummy SEG dummy SEG
0-7
0-7
0-7
0-7
0-7
data
data
data
data
DIG n
SOUT
X
X
AD
0
DIG n-1
AD
1
AD
2
DIG n-2
AD
3
AD
4
SEG dummy
0-7
data
DIG n-3
AD
5
X
DIG 0
X
X
AD valid data
Note: 2 bytes “X” data is output before outputting AD valid data.
Fig. 6. Serial communication format
6
X
X
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
FLD DISPLAY TIMING
Gn
G n-1
G1
Segment
output
Tscan = 0ns
Tdisp
Digit
Tdisp = 384 µs
(oscillation frequency f(X IN) = 4.0 MHz)
Toff= 264 µs ( 5/16 ✕ Tdisp)
240 µs ( 6/16 ✕ Tdisp)
48 µs (14/16 ✕ Tdisp)
24 µs (15/16 ✕ Tdisp)
Segment
Toff
Tdisp
Fig. 7. FLD display timing diagram
SEGMENT/DIGIT SETTING EXAMPLE
PORT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P7
P6
P5
P4
P3
P2
P1
P0
DIG
DIG17
DIG16
DIG15
DIG14
DIG13
DIG12
DIG11
DIG10
DIG9
DIG8
DIG7
DIG6
DIG5
DIG4
DIG3
DIG2
DIG1
DIG0
SEG
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
Grid
:7
Segment : 8
S1
S2
S3
S4
S5
S6
S7
S8
G7
G6
G5
G4
G3
G2
G1
Grid
: 10 Grid
: 10 Grid
:7
Segment : 8 Segment : 16 Segment : 18
S1
S1
S1
S2
S2
S2
S3
S3
S3
S4
S4
S4
S5
S5
S5
S6
S6
S6
S7
S7
S7
S8
S8
S8
G10
S9
S9
G9
S10
S10
G8
S11
S11
G7
S12
S12
G6
S13
S13
G5
S14
S14
G4
S15
S15
G3
S16
S16
G2
G10
S17
G1
G9
S18
G8
G7
G7
G6
G6
G5
G5
G4
G4
G3
G3
G2
G2
G1
G1
Fig. 8. Segment/Digit setting example
7
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
BIT ALLOCATION FOR DISPLAY RAM
ADDRESS
Fig. 9. Bit allocation for display RAM
8
b7
b0
0916
SEG SEG
17
16
0A16
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
0B16
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
0D16
SEG SEG
17
16
0E16
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
0F16
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
1116
SEG SEG
17
16
1216
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
1316
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
1516
SEG SEG
17
16
1616
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
1716
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
1916
SEG SEG
17
16
1A16
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
1B16
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
1D16
SEG SEG
17
16
1E16
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
1F16
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
2116
SEG SEG
17
16
2216
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
2316
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
2516
SEG SEG
17
16
2616
SEG SEG SEG SEG SEG SEG SEG SEG
9
8
15
14
13
12
11
10
2716
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
2916
SEG SEG
17
16
2A16
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
2B16
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
2D16
SEG SEG
17
16
2E16
SEG SEG SEG SEG SEG SEG SEG SEG
15
14
13
12
11
10
9
8
2F16
SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
Digit0
Digit1
Digit2
Digit3
Digit4
Digit5
Digit6
Digit7
Digit8
Digit9
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
RESET CIRCUIT
To reset the controller, the RESET pin should be held at a “L” level
for 2 µs or more. Then the RESET pin is returned to an “H” level (the
power source voltage should be between 4.0 V and 5.5 V, and XIN
oscillation is stable), reset is released.
Make sure that the reset input voltage is 0.5 V or less for 4.0 V of
VCC.
Poweron
(Note)
RESET
VCC
0V
0.2VCC
0V
Note. Reset release voltage: VCC = 4.0 V
Fig. 10. Reset circuit example
CLOCK GENERATING CIRCUIT
Oscillating circuit is built up by connecting pins XIN and XOUT as short
as possible and connecting a capacitor between pins XIN (XOUT) and
VSS.
When supplying a clock externally, input it to XIN pin and leave XOUT
pin open.
X IN
X IN
XOUT
External oscillation
circuit
COSC
XOUT
Open
VCC
VSS
Fig. 11. RC generating circuit
Fig. 12. External clock input circuit
HANDLING OF UNUSED PINS
Handle unused pins as the follow.
Table. 2. Handling of unused pins
Pin
Handling
Segment
Open
Digit
Open
Analog input
Connect to VCC or VSS through a resistor.
9
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VEE
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Pull-down power source voltage
Input voltage
AN0 – AN5
Input voltage
CS, SIN, SCLK
Input voltage
RESET
Output voltage DIG0 – DIG17
SEG0 – SEG17
Output voltage
• All voltage are based on VSS.
• Output transistors are cut off.
• All voltage are based on VSS.
• Output transistors are cut off.
• A waveform: 450 µs or more
frequency and 30 µs or less
pulse width.
• Connect only capacitor load
(CL = 200pF).
SOUT
VCC
VSS
VEE
VIH
VIH
VIL
VIL
Power dissipation
Operating temperature
Storage temperature
ΣIOH(peak)
ΣIOH(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
f(XIN)
f(SCLK)
–0.3 to 7.0
VCC–45 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
VCC–45 to VCC+0.3
V
V
V
V
V
V
–0.3 to VCC+0.3
V
600
–20 to 85
–40 to 125
mW
°C
°C
Ta = 25 °C
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Min.
4.0
Power source voltage
Power source voltage
Pull-down power source voltage
“H” input voltage
CS, SIN, SCLK
“H” input voltage
RESET
“L” input voltage
CS, SIN, SCLK
“L” input voltage
RESET
RECOMMENDED OPERATING CONDITIONS
Symbol
Unit
VCC–50 to VCC+0.3
• All voltage are based on VSS.
• Output transistors are cut off.
RECOMMENDED OPERATING CONDITIONS
Symbol
Ratings
Conditions
Limits
Typ.
5.0
0
VCC–38
0.75VCC
0.8VCC
0
0
Max.
5.5
VCC
VCC
VCC
0.25VCC
0.2VCC
Unit
V
V
V
V
V
V
V
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
“H” total peak output current
DIG0 – DIG17, SEG0 – SEG17
“H” total peak output current
DIG0 – DIG17, SEG0 – SEG17
“H” peak output current
DIG0 – DIG17
“H” peak output current
SEG0 – SEG7
“L” peak output current
SOUT
“H” peak output current
DIG0 – DIG17
“H” peak output current
SEG0 – SEG7
“L” peak output current
SOUT
Main clock input oscillation frequency
Serial I/O external clock frequency
Min.
Limits
Typ.
(Note 1)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 4)
4.0
250
Max.
–240
–120
–40
–20
10
–18
–7
5.0
5.2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
MHz
kHz
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a 50 % duty cycle.
10
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VOH
“H” output voltage
VOL
VT+ — VT–
“L” output voltage
Hysteresis
IIH
“H” input voltage
IIL
“L” input voltage
ILOAD
ILEAK
Output load current
Output leakage
current
VRAM
ICC
Test conditions
DIG output
SEG output
SOUT
SIN, SCLK, CS
RESET, XIN
SIN, SCLK, CS
RESET
XIN
SIN, SCLK, CS
RESET
XIN
DIG0 – DIG17
SEG0 – SEG17
DIG0 – DIG17
SEG0 – SEG17
ELECTRICAL CHARACTERISTICS
Symbol
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Max.
2.0
0.5
0.5
VI = VCC
5.0
5.0
4.0
VI = VSS
–5.0
–150
–4.0
VEE = VCC–36 V
VOL = VCC
Output transistors “off”
VEE = VCC–38 V
VOL = VCC–38 V
Output transistors “off”
250
500
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
µA
750
µA
–10
µA
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Test conditions
RAM hold voltage
Power source current
A-D CONVERTER CHARACTERISTICS
When clock is stopped
Min.
2.0
VCC = 5 V, f(XIN) = 4.2 MHz
Output transistors “off” at
A-D converter operating
Limits
Typ.
0.5
Max.
5.5
1.0
Unit
V
mA
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Analog input voltage
Analog port input current
Ladder resistor
Tconv
VIA
IIA
RLADDER
IOH = –18 mA
IOH = –7 mA
IOL = 5 mA
VCC = 5.0 V
Min.
VCC–2.0
VCC–2.0
Test conditions
Min.
Limits
Typ.
VCC = 5.12 V
0
0.5
35
Max.
8
±3
100
VCC
5.0
Unit
Bits
LSB
tc(XIN)
V
µA
kΩ
11
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
TIMING REQUIREMENTS
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
tsu(CS)
th(CS)
tre(SCLK)
Parameter
Min.
2
238
60
60
5
2
3
2
3
50 tc(XIN)
50 tc(XIN)
50 tc(XIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Serial clock input cycle time (Note)
Serial clock input “H” pulse width (Note)
Serial clock input “L” pulse width (Note)
Serial input setup time (Note)
Serial input hold time (Note)
Serial input setup time
Serial input hold time
Serial clock interval time
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
CLKs
CLKs
CLKs
CLKs
CLKs
ns
ns
ns
Note: The unit means a number of noise filter sampling clock (2 ✕ tc(XIN)).
SWITCHING CHARACTERISTICS
Symbol
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Test conditions
td(SCLK-SOUT)
tv(SCLK-SOUT)
tr(Pch)
Serial I/O output delay time (Note 1)
Serial I/O output valid time
COSC
External capacitor size (Note 2)
Min.
2
CL = 100pF
VEE = VCC–36 V
High-breakdown-voltage P-channel
open-drain output rising time
Note 1: The unit means a number of noise filter sampling clock (2 ✕ tc(XIN)).
2: An external capacitor size varies with a mounted condition.
Measuring condition: Ta = 25 °C, VCC = 5.0 V
Frequency f(XIN) [MHz]
8.0
7.0
6.0
5.0
4.0
3.0
2.0
10
20
30
40
50
60
70
80
External capacitor size COSC [pF]
Fig. 13. Standard characteristic example of f(XIN)–COSC
12
Limits
Typ.
90
100
Max.
3
3
Unit
CLKs
CLKs
1.8
µs
22
pF
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
Serial I/O clock output port
P-channel output port
RL
CL
CL
VEE
Fig. 14. Output switching characteristics measurement circuit diagram
tw(RESET)
RESET
0.8VCC
0.2VCC
CS
SCLK
trec(SCLK)
tsu(CS)
th(CS)
tC(SCLK)
twL(SCLK)
SCLK
twH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
th(SCLK-SIN)
0.8VCC
0.2VCC
SIN
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
Fig. 15. Timing diagram
13
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
PACKAGE OUTLINE
44P6N-A
Plastic 44pin 10✕10mm body QFP
EIAJ Package Code
QFP44-P-1010-0.80
Weight(g)
0.59
Lead Material
Alloy 42
MD
e
JEDEC Code
–
HD
b2
44
ME
D
34
1
I2
33
E
HE
Recommended Mount Pad
Symbol
23
11
12
22
A
A2
L1
y
M
A1
e
x
c
F
b
L
Detail F
14
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.3
0.35
0.45
0.13
0.15
0.2
9.8
10.0
10.2
9.8
10.0
10.2
–
0.8
–
12.5
12.8
13.1
12.5
12.8
13.1
0.4
0.6
0.8
1.4
–
–
–
–
0.2
–
–
0.1
–
0°
10°
–
–
0.5
1.3
–
–
10.6
–
–
–
–
10.6
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
44P6X
Plastic 44pin 10✕10mm body QFP
EIAJ Package Code
QFP44-P-1010-0.80
Weight(g)
–
Lead Material
Cu Alloy
MD
e
JEDEC Code
–
HD
44
b2
ME
D
34
1
I2
33
E
HE
Recommended Mount Pad
Symbol
23
11
12
22
A
b
y
x
c
F
M
A1
e
A2
L1
L
Detail F
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
2.3
–
–
0
0.2
0.1
2.0
–
–
0.3
0.375
0.45
0.15
0.175
0.2
9.9
10.0
10.1
9.9
10.0
10.1
0.8
–
–
12.5
12.8
13.1
12.8
13.1
12.5
0.4
0.6
0.8
1.4
–
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
1.3
–
–
10.6
–
–
10.6
–
–
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
•
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rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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Notes regarding these materials
•
•
•
•
•
•
•
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Mar. 2000.
Specifications subject to change without notice.
REVISION HISTORY
Rev.
No.
M35500AFP/BGP DATA SHEET
Revision Description
Rev.
date
1.0
First Edition; As M35500AFP/AGP
11/15/97
2.0
The followings are updated:
01/07/00
Product M35500AGP is switched to M35500BGP.
Page 1: Oscillating circuit.....RC oscillating...
Page 3, Table 1: RC oscillator
Page 9: Fig. 11. RC generating circuit
Page 12, TIMING REQUIREMENTS: Limits of tc(SCLK) and twL(SCLK)
Page 12, SWITCHING CHARACTERISTICS: Limits and Unit of tv(SCLK-SOUT)
2.1
Page 15: The 44P6X package outline is added.
(1/1)
03/09/00
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