256MB, 512MB, 1GB Unbuffered DIMM SDRAM SDRAM Unbuffered Module 168pin Unbuffered Module based on 512Mb B-die 62/72-bit Non ECC/ECC Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM Revision History Revision 0.0 (October, 2003) - First release Revision1.0 (January, 2004) - Finalized Revision 1.1 (February, 2004) - Corrected typo. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM 168Pin Unbuffered DIMM based on 512Mb B-die (x8, x16) Ordering Information Part Number Density Organization Component Composition Component Package Height M366S3354BTS-C7A 256MB 32M x 64 32Mx16(K4S511632B) * 4EA 1,000mil M366S6553BTS-C7A 512MB 64M x 64 64Mx8(K4S510832B) * 8EA 1,375mil M374S6553BTS-C7A 512MB 64M x 72 64Mx8(K4S510832B) * 9EA M366S2953BTS-C7A 1GB 128M x 64 64Mx8(K4S510832B)*16EA 1,375mil M374S2953BTS-C7A 1GB 128M x 72 64Mx8(K4S510832B)*18EA 1,375mil 54-TSOP(II) 1,375mil Operating Frequencies 7A @CL3 @CL2 Maximum Clock Frequency 133MHz(7.5ns) 100MHz(10ns) CL-tRCD-tRP(clock) 3-3-3 2-2-2 Feature • • • • • Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 **CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD **CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 **CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD **CLK1 A12 VSS **CKE0 **CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD Note : 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module. 4. ** About these pins, Refer to the Block Diagram of each. Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) DQM0 ~ 7 DQM BA0 ~ BA1 Select bank VDD Power supply (3.3V) DQ0 ~ DQ63 Data input/output VSS Ground CB0 ~ CB7 Check bit (Data-in/data-out) VREF Power supply for reference CLK0 ~ 3 Clock input REGE Register enable CKE0, CKE1 Clock enable input SDA Serial data I/O CS0 ~ CS3 Chip select input SCL Serial clock RAS Row address strobe SA0 ~ 2 Address in EEPROM CAS Colume address strobe DU Don′t use WE Write enable NC No connection * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Columnaddress:(x8: CA0 ~CA9,CA11),(x16:CA0~CA9) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) REGE Register enable The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM 256MB, 32Mx64 Module (M366S3354BTS) (Populated as 1 bank of x16 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM • CS0 DQM0 DQM4 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 CS LDQM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U0 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 UDQM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 • CS2 DQM2 DQM6 LDQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM3 CS LDQM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U1 UDQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 UDQM DQ57 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD A0 ~ A12, BA0 & 1 SDRAM U0 ~ U3 RAS SDRAM U0 ~ U3 CAS SDRAM U0 ~ U3 WE SDRAM U0 ~ U3 CKE0 SDRAM U0 ~ U3 SCL 47KΩ SDA A1 A2 SA0 SA1 SA2 10Ω CLK0/2 • • U0/U2 U1/U3 15pF 10Ω DQn WP A0 Every DQpin of SDRAM 10Ω VDD Vss • • CLK1/3 • • Two 0.1uF Capacitors per each SDRAM To all SDRAMs 10pF Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM 512MB,64Mx64 Non ECC Module(M366S6553BTS)(Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM • CS0 DQM0 DQM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U0 DQM1 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U4 DQM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U1 DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7 • CS2 DQM2 DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2 DQM3 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U6 DQM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U3 A0 ~ A12, BA0 & 1 SDRAM U0 ~ U7 RAS SDRAM U0 ~ U7 CAS SDRAM U0 ~ U7 WE SDRAM U0 ~ U7 CKE0 SDRAM U0 ~ U7 U7 Serial PD SCL 47KΩ WP A0 SDA A1 A2 SA0 SA1 SA2 • U4/U6 10Ω • CLK0/2 • VDD Vss Every DQpin of SDRAM • • 3.3pF*1 • • U1/U3 U5/U7 10Ω DQn U0/U2 One 0.1uF and one 0.22 uF Cap. To all SDRAMs per each SDRAM 10Ω CLK2/3 10pF Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM 512MB, 64Mx72 ECC Module (M374S6553BTS) (Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM • CS0 DQM0 DQM4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U0 DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U5 DQM5 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U1 CS DQM6 U2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM • CS2 DQM2 DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U6 CS U7 DQM7 CS DQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U3 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U8 CS Serial PD U4 SCL SDA WP A0 47KΩ A1 A2 SA0 SA1 SA2 • U0/U3 A0 ~ A12, BA0 & 1 SDRAM U0 ~ U8 RAS SDRAM U0 ~ U8 CAS SDRAM U0 ~ U8 • U6/U8 WE SDRAM U0 ~ U8 • U2 CKE0 SDRAM U0 ~ U8 10Ω CLK0/2 VDD Vss • • *1 : For 4 loads, CLK2 only. Every DQpin of SDRAM 10Ω • • U1/U4 3.3pF*1 10Ω DQn U5/U7 • CLK1/3 One 0.1uF and one 0.22 uF Cap. To all SDRAMs per each SDRAM 10pF Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM 1GB, 128Mx64 Non ECC Module (M366S2953BTS) (Populated as 2 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • • DQM4 CS U0 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U8 • DQM1 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS3 CS2 DQM2 • DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM5 CS U1 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U9 DQM6 U2 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U10 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM7 CS U3 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 ~ A12, BA0 & 1 SDRAM U0 ~ U15 RAS SDRAM U0 ~ U15 CAS SDRAM U0 ~ U15 WE SDRAM U0 ~ U15 CKE0 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 VDD Vss • • SDRAM U0 ~ U7 DQM CS DQ1 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 U13 • DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U11 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 10KΩ A1 CS U15 A2 SA0 SA1 SA2 SDRAM U8 ~ U15 10Ω • CLK0/1/2/3 U0/U1/U2/U3 U4/U5/U6/U7 • • • To all SDRAMs U14 SDA WP A0 • Two 0.1uF Capacitors per each SDRAM CS Serial PD SCL 47KΩ • DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VDD CKE1 DQM • DQM CS Every DQpin of SDRAM • U12 • 10Ω DQn CS DQM CS DQM • DQM3 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • • CS • DQM CS U8/U9/U10/U11 U12/U13/U14/U15 3.3pF Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM 1GB, 128Mx72 ECC Module (M374S2953BTS) (Populated as 2 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 DQM4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U0 • DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS3 CS2 DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U1 CS U2 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U9 • DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM3 • DQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 ~ A12, BA0 & 1 CS U3 CS U4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U10 CS DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 RAS SDRAM U0 ~ U17 SDRAM U0 ~ U17 DQM7 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CKE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U6 Vss • DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 • DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U16 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U8 CS U17 Serial PD SCL VDD WP A0 47KΩ • SDA A1 A2 SA0 SA1 SA2 10KΩ • SDRAM U9 ~ U17 10Ω CLK0/1/2/3 • • CS • U1/U3/U0/U4 U6/U7/U5/U8 • Every DQpin of SDRAM Two 0.1uF Capacitors per each SDRAM U15 • U10/U12/U9/U13 10Ω VDD CS U13 SDRAM U0 ~ U8 DQn U14 DQM CS CS CS SDRAM U0 ~ U17 CKE1 WE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM U12 DQM CS • DQM U11 SDRAM U0 ~ U17 CAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS • • DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM • DQM DQM5 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 • • • • U15/U16/U14/U17 • U2/U11 3.3pF*1 To all SDRAMs *1 : For 4 loads, CLK2 & CLK3 only. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1.0 * # of component W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Symbol Min Typ Max Unit Supply voltage Parameter VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input low voltage VIL -0.3 0 0.8 V 2 Output high voltage VOH 2.4 - - V IOH = -2mA Output low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Symbol Input capacitance (A0 ~ A12) M366S3354BTS M366S6553BTS M366S2953TS Unit Min Max Min Max Min Max CIN1 15 25 25 45 45 85 pF Input capacitance (RAS, CAS, WE) CIN2 15 25 25 45 45 85 pF Input capacitance (CKE) CIN3 15 25 25 45 25 45 pF Input capacitance (CLK) CIN4 10 13 15 21 15 21 pF Input capacitance (CS) CIN5 10 15 15 25 15 25 pF Input capacitance (DQM0 ~ DQM7) CIN6 8 10 8 12 10 15 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 9 12 9 12 13 18 pF Pin Symbol Min Max Min Max Input capacitance (A0 ~ A12) CIN1 28 50 50 95 pF Input capacitance (RAS, CAS, WE) CIN2 28 50 50 95 pF Input capacitance (CKE) CIN3 28 50 28 50 pF Input capacitance (CLK) CIN4 18 25 18 25 pF M374S6553BTS M374S2953BTS Unit Input capacitance (CS) CIN5 18 30 18 30 pF Input capacitance (DQM0 ~ DQM7) CIN6 8 10 13 20 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 9 12 13 18 pF Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM DC CHARACTERISTICS M366S3354BTS (32M x 64,256MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V Version 7A Unit Note 400 mA 1 8 8 mA 80 mA 40 25 25 mA 120 mA 100 mA 520 mA 1 800 12 mA mA 2 Version 7A Unit Note 720 mA 1 16 16 mA M366S6553BTS (64M x 64, 512MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V 160 mA 80 50 50 mA 240 mA 200 mA 800 mA 1 1,600 24 mA mA 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM DC CHARACTERISTICS M374S6553ETS (64M x 72, 512MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V Version 7A Unit Note 810 mA 1 18 18 mA 180 mA 90 55 55 mA 270 mA 225 mA 900 mA 1 1,800 27 mA mA 2 Version 7A Unit Note 960 mA 1 32 32 mA M366S2953BTS (128M x 64, 1GB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V 320 mA 160 100 100 mA 480 mA 400 mA 1,040 mA 1 1,840 48 mA mA 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM DC CHARACTERISTICS M374S2953BTS (128M x 72, 1GB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode ICC1 ICC2P ICC2PS ICC2N ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC =∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V Version 7A Unit Note 1,080 mA 1 36 36 mA 360 mA 180 110 110 mA 540 mA 450 mA 1,170 mA 1 2,070 54 mA mA 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note 7A Row active to row active delay tRRD(min) 15 ns 1 RAS to CAS delay tRCD(min) 20 ns 1 tRP(min) 20 ns 1 1 Row precharge time tRAS(min) 45 ns tRAS(max) 100 us Row cycle time tRC(min) 65 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to Active delay tDAL(min) 2 CLK + tRP - Row active time Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Number of valid output data CAS latency=3 2 CAS latency=2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter 7A Symbol Min CLK cycle time CAS latency=3 CLK to valid output delay CAS latency=3 Output data hold time tCC CAS latency=2 7.5 Note 1000 ns 1 ns 1,2 ns 2 10 5.4 tSAC CAS latency=2 CAS latency=3 Unit Max 6 tOH CAS latency=2 3 3 CLK high pulse width tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 1.5 ns 3 Input hold time tSH 0.8 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.4 ns 6 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh (V=Valid, X=Don′t care, H=Logic high, L=Logic low) CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh H Bank active & row addr. H X Read & column address H X Auto precharge disable Precharge L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H H L H L L X Entry H L Exit L H Entry H L Precharge power down mode Exit L V Column address L X X All banks Clock suspend or active power down L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 Column address H H Bank selection 3 Row address H H Note 1,2 X Auto precharge enable Burst stop A0 ~ A9, A11, A12 3 Auto precharge enable Auto precharge disable A10/AP L L Write & column address Exit H BA0,1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PACKAGE DIMENSIONS : 32Mx64 (M366S3354BTS) Units : Inches (Millimeters) 5.250 (133.350) 5.014 (127.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.700 (17.780) 0.118 (3.000) 0.350 (8.890) B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.250 (6.350) 0.250 (6.350) .450 (11.430) C 0.0984 ±0.008 (2.500 ±0.2) 1.000 (25.40) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.200 Min (5.08 Min) 0.100 Max (2.54 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.050 (1.270) Detail C Tolerances : ± .005(.13) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4S511632B Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PACKAGE DIMENSIONS : 64Mx64 (M366S6553BTS) Units : Inches (Millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.700 (17.780) 0.118 (3.000) 0.350 (8.890) B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.250 (6.350) 0.250 (6.350) .450 (11.430) C 0.0984 ±0.008 (2.500 ±0.2) 1.375 (34.925) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.165 Min (4.19 Min) 0.100 Max (2.54 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.050 (1.270) Detail C Tolerances : ± .005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PACKAGE DIMENSIONS : 64Mx72 (M374S6553BTS) Units : Inches (Millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.700 (17.780) 0.118 (3.000) B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.250 (6.350) 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.0984 ±0.008 (2.500 ±0.2) 1.375 (34.925) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.165 Min (4.19 Min) 0.100 Max (2.54 Max) 0.250 (6.350) 0.123 ± .005 (3.125 ± .125) 0.079 ± .004 (2.000 ± .100) Detail A 0.123 ± .005 (3.125 ± .125) 0.079 ± .004 (2.000 ± .100) Detail B (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.050 (1.270) Detail C Tolerances : ± .005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PACKAGE DIMENSIONS : 128Mx64 (M366S2953BTS) Units : Inches (Millimeters) 5.250 (133.350) 5.014 (127.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.700 (17.780) 0.118 (3.000) 0.350 (8.890) B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.250 (6.350) 0.250 (6.350) .450 (11.430) C 0.0984 ±0.008 (2.500 ±0.2) 1.375 (34.925) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.165 Min (4.19 Min) 0.150 Max (3.81 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± .005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B Rev. 1.1 February 2004 256MB, 512MB, 1GB Unbuffered DIMM SDRAM PACKAGE DIMENSIONS : 128Mx72 (M374S2953BTS) Units : Inches (Millimeters) 5.250 (133.350) 5.014 (127.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.700 (17.780) 0.118 (3.000) 0.350 (8.890) B A .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.250 (6.350) 0.250 (6.350) .450 (11.430) C 0.0984 ±0.008 (2.500 ±0.2) 1.375 (34.925) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.165 Min (4.19 Min) 0.150 Max (3.81 Max) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B (2.500 ±0.2) 0.250 (6.350) 0.0984 ±0.008 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B Rev. 1.1 February 2004