STMicroelectronics M36W0R5020T0 32 mbit (2mb x16, multiple bank, burst) flash memory and 4 mbit sram, 1.8v supply multi-chip package Datasheet

M36W0R5020T0
M36W0R5020B0
32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory
and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
– 1 die of 32 Mbit (2Mb x 16) Flash Memory
– 1 die of 4 Mbit (256Kb x16) SRAM
■
SUPPLY VOLTAGE
– VDDF = VDDQ = VDDS = 1.7 to 1.95V
■
LOW POWER CONSUMPTION
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration):
8814h
– Device Code (Bottom Flash
Configuration): 8815h
■
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■
PROGRAMMING TIME
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■
MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
■
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 66MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70ns
■
DUAL OPERATIONS
– Program Erase in one Bank while Read in
others
– No delay between Read and Write
operations
■
December 2004
Figure 1. Package
FBGA
Stacked TFBGA88
(ZAQ)
BLOCK LOCKING
– All blocks locked at Power-up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
■
SECURITY
– 128-bit user programmable OTP cells
– 64-bit unique device number
■
COMMON FLASH INTERFACE (CFI)
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM
■
ACCESS TIME: 70ns
■
LOW VDDS DATA RETENTION: 1.0V
■
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
■
1/26
M36W0R5020T0, M36W0R5020B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Chip Enable inputs (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Output Enable (GS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDS Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. SRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/26
M36W0R5020T0, M36W0R5020B0
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . . . 16
Figure 9. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.SRAM Standby AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.SRAM Write AC Waveforms, E1S or E2S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.SRAM Write AC Waveforms, WS Controlled, GS High during Write . . . . . . . . . . . . . . . . 19
Figure 13.SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.SRAM Write AC Waveform, UBS and LBS Controlled GS Low . . . . . . . . . . . . . . . . . . . . 20
Table 10. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . . . . . 22
Figure 16.SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . . 22
Table 11. SRAM Low VDDS Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline . . 23
Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Mechanical Data . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M36W0R5020T0, M36W0R5020B0
SUMMARY DESCRIPTION
The M36W0R5020T0 and M36W0R5020B0 combine two memory devices in a Multi-Chip Package:
■
a 32-Mbit, Multiple Bank Flash memory, the
M58WR032FT/B
■
and a 4-Mbit SRAM.
Recommended operating conditions do not allow
more than one memory to be active at the same
time.
The memory is offered in a Stacked TFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
The memory supplied with all the bits erased (set
to ‘1’).
A0-A20 (1)
Address Inputs
DQ0-DQ15
Common Data Input/Output
VDDF
Flash Memory Power Supply
VDDQ
Common Flash and SRAM Power
Supply for I/O Buffers
VPPF
Common Flash Optional Supply
Voltage for Fast Program and Erase
VSS
Ground
VDDS
SRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory
LF
Latch Enable input
EF
Chip Enable input
GF
Output Enable input
WF
Write Enable input
RPF
Reset input
WPF
Write Protect input
KF
Burst Clock
WF
WAITF
Wait Data in Burst Mode
RPF
SRAM
Figure 2. Logic Diagram
VDDQ
VPPF
VDDS
VDDF
21
16
A0-A20
DQ0-DQ15
EF
GF
WPF
WAITF
E1S, E2S
Chip Enable input
GS
Output Enable input
WS
Write Enable input
E1S
UBS
Upper Byte Enable input
GS
LBS
Lower Byte Enable input
LF
M36W0R5020T
M36W0R5020B
KF
WS
Note: 1. A20-A18 are address inputs for the Flash memory component only.
E2S
UBS
LBS
VSS
4/26
Table 1. Signal Names
AI08754b
M36W0R5020T0, M36W0R5020B0
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
A
DU
DU
B
A4
A18
A19
VSS
VDDF
C
A5
LBS
NC
VSS
D
A3
A17
NC
E
A2
A7
F
A1
G
6
7
8
DU
DU
NC
NC
A11
E2S
KF
NC
A12
VPPF
WS
NC
A9
A13
NC
WPF
LF
A20
A10
A15
A6
UBS
RPF
WF
A8
A14
A16
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
NC
H
GS
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
E1S
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
EF
NC
NC
VDDS
NC
NC
VDDQ
NC
L
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI08755
5/26
M36W0R5020T0, M36W0R5020B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A20). Addresses A0-A17
are common inputs for the Flash memory and
SRAM components. The other lines (A18-A20) are
inputs for the Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the
internal state machine. The Flash memory is accessed through the Chip Enable signal (EF) and
through the Write Enable (WF) signal, while the
SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal
(WS).
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address during a Bus Read operation or input a command or
the data to be programmed during a Write Bus operation.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is Low, VIL, and Reset is High, VIH,
the device is in active mode. When Chip Enable is
at VIH the Flash memory is deselected, the outputs
are high impedance and the power consumption is
reduced to the standby level.
It is not allowed to set EF at VIL, E1S at VIL and E2S
at VIH at the same time.
Flash Output Enable (GF). The Output Enable
pin controls data outputs during Flash memory
Bus Read operations.
Flash Write Enable (WF). The Write Enable input controls the Bus Write operation of the Flash
memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR032FT/B datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
6/26
rents, for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH
(refer to Table 7., Flash Memory DC Characteristics - Voltages).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF). WAIT is a Flash memory
output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when the Flash
memory Chip Enable is at VIH or Reset is at VIL. It
can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.
SRAM Chip Enable inputs (E1S, E2S). The
Chip Enable inputs activate the SRAM memory
control logic, input buffers and decoders. E1S at
VIH with E2S at VIH deselects the memory, reducing the power consumption to the standby level,
whereas E2S at VIL deselects the memory and reduces the power consumption to the Power-down
level, regardless of the level of E1S. E1S and E2S
can also be used to control writing to the SRAM
memory array, while WS remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at
the same time.
SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a Read operation of the SRAM memory. GS is active low.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UBS is active low.
M36W0R5020T0, M36W0R5020B0
SRAM Lower Byte Enable (LBS). The
Lower
Byte Enable input enables the lower byte for
SRAM (DQ0-DQ7). LBS is active low.
VDDF Supply Voltage. VDDF provides the power
supply to the internal core of the Flash memory
component. It is the main power supply for all
Flash memory operations (Read, Program and
Erase).
VDDS Supply Voltage. VDDS provides the power
supply to the internal core of the SRAM device. It
is the main power supply for all SRAM operations.
VDDQ Supply Voltage. VDDQ provides the power
supply for the Flash memory and SRAM I/O pins.
This allows all Outputs to be powered independently of the Flash memory and SRAM core power
supplies: VDDF and VDDS, respectively.
VPPF Program Supply Voltage. VPPF is a Flash
memory power supply pin. The Supply Voltage
VDDF and the Program Supply Voltage VPP can be
applied in any order. The pin can also be used as
a control input for the Flash memory.
The two functions are selected by the voltage
range applied to the pin. If VPPF is kept in a low
voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLK
gives an absolute protection against program or
erase, while VPPF > VPP1 enables these functions
(see Tables 6 and 7, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a program or erase; a change in its value
after the operation has started does not have any
effect and program or erase operations continue.
If VPPF is in the range of VPPH it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash
memory (core and I/O Buffers) and SRAM components.
Note: Each Flash memory device in a system
should have its supply voltage (VDDF) and the
program supply voltage VPPF decoupled with a
0.1µF ceramic capacitor close to the pin (high
frequency, inherently low inductance capacitors should be as close as possible to the
package). See Figure 7., AC Measurement
Load Circuit. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
7/26
M36W0R5020T0, M36W0R5020B0
FUNCTIONAL DESCRIPTION
The Flash memory and SRAM components have
separate power supplies but share the same
grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1S and
E2S for the SRAM.
Recommended operating conditions do not allow
more than one device to be active at a time. The
most common example is simultaneous read operations on the Flash memory and SRAM components which would result in a data bus contention.
Therefore it is recommended to put the other devices in the high impedance state when reading
the selected device.
Figure 4. Functional Block Diagram
VDDF
VPPF
VDDQ
A18-A20
EF
32 Mbit
Flash
Memory
GF
WF
WAITF
LF
KF
RPF
A0-A17
WPF
DQ0-DQ15
VDDS
E1S
GS
WS
4Mbit
SRAM
E2S
UBS
LBS
VSS
AI08756b
8/26
M36W0R5020T0, M36W0R5020B0
Table 2. Main Operating modes
WAITF(4)
EF
GF
WF
LF
RPF
Flash Read
VIL
VIL
VIH
VIL(2)
VIH
Flash Write
VIL
VIH
VIL
VIL(2)
VIH
Flash Address
Latch
VIL
X
VIH
VIL
VIH
Flash Data Out
or Hi-Z (3)
Flash Output
Disable
VIL
VIH
VIH
X
VIH
Flash Hi-Z
Flash Standby
VIH
X
X
X
VIH
Hi-Z
X
X
X
X
VIL
Hi-Z
Operation
Flash Reset
E1S
E2S
GS
WS
UBS LBS
DQ15-DQ0
Flash Data Out
Flash Data In
SRAM must be disabled
Any SRAM mode is allowed
Flash Hi-Z
Flash Hi-Z
VIL
VIH
VIL
VIH
VIL
VIL
SRAM data out
SRAM Write
VIL
VIH
X
VIL
VIL
VIL
SRAM data in
Output Disable
VIL
VIH
VIH
VIH
VIL
VIL
SRAM Hi-Z
VIH
X
X
X
X
X
SRAM Hi-Z
X
VIL
X
X
X
X
SRAM Hi-Z
SRAM Read
Flash Memory must be disabled
Any Flash mode is allowed.
SRAM Standby
Note: 1.
2.
3.
4.
X = Don't care.
LF can be tied to VIH if the valid address has been previously latched.
Depends on GF.
WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR032FT/B datasheet for details.
9/26
M36W0R5020T0, M36W0R5020B0
FLASH MEMORY COMPONENT
The M36W0R5020T0 and M36W0R5020B0 contain a 32 Mbit Flash memory. For detailed information on how to use it, see the M58WR032FT/B
datasheet which is available from your local STMicroelectronics distributor.
SRAM COMPONENT
The M36W0R5020T0 and M36W0R5020B0 contain a 4 Mbit SRAM. See Figure 5., SRAM Block
Diagram in conjunction with the SRAM OPERA-
TIONS section, Table 2., Main Operating modes
and the SRAM AC Waveforms and Characteristics
for details.
Figure 5. SRAM Block Diagram
256K x16
RAM Array
2048 x 2048
SENSE AMPS
A0-A10
ROW DECODER
DATA IN DRIVERS
DQ0-DQ7
DQ8-DQ15
COLUMN DECODER
UBS
WS
A11-A17
GS
E2S
E1S
LBS
E2S
POWER-DOWN
CIRCUIT
UBS
E1S
LBS
AI08706b
10/26
M36W0R5020T0, M36W0R5020B0
SRAM OPERATIONS
There are five standard operations that control the
device. These are Read, Write, Standby/Powerdown, Data Retention and Output Disable.
Read. Read operations are used to output the
contents of the SRAM Array.
The device is in Byte Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at
VIH, and UBS or LBS is at VIL.
The device is in Word Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Byte Enable inputs UBS and LBS are both at VIL
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
The Read and Standby AC Waveforms are shown
in Figures 9 and 10, respectively and the parameters are given in Table 9., SRAM Read AC Characteristics.
Write. Write operations are used to write data to
the SRAM. The device is in Write mode whenever
WS, E1S and UBS and/or LBS are at VIL, and E2S
is at VIH. All these signals must be asserted to initiate a Write cycle. The data is latched on the falling edge of E1S, the rising edge of E2S, the falling
edge of WS, or the falling edge of UBS and/or LBS,
whichever occurs last. The Write cycle will terminate on the rising edge of E1S, the rising edge of
WS, the rising edge of UBS and/or LBS, or the falling edge of E2S, whichever occurs first. The tim-
ings are referenced to the signal that terminates
the Write cycle.
The outputs are disabled during Write cycles
(whenever E1S, at VIL, E2S at VIH, and WS at VIL).
The Write AC Waveforms are shown in Figures
11, 12, 13 and 14, while Table 10. gives the Write
AC Characteristics.
Standby/Power-Down. The device automatically
enters the Standby/Power-Down mode when
DQ0-DQ15 are not toggling, reducing the power
consumption to the Standby level, ISB.
The device is also in Standby/Power-Down mode
whenever E1S is at VIH, E2S is at VIL or both UBS
and LBS are at VIH. The outputs then become high
impedance.
The Standby AC Waveforms are shown in Figure
10. See Table 9., SRAM Read AC Characteristics,
for timings.
Data Retention. The data retention mode is entered tCDR after de-asserting E1S, E2S or UBS and
LBS. The data retention performance as VDD goes
down to VDR is described in Table 11., Figures 15
and 16, SRAM Low VDDS Data Retention AC
Waveforms, E1S or UBS / LBS Controlled and
SRAM Low VDDS Data Retention AC Waveforms,
E2S Controlled, respectively.
Output Disable. The device is in the Output Disable mode whenever GS, is at VIH. In this mode,
DQ0-DQ15 are high impedance.
11/26
M36W0R5020T0, M36W0R5020B0
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
Ambient Operating Temperature
–40
85
°C
TBIAS
Temperature Under Bias
–40
125
°C
TSTG
Storage Temperature
–65
155
°C
TLEAD
Lead Temperature During Soldering
(1)
°C
TA
Input or Output Voltage
–0.5
VDDQ+0.6
V
VDDF
Flash Memory Core Supply Voltage
–0.2
2.45
V
VDDQ
Input/Output Supply Voltage
–0.2
2.45
V
VDDS
SRAM Supply Voltage
–0.2
2.4
V
VPPF
Flash Memory Program Voltage
–0.2
14
V
Output Short Circuit Current
100
mA
Time for VPPF at VPPFH
100
hours
VIO
IO
tVPPFH
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
12/26
M36W0R5020T0, M36W0R5020B0
DC AND AC PARAMETERS
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Table 4. Operating and AC Measurement Conditions
Flash Memory
SRAM
Parameter
Unit
Min
Max
Min
Max
VDDF Supply Voltage
1.7
1.95
–
–
V
VDDS Supply Voltage
–
–
1.7
1.95
V
VDDQ Supply Voltage
1.7
1.95
–
–
V
VPPF Supply Voltage (Factory environment)
11.4
12.6
–
–
V
VPPF Supply Voltage (Application environment)
–0.4
VDDQ +0.4
–
–
V
Ambient Operating Temperature
–40
85
–40
85
°C
Load Capacitance (CL)
Output Circuit Resistors (R1, R2)
30
30
pF
16.7
16.7
kΩ
Input Rise and Fall Times
5
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 6. AC Measurement I/O Waveform
1
ns
0 to VDDQ
0 to VDDS
V
VDDQ/2
VDDS/2
V
Figure 7. AC Measurement Load Circuit
VDDQ
VDDQ
VDDF
VDDQ/2
VDDQ
R1
0V
DEVICE
UNDER
TEST
AI06161
CL
0.1µF
R2
0.1µF
CL includes JIG capacitance
AI08364B
Table 5. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
12
pF
VOUT = 0V
15
pF
Note: Sampled only, not 100% tested.
13/26
M36W0R5020T0, M36W0R5020B0
Table 6. Flash Memory DC Characteristics - Currents
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
0V ≤ VIN ≤ VDDQ
±1
µA
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VDDQ
Supply Current
Asynchronous Read (f=6MHz)
EF = VIL, GF = VIH
3
6
mA
4 Word
7
16
mA
8 Word
10
18
mA
16 Word
12
22
mA
Continuous
13
25
mA
4 Word
8
17
mA
8 Word
11
20
mA
16 Word
14
25
mA
Continuous
16
30
mA
Supply Current
Synchronous Read (f=54MHz)
IDD1
Supply Current
Synchronous Read (f=66MHz)
IDD2
Supply Current (Reset)
RPF = VSS ± 0.2V
10
50
µA
IDD3
Supply Current (Standby)
EF = VDDF ± 0.2V
10
50
µA
IDD4
Supply Current (Automatic Standby)
EF = VIL, GF = VIH
10
50
µA
VPPF = VPPH
8
15
mA
VPPF = VDDF
10
20
mA
VPPF = VPPH
8
15
mA
VPPF = VDDF
10
20
mA
Program/Erase in one
Bank, Asynchronous
Read in another Bank
13
26
mA
Program/Erase in one
Bank, Synchronous
Read in another Bank
23
45
mA
EF = VDDF ± 0.2V
10
50
µA
VPPF = VPPH
2
5
mA
VPPF = VDDF
0.2
5
µA
VPPF = VPPH
2
5
mA
VPPF = VDDF
0.2
5
µA
VPPF Supply Current (Read)
VPPF ≤ VDDF
0.2
5
µA
VPPF Supply Current (Standby)
VPPF ≤ VDDF
0.2
5
µA
Supply Current (Program)
IDD5 (1)
Supply Current (Erase)
Supply Current
IDD6 (1,2) (Dual Operations)
IDD7(1)
Supply Current Program/ Erase
Suspended (Standby)
VPPF Supply Current (Program)
IPP1(1)
VPPF Supply Current (Erase)
IPP2
IPP3(1)
Note: 1. Sampled only, not 100% tested.
2. VDDF Dual Operation current is the sum of read and program or erase currents.
14/26
M36W0R5020T0, M36W0R5020B0
Table 7. Flash Memory DC Characteristics - Voltages
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
IOH = –100µA
VDDQ –0.1
VPP1
VPPF Program Voltage-Logic
Program, Erase
1.1
1.8
3.3
V
VPPH
VPPF Program Voltage Factory
Program, Erase
11.4
12
12.6
V
VPPLK
Program or Erase Lockout
0.4
V
VLKO
VDDF Lock Voltage
VRPH
RPF pin Extended High Voltage
V
1
V
3.3
V
Table 8. SRAM DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VDD
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VDDS, Output disabled
±1
µA
10
µA
VDD Standby Current
E1S ≥ VDDS – 0.2V or E2S ≤ 0.2V
VIN ≥ VDDS – 0.2V or VIN ≤ 0.2V
f = fmax (Address and Data inputs only)
f = 0 (GS, WS, UBS and LBS)
E1S ≥ VDDS – 0.2V or E2S ≤ 0.2V
VIN ≥ VDDS – 0.2V or VIN ≤ 0.2V
f = 0, VDD(max)
10
µA
f = fmax = 1/tAVAV, CMOS levels VDDS =
VDDS(max)
6
mA
IOUT = 0 mA, f = 1MHz, CMOS levels
3
mA
IDDS
IDD
Supply Current
VIL
Input Low Voltage
–0.2
0.4
V
VIH
Input High Voltage
1.4
VDDS+0.2
V
VOL
Output Low Voltage
IOL = 0.1mA, VDSD = 1.65V
0.2
V
VOH
Output High Voltage
IOH = −0.1mA, VDDS = 1.65V
1.4
V
15/26
M36W0R5020T0, M36W0R5020B0
Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL
tAVAV
VALID
A0-A17
tAVQV
tAVQX
DQ0-DQ15
DATA VALID
DATA VALID
AI09881
Note: E1S = Low, E2S = High, GS = Low, WS = High.
Figure 9. SRAM Read AC Waveforms, GS Controlled
tE1LE1H
tE2HE2L
VALID
A0-A17
tE1HQZ
tE1LQV
tE2HQV
E1S
tE2LQZ
tE1LQX
tE2HQX
E2S
tGLQV
tGHQZ
GS
tGLQX
LBS, UBS
tBLQX
DQ0-DQ15
tBHQZ
DATA VALID
AI09882
Note: 1. UBS, LBS means both UBS and LBS.
2. Write Enable (WS) = High. Address Valid prior to or at the same time as E1S and UBS, LBS go Low and E2S goes High.
Figure 10. SRAM Standby AC Waveforms
E1S
E2S
IDD
IDDS
tPU
tPD
50%
AI08192
16/26
M36W0R5020T0, M36W0R5020B0
Table 9. SRAM Read AC Characteristics
Symbol
Alt
Parameter
M36W0R5020T0,
M36W0R5020B0
Min
Unit
Max
tAVAV
tE1LE1H
tE2HE2L
tRC
Read Cycle Time
tAVQV
tAA
Address Valid to Output Valid
tAVQX
tOHA
Address Transition to Output Transition
tBHQZ(2)
tHZBE
Byte Enable High to Data Hi-Z
25
ns
tBLQV
tDBE
Byte Enable Low to Data Valid
70
ns
tBLQX(2)
tLZBE
Byte Enable Low to Data Transition
tE1HQZ
tE2LQZ
tHZCE
Chip Enable 1 High or Chip Enable 2 Low to Data Hi-Z
25
ns
tE1LQV
tE2HQV
tACE
Chip Enable 1 Low or Chip Enable 2 High to Data Valid
70
ns
tE1LQX
tE2HQX
tLZCE
Chip Enable 1 Low or Chip Enable 2 High to Data Transition
tGHQZ
tHZOE
Output Enable High to Data Hi-Z
25
ns
tGLQV
tDOE
Output Enable Low to Data Valid
35
ns
tGLQX
tLZOE
Output Enable Low to Data Transition
tPD(1)
Chip Enable 1 High or Chip Enable 2 Low to Power Down
tPU(1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
70
ns
70
10
ns
5
ns
10
ns
5
ns
70
0
ns
ns
ns
Note: 1. Sampled only. Not 100% tested.
2. Whatever the temperature and voltage, tE1HDZ and tE2LDZ are less than tE1LDX and tE2HDX; tBHDZ is less than tBLDX and, tGHDZ is
less than tGHDX.
17/26
M36W0R5020T0, M36W0R5020B0
Figure 11. SRAM Write AC Waveforms, E1S or E2S Controlled
tAVAV
A0-A17
VALID
tAVE1H
tAVE2L
tAVE1L
tE1LE1H
tE1HAX
tAVE2H
tE2HE2L
tE2LAX
E1S
E2S
tWLE1H
tWLE2L
WS
tBLE1H
tBLE2L
UBS, LBS
GS
tDVE1H
tDVE2L
tGHDZ
DQ0-DQ15
Note 2
tE1HDX
tE2LDX
INPUT VALID
AI09883
Note: 1.
2.
3.
4.
18/26
WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
The I/O pins are in output mode and input signals should not be applied.
If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
UBS, LBS means both UBS and LBS.
M36W0R5020T0, M36W0R5020B0
Figure 12. SRAM Write AC Waveforms, WS Controlled, GS High during Write
tAVAV
A0-A17
VALID
tAVWH
tE1LWH
tWHAX
E1S
E2S
tE2HWH
tAVWL
tWLWH
WS
tBLWH
UBS, LBS
GS
tDVWH
tGHDX
DQ0-DQ15
Note 2
tWHDX
INPUT VALID
AI09884
Note: 1.
2.
3.
4.
WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
The I/O pins are in output mode and input signals should not be applied.
If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
UBS, LBS means both UBS and LBS.
19/26
M36W0R5020T0, M36W0R5020B0
Figure 13. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV
VALID
A0-A17
tAVWH
tE1LWH
tE2HWH
tWHAX
E1S
E2S
tBLWH
UBS, LBS
tAVWL
tWLWH
WS
tWHDX
tDVWH
tWLDZ
DQ0-DQ15
tWHDZ
INPUT VALID
Note 1
AI09885
Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.
2. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
3. UBS, LBS means both UBS and LBS.
Figure 14. SRAM Write AC Waveform, UBS and LBS Controlled GS Low
tAVAV
A0-A17
VALID
tAVBH
tE1LBH
tE2HBH
E1S
E2S
tAVBL
tBLBH
tBHAX
UBS, LBS
tWLBH
WS
tDVBH
DQ0-DQ15
Note 2
tBHDX
INPUT VALID
AI09886
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
2. The I/O pins are in output mode and input signals should not be applied.
3. UBS, LBS means both UBS and LBS.
20/26
M36W0R5020T0, M36W0R5020B0
Table 10. SRAM Write AC Characteristics
M36W0R5020T0, M36W0R5020B0
Symbol
Alt
Parameter
Unit
Min
Max
tAVAV
tWC
Write Cycle Time
70
ns
tAVE1L,
tAVE2H,
tAVWL
tAVBL
tSA
Address Valid to Beginning of Write
0
ns
tAVWH
tAVE1H
tAVE2L
tAVBH
tAW
Address Valid to Write Enable High
60
ns
tBLWH
tBLE1H
tBLE2L
tBLBH
tBW
UBS, LBS Valid to End of Write
60
ns
tDVE1H,
tDVE2L,
tDVWH
tDVBH
tSD
Input Valid to End of Write
30
ns
tE1HAX,
tE2LAX,
tWHAX
tBHAX
tHA
End of Write to Address Change
0
ns
tE1HDX,
tE2LDX,
tWHDX
tBHDX
tHD
Data Transition to End of Write
0
ns
tE1LE1H,
tE2HE2L,
tE1LWH
tE2HWH
tE1LBH,
tE2HBH
tSCE
Chip Enable 1 Low or Chip Enable 2 High to
End of Write
60
ns
tGHDZ
tHZOE
Output Enable High to Output Hi-Z
tWHDZ(1)
tLZWE
Write Enable High to Input Transition
tWLDZ(1)
tHZWE
Write Enable Low to Output Hi-Z
tWLWH
tWLE1H
tWLE2L
tWLBH
tPWE
Write Enable Pulse Width
25
10
ns
25
50
ns
ns
ns
Note: 1. Whatever the temperature and voltage, tWLDZ is less than tWHDX.
21/26
M36W0R5020T0, M36W0R5020B0
Figure 15. SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled
DATA RETENTION MODE
VDDS
VDDS (min)
VDDS (min)
VDR
tCDR
tR
E1S or UBS, LBS
AI08197B
Figure 16. SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled
DATA RETENTION MODE
VDDS
VDDS (min)
VDDS (min)
VDR
tCDR
tR
E2S
AI08198B
Table 11. SRAM Low VDDS Data Retention Characteristic
Symbol
Parameter
Test Condition
Min
VDDS = 1.0V, E1S ≥ VDDS – 0.2V
or E2S ≤ 0.2V,
VIN ≥ VDDS – 0.2V or VIN ≤ 0.2V
Max
Unit
8
µA
1.95
V
IDDDR
Supply Current
(Data Retention)
VDR
Supply Voltage
(Data Retention)
tCDR
Chip Disable to Power Down
0
ns
Operation Recovery Time
70
ns
tR
Note: 1. Sampled only. Not 100% tested.
22/26
1.0
M36W0R5020T0, M36W0R5020B0
PACKAGE MECHANICAL
Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline
D
D1
e
SE
E
E2
E1
b
BALL "A1"
ddd
FE
FE1
FD
SD
A2
A
A1
BGA-Z42
Note: Drawing is not to scale.
Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
Max
0.0472
0.200
0.0079
A2
0.850
0.0335
b
0.350
0.300
0.400
0.0138
0.0118
0.0157
D
8.000
7.900
8.100
0.3150
0.3110
0.3189
D1
5.600
0.2205
ddd
0.100
9.900
E
10.000
E1
7.200
0.2835
E2
8.800
0.3465
e
0.800
FD
1.200
0.0472
FE
1.400
0.0551
FE1
0.600
0.0236
SD
0.400
0.0157
SE
0.400
0.0157
–
10.100
0.0039
–
0.3937
0.0315
0.3898
0.3976
–
–
23/26
M36W0R5020T0, M36W0R5020B0
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M36 W0 R 5 0 2 0 T 0 ZAQ T
Device Type
M36 = Multi-Chip Package (Flash + RAM)
Flash 1 Architecture
W = Multiple Bank, Burst mode
Flash 2 Architecture
0 = none present
Operating Voltage
R = VDDF = VDDQ =VDDP = 1.7 to 1.95V
Flash 1 Density
5 = 32 Mbit
Flash 2 Density
0 = none present
RAM 1 Density
2 = 4 Mbit
RAM 0 Density
0 = none present
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
0 = 0.13µm Flash technology, 70ns; 0.15µm RAM, 70ns speed
Package
ZAQ = Stacked TFBGA88 8 x 10mm - 8x10 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free and RoHS Package, Standard Packing
F = Lead-free and RoHS Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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REVISION HISTORY
Table 14. Document Revision History
Date
Version
Revision Details
27-Aug-2003
1.0
First Issue
06-May-2004
2.0
M36W0R5030T0 and M36W0R5030B0 part numbers and 8 Mbit SRAM option
removed. 0.15µm Flash memory technology replaced by the 0.13µm technology.
Package specifications updated. E and F Lead-free Package options added to Table
13., Ordering Information Scheme.
17-Dec-2004
3.0
Document status promoted to full Datasheet.
Flash memory and PSRAM data updated.
TFBGA88 package fully compliant with the ST ECOPACK specification.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2004 STMicroelectronics - All rights reserved
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