256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb B-die
with 64/72-bit Non ECC/ECC
66 TSOP-II
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Table of Contents
1.0 Ordering Information................................................................................................................... 4
2.0 Operating Frequencies................................................................................................................ 4
3.0 Feature.......................................................................................................................................... 4
4.0 Pin Configuration (Front side/back side) ................................................................................. 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Functional Block Diagram .......................................................................................................... 6
6.1 256MB, 32M x 64 Non ECC Module (M368L3324BT(U)).....................................................................................6
6.2 512MB, 64M x 64 Non ECC Module (M368L6523BT(U)) ....................................................................................7
6.3 512MB, 64M x 72 ECC Module (M381L6523B(U)) ..............................................................................................8
6.4 1GB, 128M x 64 Non ECC Module (M368L2923BT(U)) .......................................................................................9
6.5 1GB, 128M x 72 ECC Module (M381L2923BT(U)) ........................................................................................... 10
7.0 Absolute Maximum Ratings...................................................................................................... 11
8.0 DC Operating Conditions.......................................................................................................... 11
9.0 DDR SDRAM IDD spec table ..................................................................................................... 12
9.1 M368L3324BT(U) [ (32M x 16) * 4, 256MB Non ECC Module ] ............................................................................... 12
9.2 M368L6523BT(U) [ (64M x 8) * 8, 512MB Non ECC Module ] ................................................................................. 12
9.3 M381L6523BT(U) [ (64M x 8) * 9, 512MB ECC Module ] .......................................................................................... 13
9.4 M368L2923BT(U) [ (64M x 8) * 16, 1GB Non ECC Module ] .................................................................................... 13
9.5 M381L2923BT(U) [ (64M x 8) * 18, 1GB ECC Module ] ............................................................................................ 14
10.0 AC Operating Conditions........................................................................................................ 15
11.0 Input/Output Capacitance ....................................................................................................... 15
12.0 AC Timming Parameters & Specifications ............................................................................ 16
13.0 System Characteristics for DDR SDRAM .............................................................................. 17
14.0 Component Notes.................................................................................................................... 18
15.0 System Notes ........................................................................................................................... 19
16.0 Command Truth Table............................................................................................................. 20
17.0 Physical Dimensions............................................................................................................... 21
17.1 32M x 64 (M368L3324BT(U)) ..................................................................................................... 21
17.2 64Mx64 (M368L6523BT(U)) ....................................................................................................... 22
17.3 64Mx72 (M381L6523BT(U)) ....................................................................................................... 23
17.4 128Mx64 (M368L2923BT(U)) ..................................................................................................... 24
17.5 128Mx72 (M381L2923BT(U)) ..................................................................................................... 25
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Revision History
Revision
Month
Year
History
0.0
February
2003
- First version for internal review
1.0
August
2003
- Revision 1.0 spec release.
1.1
June
2005
- Deleted “B0, AA, A2” speed and changed master format.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
184Pin Unbuffered DIMM based on 512Mb B-die (x8, x16)
1.0 Ordering Information
Part Number
Density
Organization
Component Composition
Height
M368L3324BT(U)M-C(L)CC/B3
256MB
32M x 64
32Mx16 (K4H511638B) * 4EA
1,250mil
512MB
64M x 64
64Mx8 (K4H510838B) * 8EA
1,250mil
512MB
64M x 72
64Mx8 (K4H510838B) * 9EA
1,250mil
1GB
128M x 64
64Mx8 (K4H510838B) * 16EA
1,250mil
1GB
128M x 72
64Mx8 (K4H510838B) * 18EA
1,250mil
M368L6523BT(U)M-C(L)CC
M368L6523BT(U)N-C(L)B3
M381L6523BT(U)M-C(L)CC/B3
M368L2923BT(U)M-C(L)CC
M368L2923BT(U)N-C(L)B3
M381L2923BT(U)M-C(L)CC/B3
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free)
2.0 Operating Frequencies
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Speed @CL2
-
133MHz
Speed @CL2.5
166MHz
166MHz
Speed @CL3
200MHz
-
CL-tRCD-tRP
3-3-3
2.5-3-3
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided
• SSTL_2 Interface
• 66pin TSOP II (Leaded & Pb-Free(RoHS compliant)) package
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
4.0 Pin Configuration (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
*CS2
DQ48
DQ49
VSS
*CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
DM8
A10
CB6
VDDQ
CB7
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
*CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.
3. Pins 111, 158 are NC for 1row modules & used for 2row modules[ M368(81)L2923B ].
4. Pins 137, 138 are NC for x16 1Row module (M368L3324B).
5.0 Pin Description
A0 ~ A12
Pin Name
Function
Address input (Multiplexed)
BA0 ~ BA1A
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS8
CK0,CK0 ~ CK2, CK2
CKE0, CKE1(for double banks)
CS0, CS1(for double banks)
RAS
CAS
WE
CB0 ~ CB7(for x72 module)
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Check bit(Data-in/data-out)
Pin Name
Function
DM0 ~7,8(for ECC) Data - in mask
Power supply
VDD
(2.5V for DDR333, 2.6V for DDR400)
Power Supply for DQS
VDDQ
(2.5V for DDR333, 2.6V for DDR400)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD, VDDQ level detection
NC
No connection
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
6.0 Functional Block Diagram
6.1 256MB, 32M x 64 Non ECC Module (M368L3324BT(U))
(Populated as 1 bank of x16 DDR SDRAM Module)
CS0
DQS1
DM1
DQ13
DQ14
DQ12
DQ15
DQ9
DQ10
DQ8
DQ11
DQS0
DM0
DQ0
DQ3
DQ4
DQ7
DQ5
DQ2
DQ1
DQ6
DQS3
DM3
DQ29
DQ26
DQ25
DQ30
DQ28
DQ27
DQ24
DQ31
DQS0
DM0
DQ20
DQ23
DQ16
DQ19
DQ17
DQ22
DQ21
DQ18
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS5
DM5
CS
DQ41
DQ42
DQ45
DQ43
DQ44
DQ46
DQ40
DQ47
D0
DQS0
DM0
DQ32
DQ35
DQ36
DQ39
DQ33
DQ38
DQ37
DQ34
CS
DQS3
DM3
DQ57
DQ62
DQ56
DQ58
DQ61
DQ63
DQ60
DQ59
D1
DQS0
DM0
DQ48
DQ51
DQ52
DQ50
DQ49
DQ55
DQ53
DQ54
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D3
A0 - A12
A0-A12: DDR SDRAMs D0 - D3
RAS
CAS: DDR SDRAMs D0 - D3
CKE0
CKE: DDR SDRAMs D0 - D3
WE
WE: DDR SDRAMs D0 - D3
VDDSPD
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
D2
CS
D3
RAS: DDR SDRAMs D0 - D3
CAS
VDD/VDDQ
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Clock Wiring
Clock
DDR SDRAMs
Input
NC
2 DDR SDRAMs
2 DDR SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
SPD
D0 - D3
D0 - D3
VREF
D0 - D3
VSS
D0 - D3
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
Notes:
1. DQ-to-I/O wiring is shown as recomended but
may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 7.5 Ohms
+ 5%
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
6.2 512MB, 64M x 64 Non ECC Module (M368L6523BT(U))
(Populated as 1 bank of x8 DDR SDRAM Module)
CS0
DQS0
DM0
DQS4
DM4
DM/
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
DM/
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DM1
I/O 7
I/O 4
I/O 1
I/O 3
I/O 6
I/O 5
I/O 0
I/O 2
CS
DQS
Serial PD
SCL
D4
SDA
WP
A0
A1
A2
SA0
SA1
SA2
DQS5
DM5
DM/
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
I/O 7
I/O 5
I/O 1
I/O 0
I/O 6
I/O 4
I/O 3
I/O 2
DQS
DM/
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DM2
I/O 6
I/O 4
I/O 3
I/O 1
I/O 7
I/O 5
I/O 2
I/O 0
CS
DQS
D5
VDDSPD
SPD
VDD/VDDQ
D0 - D7
D0 - D7
VREF
D0 - D7
VSS
D0 - D7
DQS6
DM6
DM/
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
I/O 6
I/O 5
I/O 3
I/O 0
I/O 7
I/O 4
I/O 2
I/O 1
D3/D0/D5
DQS
DM/
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DM3
I/O 7
I/O 5
I/O 1
I/O 0
I/O 6
I/O 4
I/O 3
I/O 2
CS
DQS
Cap/Cap/Cap
R=120Ω
D6
CK0/1/2
CK0/1/2 Card
Edge
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BA0 - BA1
A0 - A12
CS
I/O 7
I/O 4
I/O 2
I/O 1
I/O 6
I/O 5
I/O 3
I/O 0
DM/
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 5
I/O 4
I/O 1
I/O 0
I/O 7
I/O 6
I/O 3
I/O 2
A0-A12 : DDR SDRAMs D0 - D7
RAS : DDR SDRAMs D0 - D7
CAS
CAS : DDR SDRAMs D0 - D7
CKE0
CKE : DDR SDRAMs D0 - D7
WE : DDR SDRAMs D0 - D7
CS
Cap/Cap/Cap
DQS
D7
* Clock Wiring
BA0-BA1 : DDR SDRAMs D0 - D7
RAS
WE
Cap
DQS
D3
Cap/Cap/Cap
D4/D2/C7
DQS7
DM7
DM/
Cap/D1/D6
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 DDR SDRAMs
3 DDR SDRAMs
3 DDR SDRAMs
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
*Clock Net Wiring
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
6.3 512MB, 64M x 72 ECC Module (M381L6523BT(U))
(Populated as 1 bank of x8 DDR SDRAM Module)
CS0
DQS0
DM0
DQS4
DM4
DM/
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
DM/
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DM1
I/O 7
I/O 4
I/O 3
I/O 0
I/O 6
I/O 5
I/O 2
I/O 1
CS
DQS
Serial PD
D4
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
DQS5
DM5
DM/
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
I/O 7
I/O 5
I/O 1
I/O 0
I/O 6
I/O 4
I/O 3
I/O 2
DQS
DM/
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DM2
I/O 6
I/O 4
I/O 3
I/O 2
I/O 7
I/O 5
I/O 1
I/O 0
CS
DQS
D5
VDDSPD
SPD
VDD/VDDQ
D0 - D8
D0 - D8
VREF
D0 - D8
VSS
D0 - D8
DQS6
DM6
DM/
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
I/O 6
I/O 5
I/O 3
I/O 0
I/O 7
I/O 4
I/O 2
I/O 1
D3/D0/D6
DQS
DM/
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DM3
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
Cap/Cap/Cap
R=120Ω
D6
CK0/1/2
CK0/1/2 Card
Edge
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS
I/O 7
I/O 4
I/O 3
I/O 1
I/O 6
I/O 5
I/O 2
I/O 0
Cap/Cap/Cap
DQS
DM/
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
Cap/Cap/Cap
D5/D2/D8
DQS7
DM7
DM/
D4/D1/D7
I/O 5
I/O 4
I/O 1
I/O 0
I/O 7
I/O 6
I/O 3
I/O 2
CS
DQS
D7
DQS8
DM8
DM/
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0 - BA1
A0 - A12
CS
I/O 5
I/O 4
I/O 3
I/O 1
I/O 7
I/O 6
I/O 2
I/O 0
DQS
D8
BA0-BA1 : DDR SDRAMs D0 - D8
A0-A12 : DDR SDRAMs D0 - D8
RAS
RAS : DDR SDRAMs D0 - D8
CAS
CAS : DDR SDRAMs D0 - D8
CKE0
CKE : DDR SDRAMs D0 - D8
WE
* Clock Wiring
WE : DDR SDRAMs D0 - D8
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR SDRAMs
3 DDR SDRAMs
3 DDR SDRAMs
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
*Clock Net Wiring
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
6.4 1GB, 128M x 64 Non ECC Module (M368L2923BT(U))
(Populated as 2 bank of x8 DDR SDRAM Module)
CS1
CS0
DQS0
DM0
DQS4
DM4
DM/
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D0
CS
DQS
DM/
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D8
DQS1
DM1
I/O 7
I/O 6
I/O 1
I/O 2
I/O 5
I/O 4
I/O 3
I/O 0
CS
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 2
I/O 3
I/O 4
I/O 7
D4
DQS
D12
DQS5
DM5
DM/
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 5
I/O 6
I/O 1
I/O 0
I/O 7
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
I/O 2
I/O 1
I/O 6
I/O 7
I/O 0
I/O 3
I/O 4
I/O 5
D1
CS
DQS
DM/
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DQS2
DM2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D5
DQS
D13
DQS6
DM6
DM/
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 5
I/O 4
I/O 1
I/O 0
I/O 7
I/O 6
I/O 3
I/O 2
CS
DQS
DM/
I/O 2
I/O 3
I/O 6
I/O 7
I/O 0
I/O 1
I/O 4
I/O 5
D2
CS
DQS
DM/
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
DQS3
DM3
I/O 7
I/O 6
I/O 1
I/O 2
I/O 5
I/O 4
I/O 3
I/O 0
CS
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 2
I/O 3
I/O 4
I/O 7
D6
DQS
D14
DQS7
DM7
DM/
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 5
I/O 6
I/O 1
I/O 0
I/O 7
I/O 4
I/O 3
I/O 2
CS
D3
DQS
DM/
I/O 2
I/O 1
I/O 6
I/O 7
I/O 0
I/O 3
I/O 4
I/O 5
CS
DM/
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D7
DQS
D15
D3/D0/D5
VDDSPD
SPD
VDD/VDDQ
D0 - D15
D11/D8/D13
Serial PD
SCL
D0 - D15
CK0/1/2
VREF
D0 - D15
VSS
D0 - D15
CK0/1/2 Card
Edge
SDA
WP
A0
A1
A2
SA0
SA1
SA2
R=120Ω
*Cap/D1/D6
*Cap/D9/D14
D4/D2/D7
D12/D10/D15
BA0 - BA1
A0 - A12
BA0-BA1 : DDR SDRAMs D0 - D15
RAS
RAS : DDR SDRAMs D0 - D15
CAS
CAS : DDR SDRAMs D0 - D15
CKE 0/1
CKE : DDR SDRAMs D0 - D15
WE
* Clock Wiring
A0-A12: DDR SDRAMs D0 - D15
WE : DDR SDRAMs D0 - D15
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3 Ohms +
5%
*Clock Net Wiring
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
6.5 1GB, 128M x 72 ECC Module (M381L2923BT(U))
(Populated as 2 bank of x8 DDR SDRAM Module)
CS1
CS0
DQS0
DM0
DQS4
DM4
DM/
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM/
DQS
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D0
DQS
DM/
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQS1
DM1
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D4
CS
DQS
D13
DQS5
DM5
DM/
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D1
DQS
DM/
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D10
DQS2
DM2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D5
CS
DQS
D14
DQS6
DM6
DM/
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D2
DQS
DM/
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
DQS3
DM3
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM/
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D6
CS
DQS
D15
DQS7
DM7
DM/
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D3
DM/
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D7
DM/
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D16
DQS8
DM8
DM/
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS
DM/
CS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D8
DQS
D17
D12/D9/D14
R=120Ω
Serial PD
SCL
SDA
WP
A0
SA0
BA0 - BA1
A0 - A12
A1
SA1
VDDSPD
SPD
VDD/VDDQ
D0 - D17
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
SA2
BA0-BA1 : DDR SDRAMs D0 - D17
* Clock Wiring
A0-A12 : DDR SDRAMs D0 - D17
RAS : DDR SDRAMs D0 - D17
CAS
CAS : DDR SDRAMs D0 - D17
CKE0/1
CKE : DDR SDRAMs D0 - D17
WE : DDR SDRAMs D0 - D17
D8/D1/D6
CK0/1/2
A2
RAS
WE
D3/D0/D5
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs
Card
Edge
D17/D10/D15
D4/D2/D7
D13/D11/D16
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors:3 Ohms +
5%
*Clock Net Wiring
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
7.0 Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD,VDDQ
-1.0 ~ 3.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.5 * # of component
W
Short circuit current
IOS
50
mA
Storage temperature
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
8.0 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Supply voltage(for device with a nominal VDD of 2.5V for DDR333)
VDD
2.3
2.7
V
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD
2.5
2.7
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR333)
VDDQ
2.3
2.7
V
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDDQ
2.5
2.7
V
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage(system)
VTT
VREF-0.04
VREF+0.04
V
2
VIH(DC)
VREF+0.15
VDDQ+0.3
V
Input logic high voltage
Note
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
9
mA
Input leakage current
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track
variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
9.0 DDR SDRAM IDD spec table
9.1 M368L3324BT(U) [ (32M x 16) * 4, 256MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
IDD6
Symbol
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
IDD0
660
500
mA
IDD1
760
620
mA
IDD2P
20
20
mA
IDD2F
120
120
mA
IDD2Q
100
100
mA
IDD3P
220
120
mA
IDD3N
400
200
mA
IDD4R
920
780
mA
IDD4W
1,120
860
mA
IDD5
1,060
1,000
mA
20
20
mA
Normal
Low power
IDD7A
12
12
mA
1,800
1,620
mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.2 M368L6523BT(U) [ (64M x 8) * 8, 512MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
IDD6
Symbol
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
IDD0
1,320
1,000
mA
IDD1
1,480
1,200
mA
IDD2P
40
40
mA
IDD2F
240
240
mA
IDD2Q
200
200
mA
IDD3P
440
240
mA
IDD3N
760
400
mA
IDD4R
1,600
1,320
mA
IDD4W
1,920
1,520
mA
IDD5
2,120
2,000
mA
Normal
40
40
mA
Low power
24
24
mA
3,440
3,200
mA
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
9.3 M381L6523BT(U) [ (64M x 8) * 9, 512MB ECC Module ]
(VDD=2.7V, T = 10°C)
IDD6
Symbol
CC(DDR400@CL=3)
B0(DDR333@CL=2.5)
Unit
IDD0
1,485
1,130
mA
IDD1
1,665
1,350
mA
IDD2P
45
45
mA
IDD2F
270
270
mA
IDD2Q
225
230
mA
IDD3P
500
270
mA
IDD3N
855
450
mA
IDD4R
1,800
1,490
mA
IDD4W
2,160
1,710
mA
IDD5
2,385
2,250
mA
Normal
45
45
mA
Low power
27
27
mA
3,870
3,600
mA
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.4 M368L2923BT(U) [ (64M x 8) * 16, 1GB Non ECC Module ]
(VDD=2.7V, T = 10°C)
IDD6
Symbol
CC(DDR400@CL=3)
B0(DDR333@CL=2.5)
Unit
IDD0
2,080
1,400
mA
IDD1
2,240
1,600
mA
IDD2P
80
80
mA
IDD2F
480
480
mA
IDD2Q
400
400
mA
IDD3P
880
480
mA
IDD3N
1,520
800
mA
IDD4R
2,360
1,720
mA
IDD4W
2,680
1,920
mA
IDD5
2,880
2,400
mA
80
80
mA
48
48
mA
4,200
3,600
mA
Normal
Low power
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
9.5 M381L2923BT(U) [ (64M x 8) * 18, 1GB ECC Module ]
(VDD=2.7V, T = 10°C)
IDD6
Symbol
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
Unit
IDD0
2,340
1,580
mA
IDD1
2,520
1,800
mA
IDD2P
90
90
mA
IDD2F
540
540
mA
IDD2Q
450
450
mA
IDD3P
990
540
mA
IDD3N
1,710
900
mA
IDD4R
2,655
1,940
mA
IDD4W
3,015
2,160
mA
IDD5
3,240
2,700
mA
Normal
90
90
mA
Low power
54
54
mA
4,725
4,050
mA
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
10.0 AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Unit
Note
V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
11.0 Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
M368L3324BT(U) M368L6523BT(U) M381L6523BT(U)
Unit
Min
Max
Min
Max
Min
Max
CIN1
41
45
49
57
51
60
pF
Input capacitance(CKE0)
CIN2
34
38
42
50
44
53
pF
Input capacitance( CS0)
CIN3
34
38
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
25
30
25
30
25
30
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
6
7
6
7
6
7
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
6
7
6
7
6
7
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
-
-
-
6
7
pF
Parameter
Symbol
M368L2923BT(U)
M381L2923BT(U)
Min
Min
Max
Max
Unit
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
65
81
69
87
pF
Input capacitance(CKE0,CKE1)
CIN2
42
50
44
53
pF
Input capacitance( CS0, CS1)
CIN3
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
28
34
28
34
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
10
12
10
12
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
10
12
10
12
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
-
10
12
pF
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
12.0 AC Timming Parameters & Specifications
Parameter
Symbol
Row cycle time
CC
(DDR400@CL=3.0)
Min
Max
B3
(DDR333@CL=2.5)
Min
Max
Unit
tRC
55
60
ns
tRFC
70
72
ns
Row active time
tRAS
40
RAS to CAS delay
tRCD
15
Refresh row cycle time
Row precharge time
Row active to Row active delay
Write recovery time
70K
42
70K
18
ns
ns
tRP
15
18
ns
tRRD
10
12
ns
tWR
15
15
ns
tWTR
2
1
tCK
-
-
7.5
12
ns
tCK
6
12
6
12
ns
5
10
-
-
Clock high level width
tCH
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
tCK
Last data in to Read command
CL=2.0
Clock cycle time
CL=2.5
CL=3.0
tDQSCK
-0.55
+0.55
-0.6
+0.6
ns
Output data access time from CK/CK
tAC
-0.65
+0.65
-0.7
+0.7
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.4
-
0.45
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS-out access time from CK/CK
Note
Read Postamble
tRPST
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.72
1.28
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
ns
DQS-in hold time
tWPRE
0.25
0.25
tCK
22
13
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
tCK
Address and Control Input setup time(fast)
tIS
0.6
0.75
ns
15, 17~19
Address and Control Input hold time(fast)
tIH
0.6
0.75
ns
15, 17~19
Address and Control Input setup time(slow)
tIS
0.7
0.8
ns
16~19
Address and Control Input hold time(slow)
tIH
0.7
0.8
ns
16~19
Data-out high impedence time from CK/CK
tHZ
-0.65
+0.65
-0.7
+0.7
ns
11
Data-out low impedence time from CK/CK
tLZ
-0.65
+0.65
-0.7
+0.7
ns
11
Mode register set cycle time
tMRD
10
12
ns
DQ & DM setup time to DQS
tDS
0.4
0.45
ns
j, k
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
ns
Control & Address input pulse width
tIPW
2.2
2.2
ns
18
DQ & DM input pulse width
tDIPW
1.75
1.75
ns
18
Exit self refresh to non-Read command
tXSNR
75
75
ns
Exit self refresh to read command
tXSRD
200
200
tCK
Refresh interval time
tREFI
7.8
Output DQS valid window
tQH
tHP
-tQHS
Clock half period
tHP
tCLmin
or tCHmin
Data hold skew factor
DQS write postamble time
tQHS
7.8
us
14
-
tHP
-tQHS
-
ns
21
-
tCLmin
or tCHmin
-
ns
20, 21
0.55
ns
21
0.6
tCK
12
tCK
23
0.5
tWPST
0.4
0.6
0.4
Active to Read with Auto precharge
command
tRAP
15
18
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
13.0 System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333 devices to ensure proper system performance. these
characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR400
DDR333
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
TBD
TBD
TBD
TBD
V/ns
a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
∆tIS
∆tIH
Units
Notes
0.5 V/ns
0
0
ps
i
0.4 V/ns
+50
0
ps
i
0.3 V/ns
+100
0
ps
i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
∆tDS
∆tDH
Units
Notes
0.5 V/ns
0
0
ps
k
0.4 V/ns
+75
+75
ps
k
0.3 V/ns
+150
+150
ps
k
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
∆tDS
∆tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
j
+/- 0.25 V/ns
+50
+50
ps
j
+/- 0.5 V/ns
+100
+100
ps
j
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
DDR400
DDR333
PARAMETER
MIN
MAX
MIN
MAX
Notes
Output Slew Rate Matching Ratio (Pullup to Pulldown)
TBD
TBD
TBD
TBD
e,m
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
14.0 Component Notes
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions
(generally a coaxial transmission line terminated at the tester electronics).
VDDQ
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew
rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing
the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other
than CK/CK, is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage
level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance
(bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will
be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this
time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the
clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers.
22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15
ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
15.0 System Notes:
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Test point
Output
50Ω
VSSQ
Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
VDDQ
50Ω
Output
Test point
Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range.
For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is
based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate
is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either
VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of
the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or
VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the
DC region must be monotonic.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
16.0 Command Truth Table
COMMAND
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn-1
CKEn
CS
RAS
CAS
WE BA0,1 A10/AP
A0 ~ A9
A11, A12
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
Auto Refresh
Entry
Refresh
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Bank Selection
Precharge
H
L
L
H
H
H
H
X
X
X
X
L
L
H
H
V
H
X
L
H
L
H
V
H
X
L
H
L
L
V
H
X
L
H
H
L
L
H
H
H
X
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
All Banks
Active Power Down
H
Precharge Power Down Mode
DM
H
No operation (NOP) : Not defined
H
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
3
3
3
X
3
Row Address
(A0~A9, A11,A12)
L
Column
Address
H
L
Column
Address
H
X
V
L
X
H
X
X
X
L
H
H
H
4
4, 6
7
X
5
X
X
X
H
4
4
X
8
9
9
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
17.0 Physical Dimensions
17.1 32M x 64 (M368L3324BT(U))
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
B
0.100
(2.30)
A
0.7
(17.80)
0.393
(10.00)
(2X) 0.157
(4.00±0.1)
1.25 ± 0.006
(31.75 ±0.15)
2.500 +0.1/-0.0
0.10 M
1.95
2.55
(64.77)
C B A
0.098 Max
(2.47 Max)
(49.53)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
(2.50 ± 0.2 )
0.250
(6.350)
0.100 ± 0.0079
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.118 Min
(3.00 Min)
0.0787
R (2.00)
0.0078 ±0.006
(0.20 ±0.15)
0.050
(1.270)
Detail B
0.1575 ± 0.004
(4.00 ± 0.1)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx16 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H511638B
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
17.2 64Mx64 (M368L6523BT(U))
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00Min)
5.077
(128.950)
0.7
(17.80)
0.393
B
0.100
(2.30)
A
(10.00)
(2X) 0.157
(4.00 ± 0.1)
1.25 ± 0.006
(31.75 ±0.15)
2.500 +0.1/-0.0
0.10 M
2.55
1.95
(64.77)
(49.53)
C B A
0.07 Max
(1.20 Max)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
(2.50 ± 0.2)
0.250
(6.350)
0.100 ± 0.0079
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00Min)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.0078 ± 0.006
(0.20 ± 0.15)
0.050
(1.270)
Detail B
0.1575 ± 0.004
(4.00 ± 0.1)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838B
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
17.3 64Mx72 (M381L6523BT(U))
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
0.7
(17.80)
0.393
B
0.100
(2.30)
A
(10.00)
(2X) 0.157
(4.00 ± 0.1)
1.25 ± 0.006
(31.75 ±0.15)
2.500 +0.1/-0.0
0.10 M
2.55
1.95
(64.77)
(49.53)
C B A
0.07 Max
(1.20 Max)
0.100
0.250
(6.350)
(2.50 )
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
0.118 Min
(3.00 Min)
0.0078 ± 0.006
(0.20 ± 0.15)
0.050
(1.270)
Detail B
0.1575 ± 0.004
(4.00 ± 0.1)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838B
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
17.4 128Mx64 (M368L2923BT(U))
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
0.7
(17.80)
0.393
B
0.100
(2.30)
A
(10.00)
(2X) 0.157
(4.00 ± 0.1)
1.25 ± 0.006
(31.75 ±0.15)
2.500 +0.1/-0.0
0.10 M
2.55
1.95
(64.77)
(49.53)
C B A
0.145 Max
(3.67 Max)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
(2.50 ± 0.2)
0.250
(6.350)
0.100 ± 0.0079
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.0078 ± 0.006
(0.20 ± 0.15)
0.050
(1.270)
Detail B
0.1575 ± 0.004
(4.00 ± 0.1)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838B
Rev. 1.1 June 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
17.5 128Mx72 (M381L2923BT(U))
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
0.7
(17.80)
0.393
0.100 ± 0.005
(2.30 ± 0.13)
B
A
(10.00)
(2X) 0.157
(4.00 ± 0.1)
1.25 ± 0.006
(31.75 ±0.15)
2.500 +0.1/-0.0
0.10 M
2.55
1.95
(64.77)
(49.53)
C B A
0.145 Max
(3.67 Max)
0.100
0.250
(6.350)
(2.50 )
0.050 ± 0.0039
(1.270 ± 0.10)
0.0787
R (2.00)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
0.118 Min
(3.00 Min)
0.039 ± 0.002
(1.000 ± 0.050)
0.0078 ± 0.006
(0.20 ± 0.15)
0.050
(1.270)
Detail B
0.1575 ± 0.004
(4.00 ± 0.1)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838B
Rev. 1.1 June 2005