Renesas M38B78M3H-AXXXFP 8-bit single-chip microcomputer 740 family / 38000 sery Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
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have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
38B7
Group
User’s Manual
http://www.infomicom.maec.co.jp/indexe.htm
Before using this material, please visit the above website to confirm that this is the most
current document available.
Rev. 1.3
Revision date: Jan. 29, 2003
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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REVISION HISTORY
Rev.
38B7 GROUP USER’S MANUAL
Date
Description
Summary
Page
1.0
07/07/00
1.1
03/10/00
First Edition
74
100
Mask options B to G are shaded to show that they cannoto be specified. Note 4
added.
Absolute maximum ratings
VEE VCC–45 to VCC +0.3
VI
VCC–45 to VCC +0.3
VO VCC–45 to VCC +0.3
1.2
11/01/01
1-2
1-2
1-7
1-8
1-75
Explanations of “DESCRIPTION” are partly eliminated.
Oscillation frequency value of “FEATURES” are partly revised.
Figure 3 is partly revised.
Figure 4 is partly revised.
“MASK OPTION OF PULL-DOWN RESISTOR” is eliminated.
1.3
01/29/03
1-21
1-41
1-100
Explanations of “■Note” are revised.
“■Notes” is added.
“Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs” is added.
Sub clause name and explanations of “(7) Setting procedure when serial I/O2
transmit interrupt is used” are revised.
Clause name and explanations of “2.11.3 Each port state during “L” state of
RESET pin” are revised.
Table name of Table 2.11.1 is revised.
Note of Table 2.11.1 is eliminated.
Table 2.13.1 is partly revised.
Explanations of “2.13.5 Serial I/O mode” are partly revised.
Table 2.13.2 is partly revised.
Figure 3.2.2 is revised.
Sub clause name and explanations of “(1) Change of relevant register settings”
are revised.
Sub clause name and explanations of “(7) Setting procedure when serial I/O2
transmit interrupt is used” are revised.
Clause name and explanations of “3.3.11 Each port state during “L” state of
RESET pin” are revised.
Table name of Table 3.3.3 is revised.
2-91
2-164
2-164
2-164
2-177
2-177
2-177
3-10
3-15
3-21
3-23
3-23
(1/1)
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 38B7 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 38B7 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “740 Family
Software Manual.”
For details of development support tools, refer to the
“Mitsubishi Microcomputer Development Support Tools”
Homepage (http://www.tool-spt.maec.co.jp/index_e.htm).
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes a list of registers, and necessary information for systems development using
the microcomputer.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
b
0
Name
Processor mode bits
1
Functions
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
0
0
0
2
Stack page selection bit
3
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
0
✕
5
Fix this bit to “0.”
0
6
Main clock division ratio selection
bits
4
b7 b6
7
: Bit in which nothing is arranged
0 0 : φ = XIN /2 (High-speed mode)
0 1 : φ = XIN /8 (Middle-speed mode)
1 0 : φ = XIN /8 (Middle-speed mode)
1 1 : φ = XIN (Double-speed mode)
1
0
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻ ••••••Contents determined by option at reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES .................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-3
FUNCTIONAL BLOCK .................................................................................................................. 1-4
PIN DESCRIPTION ........................................................................................................................ 1-5
PART NUMBERING ....................................................................................................................... 1-7
GROUP EXPANSION .................................................................................................................... 1-8
Memory Type ............................................................................................................................ 1-8
Memory Size ............................................................................................................................. 1-8
Package ..................................................................................................................................... 1-8
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-9
Central Processing Unit (CPU) .............................................................................................. 1-9
Memory .................................................................................................................................... 1-13
I/O Ports .................................................................................................................................. 1-15
Interrupts ................................................................................................................................. 1-21
Timers ...................................................................................................................................... 1-24
Serial I/O ................................................................................................................................. 1-29
FLD Controller ........................................................................................................................ 1-44
A-D Converter ......................................................................................................................... 1-61
D-A Converter ......................................................................................................................... 1-62
PWM (Pulse Width Modulation) ........................................................................................... 1-63
Interrupt Interval Determination Function ............................................................................ 1-66
Watchdog Timer ..................................................................................................................... 1-68
Buzzer Output Circucit .......................................................................................................... 1-69
Reset Circuit ........................................................................................................................... 1-70
Clock Generating Circuit ....................................................................................................... 1-72
Power Dissipation Calculating Method ................................................................................ 1-75
Flash Memory Mode .............................................................................................................. 1-78
NOTES ON PROGRAMMING ..................................................................................................... 1-99
NOTES ON USAGE ................................................................................................................... 1-100
DATA REQUIRED FOR MASK ORDERS .............................................................................. 1-100
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory assignment ....................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Terminate unused pins .................................................................................................. 2-8
2.1.4 Notes on I/O port ........................................................................................................... 2-9
2.1.5 Termination of unused pins ........................................................................................ 2-10
2.2 Timer ....................................................................................................................................... 2-11
2.2.1 Memory map ................................................................................................................. 2-10
2.2.2 Relevant registers ........................................................................................................ 2-12
2.2.3 Timer application examples ........................................................................................ 2-21
38B7 Group User’s Manual
i
Table of contents
2.3 Serial I/O ................................................................................................................................ 2-37
2.3.1 Memory map ................................................................................................................. 2-37
2.3.2 Relevant registers ........................................................................................................ 2-38
2.3.3 Serial I/O1 connection examples ............................................................................... 2-50
2.3.4 Serial I/O1’s modes ..................................................................................................... 2-52
2.3.5 Serial I/O1 application examples ............................................................................... 2-53
2.3.6 Serial I/O2 connection examples ............................................................................... 2-59
2.3.7 Serial I/O2’s modes ..................................................................................................... 2-61
2.3.8 Serial I/O2 application examples ............................................................................... 2-62
2.3.9 Serial I/O3 connection examples ............................................................................... 2-81
2.3.10 Serial I/O3’s modes ................................................................................................... 2-83
2.3.11 Serial I/O3 application examples ............................................................................. 2-84
2.3.12 Notes on serial I/O1 .................................................................................................. 2-87
2.3.13 Notes on serial I/O2 .................................................................................................. 2-89
2.4 FLD controller ...................................................................................................................... 2-92
2.4.1 Memory assignment ..................................................................................................... 2-92
2.4.2 Relevant registers ........................................................................................................ 2-93
2.4.3 FLD controller application examples ....................................................................... 2-101
2.4.4 Notes on FLD controller ............................................................................................ 2-132
2.5 A-D converter ..................................................................................................................... 2-133
2.5.1 Memory assignment ................................................................................................... 2-133
2.5.2 Relevant registers ...................................................................................................... 2-134
2.5.3 A-D converter application examples ........................................................................ 2-138
2.5.4 Notes on A-D converter ............................................................................................ 2-140
2.6 D-A converter ..................................................................................................................... 2-141
2.6.1 Memory assignment ................................................................................................... 2-141
2.6.2 Relevant registers ...................................................................................................... 2-141
2.6.3 D-A converter application examples ........................................................................ 2-143
2.6.4 Notes on D-A converter ............................................................................................ 2-144
2.7 PWM ...................................................................................................................................... 2-145
2.7.1 Memory assignment ................................................................................................... 2-145
2.7.2 Relevant registers ...................................................................................................... 2-145
2.7.3 PWM application example ......................................................................................... 2-147
2.7.4 Notes on PWM ........................................................................................................... 2-148
2.8 Interrupt interval determination function ..................................................................... 2-149
2.8.1 Memory assignment ................................................................................................... 2-149
2.8.2 Relevant registers ...................................................................................................... 2-149
2.8.3 Interrupt interval determination function application examples ............................ 2-153
2.9 Watchdog timer .................................................................................................................. 2-157
2.9.1 Memory assignment ................................................................................................... 2-157
2.9.2 Relevant register ........................................................................................................ 2-157
2.9.3 Watchdog timer application examples ..................................................................... 2-159
2.9.4 Notes on watchdog timer .......................................................................................... 2-160
2.10 Buzzer output circuit ...................................................................................................... 2-161
2.10.1 Memory assignment ................................................................................................. 2-161
2.10.2 Relevant register ...................................................................................................... 2-161
2.10.3 Buzzer output circuit application examples .......................................................... 2-162
2.11 Reset circuit ..................................................................................................................... 2-163
2.11.1 Connection example of reset IC ............................................................................ 2-163
2.11.2 Notes on reset .......................................................................................................... 2-164
2.11.3 Each port state during “L” state of RESET pin ................................................... 2-164
ii
38B7 Group User’s Manual
Table of contents
2.12 Clock generating circuit ................................................................................................ 2-165
2.12.1 Relevant register ...................................................................................................... 2-165
2.12.2 Clock generating circuit application examples ..................................................... 2-166
2.13 Flash memory ................................................................................................................... 2-174
2.13.1 Overview .................................................................................................................... 2-174
2.13.2 Memory map ............................................................................................................. 2-174
2.13.3 Relevant registers .................................................................................................... 2-175
2.13.4 Parallel I/O mode ..................................................................................................... 2-177
2.13.5 Serial I/O mode ........................................................................................................ 2-177
2.13.6 CPU reprogramming mode ..................................................................................... 2-178
2.13.7 Flash memory mode application examples .......................................................... 2-179
2.13.8 Notes on CPU reprogramming mode .................................................................... 2-188
2.13.9 Notes on flash memory version ............................................................................. 2-188
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-2
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 A-D converter characteristics ....................................................................................... 3-6
3.1.5 D-A converter characteristics ....................................................................................... 3-6
3.1.6 Timing requirements and switching characteristics ................................................... 3-7
3.2 Standard characteristics .................................................................................................... 3-10
3.2.1 Power source current standard characteristics ........................................................ 3-10
3.2.2 Port standard characteristics ...................................................................................... 3-11
3.2.3 A-D conversion standard characteristics ................................................................... 3-14
3.3 Notes on use ........................................................................................................................ 3-15
3.3.1 Notes on interrupts ...................................................................................................... 3-15
3.3.2 Notes on I/O port ......................................................................................................... 3-16
3.3.3 Notes on serial I/O1 .................................................................................................... 3-17
3.3.4 Notes on serial I/O2 .................................................................................................... 3-19
3.3.5 Notes on FLD controller .............................................................................................. 3-21
3.3.6 Notes on A-D converter .............................................................................................. 3-22
3.3.7 Notes on D-A converter .............................................................................................. 3-22
3.3.8 Notes on PWM ............................................................................................................. 3-22
3.3.9 Notes on watchdog timer ............................................................................................ 3-23
3.3.10 Notes on reset ............................................................................................................ 3-23
3.3.11 Each pin state during “L” state of RESET pin ...................................................... 3-23
3.3.12 Notes on programming .............................................................................................. 3-24
3.3.13 Notes on CPU reprogramming mode ...................................................................... 3-26
3.3.14 Notes on flash memory version ............................................................................... 3-26
3.3.15 Termination of unused pins ...................................................................................... 3-27
3.4 Countermeasures against noise ...................................................................................... 3-28
3.4.1 Shortest wiring length .................................................................................................. 3-28
3.4.2 Connection of bypass capacitor across V SS line and V CC line ............................... 3-30
3.4.3 Wiring to analog input pins ........................................................................................ 3-31
3.4.4 Oscillator concerns ....................................................................................................... 3-32
3.4.5 Setup for I/O ports ....................................................................................................... 3-33
3.4.6 Providing of watchdog timer function by software .................................................. 3-34
38B7 Group User’s Manual
iii
Table of contents
3.5 Control registers .................................................................................................................. 3-35
3.6 Package outline ................................................................................................................... 3-75
3.7 Machine instructions .......................................................................................................... 3-76
3.8 List of instruction code ..................................................................................................... 3-87
3.9 M35501FP .............................................................................................................................. 3-88
3.10 SFR memory map ............................................................................................................ 3-100
3.11 Pin configuration ............................................................................................................. 3-101
iv
38B7 Group User’s Manual
List of figures
List of figures
CHAPTER 1 HARDWARE
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1 Pin configuration of M38B79MFH-XXXXFP .................................................................... 1-3
2 Functional block diagram ................................................................................................... 1-4
3 Part numbering .................................................................................................................... 1-7
4 Memory expansion plan ..................................................................................................... 1-8
5 740 Family CPU register structure................................................................................... 1-9
6 Register push and pop at interrupt generation and subroutine call ......................... 1-10
7 Structure of CPU mode register ..................................................................................... 1-12
8 Memory map diagram ...................................................................................................... 1-13
9 Memory map of special function register (SFR) .......................................................... 1-14
10 Structure of pull-up control registers (PULL1, PULL2 and PULL3) ........................ 1-15
11 Port block diagram (1) ................................................................................................... 1-18
12 Port block diagram (2) ................................................................................................... 1-19
13 Port block diagram (3) ................................................................................................... 1-20
14 Interrupt control ............................................................................................................... 1-23
15 Structure of interrupt related registers ........................................................................ 1-23
16 Structure of timer related register ................................................................................ 1-24
17 Block diagram of timer .................................................................................................. 1-25
18 Timing chart of timer 6 PWM 1 mode ........................................................................... 1-26
19 Block diagram of timer X .............................................................................................. 1-28
20 Structure of timer X related registers .......................................................................... 1-28
21 Block diagram of serial I/O1 ......................................................................................... 1-29
22 Structure of serail I/O1 control registers 1, 2 ............................................................ 1-30
23 Structure of serial I/O1 control register 3 ................................................................... 1-31
24 Structure of serial I/O1 automatic transfer data pointer ........................................... 1-32
25 Automatic transfer serial I/O operation ....................................................................... 1-33
26 SSTB1 output operation .................................................................................................... 1-34
27 SBUSY1 input operation (internal synchronous clock) ................................................... 1-34
28 S BUSY1 input operation (external synchronous clock) .................................................. 1-34
29 SBUSY1 output operation (internal synchronous clock, 8-bits serial I/O) ................... 1-35
30 SBUSY1 output operation (external synchronous clock, 8-bits serial I/O) .................. 1-35
31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous
clock, SBUSY1 output function outputs each 1-byte) ................................................... 1-35
32 SRDY1 output operation .................................................................................................... 1-36
33 SRDY1 input operation (internal synchronous clock) .................................................... 1-36
34 Handshake operation at serial I/O1 mutual connecting (1) ...................................... 1-37
35 Handshake operation at serial I/O1 mutual connecting (2) ...................................... 1-37
36 Block diagram of clock snchronous serial I/O2 ......................................................... 1-38
37 Operation of clock synchronous serial I/O2 function ................................................ 1-38
38 Block diagram of UART serial I/O2 ............................................................................. 1-39
39 Operation of UART serial I/O2 function ...................................................................... 1-39
40 Structure of serial I/O2 related register ...................................................................... 1-41
41 Block diagram of serial I/O3 ......................................................................................... 1-42
42 Structure of serial I/O3 control register ....................................................................... 1-42
43 Timing of serial I/O3 (LSB first) ................................................................................... 1-43
44 Block diagram for FLD control circuit .......................................................................... 1-45
45 Structure of FLDC related registers (1) ...................................................................... 1-46
46 Structure of FLDC related registers (2) ...................................................................... 1-47
38B7 Group User’s Manual
i
List of figures
Fig. 47 Structure of FLDC related registers (3) ...................................................................... 1-48
Fig. 48 Structure of FLDC related registers (4) ...................................................................... 1-49
Fig. 49 Segment/Digit setting example ..................................................................................... 1-50
Fig. 50 FLD automatic display RAM assignment .................................................................... 1-51
Fig. 51 Example of using FLD automatic display RAM in 16-timing•ordinary mode ......... 1-52
Fig. 52 Example of using FLD automatic display RAM in 16-timing•gradation display mode
........................................................................................................................................................ 1-53
Fig. 53 Example of using FLD automatic display RAM in 32-timing mode ......................... 1-54
Fig. 54 FLD and digit output timing .......................................................................................... 1-55
Fig. 55 Timing using digit interrupt ........................................................................................... 1-56
Fig. 56 Timing using FLD blanking interrupt ............................................................................ 1-57
Fig. 57 P64 to P67 FLD output pulses ...................................................................................... 1-58
Fig. 58 Toff section generating/nothing function ..................................................................... 1-59
Fig. 59 Digit pulses output function .......................................................................................... 1-60
Fig. 60 Structure of AD/DA control register ............................................................................. 1-61
Fig. 61 Black diagram of A-D converter ................................................................................... 1-61
Fig. 62 Black diagram of D-A converter ................................................................................... 1-62
Fig. 63 Equivalent connection circuit of D-A converter .......................................................... 1-62
Fig. 64 PWM block diagram ....................................................................................................... 1-63
Fig. 65 PWM timing ..................................................................................................................... 1-64
Fig. 66 Structure of PWM control register ............................................................................... 1-65
Fig. 67 14-bit PWM timing .......................................................................................................... 1-65
Fig. 68 Interrupt interval determination circuit block diagram ............................................... 1-66
Fig. 69 Structure of itnerrupt interval determination control register .................................... 1-67
Fig. 70 Interrupt inteval determination operation example (at rising edge active) ............. 1-67
Fig. 71 Interrupt interval determination operation example (at both-sided edge active) ... 1-67
Fig. 72 Block diagram of watchdog timer ................................................................................. 1-68
Fig. 73 Structure of watchdog timer control register .............................................................. 1-68
Fig. 74 Block diagram of buzzer output circuit ........................................................................ 1-69
Fig. 75 Structure of buzzer output control register ................................................................ 1-69
Fig. 76 Reset circuit example .................................................................................................... 1-70
Fig. 77 Reset sequence .............................................................................................................. 1-70
Fig. 78 Internal status at reset .................................................................................................. 1-71
Fig. 79 Ceramic resonator circuit .............................................................................................. 1-72
Fig. 80 External clock input circuit ............................................................................................ 1-72
Fig. 81 Clock generating circuit block diagram ....................................................................... 1-73
Fig. 82 State transitions of system clock ................................................................................. 1-74
Fig. 83 Digit timing waveform (1) .............................................................................................. 1-76
Fig. 84 Digit timing waveform (2) .............................................................................................. 1-77
Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode ........ 1-80
Fig. 86 Read timong .................................................................................................................... 1-81
Fig. 87 Timings during reading .................................................................................................. 1-82
Fig. 88 Input/output timings during programming (Verify data is output at the same timing as
for read.) ......................................................................................................................... 1-83
Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for
read.)................................................................................................................................ 1-84
Fig. 90 Programming/Erasing algorithm flow chart ................................................................. 1-86
Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode .......................... 1-88
Fig. 92 Timings during reading .................................................................................................. 1-90
Fig. 93 Timings during programming ......................................................................................... 1-91
Fig. 94 Timings during program verify ...................................................................................... 1-91
Fig. 95 Timings at erasing .......................................................................................................... 1-92
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38B7 Group User’s Manual
List of figures
Fig.
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96 Timings during erase verify........................................................................................... 1-92
97 Timings at error checking .............................................................................................. 1-93
98 Flash memory control register bit configuration ......................................................... 1-95
99 Flash command register bit configuration ................................................................... 1-96
100 CPU mode register bit configuration in CPU rewriting mode ................................ 1-96
101 Flowchart of program/erase operation at CPU reprogramming mode .................. 1-98
CHAPTER 2 APPLICATION
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2.1.1 Memory assignment of I/O port relevant registers .................................................. 2-2
2.1.2 Structure of port Pi (i = 0 to 7, 9, A) ....................................................................... 2-3
2.1.3 Structure of port P8 ..................................................................................................... 2-3
2.1.4 Structure of port PB..................................................................................................... 2-4
2.1.5 Structure of port Pi (i = 1, 3 to 7, 9, A) direction register .................................... 2-4
2.1.6 Structure of port P8 direction register ...................................................................... 2-5
2.1.7 Structure of port PB direction register ...................................................................... 2-5
2.1.8 Structure of pull-up control register 1 ....................................................................... 2-6
2.1.9 Structure of pull-up control register 2 ....................................................................... 2-6
2.1.10 Structure of pull-up control register 3 ..................................................................... 2-7
2.2.1 Memory map of registers relevant to timers .......................................................... 2-11
2.2.2 Structure of Timer i (i=1, 3 to 6) ............................................................................. 2-12
2.2.3 Structure of Timer 2 .................................................................................................. 2-12
2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-12
2.2.5 Structure of Timer 12 mode register ....................................................................... 2-13
2.2.6 Structure of Timer 34 mode register ....................................................................... 2-13
2.2.7 Structure of Timer 56 mode register ....................................................................... 2-14
2.2.8 Structure of Timer X (low-order, high-order) .......................................................... 2-15
2.2.9 Structure of Timer X mode register 1 ..................................................................... 2-16
2.2.10 Structure of Timer X mode register 2 ................................................................... 2-17
2.2.11 Structure of Interrupt request register 1 ............................................................... 2-18
2.2.12 Structure of Interrupt request register 2 ............................................................... 2-19
2.2.13 Structure of Interrupt control register 1 ................................................................ 2-20
2.2.14 Structure of Interrupt control register 2 ................................................................ 2-20
2.2.15 Timers connection and setting of division ratios ................................................. 2-22
2.2.16 Relevant registers setting ....................................................................................... 2-23
2.2.17 Control procedure..................................................................................................... 2-24
2.2.18 Peripheral circuit example ....................................................................................... 2-25
2.2.19 Timers connection and setting of division ratios ................................................. 2-25
2.2.20 Relevant registers setting ....................................................................................... 2-26
2.2.21 Control procedure..................................................................................................... 2-26
2.2.22 Judgment method of valid/invalid of input pulses ............................................... 2-27
2.2.23 Relevant registers setting ....................................................................................... 2-28
2.2.24 Control procedure..................................................................................................... 2-29
2.2.25 Timers connection and setting of division ratios ................................................. 2-30
2.2.26 Relevant registers setting ....................................................................................... 2-31
2.2.27 Control procedure..................................................................................................... 2-32
2.2.28 Timers connection and table example of timer X/RTP setting values ............. 2-34
2.2.29 RTP output example ................................................................................................ 2-34
2.2.30 Relevant registers setting ....................................................................................... 2-35
2.2.31 Control procedure..................................................................................................... 2-36
38B7 Group User’s Manual
iii
List of figures
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iv
2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-37
2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-38
2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-39
2.3.4 Structure of Serial I/O1 control register 2 .............................................................. 2-40
2.3.5 Structure of Serial I/O1 register/Transfer counter ................................................. 2-41
2.3.6 Structure of Serial I/O1 control register 3 .............................................................. 2-42
2.3.7 Structure of Baud rate generator ............................................................................. 2-43
2.3.8 Structure of UART control register .......................................................................... 2-43
2.3.9 Structure of Serial I/O2 control register.................................................................. 2-44
2.3.10 Structure of Serial I/O2 status register ................................................................. 2-45
2.3.11 Structure of Serial I/O2 transmit/receive buffer register ..................................... 2-45
2.3.12 Structure of Serial I/O3 control register ................................................................ 2-46
2.3.13 Structure of Serial I/O3 register ............................................................................. 2-46
2.3.14 Structure of Interrupt source switch register ........................................................ 2-47
2.3.15 Structure of Interrupt request register 1 ............................................................... 2-47
2.3.16 Structure of Interrupt request register 2 ............................................................... 2-48
2.3.17 Structure of Interrupt control register 1 ................................................................ 2-49
2.3.18 Structure of Interrupt control register 2 ................................................................ 2-49
2.3.19 Serial I/O1 connection examples (1) ..................................................................... 2-50
2.3.20 Serial I/O1 connection examples (2) ..................................................................... 2-51
2.3.21 Serial I/O1’s modes ................................................................................................. 2-52
2.3.22 Connection diagram ................................................................................................. 2-53
2.3.23 Timing chart .............................................................................................................. 2-53
2.3.24 Registers setting relevant to transmission side ................................................... 2-54
2.3.25 Setting of transmission data ................................................................................... 2-54
2.3.26 Control procedure..................................................................................................... 2-55
2.3.27 Connection diagram ................................................................................................. 2-56
2.3.28 Timing chart of serial data transmission/reception .............................................. 2-56
2.3.29 Relevant registers setting ....................................................................................... 2-57
2.3.30 Control procedure..................................................................................................... 2-58
2.3.31 Serial I/O2 connection examples (1) ..................................................................... 2-59
2.3.32 Serial I/O2 connection examples (2) ..................................................................... 2-60
2.3.33 Serial I/O2’s modes ................................................................................................. 2-61
2.3.34 Serial I/O2 transfer data format ............................................................................. 2-61
2.3.35 Connection diagram ................................................................................................. 2-62
2.3.36 Timing chart .............................................................................................................. 2-62
2.3.37 Registers setting relevant to transmission side ................................................... 2-63
2.3.38 Registers setting relevant to reception side......................................................... 2-64
2.3.39 Control procedure of transmission side ................................................................ 2-65
2.3.40 Control procedure of reception side ...................................................................... 2-66
2.3.41 Connection diagram ................................................................................................. 2-67
2.3.42 Timing chart .............................................................................................................. 2-67
2.3.43 Relevant registers setting ....................................................................................... 2-68
2.3.44 Setting of transmission data ................................................................................... 2-68
2.3.45 Control procedure..................................................................................................... 2-69
2.3.46 Connection diagram ................................................................................................. 2-70
2.3.47 Timing chart .............................................................................................................. 2-71
2.3.48 Relevant registers setting in master unit .............................................................. 2-71
2.3.49 Relevant registers setting in slave unit ................................................................ 2-72
2.3.50 Control procedure of master unit ........................................................................... 2-73
2.3.51 Control procedure of slave unit ............................................................................. 2-74
2.3.52 Connection diagram ................................................................................................. 2-75
38B7 Group User’s Manual
List of figures
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2.3.53 Timing chart .............................................................................................................. 2-75
2.3.54 Registers setting relevant to transmission side ................................................... 2-77
2.3.55 Registers setting relevant to reception side......................................................... 2-78
2.3.56 Control procedure of transmission side ................................................................ 2-79
2.3.57 Control procedure of reception side ...................................................................... 2-80
2.3.58 Serial I/O3 connection examples (1) ..................................................................... 2-81
2.3.59 Serial I/O3 connection examples (2) ..................................................................... 2-82
2.3.60 Serial I/O3’s modes ................................................................................................. 2-83
2.3.61 Connection diagram ................................................................................................. 2-84
2.3.62 Timing chart .............................................................................................................. 2-84
2.3.63 Registers setting relevant to transmission side ................................................... 2-85
2.3.64 Setting of transmission data ................................................................................... 2-85
2.3.65 Control procedure..................................................................................................... 2-86
2.3.66 Sequence of setting serial I/O2 control register again ....................................... 2-90
2.4.1 Memory assignment of FLD controller relevant registers ..................................... 2-92
2.4.2 Structure of Port P0 digit output set switch register ............................................ 2-93
2.4.3 Structure of Port P2 digit output set switch register ............................................ 2-93
2.4.4 Structure of FLDC mode register............................................................................. 2-94
2.4.5 Structure of Tdisp time set register ......................................................................... 2-95
2.4.6 Structure of Toff1 time set register ......................................................................... 2-96
2.4.7 Structure of Toff2 time set register ......................................................................... 2-96
2.4.8 Structure of FLD data pointer/FLD data pointer reload register ......................... 2-97
2.4.9 Structure of port P4FLD/port switch register.......................................................... 2-97
2.4.10 Structure of port P5FLD/port switch register ....................................................... 2-98
2.4.11 Structure of port P6FLD/port switch register ....................................................... 2-98
2.4.12 Structure of FLD output control register ............................................................... 2-99
2.4.13 Structure of Interrupt request register 2 ............................................................. 2-100
2.4.14 Structure of Interrupt control register 2 .............................................................. 2-100
2.4.15 Connection diagram ............................................................................................... 2-101
2.4.16 Timing chart of key-scan using FLD automatic display mode and segments
................................................................................................................................. 2-101
2.4.17 Enlarged view of FLD0 (P20) to FLD7 (P2 7) Tscan ........................................... 2-101
2.4.18 Setting of relevant registers ................................................................................. 2-102
2.4.19 FLD digit allocation example ................................................................................ 2-105
2.4.20 Control procedure................................................................................................... 2-106
2.4.21 Connection diagram ............................................................................................... 2-108
2.4.22 Timing chart of key-scan using FLD automatic display mode and digits ...... 2-109
2.4.23 Setting of relevant registers ................................................................................. 2-110
2.4.24 FLD digit allocation example ................................................................................ 2-113
2.4.25 Control procedure................................................................................................... 2-114
2.4.26 Connection diagram ............................................................................................... 2-116
2.4.27 Timing chart of FLD display by software ........................................................... 2-116
2.4.28 Enlarged view of P20 to P27 key-scan ................................................................ 2-116
2.4.29 Setting of relevant registers ................................................................................. 2-117
2.4.30 FLD digit allocation example ................................................................................ 2-118
2.4.31 Control procedure................................................................................................... 2-119
2.4.32 Connection diagram ............................................................................................... 2-120
2.4.33 Timing chart of 38B7 Group and M35501FP ..................................................... 2-121
2.4.34 Timing chart (enlarged view) of digit and segment output .............................. 2-121
2.4.35 Setting of relevant registers ................................................................................. 2-122
2.4.36 FLD digit allocation example ................................................................................ 2-125
2.4.37 Control procedure................................................................................................... 2-125
2.4.38 Connection diagram ............................................................................................... 2-126
38B7 Group User’s Manual
v
List of figures
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vi
2.4.39 Timing chart (at correct state) of 38B7 Group and M35501FP ...................... 2-127
2.4.40 Timing chart (at incorrect state) of 38B7 Group and M35501FP ................... 2-127
2.4.41 Setting of relevant registers ................................................................................. 2-128
2.4.42 Control procedure................................................................................................... 2-130
2.5.1 Memory assignment of A-D converter relevant registers ................................... 2-133
2.5.2 Structure of AD/DA control register ....................................................................... 2-134
2.5.3 Structure of A-D conversion register (low-order) ................................................. 2-135
2.5.4 Structure of A-D conversion register (high-order) ............................................... 2-135
2.5.5 Structure of Interrupt source switch register ........................................................ 2-136
2.5.6 Structure of Interrupt request register 2 ............................................................... 2-136
2.5.7 Structure of Interrupt control register 2 ................................................................ 2-137
2.5.8 Connection diagram ................................................................................................. 2-138
2.5.9 Setting of relevant registers ................................................................................... 2-138
2.5.10 Control procedure................................................................................................... 2-139
2.6.1 Memory assignment of D-A converter relevant registers ................................... 2-141
2.6.2 Structure of D-A conversion register ..................................................................... 2-141
2.6.3 Structure of AD/DA control register ....................................................................... 2-142
2.6.4 Connection diagram ................................................................................................. 2-143
2.6.5 Setting of relevant registers ................................................................................... 2-143
2.6.6 Control procedure ..................................................................................................... 2-144
2.7.1 Memory assignment of PWM relevant registers .................................................. 2-145
2.7.2 Structure of PWM control register ......................................................................... 2-145
2.7.3 Structure of PWM register (high-order) ................................................................. 2-146
2.7.4 Structure of PWM register (low-order) .................................................................. 2-146
2.7.5 Connection diagram ................................................................................................. 2-147
2.7.6 Setting of relevant registers ................................................................................... 2-147
2.7.7 Control procedure ..................................................................................................... 2-148
2.7.8 PWM0 output ............................................................................................................. 2-148
2.8.1 Memory assignment of interrupt interval determination function relevant registers
................................................................................................................................... 2-149
2.8.2 Structure of Interrupt interval determination register .......................................... 2-149
2.8.3 Structure of Interrupt interval determination control register ............................. 2-150
2.8.4 Structure of Interrupt edge selection register ...................................................... 2-150
2.8.5 Structure of Interrupt request register 1 ............................................................... 2-151
2.8.6 Structure of Interrupt control register 1 ................................................................ 2-152
2.8.7 Connection diagram ................................................................................................. 2-153
2.8.8 Function block diagram ........................................................................................... 2-153
2.8.9 Timing chart of data determination ........................................................................ 2-153
2.8.10 Setting of relevant registers ................................................................................. 2-154
2.8.11 Control procedure................................................................................................... 2-155
2.8.12 Reception of remote-control data (timer 2 interrupt) ........................................ 2-156
2.9.1 Memory assignment of watchdog timer relevant register ................................... 2-157
2.9.2 Structure of Watchdog timer control register ....................................................... 2-157
2.9.3 Structure of CPU mode register ............................................................................ 2-158
2.9.4 Connection of watchdog timer and setting of division ratio ............................... 2-159
2.9.5 Setting of relevant registers ................................................................................... 2-159
2.9.6 Control procedure ..................................................................................................... 2-160
2.10.1 Memory assignment of buzzer output circuit relevant register ........................ 2-161
2.10.2 Structure of buzzer output control register......................................................... 2-161
2.10.3 Connection of buzzer output circuit and setting of division ratio.................... 2-162
2.10.4 Setting of relevant register ................................................................................... 2-162
2.10.5 Control procedure................................................................................................... 2-162
38B7 Group User’s Manual
List of figures
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2.11.1 Example of power-on reset circuit ....................................................................... 2-163
2.11.2 RAM backup system example .............................................................................. 2-163
2.12.1 Structure of CPU mode register .......................................................................... 2-165
2.12.2 Connection diagram ............................................................................................... 2-166
2.12.3 Status transition diagram during power failure .................................................. 2-166
2.12.4 Setting of relevant registers ................................................................................. 2-167
2.12.5 Control procedure ................................................................................................... 2-168
2.12.6 Structure of clock counter ..................................................................................... 2-169
2.12.7 Initial setting of relevant registers ....................................................................... 2-170
2.12.8 Setting of relevant registers after detecting power failure ............................... 2-171
2.12.9 Control procedure ................................................................................................... 2-172
2.13.1 Memory map of flash memory version for 38B7 Group ................................... 2-174
2.13.2 Memory map of registers relevant to flash memory ......................................... 2-175
2.13.3 Structure of Flash memory control register ........................................................ 2-175
2.13.4 Structure of Flash command register .................................................................. 2-176
2.13.5 Structure of CPU mode register .......................................................................... 2-176
2.13.6 Reprogramming example of built-in flash memory by serial I/O mode .......... 2-179
2.13.7 Processing example of pins on board in serial I/O mode (1) ......................... 2-180
2.13.8 Processing example of pins on board in serial I/O mode (2) ......................... 2-180
2.13.9 Processing example of pins on board in serial I/O mode (3) ......................... 2-181
2.13.10 Example for reprogramming system of built-in flash memory by CPU reprogramming
mode ....................................................................................................................... 2-182
2.13.11 CPU reprogramming control program example (1) ......................................... 2-183
2.13.12 CPU reprogramming control program example (2) ......................................... 2-184
2.13.13 CPU reprogramming control program example (3) ......................................... 2-185
2.13.14 CPU reprogramming control program example (4) ......................................... 2-186
2.13.15 V PP control circuit example (1) ........................................................................... 2-187
2.13.16 V PP control circuit example (2) ........................................................................... 2-187
CHAPTER 3 APPENDIX
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3.1.1
3.1.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
Circuit for measuring output switching characteristics ............................................ 3-8
Timing diagram ............................................................................................................. 3-9
Power source current standard characteristics ...................................................... 3-10
Power source current standard characteristics (in wait mode) ........................... 3-10
High-breakdown P-channel open-drain output port characteristics (25 °C) ....... 3-11
High-breakdown P-channel open-drain output port characteristics (90 °C) ....... 3-11
CMOS output port P-channel side characteristics (25 °C) .................................. 3-12
CMOS output port P-channel side characteristics (90 °C) .................................. 3-12
CMOS output port N-channel side characteristics (25 °C) .................................. 3-13
CMOS output port N-channel side characteristics (90 °C) .................................. 3-13
A-D conversion standard characteristics ................................................................. 3-14
Setting procedure of relevant registers ................................................................... 3-15
Sequence of check of interrupt request bit ............................................................ 3-16
Structure of interrupt control register 2 .................................................................. 3-16
Sequence of setting serial I/O2 control register again ......................................... 3-20
PWM 0 output ............................................................................................................... 3-22
Initialization of processor status register ................................................................ 3-24
Sequence of PLP instruction execution .................................................................. 3-24
Stack memory contents after PHP instruction execution ..................................... 3-24
Status flag at decimal calculations .......................................................................... 3-25
38B7 Group User’s Manual
vii
List of figures
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viii
3.4.1 Wiring for the RESET pin ......................................................................................... 3-28
3.4.2 Wiring for clock I/O pins ........................................................................................... 3-29
3.4.3 Wiring for CNVss pin ................................................................................................. 3-29
3.4.4 Wiring for the VPP pin of the flash memory version .............................................. 3-30
3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-30
3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-31
3.4.7 Wiring for a large current signal line ...................................................................... 3-32
3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-32
3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-33
3.4.10 Setup for I/O ports ................................................................................................... 3-33
3.4.11 Watchdog timer by software ................................................................................... 3-34
3.5.1 Structure of Port Pi (i =0–7, 9, A)........................................................................... 3-35
3.5.2 Structure of Port P8................................................................................................... 3-35
3.5.3 Structure of Port PB .................................................................................................. 3-36
3.5.4 Structure of Port Pi direction register (i = 1, 3–7, 9, A) ...................................... 3-36
3.5.5 Structure of Port P8 direction register .................................................................... 3-37
3.5.6 Structure of Port PB direction register .................................................................... 3-37
3.5.7 Structure of Serial I/O1 automatic transfer data pointer ...................................... 3-38
3.5.8 Structure of Serial I/O1 control register 1 .............................................................. 3-38
3.5.9 Structure of Serial I/O1 control register 2 .............................................................. 3-39
3.5.10 Structure of Serial I/O1 register/Transfer counter ............................................... 3-40
3.5.11 Structure of Serial I/O1 control register 3 ............................................................ 3-41
3.5.12 Structure of Serial I/O2 control register ................................................................ 3-42
3.5.13 Structure of Serial I/O2 status register ................................................................. 3-43
3.5.14 Structure of Serial I/O2 transmit/receive buffer register ..................................... 3-43
3.5.15 Structure of Timer i ................................................................................................. 3-44
3.5.16 Structure of Timer 2 ................................................................................................ 3-44
3.5.17 Structure of PWM control register ......................................................................... 3-44
3.5.18 Structure of Timer 6 PWM register ....................................................................... 3-45
3.5.19 Structure of Timer 12 mode register ..................................................................... 3-45
3.5.20 Structure of Timer 34 mode register ..................................................................... 3-46
3.5.21 Structure of Timer 56 mode register ..................................................................... 3-46
3.5.22 Structure of D-A conversion register ..................................................................... 3-47
3.5.23 Structure of Timer X (low-order, high-order) ........................................................ 3-47
3.5.24 Structure of Timer X mode register 1 ................................................................... 3-48
3.5.25 Structure of Timer X mode register 2 ................................................................... 3-49
3.5.26 Structure of Interrupt interval determination register .......................................... 3-49
3.5.27 Structure of Interrupt interval determination control register ............................. 3-50
3.5.28 Structure of AD/DA control register ....................................................................... 3-51
3.5.29 Structure of A-D conversion register (low-order) ................................................. 3-51
3.5.30 Structure of A-D conversion register (high-order) ............................................... 3-52
3.5.31 Structure of PWM register (high-order)................................................................. 3-52
3.5.32 Structure of PWM register (low-order) .................................................................. 3-53
3.5.33 Structure of Baud rate generator ........................................................................... 3-53
3.5.34 Structure of UART control register ........................................................................ 3-54
3.5.35 Structure of Interrupt source switch register ........................................................ 3-55
3.5.36 Structure of Interrupt edge selection register ...................................................... 3-56
3.5.37 Structure of CPU mode register ............................................................................ 3-57
3.5.38 Structure of Interrupt request register 1 ............................................................... 3-58
3.5.39 Structure of Interrupt request register 2 ............................................................... 3-59
3.5.40 Structure of Interrupt control register 1 ................................................................ 3-60
3.5.41 Structure of Interrupt control register 2 ................................................................ 3-61
3.5.42 Structure of Serial I/O3 control register ................................................................ 3-62
38B7 Group User’s Manual
List of figures
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3.5.43 Structure of Serial I/O3 register ............................................................................. 3-62
3.5.44 Structure of Watchdog timer control register ....................................................... 3-63
3.5.45 Structure of Pull-up control register 3................................................................... 3-63
3.5.46 Structure of Pull-up control register 1................................................................... 3-64
3.5.47 Structure of Pull-up control register 2................................................................... 3-64
3.5.48 Structure of Port P0 digit output set switch register .......................................... 3-65
3.5.49 Structure of Port P2 digit output set switch register .......................................... 3-65
3.5.50 Structure of FLDC mode register .......................................................................... 3-66
3.5.51 Structure of Tdisp time set register ...................................................................... 3-67
3.5.52 Structure of Toff1 time set register ....................................................................... 3-68
3.5.53 Structure of Toff2 time set register ....................................................................... 3-68
3.5.54 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-69
3.5.55 Structure of Port P4FLD/port switch register ....................................................... 3-69
3.5.56 Structure of Port P5FLD/port switch register ....................................................... 3-70
3.5.57 Structure of Port P6FLD/port switch register ....................................................... 3-70
3.5.58 Structure of FLD output control register ............................................................... 3-71
3.5.59 Structure of Buzzer output control register .......................................................... 3-72
3.5.60 Structure of Flash memory control register .......................................................... 3-73
3.5.61 Structure of Flash command register .................................................................... 3-74
3.9.1 Pin configuration of M35501FP ................................................................................ 3-88
3.9.2 Functional block diagram .......................................................................................... 3-89
3.9.3 Port block diagram ..................................................................................................... 3-90
3.9.4 Digit setting ................................................................................................................. 3-91
3.9.5 16-digit mode output waveform ................................................................................ 3-92
3.9.6 Optional digit mode output waveform...................................................................... 3-92
3.9.7 Cascade mode connection example: 17 digits or more selected ....................... 3-93
3.9.8 Cascade mode output waveform .............................................................................. 3-93
3.9.9 Connection example with 38B7 Group microcomputer (1 to 16 digits) ............. 3-94
3.9.10 Connection example with 38B7 Group microccomputer (17 to 32 digits) ....... 3-94
3.9.11 Digit output waveform when reset signal is input ............................................... 3-95
3.9.12 Power-on reset circuit .............................................................................................. 3-96
3.9.13 Timing diagram ......................................................................................................... 3-99
38B7 Group User’s Manual
ix
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description (1) ........................................................................................................... 1-5
2 Pin description (2) ........................................................................................................... 1-6
3 List of supported products ............................................................................................. 1-8
4 Push and pop instructions of accumulator or processor status register ............... 1-10
5 Set and clear instructions of each bit of processor status register ....................... 1-11
6 List of I/O port functions (1) ........................................................................................ 1-16
7 List of I/O port functions (2) ........................................................................................ 1-17
8 Interrupt vector addresses and priority ...................................................................... 1-22
9 FLD controller specifications ........................................................................................ 1-44
10 Pins in FLD automatic display mode ........................................................................ 1-50
11 Relationship between low-order 6-bit data and setting period of ADD bit ......... 1-64
12 Pin assignments of M38B79FF when operating in the parallel input/output mode
..................................................................................................................................... 1-78
13 Assignment states of control input and each state ................................................ 1-78
14 Pin description (flash memory parallel I/O mode) .................................................. 1-79
15 Software command (parallel input/output mode) ..................................................... 1-81
16 DC ELECTRICAL CHARACTERISTICS (T a = 25 °C, V CC = 5 V ± 10 %, unless
otherwise noted) ......................................................................................................... 1-87
17 Read-only mode ........................................................................................................... 1-87
18 Read/Write mode ......................................................................................................... 1-87
19 Pin description (flash memory serial I/O mode) ..................................................... 1-89
20 Software command (serial I/O mode) ....................................................................... 1-90
21 AC Electrical characteristics ...................................................................................... 1-94
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-8
Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values
........................................................................................................................................................ 2-76
Table 2.3.2 SIO1CON3 (address 001C 16) setting example selecting internal synchronous clock
........................................................................................................................................................ 2-88
Table 2.3.3 SIO1CON3 (address 001C16) setting example selecting external synchronous clock
........................................................................................................................................................ 2-88
Table 2.4.1 FLD automatic display RAM map ....................................................................... 2-104
Table 2.4.2 FLD automatic display RAM map example ....................................................... 2-105
Table 2.4.3 FLD automatic display RAM map ....................................................................... 2-112
Table 2.4.4 FLD automatic display RAM map example ....................................................... 2-113
Table 2.4.5 FLD automatic display RAM map example ....................................................... 2-118
Table 2.4.6 FLD automatic display RAM map ....................................................................... 2-124
Table 2.11.1 Pin state during “L” state of RESET pin ......................................................... 2-164
Table 2.13.1 Setting of EPROM programmer when parallel programming ........................ 2-177
Table 2.13.2 Connection example to programmer when serial programming ................... 2-177
38B7 Group User’s Manual
i
List of tables
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2
Table 3.1.2 Recommended operating conditions
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ........................................ 3-2
Table 3.1.3 Recommended operating conditions
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ........................................ 3-3
Table 3.1.4 Electrical characteristics
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ........................................ 3-4
Table 3.1.5 Electrical characteristics
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) .................... 3-5
Table 3.1.6 A-D converter characteristics .................................................................................. 3-6
Table 3.1.7 D-A converter characteristics .................................................................................. 3-6
Table 3.1.8 Timing requirements (1) ........................................................................................... 3-7
Table 3.1.9 Switching characteristics .......................................................................................... 3-8
Table 3.3.1 SIO1CON3 (address 001C16) setting example selecting internal synchronous clock
........................................................................................................................................................ 3-19
Table 3.3.2 SIO1CON3 (address 001C16) setting example selecting external synchronous clock
........................................................................................................................................................ 3-19
Table 3.3.3 Pin state during “L” state of RESET pin ............................................................. 3-23
Table 3.9.1 Pin description ......................................................................................................... 3-89
Table 3.9.2 Absolute maximum ratings ..................................................................................... 3-97
Table 3.9.3 Recommended operating conditions (V CC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless
otherwise noted) ..................................................................................................... 3-97
Table 3.9.4 Recommended operating conditions (V CC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless
otherwise noted) ..................................................................................................... 3-97
Table 3.9.5 Electrical characteristics (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise
noted) ......................................................................................................................... 3-98
Table 3.9.6 Timing requirements (V CC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise
noted) ........................................................................................................................ 3-98
ii
38B7 Group User’s Manual
List of tables
MEMORANDUM
38B7 Group User’s Manual
iii
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USAGE
DATA REQUIRED FOR MASK ORDERS
HARDWARE
DESCRIPTION/FEATURES
DESCRIPTION
The 38B7 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38B7 group has six 8-bit timers, one 16-bit timer, a fluorescent
display automatic display circuit, 16-channel 10-bit A-D converter, a
serial I/O with automatic transfer function, which are available for
controlling musical instruments and household appliances.
FEATURES
<Microcomputer mode>
Basic machine-language instructions ....................................... 71
The minimum instruction execution time .......................... 0.48 µs
(at 4.2 MHz oscillation frequency)
Memory size
ROM ........................................................ 60K bytes
RAM ....................................................... 2048 bytes
Programmable input/output ports ............................................. 75
High-breakdown-voltage output ports ...................................... 52
Software pull-up resistors . (Ports P64 to P67, P7, P80 to P83, P9,
PA, PB)
Interrupts .................................................. 22 sources, 16 vectors
Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1
(max. 256-byte automatic transfer function)
Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1
Serial I/O3 (Clock-synchronized) ................................... 8-bit ✕ 1
PWM ............................................................................ 14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
A-D converter .............................................. 10-bit ✕ 16 channels
D-A converter ................................................................ 1 channel
Fluorescent display function ......................... Total 56 control pins
Interrupt interval determination function ..................................... 1
(Serviceable even in low-speed mode)
Watchdog timer ............................................................ 16-bit ✕ 1
Buzzer output ............................................................................. 1
Two clock generating circuits
Main clock (XIN–XOUT ) .......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) .......... Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.2 MHz oscillation frequency and high-speed selected)
In middle-speed mode ........................................... 2.7 to 5.5 V (*)
(at 4.2 MHz oscillation frequency and middle-speed selected)
In low-speed mode ................................................ 2.7 to 5.5 V (*)
(at 32 kHz oscillation frequency)
(*: 4.0 to 5.5 V for Flash memory version)
Power dissipation
In high-speed mode .......................................................... 35 mW
(at 4.2 MHz oscillation frequency)
In low-speed mode ............................................................. 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... –20 to 85 °C
•
•
•
•
•
•
<Flash memory mode>
●Supply voltage ................................................. VCC = 5 V ± 10 %
●Program/Erase voltage ............................... VPP = 11.7 to 12.6 V
●Programming method ...................... Programming in unit of byte
●Erasing method
Batch erasing ........................................ Parallel/Serial I/O mode
Block erasing .................................... CPU reprogramming mode
●Program/Erase control by software command
●Number of times for programming/erasing ............................ 100
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
1. The flash memory version cannot be used for application embedded in the MCU card.
2. Power source voltage Vcc of the flash memory version is 4.0
to 5.5 V.
APPLICATION
Musical instruments, VCR, household appliances, etc.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1-2
38B7 Group User’s Manual
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
C N VS S
RESET
P81/XCOUT
P80/XCIN
VS S
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
*P27/FLD7
*P26/FLD6
*P25/FLD5
*P24/FLD4
*P23/FLD3
*P22/FLD2
*P21/FLD1
*P20/FLD0
VEE
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/DA
AVSS
VREF
PA7/AN7
PA6/AN6
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
38B7 Group User’s Manual
55
54
53
52
51
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
M38B79MFH-XXXXFP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
Package type: 100P6S-A
*High-breakdown-voltage output port: Totaling 52
Fig. 1 Pin configuration of M38B79MFH-XXXXFP
1-3
1-4
Port P0(8)
8
Port P1(8)
8
Fig. 2 Functional block diagram
38B7 Group User’s Manual
8
Port P6(8)
8
Port P7(8)
(52 high-breakdown
voltage ports)
56 control pins
FLD display function
Buzzer output
PWM0(14-bit)
PWM1(8-bit)
Serial I/O3(Clock-synchronized)
Serial I/O2
(Clock-synchronized or UART)
Serial I/O1(Clock-synchronized)
(256 byte automatic transfer)
Serial I/Os
(10-bit ✕ 12 channel)
A-D converter
Build-in peripheral functions
I/O ports
FUNCTIONAL BLOCK DIAGRAM
4
Port P8(4)
Interrupt interval
determination function
Watchdog timer
CPU core
8
8
Port PA(8)
RAM
ROM
Me mo r y
XIN-XOUT
(main-clock)
XCIN-XCOUT
(sub-clock)
Timer X(16-bit)
Timer 1(8-bit)
Timer 2(8-bit)
Timer 3(8-bit)
Timer 4(8-bit)
Timer 5(8-bit)
Timer 6(8-bit)
Port P4(8)
8
System clock generation
Port P9(8)
Port P3(8)
8
Timers
Port P2(8)
8
7
Port PB(7)
Port P5(8)
8
HARDWARE
FUNCTIONAL BLOCK
HARDWARE
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
VCC, VSS
CNVSS
Power source
CNVSS
VEE
Pull-down
power source
Reference voltage
Analog power
VREF
AVSS
Function
Function except a port function
• Apply voltage of 4.0–5.5 V to VCC , and 0 V to VSS.
• Connect to VSS.
• VPP power input pin in flash memory mode.
• Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
• Reference voltage input pin for A-D converter.
• Analog power source input pin for A-D converter.
RESET
XIN
source
Reset input
Clock input
• Connect to VSS.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
XOUT
Clock output
P00/FLD8–
P07/FLD15
Output port P0
oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
• 8-bit output port.
• FLD automatic display
• High-breakdown-voltage P-channel open-drain output structure.
pins
• A pull-down resistor is built in between port P0 and the VEE pin.
______
P10/FLD16– I/O port P1
P17/FLD23
• At reset, this port is set to VEE level.
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P1 and the VEE pin.
• At reset, this port is set to VEE level.
P20/FLD0–
P27/FLD7
Output port P2
• FLD automatic display
pins
I/O port P3
• 8-bit output port with the same function as port P0.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P2 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P1.
P30/FLD24–
pins
P40/FLD32– I/O port P4
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P3 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P1.
P37/FLD31
P47/FLD39
P50/FLD40– I/O port P5
P57/FLD47
P60/FLD48– I/O port P6
P63/FLD51
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P4 and the VEE pin.
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P5 and the VEE pin.
• 4-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P6 and the VEE pin.
38B7 Group User’s Manual
• FLD automatic display
• FLD automatic display
pins
• FLD automatic display
pins
• FLD automatic display
pins
1-5
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2)
Pin
Name
Function
P64/RXD/FLD52 , I/O port P6
P65/TXD/FLD53 ,
P66/SCLK21/FLD54 ,
• 4-bit I/O port .
• Low-voltage input level for input ports.
• CMOS compatible input level for RxD, SCLK21, SCLK22.
P67/SRDY2/SCLK22/
FLD55,
P70/INT0,
I/O port P7
P71/INT1,
P72/INT2,
P73/INT3/DIMOUT,
• CMOS 3-state output structure.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Dimmer signal output pin
• PWM output pin
• Timer output pins
• Interrupt input pin
I/O port P8
P82/CNTR1,
P83/CNTR0/CNTR2
P90/SIN3/AN8,
I/O port P9
P91/SOUT3/AN9,
P92/SCLK3/AN10,
• 4-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 8-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• CMOS 3-state output structure.
P93/SRDY3/AN11,
P94/RTP1/AN12,
P95/RTP0/AN13
P96/PWM0/AN14
• Buzzer output pin
• I/O pins for sub-clock generating
circuit (connect a ceramic resonator
or a quarts-crystal oscillator)
• Timer input pin
• Timer I/O pin
• Serial I/O3 function pins
• A-D converter input pins
• Real time port output pins
• A-D converter input pins
• 14-bit PWM output pin
• A-D converter input pin
P97/BUZ02/AN15
PA0 /AN0–PA 7/AN7 I/O port PA
PB0/SCLK12/DA
• Interrupt input pins
• Interrupt input pin
P74/PWM1
P75/T1OUT,
P76/T3OUT,
P77/INT4/BUZ01
P80/XCIN,
P81/XCOUT
Function except a port function
• FLD automatic display
pins
• Serial I/O2 function pins
I/O port PB
• 8-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 7-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• Buzzer output pin
• A-D converter input pin
• A-D converter input pin
• Serial I/O1 function pin
• D-A converter output pin
• CMOS 3-state output structure.
PB1/SRDY1,
PB2/SBUSY1,
PB3/SSTB1,
PB4/SCLK11,
• Serial I/O1 function pins
PB5/SOUT1,
PB6/SIN1
1-6
38B7 Group User’s Manual
HARDWARE
PART NUMBERING
Product M38B7 9 M F H - AXXX FP
Package type
FP : 100P6S-A package
ROM number
Omitted in Flash memory version
ROM/Flash memory size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
38B7 Group User’s Manual
1-7
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 38B7 group as follows.
Memory Type
Support for Mask ROM and Flash memory versions.
Memory Size
Flash memory size ........................................................... 60K bytes
Mask ROM size ................................................................ 60K bytes
RAM size ......................................................................... 2048 bytes
Package
100P6S-A .................................. 0.65 mm-pitch plastic molded QFP
Mass product
ROM size (bytes)
60 K
M38B79FF
M38B79MFH
56 K
Mass product
52 K
48 K
44 K
40 K
36 K
32 K
28 K
24 K
20 K
16 K
12 K
8K
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Note : Products under development: the development schedule and specifications may be revised without notice.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
ROM size (bytes)
Product
ROM size for User ( )
M38B79MFH-XXXXFP
61440
(61310)
M38B79FFFP
1-8
As of Nov. 2001
RAM size (bytes)
Package
2048
100P6S-A
38B7 Group User’s Manual
Remarks
Mask ROM version
Flash memory version
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016 ”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls.
The 38B7 group uses the standard 740 Family instruction set. Refer to the table of 740 Series addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Series instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PC L. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
38B7 Group User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
POP return
address from stack
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
1-10
Push instruction to stack
Pop instruction from stack
PHA
PHP
PLA
PLP
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
SEC
CLC
Z flag
_
_
I flag
D flag
SEI
CLI
SED
CLD
38B7 Group User’s Manual
B flag
_
_
T flag
SET
CLT
V flag
_
N flag
_
CLV
_
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B 16.
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits
b1b0
0 0 : Single-chip mode
0 1:
1 0 : Not available
1 1:
Stack page selection bit
0 : Page 0
1 : Page 1
Not used (return “1” when read)
(Do not write “0” to this bit.)
Port XC switch bit
0 : I/O port function
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN) (high-speed mode)
1 : f(XIN)/4 (middle-speed mode)
Internal system clock selection bit
0 : XIN-XOUT selection (middle-/high-speed mode)
1 : XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
1-12
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Special Function Register (SFR) Area
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The special function register (SFR) area contains control registers
for I/O ports, timers and other functions.
Zero Page
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
Special Page
ROM
The special page addressing mode can be used to specify memory
addresses in the special page area. Access to this area with only 2
bytes is possible in the special page addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing programs.
RAM area
RAM size
(byte)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
000016
SFR area 1
RAM
Zero page
004016
010016
XXXX16
044016
ROM area
ROM size
(byte)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM
0E0016
0EDF16
0EE016
0EFF16
0F0016
0FFF16
YYYY16
Reserved area
Not used (Note)
RAM area for FLD automatic display
SFR area 2
RAM area for Serial I/O
automatic transfer
Reserved ROM area
(common ROM area,128 bytes)
ZZZZ16
FF0016
Special page
FFDC16
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
38B7 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Timer 1 (T1)
002116
Timer 2 (T2)
Port P1 (P1)
002216
Timer 3 (T3)
000316
Port P1 direction register (P1D)
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
Timer 5 (T5)
002516
Timer 6 (T6)
000116
000216
000516
000616
000716
Port P3 (P3)
002616
PWM control register (PWMCON)
Timer 6 PWM register (T6PWM)
Port P3 direction register (P3D)
002716
000816
Port P4 (P4)
002816
Timer 12 mode register (T12M)
000916
Port P4 direction register (P4D)
002916
Timer 34 mode register (T34M)
000A16
Port P5 (P5)
002A16
Timer 56 mode register (T56M)
000B16
Port P5 direction register (P5D)
002B16
D-A conversion register (DA)
000C16
Port P6 (P6)
002C16
Timer X (low-order) (TXL)
000D16
Port P6 direction register (P6D)
002D16
Timer X (high-order) (TXH)
000E16
Port P7 (P7)
002E16
Timer X mode register 1 (TXM1)
000F16
Port P7 direction register (P7D)
002F16
Timer X mode register 2 (TXM2)
001016
Port P8 (P8)
003016
Interrupt interval determination register (IID)
001116
Port P8 direction register (P8D)
003116
Interrupt interval determination control register (IIDCON)
001216
Port P9 (P9)
003216
AD/DA control register (ADCON)
001316
Port P9 direction register (P9D)
003316
A-D conversion register (low-order) (ADL)
001416
Port PA (PA)
003416
A-D conversion register (high-order) (ADH)
001516
Port PA direction register (PAD)
003516
PWM register (high-order) (PWMH)
001616
Port PB (PB)
003616
PWM register (low-order) (PWML)
001716
Port PB direction register (PBD)
003716
Baud rate generator (BRG)
001816
Serial I/O1 automatic transfer data pointer (SIO1DP)
003816
UART control register (UARTCON)
001916
Serial I/O1 control register 1 (SIO1CON1)
003916
Interrupt source switch register (IFR)
001A16
Serial I/O1 control register 2 (SIO1CON2)
003A16
Interrupt edge selection register (INTEDGE)
001B16
Serial I/O1 register/Transfer counter (SIO1)
003B16
CPU mode register (CPUM)
001C16
Serial I/O1 control register 3 (SIO1CON3)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 status register (SIO2STS)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
003F16
Interrupt control register 2(ICON2)
0EEC16
Serial I/O3 control register (SIO3CON)
0EF616
Toff1 time set register (TOFF1)
0EED16
Serial I/O3 register (SIO3)
0EF716
Toff2 time set register (TOFF2)
0EEE16
Watchdog timer control register (WDTCON)
0EF816
FLD data pointer (FLDDP)
0EEF16
Pull-up control register 3 (PULL3)
0EF916
Port P4 FLD/Port switch register (P4FPR)
0EF016
Pull-up control register 1 (PULL1)
0EFA16
Port P5 FLD/Port switch register (P5FPR)
0EF116
Pull-up control register 2 (PULL2)
0EFB16
Port P6 FLD/Port switch register (P6FPR)
0EF216
Port P0 digit output set switch register (P0DOR)
0EFC16 FLD output control register (FLDCON)
0EF316
Port P2 digit output set switch register (P2DOR)
0EFD16 Buzzer output control register (BUZCON)
0EF416
FLDC mode register (FLDM)
0EFE16
Flash memory control register (FCON)
(Note)
0EF516
Tdisp time set register (TDISP)
0EFF16
Flash command register (FCMD)
(Note)
Note: Flash memory version only.
Fig. 9 Memory map of special function register (SFR)
1-14
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
[Direction Registers] PiD
[High-Breakdown-Voltage Output Ports]
The 38B7 group has 75 programmable I/O pins arranged in ten individual I/O ports (P1, P3, P4, P5, P6, P7, P8, P9, PA and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port. When “0” is written to the bit corresponding to
a pin, that pin becomes an input pin. When “1” is written to that
pin, that pin becomes an output pin. If data is read from a pin set
to output, the value of the port output latch is read, not the value of
the pin itself. Pins set to input (the bit corresponding to that pin
must be set to “0”) are floating and the value of that pin can be
read. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
b7
The 38B7 group has seven ports with high-breakdown-voltage
pins (ports P0 to P5 and P60 –P63). The high-breakdown-voltage
ports have P-channel open-drain output with Vcc – 45 V of breakdown voltage. Each pin in ports P0 to P3 has an internal pull-down
resistor connected to VEE. At reset, the P-channel output transistor of each port latch is turned off, so that it goes to VEE level (“L”)
by the pull-down resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register
(address 0EF416 ) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode
register is set to “0” (strong drivability).
[Pull-up Control Register] PULL
Ports P6 4–P6 7, P7, P8 0–P8 3 , P9, PA and PB have built-in programmable pull-up resistors. The pull-up resistors are valid only in
the case that the each control bit is set to “1” and the corresponding port direction registers are set to input mode.
b7
b0
b0
Pull-up control register 2
(PULL2 : address 0EF116)
Pull-up control register 1
(PULL1 : address 0EF016)
P64, P65 pull-up control bit
P80, P81 pull-up control bit
P66, P67 pull-up control bit
P82, P83 pull-up control bit
P70, P71 pull-up control bit
P72, P73 pull-up control bit
0: No pull-up
1: Pull-up
P74, P75 pull-up control bit
P76, P77 pull-up control bit
Not used (returns “0” when read)
(Do not write “1”.)
Not used (returns “0” when read)
(Do not write “1”.)
P90, P91 pull-up control bit
P92, P93 pull-up control bit
P94, P95 pull-up control bit
P96, P97 pull-up control bit
Not used (returns “0” when read)
(Do not write “1”.)
0: No pull-up
1: Pull-up
b7
b0
Pull-up control register 3
(PULL3 : address 0EEF16)
PA0, PA1 pull-up control bit
PA2, PA3 pull-up control bit
PA4, PA5 pull-up control bit
PA6, PA7 pull-up control bit
PB0, PB1 pull-up control bit
0: No pull-up
1: Pull-up
PB2, PB3 pull-up control bit
PB4, PB5 pull-up control bit
PB6 pull-up control bit
Fig. 10 Structure of pull-up control registers (PULL1, PULL2 and PULL3)
38B7 Group User’s Manual
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
Table 6 List of I/O port functions (1)
Pin
P00/FLD 8–
P07/FLD 15
Nama
Port P0
Input/Output
Output
P10/FLD16–
P17/FLD 23
Port P1
Input/output,
individual
bits
P20/FLD 0–
P27 /FLD7
Port P2
Output
P30/FLD 24–
P37/FLD 31
Port P3
Input/output,
individual
bits
P40/FLD 32–
P47/FLD 39
Port P4
Input/output,
individual
bits
P50/FLD 40–
P57/FLD 47
Port P5
Input/output,
individual
bits
P60/FLD 48–
P63/FLD 51
Port P6
Input/output,
individual
bits
P64/RxD/
FLD 52
P65/TxD/
FLD53 ,
P66/S CLK21/
FLD 54
P67/S RDY2/
SCLK22/
FLD 55
P70/INT0 ,
P71/INT1
P72/INT2
I/O Format
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
(port input)
CMOS compatible input
level (RxD, SCLK21,
SCLK22)
CMOS 3-state output
Non-Port Function
FLD automatic display
function
FLD automatic display
function
Serial I/O2 function I/O
Port P7
Input/output,
individual
bits
CMOS compatible input
level
CMOS 3-state output
External interrput input
External interrput input
Dimmer signal output
P74 /PWM1
P75/T1 OUT
P76/T3 OUT
P77/INT4 /
BUZ01
PWM output
Timer output
Timer output
Buzzer output
External interrput input
1-16
Ref.No.
(1)
FLDC mode register
(2)
FLDC mode register
P2 digit output set switch
register
(1)
FLDC mode register
(2)
FLDC mode register
Port P4 FLD/Port switch
register
(2)
FLDC mode register
Port P5 FLD/Port switch
register
(2)
FLDC mode register
Port P6 FLD/Port switch
register
(2)
FLDC mode register
Serial I/O2 control
register
UART control register
(3)
(4)
(5)
P73/INT3 /
DIMOUT
P80/X CIN
P81/X COUT
P82 /CNTR1
P83 /CNTR0 /
CNTR2
Related SFRs
FLDC mode register
P0 digit output set switch
register
Port P8
Input/output,
individual
bits
CMOS compatible input
level
CMOS 3-state output
Sub-clock generating
circuit I/O
External count input
38B7 Group User’s Manual
Interrupt edge selection
register
Interrupt edge selection
register
Interrupt interval determination control register
Interrupt edge selection
register
FLD output control register
Timer 56 mode register
Timer 12 mode register
Timer 34 mode register
Buzzer output control
register
Interrupt edge selection
register
CPU mode register
Interrupt edge selection
register
(6)
(7)
(8)
(9)
(10)
(11)
(6)
(12)
HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 List of I/O port functions (2)
Pin
Nama
Input/Output
P90/S IN3/
Port P9
Input/output,
AN 8
individual
bits
P91/S OUT3/
AN 9,
P92/S CLK3/
AN 10
P93/S RDY3/
AN11
P94/RTP1/
AN 12,
P95/RTP0/
AN 13
P96/PWM0 /
AN 14
P97/B UZ02/
AN 15
PA0/AN 0–
Port PA
Input/output,
PA7/AN 7
individual
bits
PB 0/SCLK12/
DA
Port PB
Input/output,
individual
bits
I/O Format
CMOS compatible input
level
CMOS 3-state output
Non-Port Function
Serial I/O3 function I/O
A-D conversion input
Related SFRs
Serial I/O3 control
register
AD/DA control register
Ref.No.
(6)
(13)
(14)
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
Real time port output
A-D conversion input
Timer X mode register 2
AD/DA control register
(15)
PWM output
A-D conversion input
Buzzer output
A-D conversion input
A-D conversion input
PWM control register
AD/DA control register
Buzzer output control register
AD/DA control register
AD/DA control register
(16)
Serial I/O1 function I/O
D-A conversion output
Serial I/O1 control
registers 1, 2
AD/DA control register
Serial I/O1 control
registers 1, 2
(18)
Serial I/O1 function I/O
PB 1/SRDY1
PB 2/SBUSY1
PB 3/SSTB1
PB4 /SCLK11
PB 5/SOUT1
PB 6/SIN1
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
38B7 Group User’s Manual
(16)
(17)
(19)
(18)
(20)
(21)
(6)
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Ports P0, P2
(2) Ports P1, P3, P4, P5, P60 to P63
FLD/Port
switch register
Dimmer signal
(Note 1)
Local data
bus
Data bus
Output
✽
Port latch
P4, P5, P60 to P63
Dimmer signal
(Note 1)
Direction register
Local data
bus
✽
Port latch
Data bus
read
VEE
(Note 2)
VEE
(3) Port P64
(4) Ports P65, P66
Pull-up control
Dimmer signal
(Note 1)
P-channel output disable signal (P65)
Pull-up control
Output OFF control signal
FLD/Port
switch register
Dimmer signal
(Note 1)
FLD/Port
switch register
Direction register
Local data
bus
Serial I/O2 selection signal
Port latch
Data bus
Direction register
Local data
bus
Port latch
Data bus
RxD input
TxD or SCLK21 output
Serial clock input
P66
(5) Port P67
(6) Ports P70 to P72, P82, P90, PB6
Dimmer signal
(Note 1)
Pull-up control
Pull-up control
FLD/Port
switch register
Direction register
Local data
bus
Data bus
Direction register
Data bus
Port latch
Port latch
INT0, INT1, INT2 interrupt input
CNTR1 input
Serial I/O input
Serial ready output
SRDY2 output enable bit
Serial I/O2 enable bit
A-D conversion input
Analog input pin selection bit
Serial clock output
P90
Clock I/O pin selection bit
Synchronous clock
selection bit
Serial clock input
✽ High-breakdown-voltage P-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P4, P5 and P60 to P63.
Fig. 11 Port block diagram (1)
1-18
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(7) Port P73
(8) Ports P74 to P76
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Pull-up control
Dimmer output
control bit
Direction register
Direction register
Data bus
Pull-up control
Data bus
Port latch
Port latch
Dimmer signal output
Timer 1 output
Timer 3 output
Timer 6 output
INT3 interrupt input
(9) Port P77
(10) Port P80
Pull-up control
Pull-up control
Port Xc switch bit
Buzzer control signal
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Buzzer signal output
INT4 interrupt input
Sub-clock generating circuit input
(12) Port P83
(11) Port P81
Pull-up control
Port Xc switch bit
Pull-up control
Timer X operating mode bits
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator
Timer X output
Port P80
CNTR0, CNTR2 input
Port Xc switch bit
(13) Ports P91, P92
(14) Port P93
Pull-up control
P-channel output disable signal (P91)
Output OFF control signal
Pull-up control
SRDY3 output enable bit
Serial I/O3 selection signal
Direction register
Data bus
Direction register
Data bus
Port latch
Port latch
SOUT or SCLK
Serial ready output
Serial clock input
A-D conversion input
Analog input pin selection bits
P92
A-D conversion input
Analog input pin selection bits
Fig. 12 Port block diagram (2)
38B7 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
(16) Ports P96, P97
(15) Ports P94, P95
Pull-up control
Pull-up control
PWM output selection bit
Buzzer control signal
Real time port control bit
Direction register
Data bus
Direction register
Data bus
Port latch
Port latch
PWM output
Buzzer signal output
RTP output
A-D conversion input
A-D conversion input
Analog input pin selection bits
(17) Port PA
Analog input pin selection bits
(18) Ports PB0, PB2
Pull-up control
Pull-up control
Serial I/O1 selection signal
PB1/SRDY1•PB2/SBUSY1 pin
control bit
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
SCLK12 output
SBUSY1 output
Serial clock input
SBUSY1 input
A-D conversion input
Analog input pin selection bits
D-A converter output
D-A output enable bit
PB0
(20) Port PB3
(19) Port PB1
Pull-up control
Pull-up control
PB1/SRDY1•PB2/SBUSY1 pin
control bit
PB3/SSTB1 pin control bit
Direction register
Direction register
Data bus
Port latch
Data bus
SSTB1 output
Serial ready output
Serial ready input
(21) Ports PB4, PB5
Pull-up control
P-channel output disable signal (PB5)
Output OFF control signal
Serial I/O1 selection signal
Direction register
Data bus
Port latch
SOUT or SCLK
Serial clock input
PB4
Fig. 13 Port block diagram (3)
1-20
Port latch
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
Interrupts occur by twenty two sources: five external, sixteen internal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is
“0.” Interrupt enable bits can be set or cleared by software. Interrupt
request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occur at
the same time, the interrupt with highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the interrupt source switch register (address 003916).
1. INT1 or Serial I/O3
2. INT3 or Serial I/O2 transmit
3. INT4 or A-D conversion
■Note
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
•When switching interrupt sources of an interrupt vector address where
two or more interrupt sources are allocated
Related register: Interrupt source switch register (address 3916)
When not requiring the interrupt occurrence synchronized with these
setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) or the
interrupt (source) select/switch bit.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
1
2
High
FFFD16
FFFB16
INT1
3
FFF916
FFF816
Serial I/O3
INT2
4
FFF716
FFF616
Remote control/
counter overflow
Serial I/O1
Low
FFFC16
FFFA16
Interrupt Request
At reset
At detection of either rising or falling edge of
INT0 input
Non-maskable
External interrupt
(active edge selectable)
At detection of either rising or falling edge of
INT1 input
External interrupt
(active edge selectable)
Valid when INT1 interrupt is selected
Valid when serial I/O3 is selected
External interrupt
(active edge selectable)
At completion of data transfer
At detection of either rising or falling edge of
INT2 input
At 8-bit counter overflow
5
FFF516
FFF416
Serial I/O auto-
At completion of data transfer
At completion of the last data transfer
matic transfer
Timer X
Timer 1
Timer 2
Timer 3
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
Timer 4
Timer 5
Timer 6
Serial I/O2 receive
INT3
10
11
12
13
14
FFEB16
FFE916
FFE716
FFE516
FFE316
FFEA16
FFE816
FFE616
FFE416
FFE216
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At completion of serial I/O2 data receive
At detection of either rising or falling edge of
15
FFE116
FFE016
At completion of serial I/O2 data transmit
At detection of either rising or falling edge of
INT4 input
A-D conversion
FLD blanking
16
FFDF16
FFDE16
At completion of A-D conversion
At falling edge of the last timing immediately
before blanking period starts
FLD digit
At rising edge of digit (each timing)
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
1-22
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
mode is selected
Valid when serial I/O automatic
transfer mode is selected
INT3 input
Serial I/O2 transmit
INT4
Remarks
Generating Conditions
38B7 Group User’s Manual
STP release timer underflow
External interrupt
(active edge selectable)
Valid when INT3 interrupt is selected
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
Valid when A-D conversion is selected
Valid when FLD blanking
interrupt is selected
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0 Interrupt source switch register
(IFR : address 003916)
INT3/serial I/O2 transmit interrupt switch bit
0 : INT3 interrupt
1 : Serial I/O2 transmit interrupt
INT4/AD conversion interrupt switch bit
0 : INT4 interrupt
1 : A-D conversion interrupt
INT1/serial I/O3 interrupt switch bit
0 : INT1 interrupt
1 : Serial I/O3 interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
INT4 interrupt edge selection bit
Not used (return “0” when read)
CNTR0 pin edge switch bit
CNTR1 pin edge switch bit
b7
0 : Falling edge active
1 : Rising edge active
0 : Rising edge count
1 : Falling edge count
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O3 interrupt request bit
INT2 interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O1 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D16)
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
INT3/serial I/O2 transmit interrupt request bit
INT4 interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
b7
b0
0 : No interrupt request issued
1 : Interrupt request issued
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O3 interrupt enable bit
INT2 interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b0 Interrupt control register 2
(ICON2 : address 003F16)
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O2 receive interrupt enable bit
INT3/serial I/O2 transmit interrupt enable bit
INT4 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 15 Structure of interrupt related registers
38B7 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
8-Bit Timer
b7
b0
Timer 12 mode register
(T12M: address 002816)
The 38B7 group has six built-in 8-bit timers : Timer 1, Timer 2, Timer
3, Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016”, an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is set
to “1”.
The count can be stopped by setting the stop bit of each timer to “1”.
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
the timer internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P75/T1OUT pin. The
active edge of the external clock CNTR0 can be switched with the bit
6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0”, timer 1 is set to “FF16”, and timer 2
is set to “0116 ”.
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P75)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1
11 : Not available
Timer 3 output selection bit (P76)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P76/T3OUT pin. The
active edge of the external clock CNTR1 can be switched with the bit
7 of the interrupt edge selection register.
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P74/PWM1 pin.
b7
b0
Timer 56 mode register
(T56M: address 002A16)
●Timer 6 PWM1 Mode
Timer 6 can output a PWM rectangular waveform with “H” duty cycle
n/(n+m) from the P74/PWM1 pin by setting the timer 56 mode register (refer to Figure 18). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L”, if m is “0”, the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P74)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Fig. 16 Structure of timer related registers
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
XCIN
Timer 1 latch (8)
1/2
Timer 1 count source
“1”
“01” selection bits
Internal system clock
selection bit
Timer 1 (8)
1/8
XIN
“0”
FF16
“00”
1/16
“10”
RESET
STP instruction
Timer 1 interrupt request
Timer 1 count
stop bit
1/64
“11”
P75 latch
P75/T1OUT
1/2
Timer 1 output selection bit
Timer 2 latch (8)
“00”
Timer 2 count source
selection bits
0116
Timer 2 (8)
P75 direction register
“10”
CNTR0
P83/CNTR0/CNTR2
Timer 2 interrupt request
“01”
Timer 2 count
stop bit
Rising/Falling
active edge switch
CNTR2
Timer 3 latch (8)
“01”
“00”
P76/T3OUT
Timer 3 count source
selection bits
Timer 3 (8)
Timer 3 count
stop bit
“10”
P76 latch
Timer 3 interrupt request
“11”
1/2
Timer 3 output selection bit
Timer 4 latch (8)
“01”
P76 direction register
Timer 4 count source
selection bits
Timer 4 (8)
“00”
P82/CNTR1
Timer 4 interrupt request
Timer 4 count
stop bit
“10”
Rising/Falling
active edge switch
Timer 5 latch (8)
“1”
Timer 5 count source
selection bit
Timer 5 (8)
“0”
Timer 5 interrupt request
Timer 5 count
stop bit
Timer 6 latch (8)
“01”
Timer 6 count source
selection bits
Timer 6 (8)
“00”
Timer 6 interrupt request
Timer 6 count
stop bit
“10”
Timer 6 PWM register (8)
P74/PWM1
P74 latch
“1”
“0”
PWM
1/2
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P74 direction register
Fig. 17 Block diagram of timer
38B7 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
ts
Timer 6
count source
Timer 6 PWM
mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m) ✕ ts) is output.
n : setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
16-Bit Timer
■ Note
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled for the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
•Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Timer X
Timer X is a down-counter. When the timer reaches “000016”, an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues downcounting. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P94 and P95 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1”,
data are output independent of the timer X.) When the data for the
real time port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction registers to output mode.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR 2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR 2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR 2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR 2 active edge switch bit is “0”, the timer counts while the input
signal of the CNTR2 pin is at “H”. When it is “1”, the timer counts
while the input signal of the CNTR2 pin is at “L”. When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
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HARDWARE
FUNCTIONAL DESCRIPTION
Real time port
control bit “1”
Data bus
Q D
P94 data for real time port
P94
“0 ”
Latch
P94 direction
register
P94 latch
Real time port
control bit “1”
Q D
Real time port
control bit (P94) “0”
“0 ”
Latch
P95 direction
register
P95 latch
Real time port
control bit (P95) “0”
“1 ”
Timer X mode register
write signal
P95 data for real time port
P95
XCIN
1/2
“1 ”
Timer X mode register
write signal
Internal system clock
selection bit
1/2
Count source selection bit
1/8
“0 ”
1/64
Timer X stop
control bit
Timer X operating
XIN
Divider
“1”
CNTR2 active
edge switch bit
P83/CNTR0/CNTR2
Timer X write
control bit
mode bits
“0”
Timer X latch (low-order) (8) Timer X latch (high-order) (8)
“00”,“01”,“11”
Timer X (low-order) (8)
Timer X
interrupt request
Timer X (high-order) (8)
“10”
“1”
Pulse width
measurement mode
CNTR2 active
edge switch bit “0”
Pulse output mode
Q
P83 direction
register
“1”
S
T
Q
P83 latch
Pulse output mode
CNTR0
Fig. 19 Block diagram of timer X
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1 : address 002E16)
Timer X mode register 2
(TXM2 : address 002F16)
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0 0 : f(XIN)/2 or f(XCIN)/4
0 1 : f(XIN)/8 or f(XCIN)/16
1 0 : f(XIN)/64 or f(XCIN)/128
1 1 : Not available
Not used (returns “0” when read)
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR2 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Real time port control bit (P94)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P95)
0 : Real time port function is invalid
1 : Real time port function is valid
P94 data for real time port
P95 data for real time port
Not used (returns “0” when read)
Fig. 20 Structure of timer X related registers
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HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
Serial I/O1
0F0016 to 0FFF16 ).
The PB 1/SRDY1 , PB 2/SBUSY1 , and PB3/S STB1 pins each have a
handshake I/O signal function and can select either “H” active or
“L” active for active logic.
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
Main address
bus
Local address
bus
Serial I/O automatic
transfer RAM
(0F0016 to 0FFF16)
Main
Local
data bus data bus
Serial I/O1
automatic transfer
data pointer
Address decoder
Serial I/O1
automatic transfer
controller
XCIN
1/2
Serial I/O1
control register 3
Internal system
clock selection bit
“1 ”
PB3 latch
“0 ”
PB3/SSTB1
Divider
XIN
“0 ”
(PB3/SSTB1 pin control bit)
“1”
PB1/SRDY1•PB2/SBUSY1 PB2 latch
pin control bit
“0”
Internal synchronous
clock selection bits
Serial I/O1
synchronous clock
selection bit
PB2/SBUSY1
“1”
PB1/SRDY1•PB2/SBUSY1
PB1 latch
pin control bit
1/4
1/8
1/16
1/32
1/64
1/128
1/256
“0”
Synchronous
circuit
“1”
SCLK1
“0 ”
PB1/SRDY1
“1”
Serial I/O1 clock
pin selection bit
“0 ”
“1”
Serial transfer
status flag
Serial I/O1
interrupt request
PB4 latch
“0 ”
PB4/SCLK11
“0 ”
“1”
“1 ”
Serial I/O1 counter
“1”
PB0/SCLK12
Serial I/O1 clock
pin selection bits
“0 ”
PB0 latch
“0”
PB5/SOUT1
PB5 latch
“1” Serial transfer selection bits
PB6/SIN1
Serial I/O1 register (8)
Fig. 21 Block diagram of serial I/O1
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HARDWARE
FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1 (SC11):address 001916)
Serial transfer selection bits
b1 b0
0 0 : Serial I/O disabled (pins PB0 to PB6 are I/O ports)
0 1 : 8-bit serial I/O
1 0 : Not available
1 1 : Automatic transfer serial I/O (8-bits)
Serial I/O1 synchronous clock selection bits (PB3/SSTB1 pin control bit)
b3 b2
0 0 : Internal synchronous clock (PB3 pin is an I/O port.)
0 1 : External synchronous clock (PB3 pin is an I/O port.)
1 0 : Internal synchronous clock (PB3 pin is an SSTB1 output.)
1 1 : Internal synchronous clock (PB3 pin is an SSTB1 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (PB6 pin is an SIN1 input.)
1: Transmit-only mode (PB6 pin is an I/O port.)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O1 clock pin selection bit
0:SCLK11 (PB0/SCLK12 pin is an I/O port.)
1:SCLK12 (PB4/SCLK11 pin is an I/O port.)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A16)
PB1/SRDY1 • PB2/SBUSY1 pin control bits
b3b2b1b0
0 0 0 0: Pins PB1 and PB2 are I/O ports
0 0 0 1: Not used
0 0 1 0: PB1 pin is an SRDY1 output, PB2 pin is an I/O port.
0 0 1 1: PB1 pin is an SRDY1 output, PB2 pin is an I/O port.
0 1 0 0: PB1 pin is an I/O port, PB2 pin is an SBUSY1 input.
0 1 0 1: PB1 pin is an I/O port, PB2 pin is an SBUSY1 input.
0 1 1 0: PB1 pin is an I/O port, PB2 pin is an SBUSY1 output.
0 1 1 1: PB1 pin is an I/O port, PB2 pin is an SBUSY1 output.
1 0 0 0: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 0 0 1: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 0 1 0: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 0 1 1: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 1 0 0: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
1 1 0 1: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
1 1 1 0: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
1 1 1 1: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
SBUSY1 output • SSTB1 output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
SOUT1 pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
PB5/SOUT1 P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
Fig. 22 Structure of serial I/O1 control registers 1, 2
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HARDWARE
FUNCTIONAL DESCRIPTION
(1) Serial I/O1 operation
Either the internal synchronous clock or external synchronous
clock can be selected by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 0019 16) of serial I/O1 control
register 1 as synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider
where 7 different clocks are selected by the internal synchronous
clock selection bits (b5, b6 and b7 of address 001C16) of serial
I/O1 control register 3.
The PB1/S RDY1, PB2/S BUSY1, and PB3 /SSTB1 pins each select either I/O port or handshake I/O signal by the serial I/O1
synchronous clock selection bits (b2 and b3 of address 001916) of
serial I/O1 control register 1 as well as the PB 1/S RDY1 • PB2 /
SBUSY1 pin control bits (b0 to b3 of address 001A 16) of serial
I/O1 control register 2.
For the SOUT1 being used as an output pin, either CMOS output
or N-channel open-drain output is selected by the PB5/S OUT1 Pchannel output disable bit (b7 of address 001A16) of serial I/O1
control register 2.
Either output active or high-impedance can be selected as a
SOUT1 pin state at serial non-transfer by the SOUT1 pin control bit
(b6 of address 001A16) of serial I/O1 control register 2. However,
when the external synchronous clock is selected, perform the following setup to put the SOUT1 pin into a high-impedance state:
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1”.
b7 b6 b5 b4 b3 b2 b1 b0
When the S CLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the transmit-only mode are available for serial transfer, one of which is
selected by the transfer mode selection bit (b5 of address 001916 )
of serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6
of address 001916 ) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or automatic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 0019 16) of serial I/O1 control register 1, after
completion of the above bit setup. Next, set the serial I/O initialization bit (b4 of address 001916 ) of serial I/O1 control register 1 to
“1” (Serial I/O enable) .
When stopping serial transfer while data is being transferred, regardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0”.
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C16)
Automatic transfer interval set bits
b4b3b2b1b0
0 0 0 0 0: 2 cycles of transfer clocks
0 0 0 0 1: 3 cycles of transfer clocks
:
1 1 1 1 0: 32 cycles of transfer clocks
1 1 1 1 1: 33 cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
b7b6b5
0 0 0: f(XIN)/4 or f(XCIN)/8
0 0 1: f(XIN)/8 or f(XCIN)/16
0 1 0: f(XIN)/16 or f(XCIN)/32
0 1 1: f(XIN)/32 or f(XCIN)/64
1 0 0: f(XIN)/64 or f(XCIN)/128
1 0 1: f(XIN)/128 or f(XCIN)/256
1 1 0: f(XIN)/256 or f(XCIN)/512
Fig. 23 Structure of serial I/O1 control register 3
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HARDWARE
FUNCTIONAL DESCRIPTION
(2) 8-bit serial I/O mode
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16 ).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which becomes a transfer start trigger and reset to “0” after completion of
8-bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer
clocks are input to SCLK1 . Therefore, the clock needs to be controlled externally.
(3) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so that the function of
address 001B16 is used as a transfer counter (1-byte unit).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF 16), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be serially transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer interval for each 1-byte data can be set by the automatic transfer
interval set bits (b0 to b4 of address 001C16 ) of serial I/O1 control
register 3 in the following cases:
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or
a combination of S BUSY1 output and SSTB1 output of the handshake signal.
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
b7
I/O1 control register 2 as the signal for all transfer data, provided
that the automatic transfer interval setting is valid, a transfer interval is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the S BUSY1 output
• SSTB1 output function selection bit (b4), the transfer interval for
each 1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of S BUSY1 output and
SSTB1 output as a signal for all transfer data, the transfer interval
after the end of transmission/reception of the last data is longer
than the set value by 2 cycles.
When the external synchronous clock is selected, automatic transfer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes – 1” into the transfer counter
(address 001B16 ).
When the external synchronous clock is selected, write the value
of “number of transfer bytes – 1” into the transfer counter and
keep an internal system clock interval of 5 cycles or more. After
that, input transfer clock to SCLK1 .
As a transfer interval for each 1-byte data transfer, keep an internal system clock interval of 5 cycles or more from the clock rise
time of the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data
is written into the automatic transfer RAM. At the same time, a serial I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval
set bits (b0 to b4 of address 001C 16) are held in the latch.
When data is written into the transfer counter, the values latched
in the automatic transfer data pointer set bits (b0 to b7) and the
automatic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 001816)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
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HARDWARE
FUNCTIONAL DESCRIPTION
Automatic transfer RAM
FFF16
Automatic transfer
data pointer
5216
F5216
F5116
F5016
F4F16
F4E16
Transfer counter
0416
F0016
SIN1
SOUT1
Serial I/O1 register
Fig. 25 Automatic transfer serial I/O operation
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HARDWARE
FUNCTIONAL DESCRIPTION
(4) Handshake signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/reception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O initialization bit (b4) is reset to “0”, the SSTB1 output goes to “L”, or
the SSTB1 output goes to “H”.
At the end of transmit/receive operation, when the data of the serial I/O1 register is all output from SOUT1, pulses are output in the
period of 1 cycle of the transfer clock so as to cause the SSTB1
output to go “H” or the S STB1 output to go “L”. After that, each
pulse is returned to the initial status in which SSTB1 output goes to
“L” or the SSTB1 output goes to “H”.
Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to “0”.
In the automatic transfer serial I/O mode, whether the SSTB1 output is to be active at an end of each 1-byte data or after
completion of transfer of all data can be selected by the SBUSY1
output • SSTB1 output function selection bit (b4 of address 001A16 )
of serial I/O1 control register 2.
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H”
level signal into the SBUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal into the SBUSY1 input and an “H” level signal into the SBUSY1
input in the period of 1.5 cycles or more of the transfer clock.
Then, transfer clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive operation is started, this transmit/receive operation are not stopped
immediately and the transfer clocks from the SCLK1 output is not
stopped until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, input an “H”
level signal into the SBUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped. At
this time, the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 become valid, enabling a transmit/receive operation, while an “L”
level signal is input into the SBUSY1 input and an “H” level signal is
input into the SBUSY1 input.
When changing the input values in the S BUSY1 input and the
SBUSY1 input at these operations, change them when the SCLK1
input is in a high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK1, while
an “L” level signal is input into the SBUSY1 input and an “H” level
signal is input into the SBUSY1 input.
1-34
SSTB1
Serial transfer
status flag
SCLK1
SOUT1
Fig. 26 SSTB1 output operation
SBUSY1
SCLK1
SOUT1
Fig. 27 SBUSY1 input operation (internal synchronous clock)
SBUSY1
SCLK1
Invalid
SOUT1
(Output high-impedance)
Fig. 28 SBUSY1 input operation (external synchronous clock)
3. SBUSY1 output signal
The S BUSY1 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the S BUSY1 output is to be active at
transfer of each 1-byte data or during transfer of all data can be
selected by the S BUSY1 output • SSTB1 output function selection bit
(b4).
In the initial status, the status in which the serial I/O initialization
bit (b4) is reset to “0”, the S BUSY1 output goes to “H” and the
SBUSY1 output goes to “L”.
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (S BUSY1 output function outputs in 1-byte units), the S BUSY1 output goes to “L”
and the S BUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the S CLK1 output
goes to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output function outputs all transfer data), the S BUSY1 output goes to “L” and
the S BUSY1 output goes to “H” when the first transmit data is written into the serial I/O1 register (address 001B 16).
When the external synchronous clock is selected, the SBUSY1 output goes to “L” and the S BUSY1 output goes to “H” when transmit
data is written into the serial I/O1 register to start a transmit operation, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output returns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to “0”, regardless of
whether the internal or external synchronous clock is selected.
Furthermore, in the automatic transfer serial I/O mode (S BUSY1
output function outputs in 1-byte units), the SBUSY1 output goes to
“H” and the SBUSY1 output goes to “L” each time 1-byte of receive
data is written into the automatic transfer RAM.
SBUSY1
SBUSY1
Serial transfer
status flag
Serial transfer
status flag
SCLK1
SCLK1
Write to Serial
I/O1 register
SOUT1
Fig. 29 S BUSY1 output operation
(internal synchronous clock, 8-bit serial I/O)
Fig. 30 SBUSY1 output operation
(external synchronous clock, 8-bit serial I/O)
Automatic transfer
interval
SCLK1
Serial I/O1 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O1 register
SBUSY1
Serial transfer
status flag
SOUT1
Fig. 31 S BUSY1 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
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HARDWARE
FUNCTIONAL DESCRIPTION
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready.
In the initial status, when the serial I/O initialization bit (b4) is reset
to “0”, the SRDY1 output goes to “L” and the S RDY1 output goes to
“H”. After transmitted data is stored in the serial I/O1 register (address 001B16) and a transmit/receive operation becomes ready,
the SRDY1 output goes to “H” and the SRDY1 output goes to “L”.
When a transmit/receive operation is started and the transfer clock
goes to “L”, the SRDY1 output goes to “L” and the SRDY1 output
goes to “H”.
5. SRDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles
or more of transfer clock, transfer clocks are output from the
SCLK1 output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level signal is input into the S RDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received,
the transfer clocks from the SCLK1 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer
serial I/O are of 8 bits.
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To start a transmit/receive operation (SBUSY1 output: “L”, S BUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an
“L” level signal into the SRDY1 input, and also write transmit data
into the serial I/O1 register.
1-36
SRDY1
SCLK1
Write to serial
I/O1 register
Fig. 32 SRDY1 output operation
SRDY1
SCLK1
SOUT1
Fig. 33 SRDY1 input operation (internal synchronous clock)
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
A:
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
SCLK1
B:
Internal synchronous
clock selection
External synchronous
clock selection
B:
Write to serial
I/O1 register
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
A:
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
Internal synchronous
clock selection
SCLK1
B:
External synchronous
clock selection
B:
Write to serial
I/O1 register
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
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HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O2
register (address 001D 16) to “1”. For clock synchronous serial I/O,
the transmitter and the receiver must use the same clock for serial
I/O2 operation. If an internal clock is used, transmit/receive is
started by a write signal to the serial I/O2 transmit/receive buffer
register (TB/RB) (address 001F16 ).
When P6 7 (SCLK22 ) is selected as a clock I/O pin, SRDY2 output
function is invalid, and P66 (SCLK21) is used as an I/O port.
Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control
Data bus
Serial I/O2 control register
Address 001F16
Receive buffer register
Shift clock
“0 ”
P66/SCLK21
P67/SRDY2/SCLK22
XIN
Serial I/O2 clock I/O pin selection bit
P67/SRDY2/SCLK22
P65/TXD
Clock control circuit
“1 ”
“0 ”
Internal system clock selection bit
Serial I/O2 synchronous clock selection bit
“0 ”
“1 ”
XCIN
Receive interrupt request (RI)
Receive shift register
P64/RXD
Address 001D16
Receive buffer full flag (RBF)
“1 ”
1/2
F/F
BRG count source selection bit Division ratio 1/(n+1)
Baud rate generator
BRG clock
Address 003716
1/4
switch bit
Falling edge detector
Serial I/O2
clock I/O pin
selection bit
1/4
Clock control circuit
Transmit shift register shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Shift clock
Transmit shift register
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 001E16
Address 001F16
Data bus
Fig. 36 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock
(1/2 to 1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig. 37 Operation of clock synchronous serial I/O2 function
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HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous serial I/O (UART) mode
The transmit and receive shift registers each have a buffer (the
two buffers have the same address in memory). Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be
transmitted, and the receive buffer can receive 2-byte data continuously.
The asynchronous serial I/O (UART) mode can be selected by
clearing the serial I/O2 mode selection bit (b6) of the serial I/O2
control register (address 001D16) to “0”. Eight serial data transfer
formats can be selected and the transfer formats used by the
transmitter and receiver must be identical.
Data bus
Serial I/O2 control register Address 001D16
Address 001F16
P64/RXD
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
7 bit
ST detector
Receive shift register
1/16
8 bit
PE FE
P66/SCLK21
P67/SRDY2/SCLK22
XIN
“0”
Clock control circuit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 clock I/O pin
selection bit
UART control register
Address 003816
“1”
Internal system clock selection bit
“0 ”
“1”
XCIN
SP detector
1/2
BRG count source
selection bit
“1 ”
BRG clock
switch bit
1/4
Division ratio 1/(n+1)
Baud rate generator
Address 003716
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
P65/TXD
Character length selection bit
Transmit buffer empty flag (TBE)
Address 001E16
Serial I/O2 status register
Transmit buffer register
Address 001F16
Data bus
Fig. 38 Block diagram of UART serial I/O2
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
Serial I/O2 output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1*
ST
D0
Read-out signal from receive
buffer register
ST
D0
D1
SP
* Generated at 2nd bit in 2-stop
bit mode
RBF=0
RBF=1
Serial I/O2 input RXD
D1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
SP
ST
D0
D1
RBF=1
SP
Fig. 39 Operation of UART serial I/O2 function
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HARDWARE
FUNCTIONAL DESCRIPTION
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (003816)
This is a 7 bit register containing four control bits, of which four
bits are valid when UART is selected, and of which three bits are
always valid.
Data format of serial data receive/transfer and the output structure
of the P65/TxD pin and others are set by this register.
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags
(b0 to b6) which indicate the operating status of the serial I/O2
function and various errors. Three of the flags (b4 to b6) are only
valid in the UART mode. The receive buffer full flag (b1) is cleared
to “0” when the receive buffer is read.
The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A writing to the serial I/O2
status register clears error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing “0” to the serial I/O2 enable bit (SIOE : b7 of
the serial I/O2 control register) also clears all the status flags, including the error flags.
All bits of the serial I/O2 status register are initialized to “0” at reset, but if the transmit enable bit (b4) of the serial I/O2 control
register has been set to “1”, the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become “1”.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
[Baud Rate Generator] BRG (003716)
The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register, the baud rate
generator divides the frequency of the count source by 1/(n+1),
where n is the value written to the baud rate generator.
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FUNCTIONAL DESCRIPTION
b7
b0
b7
Serial I/O2 status register
(SIO2STS : address 001E16)
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
SRDY2 output enable bit (SRDY)
0: P67 pin operates as ordinary I/O pin
1: P67 pin operates as SRDY2 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
BRG count source selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b7
b0
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P64 to P67 operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P64 to P67 operate as serial I/O pins)
UART control register
(UARTCON : address 003816)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P65/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P67/SCLK22 pin is used as I/O port or SRDY2 output pin.)
1: SCLK22 (P66/SCLK21 pin is used as I/O port.)
Not used (return “1” when read)
Fig. 40 Structure of serial I/O2 related register
■Notes
When setting the transmit enable bit to “1”, the serial I/O2 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled,
take the following sequence.
➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the serial I/O1 tranmit interrupt enable bit to “1” (enabled).
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HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O3
b7
The serial I/O3 function can be used only for 8-bit clock synchronous serial I/O.
All serial I/O pins are shared with port P9, which can be set with
the serial I/O3 control register (address 0EEC16).
b0
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(XIN)/4 (f(XCIN)/8)
0 0 1: f(XIN)/8 (f(XCIN)/16)
0 1 0: f(XIN)/16 (f(XCIN)/32)
0 1 1: f(XIN)/32 (f(XCIN)/64)
1 1 0: f(XIN)/64 (f(XCIN)/128)
1 1 1: f(XIN)/128 (f(XCIN)/256)
[Serial I/O3 Control Register (SIO3CON)] 0EEC16
The serial I/O3 control register contains eight bits which control
various serial I/O functions.
Serial I/O3 port selection bit (P91, P92)
0: I/O port
1: SOUT3, SCLK3 signal output
● Serial I/O3 Operation
Either the internal clock or external clock can be selected as synchronous clock for serial I/O3 transfer.
The internal clock can use a built-in dedicated divider where 6 different clocks are selected. In the case of the internal clock used,
transfer is started by a write signal to the serial I/O3 register (address 0EED16). When 8-bit data has been transferred, the SOUT3
pin goes to high impedance state.
In the case of the external clock used, the clock must be externally
controlled. It is because the contents of serial I/O3 register is kept
shifted while the clock is being input. Additionally, the function to
put the SOUT3 pin high impedance state at completion of data
transfer is not available.
The serial I/O3 interrupt request bit is set at completion of 8-bit
data transfer, regardless of use of the internal clock or external
clock.
1/2
SRDY3 output selection bit (P93)
0: I/O port
1: SRDY3 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O3 synchronous clock selection bit
0: External clock
1: Internal clock
P91/SOUT3 P-channel output disable bit (P91)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Fig. 42 Structure of serial I/O3 control register
1/4
Internal system clock
selection bit
“1”
Internal synchronous
clock selection bits
1/8
Divider
XCIN
Serial I/O3 control register
(SIO3CON : address 0EEC16)
XIN
“0 ”
1/16
Data bus
1/32
1/64
1/128
P93 latch
“0 ”
SRDY3
Synchronization
“1 ”
circuit
SRDY3 output selection bit
SCLK3
P93/SRDY3
Serial I/O3 synchronous
clock selection bit “1”
“0”
External clock
P92 latch
“0 ”
P92/SCLK3
“1 ”
Serial I/O3 port selection bit
Serial I/O3 counter (3)
P91 latch
“0 ”
P91/SOUT3
“1 ”
Serial I/O3 port selection bit
P90/SIN3
Serial I/O3 shift register (8)
Fig. 41 Block diagram of serial I/O3
1-42
38B7 Group User’s Manual
Serial I/O3
interrupt request
HARDWARE
FUNCTIONAL DESCRIPTION
Synchronous clock
Transfer clock
Serial I/O3 register
write signal
(Note)
Serial I/O3 output SOUT3
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O3 input SIN3
Receive enable signal SRDY3
Note: When the internal clock is selected as the transfer clock, the SOUT3 pin goes to high
impedance after transfer completion.
Serial I/O3 interrupt request bit set
Fig. 43 Timing of serial I/O3 (LSB first)
38B7 Group User’s Manual
1-43
HARDWARE
FUNCTIONAL DESCRIPTION
FLD CONTROLLER
The M38B7 group has fluorescent display (FLD) drive and control
circuits.
Table 9 shows the FLD controller specifications.
Table 9 FLD controller specifications
FLD
controller
port
Item
High-breakdownvoltage output port
CMOS port
Display pixel number
Period
Dimmer time
Interrupt
Key-scan
Expanded function
1-44
Specifications
• 52 pins (20 pins can be switched to general-purpose ports)
• 4 pins (all 4 pins can be switched to general-purpose ports)
(A driver IC must be installed externally)
• Used FLD output
28 segment ✕ 28 digit (segment number + digit number ≤ 56)
• Used digit output
40 segment ✕ 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501
56 segment ✕ (connected number of M35501) digit
(segment number ≤ 56, digit number ≤ number of M35501 ✕ 16)
• Used P64 to P67 expansion
52 segment ✕ 16 digit (segment number ≤ 52, digit number ≤ 16)
• 4.0 µs to 1024 µs (count source XIN/16, 4 MHz)
• 16.0 µs to 4096 µs (count source XIN/64, 4 MHz)
• 4.0 µs to 1024 µs (count source XIN/16, 4 MHz)
• 16.0 µs to 4096 µs (count source XIN/64, 4 MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan using digit
• Key-scan using segment
• Digit pulse output function
This function automatically outputs digit pulses.
• M35501 connection function
The number of digits can be increased easily by using the output of DIMOUT(P7 3) as CLK for the
M35501.
• Toff section generating/nothing function
This function does not generate Toff1 section when the connected outputs are the same.
• Gradation display function
This function allows each segment to be set for dark or bright display.
• P64 to P67 expansion function
This function provides 16 lines of digit outputs from four ports by attaching the decoder converting
4-bit data to 16-bit data.
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Main
data bus
Main address bus
Local
data bus
Digit output set switch register
P20/FLD0 DIG/FLD
P21/FLD1 DIG/FLD
P22/FLD2 DIG/FLD
P23/FLD3 DIG/FLD 8
P24/FLD4 DIG/FLD
P25/FLD5 DIG/FLD
P26/FLD6 DIG/FLD
P27/FLD7 DIG/FLD
0EF316
000416
P00/FLD8
P01/FLD9
P02/FLD10
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
000016
Local address bus
FLD automatic display RAM
0E0016
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD 8
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
0EF216
P10/FLD16
P11/FLD17
P12/FLD18
P13/FLD19 8
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
000216
0EDF16
P30/FLD24
P31/FLD25
P32/FLD26
P33/FLD27 8
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
000616
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0EF916
FLDC mode
register
(0EF416)
FLD data pointer
reload register
(0EF816)
Address
decoder
FLD data pointer
(0EF816)
Timing generator
P40/FLD32
P41/FLD33
P42/FLD34
P43/FLD35 8
P44/FLD36
P45/FLD37
P46/FLD38
P47/FLD39
000816
FLD/P P50/FLD40
FLD/P P51/FLD41
FLD/P P52/FLD42
FLD/P P53/FLD43 8
FLD/P P54/FLD44
FLD/P P55/FLD45
FLD/P P56/FLD46
FLD/P P57/FLD47
000A16
0EFA16
FLD blanking interrupt
FLD digit interrupt
FLD/P P60/FLD48
FLD/P P61/FLD49
FLD/P P62/FLD50
FLD/P P63/FLD51 8
FLD/P P64/FLD52
FLD/P P65/FLD53
FLD/P P66/FLD54
FLD/P P67/FLD55
000C16
0EFB16
FLD/Port switch register
Fig. 44 Block diagram of FLD control circuit
38B7 Group User’s Manual
1-45
HARDWARE
FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
Automatic display control bit
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display( start to display by switching “0” to “1”)
Tscan control bits
b3b2
0 0 : FLD digit interrupt (at rising edge of each digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
FLD blanking interrupt
1 1 : 3 ✕ Tdisp
(at falling edge of the last digit)
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16
1 : f(XIN)/64
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Note: When the gradation display mode is selected, the max. number of timing is 16
timing. (Be sure to set the timing number control bit to “0”.)
b7 b6 b5 b4 b3 b2 b1 b0
FLD output control register
(FLDCON: address 0EFC16)
P64 to P67 output reverse bit
0 : Output normally
1 : Reverse output
Not used (return “0” when read); (Do not write “1”.)
P64 to P67 Toff invalid bit
0 : Operation normally
1 : Toff invalid
Not used (return “0” when read); (Do not write “1”.)
P73 dimmer output control bit
0 : Normal port
1 : Dimmer output
Generating/Not of CMOS port Toff section selection bit
0 : Toff section not generated
1 : Toff section generated
Generating/Not of high-breakdown voltage port Toff section
selection bit
0 : Toff section not generated
1 : Toff section generated
Toff2 SET/RESET switch bit
0 : Toff2 RESET; Toff1 SET
1 : Toff2 SET; Tdisp RESET
Fig. 45 Structure of FLDC related registers (1)
1-46
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Port P4 FLD/Port switch register
(P4FPR: address 0EF916)
Port P40 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P41 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P42 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P43 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P44 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P45 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P46 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P47 FLD/Port switch bit
0 : Normal port
1 : FLD output port
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 FLD/Port switch register
(P5FPR: address 0EFA16)
Port P50 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P51 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P52 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P53 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P54 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P55 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P56 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P57 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Fig. 46 Structure of FLDC related registers (2)
38B7 Group User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 FLD/Port switch register
(P6FPR: address 0EFB16)
Port P60 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P61 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P62 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P63 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P64 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P65 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P66 FLD/Port switch bit
0 : Normal port
1 : FLD output Port
Port P67 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Fig. 47 Structure of FLDC related registers (3)
1-48
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 digit output set switch register
(P0DOR: address 0EF216)
Port P00 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P01 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P02 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P03 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P04 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P05 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P06 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P07 FLD/Digit switch bit
0 : FLD output
1 : Digit output
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 digit output set switch register
(P2DOR: address 0EF316)
Port P20 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P21 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P22 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P23 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P24 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P25 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P26 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P27 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Fig. 48 Structure of FLDC related registers (4)
38B7 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION
FLD Automatic Display Pins
P0 to P6 are the pins capable of automatic display output for the
FLD. The FLD star ts operating by setting the automatic display
control bit (bit 0 at address 0EF416) to “1”. There is the FLD output
function that outputs the RAM contents from the port every timing
or the digit output function that drives the port high with a digit tim-
ing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for the digits. When using the
FLD output for the digits, be sure to write digit display patterns to
the RAM in advance. The remaining segment and digit lines can
be used as general-purpose ports. Settings of each port are
shown below.
Table 10 Pins in FLD automatic display mode
Automatic display pin
Setting method
Port
FLD
0
to
FLD
15
The
individual
bits
of
the
digit
output
set switch registers (addresses 0EF216 , 0EF316 ) can
P0, P2
set each pin to either an FLD port (“0”) or a digit port (“1”).
P1, P3
FLD16 to FLD31
P4, P5,
P60 to P63
P64 to P67
FLD32 to FLD51
When the pins are set for the digit port, the digit pulse output function is enabled, so that the
digit pulses can always be output regardless the value of FLD automatic display RAM.
Setting the automatic display control bit (bit 0 of address 0EF416) to “1” can set these ports
to the FLD exclusive use port.
The individual bits of the FLD/Port switch register (addresses 0EF916 to 0EFB 16) can set
each pin to either an FLD port (“1”) or a general-purpose port (“0”).
The individual bits of the port P6 FLD/Port switch register (address 0EFB16 ) can set each
pin to either FLD port (“1”) or general-purpose port (“0”). A variety of output pulses can be
available by setting of the FLD output control register (address 0EFC 16 ). The port output
structure is the CMOS output. When using the port as a display pin, a driver IC must be installed externally.
FLD52 to FLD55
Setting example 1
This is a register setup example where only FLD output is used.
In this case, the digit display output pattern must be set in the FLD automatic
display RAM in advance.
Number of segments
Number of digits
Port P2
Port P0
Port P1
Port P3
36
16
The contents of digit output set switch registers
(0EF216, 0EF316)
FLD0 (DIG output)
FLD1 (DIG output)
FLD2 (DIG output)
FLD3 (DIG output)
FLD4 (DIG output)
FLD5 (DIG output)
FLD6 (DIG output)
FLD7 (DIG output)
0
0
0
0
0
0
0
0
FLD8 (DIG output)
FLD9 (DIG output)
FLD10 (DIG output)
FLD11 (DIG output)
FLD12 (DIG output)
FLD13 (DIG output)
FLD14 (DIG output)
FLD15 (DIG output)
0
0
0
0
0
0
FLD16 (SEG output)
FLD17 (SEG output)
FLD18 (SEG output)
FLD19 (SEG output)
FLD20 (SEG output)
FLD21 (SEG output)
FLD22 (SEG output)
FLD23 (SEG output)
FLD24 (SEG output)
FLD25 (SEG output)
FLD26 (SEG output)
FLD27 (SEG output)
FLD28 (SEG output)
FLD29 (SEG output)
FLD30 (SEG output)
FLD31 (SEG output)
Setting example 2
This is a register setup example where both FLD output and digit waveform output are
used. In this case, because the digit display output is automatically generated, there is
no need to set the display pattern in the FLD automatic display RAM.
Number of segments
Number of digits
Port P2
FLD/Port switch registers
(0EF916 to 0EFB16)
Port P4
0
0
Port P5
Port P6
1
1
1
1
1
1
1
1
FLD32 (SEG output)
FLD33 (SEG output)
FLD34 (SEG output)
FLD35 (SEG output)
FLD36 (SEG output)
FLD37 (SEG output)
FLD38 (SEG output)
Port P0
FLD39(SEG output)
1 FLD40 (SEG output)
1 FLD41 (SEG output)
1 FLD42 (SEG output)
1 FLD43 (SEG output)
1 FLD44 (SEG output)
1 FLD45 (SEG output)
1 FLD46 (SEG output)
1 FLD47 (SEG output)
Port P1
1
1
1
1
0
0
0
0
Port P3
FLD48 (SEG output)
FLD49 (SEG output)
FLD50 (SEG output)
FLD51 (SEG output)
FLD52 (port output)
FLD53 (port output)
FLD54 (port output)
FLD55 (port output)
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port (used by program).
The contents of digit output set switch registers
(0EF216, 0EF316)
FLD0 (DIG output)
FLD1 (DIG output)
FLD2 (DIG output)
FLD3 (DIG output)
FLD4 (DIG output)
FLD5 (DIG output)
FLD6 (DIG output)
FLD7 (DIG output)
1
1
1
1
1
1
1
1
FLD8 (DIG output)
FLD9 (DIG output)
FLD10 (DIG output)
FLD11 (DIG output)
FLD12 (SEG output)
FLD13 (SEG output)
FLD14 (SEG output)
FLD15 (SEG output)
1
1
1
1
0
0
FLD16 (SEG output)
FLD17 (SEG output)
FLD18 (SEG output)
FLD19 (SEG output)
FLD20 (SEG output)
FLD21 (SEG output)
FLD22 (SEG output)
FLD23 (SEG output)
FLD24 (SEG output)
FLD25 (SEG output)
FLD26 (SEG output)
FLD27 (SEG output)
FLD28 (SEG output)
FLD29 (SEG output)
FLD30 (SEG output)
FLD31 (SEG output)
FLD/Port switch registers
(0EF916 to 0EFB16)
Port P4
1
1
1
1
1
Port P5
1
1
1
1
0
0
0
0
FLD40 (SEG output)
FLD41 (SEG output)
FLD42 (SEG output)
FLD43 (SEG output)
FLD44 (port output)
FLD45 (port output)
FLD46 (port output)
FLD47 (port output)
Port P6
0
0
0
0
0
0
0
FLD48 (port output)
FLD49 (port output)
FLD50 (port output)
FLD51 (port output)
FLD52 (port output)
0
0
FLD32 (SEG output)
FLD33 (SEG output)
FLD34 (SEG output)
FLD35 (SEG output)
FLD36 (SEG output)
1 FLD37 (SEG output)
1 FLD38 (SEG output)
1 FLD39 (SEG output)
FLD53 (port output)
FLD54 (port output)
0 FLD55 (port output)
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port (used by program).
Fig. 49 Segment/Digit setting example
1-50
28
12
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
FLD Automatic Display RAM
(3) 32-timing mode
The FLD automatic display RAM uses the 224 bytes of addresses
0E0016 to 0EDF16. For FLD, the 3 modes of 16-timing•ordinary
mode, 16-timing•gradation display mode and 32-timing mode are
available depending on the number of timings and the use/not use
of gradation display.
The automatic display RAM in each mode is as follows:
This mode is used when the display timing is 16 or greater. This
mode can be used for up to 32-timing.
The 224 bytes of addresses 0E0016 to 0EDF 16 are used as an
FLD display data store area.
(1) 16-timing•ordinary mode
This mode is used when the display timing is 16 or less. The 112
bytes of addresses 0E7016 to 0EDF 16 are used as a FLD display
data store area. Because addresses 0E0016 to 0E6F 16 are not
used as the automatic display RAM, they can be the ordinary
RAM.
The FLD data pointer (address 0EF816 ) is a register to count display timings. This pointer has a reload register. When the pointer
underflow occurs, it starts counting over again after being reloaded with the initial value in the reload register. Make sure that
(the timing counts – 1) is set to the FLD data pointer. When writing
data to this address, the data is written to the FLD data pointer reload register; when reading data from this address, the value in
the FLD data pointer is read.
(2) 16-timing•gradation display mode
This mode is used when the display timing is 16 or less, in which
mode each segment can be set for dark or bright display. The 224
bytes of addresses 0E0016 to 0EDF 16 are used. The 112 bytes of
addresses 0E70 16 to 0EDF16 are used as an FLD display data
store area, while the 112 bytes of addresses 0E0016 to 0E6F16 are
used as a gradation display control data store area.
16-timing•ordinary mode
16-timing•gradation display mode
0E0016
0E0016
0E0016
Gradation display
control data stored
area
Not used
0E7016
1 to 32 timing display
data stored area
0E7016
1 to 16 timing display
data stored area
1 to 16 timing display
data stored area
0EDF16
32-timing mode
0EDF16
0EDF16
Fig. 50 FLD automatic display RAM assignment
38B7 Group User’s Manual
1-51
HARDWARE
FUNCTIONAL DESCRIPTION
Data Setup
(1) 16-timing•ordinary mode
(2) 16-timing•gradation display mode
The area of addresses 0E7016 to 0EDF16 are used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last
data of FLD port P6 is stored at address 0E7016 , the last data of
FLD port P5 is stored at address 0E8016 , the last data of FLD port
P4 is stored at address 0E9016, the last data of FLD port P3 is
stored at address 0EA016, the last data of FLD port P1 is stored at
address 0EB016, the last data of FLD port P0 is stored at address
0EC016, and the last data of FLD port P2 is stored at address
0ED016, to assign in sequence from the last data respectively.
The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is
stored at an address which adds the value of (the timing number –
1) to the corresponding addresses 0E70 16, 0E80 16, 0E9016 ,
0EA016, 0EB016 , 0EC016 and 0ED016 .
Set the FLD data pointer reload register to the value given by (the
timing number – 1).
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 007016 from the
display data store address of each timing and pin. Bright display is
performed by setting “0”, and dark display is performed by setting
“1” .
(3) 32-timing Mode
The area of addresses 0E0016 to 0EDF 16 is used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last
data of FLD port P6 is stored at address 0E0016 , the last data of
FLD port P5 is stored at address 0E2016 , the last data of FLD port
P4 is stored at address 0E4016, the last data of FLD port P3 is
stored at address 0E6016 , the last data of FLD port P1 is stored at
address 0E8016 , the last data of FLD port P0 is stored at address
0EA016, and the last data of FLD port P2 is stored at address
0EC016 , to assign in sequence from the last data respectively.
The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is
stored at an address which adds the value of (the timing number –
1) to the corresponding addresses 0E00 16, 0E2016 , 0E4016,
0E6016, 0E8016 , 0EA016 and 0EC016 .
Set the FLD data pointer reload register to the value given by (the
timing number – 1).
Number of timing: 8
(FLD data pointer reload register = 7)
B it
Address
0E7016
0E7116
0E7216
0E7316
0E7416
0E7516
0E7616
0E7716
0E7816
0E7916
0E7A16
0E7B16
0E7C16
0E7D16
0E7E16
0E7F16
0E8016
0E8116
0E8216
0E8316
0E8416
0E8516
0E8616
0E8716
0E8816
0E8916
0E8A16
0E8B16
0E8C16
0E8D16
0E8E16
0E8F16
0E9016
0E9116
0E9216
0E9316
0E9416
0E9516
0E9616
0E9716
0E9816
0E9916
0E9A16
0E9B16
0E9C16
0E9D16
0E9E16
0E9F16
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
7
6
5
4
3
2
1
Bit
0
Address
The last timing
(The last data of FLDP6)
Timing for start
(The first data of FLDP6)
FLDP6 data area
The last timing
(The last data of FLDP5)
Timing for start
(The first data of FLDP5)
FLDP5 data area
The last timing
(The last data of FLDP4)
Timing for start
(The first data of FLDP4)
FLDP4 data area
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
FLDP3 data area
Fig. 51 Example of using FLD automatic display RAM in 16-timing•ordinary mode
1-52
38B7 Group User’s Manual
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP1)
FLDP1 data area
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP0)
FLDP0 data area
The last timing
(The last data of FLDP2)
Timing for start
(The first data of FLDP2)
FLDP2 data area
HARDWARE
FUNCTIONAL DESCRIPTION
Number of timing: 15
(FLD data pointer reload register = 14)
B it
Address
0E7016
0E7116
0E7216
0E7316
0E7416
0E7516
0E7616
0E7716
0E7816
0E7916
0E7A16
0E7B16
0E7C16
0E7D16
0E7E16
0E7F16
0E8016
0E8116
0E8216
0E8316
0E8416
0E8516
0E8616
0E8716
0E8816
0E8916
0E8A16
0E8B16
0E8C16
0E8D16
0E8E16
0E8F16
0E9016
0E9116
0E9216
0E9316
0E9416
0E9516
0E9616
0E9716
0E9816
0E9916
0E9A16
0E9B16
0E9C16
0E9D16
0E9E16
0E9F16
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
7
6
5
4
3
2
1
Bit
0
Address
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP4)
FLDP4 data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
7
6
5
4
3
2
1
0
0E0016
0E0116
0E0216
0E0316
0E0416
0E0516
0E0616
0E0716
0E0816
0E0916
0E0A16
0E0B16
0E0C16
0E0D16
0E0E16
0E0F16
0E1016
0E1116
0E1216
0E1316
0E1416
0E1516
0E1616
0E1716
0E1816
0E1916
0E1A16
0E1B16
0E1C16
0E1D16
0E1E16
0E1F16
0E2016
0E2116
0E2216
0E2316
0E2416
0E2516
0E2616
0E2716
0E2816
0E2916
0E2A16
0E2B16
0E2C16
0E2D16
0E2E16
0E2F16
0E3016
0E3116
0E3216
0E3316
0E3416
0E3516
0E3616
0E3716
0E3816
0E3916
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016
0E4116
0E4216
0E4316
0E4416
0E4516
0E4616
0E4716
0E4816
0E4916
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
0E6A16
0E6B16
0E6C16
0E6D16
0E6E16
0E6F16
The last timing
(The last data of FLDP6)
FLDP6 gradation
display data area
Timing for start
(The first data of FLDP6)
The last timing
(The last data of FLDP5)
FLDP5 gradation
display data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP4)
FLDP4 gradation
display data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 gradation
display data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP1)
FLDP1 gradation
display data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 gradation
display data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP2)
FLDP2 gradation
display data area
Timing for start
(The first data of FLDP2)
Fig. 52 Example of using FLD automatic display RAM in 16-timing•gradation display mode
38B7 Group User’s Manual
1-53
HARDWARE
FUNCTIONAL DESCRIPTION
B it
Number of timing: 20
(FLD data pointer reload register = 19)
B it
Address
0E7016
0E7116
0E7216
0E7316
0E7416
0E7516
0E7616
0E7716
0E7816
0E7916
0E7A16
0E7B16
0E7C16
0E7D16
0E7E16
0E7F16
0E8016
0E8116
0E8216
0E8316
0E8416
0E8516
0E8616
0E8716
0E8816
0E8916
0E8A16
0E8B16
0E8C16
0E8D16
0E8E16
0E8F16
0E9016
0E9116
0E9216
0E9316
0E9416
0E9516
0E9616
0E9716
0E9816
0E9916
0E9A16
0E9B16
0E9C16
0E9D16
0E9E16
0E9F16
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
7
6
5
4
3
2
Address
1
0
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
7
6
5
0E0016
0E0116
0E0216
0E0316
0E0416
0E0516
0E0616
0E0716
0E0816
0E0916
0E0A16
0E0B16
0E0C16
0E0D16
0E0E16
0E0F16
0E1016
0E1116
0E1216
0E1316
0E1416
0E1516
0E1616
0E1716
0E1816
0E1916
0E1A16
0E1B16
0E1C16
0E1D16
0E1E16
0E1F16
0E2016
0E2116
0E2216
0E2316
0E2416
0E2516
0E2616
0E2716
0E2816
0E2916
0E2A16
0E2B16
0E2C16
0E2D16
0E2E16
0E2F16
0E3016
0E3116
0E3216
0E3316
0E3416
0E3516
0E3616
0E3716
0E3816
0E3916
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016
0E4116
0E4216
0E4316
0E4416
0E4516
0E4616
0E4716
0E4816
0E4916
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
0E6A16
0E6B16
0E6C16
0E6D16
0E6E16
0E6F16
Fig. 53 Example of using FLD automatic display RAM in 32-timing mode
1-54
38B7 Group User’s Manual
4
3
2
1
0
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP4)
FLDP4 data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 data area
HARDWARE
FUNCTIONAL DESCRIPTION
Timing Setting
(3) Toff2 time setting
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
The Toff2 time is time for dark display. For bright display, the FLD
display output remains effective until the counter that is counting
Tdisp underflows. For dark display, however, “L” (or “off”) signal is
output when the counter that is counting Toff2 underflows. This
Toff2 time setting is valid only for FLD ports which are in the gradation display mode and whose gradation display control RAM
value is “1” .
Set the Toff2 time by the Toff2 time set register. Make sure the
value set to Toff2 is smaller than Tdisp but larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2
time is represented as Toff2 = n2 ✕ t. When the Tdisp counter
count source selection bit of the FLDC mode register is “0” and
the value of the Toff2 time set register is 180 (B4 16), Toff2 = 180 ✕
4.0 µs (at X IN = 4 MHz) = 720 µs.
When bit 7 of the FLD output control register (address 0EFC16 ) is
set to “1”, be sure to set the value of 03 16 or more to the Toff2 time
set register (address 0EF716 ).
(1) Tdisp time setting
The Tdisp time means the length of display timing. In non-gradation display mode, it consists of the FLD display output term and
the Toff1 time. In gradation display mode, it consists of the display
output term and the Toff1 time plus a low signal output term for
dark display. Set the Tdisp time by the Tdisp counter count source
selection bit of the FLDC mode register and the Tdisp time set
register. Supposing that the value of the Tdisp time set register is
n, the Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count
source). When the Tdisp counter count source selection bit of the
FLDC mode register is “0” and the value of the Tdisp time set register is 200 (C816 ), the Tdisp time is: Tdisp = (200 + 1) ✕ 4.0 µs (at
XIN = 4 MHz) = 804 µs. When reading the Tdisp time set register,
the counting value is read out.
(2) Toff1 time setting
The Toff1 time means a non-output (low signal output) time to prevent blurring of FLD and for dimmer display. Use the Toff1 time set
register to set this Toff1 time. Make sure the value set to Toff1 is
smaller than Tdisp and Toff2. Supposing that the value of the Toff1
time set register is n1, the Toff1 time is represented as Toff1 =
n1 ✕ t. When the Tdisp counter count source selection bit of the
FLDC mode register is “0” and the value of the Toff1 time set register is 30 (1E16 ), Toff1 = 30 ✕ 4.0 µs (at X IN = 4 MHz) = 120 µs.
Be sure to set the value of 0316 or more to the Toff1 time set register (address 0EF616).
Low output term for
blurring prevention
Display output term
•Gradation display mode is not selected
(Address 0EF416 bit 5 = “0”)
•Gradation display mode is selected and set for bright display
(Address 0EF416 bit 5 = “1” and the corresponding gradation
display control data = “0”)
Toff1
Tdisp
Low output term for
blurring prevention Display output term
•Gradation display mode is selected and set for dark display
(Address 0EF416 bit 5 = “1” and the corresponding gradation
display control data = “1”)
Low output term for
dark display
Toff1
Toff2
Tdisp
Fig. 54 FLD and digit output timing
38B7 Group User’s Manual
1-55
HARDWARE
FUNCTIONAL DESCRIPTION
FLD Automatic Display Start
Key-scan and Interrupt
Automatic display starts by setting both the automatic display control bit (bit 0 of address 0EF416 ) and the display start bit (bit 1 of
address 0EF416) to “1”. The RAM contents at a location apart from
the start address of the automatic display RAM for each port by
(FLD data pointer (address 0EF816) – 1) are output to each port.
The FLD data pointer (address 0EF816 ) counts down in the Tdisp
interval. When the count results in “FF 16”, the pointer is reloaded
and starts counting over again. Before setting the display start bit
(bit 1 of address 0EF416 ) to “1”, be sure to set the FLD/port switch
registers, digit output set switch registers, FLDC mode register,
Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer.
During FLD automatic display, the display star t bit always keeps
“1”, and FLD automatic display can be interrupted by writing “0” to
this bit.
Either the FLD digit interrupt or FLD blanking interrupt can be selected using the Tscan control bits (bits 2, 3 of address 0EF416 ).
The FLD digit interrupt is generated when the Toff1 time in each
timing expires (at rising edge of digit output). Key scanning that
makes use of FLD digits can be achieved using each FLD digit interrupt. To use FLD digit interrupts for key scanning, follow the
procedure described below:
(1) Read the port value each time the interrupt occurs.
(2) The key is fixed on the last digit interrupt.
The output digit positions can be determined by reading the FLD
data pointer (address 0EF816).
Repeat cycle
Tdisp
Toff1
Tn
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
FLD digit output
FLD digit interrupt generated at the rising edge of digit (each timing)
Fig. 55 Timing using digit interrupt
1-56
38B7 Group User’s Manual
T4
HARDWARE
FUNCTIONAL DESCRIPTION
■ Note
The FLD blanking interrupt is generated when the FLD data
pointer (address 0EF816 ) reaches “FF 16”. The FLD automatic display output is turned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp, or
3 ✕ Tdisp depending on post-interrupt settings. During this time,
key scanning that makes use of FLD segments can be achieved.
When the key scanning is performed with the segment during
key-scan blanking time Tscan, follow the procedure described
below:
(1) Write “0” to the automatic display control bit (bit 0 of address
0EF416 ).
(2) Set the port corresponding to the segment for key scanning to
the output port.
(3) Perform key scanning.
(4) Write “1” to the automatic display control bit.
When performing a key-scan according to the above steps 1 to 4,
take the following points into consideration.
1. Do not set the display start bit (bit 1 of address 0EF416) to “0”.
2. Do not set “1” in the ports corresponding to digits.
Repeat cycle
Tdisp
Tn
Tscan
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
FLD digit output
Segment setting by software
FLD blanking interrupt generated at the
falling of edge of the last timing
Fig. 56 Timing using FLD blanking interrupt
38B7 Group User’s Manual
1-57
HARDWARE
FUNCTIONAL DESCRIPTION
P64 to P67 Expansion Function
(3) P64 to P67 FLD output reverse function
Ports P6 4 to P6 7 are CMOS output structure. FLD digit outputs
can be increased as many as 16 lines by connecting a decoder
converting 4-bit to 16-bit data to these ports. P64 to P6 7 have the
function to allow for connection to a decoder converting 4-bit to
16-bit data.
P64 to P67 have the function to reverse the polarity of the FLD output. This function is useful in adjusting the polarity when using an
externally installed driver.
The output polarity can be reversed by setting the P64 to P6 7 output reverse bit of the FLD output control register (bit 0 of address
0EFC16 ) to “1”.
(1) P64 to P67 Toff invalid function
This function disables the Toff1 time and Toff2 time and outputs
display data for the duration of Tdisp. (See Figure 57.) This can be
achieved by setting the P64 to P6 7 Toff invalid bit (bit 2 of address
0EFC16 ) to “1”.
■ Note
In the case of gradation display mode and dark display, P64 to P6 7
Toff invalid function is disabled.
(2) Dimmer signal output function
This function allows a dimmer signal creation signal to be output
from DIMOUT (P73). The dimmer function can be achieved by controlling the decoder with this signal. (See Figure 57.) This function
can be set by setting P73 dimmer output control bit (bit 4 of address 0EFC16 ) to “1”.
Unlike the Toff section generating/nothing function, this function
disables all display data.
•Gradation display mode is not selected
•Gradation display mode is selected and
set for bright display
(gradation display control data = “0”)
FLD output
•Gradation display mode is selected and
set for dark display
(gradation display control data = “1”)
•Gradation display mode is selected and
Toff2 SET/RESET switch bit is “1”
(gradation display control data = “1”)
Toff1
Toff2
Tdisp
Output selecting P64 to P67
Toff invalid
For dimmer signal
DIMOUT (P73)
Fig. 57 P64 to P67 FLD output pulses
1-58
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Toff Section Generate/Nothing Function
The function is for reduction of useless noises which generated as
every switching of ports, because of the combined capacity of
among FLD ports. When the continuous data is output to each
FLD port, the Toff1 section of the continuous par ts is not generated. (See Figure 58)
If it needs Toff1 section on FLD pulses, set the generating /not of
CMOS port Toff section selection bit (bit 5 of address 0EFC 16 ) to
“1” and set the generating /not of high-breakdown-voltage port Toff
section selection bit to “1”.
High-breakdown-voltage ports (P2, P0, P1, P3, P4, P5, P63 to
P60 , total 52 pins) generate Toff1 section by setting the generating
/not of high-breakdown-voltage port Toff section selection bit to
“1”.
The CMOS ports (P64 to P67, total 4 pins ) generate Toff1 section
by setting the generating /not of CMOS port Toff section selection
bit to “1”.
Tdisp
Toff1
“H” output
“L” output
“H” output
“H” output
“H” output
“H” output
“L” output
“H” output
“H” output
“L” output
“H” output
“H” output
P1X
Output waveform when
generating/not of high-breakdown
voltage port Toff section selection
P2X
bit (bit 6 of address 0EFC16) is “1”.
P1X
Output waveform when
generating/not of high-breakdown
voltage port Toff section selection
bit (bit 6 of address 0EFC16) is “0”.
Section of Toff1 is not generated because of output is the same.
“H” output
“H” output
“L” output
“H” output
P2X
Section of Toff1 is not generated because of output is the same.
Fig. 58 Toff section generating/nothing function
Toff2 SET/RESET Switch Function
In gradation display mode, the values set by the Toff2 time set register (TOFF2) are effective. When the Toff2 SET/RESET switch bit
of FLD output control register (bit 7 of address 0EFC 16) is “0”,
RAM data is output to the FLD output ports (SET) at the time that
is set by TOFF1 and it is turned to “0” (RESET) at the time that is
set by TOFF2.
When Toff2 SET/RESET switch bit is “1”, RAM data is output
(SET) at the time that is set by TOFF2 and it is turned to “0” (RESET) when the Tdisp time expires.
■ Note
In the case of gradation display mode and dark display, the Toff
section generate/nothing function is disabled.
38B7 Group User’s Manual
1-59
HARDWARE
FUNCTIONAL DESCRIPTION
Digit Pulses Output Function
This function is effective in 16-timing•ordinary mode and 16-timing
gradation display mode. If a value is set exceeding the timing
count (FLD data pointer reload register’s set value + 1) for any
port, the output of such port is “L”.
P00 to P07 and P20 to P27 can output digit pulses by using the
digit output set switch registers. Set the digit output set switch registers by setting as many consecutive 1s as the timing count from
P20. The contents of FLD automatic display RAM for the ports that
have been selected for digit output are disabled, and the pulse
shown in Figure 59 is output automatically.
The output timing consists of Tdisp time and Toff1 time, and Toff2
time does not exist.
Because the contents of FLD automatic display RAM are disabled, the segment data can be changed easily even when
segment data and digit data coexist at the same address in the
FLD automatic display RAM.
Tdisp
Toff1
P 07
P 06
P 05
P 04
P 03
P 02
P 01
P 00
P27
P 26
P 25
P 24
P23
P22
P 21
P 20
Low-order 4bits
of the data pointer
F
E
D
C
B
A
9
8
7
Fig. 59 Digit pulses output function
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HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
The 38B7 group has a 10-bit A-D converter. The A-D converter
performs successive approximation conversion.
Note that the comparator is constructed linked to a capacitor, so
that set f(XIN) to at least 250 kHz during A-D conversion. Additionally, bit 7 of the CPU mode register (address 003B16 ) must be set
to “0”.
[A-D Conversion Register] ADH, ADL
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the A-D conversion register (high-order) (address
0034 16), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the A-D conversion register (low-order) (address
003316 ).
During A-D conversion, do not read these registers.
b7 b6 b5 b4 b3 b2 b1 b0
b3b2b1b0
0 0 0 0 : PA0/AN0
0 0 0 1 : PA1/AN1
0 0 1 0 : PA2/AN2
0 0 1 1 : PA3/AN3
0 1 0 0 : PA4/AN4
0 1 0 1 : PA5/AN5
0 1 1 0 : PA6/AN6
0 1 1 1 : PA7/AN7
1 0 0 0 : P90/SIN3/AN8
1 0 0 1 : P91/SOUT3/AN9
1 0 1 0 : P92/SCLK3/AN10
1 0 1 1 : P93/SRDY3/AN11
1 1 0 0 : P94/RTP1/AN12
1 1 0 1 : P95/RTP0/AN13
1 1 1 0 : P96/PWM0/AN14
1 1 1 1 : P97/BUZ02/AN15
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
DA output enable bit
0 : DA output disabled
1 : DA output enabled
Not used (returns “0” when read)
[AD/DA Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input
pin selection bits. Bit 4 is an AD conversion completion bit and “0”
during A-D conversion. This bit is set to “1” upon completion of AD conversion.
A-D conversion is started by writing “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVss and VREF by 1024, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports PA7/AN7 –PA0 /
AN0 , and P9 7/B UZ02/AN15 to P90 /SIN3/AN8 and inputs it to the
comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog
inputvoltage with the comparison voltage and stores the result in
the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit
and the AD conversion interrupt request bit to “1”.
AD/DA control register
(ADCON: address 003216)
Analoginput pin selection bits
AD conversion register (high-order)
(ADH: address 003416)
b7
AD conversion register (low-order)
(ADL: address 003316)
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
b0
b1 b0
Note: When reading the low-order 6 bits at address 003316,
“0” is read out.
Fig. 60 Structure of AD/DA control register
Data bus
b7
b0
AD/DA control register
4
A-D control circuit
Comparator
Channel selector
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
P90/SIN3/AN8
P91/SOUT3/AN9
P92/SCLK3/AN10
P93/SRDY3/AN11
P94/RTP1/AN12
P95/RTP0/AN13
P96/PWM0/AN14
P97/BUZ02/AN15
A-D interrupt request
A-D conversion register (H) A-D conversion register (L)
(Address 003416)
(Address 003316)
Resistor ladder
AVSS VREF
Fig. 61 Block diagram of A-D converter
38B7 Group User’s Manual
1-61
HARDWARE
FUNCTIONAL DESCRIPTION
D-A CONVERTER
Data bus
The 38B7 group has one internal D-A converter with 8-bit resolution.
The D-A conversion is performed by setting the value in the D-A
conversion register. The result of D-A conversion is output from
the DA pin by setting the DA output enable bit to “1”.
When using the D-A converter, the PB0/DA port direction register
bit must be set to “0” (input status).
The output analog voltage V is determined by the value n (decimal notation) in the D-A conversion register as follows:
D-A conversion register (8)
R-2R resistor ladder
DA output enable bit
PB0/DA
V = VREF ✕ n/256 (n = 0 to 255)
Where V REF is the reference voltage.
At reset, the D-A conversion register is cleared to “0016”, and the
DA output enable bit is cleared to “0”, and PB0/DA pin becomes
high impedance.
The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load.
Set VCC to 3.0 V or more when using the D-A converter.
“0” DA output enable bit
R
R
Fig. 62 Block diagram of D-A converter
R
R
R
R
R
2R
PB0/DA
“1”
2R
2R
2R
2R
MSB
D-A conversion register
“0”
2R
2R
2R
LSB
“1”
AVSS
VREF
Fig. 63 Equivalent connection circuit of D-A converter
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
PWM (Pulse Width Modulation)
The 38B7 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest assumes XIN = 4 MHz.
Data bus
It is set to “1”
when write.
bit7
PWM register (low-order)
(address 003616)
bit7
bit5
bit0
bit0
PWM register (high-order)
(address 003516)
PWM latch (14-bit)
MSB
LSB
14
P96 latch
P96/PWM0
14-bit PWM circuit
When the internal
XCIN
1/2
system clock
selection bit is set
(64 µs cycle)
Timing
“1”
to “0”
generating
XI N
unit for PWM (4096 µs cycle)
(4MHz) “0”
PWM
P96/PWM output
selection bit
P96/PWM output
selection bit
P96 direction
register
Fig. 64 PWM block diagram
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1-63
HARDWARE
FUNCTIONAL DESCRIPTION
Data Setup
Transfer From Register to Latch
The PWM output pin also function as port P96. Set port P96 to be
the PWM output pin by setting bit 0 of the PWM control register
(address 002616) to “1”. The high-order 8 bits of output data are
set in the high-order PWM register PWMH (address 003516 ) and
the low-order 6 bits are set in the low-order PWM register PWML
(address 003616 ).
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each subperiod (every 64 µs). Pulses output from the PWM output pin
correspond to this latch contents.
When the PWML register is read, the contents of the latch are
read. However, bit 7 of the PWML register indicates whether the
transfer to the PWM latch is completed: the transfer is completed
when bit 7 is “0”, it is not done when bit 7 is “1”.
PWM Operation
The timing of the 14-bit PWM function is shown in Figure 65.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level signal is output during each sub-period. There are 64 sub-periods in
each period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The
signal’s “H” has a length equal to N times τ, and its minimum resolution = 250 ns.
The last bit of the sub-period becomes the ADD bit which is specified either “H” or “L,” by the contents of PWML. As shown in Table
11, the ADD bit is decided either “H” or “L.”
That is, only in the sub-period tm shown in Table 11 in the PWM
cycle period T = 64 t, the “H” duration is lengthened during the
minimum resolution width τ period in comparison with the other
period.
For example, if the high-order eight bits of the 14-bit data are
“0316 ” and the low-order six bits are “0516 ,” the length of the “H”
level output in sub-periods t8, t24, t32, t40 and t56 is 4 τ, and its
length 3 τ in all other sub-periods.
Time at the “H” level of each sub-period almost becomes equal
because the time becomes length set in the high-order 8 bits or
becomes the value plus t, and this sub-period t (= 64 µs, approximate 15.6 kHz) becomes cycle period approximately.
Table 11 Relationship between low-order 6-bit data and setting
period of ADD bit
Low-order
Sub-periods tm lengthened (m = 0 to 63)
6-bit data
LSB
000000
000001
000010
000100
001000
None
010000
100000
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
4096 µs
64 µs
64 µs
m=0
15.75 µs
m=7
15.75 µs
15.75 µs
64 µs
m=8
16.0 µs
64 µs
64 µs
m=9
15.75 µs
m = 63
15.75 µs
15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
Fig. 65 PWM timing
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON: address 002616)
P96/PWM0 output selection bit
0: I/O port
1: PWM0 output
Not used (return “0” when read)
Fig. 66 Structure of PWM control register
Data 6A16 stored at address 003516
PWM register
(high-order)
5916
Data 7B16 stored at address 003516
6A16
7B16
Data 2416 stored at address 003616
PWM register
(low-order)
1316
Bit 7 cleared after transfer
A416
Data 3516 stored at address 003616
2416
3516
Transfer from register to latch
PWM latch
(14-bit)
165316
1A9316
Transfer from register to latch
B516
1AA416
1AA416
1EE416
1EF516
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
6A
(Example 1)
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
5
2
5
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
PWM output
1
Low-order 6-bits
output
H = 6A16
L = 2416
5
5
5
6B16............36 times
(107)
6A
(Example 2)
5
6A
6A
6A
6B
6A
5
5
6A16............28 times
(106)
6B
6A
6B
6A
6A
6A
5
106 ✕ 64
6B
6A
6B
6A
6B
5
5
5
5
5
36
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
PWM output
Low-order 6 bits
output
H = 6A16
L = 1816
4
3
4
6B16............24 times
4
3
4
6A16............40 times
4
106 ✕ 64
3
4
24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum bit width
PWM output
6B
τ = 0.25 µs
6A
69
68
67
………
02
01
6A
69
68
67
………
02
01
FF
FE
FD
FC
………
97
96
2
ADD
8-bit counter
02
01
The ADD portions with
additional τ are determined
either “H” or “L” by low-order
6-bit data.
00
ADD
FF
FE
FD
FC
………
97
96
95
………
02
01
00
95
………
“H” period length specified by PWMH
256
τ (64 µs), fixed
Fig. 67 14-bit PWM timing
38B7 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPT INTERVAL DETERMINATION FUNCTION
Noise Filter
The 38B7 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising edge (falling edge) of an input signal pulse on the P72 /
INT2 pin to the rising edge (falling edge) of the signal pulse that is
input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
2. Set bit 0 of the interrupt interval determination control register
(address 003116) to “1” (interrupt interval determination operating).
3. Select the sampling clock of 8-bit binary up counter by setting
bit 1 of the interrupt interval determination control register.
4. When the signal of polarity which is set on the INT2 pin (rising
or falling edge) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock.
5. When the signal of polarity selected above is input again, the
value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 003016 ), and the
remote control interrupt request occurs. Immediately after that,
the 8-bit binary up counter continues to count up again from
“0016 ”.
6. When count value reaches “FF16 ”, the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF16” to the interrupt interval determination register to generate the counter
overflow interrupt request.
The P72/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00 16”.
2. The P7 2/INT 2 input signal is sampled in synchronization with
the selected clock. When sampling the same level signal in a
series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs.
Counter sampling
clock selection bit
1/1
Internal system
clock selection bit
f(XIN)/128
f(XCIN)
Divider
1/2
Noise filter
INT2 interrupt input
When setting bit 4 of interrupt interval determination control register to “1”, the interrupt request can occur at both rising and falling
edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
8-bit binary up
counter
Interrupt interval
determination register
address 003016
Noise filter sampling
clock selection bit
1/1
One-sided/both-sided
edge detection
selection bit
1/4
1/2
Divider
f(XIN)/32
f(XCIN)
Internal system
clock selection bit
Fig. 68 Interrupt interval determination circuit block diagram
1-66
38B7 Group User’s Manual
Data bus
Counter overflow
interrupt request
or remote control
interrupt request
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Interrupt interval determination control register
(IIDCON: address 003116)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/128 or f(XCIN)
1 : f(XIN)/256 or f(XCIN)/2
Noise filter sampling clock selection bits (INT2)
b3b2
0 0 : Filter stop
0 1 : f(XIN)/32 or f(XCIN)
1 0 : f(XIN)/64 or f(XCIN)/2
1 1 : f(XIN)/128 or f(XCIN)/4
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
(Do not write “1” to these bits.)
Fig. 69 Structure of interrupt interval determination control register
(When IIDCON4 = “0”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
N
8-bit binary up
counter value
0
1
3
2
5
4
0
3
2
1
FF
~
~
0
N
FF
6
Counter overflow
interrupt request
Remote control
interrupt request
Remote control
interrupt request
1
FF
6
N
Interrupt interval
determination
register value
FE
6
Fig. 70 Interrupt interval determination operation example (at rising edge active)
(When IIDCON4 = “1”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
FE
N
8-bit binary up
counter value
0
1
N
Interrupt interval
determination
register value
2
0
2
N
Remote control
interrupt request
2
1
0
2
1
3
2
Remote control
interrupt request
3
0
1
2
2
Remote control
interrupt request
0
1
FF
2
3
Remote control
interrupt request
FF
FF
Counter overflow
interrupt request
Fig. 71 Interrupt interval determination operation example (at both-sided edge active)
38B7 Group User’s Manual
1-67
HARDWARE
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an
8-bit watchdog timer L and a 8-bit watchdog timer H.
Standard Operation Of Watchdog Timer
When any data is not written into the watchdog timer control register (address 0EEE 16) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register may be started before an underflow. When the watchdog timer control register is read, the
values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection
bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
0EEE16), a watchdog timer H is set to “FF 16” and a watchdog
timer L to “FF16”.
(2) Watchdog timer H count source selection
bit operation
Bit 7 of the watchdog timer control register (address 0EEE16 ) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the underflow signal of watchdog timer L becomes the
count source. The detection time is set to 131.072 ms at f(X IN) = 4
MHz frequency, and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal divided by 8 for f(X IN ) or divided by 16 for f(X CIN). The detection
time in this case is set to 512 µs at f(X IN) = 4 MHz frequency, and
128 ms at f(XCIN ) = 32 kHz frequency.
This bit is cleared to “0” after reset.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0EEE16 ) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
If the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after reset.
■ Note
When releasing the stop mode, the watchdog timer performs its
count operation even in the stop release waiting time. Be careful
not to cause the watchdog timer H to underflow in the stop release
waiting time, for example, by writing any data in the watchdog
timer control register (address 0EEE16 ) before executing the STP
instruction.
XCIN
1/2
“1”
Internal system clock
selection bit
(Note)
“0”
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“0”
Watchdog timer L (8)
1/8
“1”
Watchdog timer H (8)
“FF16” is set
when watchdog
timer control
register is written
to.
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 72 Block diagram of watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 0EEE16)
Watchdog timer H (for read-out of high-order 6 bits)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Fig. 73 Structure of watchdog timer control register
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38B7 Group User’s Manual
Internal reset
HARDWARE
FUNCTIONAL DESCRIPTION
BUZZER OUTPUT CIRCUIT
Note: In the low-speed mode, a buzzer output is made OFF.
The 38B7 group has a buzzer output circuit. One of 1 kHz, 2 kHz
and 4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the
buzzer output control register (address 0EFD16). Either P77/BUZ01
or P97/B UZ02/AN15 can be selected as a buzzer output port by the
output port selection bits (b2 and b3 of address 0EFD16 ).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Port latch
f(XIN)
Divider
1/1024
1/2048
1/4096
Buzzer output
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 74 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register
(BUZCON: address 0EFD16)
Output frequency selection bits (XIN = 4.19 MHz)
b1b0
0 0 : 1 kHz (f(XIN)/4096)
0 1 : 2 kHz (f(XIN)/2048)
1 0 : 4 kHz (f(XIN)/1024)
1 1 : Not available
Output port selection bits
b3b2
0 0 : P77 and P97 function as ordinary ports.
0 1 : P77/BUZ01 functions as a buzzer output.
1 0 : P97/BUZ02/AN15 functions as a buzzer output.
1 1 : Not available
Buzzer output ON/OFF bit
b4
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (returns “0” when read)
Fig. 75 Structure of buzzer output control register
38B7 Group User’s Manual
1-69
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 2.7 V and 5.5
V, and the oscillation should be stable), reset is released. After the
reset is completed, the program starts from the address contained
in address FFFD 16 (high-order byte) and address FFFC16 (loworder byte). Make sure that the reset input voltage is less than
0.54 V for Vcc of 2.7 V (switching to the high-speed mode, a
power source voltage must be between 4.0 V and 5.5 V).
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 76 Reset circuit example
XIN
φ
RESET
Internal
reset
?
Address
?
?
?
FFFC
FFFD
ADL
Data
ADH, ADL
ADH
SYNC
XIN: about 4000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=4 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 77 Reset sequence
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
(1) Port P0
000016
0016
(38) D-A conversion register
002B16
0016
(2) Port P1
000216
0016
(39) Timer X (low-order)
002C16
FF16
(3) Port P1 direction register
000316
0016
(40) Timer X (high-order)
002D16
FF16
(4) Port P2
000416
0016
(41) Timer X mode register 1
002E16
0016
(5) Port P3
000616
0016
(42) Timer X mode register 2
002F16
0016
(6) Port P3 direction register
000716
0016
003016
0016
(7) Port P4
000816
0016
003116
0016
(8) Port P4 direction register
000916
0016
(43) Interrupt interval determination
register
(44) Interrupt interval determination
control register
(45) AD/DA control register
003216
1016
(9) Port P5
000A16
0016
(46) UART control register
003816
8016
(10) Port P5 direction register
000B16
0016
(47) Interrupt source switch register
003916
0016
(11) Port P6
000C16
0016
(48) Interrupt edge selection register
003A16
0016
(12) Port P6 direction register
000D16
0016
(49) CPU mode register
003B16 0 1 0 0 1 0 0 0
(13) Port P7
000E16
0016
(50) Interrupt request register 1
003C16
0016
(14) Port P7 direction register
000F16
0016
(51) Interrupt request register 2
003D16
0016
(15) Port P8
001016
0016
(52) Interrupt control register 1
003E16
0016
(16) Port P8 direction register
001116
0016
(53) Interrupt control register 2
003F16
0016
(17) Port P9
001216
0016
(54) Serial I/O3 control register
0EEC16
0016
(18) Port P9 direction register
001316
0016
(55) Watchdog timer control register
0EEE16
3F16
(19) Port PA
001416
0016
(56) Pull-up control register 3
0EEF16
0016
(20) Port PA direction register
001516
0016
(57) Pull-up control register 1
0EF016
0016
0016
(21) Port PB
001616
0016
(58) Pull-up control register 2
0EF116
(22) Port PB direction register
001716
0016
0EF216
0016
(23) Serial I/O1 control register 1
001916
0016
0EF316
0016
(24) Serial I/O1 control register 2
001A16
0016
(59) Port P0 digit output set switch
register
(60) Port P2 digit output set switch
register
(61) FLDC mode register
0EF416
0016
(25) Serial I/O1 control register 3
001C16
0016
(62) Tdisp time set register
0EF516
0016
(26) Serial I/O2 control register
001D16
0016
(63) Toff1 time set register
0EF616
FF16
(27) Serial I/O2 status register
001E16
8016
(64) Toff2 time set register
0EF716
FF16
(28) Timer 1
002016
FF16
(65) Port P4 FLD/Port switch register 0EF916
0016
(29) Timer 2
002116
0116
(66) Port P5 FLD/Port switch register 0EFA16
0016
(30) Timer 3
002216
FF16
(67) Port P6 FLD/Port switch register 0EFB16
0016
(31) Timer 4
002316
FF16
(68) FLD output control register
0EFC16
0016
(32) Timer 5
002416
FF16
(69) Buzzer output control register
0EFD16
0016
(33) Timer 6
002516
FF16
(70) Flash memory control register
0EFE16
0016
(34) PWM control register
002616
0016
(71) Flash command register
0EFF16
0016
(35) Timer 12 mode register
002816
0016
(72) Processor status register
(36) Timer 34 mode register
002916
0016
(73) Program counter
(37) Timer 56 mode register
002A16
0016
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
✕: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 78 Internal status at reset
38B7 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
Oscillation Control
The 38B7 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT or XCIN and XCOUT. Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops
at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16 ” and timer 2 is set to “01 16”.
Either XIN divided by 8 or X CIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2.
The bits of the timer 12 mode register are cleared to “0”. Set the
interrupt enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts when an
external interrupt is received, but the internal system clock is not
supplied to the CPU until timer 2 underflows. This allows time for
the clock circuit oscillation to stabilize.
Frequency Control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. After reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops
at an “H” level. The states of XIN and XCIN are the same as the
state before executing the WIT instruction. The internal system
clock restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immediately after the clock is restarted.
■ Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3 • f(XCIN ).
XCIN
XCOUT
Rf
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
the main clock stop bit (bit 5) of the CPU mode register to “1”.
When the main clock XIN is restarted (by setting the main clock
stop bit to “0”), set enough time for oscillation to stabilize.
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 79 Ceramic resonator circuit
XCIN
XCOUT
open
XIN
open
External oscillation circuit
External oscillation circuit
or external pulse
VCC
VCC
VSS
VSS
Fig. 80 External clock input circuit
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38B7 Group User’s Manual
XOUT
HARDWARE
FUNCTIONAL DESCRIPTION
XCOUT
XCIN
“0”
“1”
Port XC
switch bit (Note 3)
1/2
XOUT
XIN
Timer 2 count source
selection bit (Note 2)
Timer 1 count source
selection bit (Note 2)
Internal system clock
selection bit (Notes 1, 3)
“1”
Low-speed mode
Timer 1
“1”
1/4
1/2
“0”
Timer 2
“0”
“0”
“1”
High-speed or
middle-speed
mode
Main clock division ratio
selection bits (Note 3)
Middle-speed mode
“1”
Timing φ (internal clock)
“0”
Main clock stop bit
(Note 3)
Q
High-speed or
low-speed mode
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1”.
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 81 Clock generating circuit block diagram
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset
C M4
“1”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
“0
”
4 “0”
CM
6
0”
”
M “
“1 C
”
“1
Middle-speed mode
(φ =1 MHz)
“0”
“1
”
CM
4
CM
“1
”
6
“0
”
High-speed mode
(φ =4 MHz)
CM6
“1”
“0”
C M7
“1”
“1”
C M7
“0”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0”
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
High-speed mode
(φ =4 MHz)
C M4
CM6
“1”
“1”
Middle-speed mode
(φ =1 MHz)
5
C
M
“0
”
”
“0
6
CM
”
“1
“1
”
”
“0
CM
CM
6
“0
”
Low-power dissipation mode
(φ =16 kHz)
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
5
“1
”
Low-power dissipation mode
(φ =16 kHz)
CM6
“1”
b7
“0”
“0”
“1”
”
“1
“0”
C M5
“1”
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
C M5
Low-speed mode
(φ =16 kHz)
CM6
“1”
Low-speed mode
(φ =16 kHz)
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(XIN) (High-speed mode)
1: f(XIN)/4 (Middle-speed mode)
CM7: Internal system clock selection bit
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal system clock.
Fig. 82 State transitions of system clock
1-74
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Power Dissipation Calculating Method
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a ✕ c)
• Total number of built-in resistor: for digit, f; for segment, g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
(1) Digit pin power dissipation
{h ✕ b ✕ (1 – Toff / Tdisp) ✕ voltage} / a
(2) Segment pin power dissipation
{i ✕ d ✕ (1–Toff / Tdisp) ✕ voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit ✕ (b ✕ f / b) ✕ (1–Toff / Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment ✕ (d ✕ g / c) ✕ (1–Toff /
Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 190 mW
(1) + (2)+ (3) + (4) + (5) = X mW
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HARDWARE
FUNCTIONAL DESCRIPTION
Power Dissipation Calculating Example 1
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µs = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 ✕ 20)
• Total number of built-in resistor: for digit, 16; for segment, 20
• Digit pin current value 18 (mA)
• Segment pin current value 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 16 ✕ (1 – 1 / 16) ✕ 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 ✕ 31 ✕ (1– 1 / 16) ✕ 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
[{45 – 2} 2/ 48 ✕ (16 ✕ 16 / 16) ✕ (1 – 1 / 16)] / 17 = 33.94 mW
(4) Pull-down resistor power dissipation (segment)
[{45 – 2} 2/ 48 ✕ (31 ✕ 20 / 20) ✕ (1 – 1 / 16)] / 17 = 65.86 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 75 mW
(1) + (2)+ (3) + (4) + (5) = 217 mW
DIG0
DIG1
DIG2
DIG3
DIG13
DIG14
DIG15
Timing
number
1
2
14
3
15
16
17
Repeat cycle
Tscan
Fig. 83 Digit timing waveform (1)
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HARDWARE
FUNCTIONAL DESCRIPTION
Power Dissipation Calculating Example 2
(2 or more digits turned ON at the same time)
(1) Digit pin power dissipation
{18 ✕ 12 ✕ (1 – 1 / 16) ✕ 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 ✕ 114 ✕ (1– 1 / 16) ✕ 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
[{45 – 2}2/ 48 ✕ (12 ✕ 10 / 12) ✕ (1 – 1 / 16)] / 11 = 32.84 mW
(4) Pull-down resistor power dissipation (segment)
[{45 – 2}2/ 48 ✕ (114 ✕ 22 / 24) ✕ (1 – 1 / 16)] / 11 = 343.08 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 75 mW
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µs = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 ✕ 24)
• Total number of built-in resistor: for digit, 10; for segment, 22
• Digit pin current value 18 (mA)
• Segment pin current value 3 (mA)
(1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
Timing
number
1
2
3
4
5
6
7
8
9
10
11
Repeat cycle
Tscan
Fig. 84 Digit timing waveform (2)
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1-77
HARDWARE
FUNCTIONAL DESCRIPTION
FLASH MEMORY MODE
Functional Outline (parallel input/output mode)
The M38B79FF has the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this
mode to perform read, program, and erase operations for the internal flash memory.
The M38B79FF has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash
memory is handled by using the external programmer, and the
CPU reprogramming mode, where the flash memory is handled by
the central processing unit (CPU). The following explains these
modes.
In the parallel input/output mode, the M38B79FF allow the user to
choose an operation mode between the read-only mode and the
read/write mode (software command control mode) depending on
the voltage applied to the VPP pin. When V PP = VPP L, the readonly mode is selected, and the user can choose one of three
states ___
(e.g.,___
read, output
disable, or standby) depending on inputs
___
to the CE, OE, and WE pins. When VPP = V PP H, the read/write
mode is selected, and the user can choose one of four states
(e.g., read,
output disable,
standby, or write) depending on inputs
__ __
___
to the CE, OE, and WE pins. Table 13 shows assignment states of
control input and each state.
(1) Flash memory mode 1 (parallel I/O mode)
● Read
__
The
microcomputer enters
the read state by driving the CE, and
__
___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0–A16 ) are output to the data input/output pins (D0–D7 ).
The parallel I/O mode can be selected by connecting wires as
shown in Figures 85 and supplying power to the VCC and V PP
pins. In this mode, the M38B79FF operates as an equivalent of
MITSUBISHI’s CMOS flash memory M5M28F101. However, because the M38B79FF’s internal memory has a capacity of 60
Kbytes, programming is available for addresses 0100016 to
0FFFF16, and make sure that the data in addresses 0000016 to
00FFF16 and addresses 10000 16 to 1FFFF16 are FF16 . Note also
that the M38B79FF does not contain a facility to read out a device
identification code by applying a high voltage to address input
(A9 ). Be careful not to erratically set program conditions when using a general-purpose PROM programmer.
Table 12 shows the pin assignments when operating in the parallel input/output mode.
● Output disable
The
microcomputer___
enters the
output disable state by driving the
__
__
CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state.
● Standby
__
The microcomputer enters the standby state by driving the CE pin
high. The M38B79FF is placed in a power-down state consuming
only a minimal supply current. At this time, the data input/output
pins enter the floating state.
Table 12 Pin assignments of M38B79FF when operating in
the parallel input/output mode
VCC
VPP
VSS
Address input
Data
I/O
__
CE
___
OE
___
WE
M38B79FF
VCC
CNVSS
VSS
Ports P0, P1, P3 1
Port P2
P36
P37
P33
● Write
The microcomputer enters the write
state by driving the__
VPP pin
___
high (VPP = __
V PP H) and then the WE pin low when the CE pin is
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this software command.
M5M28F101
VCC
VPP
VSS
A0–A16
D0__
–D7
CE
__
OE
___
WE
Table 13 Assignment states of control input and each state
Pin
Mode
Read-only
Read/Write
State
Read
Output disable
Standby
Read
Output disable
Standby
Write
__
__
___
CE
OE
WE
VPP
Data I/O
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
×
VIL
VIH
×
VIH
VIH
VIH
×
VIH
VIH
×
VIL
VPPL
VPPL
VPPL
VPP H
VPP H
VPP H
VPP H
Output
Floating
Floating
Output
Floating
Floating
Input
Note: × can be VIL or VIH.
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Table 14 Pin description (flash memory parallel I/O mode)
Pin
Name
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
I/O
VCC, VSS
CNV
SS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20 –P27
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Address input (A0–A7)
Address input (A8–A15)
Data I/O (D0–D7)
P30–P37
Control signal input
Input
P40–P47
P50 –P57
P60 –P67
Input port P4
Input port P5
Input port P6
Input
Input
Input
P70 –P77
P80–P83
P90–P97
PA0–PA7
PB0–PB6
VEE
Input port P7
Input port P8
Input port P9
Input port PA
Input port PB
Pull-down power supply
Input
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 5 V ± 10 % in read-only mode, connect to 11.7 V to 12.6 V in read/write mode.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Connect to VSS.
Port P0 functions as 8-bit address input (A0–A7).
Port P1 functions as 8-bit address input (A8–A15).
Function as 8-bit data’s I/O pins (D0–D 7).
Connect them to Vss through each resistor of 6.8 kΩ.
P37, P36 and P33 function as the OE, CE and WE input pins respectively. P3 1 functions as
the A16 input pin. Connect P30 and P32 to VSS. Input “H” or “L” to P34, P35, or keep
them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Connect P64 and P6 6 to VSS. Input “H” or “L” to P60 –P63, P6 5, P67, or keep them
open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Keep this open.
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1-79
HARDWARE
CE
OE
WE
A15
A16
A14
A12
A13
A9
A11
A10
A8
A7
A6
A5
A4
A2
A3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
A0
A1
FUNCTIONAL DESCRIPTION
6.8 kΩ
*P27/FLD7
*P26/FLD6
*P25/FLD5
D4
*P24/FLD4
D3
*P23/FLD3
D2
*P22/FLD2
D1
*P21/FLD1
D0
*P20/FLD0
VE E
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/SVIN/DA
AVSS
VREF
PA7/AN7
PA6/AN6
D7
D6
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M38B79FFFP
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
Vpp
C N VS S
RESET
P81/XCOUT
P80/XCIN
VS S
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D5
Vcc
Vss
✱
✱ :Connect to the ceramic oscillation circuit.
* : High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode
1-80
38B7 Group User’s Manual
indicates the flash memory pin.
HARDWARE
FUNCTIONAL DESCRIPTION
Read-only Mode
shown in Figure 86, and the M38B79FF will output the contents of
the user’s specified address from data I/O pin to the external. In
this mode, the user cannot perform any operation other than read.
The microcomputer enters the read-only mode by applying VPPL
to the V PP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
VIH
Address
Valid address
VIL
tRC
VIH
CE
VIL
ta(CE)
VIH
OE
VIL
tWRR
tDF
VIH
WE
VIL
VOH
Data
ta(OE)
tDH
tOLZ
Floating
Dout
tCLZ
VOL
Floating
ta(AD)
Fig. 86 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPP H
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38B79FF executes the
specified operation.
Table 15 shows the software commands and the input/output information in the first and the second cycles. The
input address is
___
latched internally at the falling edge of the WE input; software
commands ___
and other input data are latched internally at the rising
edge of the WE input.
The following explains each software command. Refer to Figures 87
to 89 for details about the signal input/output timings.
Table 15 Software command (parallel input/output mode)
Symbol
Read
Program
Program verify
Erase
Erase verify
Reset
Device identification
First cycle
Address input
×
×
×
×
Verify address
×
×
Data input
0016
4016
C0 16
2016
A016
FF16
9016
Second cycle
Address input
Data I/O
Read address
Read data (Output)
Program address
Program data (Input)
×
Verify data (Output)
×
2016 (Input)
×
Verify data (Output)
×
FF16 (Input)
ADI
DDI (Output)
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 00001 16
DDI = Device identification data : manufacturer’s code 1C16, device code D0 16
× can be V IL or VIH.
38B7 Group User’s Manual
1-81
HARDWARE
FUNCTIONAL DESCRIPTION
● Read command
The microcomputer enters the read mode by inputting command
code “0016” in the first cycle. The command code is latched
into
___
the internal command latch at the rising edge of the WE input.
When the address of a memory location to be read is input in the
second cycle, with control signals input at the timing shown in
Figure 87, the M38B79FF outputs the contents of the specified address from the data I/O pins to the external.
The read mode is retained until any other command is latched into
the command latch. Consequently, once the M38B79FF enters the
read mode, the user can read out the successive memory contents
simply by changing the input address and executing the second
cycle only. Any command other than the read command must be input beginning from its command code over again each time the user
execute it. The contents of the command latch immediately after
power-on is 0016 .
VIH
Address
Valid address
VIL
tWC
tRC
VIH
CE
VIL
tCH
ta(CE)
tCS
VIH
OE
VIL
tRRW
tWP
tWRR
tDF
VIH
WE
VIL
ta(OE)
tDS
VIH
Data
tOLZ
0016
VIL
tDH
tVSC
tCLZ
ta(AD)
VPPH
VPP
VPPL
Fig. 87 Timings during reading
1-82
38B7 Group User’s Manual
Dout
tDH
HARDWARE
FUNCTIONAL DESCRIPTION
● Program command
The microcomputer enters the program mode by inputting command code “4016 ” in the first cycle. The command code ___
is latched
into the internal command latch at the rising edge of the WE input.
When the address which indicates a program location and data is
input in the second cycle, the M38B79FF
internally latches the ad___
dress at the___
falling edge of the WE input and the data at the rising
edge of the WE input.
The M38B79FF starts programming at the
___
rising edge of the WE input in the second cycle and finishes progr amming within 10 µs as measured by its internal timer.
Programming is performed in units of bytes.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 90 for the programming flowchart.
● Program verify command
The microcomputer enters the program verify mode by inputting
command code “C016 ” in the first cycle. This command is used to
verify the programmed data after executing the program command. The command code is ___
latched into the internal command
latch at the rising edge of the WE input. When control signals are
input in the second cycle at the timing shown in Figure 88, the
M38B79FF outputs the programmed address’s contents to the external. Since the address is internally latched when the program
command is executed, there is no need to input it in the second
cycle.
Program verify
VIH
Program
address
Address
VIL
tAS
tWC
Program
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDP
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
4016
Data
VIL
DIN
tDH
C016
tDH
Dout
tDH
Verify data output
tVSC
VPPH
VPP
VPPL
Fig. 88 Input/output timings during programming (Verify data is output at the same timing as for read.)
38B7 Group User’s Manual
1-83
HARDWARE
FUNCTIONAL DESCRIPTION
● Erase command
The erase command is executed by inputting command code 2016
in the first cycle and command code 2016 again in the second
cycle. The command code is latched
into the internal command
___
latch at the rising edges of the WE input in the first cycle and in
the second cycle, respectively.
The erase operation is initiated at
___
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 90
for the erase flowchart.
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
A016 in the first cycle.
The address is internally latched at the fall___
ing edge of the WE input, and the
command code is internally
___
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 89, the
M38B79FF outputs the contents of the specified address to the
external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
Erase verify
VIH
Address
Erase
VIL
Verify
address
tAS
tWC
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDE
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
2016
Data
2016
A016
VIL
tVSC
tDH
tDH
tDH
VPPH
VPP
VPPL
Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for read.)
1-84
Dout
Verify data output
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
● Reset command
The reset command provides a means of stopping execution of
the erase or program command safely. If the user inputs command
code FF 16 in the second cycle after inputting the erase or program
command in the first cycle and again input command code FF16 in
the third cycle, the erase or program command is disabled (i.e.,
reset), and the M38B79FF is placed in the read mode. If the reset
command is executed, the contents of the memory does not
change.
● Device identification code command
By inputting command code 9016 in the first cycle, the user can
read out the device identification code. The command code is
latched into the internal command latch at the rising edge of the
___
WE input. At this time, the user can read out manufacture’s code
1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input
pins in the second cycle; the user can read out device code D016
(i. e., 1M-bit flash memory) by inputting 000116 .
These command and data codes are input/output at the same timing as for read.
38B7 Group User’s Manual
1-85
HARDWARE
FUNCTIONAL DESCRIPTION
Program
Erase
START
START
VCC = 5 V, VPP = VPPH
VCC = 5 V, VPP = VPPH
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
DURATION = 10 µs
X=X+1
WRITE PROGRAM-VERIFY
COMMAND
C016
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
DURATION = 9.5 ms
DURATION = 6 µs
YES
X=X+1
X = 25 ?
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
FAIL
YES
X = 1000 ?
NO
INC ADRS
A016
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
0016
VERIFY BYTE ?
FAIL
PASS
VPP = VPPL
NO
INC ADRS
DEVICE
PASSED
DEVICE
FAILED
LAST ADRS ?
YES
WRITE READ COMMAND
0016
VPP = VPPL
DEVICE
PASSED
Fig. 90 Programming/Erasing algorithm flow chart
1-86
38B7 Group User’s Manual
DEVICE
FAILED
HARDWARE
FUNCTIONAL DESCRIPTION
Table 16 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Symbol
Parameter
Test conditions
__
ISB1
ISB2
VCC supply current (at read)
ICC2
ICC3
VCC supply current (at program)
VCC supply current (at erase)
IPP1
VPP supply current (at read)
IPP2
IPP3
VIL
VIH
VOH1
VOH2
VPPL
VPPH
VPP supply current (at program)
VPP supply current (at erase)
“L” input voltage
“H” input voltage
“H” output voltage
Limits
Typ.
VCC = 5.5 V, CE = VIH
V
CC = 5.5 V,
__
CE = VCC ± 0.2
V
__
VCC = 5.5 V, CE = VIL,
tRC = 150 ns, I OUT = 0 mA
VPP = VPPH
VPP = VPPH
0≤VPP≤VCC
VCC <VPP≤VCC + 1.0 V
VPP = VPPH
VPP = VPPH
VPP = VPPH
VCC supply current (at standby)
ICC1
Min.
I OH = –400 µA
I OH = –100 µA
VPP supply voltage (read only)
VPP supply voltage (read/write)
0
0.52Vcc
2.4
VCC –0.4
VCC
11.7
12.0
Max.
1
100
Unit
mA
µA
15
mA
15
15
10
100
100
30
30
0.2Vcc
VCC
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
V
VCC + 1.0
12.6
AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Table 17 Read-only mode
Symbol
tRC
ta(AD)
ta(CE)
ta(OE)
tCLZ
tOLZ
tDF
tDH
tWRR
Parameter
Read cycle time
Address
access time
__
CE
access
time
__
OE access time
__
Output enable time (after CE)
__
Output enable time (after OE)
__
Output floating time (after
OE)
__ __
Output valid time (after CE, OE, address)
Write recovery time (before read)
Limits
Min.
500
Max.
500
500
200
0
0
70
0
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Table 18 Read/Write mode
Symbol
tWC
tAS
tAH
tDS
tDH
tWRR
t RRW
tCS
tCH
tWP
tWPH
tDP
tDE
tVSC
Parameter
Write cycle time
Address set up time
Address hold time
Data setup time
Data hold time
Write recovery time (before read)
Read
recovery time (before write)
__
CE
setup
time
__
CE hold time
Write pulse width
Write pulse waiting time
Program time
Erase time
VPP setup time
Limits
Min.
300
0
120
100
20
6
0
40
0
120
40
10
9.5
1
Max.
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
Note: Read timing of Read/Write mode is same as Read-only mode.
38B7 Group User’s Manual
1-87
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Flash memory mode 2 (serial I/O mode)
wires as shown in Figures 91 and powering on the VCC pin and
then applying VPP H to the VPP pin.
In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and
error check.
Serial input/output is accomplished synchronously with the clock,
beginning from the LSB (LSB first).
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
OE
The M38B79FF has a function to serially input/output the software
commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a
few pins. This is called the serial I/O (input/output) mode. This
mode can be selected by driving the__SDA (serial data input/output), SCLK (serial clock input ), and OE pins high after connecting
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M38B79FFFP
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
SDA
SCLK
BUSY
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
Vpp
C N VS S
RESET
P81/XCOUT
P80/XCIN
VS S
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
*P27/FLD7
*P26/FLD6
*P25/FLD5
*P24/FLD4
*P23/FLD3
*P22/FLD2
*P21/FLD1
*P20/FLD0
VE E
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/SVIN/DA
AVSS
VREF
PA7/AN7
PA6/AN6
Vcc
Vss
✱
✱ :Connect to the ceramic oscillation circuit.
*: High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode
1-88
38B7 Group User’s Manual
indicates the flash memory pin.
HARDWARE
FUNCTIONAL DESCRIPTION
Table 19 Pin description (flash memory serial I/O mode)
Pin
Name
VCC, VSS
CNV
SS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
P30–P36
P37
P40–P47
P50–P57
P60–P63, P65
P64
P66
P67
P70–P77
P80–P83
P90–P97
PA0–PA7
PB0–PB 6
Input port P3
Control signal input
Input port P4
Input port P5
Input port P6
SDA I/O
SCLK input
BUSY output
Input port P7
Input port P8
Input port P9
Input port PA
Input port PB
Pull-down power supply
VEE
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Output
Input
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 11.7 V to 12.6 V.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Input an arbitrary level between the range of VSS and V CC.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input
“H” or “L”, or keep them open.
__
OE input pin
Input “H” or “L” , or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L” to P60–P63, P6 5, or keep them open.
This pin is for serial data I/O.
This pin is for serial clock input.
This pin is for BUSY signal output.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Keep this open.
38B7 Group User’s Manual
1-89
HARDWARE
FUNCTIONAL DESCRIPTION
Functional Outline (serial I/O mode)
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the
contents of the command. Table 20 shows the software commands used in the serial I/O mode. The following explains each
software command.
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Table 20 Software command (serial I/O mode)
Number of transfers First command
Command
code input
Read
0016
Program
4016
Program verify
C0 16
Erase
2016
Erase verify
A016
Error check
8016
Second
Third
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Verify address L (Input)
Error code (Output)
Fourth
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
__
● Read command
Input command code 0016 in the first transfer. Proceed and input
the low-order
8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the M38B79FF reads out
the contents of the specified address, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the read data that has been
latched into the data latch is serially output from the SDA pin.
tCH
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 0 0 0
Command code input (0016) Read address input (L)
A8
A15
Read address input (H)
tCR
D0
tWR
tRC
Read data output
OE
Read
BUSY “L”
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 92 Timings during reading
1-90
38B7 Group User’s Manual
D7
HARDWARE
FUNCTIONAL DESCRIPTION
● Program command
Input command code 40 16 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the serial clock during program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 µs as measured by the internal timer, and the BUSY pin
is pulled low.
tCH
Note : A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the
verification. Refer to Figure 90 for the programming flowchart.
tCH
tCH
SCLK
tPC
A0
SDA
0 0 0 0 0 0 1 0
Command code input (4016)
A7
A8
D0
A15
Program address input (L) Program address input (H)
D7
Program data input
OE
tWP
Program
BUSY
Fig. 93 Timings during programming
__
● Program verify command
Input__
command code C016 in the first transfer. Proceed and drive
the OE pin low. When this is done, The M38B79FF verify-reads
the programmed address’s contents, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
SCLK
D0
SDA
0 0 0 0 0 0 1 1
Command code input (C016)
D7
Verify data output
tCRPV
tWR
tRC
OE
Verify read
BUSY
“L”
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 94 Timings during program verify
38B7 Group User’s Manual
1-91
HARDWARE
FUNCTIONAL DESCRIPTION
● Erase command
Input command code 2016 in the first transfer and command code
2016 again in the second transfer. When this is done, the
M38B79FF executes an erase command. Erase is initiated at the
last rising edge of the serial clock. The BUSY pin is driven high
during the erase operation. Erase is completed within 9.5 ms as
measured by the internal timer, and the BUSY pin is pulled low.
Note that data 0016 must be written to all memory locations before
executing the erase command.
Note: A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification.
Refer to Figure 90 for the erase flowchart.
tCH
SCLK
tEC
SDA
0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0
Command code input (2016) Command code input (2016)
“H”
OE
twE
BUSY
Erase
Fig. 95 Timings at erasing
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. Input command code A016 in the first
transfer. Proceed and input the low-order
8 bits and the high-order
__
8 bits of the address and pull the OE pin low. When this is done,
the M38B79FF reads out the contents of the specified __
address,
and then latchs it into the internal data latch. When the OE pin is
released back high and serial clock is input to the SCLK pin, the
tCH
verify data that has been latched into the data latch is serially output from the SDA pin.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 1 0 1
Command code input (A016) Verify address input (L)
A8
A15
Verify address input (H)
tCREV
D0
tWR
tRC
D7
Verify data output
OE
Verify read
BUSY “L”
Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 96 Timings during erase verify
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38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
● Error check command
Input command code 8016 in the first transfer, and the M38B79FF
outputs error information from the SDA pin, beginning at the next
falling edge of the serial clock. If the LSB bit of the 8-bit error information is 1, it indicates that a command error has occurred. A
command error means that some invalid commands other than
commands shown in Table 20 has been input.
When a command error occurs, the serial communication circuit
sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the
serial communication circuit does not accept the subsequent serial
clock and data (even including an error check command). Therefore, if the user wants to execute an error check command,
temporarily drop the VPP pin input to the V PPL level to terminate
the serial input/output mode. Then, place the M38B79FF into the
serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands. The error
flag alone is not cleared by this operation, so the user can examine the serial communication circuit’s error conditions before reset.
This examination is done by the first execution of an error check
command after the reset. The error flag is cleared when the user
has executed the error check command. Because the error flag is
undefined immediately after power-on, always be sure to execute
the error check command.
tCH
SCLK
E0
SDA
OE
0 0 0 0 0 0 0 1
Command code input (8016)
? ? ? ? ? ? ?
Error flag output
“H”
BUSY “L”
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
Fig. 97 Timings at error checking
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1-93
HARDWARE
FUNCTIONAL DESCRIPTION
DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, unless otherwise noted)
ICC, IPP-relevant standards during
read, program, and erase are the same as in the parallel input/output mode. V IH, VIL, VOH, VOL , IIH, and
__
IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 21 AC Electrical characteristics
(Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, f(XIN ) = 4 MHz, unless otherwise noted)
Symbol
tCH
tCR
tWR
tRC
tCRPV
tWP
tPC
tCREV
tWE
tEC
tc(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
td(C-Q)
th(C-Q)
th(C-E)
tsu(D-C)
th(C-D)
Limits
Parameter
Min.
625(Note 1)
625(Note 1)
500(Note 2)
625(Note 1)
6
Serial transmission interval
Read waiting time after transmission
Read pulse width
Transfer waiting time after read
Waiting time before program verify
Programming time
Transfer waiting time after programming
Waiting time before erase verify
Erase time
Transfer waiting time after erase
SCLK input cycle time
SCLK high-level pulse width
SCLK low-level pulse width
SCLK rise time
SCLK fall time
SDA output delay time
SDA output hold time
SDA output hold time (only the 8th bit)
SDA input set up time
SDA input hold time
Max.
10
625(Note 1)
6
9.5
625(Note 1)
250
100
100
20
20
90
0
0
187.5 (Note 3) 312.5(Note 4)
30
90
Unit
ns
ns
ns
ns
µs
µs
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When f(XIN ) = 4 MHz or less, calculate the minimum value according to formula 1.
2500
× 106
f(XIN)
2: When f(XIN ) = 4 MHz or less, calculate the minimum value according to formula 2.
Formula 1 :
2000
× 106
f(XIN)
3: When f(XIN ) = 4 MHz or less, calculate the minimum value according to formula 3.
Formula 2 :
750
× 106
f(XIN)
4: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 4
Formula 3 :
Formula 4 :
1250
f(XIN)
× 106
AC waveforms
tf(CK)
tw(CKL)
tc(CK)
tr(CK)
tw(CKH)
SCLK
th(C-Q)
td(C-Q)
th(C-E)
Test conditions for AC characteristics
SDA output
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
tsu(D-C)
th(C-D)
SDA input
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38B7 Group User’s Manual
• Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
HARDWARE
FUNCTIONAL DESCRIPTION
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38B79FF has the CPU reprogramming mode where a builtin flash memory is handled by the central processing unit (CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 98) and the flash command register (see Figure 99).
The CNVSS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
by checking this flag after each command of erase and the program is executed.
Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Only for the specified area, programming is enabled; for
the other areas, programming is disabled.
Figure 100 shows the CPU mode register bit configuration in the
CPU reprogramming mode.
Functional Outline (CPU reprogramming mode)
Figure 98 shows the flash memory control register bit configuration. Figure 99 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to “1” and VPPH is
applied to the CNVss/VPP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
Whether these operations have been completed or not is judged
7
6
0
5
4
3
0
2
1
0
Flash memory control regsiter
(FCON : address 0EFE16)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Fix this bit to “0”.
Erase/Program area select bits
0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes)
0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes)
1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes)
1 1 : Not available
Fix this bit to “0”.
Not used (returns “0” when read)
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 98 Flash memory control register bit configuration
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1-95
HARDWARE
FUNCTIONAL DESCRIPTION
● CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is described below.
< Beginning procedure >
➀ Apply 0 V to the CNVss/VPP pin for reset release.
➁ Set the CPU mode register. (see Figure 100)
➂ After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program).
➃ Set “1” to the CPU reprogramming mode select bit.
➄ Apply VPPH to the CNVSS/VPP pin.
➅ Wait till CNVSS/VPP pin becomes 12 V.
➆ Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
➇ The operation of the flash memory is executed by software-command-writing to the flash command register .
Note: The following are necessary other than this:
•Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
•Initial setting for ports etc.
•Writing to the watchdog timer
< Release procedure >
➀ Apply 0V to the CNV SS/VPP pin.
➁ Wait till CNVSS /VPP pin becomes 0V.
➂ Set the CPU reprogramming mode select bit to “0”.
Each software command is explained as follows.
● Read command
When “00 16” is written to the flash command register, the
M38B79FF enters the read mode. The contents of the corresponding address can be read by reading the flash memory (For
instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
b7
7
6
5
4
3
2
1
Flash command register
(FCMD : address 0EFF16)
<Command code>
• Read command
“0016”
• Program command
“4016”
• Program verify command
“C016”
(CPUM : address 003B16)
Stack page selection bit
0 : 0 page
1 : 1 page
“2016” + “2016”
• Erase verify command
“A016”
• Reset command
“FF16” + “FF16”
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN) (high-speed mode)
0 1 : φ = f(XIN)/4 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Note: The flash command register is write-only register.
1-96
CPU mode register
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
• Erase command
Fig. 99 Flash command register bit configuration
0
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Not available
1 X : Not available
Writing of software command
<Software command name>
b0
0
0
Fig. 100 CPU mode register bit configuration in CPU rewriting
mode
38B7 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
● Program command
When “40 16 ” is written to the flash command register, the
M38B79FF enters the program mode.
Subsequently to this, if the instruction (for instance, STA
instruction) for writing byte data in the address to be programmed
is executed, the control circuit of the flash memory executes the
program. The erase/program busy flag of the flash memory control
register is set to “1” when the program starts, and becomes “0”
when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the
program by polling this bit.
The programmed area must be specified beforehand by the erase/
program area select bits.
During programming, watchdog timer stops with “FFFF16” set.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 101 for the flow chart of the programming.
● Program verify command
When “C016 ” is written to the flash command register, the
M38B79FF enters the program verify mode. Subsequently to this,
if the instruction (for instance, LDA instruction) for reading byte
data from the address to be verified (i.e., previously programmed
address), the contents which has been written to the address actually is read.
CPU compares this read data with data which has been written by
the previous program command. In consequence of the comparison, if not agreeing, the operation of “program → program verify”
must be executed again.
● Erase verify command
When “A0 16” is written to the flash command register, the
M38B79FF enters the erase verify mode. Subsequently to this, if
the instruction (for instance, LDA instruction) for reading byte data
from the address to be verified, the contents of the address is
read.
CPU must erase and verify to all erased areas in a unit of address.
If the address of which data is not “FF 16” (i.e., data is not erased)
is found, it is necessary to discontinue erasure verification there,
and execute the operation of “erase → erase verify” again.
Note: By executing the operation of “erase → erase verify” again
when the memory not erased is found. It is unnecessary to
write data “0016” before erasing in this case.
● Reset command
The reset command is a command to discontinue the program or
erase command on the way. When “FF16 ” is written to the command
register two times continuously after “4016” or “2016” is written to the
flash command register, the program, or erase command becomes
invalid (reset), and the M38B79FF enters the reset mode.
The contents of the memory does not change even if the reset command is executed.
DC Electric Characteristics
Note: The characteristic concerning the flash memory part are the
same as the characteristic of the parallel I/O mode.
AC Electric Characteristics
Note: The characteristics are the same as the characteristic of the
microcomputer mode.
● Erase command
When writing “2016 ” twice continuously to the flash command register, the flash memory control circuit performs erase to the area
specified beforehand by the erase/program area select bits.
Erase/program busy flag of the flash memory control register becomes “1” when erase begins, and it becomes “0” when erase
completes. Accordingly, CPU can recognize the completion of
erase by polling this bit.
Data “0016 ” must be written to all areas to be erased by the program and the program verify commands before the erase
command is executed.
During erasing, watchdog timer stops with “FFFF16 ” set.
Note: The erasing operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 101
for the erasing flowchart.
38B7 Group User’s Manual
1-97
HARDWARE
FUNCTIONAL DESCRIPTION
Program
Erase
START
START
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
WAIT 1µs
NO
ERASE PROGRAM
BUSY FLAG = 0
YES
X=X+1
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
WAIT 1µs
WRITE PROGRAM-VERIFY
COMMAND
C016
NO
ERASE PROGRAM
BUSY FLAG = 0
DURATION = 6 µs
YES
X=X+1
X = 25 ?
YES
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
A016
FAIL
YES
X = 1000 ?
INC ADRS
NO
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
VERIFY BYTE ?
0016
FAIL
PASS
DEVICE
PASSED
DEVICE
FAILED
NO
INC ADRS
LAST ADRS ?
YES
WRITE READ COMMAND
DEVICE
PASSED
Fig. 101 Flowchart of program/erase operation at CPU reprogramming mode
1-98
38B7 Group User’s Manual
0016
DEVICE
FAILED
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before
executing serial I/O transfer and serial I/O automatic transfer.
Automatic Transfer Serial I/O
When using the automatic transfer serial I/O mode of the serial I/
O1, set an automatic transfer interval as the following.
Otherwise the serial data might be incorrectly transmitted/received.
•Set an automatic transfer interval for each 1-byte data transfer as
the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 17 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 27 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V
is recommended. When a D-A converter is not used, set the value
of D-A conversion register to “0016”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is half of the XIN period in highspeed mode.
38B7 Group User’s Manual
1-99
HARDWARE
NOTES ON USAGE/ DATA REQUIRED FOR MASK ORDERS
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (V CC pin) and GND pin (V SS pin), between power
source pin (V CC pin) and analog power source input pin (AV SS
pin), and between program power source pin (CNVss/V PP) and
GND pin for flash memory version when on-board reprogramming
is executed. Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far
from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1
µF is recommended.
Flash Memory Version
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVSS
pin and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVSS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
Flash Memory version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with Flash Memory
version and then switching to use of Mask ROM version, please
perform sufficient evaluations for the commercial samples of Mask
ROM version.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1.Mask ROM Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical copies) or in one floppy disk.
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38B7 Group User’s Manual
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
I/O port
Timer
Serial I/O
FLD controller
A-D converter
D-A converter
PWM
Interrupt interval determination
function
2.9 Watchdog timer
2.10 Buzzer output circuit
2.11 Reset circuit
2.12 Clock generating circuit
2.13 Flash memory
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory assignment
Address
000016
Port P0 (P0)
000116
000216
Port P1 (P1)
000316
Port P1 direction register (P0D)
000416
Port P2 (P2)
000516
000616
Port P3 (P3)
000716
Port P3 direction register (P2D)
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
000A16
000B16
Port P5 (P5)
Port P5 direction register (P5D)
000C16
Port P6 (P6)
000D16
Port P6 direction register (P6D)
000E16
Port P7 (P7)
000F16
Port P7 direction register (P7D)
001016
Port P8 (P8)
001116
Port P8 direction register (P8D)
001216
001316
Port P9 (P9)
001416
Port PA (PA)
001516
Port PA direction register (PAD)
001616
Port PB (PB)
001716
Port PB direction register (PBD)
0EEF16
Pull-up control register 3 (PULL3)
0EF016
Pull-up control register 1 (PULL1)
0EF116
Pull-up control register 2 (PULL2)
Port P9 direction register (P9D)
Fig. 2.1.1 Memory assignment of I/O port relevant registers
2-2
38B7 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0 to 7, 9, A)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1216, 1416)
b
0
1
2
3
4
5
6
7
Name
Port Pi0
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Functions
●In output mode
Write • • • • • • • • Port latch
Read • • • • • • • • Port latch
●In input mode
Write • • • • • • • • Port latch
Read • • • • • • • • Value of pin
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.1.2 Structure of port Pi (i = 0 to 7, 9, A)
Port P8
b7 b6 b5 b4 b3 b2 b1 b0
Port P8
(P8: address 1016)
b
Name
0 Port P80
1 Port P81
2 Port P82
3 Port P83
Functions
●In output mode
Write • • • • • • • • Port latch
Read • • • • • • • • Port latch
●In input mode
Write • • • • • • • • Port latch
Read • • • • • • • • Value of pin
4 Nothing is arranged for these bits. When these
5 bits are read out, the contents are undefined.
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.1.3 Structure of port P8
38B7 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
Port PB
b7 b6 b5 b4 b3 b2 b1 b0
Port PB
(PB: address 1616)
b
0
1
2
3
4
5
6
7
Name
Functions
Port PB0
●In output mode
Port PB1
Write • • • • • • • • Port latch
Port PB2
Read • • • • • • • • Port latch
●In input mode
Port PB3
Write • • • • • • • • Port latch
Port PB4
Read • • • • • • • • Value of pin
Port PB5
Port PB6
Nothing is arranged for this bit. When this bit is
read out, the contents are undefined.
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.1.4 Structure of port PB
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 1, 3 to 7, 9, A)
[Addresses 0316, 0716, 0916, 0B16, 0D16, 0F16, 1316, 1516]
b
Name
0 Port Pi direction
register
1
2
3
4
5
6
7
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Fig. 2.1.5 Structure of port Pi (i = 1, 3 to 7, 9, A) direction register
2-4
38B7 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.1 I/O port
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8 direction register
(P8D: address 1116)
b
Name
Functions
0
2
0
3
4
5
6
7
0 : Port P80 input mode
1 : Port P80 output mode
0 : Port P81 input mode
1 : Port P81 output mode
0 : Port P82 input mode
1 : Port P82 output mode
0 : Port P83 input mode
1 : Port P83 output mode
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
At reset R W
0 Port P8 direction
register
1
0
0
0
0
0
0
Fig. 2.1.6 Structure of port P8 direction register
Port PB direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port PB direction register
(PBD: address 1716)
b
Name
Functions
0 Port PB direction
register
1
0
2
0
3
4
5
6
7
0 : Port PB0 input mode
1 : Port PB0 output mode
0 : Port PB1 input mode
1 : Port PB1 output mode
0 : Port PB2 input mode
1 : Port PB2 output mode
0 : Port PB3 input mode
1 : Port PB3 output mode
0 : Port PB4 input mode
1 : Port PB4 output mode
0 : Port PB5 input mode
1 : Port PB5 output mode
0 : Port PB6 input mode
1 : Port PB6 output mode
Nothing is arranged for this bit. When this bit is
read out, the contents are undefined.
At reset R W
0
0
0
0
0
✕
0
✕ ✕
Fig. 2.1.7 Structure of port PB direction register
38B7 Group User’s Manual
2-5
APPLICATION
2.1 I/O port
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1
(PULL1: address 0EF016)
b
Name
Functions
0: No pull-up
0 Ports P64, P65
1: Pull-up
pull-up control
0: No pull-up
1 Ports P66, P67
1: Pull-up
pull-up control
0: No pull-up
2 Ports P70, P71
1: Pull-up
pull-up control
0: No pull-up
3 Ports P72, P73
pull-up control
1: Pull-up
0: No pull-up
4 Ports P74, P75
pull-up control
1: Pull-up
6
,
P7
7
Ports
P7
0: No pull-up
5
pull-up control
1: Pull-up
6 Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
7 out, the contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.8 Structure of pull-up control register 1
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2
(PULL2: address 0EF116)
b
Name
Functions
0 Ports P80, P81 pull- 0: No pull-up
1: Pull-up
up control
0: No pull-up
Ports
P8
2
,
P8
3
pull1
1: Pull-up
up control
2 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
3 Ports P90, P91 pull- 0: No pull-up
up control
1: Pull-up
4 Ports P92, P93 pull- 0: No pull-up
1: Pull-up
up control
5 Ports P94, P95 pull- 0: No pull-up
1: Pull-up
up control
6 Ports P96, P97 pull- 0: No pull-up
up control
1: Pull-up
Nothing
is
arranged
for
this bit. This is a write
7
disabled bit. When this bit is read out, the
contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.9 Structure of pull-up control register 2
2-6
38B7 Group User’s Manual
APPLICATION
2.1 I/O port
Pull-up control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 3
(PULL3: address 0EEF16)
b
Name
0 Ports PA0, PA1
pull-up control
1 Ports PA2, PA3
pull-up control
2 Ports PA4, PA5
pull-up control
3 Ports PA6, PA7
pull-up control
4 Ports PB0, PB1
pull-up control
5 Ports PB2, PB3
pull-up control
6 Ports PB4, PB5
pull-up control
7 Ports PB6
pull-up control
Functions
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.10 Structure of pull-up control register 3
38B7 Group User’s Manual
2-7
APPLICATION
2.1 I/O port
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Pins
Termination
P0, P2
Open at “H” output state.
P1, P3–P5, P60– • Set to the input mode and connect each to V CC or V SS through a resistor of 1 kΩ to
P63
10 kΩ.
• Set to the output mode and open at “H” output state.
P64–P67, P7, P80– • Set to the input mode and connect each to V CC or V SS through a resistor of 1 kΩ to
P83, P9, PA, PB0– 10 kΩ.
PB6
• Set to the output mode and open at “L” or “H” output state.
V REF
Open.
X OUT
Open (only when using external clock).
AV SS
Connect to V SS (GND).
V EE
Connect to V SS (GND).
CNV SS
Connect to V SS through a resistor of 1 kΩ to 10 kΩ.
2-8
38B7 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.4 Notes on I/O port
(1) Notes in standby state
In standby state ✽1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”.
Pull-up (connect the port to V CC) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using an optional built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying port latch of I/O port with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ✽2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
(3) Pull-up/Pull-down control
When each port which has built-in pull-up/pull-down resistor is set to output port, pull-up/pull-down
control of corresponding port becomes invalid. (Pull-up/pull-down cannot be set.)
● Reason
Pull-up/pull-down control is valid only when each direction register is set to the input mode.
38B7 Group User’s Manual
2-9
APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or VSS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pin INT or others, select the VCC
pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or VSS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
2-10
38B7 Group User’s Manual
APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
002016
Timer 1 (T1)
002116
Timer 2 (T2)
002216
Timer 3 (T3)
002316
Timer 4 (T4)
002416
Timer 5 (T5)
002516
Timer 6 (T6)
002616 (PWM control register (PWMCON))
002716 Timer 6 PWM register (T6PWM)
002816
Timer 12 mode register (T12M)
002916
Timer 34 mode register (T34M)
002A16
Timer 56 mode register (T56M)
002B16 (D-A conversion register (DA))
002C16 Timer X (low-order) (TXL)
002D16
Timer X (high-order) (TXH)
002E16
Timer X mode register 1 (TXM1)
002F16
Timer X mode register 2 (TXM2)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
38B7 Group User’s Manual
2-11
APPLICATION
2.2 Timer
2.2.2 Relevant registers
(1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3 to 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
0 • Set timer i count value.
1 • The value set in this register is written to both
2 the timer i and the timer i latch at one time.
3 • When the timer i is read out, the count value
4 of the timer i is read out.
5
6
7
At reset R W
1
1
1
1
1
1
1
1
Fig. 2.2.2 Structure of Timer i (i=1, 3 to 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 the timer 2 and the timer 2 latch at one time.
3 • When the timer 2 is read out, the count value
4 of the timer 2 is read out.
5
6
7
At reset R W
1
0
0
0
0
0
0
0
Fig. 2.2.3 Structure of Timer 2
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
0
1
2
3
4
5
6
Functions
• In timer 6 PWM1 mode
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
Fig. 2.2.4 Structure of Timer 6 PWM register
2-12
At reset R W
Undefined
38B7 Group User’s Manual
APPLICATION
2.2 Timer
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
Name
0 Timer 1 count stop
bit
1 Timer 2 count stop
bit
2 Timer 1 count
source selection
3 bits
4 Timer 2 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: Timer 1 underflow
0 1: f(XCIN)
1 0: External count input
CNTR0
1 1: Not available
0: I/O port
6 Timer 1 output
selection bit (P75) 1: Timer 1 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 2.2.5 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
Name
0 Timer 3 count stop
bit
1 Timer 4 count stop
bit
2 Timer 3 count
source selection
3 bits
4 Timer 4 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1
1 1: Not available
0: I/O port
6 Timer 3 output
selection bit (P76) 1: Timer 3 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 2.2.6 Structure of Timer 34 mode register
38B7 Group User’s Manual
2-13
APPLICATION
2.2 Timer
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
Name
0 Timer 5 count stop
bit
1 Timer 6 count stop
bit
Timer
5 count
2
source selection bit
3 Timer 6 operation
mode selection bit
4 Timer 6 count
source selection
5 bits
6 Timer 6 (PWM)
output selection bit
(P74)
Functions
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 2.2.7 Structure of Timer 56 mode register
2-14
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0: f(XIN)/8 or f(XCIN)/16
1: Timer 4 underflow
0: Timer mode
1: PWM mode
38B7 Group User’s Manual
0
0
0
0
0
0
APPLICATION
2.2 Timer
(2) 16-bit timer
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-order, high-order)
(TXL, TXH: addresses 2C16, 2D16)
b
Functions
0 • Set timer X count value.
1 • When the timer X write control bit of the timer
X mode register 1 is “0”, the value is written to
2
timer X and the latch at one time.
3
When the timer X write control bit of the timer
X mode register 1 is “1”, the value is written
4
only to the latch.
5
• The timer X count value is read out by reading
6
this register.
7
At reset R W
1
1
1
1
1
1
1
1
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes.
2: Read both registers in order of TXH and TXL following.
3: Write both registers in order of TXL and TXH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 2.2.8 Structure of Timer X (low-order, high-order)
38B7 Group User’s Manual
2-15
APPLICATION
2.2 Timer
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1: address 2E16)
b
Name
0 Timer X write
control bit
Functions
0 : Write value in latch and
counter
1 : Write value in latch only
0
b2 b1
1 Timer X count
0 0: f(XIN)/2 or f(XCIN)/4
source selection bits 0 1: f(XIN)/8 or f(XCIN)/16
1 0: f(XIN)/64 or f(XCIN)/128
2
1 1: Not available
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
4 Timer X operating
mode bits
5
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width
measurement mode
6 CNTR2 active edge 0 : •Start from “H” output in
pulse output mode
switch bit
•Count at rising edge in
event counter mode
•Measure “H” pulse
width in pulse width
measurement mode
1 : •Start from “L” output in
pulse output mode
•Count at falling edge in
event counter mode
•Measure “L” pulse
width in pulse width
measurement mode
7 Timer X stop
control bit
0 : Count operating
1 : Count stop
Fig. 2.2.9 Structure of Timer X mode register 1
2-16
At reset R W
38B7 Group User’s Manual
0
0
0
0
0
0
APPLICATION
2.2 Timer
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 2
(TXM2: address 2F16)
b
Name
0 Real time port control
bit (P94)
1 Real time port control
bit (P95)
2 P94 data for real time
port
3 P95 data for real time
port
Functions
At reset R W
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: “L” output
1: “H” output
0
0: “L” output
1: “H” output
0
4 Nothing is arranged for these bits. These are
5 write disabled bits. When these bits are read
6 out, the contents are “0”.
7
0
0
0
0
0
Fig. 2.2.10 Structure of Timer X mode register 2
38B7 Group User’s Manual
2-17
APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
0 INT0 interrupt
request bit
Functions
0
✽
1 INT1/serial I/O3
0 : No interrupt request
interrupt request bit
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.11 Structure of Interrupt request register 1
2-18
At reset R W
0 : No interrupt request
issued
1 : Interrupt request issued
38B7 Group User’s Manual
APPLICATION
2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
Timer
6
interrupt
0 : No interrupt request issued
2
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.12 Structure of Interrupt request register 2
38B7 Group User’s Manual
2-19
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
At reset R W
0 INT0 interrupt
enable bit
1 INT1/serial I/O3
interrupt enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
Timer
X interrupt
4
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
Fig. 2.2.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit
1 Timer 5 interrupt
enable bit
Timer
6 interrupt
2
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/Serial I/O2
transmit interrupt
enable bit
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
Fig. 2.2.14 Structure of Interrupt control register 2
2-20
At reset R W
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
38B7 Group User’s Manual
0
0
0
0
0
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs.
<Use>
•Generating of an output signal timing
•Generating of a wait time
[Function 2] Control of cyclic operation (Timer 1 to Timer 6, Timer X: timer mode)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generating of cyclic interrupts
•Clock function (measurement of 1 s); see “(2) Timer application example 1”
•Control of a main routine cycle
[Function 3] Output of rectangular waveform
(Timer 1, Timer 3, Timer 6, Timer X: pulse output mode)
The output level of the T1OUT pin, T 3OUT pin, PWM1 pin or CNTR2 pin is inverted each time the timer
underflows.
<Use>
•Piezoelectric buzzer output; see “(3) Timer application example 2”
•Generating of the remote control carrier waveforms
[Function 4] Count of external pulses (Timer 2, Timer 4, Timer X: event counter mode)
External pulses input to the CNTR0 pin, CNTR 1 pin, CNTR 2 pin are counted as the timer count
source (in the event counter mode).
<Use>
•Frequency measurement; see “(4) Timer application example 3”
•Division of external pulses
•Generating of interrupts due to a cycle using external pulses as the count source; count of a reel pulse
[Function 5] Output of PWM signal (Timer 6)
“H” interval and “L” interval are specified, respectively, and the output of pulses from P7 4/PWM 1
pin is repeated.
<Use>
•Control of electric volume
[Function 6] Measurement of external pulse width (Timer X: pulse width measurement mode)
The “H” or “L” level width of external pulses input to CNTR 2 pin is measured.
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse✽ for a motor);
see “(5) Timer application example 4”
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed.
[Function 7] Control of real time port (Timer X: real time port function)
The data for real time is output from the P94 pin or P9 5 pin each time the timer underflows.
<Use>
•Stepping motor control; see “(6) Timer application example 5”
38B7 Group User’s Manual
2-21
APPLICATION
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 1 s)
Outline: The input clock is divided by the timer so that the clock can count up at 1 s intervals.
Specifications: •The clock f(X IN) = 4.19 MHz (2 22 Hz) is divided by the timer.
•The timer 3 interrupt request bit is checked in main routine, and if the interrupt
request is issued, the clock is counted up.
• The timer 1 interrupt occurs every 244 µs to execute processing of other interrupts.
Figure 2.2.15 shows the timers connection and setting of division ratios; Figure 2.2.16 shows the
relevant registers setting; Figure 2.2.17 shows the control procedure.
f(XIN)
4.19 MHz
1/16
Timer 1
Timer 2
Timer 3
1/64
1/256
1/16
Timer 3 interrupt request bit
0/1
1s
0/1
244 µs
Timer 1 interrupt
request bit
Fig. 2.2.15 Timers connection and setting of division ratios
2-22
38B7 Group User’s Manual
0 : No interrupt request issued
1 : Interrupt request issued
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
T12M
b0
0 0 0 0 1 0 0 1
Timer 1 count: Stop; Clear to “0” when starting count.
Timer 2 count: In progress
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1’s underflow
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
T34M
0 0
b0
0 1
0
Timer 3 count: In progress
Timer 3 count source: Timer 2’s underflow
Timer 3 output selection: I/O port
Timer 1 (address 2016)
b7
T1
b0
3F16
Timer 2 (address 2116)
b7
T2
b0
Set “division ratio – 1”.
[ T1 = 63 (3F16), T2 = 255 (FF16), T3 = 15 (0F16) ]
FF16
Timer 3 (address 2216)
b7
T3
b0
0F16
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0 0 1
Timer 1 interrupt: Enabled
Timer 2 interrupt: Disabled
Timer 3 interrupt: Disabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
Timer 1 interrupt request (becomes “1” at 244 µs intervals)
Timer 2 interrupt request
Timer 3 interrupt request (becomes “1” at 1 s intervals)
Fig. 2.2.16 Relevant registers setting
38B7 Group User’s Manual
2-23
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
.....
•All interrupts disabled
T12M
T34M
IREQ1
ICON1
(address 2816)
(address 2916)
(address 3C16)
(address 3E16)
000010012
00XX01X02
000XXXXX2
001XXXXX2
•Connection of Timers 1 to 3
(address 2016)
(address 2116)
(address 2216)
3F16
FF16
0F16
•Setting “Division ratio – 1” to Timers 1 to 3
•Setting of Interrupt request bits of Timers 1 to 3 to “0”
•Timer 1 interrupt enabled, Timers 2 and 3 interrupts disabled
.....
T1
T2
T3
.....
T12M
(address 2816), bit0
0
•Timer count start
.....
CLI
•Interrupts enabled
Y
Clock is stopped ?
•Judgment whether time is not set or time is being set
N
0
IREQ1 (address 3C16), bit7 ?
•Confirmation that 1 s has passed
(Check of Timer 3 interrupt request bit)
1
IREQ1 (address 3C16), bit7
•Interrupt request bit cleared
(Clear it by software when not using the interrupt.)
0
✽
Clock count up
Second to Year
•Clock count up
Main processing
.....
•Adjust the main processing so that all processing in the loop ✽ will
be processed within 1 s interval.
<Procedure for end of clock setting> (Note)
T2
T3
IREQ1
(address 2116)
(address 2216)
(address 3C16), bit7
FF16
0 F1 6
0
•Set Timers again when starting clock from 0 s after end of
clcok setting.
The procedure is Timer 2 setting followed by Timer 3 setting.
•Do not set Timer 1 again because Timer 1 is used to
generate the interrupt at 244 µs intervals.
Note : Perform proc edure f or end o f clock sett ing o nly when end of
clock sett ing.
Fig. 2.2.17 Control procedure
2-24
38B7 Group User’s Manual
APPLICATION
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (2 22 Hz) into about
2 kHz (2048 Hz), is output from the P7 6/T3OUT pin.
•The level of the P76/T 3OUT pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.2.18 shows a peripheral circuit example, and Figure 2.2.19 shows the timers connection and
setting of division ratios. Figure 2.2.20 shows the relevant registers setting, and Figure 2.2.21 shows
the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
T3OUT output
T3OUT
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the underflow
38B7 Group
output period of the timer 3 can be 244 µs.
Fig. 2.2.18 Peripheral circuit example
f(XIN)
4.19 MHz
1/16
Timer 3
Fixed
1/64
1/2
T3OUT
Fig. 2.2.19 Timers connection and setting of division ratios
38B7 Group User’s Manual
2-25
APPLICATION
2.2 Timer
Timer 34 mode register (address 2916)
b7
T34M
b0
0 1
1 0
0
Timer 3 count: In progress
Timer 3 count source: f(XIN)/16
Timer 3 output selection: Buzzer output in progress = “1”
Buzzer output stopped = “0”
Timer 3 (address 2216)
b7
b0
Set “division ratio – 1”; 63 (3F16).
3F16
T3
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0
Timer 3 interrupt: Disabled
Fig. 2.2.20 Relevant registers setting
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
•All interrupts disabled
.....
P7D
P7
(address 0F16), bit6
(address 0E16), bit6
•Port state setting at buzzer output stopped; “H” level output
1
1
.....
ICON1 (address 3E16), bit7
T34M (address 2916)
T3
(address 2216)
0
00XX10X02
3F16
•Timer 3 interrupt disabled
•T3OUT output stopped; Buzzer output stopped
.....
•Interrupts enabled
CLI
Main processing
.....
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Piezoelectric buzzer request ?
Yes
No
T34M
T3
(address 2916), bit6
(address 2216)
0
3F16
T34M
(address 2916), bit6
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.2.21 Control procedure
2-26
1
38B7 Group User’s Manual
APPLICATION
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P8 2/CNTR 1 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P8 2/CNTR1 pin and counted by the timer 4. (Note 1)
•A count value of timer 4 is read out at about 2 ms intervals, the timer 1 interrupt
interval. When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note 2).
Notes 1: In the mask option type P, use the CNTR 0 pin and timer 2.
2: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.2.22 shows the judgment method of valid/invalid of input pulses; Figure 2.2.23 shows the
relevant registers setting; Figure 2.2.24 shows the control procedure.
Input pulse
@
@
@
@
71.4 µs or more
(14 kHz or less)
@
@
@
@
71.4 µs
(14 kHz)
@
50 µs
(20 kHz)
Valid
Invalid
2 ms = 28 counts
71.4 µs
@
@
@
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
Fig. 2.2.22 Judgment method of valid/invalid of input pulses
38B7 Group User’s Manual
2-27
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
T12M
b0
0 0
1 0
1
Timer 1 count: Stop; Clear to “0” when starting count.
Timer 1 count source: f(XIN)/16
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
T34M
0
b0
1 0
0
Timer 4 count: In progress
Timer 4 count source: External count input CNTR1
Timer 1 (address 2016)
b7
b0
T1
Set “division ratio – 1”; 63 (3F16).
3F16
Timer 4 (address 2316)
b7
b0
T4
Set 255 (FF16) just before counting pulses.
(After a certain time has passed, the number of
input pulses is decreased from this value.)
FF16
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer 1 interrupt: Enabled
Interrupt control register 2 (address 3F16)
b7
b0
0
ICON2
Timer 4 interrupt: Disabled
Interrupt request register 2 (address 3D16)
b7
IREQ2
b0
0
Timer 4 interrupt request
( “1” of this bit when reading the count value
indicates the 256 or more pulses input in the
condition of Timer 4 = 255)
Fig. 2.2.23 Relevant registers setting
2-28
38B7 Group User’s Manual
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
•All interrupts disabled
SEI
.....
T12M (address 2816)
(address 2016)
T1
T34M (address 2916)
(address 2316)
T4
ICON1 (address 3E16),bit5
ICON2 (address 3F16),bit0
00XX10X12
3F16
0X10XX0X2
FF16
1
0
•Set div ision rat io s o that Timer 1 inte rrupt will oc cur at 244 µs interv als .
0
•Timer 1 count start
•External pulses input from CNTR1 pin selected as Timer 4’s count source
•Setting Timer 4 count value
•Timer 1 interrupt enabled
•Timer 4 interrupt disabled
.....
T12M (address 2816), bit0
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
1/8
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Pushing registers used in interrupt process routine
1
•Processing as out of range when the count value is 256 or more
IREQ2 (address 3D16), bit0 ?
(A)
•Set so that pulse judgment process will be performed once each time
Timer 1 interrupt occurs 8 times, at 2 ms intervals.
T4 (address 2316)
•Count value read
•Storing count value into Accumulator (A)
In range
214 < (A) < 228
•Compare the read value with
reference value.
•Store the comparison result to flag Fpulse.
Out of range
Fpulse
Fpulse
0
T4
(address 2316)
IREQ2 (address 3D16), bit0
FF16
0
1
•Initialization of counter value
•Timer 4 interrupt request bit cleared
Process judgment result
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.24 Control procedure
38B7 Group User’s Manual
2-29
APPLICATION
2.2 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P8 3/CNTR 0/CNTR 2 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the timer 2 interrupt of which count source is the input to P83/CNTR0/CNTR2
pin.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P8 3/CNTR 0/
CNTR2 pin.
<Example>
When f(X IN) = 4.19 MHz, the count source is 15.2 µs, which is obtained by dividing the clock
frequency by 64. Measurement can be made up to 1 s in the range of FFFF16 to 0000 16 .
Figure 2.2.25 shows the timers connection and setting of division ratio; Figure 2.2.26 shows the
relevant registers setting; Figure 2.2.27 shows the control procedure.
Timer X count source
selection bit
f(XIN) = 4.19 MHz
1/64
Timer X
1/65536
Timer X interrupt
request bit
0/1
1s
Fig. 2.2.25 Timers connection and setting of division ratios
2-30
38B7 Group User’s Manual
APPLICATION
2.2 Timer
Port P8 direction register (address 1116)
b7
b0
0
P8D
P83/CNTR0/CNTR2: Input mode
Timer X mode register 1 (address 2E16)
b7
TXM1
b0
1 0 1 1
1 0 0
Write value in latch and counter
Timer X count source: f(XIN)/64
Timer X operating mode: Pulse width measurement mode
CNTR2 active edge: Measuring “H” pulse width in pulse width measurement mode
Timer X count: Stop; Clear to “0” when starting count.
Timer X mode register 2 (address 2F16)
b7
b0
0 0
TXM2
Real time port function (P94): Invalid
Real time port function (P95): Invalid
Timer X (low-order) (address 2C16)
b7
b0
FF16
TXL
Timer X (high-order) (address 2D16)
b7
b0
TXH
Set “65535 (FFFF16)” before stat of pulse width
measurement.
FF16
Interrupt edge selection register (address 3A16)
b7
INTEDGE
b0
1
CNTR0 pin edge: Falling edge count
Timer 12 mode register (address 2816)
b7
T12M
b0
0
1 0
0
Timer 2 count: Stop
Timer 2 count source: External count input CNTR0
Timer 2 (address 2116)
b7
T2
b0
Set “0”.
Timer 2 interrupt request occurs due to falling edge input to CNTR0 pin.
Interrupt control register 1 (address 3E16)
0
b7
ICON1
b0
1
1
Timer X interrupt: Enabled
Timer 2 interrupt: Enabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
Timer X interrupt request (becomes “1” when Timer X underflows)
Timer 2 interrupt request (becomes “1” when “H” level input ends)
Fig. 2.2.26 Relevant registers setting
38B7 Group User’s Manual
2-31
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
P8D
(address 1116),bit3
TXM1
(address 2E16)
TXM2
(address 2F16)
TXL
(address 2C16)
TXH
(address 2D16)
INTEDGE (address 3A16),bit6
T12M
(address 2816)
T2
(address 2116)
ICON1 (address 3E16)
0
1011X1002
XXXXXX002
FF16
FF16
1
0X10XX1X2
0
XXXX1X1X2
•Sett ing P83/CNTR0/CNTR2 pin to input mode
•Timer X: Pulse width measurement mode
(Measuring “H” pulse width of input pulses from CNTR2 pin)
•Setting Timer X count value
•CNTR0 pin edge: Falling edge count
•External pulses input from CNTR0 pin selected as Timer 2’s count source
•Setting “0” to Timer 2
•Timers X and 2 interrupts: Enabled
.....
TXM1
T12M
(address 2E16),bit7
(address 2816),bit1
0
0
•Timers X and 2 count start
.....
CLI
•Interrupts enabled
Timer X interrupt process routine (Note 1)
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Notes 1: Timer X interrupt also occurs owing to factors other than
measurement level.(CNTR2 input = “L” in this application)
Process it by software as error proccesing is performed for
measurement level as necessary . CNTR2 input level can be
checked by reading the contents of sharing port P83 register.
2: When using Index X mode flag (T)
3: When using Decimal mode flag (D)
•Pus hing regist ers us ed in int errupt pro cess routine
Error processing
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.27 Control procedure
2-32
38B7 Group User’s Manual
APPLICATION
2.2 Timer
Timer 2 interrupt process routine (Note 1)
CLT (Note 2)
CLD (Note 3)
Push registers to stack
(A)
Measurement result (high-order 8 bits)
(A)
Measurement result (low-order 8 bits)
TXL
(address 2C16)
TXH
(address 2D16)
Notes 2: When using Index X mode flag (T)
3: When using Decimal mode flag (D)
•Pushing registers used in interrupt process routine
TXH
(A)
TXL
(A)
FF16
FF16
Pop registers
•Count value read and storing it to RAM
•Popping registers pushed to stack
RTI
Note 1: The first value becomes invalid depending on start timing of Time X count
shown by the following figure.
Process it by software as necessary.
[ Example 1] • Start Timer X count when CNTR2 input level is “L”.
(CNTR2 input level can be checked by reading the contents of sharing port P83 register.
FFFF16
T1
T2
000016
T2 value: Valid
T1 value: Valid
CNTR2
Count start of
Timer X
Timer 2 interrupt
Timer 2 interrupt
[ Example 2] • Start Timer X count when CNTR2 input level is “H”.
Invalidate the first Timer 2 interrupt after start of Timer X count.
FFFF16
T1
T2
000016
T1 value: Invalid
T2 value: Valid
CNTR2
Count start of
Timer 2 interrupt
Timer X
Timer 2 interrupt
38B7 Group User’s Manual
2-33
APPLICATION
2.2 Timer
(6) Timer application example 5: Control of stepping motor
Outline: The rotating of stepping motor is controlled by using real time output ports.
Specifications: •The motor is controlled by using 2 real time output ports.
•The count source is f(X IN) = 4.19 MHz divided by 8.
•Values of Timer X and real time output are updated in the timer X interrupt routine
Figure 2.2.28 shows the timers connection and the table example of timer X/RTP setting values;
Figure 2.2.29 shows the RTP output example; Figure 2.2.30 shows the relevant registers setting;
Figure 2.2.31 shows the control procedure.
RTP P94
TXL
TXH
TXM2
Timer X
table
RTP
table
Motor
RTP P95
38B7 group
Timer X setting table example
RTP
Timer X value
output time
2FD016
T1
2B7116
T2
208116
T3
186916
T4
13C916
T5
13A916
T6
122116
T7
11C116
T8
RTP setting table example
RTP value
RTP output
pattern
TXM2,b2 TXM2,b3
(1)
0
0
(2)
0
1
(3)
1
0
(4)
1
1
RTP: Real Time Port
Fig. 2.2.28 Timers connection and table example of timer X/RTP setting values
T1
T2
T3
T4
T5
T6
T7
T8
RTP
output
pattern
( 1)
RTP
output
pattern
( 2)
RTP
output
pattern
(3)
RTP
output
pattern
(4)
(1)
(2)
(3)
(4)
RTP output time
RTP P94
RTP P95
RTP: Real Time Port
Fig. 2.2.29 RTP output example
2-34
38B7 Group User’s Manual
APPLICATION
2.2 Timer
Timer X mode register 1 (address 2E16)
b7
TXM1
1
b0
0 0
0 1 0
Write value in latch and counter
Timer X count source: f(XIN)/8
Timer X operating mode: Timer mode
Timer X count: Stop; Clear to “0” when starting count.
Timer X mode register 2 (address 2F16)
b7
b0
TXM2
1 1
Real time port function (P94): Valid
Real time port function (P95): Valid
P94 data for real time port
P94 data for real time port
Timer X (low-order) (address 2C16)
b7
b0
TXL
Timer X (high-order) (address 2D16)
b7
b0
Update the value from the table each time Timer X underflows.
(When accelerating or reducing speed.)
TXH
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Fig. 2.2.30 Relevant registers setting
38B7 Group User’s Manual
2-35
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
SEI
•All interrupts disabled
.....
TXM1
TXM2
TXL
TXH
IREQ1
ICON1
(address 2E16)
(address 2F16)
(address 2C16)
(address 2D16)
(address 3C16),bit4
(address 3E16),bit4
1X00X0102
XXXX00112
D016
2F16
0
1
•Setting Timer X
•Setting RTP function, “002” data from table
•Setting Timer X initial value, “2FD016” data from table
0
•Timer X count start
•Timer X interrupt request cleared
•Timer X interrupt enabled
.....
TXM1 (address 2E16), bit7
.....
•Interrupts enabled
CLI
Main processing
.....
RTP: Real Time Port
Timer X interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Notes 1: When using Index X mode flag (T)
2: When using Decimal mode flag (D)
•Pushing registers used in interrupt process routine
Transfer the next underflow time of Timer X
from internal ROM table and store it to TXL
(address 2C16) and TXH (address 2D16)
Transfer RTP output data from internal
ROM table next underflow of Timer X and
store it to bits 2 and 3 of TXM2 (address
2 F1 6 )
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.31 Control procedure
2-36
38B7 Group User’s Manual
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
001816 Serial I/O1 automatic transfer data pointer (SIO1DP)
001916 Serial I/O1 control register 1 (SIO1CON1,SC11)
001A16 Serial I/O1 control register 2 (SIO1CON2,SC12)
001B16 Serial I/O1 register/Transfer counter (SIO1)
001C16 Serial I/O1 control register 3 (SIO1CON3,SC13)
001D16 Serial I/O2 control register (SIO2CON)
001E16 Serial I/O2 status register (SIO2STS)
001F16 Serial I/O2 transmit/receive buffer register (TB/RB)
003716 Baud rate generator (BRG)
003816 UART control register (UARTCON)
003916 Interrupt source switch register (IFR)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
0EEC16 Serial I/O3 control register (SIO3CON)
0EED16 Serial I/O3 register (SIO3)
Fig. 2.3.1 Memory map of registers relevant to Serial I/O
38B7 Group User’s Manual
2-37
APPLICATION
2.3 Serial I/O
2.3.2 Relevant registers
(1) Serial I/O1
Serial I/O1 automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 1816)
b
Functions
0 • Indicates the low-order 8 bits (0016 to FF16) of
1 the address storing the start data on the serial
2 I/O automatic transfer RAM.
3 • Data is written into the latch and read from the
4 decrement counter.
5
6
7
Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer
2-38
38B7 Group User’s Manual
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1•SC11: address 1916)
b
Name
0 Serial transfer
selection bits
1
2 Serial I/O1
synchronous clock
selection bits
(PB3/SSTB1 pin
control bits)
3
Functions
b1b0
0 0: Serial I/O disabled
(Pins PB0–PB6 pins
are I/O ports.)
0 1: 8-bit serial I/O
1 0: Not available
1 1: Automatic transfer
serial I/O (8 bits)
b3b2
0 0: Internal synchronous
clock (PB3 pin is I/O
port.)
0 1: External synchronous
clock (PB3 pin is I/O
port.)
1 0: Internal synchronous
clock (PB3 pin is
SSTB1 output.)
1 1: Internal synchronous
clock (PB3 pin is
SSTB1 output.)
At reset R W
0
0
0
0
4 Serial I/O
initialization bit
5 Transfer mode
selection bit
0: Serial I/O initialization
1: Serial I/O enabled
0: Full-duplex
(transmit/receive) mode
(PB6 pin is SIN1 input.)
1: Transmit-only mode
(PB6 pin is I/O port.)
0
6 Transfer direction
selection bit
0: LSB first
1: MSB first
0
7 Serial I/O1 clock pin 0: SCLK11 (PB0/SCLK12 pin
selection bit
is I/O port.)
1: SCLK12 (PB4/SCLK11 pin
is I/O port.)
0
0
Fig. 2.3.3 Structure of Serial I/O1 control register 1
38B7 Group User’s Manual
2-39
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 • SC12: address 1A16)
b
Name
Functions
0 PB1/SRDY1 •
PB2/SBUSY1 pin
control bits
At reset R W
0
b3b2b1b0
1
2
3
4
5
0 0 0 0: PB1, PB2 pins are I/O ports.
0 0 0 1: Not used
0 0 1 0: PB1 pin is SRDY1 output; PB2 pin is
I/O port.
0 0 1 1: PB1 pin is SRDY1 output; PB2 pin is
I/O port.
0 1 0 0: PB1 pin is I/O port; PB2 pin is
SBUSY1 input.
0 1 0 1: PB1 pin is I/O port; PB2 pin is
SBUSY1 input.
0 1 1 0: PB1 pin is I/O port; PB2 pin is
SBUSY1 output.
0 1 1 1: PB1 pin is I/O port; PB2 pin is
SBUSY1 output.
1 0 0 0: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 0 0 1: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 0 1 0: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 0 1 1: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 1 0 0: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
1 1 0 1: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
1 1 1 0: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
1 1 1 1: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
SBUSY1 output •
0: Functions as signal for
SSTB1 output
each 1-byte
function selection bit 1: Functions as signal for
(Valid in serial I/O1
each transfer data set
automatic transfer
mode)
Serial transfer
0: Serial transfer
status flag
completed
1: Serial transfer inprogress
0
0
0
0
6 SOUT1 pin control
0: Output active
bit (when serial data 1: Output high-impedance
is not transferred)
0
7 PB5/SOUT1 P-channel 0: CMOS 3 state (Poutput disable bit
channel output is valid.)
1: N-channel open-drain
output (P-channel output
is invalid.)
0
Fig. 2.3.4 Structure of Serial I/O1 control register 2
2-40
0
38B7 Group User’s Manual
APPLICATION
2.3 Serial I/O
Serial I/O1 register/Transfer counter
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 register/Transfer counter
(SIO1: address 1B16)
b
Name
Functions
At reset R W
•At function as serial I/O1
Undefined
register:
This register becomes the
shift register to perform
Undefined
serial transmit/reception.
•In automatic transfer
Set transmit data to this
serial I/O mode:
register.
Transfer counter
Undefined
The serial transfer is started
by writing the transmit data.
0 •In 8-bit serial I/O
mode:
Serial I/O1 register
1
2
3
4
5
6
7
•At function as transfer
counter:
Set (transfer byte number –
1) to this register.
When selecting an internal
clock, the automatic
transfer is started by writing
the transmit data.
(When selecting an external
clock, after writing a value
to this register, wait for 5 or
more cycles of the internal
system clock before
inputting the transfer clock
to the SCLK1 pin.)
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter
38B7 Group User’s Manual
2-41
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 • SC13: address 1C16)
b
Name
Functions
0 Automatic transfer b4b3b2b1b0
0 0 0 0 0: 2 cycles of
interval set bits
transfer clock
(valid only when
0 0 0 0 1: 3 cycles of
1 selecting internal
transfer clock
synchronous clock)
to
1
1
1
1
0:
32
cycles of
2
transfer clock
1 1 1 1 1: 33 cycles of
3
transfer clock
4
5 Internal
synchronous clock
selection bits
6
7
0
0
0
0
Data is written into the
latch and read from the
decrement counter.
0
b7b6b5
0
0 0 0 : f(XIN)/4 or f(XCIN)/8
0 0 1 : f(XIN)/8 or
f(XCIN)/16
0 1 0 : f(XIN)/16 or
f(XCIN)/32
0 1 1 : f(XIN)/32 or
f(XCIN)/64
1 0 0 : f(XIN)/64 or
f(XCIN)/128
1 0 1 : f(XIN)/128 or
f(XCIN)/256
1 1 0 : f(XIN)/256 or
f(XCIN)/512
1 1 1 : Not used
Fig. 2.3.6 Structure of Serial I/O1 control register 3
2-42
At reset R W
38B7 Group User’s Manual
0
0
APPLICATION
2.3 Serial I/O
(2) Serial I/O2
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator
(BRG: address 3716)
b
Functions
At reset R W
0 • Bit rate of the serial transfer is determined.
• This is the 8-bit counter and has the reload
1
register.
The count source is divided by n+1 owing to
2
specifying a value n.
3
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Fig. 2.3.7 Structure of Baud rate generator
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 3816)
b
Name
0 Character length
selection bit (CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length
selection bit (STPS)
4 P65/TxD P-channel
output disable bit
(POFF)
Functions
At reset R W
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0
0: CMOS output (in output
mode)
1: N-channel open-drain
output (in output mode)
0
0
0
0
5 BRG clock switch bit 0: XIN or XCIN/2 (depending
on internal system clock)
1: XCIN
6 Serial I/O2 clock
0: SCLK21 (P67/SCLK22 pin is
used as I/O port or SRDY2
I/O pin selection bit
output pin.)
1: SCLK22 (P66/SCLK21 pin is
used as I/O port.)
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
0
Fig. 2.3.8 Structure of UART control register
38B7 Group User’s Manual
2-43
APPLICATION
2.3 Serial I/O
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 1D16)
b
Name
Functions
0: f(XIN) or f(XCIN)/2 or
f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or
f(XCIN)/4
0
1 Serial I/O2
synchronous clock
selection bit
(SCS)
•In clock synchronous
mode
0: BRG output/4
1: External clock input
•In UART mode
0: BRG output/16
1: External clock input/16
0
2 SRDY2 output
enable bit (SRDY)
0: P67 pin operates as
normal I/O pin
1: P67 pin operates as
SRDY2 output pin
0
0: When transmit buffer
3 Transmit interrupt
source selection bit
has emptied
(TIC)
1: When transmit shift
operation is completed
0
4 Transmit enable bit
(TE)
5 Receive enable bit
(RE)
6 Serial I/O2 mode
selection bit (SIOM)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
0
7 Serial I/O2 enable
bit (SIOE)
0: Serial I/O2 disabled
(pins P64–P67 operate
as normal I/O pins)
1: Serial I/O2 enabled
(pins P64–P67 operate
as serial I/O pins)
0
Fig. 2.3.9 Structure of Serial I/O2 control register
2-44
At reset R W
0 BRG count source
selection bit (CSS)
38B7 Group User’s Manual
0
0
APPLICATION
2.3 Serial I/O
Serial I/O2 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 status register
(SIO2STS: address 1E16)
b
Name
0 Transmit buffer
empty flag (TBE)
1 Receive buffer full
flag (RBF)
2 Transmit shift
register shift
completion flag
(TSC)
Functions
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
3 Overrun error flag
(OE)
Parity
error flag
4
(PE)
0: No error
1: Overrun error
0: No error
1: Parity error
5 Framing error flag 0: No error
1: Framing error
(FE)
6 Summing error flag 0: (OE) U (PE) U (FE) = 0
(SE)
1: (OE) U (PE) U (FE) = 1
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
At reset R W
0
0
0
0
0
0
0
1
Fig. 2.3.10 Structure of Serial I/O2 status register
Serial I/O2 transmit/receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 transmit/receive buffer register
(TB/RB: address 1F16)
b
Functions
0 This is the buffer register which is used to write
transmit data or to read receive data.
1
• At write : The value is written to the transmit
buffer register. The value cannot be
2
written to the receive buffer register.
3 • At read : The contents of the receive buffer
register is read out. When a
4
character bit length is 7 bits, the
5
MSB of data stored in the receive
buffer is “0”. The contents of the
6
transmit buffer register cannot be
7
read out.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.3.11 Structure of Serial I/O2 transmit/receive buffer register
38B7 Group User’s Manual
2-45
APPLICATION
2.3 Serial I/O
(3) Serial I/O3
Serial I/O3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O3 control register
(SIO3CON: address 0EEC16)
b
Name
Functions
At reset R W
0 Internal synchronous b2b1b0
clock selection bits 000: f(XIN)/4 or f(XCIN)/8
001: f(XIN)/8 or f(XCIN)/16
010: f(XIN)/16 or f(XCIN)/32
1
011: f(XIN)/32 or f(XCIN)/64
110: f(XIN)/64 or
f(XCIN)/128
2
111: f(XIN)/128 or
f(XCIN)/256
0
3 Serial I/O3 port
selection bit
(P91, P92)
0
4
0
5
6
7
0: I/O port
1: SOUT3, SCLK3 signal
output
0: I/O port
SRDY3 output
1: SRDY3 signal output
selection bit (P93)
0:
LSB first
Transfer direction
1: MSB first
selection bit
Synchronous clock 0: External clock
selection bit
1: Internal clock
P91/SOUT3
0: CMOS output (in output
P-channel output
mode)
disable bit (P91)
1: N-channel open drain
output (in output mode)
0
0
0
0
0
Fig. 2.3.12 Structure of Serial I/O3 control register
Serial I/O3 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O3 register
(SIO3: address 0EED16)
b
Functions
This
isserial
the buffer
0 •In
8-bit
I/O register which is used to write
transmit data or to read receive data.
1 mode:
an internal clock, the serial
Serial selecting
I/O1 register
2 When
3 transfer is started by writing this register.
4 •In automatic transfer
serial I/O mode:
5 Transfer counter
6
7
Fig. 2.3.13 Structure of Serial I/O3 register
2-46
38B7 Group User’s Manual
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
APPLICATION
2.3 Serial I/O
(4) Serial I/O1 and Serial I/O2
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916)
b
Name
Functions
0 INT3/serial I/O2
transmit interrupt
switch bit
0: INT3 intrrupt
1: Serial I/O2 transmit
interrupt
0: INT4 interrupt
1 INT4/A-D
conversion interrupt 1: A-D conversion intrerrupt
switch bit
0: INT1 intrrupt
2 INT1/serial I/O3
interrupt switch bit 1: Serial I/O3 interrupt
3 Nothing is arranged for these bits. These are write
4 disabled bits. When these bits are read out, the
contents are “0”.
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.3.14 Structure of Interrupt source switch register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
0 INT0 interrupt
request bit
Functions
At reset R W
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1/serial I/O3
0 : No interrupt request
interrupt request bit
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.15 Structure of Interrupt request register 1
38B7 Group User’s Manual
2-47
APPLICATION
2.3 Serial I/O
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
Timer
6
interrupt
0 : No interrupt request issued
2
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.16 Structure of Interrupt request register 2
2-48
38B7 Group User’s Manual
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
At reset R W
0 INT0 interrupt
enable bit
1 INT1/serial I/O3
interrupt enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
4 Timer X interrupt
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
Fig. 2.3.17 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit
1 Timer 5 interrupt
enable bit
2 Timer 6 interrupt
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/Serial I/O2
transmit interrupt
enable bit
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
At reset R W
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Fig. 2.3.18 Structure of Interrupt control register 2
38B7 Group User’s Manual
2-49
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O1 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.19 shows connection examples with peripheral ICs equipped with the CS pin.
All examples can use the automatic transfer function.
(1) Only transmission
(Using SIN1 pin as I/O port)
(2) Transmission and reception
SBUSY1
CS
SBUSY1
CS
SCLK11
CLK
SCLK11
SOUT1
DATA
SOUT1
SIN1
CLK
IN
38B7 group
Peripheral IC
(OSD controller etc.)
38B7 group
(3) Transmission and reception
(When connecting SIN1 with SOUT1)
(When connecting IN with OUT in
peripheral IC)
SBUSY1
CS
SCLK11
SOUT1
CLK
SIN1
OUT
38B7 group✽1
OUT
Peripheral IC
(EEPROM etc.)
(4) Connection of plural IC
Port
SCLK11
IN
SOUT1
CLK
IN
SIN1
OUT
Port
Peripheral IC ✽2
(EEPROM etc.)
CS
Peripheral IC 1
38B7 group
✽1: Select an N-channel open-drain output for SOUT1 pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.19 Serial I/O1 connection examples (1)
2-50
38B7 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.20 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK11
CLK
SCLK11
CLK
SOUT1
IN
SOUT1
IN
SIN1
38B7 group
OUT
SIN1
Microcomputer
38B7 group
(3) Using SRDY1 signal output function
(Selecting external clock)
OUT
Microcomputer
(4) Using switch function of CLK signal output
pins, SCLK12 (Selecting internal clock)
SRDY1
RDY
SCLK11
CLK
SCLK11
CLK
SOUT1
IN
SOUT1
IN
SIN1
38B7 group
SIN1
OUT
SCLK12
OUT
Port
Microcomputer
Microcomputer
38B7 group
CLK
IN
OUT
CS
Peripheral IC
Fig. 2.3.20 Serial I/O1 connection examples (2)
38B7 Group User’s Manual
2-51
APPLICATION
2.3 Serial I/O
2.3.4 Serial I/O1’s modes
Figure 2.3.21 shows the serial I/O1’s modes.
Output SRDY1 ✽ signal
Input SRDY1 ✽ signal (Note)
Used
handshake
signal
Output SBUSY1 ✽ signal
Input SBUSY1 ✽ signal
Internal
clock
Full duplex
mode
8-bit serial
I/O
Transmit
only mode
Automatic
transfer
serial I/O
Output SSTB1 ✽ signal
Not used
handshake
signal
Serial I/O1
Output SRDY1 ✽ signal
Used
handshake
signal
External
clock
Input SRDY1 ✽ signal (Note)
Output SBUSY1 ✽ signal
Input SBUSY1 ✽ signal
Not used
handshake
signal
Note: This is only valid when outputting the SBUSY1 signal.
✽ Active logic can apply to each signal of SRDY1, SBUSY1, SSTB1.
Fig. 2.3.21 Serial I/O1’s modes
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38B7 Group User’s Manual
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O1 application examples
(1) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting ports with the CS pin of a peripheral IC.
Figure 2.3.22 shows a connection diagram, and Figure 2.3.23 shows a timing chart.
CS
PB1
CS
CLK
PB4/SCLK11
CLK
DATA
PB5/SOUT1
DATA
38B7 group
Peripheral IC
Fig. 2.3.22 Connection diagram
Specifications : • Use of serial I/O1 (Not using automatic transfer function)
• Synchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of serial I/O1 interrupt
• Port PB 1 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port PB 1 is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Fig. 2.3.23 Timing chart
38B7 Group User’s Manual
2-53
APPLICATION
2.3 Serial I/O
Figure 2.3.24 shows the registers setting relevant to the transmission side, and Figure 2.3.25 shows
the setting of transmission data.
Serial I/O1 control register 1 (address 001916)
SIO1CON1 0 0 1 0 0 0 0 1
(SC11)
8-bit serial I/O
Internal synchronous clock (PB3 pin is an I/O port.)
Serial I/O initialization
Transmit-only mode
LSB first
Serial I/O1 clock pin: SCLK11
Serial I/O1 control register 2 (address 001A16)
SIO1CON2
(SC12)
0 0
0 0 0 0
Pins PB1 and PB2 of I/O ports
SOUT1 pin: Output active
PB5/SOUT1: CMOS 3-state (P-channel output is valid.)
Serial I/O1 control register 3 (address 001C16)
SIO1CON3 0 1 1
(SC13)
Internal synchronous clock: f(XIN)/32
Port PB (address 001616)
PB
1
Set PB1 output level to “H”
Port PB direction register (address 001716)
1
PBD
Set PB1 to output mode
Fig. 2.3.24 Registers setting relevant to transmission side
Serial I/O1 register (001B16)
Set a transmission data.
Confirm that transmission of the previous
data is completed, where bit 5, the serial
transfer status flag of the serial I/O1 control
register 2, is “0”; before writing data.
SIO1
Fig. 2.3.25 Setting of transmission data
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APPLICATION
2.3 Serial I/O
Control procedure: When the registers are set as shown in Figure 2.3.24, the serial I/O1 can transmit
1-byte data by writing data to the serial I/O1 register.
Thus, after setting the CS signal to “L”, write the transmission data to the serial
I/O1 register by each 1 byte; and return the CS signal to “H” when the target
number of bytes has been transmitted.
Figure 2.3.26 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SC11 (address 001916)
SC12 (address 001A16)
SC13 (address 001C16)
PB (address 001616), bit1
PBD (address 001716), bit1
SC11 (address 001916), bit4
Serial I/O1 setting
001000012
00XX00002
011XXXXX2
1
1
1
CS signal output level to “H” setting
CS signal output port setting
Enabled serial I/O1
.....
0
CS signal output level to “L” setting
Transmission data
Transmission data write
(Start of 1-byte data transmission)
PB (address 001616), bit1
SIO1 (address 001B16)
SIO1CON2 (address 001A16), bit5 ?
1
Judgment of completion of transmitting 1-byte data
0
N
All data have been transmitted ?
Use any of RAM area as a counter for counting the
number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
Y
PB (address 001616), bit1
1
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
Fig. 2.3.26 Control procedure
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APPLICATION
2.3 Serial I/O
(2) Transmission/Reception using automatic transfer
Outline: Serial transmission/reception control is performed, using the serial automatic transfer function.
Figure 2.3.27 shows a connection diagram, and Figure 2.3.28 shows a timing chart of serial data
transmission/reception.
PB4/SCLK11
CLK
PB5/SOUT1
IN
PB6/SIN1
OUT
Sub microcomputer
38B7 group
Fig. 2.3.27 Connection diagram
Specifications: •
•
•
•
•
•
Use of serial I/O1 using automatic transfer function
Synchronous clock frequency: 131 kHz (f(X IN) = 4.19 MHz is divided by 32.)
Transfer direction: LSB first
Transmission/reception byte number: 8 bytes/block each
Transfer interval for 1-byte: 244 µs (32 cycles of transfer clock)
Not use of serial I/O1 automatic transfer interrupt
Figure 2.3.29 shows the relevant registers setting, and Figure 2.3.30 shows the control procedure.
.
1 block
CLK
OUT
IN
DO0
DO1
DO2
DO7
DO0
DO1
DI0
DI1
DI2
DI7
DI0
DI1
Block period is controlled by software.
(Synchronize it with the main routine.)
Fig. 2.3.28 Timing chart of serial data transmission/reception
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APPLICATION
2.3 Serial I/O
Serial I/O1 control register 1 (address 001916)
SIO1CON1
(SC11)
0 0 0 0 0 0 1 1
Automatic transfer serial I/O (8 bits)
Internal synchronous clock (PB3 pin is an I/O port.)
Serial I/O initialization
Full duplex mode
LSB first
Serial I/O1 clock pin: SCLK11
Serial I/O1 control register 2 (address 001A16)
SIO1CON2 0 0
(SC12)
0 0 0 0
Pins PB1 and PB2 of I/O ports
SOUT1 pin: Output active
PB5/SOUT1: CMOS 3-state
Serial I/O1 control register 3 (address 001C16)
SIO1CON3 0 1 1 1 1 1 1 0
(SC13)
Automatic transfer interval set bits: 32 cycles of transfer clock
Internal synchronous clock: f(XIN)/32
Serial I/O1 automatic transfer data pointer (address 001816)
0716
SIO1DP
Set low-order 8 bits of address 0F0716 (=0716)
Transfer counter (address 001B16)
Set the number of transfer bytes – 1 = 7
(Automatic transfer starts by writing to this register
when selecting an internal synchronous clock.)
0716
SIO1
Automatic transfer RAM of serial I/O (addresses 0F0016 to 0FFF16)
SIORAM
0F0016
0F0116
DO7
DO6
0F0016
0F0116
DI7
DI6
0F0616
0F0716
DI1
DI0
Transfer counter
Serial I/O1
automatic transfer
data pointer
0F0616
0F0716
0716
0716
DO1
DO0
Automatic transfer executed
The area of addresses 0F0816 to 0FFF16, which is not used as automatic transfer,
can be used as normal RAM.
Fig. 2.3.29 Relevant registers setting
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APPLICATION
2.3 Serial I/O
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SC11 (address 001916)
SC12 (address 001A16)
SC13 (address 001C16)
SIO1DP (address 001816)
SC11 (address 001916), bit4
000000112
00XX00002
011111102
0716
1
Serial I/O1 initial setting
Setting of automatic transfer function
Enabled serial I/O1
.....
The time to control main routine
period has passed ?
N
Generating certain period timing using timer’s functions
(Control so that main routine will be executed at certain
period.)
Y
Automatic transfer RAM of
serial I/O (addresses 0F0016
to 0F0716)
SIO1 (address 001B16)
Transmitted
data RAM
1-block data, 8 bytes, to be transmitted set in RAM
Number of transferred count set causing automatic
transfer start
(Set the number of transfer bytes – 1.)
8–1
Possible to process others during automatic transfer
(Perform part of main processing.)
1
SIO1CON2 (address 001A16), bit5 ?
Judgment of completion of automatic transfer
0
Received data
RAM
Automatic transfer RAM of
serial I/O (addresses 0F0016
to 0F0716)
Main processing
Taking received data into RAM for processing
Processing data taken into received data
RAM and preparing next transmission data in
main routine
Fig. 2.3.30 Control procedure
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APPLICATION
2.3 Serial I/O
2.3.6 Serial I/O2 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.31 shows connection examples with peripheral ICs equipped with the CS pin.
(1) Only transmission
(Using RxD pin as I/O port)
Port
SCLK21
TxD
38B7 group
(2) Transmission and reception
CS
Port
CLK
SCLK21
DATA
Peripheral IC
(OSD controller etc.)
Port
SCLK21
TxD
IN
RxD
OUT
38B7 group
(3) Transmission and reception
(When connecting RxD with TxD)
(When connecting IN with OUT in
peripheral IC)
CS
CLK
Peripheral IC
(EEPROM etc.)
(4) Connection of plural IC
CS
Port
CS
SCLK21
TxD
CLK
IN
TxD
IN
RxD
OUT
RxD
OUT
38B7 group ✽1
Port
Peripheral IC ✽2
(EEPROM etc.)
CLK
Peripheral IC 1
38B7 group
✽1: Select an N-channel open-drain output for TxD pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.31 Serial I/O2 connection examples (1)
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APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.32 shows connection examples with another microcomputer.
(1) Selecting internal clock
SCLK21
(2) Selecting external clock
CLK
SCLK21
CLK
TxD
IN
TxD
IN
RxD
OUT
RxD
OUT
38B7 group
Microcomputer
38B7 group
(3) Using SRDY2 signal output function
(Selecting external clock)
Microcomputer
(4) Using switch function of CLK signal output
pins, SCLK22, (Selecting internal clock)
SRDY2
RDY
SCLK21
SCLK21
CLK
TxD
IN
TxD
IN
RxD
OUT
RxD
OUT
38B7 group
CLK
SCLK22
Port
Microcomputer
Microcomputer
38B7 group
CLK
IN
OUT
CS
(5) In UART
Peripheral IC
TxD
RxD
RxD
TxD
38B7 group
Microcomputer
Fig. 2.3.32 Serial I/O2 connection examples (2)
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APPLICATION
2.3 Serial I/O
2.3.7 Serial I/O2’s modes
A clock synchronous or clock asynchronous (UART) can be selected for the serial I/O2.
Figure 2.3.33 shows the serial I/O2’s modes, and Figure 2.3.34 shows the serial I/O2 transfer data format.
Internal clock
Output SRDY2 signal
Clock synchronous serial I/O
External clock
Serial I/O2
Not output SRDY2 signal
Clock asynchronous serial I/O
(UART)
Fig. 2.3.33 Serial I/O2’s modes
Clock synchronous serial I/O
1ST-8DATA-1SP
ST
LSB
MSB SP
1ST-7DATA-1SP
Serial I/O2
ST
LSB
MSB SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB PAR SP
1ST-7DATA-1PAR-1SP
ST
LSB
MSB PAR SP
UART
1ST-8DATA-2SP
ST
LSB
MSB 2SP
1ST-7DATA-2SP
ST
LSB
MSB 2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB PAR 2SP
1ST-7DATA-1PAR-2SP
ST
LSB
MSB PAR 2SP
Fig. 2.3.34 Serial I/O2 transfer data format
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APPLICATION
2.3 Serial I/O
2.3.8 Serial I/O2 application examples
(1) Communication (transmission/reception) using clock synchronous serial I/O
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The S RDY2 signal is used for communication control.
Figure 2.3.35 shows a connection diagram, and Figure 2.3.36 shows a timing chart.
P70/INT0
SRDY2
SCLK21
SCLK21
RxD
TxD
38B7 group
38B7 group
Fig. 2.3.35 Connection diagram
Specifications : •
•
•
•
Use of serial I/O2 in clock synchronous serial I/O
Synchronous clock frequency : 125 kHz (f(XIN ) = 4 MHz is divided by 32)
Use of SRDY2 (receivable signal)
The reception side outputs the SRDY2 signal at intervals of 2 ms (generated by the
timer), and 2-byte data is transferred from the transmission side to the reception
side.
SRDY2
…
SCLK21
…
TxD
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
2 ms
Fig. 2.3.36 Timing chart
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D0 D1
…
APPLICATION
2.3 Serial I/O
Figure 2.3.37 shows the registers setting relevant to the transmission side, and Figure 2.3.38 shows
the registers setting relevant to the reception side.
Transmission side
Serial I/O2 status register (address 001E16)
SIO2STS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O2 control register (address 001D16)
SIO2CON
1 1
0 1
0 0 0
BRG count source: f(XIN)
Synchronous clock: BRG/4
SRDY2 output not used
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 003816)
UARTCON
0 0 0
P65/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 003716)
BRG
Set “division ratio – 1”
0716
Interrupt edge selection register (address 003A16)
INTEDGE
0
INT0 falling edge active
Fig. 2.3.37 Registers setting relevant to transmission side
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APPLICATION
2.3 Serial I/O
Reception side
Serial I/O2 status register (address 001E16)
SIO2STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 1 1
1 1
Synchronous clock: External clock input
SRDY2 output enabled
Transmit enabled
When using SRDY2 output, set this bit to “1”.
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 003816)
UARTCON
Serial I/O2 clock: SCLK21
Fig. 2.3.38 Registers setting relevant to reception side
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APPLICATION
2.3 Serial I/O
Figure 2.3.39 shows a control procedure of the transmission side, and Figure 2.3.40 shows a control
procedure of the reception side.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIO2CON (address 001D16)
UARTCON (address 003816)
BRG (address 003716)
INTEDGE (address 003A16), bit0
1101X0002
X000XXXX2
8–1
0
• Serial I/O2 setting
.....
IREQ1 (address 003C16), bit0 ?
0
• Detection of INT0 falling edge
1
IREQ1 (address 003C16), bit0
0
• Transmission data write
Transmit buffer empty flag is set to “0” by this writing.
The first byte of a
transmission data
TB/RB (address 001F16)
SIO2STS (address 001E16), bit0 ?
0
• Judgment of transferring from Transmit buffer
register to Transmit shift register
(Transmit buffer empty flag)
1
• Transmission data write
Transmit buffer empty flag is set to “0” by this writing.
The second byte of
a transmission data
TB/RB (address 001F16)
SIO2STS (address 001E16), bit0 ?
0
• Judgment of transferring from Transmit buffer
register to Transmit shift register
(Transmit buffer empty flag)
1
SIO2STS (address 001E16), bit2 ?
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
Fig. 2.3.39 Control procedure of transmission side
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APPLICATION
2.3 Serial I/O
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIO2CON (address 001D16)
UARTCON (address 003816), bit6
1111X11X2
0
• Serial I/O2 setting
.....
0
2ms has passed ?
1
• SRDY2 output
SRDY2 signal is output by writing data to
the TB/RB.
When using SRDY2, set Transmit enable
bit (bit4) of SIO2CON to “1.”
Dummy data
TB/RB (address 001F16)
SIO2STS (address 001E16), bit1 ?
• An interval of 2 ms generated by Timer.
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data.
Receive buffer full flag is set to “0” by reading
data.
Read out reception data from
TB/RB (address 001F16)
SIO2STS (address 001E16), bit1 ?
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (address 001F16)
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
Fig. 2.3.40 Control procedure of reception side
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APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting port P77 with the CS pin of a peripheral IC.
Figure 2.3.41 shows a connection diagram, and Figure 2.3.42 shows a timing chart.
CS
P77
CS
CLK
SCLK21
CLK
DATA
TxD
DATA
38B7 group
Peripheral IC
Fig. 2.3.41 Connection diagram
Specifications : • Use of serial I/O2 in clock synchronous serial I/O
• Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of receive/transmit interrupts of serial I/O2
• Port P77 is connected with the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P7 7 is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Fig. 2.3.42 Timing chart
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APPLICATION
2.3 Serial I/O
Figure 2.3.43 shows the relevant registers setting and Figure 2.3.44 shows the setting of transmission
data.
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 0 1 1 0 0 0
BRG count source: f(XIN)
Synchronous clock: BRG/4
SRDY2 output not used
Transmit interrupt source: When transmit shift operation is completed
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 003816)
0 0 0
UARTCON
P65/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 003716)
BRG
Set “division ratio – 1”
0716
Interrupt control register 2 (address 003F16)
ICON2 0
0
INT3/Serial I/O2 transmit interrupt: Disabled
Interrupt request register 2 (address 003D16)
IREQ2
0
INT3/serial I/O2 transmit interrupt request cleared
Confirm transmission completion of 1-byte unit.
Fig. 2.3.43 Relevant registers setting
Serial I/O2 transmit/receive buffer register (001F16)
Set a transmission data.
Confirm that transmission of the previous data is
completed, where bit 4, the INT3/serial I/O2
transmit interrupt request bit of the interrupt
request register 2, is “1”; before writing data.
TB/RB
Fig. 2.3.44 Setting of transmission data
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APPLICATION
2.3 Serial I/O
Figure 2.3.45 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIO2CON (address 001D16)
UARTCON (address 003816)
BRG (address 003716)
ICON2 (address 003F16), bit4
P7 (address 000E16), bit7
P7D (address 000F16), bit7
Serial I/O2 setting
110110002
X000XXXX2
8– 1
0
1
1
INT3/Serial I/O2 transmit interrupt: Disabled
CS signal output level to “H” setting
CS signal output port setting
.....
P7 (address 000E16), bit7
CS signal output level to “L” setting
IREQ2 (address 003D16), bit4
TB/RB (address 001F16)
INT3/Serial I/O2 transmit interrupt request bit to “0” setting
Transmission data write
(Start of 1-byte data transmission)
Transmission data
IREQ2 (address 003D16), bit4 ?
0
Judgment of completion of transmitting 1-byte
data
1
N
All data has been transmitted ?
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
Y
P7 (address000E16), bit7
1
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
Fig. 2.3.45 Control procedure
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APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.3.46 shows a connection diagram.
SCLK21
SCLK21
R XD
T XD
T XD
R XD
38B7 group
Master unit
38B7 group
Slave unit
Fig. 2.3.46 Connection diagram
Specifications: •
•
•
•
•
•
•
•
•
Use of serial I/O2 in clock synchronous serial I/O
Synchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32.)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 bytes/block each
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Transfer direction : LSB first
Limitations of the specifications:
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O2 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.47. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 bytes) is received, the clock is ignored.
Figure 2.3.48 shows the relevant registers setting in the master unit and Figure 2.3.49 shows the
relevant registers setting in the slave unit.
D0
D1
D2
D7
D0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.3.47 Timing chart
Master unit
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 1 1 1 0 0 0
BRG count source : f(XIN)
Synchronous clock : BRG/4
SRDY2 output disabled
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 003816)
UARTCON
0 0 0
P65/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 003716)
0716
Set “division ratio – 1”
Fig. 2.3.48 Relevant registers setting in master unit
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APPLICATION
2.3 Serial I/O
Slave unit
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 1 1
0 1
Synchronous clock : External clock
SRDY2 output disabled
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 003816)
UARTCON
0
0
P65/TxD pin: CMOS output
Serial I/O2 clock: SCLK21
Fig. 2.3.49 Relevant registers setting in slave unit
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APPLICATION
2.3 Serial I/O
Control procedure by software:
● Control in the master unit
After setting the relevant registers shown in Figure 2.3.48, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the serial I/O2 transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.47, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O2 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the serial I/O2
transmit buffer register.
Figure 2.3.50 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 500 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Pushing the register used in the interrupt
processing routine into the stack
●
Within a block transfer
period?
N
Generating a certain block interval by
using a timer or other functions
Y
●
Count a block interval counter
Read a reception data
Complete to transfer
a block?
Y
Start a block transfer?
N
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
Check of the block interval counter and
determination to start a block transfer
●
Popping registers which is pushed to stack
RTI
Fig. 2.3.50 Control procedure of master unit
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APPLICATION
2.3 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.3.49, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O2 receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O2 receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O2 receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.51 shows a control procedure of the slave unit using the serial I/O2 receive interrupt
and any timer interrupt (for heading adjustment).
Serial I/O2 receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
Within a block transfer
term?
N
Pushing the register used in
the interrupt processing
routine into the stack
Confirmation of the received
byte counter to judge the
block transfer term
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Heading adjustment
counter – 1
Y
N
Heading adjustment
counter = 0?
Read a reception data
Pushing the register used
in the interrupt processing
routine into the stack.
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte
counter ≥ 8?
A received byte counter
N
0
Y
Pop registers
Write a transmission data
Write dummy data (FF 16)
●
Popping registers which is
pushed to stack
RTI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
RTI
●
Popping registers which is
pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.3.51 Control procedure of slave unit
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APPLICATION
2.3 Serial I/O
(4) Communication (transmission/reception) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P7 6 is used for communication control.
Figure 2.3.52 shows a connection diagram, and Figure 2.3.53 shows a timing chart.
Transmission side
Reception side
P76
P76
T XD
RXD
38B7 group
38B7 group
Fig. 2.3.52 Connection diagram
Specifications : • Use of serial I/O2 in UART
• Transfer bit rate : 9600 bps (f(XIN) = 3.6864 MHz is divided by 384)
• Data format : 1ST-8DADA-2ST
• Communication control using port P76
(The output level of port P76 is controlled by softoware.)
• 2-byte data is transferred from the transmission side to the receiption side at
intervals of 10 ms generated by the timer.
P76
T XD
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
S T D0
10 ms
Fig. 2.3.53 Timing chart
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APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values.
Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values
Transfer bit rate
(Note 1)
600
f(XIN) = 3.6864 MHz
BRG count BRG setting
source (Note 2)
value
f(XIN)/4
95(5F16 )
f(X IN) = 4 MHz
Actual rate
600.00
BRG count
BRG setting
source (Note 2)
value
f(X IN)/4
103(6716 )
Actual rate
600.96
1200
f(XIN)/4
47(2F16 )
1200.00
f(X IN)/4
51(33 16 )
1201.92
2400
f(XIN)/4
23(17 16 )
2400.00
f(X IN)/4
25(19 16 )
2403.85
4800
f(XIN)/4
11(0B16 )
4800.00
f(X IN)/4
12(0C16 )
4807.69
9600
f(XIN)/4
5(0516 )
9600.00
f(XIN)
25(19 16 )
9615.38
19200
f(XIN)/4
2(0216 )
19200.00
f(XIN)
12(0C16 )
19230.77
38400
f(XIN)
5(0516 )
38400.00
f(XIN)
5(0516 )
41666.67
76800
f(XIN)
2(0216 )
76800.00
f(XIN)
2(0216 )
83333.33
31250
—
—
—
f(XIN)
7(0716 )
31250.00
62500
—
—
—
f(XIN)
3(0316 )
62500.00
Notes 1: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the serial I/O2 control register (address 001D 16 ) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O2 control register is set to “1”, a value of m is 4.
2: Select the BRG count source with bit 0 of the serial I/O2 control register (address 001D 16).
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APPLICATION
2.3 Serial I/O
Figure 2.3.54 shows the registers setting relevant to the transmission side; Figure 2.3.55 shows the
registers setting relevant to the reception side.
Transmission side
Serial I/O2 status register (address 001E16)
b7
b0
SIO2STS
Transmit buffer empty flag
• Confirm that tha data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O2 control register (address 001D16)
b7
b0
SIO2CON 1 0 0 1
0 0 1
BRG count source : f(XIN)/4
Serial I/O2 synchronous clock BRG/16
SRDY2 output disabled
Transmit enabled
Receive disabled
Asynchronous serial I/O (UART)
Serial I/O2 enabled
UART control register (address 003816)
b7
UARTCON
b0
0 0 1
0 0
Character length 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
P65/TXD pin : CMOS output
BRG clock : f(XIN)
Baud rate generator (address 003716)
b7
B RG
b0
0516
Set
f(XIN)
Transfer bit rate ✕16 ✕ m
✽
–1
✽ When bit 0 of SIO2CON (address 001D16) is set to “0”,
a value of m is 1.
When bit 0 of SIO2CON is set to “1”, a value of m is 4.
Fig. 2.3.54 Registers setting relevant to transmission side
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APPLICATION
2.3 Serial I/O
Reception side
Serial I/O2 status register (address 001E16)
b7
b0
SIO2STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O2 control register (address 001D16)
b7
SIO2CON
b0
1 0 1 0
0 0 1
BRG count source : f(XIN)/4
Serial I/O synchronous clock : BRG/16
SRDY2 output disabled
Transmit disabled
Receive enabled
Asynchronous serial I/O (UART)
Serial I/O2 enabled
UART control register (address 003816)
b7
UARTCON
b0
0
1
0 0
Character length 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
BRG clock: f(XIN)
Baud rate generator (address 003716)
b7
BRG
b0
0516
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m
✽
–1
✽ When bit 0 of SIO2CON (address 001D16) is set to “0”,
a value of m is 1.
When bit 0 of SIO2CON is set to “1”, a value of m is 4.
Fig. 2.3.55 Registers setting relevant to reception side
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APPLICATION
2.3 Serial I/O
Figure 2.3.56 shows a control procedure of the transmission side, and Figure 2.3.57 shows a control
procedure of the reception side.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
• Serial I/O2 setting
• Port P76 set for communication control
.....
1001X0012
SIO2CON (address 001D16)
XX001X002
UARTCON (address 003816)
6–1
(address 003716)
BRG
0
(address 000E16), bit6
P7
1
(address 000F16), bit6
P7D
N
10 ms has passed ?
• An interval of 10 ms generated by Timer
Y
P7 (address 000E16), bit6
TB/RB (address 001F16)
• Communication start
1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
SIO2STS (address 001E16), bit0?
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
TB/RB (address 001F16)
The second byte of
a transmission data
SIO2STS (address 001E16), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
SIO2STS (address 001E16), bit2?
1
P7 (address 000E16), bit6
0
• Communication completion
Fig. 2.3.56 Control procedure of transmission side
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APPLICATION
2.3 Serial I/O
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIO2CON (address 001D16) 1010X0012
UARTCON (address 003816)
XX0X1X002
BRG
(address 003716)
6–1
P7D
(address 000F16), bit6
0
SIO2STS (address 001E16), bit1?
0
• Serial I/O2 setting
• Port P76 setting for communication control
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from TB/RB (address 001F16)
SIO2STS (address 001E16), bit6?
1
• Judgment of an error flag
0
• Judgment of completion of
receiving
(Receive buffer full flag)
0
SIO2STS (address 001E16), bit1?
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from TB/RB (address 001F16)
SIO2STS (address 001E16), bit0?
1
• Judgment of an error flag
Processing for error
0
1
P7 (address 000E16), bit6?
0
SIO2CON (address 001D16)
SIO2CON (address 001D16)
0000X0012
1010X0012
• Countermeasure for a bit slippage
Fig. 2.3.57 Control procedure of reception side
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APPLICATION
2.3 Serial I/O
2.3.9 Serial I/O3 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.58 shows connection examples with peripheral ICs equipped with the CS pin.
(1) Only transmission
(Using SIN3 pin as I/O port)
Port
(2) Transmission and reception
CS
SCLK3
CLK
Port
SCLK3
SOUT3
DATA
SOUT3
CS
CLK
IN
SIN3
OUT
38B7 group
Peripheral IC
(OSD controller etc.)
38B7 group
(3) Transmission and reception
(When connecting SIN3 with SOUT3)
(When connecting IN with OUT in
peripheral IC)
Port
SCLK3
(4) Connection of plural IC
SOUT3
CLK
IN
Port
SCLK3
SOUT3
SIN3
OUT
SIN3
38B7 group✽1
Peripheral IC
(EEPROM etc.)
CS
Port
Peripheral IC ✽2
(EEPROM etc.)
CS
CLK
IN
OUT
Peripheral IC 1
38B7 group
✽1: Select an N-channel open-drain output for SOUT3 pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.58 Serial I/O3 connection examples (1)
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APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.59 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK3
CLK
SCLK3
CLK
SOUT3
IN
SOUT3
IN
SIN3
38B7 group
OUT
SIN3
Microcomputer
38B7 group
(3) Using SRDY3 signal output function
(Selecting external clock)
SRDY3
RDY
SCLK3
CLK
SOUT3
IN
SIN3
38B7 group
OUT
Microcomputer
Fig. 2.3.59 Serial I/O3 connection examples (2)
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OUT
Microcomputer
APPLICATION
2.3 Serial I/O
2.3.10 Serial I/O3’s modes
Figure 2.3.60 shows the serial I/O3’s modes.
Internal
clock
Serial I/O3
Output SRDY3 signal
External
clock
No output SRDY3 signal
Fig. 2.3.60 Serial I/O3’s modes
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APPLICATION
2.3 Serial I/O
2.3.11 Serial I/O3 application examples
(1) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting ports with the CS pin of a peripheral IC.
Figure 2.3.61 shows a connection diagram, and Figure 2.3.62 shows a timing chart.
CS
PB1
CS
CLK
P92/SCLK3
CLK
DATA
P91/SOUT3
DATA
38B7 group
Peripheral IC
Fig. 2.3.61 Connection diagram
Specifications : • Use of serial I/O3
• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of serial I/O3 interrupt
• Port PB1 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port PB1 is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
Fig. 2.3.62 Timing chart
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DO3
APPLICATION
2.3 Serial I/O
Figure 2.3.63 shows the registers setting relevant to the transmission side, and Figure 2.3.64 shows
the setting of transmission data.
Serial I/O3 control register 1 (address 0EEC16)
SIO3CON 0 1 0 0 1 0 1 1
Internal synchronous clock: f(XIN)/32
Ports P91 and P92: SOUT3 and SCLK3 signals output
Port P93/SRDY3: I/O port
LSB first
Internal clock
Port P91/SOUT3: CMOS output (in output mode)
Port PB (address 001616)
1
Set PB1 output level to “H”
Port PB direction register (address 001716)
1
PBD
Set PB1 to output mode
Fig. 2.3.63 Registers setting relevant to transmission side
Serial I/O3 register (0EED16)
Set a transmission data.
Confirm that transmission of the previous
data is completed, where bit 1, the
INT1/serial I/O3 interrupt request bit of the
interrupt request register 1, is “1”; before
writing data.
SIO3
Fig. 2.3.64 Setting of transmission data
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APPLICATION
2.3 Serial I/O
Control procedure: When the registers are set as shown in Figure 2.3.65, the serial I/O3 can transmit
1-byte data by writing data to the serial I/O3 register.
Thus, after setting the CS signal to “L”, write the transmission data to the serial
I/O3 register by each 1 byte; and return the CS signal to “H” when the target
number of bytes has been transmitted.
Figure 2.3.65 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIO3CON (address 0EEC16)
PB (address 001616), bit1
PBD (address 001716), bit1
Serial I/O3 setting
CS signal output level to “H” setting
CS signal output port setting
010010112
1
1
.....
PB (address 001616), bit1
IREQ1 (address 003C16), bit1
SIO3 (address 0EED16)
CS signal output level to “L” setting
0
0
Transmission data write
(Start of 1-byte data transmission)
Transmission data
IREQ1 (address 003C16), bit1 ?
N
INT1/serial I/O3 interrupt request bit to “0” setting
All data have been transmitted ?
1
Judgment of completion of transmitting 1-byte data
Use any of RAM area as a counter for counting the
number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
Y
PB (address 001616), bit1
1
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
Fig. 2.3.65 Control procedure
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APPLICATION
2.3 Serial I/O
2.3.12 Notes on serial I/O1
(1) Clock
■ Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before perform the normal serial I/O transfer or the serial I/O automatic transfer.
■ Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit
before performing the normal serial I/O transfer or the serial I/O automatic transfer.
(2) Using serial I/O1 interrupt
Clear bit 3 of the interrupt request register 1 to “0” by software before enabling interrupts.
(3) State of SOUT1 pin
The S OUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the
S OUT1 pin when serial data is not transferred; either output active or high-impedance. However, when
selecting an external synchronous clock; the S OUT1 pin can become the high-impedance state by
setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.
(4) Serial I/O initialization bit
● Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a
serial transfer during transferring.
● When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is
not initialized. Set the value of each register by program.
(5) Handshake signal
■ S BUSY1 input signal
Input an “H” level to the SBUSY1 input and an “L” level signal to the SBUSY1 input in the initial state.
When the external synchronous clock is selected, switch the input level to the S BUSY1 input and
the SBUSY1 input while the serial I/O1 clock input is in “H” state.
■ S RDY1 input•output signal
When selecting the internal synchronous clock, input an “L” level to the S RDY1 input and an “H”
level signal to the S RDY1 input in the initial state.
(6) 8-bit serial I/O mode
■ When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O1 register are being
shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control
the clock externally.
(7) In automatic transfer serial I/O mode
■ Set of automatic transfer interval
● When the S BUSY1 output is used, and the SBUSY1 output and the S STB1 output function as signals
for each transfer data set by the S BUSY1 output•SSTB1 output function selection bit of serial I/O1
control register 2; the transfer interval is inserted before the first data is transmitted/received,
and after the last data is transmitted/received. Accordingly, regardless of the contents of the
S BUSY1 output•SSTB1 output function selection bit, this transfer interval for each 1-byte data becomes
2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 control
register 3.
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APPLICATION
2.3 Serial I/O
● When using the SSTB1 output, regardless of the contents of the SBUSY1 output•S STB1 output function
selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value
set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the combined output of SBUSY1 and SSTB1 as the signal for each of all transfer data
set, the transfer interval after completion of transmission/reception of the last data becomes 2
cycles longer than the value set by the automatic transfer interval set bits.
● When selecting an external clock, the set of automatic transfer interval becomes invalid.
● Set the transfer interval of each 1-byte data transfer as the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system clock from clock rising of the last
bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 17 cycles or more of internal system clock from clock rising of the
last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 27 cycles or more of internal system clock from clock rising of the
last bit of 1-byte data.
<Serial I/O1 control register 3, SIO1CON3 (address 001C16 ) setting example>
Table 2.3.2 SIO1CON3 (address 001C16) setting example selecting internal synchronous clock
Serial I/O1 control register
Internal synchronous clock
selection bits (b7 to b5)
0 0 0 : f(X IN ) / 4
0 0 1 : f(X IN ) / 8
0 1 0 : f(X IN) / 16
3, SIO1CON3 (address 001C 16)
Automatic transfer interval set bits
(b4 to b0)
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 1 0 : 4 cycles of transfer clocks
0 0 0 1 1 : 5 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
Not using
FLDC
Usable
Usable
Usable
Usable
Usable
Usable
Usable
Not using Using gradation display
gradation
mode
display mode
Prohibited
Prohibited
Prohibited
Usable
Prohibited
Usable
Usable
Prohibited
Prohibited
Prohibited
Usable
Prohibited
Usable
Usable
Table 2.3.3 SIO1CON3 (address 001C16) setting example selecting external synchronous clock
Serial I/O1 control register 3,
“n” cycles of transfer clocks
SIO1CON3 (address 001C 16 ),
Automatic transfer interval set bits
Not using FLDC
Not using gradation display mode
Using gradation display mode
Transfer clock ✕ n cycles ≥ 5 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 17 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 27 cycles of internal system clock
■ Set of serial I/O1 transfer counter
● Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer
counter.
● When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,
wait for 5 or more cycles of internal system clock before inputting the transfer clock to the serial
I/O1 clock pin.
■ Serial I/O initialization bit
A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O
initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.
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APPLICATION
2.3 Serial I/O
2.3.13 Notes on serial I/O2
(1) Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit
to “0” (serial I/O2 disabled).
➂ Stop of transmit/receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit
and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to
“0” (serial I/O2 disabled) (refer to (1), ➀).
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APPLICATION
2.3 Serial I/O
(2) Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3) S RDY2 output of reception side
When signals are output from the SRDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
Fig. 2.3.66 Sequence of setting serial I/O2 control register again
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APPLICATION
2.3 Serial I/O
(5) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.
(7) Setting procedure when serial I/O2 transmit interrupt is used
When setting the transmit enable bit to “1”, the serial I/O2 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled,
take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been
executed.
➃Set the serial I/O1 tranmit interrupt enable bit to “1” (enabled).
(8) Using TxD pin
The P65/TxD P-channel output disable bit of UART control register is valid in both cases: using as
a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P6 5/
TxD pin as an N-channel open-drain output.
Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after
completing transmission.
38B7 Group User’s Manual
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APPLICATION
2.4 FLD controller
2.4 FLD controller
This paragraph describes the setting method of FLD controller relevant registers, notes etc.
2.4.1 Memory assignment
Address
003D16
Interrupt request register 2 (IREQ2)
003E16
(Interrupt control register 1 (ICON1))
003F16
Interrupt control register 2 (ICON2)
0EF216
Port P0 digit output set switch register (P0DOR)
0EF316
Port P2 digit output set switch register (P2DOR)
0EF416
FLDC mode register (FLDM)
0EF516
0EF616
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
0EF716
Toff2 time set register (TOFF2)
0EF816
FLD data pointer (FLDDP)
0EF916
Port P4FLD/port switch register (P4FPR)
0EFA16
Port P5FLD/port switch register (P5FPR)
0EFB16
Port P6FLD/port switch register (P6FPR)
0EFC16
FLD output control register (FLDCON)
Fig. 2.4.1 Memory assignment of FLD controller relevant registers
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APPLICATION
2.4 FLD controller
2.4.2 Relevant registers
Port P0 digit output set switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 digit output set switch register
(P0DOR: address 0EF216)
b
Name
0 Port P00 FLD/Digit
switch bit
1 Port P01 FLD/Digit
switch bit
2 Port P02 FLD/Digit
switch bit
3 Port P03 FLD/Digit
switch bit
4 Port P04 FLD/Digit
switch bit
5 Port P05 FLD/Digit
switch bit
6 Port P06 FLD/Digit
switch bit
Port
P07 FLD/Digit
7
switch bit
Functions
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.2 Structure of Port P0 digit output set switch register
Port P2 digit output set switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 digit output set switch register
(P2DOR: address 0EF316)
b
Name
0 Port P20 FLD/Digit
switch bit
1 Port P21 FLD/Digit
switch bit
2 Port P22 FLD/Digit
switch bit
3 Port P23 FLD/Digit
switch bit
4 Port P24 FLD/Digit
switch bit
5 Port P25 FLD/Digit
switch bit
6 Port P26 FLD/Digit
switch bit
Port
P27 FLD/Digit
7
switch bit
Functions
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.3 Structure of Port P2 digit output set switch register
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APPLICATION
2.4 FLD controller
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
b
Name
Functions
At reset R W
0 Automatic display
control bit
0 : General-purpose mode
1 : Automatic display
mode
0
1 Display start bit
0 : Display stopped
1 : Display in progress (display
starts by writing “1”)
0
2 Tscan control bits
b3 b2
0
3
0 0 : FLD digit interrupt
(at rising edge of each
digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
1 1 : 3 ✕ Tdisp
FLD blanking interrupt (at
falling edge of last digit)
0
4 Timing number
control bit
0 : 16 timing mode
1 : 32 timing mode (Note 2)
0
5 Gradation display
mode selection
control bit
6 Tdisp counter count
source selection bit
0 : Not selected
1 : Selected (Notes 1, 2)
0
0 : f(XIN)/16
1 : f(XIN)/64
0
0 : Drivability strong
1 : Drivability weak
0
7 High-breakdown
voltage port drivability selection bit
Notes 1: When the gradation display mode is selected, the number of
timing is max. 16 timing. (Set “0” to the timing number control
bit (b4).)
2: When switching the timing number control bit (b4) or the
gradation display mode selection control bit (b5), set “0” to the
display start bit (b1) (display stop state) before that.
Fig. 2.4.4 Structure of FLDC mode register
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APPLICATION
2.4 FLD controller
Tdisp time set register
b7 b6 b5 b4 b3 b2 b1 b0
Tdisp time set register
(TDISP: address 0EF516)
b
Functions
0
•Set the Tdisp time.
•When a value n is written to this register, Tdisp
time is expressed as Tdisp = (n + 1) ✕ count
source.
•When reading this register, the value in the
counter is read out.
0
(Example)
When the following condition is satisfied, Tdisp
becomes 804 µs {(200 + 1) ✕ 4 µs};
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source. )
•Tdisp time set register = 200 (C816).
0
1
2
3
4
At reset R W
0
0
0
5
0
6
0
7
0
Fig. 2.4.5 Structure of Tdisp time set register
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APPLICATION
2.4 FLD controller
Toff1 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff1 time set register
(TOFF1: address 0EF616)
b
0
1
2
3
4
5
Functions
•Set the Toff1 time.
•When a value n1 is written to this register,
Toff1 time is expressed as Toff1 = n1 ✕ count
source.
(Example)
When the following condition is satisfied, Toff1
becomes 120 µs (= 30 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff1 time set register = 30 (1E16).
At reset R W
1
1
1
1
1
1
6
1
7
1
Note: Set value of 0316 or more.
Fig. 2.4.6 Structure of Toff1 time set register
Toff2 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff2 time set register
(TOFF2: address 0EF716)
b
Functions
0
•Set the Toff2 time.
•When a value n2 is written to this register,
Toff2 time is expressed as Toff2 = n2 ✕ count
source.
However, setting of Toff2 time is valid only for
the FLD port which is satisfied the following;
•gradation display mode
•value of FLD automatic display RAM (in
gradation display mode) = “1” (dark display).
1
(Example)
When the following condition is satisfied, Toff2
becomes 720 µs (= 180 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff2 time set register = 180 (B416).
1
1
2
3
4
5
6
7
At reset R W
1
1
1
1
1
1
Note: When the Toff2 SET/RESET switch bit (b7) of the FLD output
control register (address 0EFC16) is set to “1”, set value of 0316
or more to the Toff2 time set register.
Fig. 2.4.7 Structure of Toff2 time set register
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APPLICATION
2.4 FLD controller
FLD data pointer/FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0
FLD data pointer/FLD data pointer reload register
(FLDDP: address 0EF816)
b
Functions
0
The start address of each data of FLD ports P6,
P5, P4, P3, P1, P0, and P2, which is
transferred from FLD automatic display RAM, is
set to this register.
The start address becomes the address adding
the value set to this register into the last data
address of each FLD port.
Set a value of (timing number – 1) to this
register.
1
2
3
4
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
The value which is set to this address is written
to the FLD data pointer reload register.
Undefined
When reading data from this address, the value
in the FLD data pointer is read.
Undefined
When bits 5 to 7 of this register is read, “0” is
always read.
Undefined
Fig. 2.4.8 Structure of FLD data pointer/FLD data pointer reload register
Port P4FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P4FLD/port switch register
(P4FPR: address 0EF916)
b
0
1
2
3
4
5
6
7
Name
Port P40 FLD/port
switch bit
Port P41 FLD/port
switch bit
Port P42 FLD/port
switch bit
Port P43 FLD/port
switch bit
Port P44 FLD/port
switch bit
Port P45 FLD/port
switch bit
Port P46 FLD/port
switch bit
Port P47 FLD/port
switch bit
Functions
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.9 Structure of port P4FLD/port switch register
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APPLICATION
2.4 FLD controller
Port P5FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5FLD/port switch register
(P5FPR: address 0EFA16)
b
0
1
2
3
4
5
6
7
Name
Port P50 FLD/port
switch bit
Port P51 FLD/port
switch bit
Port P52 FLD/port
switch bit
Port P53 FLD/port
switch bit
Port P54 FLD/port
switch bit
Port P55 FLD/port
switch bit
Port P56 FLD/port
switch bit
Port P57 FLD/port
switch bit
Functions
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.10 Structure of port P5FLD/port switch register
Port P6FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6FLD/port switch register
(P6FPR: address 0EFB16)
b
0
1
2
3
4
5
6
7
Name
Port P60 FLD/port
switch bit
Port P61 FLD/port
switch bit
Port P62 FLD/port
switch bit
Port P63 FLD/port
switch bit
Port P64 FLD/port
switch bit
Port P65 FLD/port
switch bit
Port P66 FLD/port
switch bit
Port P67 FLD/port
switch bit
Functions
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
Fig. 2.4.11 Structure of port P6FLD/port switch register
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At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.4 FLD controller
FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
FLD output control register
(FLDCON : address 0EFC16)
b
Name
Functions
At reset R W
0 : Output normally
0 P64–P67 FLD
1 : Reverse output
output reverse bit
1 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0 : Operating normally
2 P64–P67 Toff
1 : Toff invalid
invalid bit
0
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
4 P73 dimmer output 0 : Ordinary port
control bit
1 : Dimmer output
5 Generating/Not of
0 : Toff section not
generated
CMOS port Toff
section selection bit 1 : Toff section generated
6 Generating/Not of
0 : Toff section not
high-breakdown
generated
1 : Toff section generated
voltage port Toff
section selection bit
7 Toff2 SET/RESET 0 : Toff2 RESET;
Toff1 SET
switch bit
1 : Toff2 SET;
Tdisp RESET
0
0
0
0
0
0
0
Fig. 2.4.12 Structure of FLD output control register
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APPLICATION
2.4 FLD controller
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
2 Timer 6 interrupt
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.4.13 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit
1 Timer 5 interrupt
enable bit
2 Timer 6 interrupt
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/Serial I/O2
transmit interrupt
enable bit
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
Fig. 2.4.14 Structure of Interrupt control register 2
2-100
At reset R W
38B7 Group User’s Manual
0
0
0
0
0
APPLICATION
2.4 FLD controller
2.4.3 FLD controller application examples
(1) Key-scan using FLD automatic display and segments
Outline: Key read-in with segment pins is performed by software using the FLD automatic display
mode.
SUN MON TUE WED THU FRI SAT
P10–P17 Digit
P30, P31
P00, P01
P20–P27
Segment
SP EP @
RE C
■
Segment
LEVEL
P44–P47
●
●
●
●
AM
PM
CH
L
R
Panel with fluorescent display (FLD)
38B7 Group
Key-matrix
Fig. 2.4.15 Connection diagram
Specifications: •Use of total 20 FLD ports (10 digits; 10 segments (8 key-scan included))
•Use of FLD automatic display mode
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, Tscan = 3 ✕ Tdisp = 612 µs,
f(X IN) = 4 MHz
•Use of FLD blanking interrupt
Figure 2.4.16 shows the timing chart of key-scan, and Figure 2.4.17 shows the enlarged view of
Tscan. After switching the segment pin to an output port, generate the waveform shown Figure 2.4.17
by software and perform key-scan.
Tdisp
Tscan
FLD16 (P10)
Toff1
Toff2
FLD17 (P11)
FLD18 (P12)
•••
•••
FLD25 (P31)
FLD blanking interrupt request occur
FLD0–FLD9
(P20–P27,
P00, P01)
•••
Key-scan
Fig. 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments
FLD0 (P20)
FLD1 (P21)
FLD2 (P22)
•••
•••
FLD7 (P27)
Fig. 2.4.17 Enlarged view of FLD 0 (P2 0) to FLD7 (P27) Tscan
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APPLICATION
2.4 FLD controller
Figure 2.4.18 shows the setting of relevant registers.
Port P4 direction register (address 000916)
P4D
0 0 0 0
Set P44 to P47 to input ports for key-scan input
Port P0 digit output set switch register (address 0EF216)
P0DOR
0 0
Set P00, P01 to FLD ports (FLD8, FLD9)
Port P2 digit output set switch register (address 0EF316)
P2DOR
0 0 0 0 0 0 0 0
Set P20–P27 to FLD ports (FLD0–FLD7)
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 1 1 0 1
Automatic display mode
Display stopped
Tscan = 3 ✕ Tdisp FLD blanking interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
FLD output control register (address 0EFC16)
FLDCON
0
P73 as ordinary port
Fig. 2.4.18 Setting of relevant registers
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APPLICATION
2.4 FLD controller
Tdisp time set register (address 0EF516)
TDISP
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
3216
Toff1 time set register (address 0EF616)
TOFF1
10 (0A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
0A16
Toff2 time set register (address 0EF716)
TOFF2
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1 0 0 1
Set {(digit number) – 1} = 9
Interrupt request register 2 (address 003D16)
IREQ2
0
Clear FLD blanking interrupt request bit
Interrupt control register 2 (address 003F16)
ICON2
0 1
FLD blanking interrupt: Enabled
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 1 1 1 1
Display start
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APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.1 FLD automatic display RAM map
1 to 16 timing display data stored area
Address
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
Gradation display control data stored area
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0E3016
FLD25 FLD24
0E3116
FLD25 FLD24
0E3216
FLD25 FLD24
0E3316
FLD25 FLD24
0E3416
FLD25 FLD24
0E3516
FLD25 FLD24
0E3616
FLD25 FLD24
0E3716
FLD25 FLD24
0E3816
FLD25 FLD24
0E3916
FLD25 FLD24
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4116 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4216 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4316 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4416 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4516 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4616 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4716 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4816 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4916 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
FLD9 FLD8
0E5116
FLD9 FLD8
0E5216
FLD9 FLD8
0E5316
FLD9 FLD8
0E5416
FLD9 FLD8
0E5516
FLD9 FLD8
0E5616
FLD9 FLD8
0E5716
FLD9 FLD8
0E5816
FLD9 FLD8
0E5916
FLD9 FLD8
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6116 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6216 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6316 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6416 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6516 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6616 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6716 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6816 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0E6916 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
: Area which is used to sed segment data
: Area which is used to sed digit data
: Area which is available as ordinary RAM
2-104
38B7 Group User’s Manual
Corresponding
digit pin
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
APPLICATION
2.4 FLD controller
FLD18
FLD19
FLD20
FLD21
SUN MON
SP EP
FLD22 FLD23
FLD25
a
TUE WED THU FRI SAT
•
•
•
•
f g b
AM
PM
RE C
■
FLD24
c
d
FLD17
L
R
LEVEL
e
CH
FLD16
Fig. 2.4.19 FLD digit allocation example
Table 2.4.2 FLD automatic display RAM map example
1 to 16 timing display data stored area
Address
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
Gradation display control data stored area
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PM
L
R
CH
SAT
FRI
WED
MON
SUN
–
■
g
g
g
g
g
g
g
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
b
c
b
c
b
c
b
c
b
c
b
c
b
REC SP
AM
THU
TUE
:
:
LEVEL
a
a
a
a
a
a
a
EP
Address
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PM
L
R
CH
SAT
FRI
WED
M ON
SUN
–
■
g
g
g
g
g
g
g
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
b
c
b
c
b
c
b
c
b
c
b
c
b
REC SP
AM
THU
TUE
:
:
LEVEL
a
a
a
a
a
a
a
EP
Corresponding
digit pin
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
: Unused
38B7 Group User’s Manual
2-105
APPLICATION
2.4 FLD controller
Control procedure:
●X: This bit is not used for this application.
RESET
Set “0” or “1” to this bit arbitrarily.
Initialization
••••
P4D (address 000916), bit 4–bit 7
P0DOR (address 0EF216)
P2DOR (address 0EF316)
FLDM (address 0EF416)
FLDCON (address 0EFC16)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
00002
XXXXXX002
000000002
101011012
XXX0XXXX2
3216
0A16
1016 (Note 1)
000010012
Port direction registers setting
FLD port setting
FLD automatic display function setting
••••
FLD automatic display RAM
(addresses 0EA016–0ED916)
Gradation display control
RAM
(addresses 0E3016–0E6916)
Data to be
display
Gradation display
control data (Note 1)
IREQ2 (address 003D16), bit 6
0
Gradation display control data setting
Set “1” for dark display
Set “0” for bright display (Note 2)
FLD blanking interrupt request bit cleared
Wait until writing to FLD blanking interrupt request
bit is completed
1 cycle or more wait
ICON2 (address 003F16), bit 6
FLDM (address 0EF416), bit 1
Digit data and segment data setting
1
1
FLD blanking interrupt enabled
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these
registers, too.
2: The display data can be rewritten at arbitrary
timing.
Fig. 2.4.20 Control procedure
2-106
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
FLD blanking interrupt routine
Segment key-scan
Push registers to stack, etc.
••••
FLDM (address 0EF416), bit 0
P1 (address 000216)
P3 (address 000616), bit 0, bit 1
Switching from automatic display mode to general-purpose mode
Setting of “L” level to port corresponding to digit
0
0016
002
• •••
Set data table for key-scan to P4 (address
000816)
Wait for key-scan
Wait until “H” level output of P4 is stabilized
Transfer the contents of P44 to P47 (address
000816) to RAM
Update the data table pointer for key-scan
N
Keys read-in
(Set the port P4 direction register (P4D) (address
000916) to the input mode in the initialization, etc.)
Data table reference pointer for the next key-scan updated
Key-scan is completed ? (Note)
Y
Set key-scan completion flag
Initialize data table pointer for key-scan
P4 (address 000816)
FLDM (address 0EF416), bit 0
R TI
0016
1
Setting of flag which judges whether key-scan is completed or not
Output of “L” level from all key-scan ports
Switching from general-purpose mode to the automatic
display mode
Note: If key-scan is not completed within Tscan set
time, perform key-scan separately.
38B7 Group User’s Manual
2-107
APPLICATION
2.4 FLD controller
(2) Key-scan using FLD automatic display and digits
Outline: Key read-in with digit output waveforms is performed by software using the FLD automatic
display mode.
P00, P01 Segment
P20–P27
P30, P31 Digit
SUN MON TUE WED THU FRI SAT
SP EP
RE C
■
P10–P17 Digit
LEVEL
P44–P47
●
●
●
●
AM
PM
CH
L
R
Panel with fluorescent display (FLD)
38B7 Group
Key-matrix
Fig. 2.4.21 Connection diagram
Specifications: •Use of total 20 FLD ports (10 digits, 8 key-scan included; 10 segments)
•Use of FLD automatic display mode
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, Tscan = 0 µs, f(XIN ) = 4 MHz
•Use of FLD digit interrupt
2-108
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
Figure 2.4.22 shows the timing chart of key-scan.
Tscan = 0 µs
Tdisp
FLD16 (P10)Toff1
FLD digit interrupt request occur
Toff2
FLD17 (P11)
FLD digit interrupt request occur
FLD0–FLD9
(P20–P27,
P00, P01)
FLD digit interrupt request occur
•
•
FLD digit interrupt request occur
•
•
•
FLD18 (P12)
•
•
•
FLD25 (P31)
Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits
38B7 Group User’s Manual
2-109
APPLICATION
2.4 FLD controller
Figure 2.4.23 shows the setting of relevant registers.
Port P4 direction register (address 000916)
P4D
0 0 0 0
Set P44 to P47 to input ports for key-scan input
Port P0 digit output set switch register (address 0EF216)
P0DOR
0 0
Set P00, P01 to FLD ports (FLD8, FLD9)
Port P2 digit output set switch register (address 0EF316)
P2DOR
0 0 0 0 0 0 0 0
Set P20–P27 to FLD ports (FLD0–FLD7)
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 0 1
Automatic display mode
Display stopped
FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
FLD output control register (0EFC16)
FLDCON
0
P73 as ordinary port
Fig. 2.4.23 Setting of relevant registers
2-110
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
Tdisp time set register (address 0EF516)
TDISP
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
3216
Toff1 time set register (address 0EF616)
TOFF1
10 (0A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
0A16
Toff2 time set register (address 0EF716)
TOFF2
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1 0 0 1
Set {(digit number) – 1} = 9
Interrupt request register 2 (address 003D16)
IREQ2
0
Clear FLD digit interrupt request bit
Interrupt control register 2 (address 003F16)
ICON2
0 1
FLD digit interrupt: Enabled
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 1 1
Display start
38B7 Group User’s Manual
2-111
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.3 FLD automatic display RAM map
1 to 16 timing display data stored area
Address
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
Gradation display control data stored area
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
Address
0E3016
0E3116
0E3216
0E3316
0E3416
0E3516
0E3616
0E3716
0E3816
0E3916
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016
0E4116
0E4216
0E4316
0E4416
0E4516
0E4616
0E4716
0E4816
0E4916
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
: Area which is used to set segment data
: Area which is used to set digit data
: Area which is available as ordinary RAM
2-112
Corresponding
digit pin
38B7 Group User’s Manual
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
APPLICATION
2.4 FLD controller
FLD18
FLD19
FLD20
FLD21
SUN MON
SP EP
FLD22 FLD23
FLD25
a
TUE WED THU FRI SAT
•
•
•
•
f g b
AM
PM
RE C
■
FLD24
c
d
FLD17
L
R
LEVEL
e
CH
FLD16
Fig. 2.4.24 FLD digit allocation example
Table 2.4.4 FLD automatic display RAM map example
1 to 16 timing display data stored area
Address
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
Gradation display control data stored area
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PM
CH
SAT
FRI
WED
M ON
SUN
–
■
g
g
g
g
g
g
g
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
REC
AM
THU
TUE
:
:
L
R
LEVEL
b
b
b
b
b
b
b
SP
a
a
a
a
a
a
a
EP
Address
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PM
CH
SAT
FRI
WED
M ON
SUN
–
■
g
g
g
g
g
g
g
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
REC
AM
THU
TUE
:
:
L
R
LEVEL
b
b
b
b
b
b
b
SP
a
a
a
a
a
a
a
EP
Corresponding
digit pin
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
→
→
→
→
→
→
→
→
→
→
FLD25(P31)
FLD24(P30)
FLD23(P17)
FLD22(P16)
FLD21(P15)
FLD20(P14)
FLD19(P13)
FLD18(P12)
FLD17(P11)
FLD16(P10)
: Unused
38B7 Group User’s Manual
2-113
APPLICATION
2.4 FLD controller
Control procedure:
●X: This bit is not used for this application.
RESET
Set “0” or “1” to this bit arbitrarily.
Initialization
•••
P4D (address 000916), bit 4–bit 7
P0DOR (address 0EF216)
P2DOR (address 0EF316)
FLDM (address 0EF416)
FLDCON (address 0EFC16)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
00002
XXXXXX002
000000002
101000012
XXX0XXXX2
3216
0A16
1016 (Note 1)
000010012
Port direction register setting
FLD port setting
FLD automatic display function setting
•••
FLD automatic display RAM
(addresses 0EA016–0ED916)
Gradation display control
RAM
(addresses 0E3016–0E6916)
Data to be
display
Gradation display
control data (Note 1)
IREQ2 (address 003D16), bit 6
0
Digit data and segment data setting (Note 2)
Setting of gradation display control data
Set “1” for dark display
Set “0” for bright display (Note 2)
FLD digit interrupt request bit cleared
Wait until writing to the FLD digit interrupt request
bit is completed
1 cycle or more wait
ICON2 (address 003F16), bit 6
FLDM (address 0EF416), bit 1
1
1
FLD digit interrupt enabled
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these
registers, too.
2: The display data can be rewritten at arbitrary
timing.
Fig. 2.4.25 Control procedure
2-114
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
FLD digit interrupt routine
Digit key-scan
Push registers to stack, etc.
••••
Wait until the digit output is stabilized since the digit
output waveform may become dull depending on the
PCB pattern wiring length etc.
Wait for key-scan
Transfer the contents of P44 to P47
(address 000816) to RAM
Keys read-in
(Set the port P4 direction register (P4D) (address
000916) to the input mode in the initialization, etc.)
Store the contents of RAM to the buffer
~
~
R TI
38B7 Group User’s Manual
2-115
APPLICATION
2.4 FLD controller
(3) FLD display by software (example of not used FLD controller)
Outline: FLD display and key read-in is performed, using a timer interrupt.
SUN MON TUE WED THU FRI SAT
P10–P17 Digit
P30, P31
P00, P01
P20–P27
Segment
SP EP
RE C
■
Segment
P44–P47
LEVEL
●
●
●
●
AM
PM
CH
L
R
Panel with fluorescent display (FLD)
38B7 Group
Key-matrix
Fig. 2.4.26 Connection diagram
Specifications: •Use of 10 digits and 10 segments (8 key-scan included)
•Display controlled by software
•Use of timer 1 interrupt
Figure 2.4.27 shows the timing chart of FLD display by software, and Figure 2.4.28 shows the
enlarged view of P20 to P2 7 key-scan. Generate the waveform shown in Figure 2.4.28 by software
and perform key-scan.
P10
P11
P12
•••
•••
P31
Key-scan
P20–P27,
P00, P01
•••
Fig. 2.4.27 Timing chart of FLD display by software
P20
P21
P22
•••
•••
P27
Fig. 2.4.28 Enlarged view of P20 to P2 7 key-scan
2-116
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
Figure 2.4.29 shows the setting of relevant registers.
Port P4 direction register (address 000916)
P4D
0 0 0 0
Set P44 to P47 to input ports for key scan input
FLDC mode register (address 0EF416)
FLDM
1
0 0
General-purpose mode
Display stopped
High-breakdown voltage port drivability weak
FLD output control register (address 0EFC16)
FLDCON
0
P73 as ordinary port
Interrupt request register 1 (address 003C16)
IREQ1
0
Clear timer 1 interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
1
Timer 1 interrupt: Enabled
Timer 12 mode register (address 002816)
T12M
0
Timer 1 count start
Fig. 2.4.29 Setting of relevant registers
38B7 Group User’s Manual
2-117
APPLICATION
2.4 FLD controller
P12
P13
P14
P15
P16
SUN MON
SP EP
RE C
■
P17
•
•
•
•
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PM
g
g
g
g
g
g
g
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
REC
AM
THU
TUE
:
:
L
R
LEVEL
b
b
b
b
b
b
b
SP
a
a
a
a
a
a
a
EP
Corresponding
digit pin
→
→
→
→
→
→
→
→
→
→
P31
P30
P17
P16
P15
P14
P13
P12
P11
P10
→
→
→
→
→
→
→
→
→
→
P31
P30
P17
P16
P15
P14
P13
P12
P11
P10
: Unused
(The automatic display is not performed because FLD controller is not used.)
2-118
f g b
AM
PM
e
CH
P10
Table 2.4.5 FLD automatic display RAM map example
CH
SAT
FRI
WED
MON
SUN
–
■
a
P11
Fig. 2.4.30 FLD digit allocation example
Address
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
P31
TUE WEDTHU FRI SAT
L
R
LEVEL
P30
38B7 Group User’s Manual
c
d
APPLICATION
2.4 FLD controller
Control procedure:
●X : This bit is not used for this application.
Set “0” or “1” to this bit arbitrarily.
RESET
Initialization
.....
P4D (address 000916), bit 4–bit 7
FLDM (address 0EF416)
FLDCON (address 0EFC16)
IREQ1 (address 003C16), bit 5
00002
1XXXXX002
XXX0XXXX2
0
Port direction registers setting
1
0
Timer 1 interrupt: Enabled
Timer 1 count start
.....
Timer 1 interrupt request bit cleared
Wait until completion of writing to timer 1 interrupt request bit
ICON1 (address 003E16), bit 5
T12M (address 002816), bit 0
.....
~
~
Timer 1 interrupt routine
Segment key-scan
Push registers to stack, etc.
.....
P0 (address 000016), bit 0, bit 1
P1 (address 000216)
P2 (address 000416)
P3 (address 000616), bit 0, bit 1
FLD display turned off
002
0016
0016
002
All column display is completed ?
Y
Set data table for key-scan to P2 (address 000416)
N
P0 (address 000016), bit 0, bit 1
P2 (address 000416)
Segment
data
P1 (address 000216)
P3 (address 000616), bit 0, bit 1
Digit data
Wait until “H” level output of P2
is stabilized.
Wait for key-scan
Transfer the contents of P44 to P47
(address 000816) to RAM
~
~
Keys read-in
(Set the port P4 direction register (P4D) (address
000916) to the input mode on initialization, etc.)
Update the data table pointer for key-scan
N
Key-scan is completed ?
Y
R TI
Fig. 2.4.31 Control procedure
38B7 Group User’s Manual
2-119
APPLICATION
2.4 FLD controller
(4) Display by combination with digit expander (M35501FP*) (basic combination example)
* For M35501FP, refer to section “3.9 M35501FP”.
Outline: The fluorescent display which has many display numbers (36 segments ✕ 16 digits) is
displayed by using the digit expander (M35501FP).
38B7 Group
M35501FP
P50
RESET
SEL
P51
P73
CLK
P20–P27
P00–P07
P10–P17
P30–P37
P40–P43
OVFIN
DIG0–DIG15
Digit (16)
REC
SLEEP
DISC
TRACK
Fluorescent display (FLD)
DATE
CLOCK
Y
M
D
h
m
s
Segment (36)
1
2
3
4 5
6
7 8
9
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
REC
Fig. 2.4.32 Connection diagram
Specifications: •Use of M35501FP (M35501FP: 16 digits, 38B7 Group: 36
segments)
_____________
Ports P5 0 and P51 of 38B7 Group supply signals to the RESET and SEL pins of
M35501FP respectively.
The P73 pin (dimmer output pin) supply signals to the CLK pin of M35501FP.
•Use of FLD automatic display mode of 38B7 Group
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, f(XIN) = 4 MHz
Figure 2.4.33 shows the timing chart of 38B7 Group and M35501FP, and Figure 2.4.34 shows the
timing chart (enlarged view) of digit and segment output.
2-120
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
DIG2
DIG3
•••
•••
DIG12
DIG13
DIG14
DIG15
38B7 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P40–P43)
Fig. 2.4.33 Timing chart of 38B7 Group and M35501FP
M35501FP
CLK
Tdisp
DIG0
DIG1
Toff1
DIG2
•••
Toff2
DIG15
38B7 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P40–P43)
•••
Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output
38B7 Group User’s Manual
2-121
APPLICATION
2.4 FLD controller
Figure 2.4.35 shows the setting of relevant registers.
Port P0 digit output set switch register (address 0EF216)
P0DOR
0 0 0 0 0 0 0 0
Set P00–P07 to FLD output ports (FLD8–FLD15)
Port P2 digit output set switch register (address 0EF316)
P2DOR
0 0 0 0 0 0 0 0
Set P20–P27 to FLD output ports (FLD0–FLD7)
Port P4FLD/port switch register (address 0EF916)
P4FPR
1 0 0 0 1 1 1 1
Set P40–P43 to FLD output ports (FLD32–FLD35)
Set P44–P46 to general-purpose I/O ports
Set P47 to FLD output port (FLD39)
Port P5 direction register (address 000B16)
P5D
0 0 0 0 0 0 1 1
Set P50 to output port (for M35501 RESET signal)
Set P51 to output port (for M35501 SEL signal)
Port P5 (address 000A16)
P5
0 0 0 0 0 0 0 0
M35501 RESET signal output (Note 1)
M35501 SEL signal “L” output
Note 1: After retain RESET signal output “L” for 2 µs or more, release reset by outputting “H” level
from RESET signal output at CLK signal = “L” .
Fig. 2.4.35 Setting of relevant registers
2-122
38B7 Group User’s Manual
APPLICATION
2.4 FLD controller
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 0 1
Automatic display mode
Display stopped
FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
FLD output control register (address 0EFC16)
FLDCON
1
P73 as dimmer output
Tdisp time set register (address 0EF516)
TDISP
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
3216
Toff1 time set register (address 0EF616)
TOFF1
10 (0A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
0A16
Toff2 time set register (address 0EF716) (Note 2)
TOFF2
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note 2: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1
1 1 1
Set {(digit number) – 1} = 15
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 1 1
Display start
38B7 Group User’s Manual
2-123
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.6 FLD automatic display RAM map
1 to 16 timing display data stored area
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0E9016
1
FLD35 FLD34 FLD33 FLD32
0E9116
1
0E9216
1
0E9316
1
0E9416
1
0E9516
1
0E9616
1
0E9716
1
0E9816
1
0E9916
1
0E9A16
1
1
0E9B16
0E9C16
1
0E9D16
1
1
0E9E16
0E9F16
1
0EA016 FLD31 FLD30 FLD29 FLD28 FLD27 FLD26 FLD25 FLD24
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016 FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016 FLD15 FLD14 FLD13 FLD12 FLD11 FLD10 FLD9 FLD8
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
Gradation display control data stored area
Address
0E2016
0E2116
0E2216
0E2316
0E2416
0E2516
0E2616
0E2716
0E2816
0E2916
0E2A16
0E2B16
0E2C16
0E2D16
0E2E16
0E2F16
0E3016
0E3116
0E3216
0E3316
0E3416
0E3516
0E3616
0E3716
0E3816
0E3916
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016
0E4116
0E4216
0E4316
0E4416
0E4516
0E4616
0E4716
0E4816
0E4916
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
0E6A16
0E6B16
0E6C16
0E6D16
0E6E16
0E6F16
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
FLD35 FLD34 FLD33 FLD32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FLD31 FLD30 FLD29 FLD28 FLD27 FLD26 FLD25 FLD24
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD15 FLD14 FLD13 FLD12 FLD11 FLD10 FLD9 FLD8
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
: CLK signal set area to M35501FP
: Unused
2-124
38B7 Group User’s Manual
Corresponding digit
pin of M35501FP
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
APPLICATION
2.4 FLD controller
DIG0
DIG1 DIG2 DIG3
DIG4 DIG5 DIG6 DIG7
DIG8 DIG9 DIG10 DIG11
FLD2 6
FLD0
FLD1
FLD2
FLD2 7
FLD2 0 FLD2 2 FLD1 8
FLD5
FLD6
FLD7 FLD8
FLD9
1
2
REC
SLEEP
3 4
5
6
FLD15 FLD16 FLD17FLD1 8 FLD1 9
DATE
CLOCK
7 8
Y
D
FLD21 FLD23 FLD19
FLD17
FLD1 2 FLD1 4
FLD2
FLD8
FLD20 FLD21FLD2 2 FLD2 3FLD2 4
FLD6
FLD4
FLD2 5
FLD1 3 FLD1 5
FLD1 0
FLD3 FLD7
FLD9
FLD5
FLD0
FLD1 1
FLD2 9
FLD1
FLD25 FLD26FLD2 7 FLD2 8 FLD2 9
9
10 11 12 13 14 15 16 17 18
M
FLD2 4
FLD1 6
FLD10 FLD11 FLD12 FLD1 3FLD1 4
DISC
TRACK
FLD2 8
FLD3 FLD4
h
m
DIG13
s
FLD30 FLD31FLD3 2 FLD3 3 FLD3 4
DIG14
FLD3 0
FLD3 1 FLD3 2
FLD3 3 FLD34
FLDE
35C
R
FLD3 5
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
RE C
DIG12
DIG15
LD
F LD
LD
F LD
F LD
F LD
10 FLD
21 FLD
32 F4
54 F6
7
8
98
3
5
6
7
FLD
FLD
FLD
D
10
1FL2D 1FL3
1FL4D 1FL5D 1FL6D 1FL7D 1FL8D
9 11
10 11 12 13 14 15 16 17
FLD
FLD
F LD
19
20
21 2FL2D 2FL3D 2FL4D 2FL5D 2FL6D 2FL7D
18 19 20 21 22 23 24 25 26
FLD
FLD
FLD
F LD
F LD
F LD
F LD
F LD
F LD
28
6
27 29
28 30
29 331
0 332
1 333
2 3
34
3 3
35
4 3
35
Fig. 2.4.36 FLD digit allocation example
Control procedure:
Figure 2.4.37 shows the control procedure.
●X: This bit is not used for this application.
RESET
Set “0” or “1” to this bit arbitrarily.
Initialization
••
P0DOR (address 0EF216)
P2DOR (address 0EF316)
P4FPR (address 0EF916)
FLDM (address 0EF416)
FLDCON (address 0EFC16)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
P5D (address 000B16)
P5 (address 000A16)
000000002
000000002
100011112
101000012
XXX1XXXX2
3216
0A16
1016 (Note 1)
000011112
000000112
000000002
FLD port setting
Supplying CLK to M35501FP
FLD automatic display function setting
000000012
FLD automatic display RAM
(address 0E9016–0EDF16)
Data to be
display
Setting of CLK data to M35501FP and
segment data (Note 3)
Gradation
display control
data (Note 1)
Gradation display control data setting
Set “1” for dark display
Set “0” for bright display (Note 3)
••
P5 (address 000A16)
Port direction registers setting
RESET to M35501FP = “L”,
SEL = “L” signal output set
RESET of M35501FP released (Note 2)
Gradation display control
RAM
(addresses 0E2016–0E6F16)
FLDM (address 0EF416), bit 1
1
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these registers, too.
2: After retaining RESET signal output “L” for 2 µs or more,
release reset while CLK signal is “L”.
3: The display data can be rewritten at arbitrary timing.
Fig. 2.4.37 Control procedure
38B7 Group User’s Manual
2-125
APPLICATION
2.4 FLD controller
(5) Display by combination with digit expander (M35501FP*) (example considering column discrepancy
prevention)
* For M35501FP, refer to section “3.9 M35501FP”.
Outline: In the case of (4), which is displayed by using the digit expander (M35501FP), if a noise
enters signals between 38B7 Group and M35501FP, a column discrepancy of display may
occur. Prevent the column discrepancy by using the OVFOUT output of M35501FP.
The OVF OUT pin of M35501FP outputs an overflow signal. The overflow signal is the
signal which outputs “H” synchronizing to the last digit output signal of M35501FP, and
the signal is output at definite intervals in the correct state. Incorrect state is detected by
measuring the output period of this signal, and a column discrepancy is prevented.
38B7 Group
M35501FP
P50
P51
RESET
SEL
P73
CLK
OVFOUT
CNTR1
P20–P27
P00–P07
P10–P17
P30–P37
P40–P43
OVFIN
DIG0–DIG15
Digit (16)
REC
SLEEP
DISC
TRACK
Fluorescent display (FLD)
DATE
CLOCK
Y
M
D
Segment (36)
1
2
3
4 5
6
7 8
9
h
m
s
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
REC
Fig. 2.4.38 Connection diagram
Specifications: •Use of M35501FP (M35501: 16 digits, 38B7 Group: 36 segments)
_____________
Ports P5 0 and P5 1 of 38B7 Group supply signal to the RESET and SEL pins of
M35501FP respectively.
The P73 pin (dimmer output pin) supply signals to the CLK pin of M35501FP.
•Use of FLD automatic display mode of 38B7 Group
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, f(XIN ) = 4 MHz
Countermeasures against
→ •OVFOUT output of M35501FP input to CNTR1 pin of 38B7 Group
column discrepancycolumn
Input signal to CNTR1 pin is counted as a count source by timer
discrepancy
4 of 38B7 Group
The timer 6 interrupt is generated each time FLD display period
(Tdisp (204 µs) ✕ 16 column = 3.264 ms), and a value of timer
4 is confirmed. M35501FP is reset at incorrect state.
Figure 2.4.39 shows the timing chart (at correct state) of 38B7 Group and M35501FP, and Figure
2.4.40 shows the timing chart (at incorrect state) of 38B7 Group and M35501FP.
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APPLICATION
2.4 FLD controller
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
•••
•••
DIG14
DIG15
38B7 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P40–P43)
Fig. 2.4.39 Timing chart (at correct state) of 38B7 Group and M35501FP
M35501FP
RESET
SEL
OVFIN
Noise
OVFOUT
CLK
DIG0
DIG1
•••
•••
DIG14
DIG15
38B7 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P40–P43)
Column discrepancy occur
Fig. 2.4.40 Timing chart (at incorrect state) of 38B7 Group and M35501FP
38B7 Group User’s Manual
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APPLICATION
2.4 FLD controller
Figure 2.4.41 shows the setting of relevant registers.
Port P0 digit output set switch register (address 0EF216)
P0DOR
0 0 0 0 0 0 0 0
Set P00–P07 to FLD output ports (FLD8–FLD15)
Port P2 digit output set switch register (address 0EF316)
P2DOR
0 0 0 0 0 0 0 0
Set P20–P27 to FLD output ports (FLD0–FLD7)
Port P4FLD/port switch register (address 0EF916)
P4FPR
1 0 0 0 1 1 1 1
Set P40–P43 to FLD output ports (FLD32–FLD35)
Set P44–P46 to general-purpose I/O ports
Set P47 to FLD output port (FLD39)
Port P5 direction register (address 000B16)
P5D
1 1
Set P50 to general-purpose output port (for M35501 RESET signal)
Set P51 to general-purpose output port (for M35501 SEL signal)
Port P5 (address 000A16)
P5
0 0
M35501 RESET signal output (Note 1)
M35501 SEL signal “L” output
Note 1: After retain RESET signal output “L” for 2 µs or more, release reset by
outputting “H” level from RESET signal output at CLK signal = “L” .
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 0 1
Automatic display mode
Display stopped
FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
FLD output control register (address 0EFC16)
FLDCON
1
P73 as dimmer output
Tdisp time set register (address 0EF516)
TDISP
3216
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Toff1 time set register (address 0EF616)
TOFF1
0A16
10 (0A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Toff2 time set register (address 0EF716) (Note 2)
TOFF2
1016
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Note 2: Perform this setting when the gradation display mode is selected.
Fig. 2.4.41 Setting of relevant registers
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APPLICATION
2.4 FLD controller
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1 1 1 1
Set {(digit number) – 1} = 15
Interrupt edge selection register (address 003A16)
INTEDGE 0
CNTR1 pin rising edge active
Timer 34 mode register (address 002916)
T34M 0
1 0
1
Timer 4 count stop, count start at FLD display started
Timer 4 count source: External count input CNTR1
Timer 4 (address 002316)
T4
Check value of T4 each time timer 6 interrupt occurrence
When the value is FE16, it is judged as correct state
FF16
Timer 56 mode register (address 002A16)
T56M 0 0 0 1 0 0 1 1
Timer 5 count stop, count start at FLD display started
Timer 6 count stop, count start at FLD display started
Timer 5 count source: f(XIN)/8
Timer 6: Timer mode
Timer 6 count source: Timer 5 underflow
P74 as I/O port
Timer 5 (address 002416)
T5
0716
Timer 6 interrupt occurs at 3.264 ms intervals
Timer 6 (address 002516)
T6
CB16
Interrupt request register 2 (address 003D16)
IREQ2
0
Clear timer 6 interrupt request
Interrupt control register 2 (address 003F16)
ICON2 0
1
Timer 6 interrupt enabled
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 1 1
Display start
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APPLICATION
2.4 FLD controller
Control procedure:
Figure 2.4.42 shows the control procedure.
●X: This bit is not used for this application.
Set “0” or “1” to this bit arbitrarily.
RESET
Initialization
•••
P0DOR (address 0EF216)
P2DOR (address 0EF316)
P4FPR (address 0EF916)
FLDM (address 0EF416)
FLDCON (address 0EFC16)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
P5D (address 000B16)
P5 (address 000A16)
T34M (address 002916)
INTEDGE (address 003A16), bit 7
T4 (address 002316)
T56M (address 002A16)
T5 (address 002416)
T6 (address 002516)
P5 (address 000A16)
000000002
000000002
100011112
101000012
XXX1XXXX2
3216
0A16
1016 (Note 1)
000011112
XXXXXX112
XXXXXX002
0X10XX1X2
0
FF16
000100112
0716
CB16
XXXXXX012
FLD port setting
Supplying CLK to M35501FP
FLD automatic display function setting
Port direction register setting
RESET to M35501FP = “L”, SEL = “L” signal output setting
Timer 4 setting
Timer 5, timer 6 setting
RESET of M35501FP released (Note 2)
•••
FLD automatic display RAM
(addresses 0E9016–0EDF16)
Data to be
display
Gradation display control
RAM
(addresses 0E2016–0E6F16)
Gradation
display control
data (Note 1)
IREQ2 (address 003D16), bit 2
ICON2 (address 003F16), bit 2
T34M (address 002916), bit 0
T56M (address 002A16), bit 0, 1
FLDM (address 0EF416), bit 1
0
1
0
002
1
Setting of CLK data to M35501FP and
segment data (Note 3)
Setting of gradation display control data
Set “1” for dark display
Set “0” for bright display (Note 3)
Timer 6 interrupt request bit cleared
Timer 6 interrupt enabled
Timer 4, timer 5, timer 6 count start (Note 4)
FLD automatic display start (Note 4)
Main processing
Fig. 2.4.42 Control procedure
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APPLICATION
2.4 FLD controller
Interrupt occurs each time FLD display cycle = 3.264 ms
Timer 6 interrupt routine
Push registers to stack, etc.
Correct
data (FE16)
Check timer 4 data ?
Check of OVFOUT output number during FLD display cycle
Only 1 time (=FE16) is correct.
Incorrect data (except FE16)
Error processing
FLDM (address 0EF416), bit 1
0
Transfer present display contents to work RAM
P5 (address 000A16)
Display data is retained as backup.
XXXXXX002
Setting of RESET to M35501FP = “L”,
SEL = “L” signal output
XXXXXX012
Releasing RESET of M35501FP (Note 2)
••
P5 (address 000A16)
FLD turned off
FLD automatic display RAM
(addresses 0E9016–0EDF16)
Data to be
display
Setting of CLK data to M35501FP
Setting of segment data by display data
of backup
(Note 5)
Gradation display control
RAM
(addresses 0E2016–0E6F16)
Gradation
display control
data (Note 1)
T56M (address 002A16), bit 0, 1
FLDM (address 0EF416), bit 1
T4 (address 002316)
FF16
002
1
Setting of gradation display control data
Set “1” for dark display
Set “0” for bright display
Timer 5, timer 6 count start (Note 4)
FLD turned on, automatic display start (Note 4)
Setting of timer 4 again
••
Pop registers
R TI
Notes 1: When selecting the gradation display, set these registers,
too.
2: After retaining RESET signal output “L” for 2 µs or more,
release reset while CLK signal is “L”.
3: The display data can be rewritten at arbitrary timing.
4: Synchronize count start timing of timer 5 and timer 6 with
FLD automatic display start timing as possible.
5: Set segment data of M35501FP at reset and others
according to necessity.
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APPLICATION
2.4 FLD controller
2.4.4 Notes on FLD controller
● Set a value of 0316 or more to the Toff1 time set register.
● When displaying in the gradation display mode, select the 16 timing mode by the timing number control
bit (bit 4 of FLDC mode register (address 0EF4 16 ) = “0”).
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APPLICATION
2.5 A-D converter
2.5 A-D converter
This paragraph describes the setting method of A-D converter relevant registers, notes etc.
2.5.1 Memory assignment
Address
003216
AD/DA control register (ADCON)
003316 A-D conversion register (low-order) (ADL)
003416 A-D conversion register (high-order) (ADH)
003916
Interrupt source switch register (IFR)
003D16
Interrupt request register 2 (IREQ2)
003E16
(Interrupt control register 1 (ICON1))
003F16
Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory assignment of A-D converter relevant registers
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APPLICATION
2.5 A-D converter
2.5.2 Relevant registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
3
Functions
b3 b2 b1 b0
0 0 0 0: PA0/AN0
0 0 0 1: PA1/AN1
0 0 1 0: PA2/AN2
0 0 1 1: PA3/AN3
0 1 0 0: PA4/AN4
0 1 0 1: PA5/AN5
0 1 1 0: PA6/AN6
0 1 1 1: PA7/AN7
1 0 0 0: P90/SIN3/AN8
1 0 0 1: P91/SOUT3/AN9
1 0 1 0: P92/SCLK3/AN10
1 0 1 1: P93/SRDY3/AN11
1 1 0 0: P94/RTP1/AN12
1 1 0 1: P95/RTP0/AN13
1 1 1 0: P96/PWM0/AN14
1 1 1 1: P97/BUZ02/AN15
0
0
0
0
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
1
0: DA output disabled
6 DA output enable
bit
1: DA output enabled
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
Fig. 2.5.2 Structure of AD/DA control register
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At reset R W
38B7 Group User’s Manual
0
0
APPLICATION
2.5 A-D converter
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
0
1
2
3
4
5
6
7
Functions
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
Undefined
Note: Do not read this register during A-D conversion.
Fig. 2.5.3 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
Functions
0 This is A-D conversion result (high-order 8 bits) stored
1 bits. This is read exclusive register.
2
3
4
5
6
7
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 2.5.4 Structure of A-D conversion register (high-order)
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APPLICATION
2.5 A-D converter
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916)
b
Name
Functions
At reset R W
0
0 INT3/serial I/O2
transmit interrupt
switch bit
0: INT3 intrrupt
1: Serial I/O2 transmit
interrupt
0: INT4 interrupt
1 INT4/A-D
conversion interrupt 1: A-D conversion intrerrupt
switch bit
0: INT1 intrrupt
2 INT1/serial I/O3
interrupt switch bit 1: Serial I/O3 interrupt
3 Nothing is arranged for these bits. These are write
4 disabled bits. When these bits are read out, the
contents are “0”.
5
6
7
0
0
0
0
0
0
0
Fig. 2.5.5 Structure of Interrupt source switch register
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
Timer
6
interrupt
0 : No interrupt request issued
2
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.5.6 Structure of Interrupt request register 2
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0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
APPLICATION
2.5 A-D converter
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit
1 Timer 5 interrupt
enable bit
2 Timer 6 interrupt
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/Serial I/O2
transmit interrupt
enable bit
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
At reset R W
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Fig. 2.5.7 Structure of Interrupt control register 2
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APPLICATION
2.5 A-D converter
2.5.3 A-D converter application examples
(1) Read-in of analog signal
Outline: The analog input voltage input from a sensor is converted to digital values.
Figure 2.5.8 shows a connection diagram, and Figure 2.5.9 shows the setting of relevant registers.
Sensor
PA0/AN0
38B7 Group
Fig. 2.5.8 Connection diagram
Specifications: •Conversion of analog input voltage input from sensor to digital values
•Use of PA 0/AN0 pin as analog input pin
AD/DA control register (address 003216)
0 0 0 0 0
ADCON
Analog input pin : PA0/AN0 selected
A-D conversion start
A-D conversion register (low-order) (address 003316)
b7
b0
(Read-only)
A DL
A result of A-D conversion is stored (Note).
A-D conversion register (high-order) (address 003416)
b7
b0
ADH
(Read-only)
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out both registers in order of ADH (address
003416) and ADL (address 003316) following.
Fig. 2.5.9 Setting of relevant registers
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APPLICATION
2.5 A-D converter
Control procedure: A-D converter is started by performing register setting shown Figure 2.5.9.
Figure 2.5.10 shows the control procedure.
~
~
ADCON (address 003216), bit 0–bit 3 ← 00002
←0
ADCON (address 003216), bit 4
• PA0/AN0 pin selected as analog input pin
• A-D conversion start
0
ADCON (address 003216), bit 4 ?
• Judgment of A-D conversion completion
1
Read out ADH (address 003416)
• Read out of high-order (b9–b2) conversion result
Read out ADL (address 003316)
• Read out of low-order (b1, b0) conversion result
~
~
Fig. 2.5.10 Control procedure
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APPLICATION
2.5 A-D converter
2.5.4 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the V SS line
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN ) is 250 kHz or more
• Do not execute the STP instruction and WIT instruction
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APPLICATION
2.6 D-A converter
2.6 D-A converter
This paragraph describes the setting method of D-A converter relevant registers, notes etc.
2.6.1 Memory assignment
Address
002B16
D-A conversion register (DA)
003216
AD/DA control register (ADCON)
Fig. 2.6.1 Memory assignment of D-A converter relevant registers
2.6.2 Relevant registers
D-A conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-A conversion register
(DA: address 2B16)
b
Functions
At reset R W
0 •This is a register for set of D-A conversion
output value.
1 • D-A conversion is performed automatically by
setting a value in this register.
2
0
3
0
4
0
5
0
6
0
7
0
0
0
Fig. 2.6.2 Structure of D-A conversion register
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APPLICATION
2.6 D-A converter
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
3
Functions
b3 b2 b1 b0
0 0 0 0: PA0/AN0
0 0 0 1: PA1/AN1
0 0 1 0: PA2/AN2
0 0 1 1: PA3/AN3
0 1 0 0: PA4/AN4
0 1 0 1: PA5/AN5
0 1 1 0: PA6/AN6
0 1 1 1: PA7/AN7
1 0 0 0: P90/SIN3/AN8
1 0 0 1: P91/SOUT3/AN9
1 0 1 0: P92/SCLK3/AN10
1 0 1 1: P93/SRDY3/AN11
1 1 0 0: P94/RTP1/AN12
1 1 0 1: P95/RTP0/AN13
1 1 1 0: P96/PWM0/AN14
1 1 1 1: P97/BUZ02/AN15
0
0
0
0
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
1
0: DA output disabled
6 DA output enable
bit
1: DA output enabled
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
Fig. 2.6.3 Structure of AD/DA control register
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At reset R W
38B7 Group User’s Manual
0
0
APPLICATION
2.6 D-A converter
2.6.3 D-A converter application examples
Outline: Digital value is converted to the analog output voltage.
Figure 2.6.4 shows a connection diagram, and Figure 2.6.5 shows the setting of relevant registers.
Electric
volume
PB0/DA
38B7 Group
Fig. 2.6.4 Connection diagram
Specifications: •Conversion of digital value to analog output voltage.
AD/DA control register (address 3216)
b7
b0
0
ADCON
DA output disabled
D-A conversion register (address 2B16)
b7
b0
DA
Output value “n” of D-A conversion (Note).
Note: The output analog voltage V is determined by the value n (decimal
notation) as follows:
V = VREF ✕ n / 256 (n = 0 to 255)
VREF: Reference voltage
Fig. 2.6.5 Setting of relevant registers
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APPLICATION
2.6 D-A converter
Control procedure: D-A converter is started by performing register setting shown Figure 2.6.5.
Figure 2.6.6 shows the control procedure.
~
~
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
ADCON (address 3216) ← X0XXXXXX2
• D-A output disabled
DA (address 2B16)
• D-A conversion started by writing data into D-A
conversion register
ADCON (address 3216) ← X1XXXXXX2
• D-A output enabled
ADCON (address 3216) ← X0XXXXXX2
• D-A output disabled
~
~
Fig. 2.6.6 Control procedure
2.6.4 Notes on D-A converter
(1) PB 0/DA pin state at reset
The PB0/DA pin becomes a high-impedance state at reset.
(2) Connection with low-impedance load
If connecting a D-A output with a load having a low impedance, use an external buffer. It is because
the D-A converter circuit does not include a buffer.
(3) Usable voltage
Vcc must be 3.0 V or more when using the D-A converter.
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APPLICATION
2.7 PWM
2.7 PWM
This paragraph describes the setting method of PWM relevant registers, notes etc.
2.7.1 Memory assignment
Address
002616
PWM control register (PWMCON)
003516
PWM register (high-order) (PWMH)
003616
PWM register (low-order) (PWML)
Fig. 2.7.1 Memory assignment of PWM relevant registers
2.7.2 Relevant registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register
(PWMCON: address 2616)
b
Name
Functions
0: I/O port
0 P96/PWM0 output
selection bit
1: PWM0 output
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read out,
3 the contents are “0”.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.7.2 Structure of PWM control register
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APPLICATION
2.7 PWM
PWM register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (high-order)
(PWMH: address 3516)
b
Functions
At reset R W
0 • High-order 8 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch each sub-period cycle (64 µs).
(At f(XIN) = 4 MHz)
2
• When this register is read out, the value of the
3
PWM register (high-order) is read out.
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Fig. 2.7.3 Structure of PWM register (high-order)
PWM register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (low-order)
(PWML: address 3616)
b
Functions
0 • Low-order 6 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch at each PWM cycle period
(4096 µs).
2
(At f(XIN) = 4 MHz)
3 • When this register is read out, the value of the
PWM latch (low-order 6 bits) is read out.
4
Undefined
5
Undefined
6 Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “0”.
7 • This bit indicates whether the transfer to the
PWM latch is completed.
0: Transfer is completed
1: Transfer is not completed
• This bit is set to “1” at writing.
Fig. 2.7.4 Structure of PWM register (low-order)
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Undefined
Undefined
Undefined
Undefined
Undefined
✕
Undefined
✕
APPLICATION
2.7 PWM
2.7.3 PWM application example
(1) Control of VS tuner
Figure 2.7.5 shows a connection diagram, and Figure 2.7.6 shows the setting of relevant registers.
VS tuner
A NT
P96/PWM0/AN14
Filter
0 to 32 V
VT
38B7 Group
Fig. 2.7.5 Connection diagram
Outline: • Control of VS tuner by using the 14-bit resolution PWM 0 output function
• f(X IN) = 4 MHz
PWM control register (address 002616)
PWMCON
1
Select PWM output
Note: The PWM output function has priority even when the
bit corresponded to the P96 pin of the port P9 direction
register is set to the input mode.
PWM register (high-order) (address 003516)
PWMH
Set high-order 8 bits (N) of a 14-bit data to be output
Note: Depending on data (N) of the high-order 8 bits, the period
(250 ✕ N) of the “H” level during the sub period (64 µs) is
determined.
PWM register (low-order) (address 003616)
PWML
Set low-order 6 bits (m) of a 14-bit data to be output
Note: Depending on data (m) of the low-order 6 bits, the number of
sub period to which the ADD bit is to be added within the
repetitive cycle consisting of 64 sub periods is determined.
When output data is written to the PWM register (low-order),
bit 7 of this register becomes “1”. When completing to transfer
data from the PWM register (low-order) to the PWM latch, bit 7
becomes “0”.
Fig. 2.7.6 Setting of relevant registers
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APPLICATION
2.7 PWM
Control procedure: PWM waveform is output to the external by setting relevant registers shown in
Figure 2.7.6. This PWM 0 output is integrated through the low pass filter and
converted into DC signals for control of the VS tuner.
Figure 2.7.7 shows the control procedure.
~
~
PWMCON (address 002616), bit 0
PWMH (address 003516)
PWML (address 003616)
1
Data to be
output
The P96/PWM0/AN14 pin is set to the PWM
output pin.
After setting data, PWM waveform
corresponding to the new data is output from
the next repetitive cycle.
~
~
Fig. 2.7.7 Control procedure
2.7.4 Notes on PWM
● For PWM 0 output, “L” level is output first.
● After data is set to the PWM register (low-order) and the PWM register (high-order), PWM waveform
corresponding to new data is output from next repetitive cycle.
PWM0 output data
change
Modified data is output from next
repetitive cycle.
Fig. 2.7.8 PWM0 output
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APPLICATION
2.8 Interrupt interval determination function
2.8 Interrupt interval determination function
This paragraph describes the setting method of interrupt interval determination function relevant registers,
notes etc.
2.8.1 Memory assignment
Address
003016 Interrupt interval determination register (IID)
003116
Interrupt interval determination control register (IIDCON)
003A16 Interrupt edge selection register (INTEDGE)
003B16
(CPU mode register (CPUM))
003C16
Interrupt request register 1 (IREQ1)
003D16
003E16
(Interrupt request register 2 (IREQ2))
Interrupt control register 1 (ICON1)
Fig. 2.8.1 Memory assignment of interrupt interval determination function relevant registers
2.8.2 Relevant registers
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination register
(IID: address 3016)
b
Functions
0 • This register stores a value which is obtained
by counting a following interval with the
1
counter sampling clock.
2
Rising interval
3
Falling interval
Both edges interval (Note)
4
(Selected by interrupt edge selection register)
5
• Read exclusive register
6
7
At reset R W
0
0
0
0
0
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) of
the interrupt interval determination control register is “00”, the
both-sided edge detection function cannot be used.
Fig. 2.8.2 Structure of Interrupt interval determination register
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APPLICATION
2.8 Interrupt interval determination function
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination control register
(IIDCON: address 3116)
b
Name
Functions
At reset R W
0: Stopped
0 Interrupt interval
determination circuit 1: Operating
operating selection
bit
0
1 Counter sampling
clock selection bit
2 Noise filter
sampling clock
3 selection bits (INT2)
0: f(XIN)/128 or f(XCIN)
1: f(XIN)/256 or f(XCIN)/2
0
b3 b2
0
4 One-sided/bothsided edge
detection selection
bit
0 0: Filter is not used.
0 1: f(XIN)/32 or f(XCIN)
1 0: f(XIN)/64 or f(XCIN)/2
1 1: f(XIN)/128 or f(XCIN)/4
0: One-sided edge
detection
1: Both-sided edge
detection (Note)
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
0
0
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) is
“00”, the both-sided edge detection function cannot be used.
Fig. 2.8.3 Structure of Interrupt interval determination control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE : address 3A16)
b
0
1
2
3
4
5
6
7
Name
Functions
INT0 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
INT1 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
INT2 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
INT3 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
INT4 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
CNTR0 pin edge
0 : Rising edge count
switch bit
1 : Falling edge count
CNTR1 pin edge
0 : Rising edge count
1 : Falling edge count
switch bit
Fig. 2.8.4 Structure of Interrupt edge selection register
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At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.8 Interrupt interval determination function
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
0 INT0 interrupt
request bit
Functions
At reset R W
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1/serial I/O3
0 : No interrupt request
interrupt request bit
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.8.5 Structure of Interrupt request register 1
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APPLICATION
2.8 Interrupt interval determination function
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 INT0 interrupt
enable bit
1 INT1/serial I/O3
interrupt enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
4 Timer X interrupt
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
Fig. 2.8.6 Structure of Interrupt control register 1
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0
0
0
0
APPLICATION
2.8 Interrupt interval determination function
2.8.3 Interrupt interval determination function application examples
(1) Reception of remote-control signal
Outline: Remote-control signal is read in by both of the interrupt interval determination function using
a noise filter and a timer interrupt.
Receiver
unit
P72/INT2
Remote controller
38B7 Group
Fig. 2.8.7 Connection diagram
Specifications: • Measurement of one-sided edge interval
• Use of noise filter
• Check of remote control interrupt request within the timer 2 interrupt (488 µs
period) processing routine
• Operation at f(XIN ) = 4 MHz in high-speed mode
Figure 2.8.8 shows the function block diagram, and Figure 2.8.9 shows a timing chart of data
determination.
Microcomputer hardware
Receiver
unit
Microcomputer software
Noise filter
Interrupt interval
determination
register
• Noise elimination
• One-sided edge
detection
• One-sided edge
interval
judgment
Determination
of header or
0/1
Data
check
1-byte
reception
• Read out register
• Comparison of
read out value with
reference value
• Recognition bit
number of each
code
Fig. 2.8.8 Function block diagram
Input (INT2)
(Overflow)
Interrupt request
Timer 2 interrupt
(488 µs)
Interrupt interval
determination
register read-in
Data determination
Ignore
Header
0
1
•••
1-byte reception
1
Ignore Ignore
Check of excess bit
Fig. 2.8.9 Timing chart of data determination
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APPLICATION
2.8 Interrupt interval determination function
Figure 2.8.10 shows the setting of relevant registers.
CPU mode register (address 003B16)
CP UM
0
High-speed (f(XIN)) mode operation
Interrupt edge selection register (address 003A16)
INTEDGE
0
INT2 pin: Falling edge active
Interrupt interval determination control register (address 003116)
IIDCON
0 1 0 1 1
Interrupt interval determination circuit: Operating
Counter sampling clock: f(XIN)/256
Noise filter sampling clock: f(XIN)/64
One-sided edge detection
Interrupt request register 1 (address 003C16)
IREQ1
Determination of remote controller/counter overflow interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
0
Remote controller/counter overflow interrupt: Disabled
Interrupt interval determination register (address 003016)
IID
Determination of header/data (0/1) with this value
Fig. 2.8.10 Setting of relevant registers
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APPLICATION
2.8 Interrupt interval determination function
Control procedure: When the registers are set as shown in Figure 2.8.10, remote-control signals
are receivable. Figure 2.8.11 shows the control procedure, and Figure 2.8.12
shows the reception of remote-control data (timer 2 interrupt).
●X: This bit is not used here. Set it to “0” or “1”
arbitrarily.
RESET
Initialization
SEI
.....
CPUM (address 003B16), bit 6
0
.....
INTEDGE (address 003A16), bit 2
IIDCON (address 003116)
IREQ1 (address 003C16), bit 2
NOP
ICON1 (address 003E16), bit 2
0
XXX010112
0
0
.....
CLI
~
~
Fig. 2.8.11 Control procedure
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APPLICATION
2.8 Interrupt interval determination function
Timer 2 interrupt
Push registers to stack etc.
Input edge ?
(IREQ1, bit 2 = ?)
N
Y
During checking excess
bit ?
Clear edge (IREQ1, bit 2 = 0)
N
Y
Y
Number of bits error
(Excess bit is found)
Excess bit
determined counter
over ?
Y
During checking
excess bit ?
N
Read IID (address 003016)
Fixed data
R TI
Y
Time error
R TI
R TI
IID (address 003016)
= FF16 ?
N
In range of header ?
Y
Start receiving data etc.
N
RTI
Out of range of 0 or 1
In range of data, 0 or 1 ?
In range of 0
In range of 1
Time error
R TI
CY ← 0
CY ← 1
Shift reception data
Complete to
receive ?
N
Y
Start checking excess bit
RTI
Fig. 2.8.12 Reception of remote-control data (timer 2 interrupt)
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N
APPLICATION
2.9 Watchdog timer
2.9 Watchdog timer
This paragraph describes the setting method of watchdog timer relevant register, notes etc.
2.9.1 Memory assignment
Address
003B16
CPU mode register (CPUM)
0EEE16
Watchdog timer contort register (WDTCON)
Fig. 2.9.1 Memory assignment of watchdog timer relevant register
2.9.2 Relevant register
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 0EEE16)
b
Name
Functions
0 Watchdog timer H
1 (high-order 6 bits of reading exclusive)
2
3
4
5
6 STP instruction
0: STP instruction enabled
disable bit
1: STP instruction disabled
7 Watchdog timer H
0: Watchdog timer L
count source
underflow
selection bit
1: f(XIN)/8 or f(XCIN)/16
At reset R W
1
1
1
1
1
1
0
0
Fig. 2.9.2 Structure of Watchdog timer control register
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APPLICATION
2.9 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
4 Port Xc switch bit
5 Main clock (XINXOUT) stop bit
Main
clock division
6
ratio selection bit
7 Internal system
clock selection bit
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
0
0
0
1
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
1: Stopped
0
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
1
Fig. 2.9.3 Structure of CPU mode register
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0
0
APPLICATION
2.9 Watchdog timer
2.9.3 Watchdog timer application examples
Outline: When a program runs away, the watchdog timer makes the microcomputer return to the
reset state.
Specifications: •When the watchdog timer H underflows, it is judged as incorrect program, and the
microcomputer is returned to the reset state.
•Bit 7 of the watchdog timer control register is set to “0” at each cycle of the main
routine before underflow of the watchdog timer H. (Initialization of watchdog timer
value)
•Use of watchdog timer L underflow as count source of watchdog timer H
•Setting of main clock division ratio to f(XIN) (high-speed mode)
Figure 2.9.4 shows the connection of watchdog timer and the setting of the division ratio.
Figure 2.9.5 shows the setting of relevant registers and Figure 2.9.6 shows the control procedure.
Watchdog timer L
Fixed
f(XIN) = 4 MHz
1/8
1/256
Watchdog timer H
1/256
Reset
circuit
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.9.4 Connection of watchdog timer and setting of division ratio
CPU mode register (address 3B16)
b7
CP UM
0 0 0
b0
1
0 0
Single-chip mode
Main clock (XIN-XOUT): Oscillating
High-speed (f(XIN)) mode operation
Internal system clock: XIN-XOUT
Watchdog timer control register (address 0EEE16)
b7
WDTCON
b0
0 0
Wachdog timer H: High-order 6 bits of reading exclusive
STP instruction: Enabled
Watchdog timer H count source:
Underflow of watchdog timer L
Fig. 2.9.5 Setting of relevant registers
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APPLICATION
2.9 Watchdog timer
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
CLT
CLD
CPUM (address 3B16)
•All interrupts disabled
000X1X002
••••
•Interrupts enabled
CLI
WDTCON (address 0EEE16), bit7, bit6
•CPU mode register setting
(single-chip mode, main clock oscillating, high-speed mode)
002
•WDT L underflow as WDT H count source
•STP instruction enabled
Main processing
Fig. 2.9.6 Control procedure
2.9.4 Notes on watchdog timer
● The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that
watchdog timer does not underflow during this term by writing to the watchdog timer control register
(address 0EEE 16 ) once before executing the STP instruction, etc.
● Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register
(address 0EEE 16), it cannot be programmed to “0” again. This bit becomes “0” after reset.
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APPLICATION
2.10 Buzzer output circuit
2.10 Buzzer output circuit
The output frequency can be selected from 1 kHz, 2 kHz, or 4 kHz (at f(XIN) = 4.19 MHz), and the output
port can be selected between either the B UZ01 pin or the B UZ02 pin.
This paragraph describes the setting method of buzzer output circuit relevant register, notes etc.
2.10.1 Memory assignment
Address
0EFD16
Buzzer output control register (BUZCON)
Fig. 2.10.1 Memory assignment of buzzer output circuit relevant register
2.10.2 Relevant register
The buzzer output circuit starts outputting a buzzer by setting the buzzer output ON/OFF bit (bit 4) of the
buzzer output control register.
Figure 2.10.2 shows the structure of the buzzer output control register.
Buzzer output control register
b7 b6 b5 b4 b3 b2 b1 b0
Buzzer output control register
(BUZCON: address 0EFD16)
b
Name
0 Output frequency
selection bits
1
2 Output port
selection bits
3
Functions
At reset R W
b1b0
0
0 0: 1 kHz (f(XIN)/4096)
0 1: 2 kHz (f(XIN)/2048)
1 0: 4 kHz (f(XIN)/1024)
1 1: Not available
0
b3b2
0
0 0: P77 and P97 function
as ordinary ports.
0 1: P77/BUZ01 functions as
a buzzer output.
1 0: P97/BUZ02/AN15
functions as a buzzer
output.
1 1: Not available
4 Buzzer output
ON/OFF bit
0: Buzzer output OFF (“0”
output)
1: Buzzer output ON
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
0
0
0
0
0
Fig. 2.10.2 Structure of buzzer output control register
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APPLICATION
2.10 Buzzer output circuit
2.10.3 Buzzer output circuit application examples
Outline: A buzzer output is performed by using the buzzer output circuit.
Specifications: •f(XIN ) = 4.19 MHz, buzzer output frequency = 4 kHz
•Buzzer output from B UZ01 pin
Figure 2.10.3 shows the connection of buzzer output circuit and the setting of the division ratio.
Figure 2.10.4 shows the setting of relevant register. Figure 2.10.5 shows the control procedure.
Port latch
f(XIN) = 4.19 MHz
1/1024
Buzzer output
(4 kHz)
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 2.10.3 Connection of buzzer output circuit and setting of division ratio
Buzzer output control register (address 0EFD16)
BUZCON
0 0 1 1 0
Output frequency: 4 kHz (f(XIN)/1024)
P77/Buz01: Buzzer output
Buzzer output: OFF
Fig. 2.10.4 Setting of relevant register
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
CLT
CLD
••••
BUZCON (address 0EFD16)
XXX001102
••••
CLI
Buzzer output control register setting
(output frequency = 4 kHz, Buz01 output,
buzzer output OFF)
~
~
BUZCON (address 0EFD16), bit 4
1
~
~
Fig. 2.10.5 Control procedure
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Buzzer output ON
APPLICATION
2.11 Reset circuit
2.11 Reset circuit
____________
The reset state is caused by applying
an “L” level to the RESET pin. After that, the reset state is released
____________
by applying an “H” level to the RESET pin, so that the program is executed in the middle-speed mode from
the contents of the reset vector address.
2.11.1 Connection example of reset IC
Figure 2.11.1 shows the example of power-on reset circuit. Figure 2.11.2 shows the system example which
switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT
interrupt.
VCC
Power source
M62022L
GND
Output
RESET
Delay capacity
0.1µF
VSS
38B7 Group
Fig. 2.11.1 Example of power-on reset circuit
System power
source voltage
+5V
VCC
VCC1
RESET
VCC2
INT
RESET
INT
VSS
V1 GND Cd
38B7 Group
M62009L, M62009P, M62009FP
Fig. 2.11.2 RAM backup system example
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APPLICATION
2.11 Reset circuit
2.11.2 Notes on reset
(1) Reset input voltage control
Make sure that the reset input voltage is 0.54 V or less for Vcc of 2.7 V.
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
2.11.3 Each port state during “L” state of RESET pin
Table 2.11.1 shows a pin state during “L” state of RESET pin.
Table 2.11.1 Pin state during “L” state of RESET pin
Pin name
Pin state
P0, P2
Output port (with pull-down resistor)
P1, P3
Input port (with pull-down resistor)
P4, P5, P6 0 to P63
P6 4 to P6 7, P7, P8 0 to P8 3,
Input port (without pull-down resistor)
Input port (floating)
P9, PA, PB 0 to PB 6
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APPLICATION
2.12 Clock generating circuit
2.12 Clock generating circuit
This paragraph explains the setting method of clock generating circuit relevant register, etc.
2.12.1 Relevant register
Figure 2.12.1 shows the structure of the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
4 Port Xc switch bit
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bit
7 Internal system
clock selection bit
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
At reset R W
0
0
0
1
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
1: Stopped
0
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
1
0
0
Fig. 2.12.1 Structure of CPU mode register
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APPLICATION
2.12 Clock generating circuit
2.12.2 Clock generating circuit application examples
(1) Status transition during power failure
Outline: The clock is counted up every one second by using the timer interrupt during a power
failure.
Power failure detection signal
Input port
( N o t e)
38B7 Group
Note: Signal is detected by inputting to each input port,
interrupt input pin, and analog input pin.
Fig. 2.12.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(XIN ) = 4.19 MHz, f(XCIN ) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level on the external
Output port: Fixed to output level that does not cause current flow to the external
(Example) When a circuit turns on LED at “L” output level, fix the
output level to “H”.
I/O port: Input port → Fixed to “H” or “L” level on the external
Output port → Output of data that does not consume current
V REF: Stop to supply to reference voltage input pin by external circuit
Figure 2.12.3 shows the status transition diagram during power failure and Figure 2.12.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
XCIN
Internal
system clock
Middle-speed
mode
High-speed mode
Change internal system
clock to high-speed
mode
Low-speed mode
After detecting, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
XCIN-XCOUT oscillation function selected
Fig. 2.12.3 Status transition diagram during power failure
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2.12 Clock generating circuit
CPU mode register (address 003B16)
CPUM
0 0 0 0 1
0 0
Main clock: High-speed mode (f(XIN)) (Note 1)
CPU mode register (address 003B16)
CP UM
0 0 0 1 1
0 0
(Note 2)
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16)
CP UM
1 0 0 1 1
0 0
(Note 2)
Internal system clock: Low-speed mode (f(XCIN))
CPU mode register (address 003B16)
CP UM
1 0 1 1 1
0 0
(Note 2)
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the highspeed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.12.4 Setting of relevant registers
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2.12 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 003B16), bit 6
CPUM (address 003B16), bit 4
0
1
When selecting main clock f(XIN) (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
••••
N
Detect power failure ?
≈
Y
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
1 (Note)
1 (Note)
Set so that timer interrupt occurs every one
second
Execute WIT instruction
N
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN) oscillation stopped
At a power failure, clock count is performed during
timer interrupt processing (every second).
Return condition from power failure
concluded ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.12.5 Control procedure
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2.12 Clock generating circuit
(2) Counting without clock error during power failure
Outline: It keeps counting without clock error during a power failure.
Specifications: •Reducing power consumption as low as possible while maintaining clock function
•Clock: f(XIN) = 4.19 MHz
•Sub clock: f(XCIN) = 32.768 kHz
•Use of Timer 3 interrupt
For the peripheral circuit and the status transition during a power failure, refer to Figures 2.12.2 and
2.12.3.
Figure 2.12.6 shows the structure of clock counter, Figures 2.12.7 and 2.12.8 show the setting of
relevant registers.
Timer 1 interrupt
Timer 1
f(XIN) = 4.19 MHz
1/16
1/64
Base counter
244 µs
1 second counter
1/256
1/16
When the system returns from a
power failure, add the time taken
for the switching processing for the
return.
Timer 1
<At power failure>
f(XCIN) = 32.768 kHz
1/8
244 µs
Timer 2
Timer 3
1/256
1/16
Timer 3 interrupt
1 minute counter
1s
1/60
Minute/Time/Day/
Month/Year
: Software timer
: Hardware timer
Fig. 2.12.6 Structure of clock counter
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2.12 Clock generating circuit
CPU mode register (address 003B16)
CP UM
0 0 0 1 1
0 0
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16)
CP UM
1 0 0 1 1
0 0
Internal system clock: f(XIN) (high-speed mode)
Timer 1 (address 002016)
T1
3F16
Set (Division ratio -1); 63 (3F16)
Timer 12 mode register (address 002816)
T12M
0 0 0 0 1 0 0 0
Timer 1 count: Operating
Timer 2 count: Operating
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1 underflow
P75 I/O port
Timer 34 mode register (address 002916)
T34M
0 0
0 1
0
Timer 3 count: Operating
Timer 3 count source: Timer 2 underflow
P76 I/O port
Interrupt request register 1 (address 003C16)
IREQ1
0
0
Set “0” to timer 1 interrupt request bit
Set “0” to timer 3 interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
1
Timer 1 interrupt: Enabled
Fig. 2.12.7 Initial setting of relevant registers
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2.12 Clock generating circuit
Timer 12 mode register (address 002816)
T12M
0 1
Timer 1 count source: f(XCIN)
CPU mode register (address 003B16)
CP UM
1 0 0 1 1
0 0
Internal system clock: f(XCIN) (low-speed mode)
CPU mode register (address 003B16)
CP UM
1 0 1 1 1
0 0
Main clock f(XIN): Stopped
Interrupt control register 1 (address 003E16)
ICON1
1
0
Timer 1 interrupt: Disabled
Timer 3 interrupt: Enabled
Timer 1 (address 002016)
T1
0716
Timer 2 (address 002116)
T2
Set (Division ratio – 1)
(T1 = 7 (0716), T2 = 255 (FF16), T3 = 15 (0F16))
FF16
Timer 3 (address 002216)
T3
0F16
Fig. 2.12.8 Setting of relevant registers after detecting power failure
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2.12 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 003B16), bit 4
CPUM (address 003B16), bit 6
T1 (address 002016)
T12M (address 002816)
T34M (address 002916)
IREQ1 (address 003C16), bit 7, bit 5
Base counter (internal RAM)
1 second counter (internal RAM)
ICON1 (address 003E16), bit 5
1
0
3F16
000010002
00XX01X02
0,0
FF16
0F16
1
Port XC: XCIN-XCOUT oscillation function
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
••••
N
Detect power failure ?
≈
Y
T12M (address 002816), bit 3, bit 2
ICON1 (address 003E16), bit 5
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
IREQ1 (address 003C16), bit 7, bit 5
T1 (address 002016)
T2 (address 002116)
T3 (address 002216)
ICON1 (address 003E16), bit 7
0, 1
0
1 (Note)
1 (Note)
0, 0
0716
3F16
0F16
1
Timer 3 interrupt: Enabled
Timer 3 interrupt occurs every second
(return from wait mode)
Execute WIT instruction
N
Timer 1 count source: f(XCIN)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 3 interrupt every second
Generation of one second by hardware timer during
power failure
Return condition for power failure is
satisfied ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.12.9 Control procedure
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2.12 Clock generating circuit
Timer 3 interrupt routine
Push registers to stack etc.
••••
Count 1 minute (internal RAM) counter
1 minute counter overflow ?
N
Y
Modify time, day, month, year
≈
RTI
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2.13 Flash memory
2.13 Flash memory
This paragraph explains the registers setting method and the notes relevant to the flash memory version.
2.13.1 Overview
The flash memory version has functions similar to those of the mask ROM version except that the flash
memory is built-in. However, some of SFR area of flash memory version is different from those of the mask
ROM version (refer to “2.13.2 Memory map”).
In the flash memory version, the built-in flash memory can be operated by using the following three modes.
• CPU reprogramming mode
• Parallel input/output mode
• Serial input/output mode
2.13.2 Memory map
M38B79FFFP has the built-in flash memory of 60 Kbytes.
Figure 2.13.1 shows the memory map of the flash memory version.
000016
SFR area
004016
Internal RAM area
(2 Kbytes)
RAM
083F16
084016
Not used area
0E0016
0EDF16
0EE016
0EFF16
0F0016
0FFF16
100016
User ROM area
RAM area for FLD
automatic display
100016
SFR area
28 Kbytes
RAM area for Serial I/O
automatic transfer
7FFF16
800016
Built-in flash memory area
(60 Kbytes)
32 Kbytes
FFFF16
FFFF16
Fig. 2.13.1 Memory map of flash memory version for 38B7 Group
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2.13 Flash memory
2.13.3 Relevant registers
003B16
CPU mode register (CPUM)
0EFE16 Flash memory control register (FCON)
0EFF16 Flash command register (FCMD)
Fig. 2.13.2 Memory map of registers relevant to flash memory
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Flash memory control register
(FCON: address 0EFE16)
b
Name
Functions
0 CPU reprogramming 0: CPU reprogramming
mod is invalid. (Normal
mode select bit
operation mode)
(Note)
1: When applying 0 V or
VPPL to CNVSS/VPP pin,
CPU reprogramming
mode is invalid. When
applying VPPH to
CNVSS/VPP pin, CPU
reprogramming mode is
valid.
1 Erase/Program
busy flag
0: Erase and program are
completed or not have
been executed.
1: Erase/program is being
executed.
At reset R W
0
0
2 CPU reprogramming 0: CPU reprogramming
mode is invalid.
mode monitor flag
1: CPU reprogramming
mode is valid.
0
3 Fix this bit to “0”.
4 Erase/Program area b5 b4
0 0: Addresses 100016 to
select bits
FFFF16 (total 60 Kbytes)
0 1: Addresses 100016 to
7FFF16 (total 28 Kbytes)
5
1 0: Addresses 800016 to
FFFF16 (total 32 Kbytes)
1 1: Not available
6 Fix this bit to “0”.
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
0
Note: Bit 0 can be reprogrammed only when 0 V is applied to the
CNVSS/VPP pin.
Fig. 2.13.3 Structure of Flash memory control register
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2.13 Flash memory
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Flash command register
(FCMD: address 0EFF16)
b
Functions
At reset R W
0
0 Writing of software command
1 <Software command name> <Command code>
0
“0016”
0
2 •Read command
“4016”
0
3 •Program command
4 •Program verify command “C016”
0
•Erase command
“2016” + “2016”
5 •Erase verify command
0
“A016”
6 •Reset command
0
“FF16” + “FF16”
7
0
Note: The flash command register is write exclusive register.
Fig. 2.13.4 Structure of Flash command register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
4 Port Xc switch bit
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bit
7 Internal system
clock selection bit
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
At reset R W
0
0
0
1
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
1: Stopped
0
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
1
0
0
Note: B6, b7 function in the CPU reprogramming mode is described below.
6 Main clock division
ratio selection bits
7
b7 b6
0 0: φ = f(XIN) (high-speed
mode)
0 1: φ = f(XIN)/4 (middlespeed mode)
1 0: φ = f(XCIN)/2 (lowspeed mode)
1 1: Not available
Fig. 2.13.5 Structure of CPU mode register
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APPLICATION
2.13 Flash memory
2.13.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory area can be performed by a general
ERPOM programmer.
Set the programming mode of EPROM programmer to M5M28F101 and the memory area of program/erase
to 01000 16 to 0FFFF 16. Be careful especially when erasing because if the setting of the memory area is
mistaken when erasing, the products are damaged eternally.
Table 2.13.1 shows the setting of EPROM programmer when programming in the parallel I/O mode.
Recommended programmer: R4945A provided by ADVANTEST CORPORATION (http://www.advantest.co.jp/
index-e.html)
Table 2.13.1 Setting of EPROM programmer when parallel programming
Products
Programming adapter
Programming mode
Memory area
M38B79FFFP
PCA4738F-100
M5M28F101
01000 16 to 0FFFF16
2.13.5 Serial I/O mode
Table 2.13.2 shows the pin connection example using EFP-I✼ between the programmer and the microcomputer
when programming in the serial I/O mode.
✼
EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(Asia and Oceania limited-product)
Table 2.13.2 Connection example to programmer when serial programming
EFP-I
Signal name
38B7 Group flash memory version
Target connector
Pin name
Pin number
Line number
BUSY
1
P67/SRDY2/SCLK22/FLD55
33
VPP (Note 1)
2
CNV SS (Note 1)
17
VDD (Note 3)
SCL
3
4
V CC (Note 3)
P6 6/SCLK21/FLD54
24
SDA
5
P6 4/RxD/FLD52
36
PGM/OE
6
P3 7/FLD 31
57
RESET
7
RESET
18
34
GND (Note 2)
8
V SS, AVSS (Note 2)
21, 97
Notes 1: Connect an approximate 0.01 µF capacitor between CNV SS/V PP and GND for noise elimination.
2: When a serial programmer is connected, at first, connect both GNDs to be the same GND level.
3: When the V CC power has been already supplied to the target board, do not connect the VDD
supply pin of the serial programmer to V CC of the target board.
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2.13 Flash memory
2.13.6 CPU reprogramming mode
In the CPU reprogramming mode, by executing the software command with Central Processing Unit (CPU),
the built-in flash memory area can be reprogrammed. Accordingly, the contents of the built-in flash memory
area can be reprogrammed with the microcomputer mounted on board, without using the ROM programmer.
Program the reprogramming program in advance to the built-in flash memory area. However, in the CPU
reprogramming mode, the read from the built-in flash memory cannot be performed. Accordingly, after
transferring the reprogramming control program on the internal RAM, not the built-in flash memory, execute
it on the RAM.
In the CPU reprogramming mode, read command, program command, program verify command, erase
command, erase verify command, and reset command can be used. As for details of each command, refer
to “CHAPTER 1 Flash memory mode 3 (CPU reprogramming mode)”.
(1)
CPU reprogramming mode beginning/release procedure
Operation procedure in the reprogramming mode for the built-in flash memory is described.
As for the control example, refer to “2.13.7 (2) Control example in the CPU reprogramming mode.”
[Beginning procedure]
➀ Apply 0 V to the CNVSS /VPP pin for reset release.
➁ Set the CPU mode register.
➂ After CPU reprogramming mode control program is transferred to internal RAM, jump to this
control program on RAM. (The following operations are controlled by this control program).
➃ Set “1” to the CPU reprogramming mode select bit (bit 0 of address 0EFE16).
➄ Apply VPPH to the CNV SS/VPP pin.
➅ Wait till CNVSS /VPP pin becomes 12 V.
➆ Read the CPU reprogramming mode monitor flag (bit 2 of address 0EFE16) to confirm that the
CPU reprogramming mode is valid.
➇ The operation of the flash memory is executed by software-command-writing to the flash command
register (address 0EFF16 ).
Note: The following are necessary other than this:
• Control for data which is input from the external (serial I/O etc.) and to be programmed
to the flash memory.
• Initial setting for ports, etc.
• Writing to the watchdog timer
[Release procedure]
➀ Apply 0 V to the CNV SS/V PP pin.
➁ Wait till CNV SS/VPP pin becomes 0 V.
➂ Set the CPU reprogramming mode select bit (bit 0 of address 0EFE 16 ) to “0”.
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2.13 Flash memory
Also, execute the following processing before the CPU reprogramming mode is selected so that interrupts
will not occur during the CPU reprogramming mode.
• Set the interrupt disable flag (I) to “1”
In the CPU reprogramming mode, write to the watchdog timer control register (address 0EEE16 ) periodically
in order not to generate the reset by the underflow of the watchdog timer H.
During the program execution (programming time: max. 10 µs), watchdog timer H is set to “FF16 ”, watchdog
timer L is set to “FF16” and the count is stopped. The count is started again after the program is executed
or the execution of erase is completed. Accordingly, the setting of write period of the watchdog timer
control register is no problem except for the program time and erase time.
When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer enters the
following state;
• Interrupt occurs
This may cause a program runaway because the read from the flash memory which has the interrupt vector
area cannot be performed.
• Underflow of watchdog timer H, reset
This may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory
control register are reset.
Also, when the above interrupt and reset occur during program/erase, error data may still exist after reset
release because the reprogramming of the flash memory is not completed, so that be careful. In this case,
reprogramming of the flash memory in the parallel I/O mode or serial I/O mode is required.
2.13.7 Flash memory mode application examples
The control pin processing example on the system board in the serial I/O mode and the control example
in the CPU reprogramming mode are described below.
(1) Control pin processing example on the system board in serial I/O mode
As shown in Figure 2.13.6, in the serial I/O mode, the contents of the built-in flash memory can be
reprogrammed with the microcomputer mounted on board. In the serial I/O mode, the processing
example of control pins (P3 7, P64, P6 6, P6 7, CNVSS and RESET pin) is described below.
RS-232C Serial programmer
Master ROM
M3
8B
79
FF
FP
Fig. 2.13.6 Reprogramming example of built-in flash memory by serial I/O mode
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2.13 Flash memory
➀ When control signals are not affected to user system circuit
When the control signals in the serial I/O mode are not used or not affected to the user system
circuit, they can be connected as shown in Figure 2.13.7.
Target board
*
Not used or to user system circuit
M38B79FFFP
SDA(P64)
SCLK(P66)
OE(P37)
BUSY(P67)
VCC
AVSS
VPP(CNVSS)
RESET
VSS
XIN XOUT
User reset signal (Low active)
* : When not used, set to input mode and pull up or pull down, or set to output mode and open.
Fig. 2.13.7 Processing example of pins on board in serial I/O mode (1)
➁ When control signals are affected to user system circuit-1
Figure 2.13.8 shows the example that the control signals supplied to the user system circuit are
cut-off by a jumper switch in the serial I/O mode.
Target board
To user system circuit
M38B79FFFP
SDA(P64)
SCLK(P66)
OE(P37)
BUSY(P67)
VCC
AVSS
VSS
VPP(CNVSS)
RESET
XIN XOUT
User reset signal (Low active)
Fig. 2.13.8 Processing example of pins on board in serial I/O mode (2)
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2.13 Flash memory
➂ When control signals are affected to user system circuit-2
Figure 2.13.9 shows the example that the control signals supplied to the user system circuit are
cut-off by an analog switch (74HC4066) in the serial I/O mode.
Target board
74HC4066
To user system circuit
M38B79FFFP
SDA(P64)
SCLK(P66)
OE(P37)
BUSY(P67)
VCC
AVSS
VSS
VPP(CNVSS)
RESET
XIN XOUT
User reset signal (Low Active)
Fig. 2.13.9 Processing example of pins on board in serial I/O mode (3)
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2.13 Flash memory
(2)
Control example in CPU reprogramming mode
In this example, the built-in flash memory is reprogrammed in the CPU reprogramming mode by
serial I/O2, receiving the reprogramming data (updated data).
Figure 2.13.10 shows the example for the reprogramming system of the built-in flash memory by the
CPU reprogramming mode.
M38B79FFFP
Port for CPU reprogramming mode switch
(CPU reprogramming mode is
selected/released by port Pi2 input signal)
Pi2
VCC
Pi0
SCLK21
Reprogramming data input mode
(Updated data is received by serial I/O2)
RxD
VSS
TxD
VPP circuit control port
ON/OFF of VPP control
circuit is controlled by
port Pi1 output.
*
12V
0V
VPP *
control
circuit
Pi1
RESET
VPP(CNVSS)
User reset signal
XIN XOUT
4MHz
Refer to Figure 2.13.15 and Figure 2.13.16.
(i = 0 to 6)
Fig. 2.13.10 Example for reprogramming system of built-in flash memory by CPU reprogramming
mode
● Specifications
➀ CPU reprogramming mode is selected/released by the input signal to Pi2.
➁ Updated data is received by serial I/O2.
➂ The transfer enable state of serial transmit side is judged by “L” level input to Pi0.
➃ V PP control circuit is turned ON/OFF by the output from Pi 1 (refer to Figure 2.13.15 and Figure
2.13.16).
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2.13 Flash memory
Note: In this example, the following program is transferred to the internal RAM
and executed on the internal RAM.
CPU reprogramming
In this program example, the flash memory is reprogrammed by
control program example receiving each 1 byte of data for reprogramming by serial I/O.
➀ Preparing for transition to CPU
reprogramming mode
Disable the interrupt of built-in
peripheral functions in this processing.
Also, initialize the watchdog timer (write
to watchdog timer register) in order not
to generate the watchdog timer
interrupt.
Serial I/O initialization
set
Interrupt disable processing
CPU reprogramming mode
select bit = “1”
12 V applied circuit
to VPP “ON”
Port Pi1 = “1”
VPP applied voltage = VPPH
waiting for stabilizing *1
NO
➁ Transition to CPU reprogramming mode
Initialize the watchdog timer (write to
watchdog timer register) in order not to
generate the watchdog timer interrupt in
this processing.
CPU reprogramming
mode monitor flag
= “1” ?
YES
5 ms wait
NO
*2
Confirmation that CPU
reprogramming mode
is valid.
CPU reprogramming
mode monitor flag
= “1” ?
YES
Continue to “CPU reprogramming
control program example (2)” to the
next page.
*1: Waiting by software until VPP input voltage is stabilized at VPPH
is recommended. (Refer to Figure 2.13.15 and Figure 2.13.16
VPP voltage control timing A .)
*2: The wait time depends on VPP control circuit (Refer to Figure
2.13.15 and Figure 2.13.16 VPP voltage control timing C .)
Fig. 2.13.11 CPU reprogramming control program example (1)
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2.13 Flash memory
From the previous page “CPU
reprogramming control
program example (1)”
YES
All addresses
= “0016” ?
NO
Program/program verify
processing
All bytes = “0016” ?
Refer to “➃ Program/program verify” for
program/program verify flow chart.
Erase/verify start
address setting
Initialization of software counter
(retry counter) for erasure retry
counter = “0”
From next
page b
Retry counter + 1
“2016” is written twice continuously
to flash command register
(address 0EFF16)
Erase command issued
1 µs wait *1
NO
Erase/program
busy flag = “0” ?
YES
“A016” is written to flash
Erase verify command issued command register
(address 0EFF16)
6 µs wait *2
To next
page a
FAIL
Erase/verify
data check
PASS
NO
Erase/verify
last address
YES
Erase/verify address +1
Continue to “CPU reprogramming control
program example (4)” to the page after next
*1: The wait processing time shown in the flow chart is required
regardless of the external clock input frequency.
*2: The wait time depends on the VPP control circuit (refer to
Figure 2.13.15 and Figure 2.13.16 VPP voltage control timing C ).
Fig. 2.13.12 CPU reprogramming control program example (2)
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➂ Erasure of reprogramming area
Initialize the watchdog timer
(write to watchdog timer register)
in order not to generate the
watchdog timer interrupt in this
processing.
APPLICATION
2.13 Flash memory
To previous page “CPU
reprogramming
control program
example (2) b”
From previous page “CPU reprogramming
control program example (2) a”
Continued from ➂
NO
Retry counter
=1000 ?
YES
Port Pi1 = “0”
VPP applied voltage = VPPL
waiting for stabilizing *1
NO
CPU reprogramming
mode monitor flag
= “0” ?
YES
5 ms wait *2
➄ CPU reprogramming mode release
Initialize the watchdog timer
(write to watchdog timer register)
in order not to generate the watchdog
timer interrupt in this processing.
CPU reprogramming mode
select bit = “0”
NO
CPU reprogramming
mode select bit
= “0”
YES
CPU reprogramming error
*1: Waiting by software until VPP input voltage is stabilized at VPPL
is recommended. (Refer to Figure 2.13.15 and Figure 2.13.16
VPP voltage control timing B.)
*2: The wait time depends on VPP control circuit (Refer to Figure
2.13.15 and Figure 2.13.16 VPP voltage control timing C.)
Fig. 2.13.13 CPU reprogramming control program example (3)
38B7 Group User’s Manual
2-185
APPLICATION
2.13 Flash memory
From the page before previous “CPU reprogramming
control program example (2)”
Program initial address setting
Initialization of software counter
(retry counter) for reprogramming
retry counter = “0”
➃ Program/program verify
Initialize the watchdog timer
(write to watchdog timer
register) in order not to
generate the watchdog timer
interrupt in this processing.
Reprogramming data receive
by serial I/O
Retry counter + 1
Program command issued
Reprogramming data is written
to program address
“4016” is writ ten to flas h
comman d register
(addres s 0EFF16)
1 µs wait *1
NO
Erase/program
busy flag = “0” ?
Waiting for writing completed
YES
Program verify command issued
“C016” is written t o flash
comman d register
(addres s 0EFF16)
6 µs wait *1
FAIL
NO
Program verify
data check
PASS
Retry counter
= 25?
Program last address
NO
YES
YES
Port Pi1 = “0”
VPP applied voltage = VPPL
waiting for stabilizing *2
Port Pi1 = “0”
Program address + 1
12 V applied circuit
to VPP “OFF”
VPP applied voltage = VPPL
waiting for stabilizing *2
NO
CPU reprogramming
mode monitor flag
= “0” ?
YES
NO
5 ms wait *3
YES
CPU reprogramming
mode select bit = “0”
NO
5 ms wait *3
CPU reprogramming mode
select bit = “0”
CPU reprogramming
mode select bit
= “0”
YES
CPU reprogramming error
➄ CPU reprogramming mode release
Initialize the watchdog timer
(write to watchdog timer register)
in order not to generate the watchdog
timer interrupt in this processing.
CPU reprogramming
mode monitor flag
= “0” ?
Waiting for release of CPU
reprogramming mode
NO
CPU reprogramming
mode select bit
= “0”
YES
END
*1: The wait processing time shown in the flow chart is required regardless of the external clock input frequency.
*2: Waiting by software until VPP input voltage is stabilized at VPPL is recommended. (Refer to Figure 2.13.15 and
Figure 2.13.16 VPP voltage control timing B .)
*3: The wait time depends on VPP control circuit (Refer to Figure 2.13.15 and Figure 2.13.16 VPP voltage control
timing C .)
Fig. 2.13.14 CPU reprogramming control program example (4)
2-186
38B7 Group User’s Manual
APPLICATION
2.13 Flash memory
● When 12 V voltage is supplied to target system
VIN=12V
At Pi1 = L output, VPP = 11.8 V
At Pi1 = H output, VPP = 0 V
2SA1364
System power source
VPP
RT1N144C
30 KΩ
1000 pF
➀ M5237L ➂
➁
220 Ω
10 KΩ
47 KΩ
2.7 KΩ
at OFF signal = 3 V
5 KΩ
47 µF
1 KΩ
Pi1 (VPP circuit control port)
ON/OFF signal
MC2848
4.3 KΩ
0.33 µF
Input ON/OFF signal
in order that this point
may become 1.5 V or
more at OFF output.
VPP voltage control timing
Pi1 = H
Pi1 = L
VPP = 12 V
C
VPP = 0 V
C
A
B
Interval until VPP = VPP H
Transition to CPU reprogramming
mode cannot be performed.
Interval until VPP = VPP L
CPU reprogramming mode cannot
be released.
Fig. 2.13.15 VPP control circuit example (1)
● When only 5 V voltage is supplied to target system
VIN=5 V
At Pi1 = L output, VPP = 12 V
At Pi1 = H output, VPP = 0 V
Shot key
Diode
100 µH
RT1P137P
System power source
VPP
100 µF
1 KΩ
22 KΩ
RT1N144C
➆
E OUT ➁
M62212FP
0.1 µF
FB
DTC
GND
➅
➄
➂
RT1N144C
22 KΩ
10 KΩ
100 µF 0.1 µF
2SD1972
1 KΩ
IN
47 KΩ
3.9 KΩ
C OUT
➃ COSC
100 pF
10 KΩ
33 KΩ
➀
➇
VCC
10 KΩ
1 KΩ
Smaller VF
is better.
100 Ω
Set radiation about
0.36 W ✕ 5
0.1 µF
1 KΩ
(VPP circuit control port) Pi
2SC3580
ON/OFF signal
47 KΩ
47 KΩ
VPP voltage control timing
Pi1 = H
Pi1 = L
VPP = 12 V
C
VPP = 0 V
A
Interval until VPP = VPP H
Transition to CPU reprogramming
mode cannot be performed.
C
B
Interval until VPP = VPP L
CPU reprogramming mode cannot
be released.
Fig. 2.13.16 VPP control circuit example (2)
38B7 Group User’s Manual
2-187
APPLICATION
2.13 Flash memory
2.13.8 Notes on CPU reprogramming mode
(1) Transfer the CPU reprogramming mode control program to the internal RAM before selecting the
CPU reprogramming mode, and then, execute it on the internal RAM. Additionally, when the subroutine
or stack operation instruction is used in the control program, make sure in order not to destroy the
control program transferred to the internal RAM through the stack area.
(2) Be careful of the instruction description (specifying address, and so on) because the CPU reprogramming
mode control program is transferred to the internal RAM and executed on the internal RAM.
(3) Write to the watchdog timer control register periodically in order not to generate the watchdog timer
interrupt by the CPU reprogramming mode control program (refer to “2.9 Watchdog timer”).
2.13.9 Notes on flash memory version
The CNV SS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has
the multiplexed function to be a programmable power source pin (VPP pin) as well.
To improve the noise margin, connect the CNV SS pin to V SS through 1 to 10 kΩ resistance.
Even when the wiring of the CNVSS pin of the mask ROM version is connected to Vss through this resistor,
that will not affect operation.
2-188
38B7 Group User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 Control registers
3.6 Package outline
3.7 Machine instructions
3.8 List of instruction code
3.9 M35501FP
3.10 SFR memory map
3.11 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VCC
VEE
VI
Pd
Parameter
Power source voltages
Pull-down power source voltages
Input voltage P64–P67, P70–P77, P80–P83,
P90–P97, PA0–PA7, PB0–PB6
Input voltage P10–P17, P30–P37, P40–P47,
P50–P57, P60–P63
Input voltage RESET, XIN, CNVSS
Input voltage XCIN
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P63
Output voltage P64–P67, P80–P83, P70–P77,
P90–P97, PA0–PA7, PB0–PB6,
XOUT, XCOUT
Power dissipation
Topr
Tstg
Operating temperature
Storage temperature
VI
VI
VI
VO
VO
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = –20 to 65 °C
Ta = 65 to 85 °C
Ratings
–0.3 to 6.5
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
Unit
V
V
V
VCC –45 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC –45 to VCC +0.3
V
V
V
–0.3 to VCC +0.3
V
800
800 –12.5 ✕ (Ta –65)
–20 to 85
–40 to 125
mW
mW
°C
°C
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
4.0
2.7
4.0
Typ.
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
VCC
Power source voltage (mask ROM version)
VCC
VSS
VEE
VREF
Power source voltage (flash memory version)
Power source voltage
Pull-down power source voltage
Analog reference voltage
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Analog power source voltage
Analog input voltage AN0–AN15
“H” input voltage
P70–P77, P80–P83, P90–P97, PA0–PA7, PB0–PB6
“H” input voltage
P64–P67
0
0.75VCC
0.4VCC
VCC
VCC
VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
0.52VCC
0.8VCC
0.8VCC
0
0
0
0
0
VCC
VCC
VCC
0.25VCC
0.16VCC
0.2VCC
0.2VCC
0.2VCC
3-2
High-speed mode
Middle/Low-speed mode
when A-D converter is used
when D-A converter is used
P10–P17, P30–P37, P40–P47, P50–P57, P60–P63
RxD, SCLK21, SCLK22
XIN, XCIN, RESET, CNVss
P70–P77, P80–P83, P90–P97, PA0–PA7, PB0–PB6
P64–P67
P10–P17, P30–P37, P40–P47, P50–P57, P60–P63
RxD, SCLK21, SCLK22
XIN, XCIN, RESET, CNVss
38B7 Group User’s Manual
Vcc –43
2.0
3.0
VCC
VCC
VCC
0
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ΣI OH(peak)
ΣI OH(peak)
ΣI OL(peak)
ΣI OL(peak)
ΣI OH(avg)
ΣI OH(avg)
ΣI OL(avg)
I OH(peak)
I OH(peak)
I OL(peak)
I OH(avg)
I OH(avg)
I OL(avg)
f(CNTR)
f(XIN )
f(XCIN )
Parameter
“H” total peak output current (Note 1) P00–P07, P10–P17, P20–P27, P3 0–P37, P40–P47,
P50–P57, P60–P67, P70–P77
“H” total peak output current (Note 1) P80–P83, P90–P97, PA 0–PA7, PB0–PB6
“L” total peak output current (Note 1) P64–P67, P70–P7 7
“L” total peak output current (Note 1) P80–P83, P90–P97, PA 0–PA7, PB0–PB6
“H” total average output current (Note 1) P0 0–P07, P10–P17, P20–P27, P3 0–P37, P40–P47,
P50–P57, P60–P63
“H” total average output current (Note 1) P6 4–P67, P7 0–P7 7, P8 0–P8 3, P9 0–P97, PA0–PA7,
PB0–PB 6
“L” total average output current (Note 1) P64–P67, P70–P77, P80–P83, P90–P97, PA0–PA7,
PB0–PB 6
“H” peak output current (Note 2) P00–P07, P10–P17, P2 0–P27, P30–P37, P40–P47,
P5 0–P57, P60–P63
“H” peak output current (Note 2) P6 4–P6 7, P7 0–P77, P80–P83, P90–P97, PA0–PA7,
PB0–PB 6
“L” peak output current (Note 2) P6 4–P67, P70–P77, P80–P83, P90–P97, PA0–PA7,
PB0–PB 6
“H” average output current (Note 3) P0 0–P07, P10–P17, P20–P27, P3 0–P37, P40–P47,
P50–P57, P60–P63
“H” average output current (Note 3) P6 4–P67, P70–P77, P8 0–P83, P90–P97, PA0–PA7,
PB0–PB 6
“L” average output current (Note 3) P6 4–P67, P70–P77, P80–P83, P9 0–P97, PA 0–PA7,
PB0–PB 6
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
Main clock input oscillation frequency (Note 4)
Sub-clock input oscillation frequency (Notes 4, 5)
Min.
Limits
Typ.
32.768
Max.
–240
Unit
mA
–60
100
60
–120
mA
mA
mA
mA
–30
mA
50
mA
–40
mA
–10
mA
10
mA
–18
mA
–5
mA
5
mA
250
4.2
50
kHz
MHz
kHz
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH(avg) are average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
38B7 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VT+ –VT–
VT+ –VT–
VT+ –VT–
I IH
I IH
I IH
I IH
I IL
Parameter
Test conditions
“H” output voltage
P00–P07, P10 –P17, P20–P27 ,
P30–P37, P40 –P47, P50-P5 7,
P60–P63
“H” output voltage
P64–P67, P70 –P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
“L” output voltage
P64–P67, P70 –P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
Hysteresis
RxD, S CLK21, SCLK22, S RDY1, P70 –
P73, P7 7, P82–P83, P90 –P92, PB0,
PB 2, PB4–PB6
Hysteresis
RESET, XIN
Hysteresis
XCIN
“H” input current
P64–P67, P70 –P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
“H” input current
P10–P17, P30 –P37, P40–P47 ,
P50-P57 , P60–P63 (Note)
“H” input current
RESET, CNVss, XCIN
“H” input current
XIN
“L” input current
P64–P67, P70 –P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
I IL
“L” input current
I IL
I IL
“L” input current
“L” input current
P10–P17, P30 –P37, P40–P47 ,
P50–P57, P60 –P63 (Note)
RESET, CNVss, XCIN
XIN
IOH = –18 mA
IOH = –10 mA
VCC–2.0
Typ.
Max.
Unit
V
V
IOL = 10 mA
2.0
V
0.4
V
0.5
0.5
VI = V CC
5.0
V
V
µA
VI = V CC
5.0
µA
5.0
–5.0
µA
µA
µA
VI = V CC
VI = V CC
VI = V SS
Pull-up “off”
VCC = 5 V, VI = VSS
Pull-up “on”
VCC = 3 V, VI = VSS
Pull-up “on”
VI = V SS
VI = V SS
VI = V SS
Note: Except when reading ports P1, P3, P4, P5 or P6.
3-4
Limits
Min.
VCC–2.0
38B7 Group User’s Manual
4.0
–30
–70
–140
µA
–6.0
–25
–45
µA
–5.0
µA
–5.0
µA
µA
–4.0
APPENDIX
3.1 Electrical characteristics
Table 3.1.5 Electrical characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, T a = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
I LOAD
I LEAK
I READH
VRAM
I CC
Parameter
Output load current
P00–P07 , P10–P17,
P20–P27 , P30–P37,
(P4 0–P47, P50–P57 ,
P60–P63 at option)
Output leak current
P00–P07 , P10–P17,
P20–P27 , P30–P37,
P40–P47 , P50–P57,
P60–P63
“H” read current
P10–P17 , P30–P37,
P40–P47 , P50–P57,
P60–P63
RAM hold voltage
Power source current
Test conditions
VEE = VCC–43 V, VOL =VCC
Output transistors “off”
Typ.
Max.
400
600
900
µA
–10
µA
VEE = VCC–43 V, VOL =VCC–43 V
Output transistors “off”
VI = 5 V
When clock is stopped
High-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz
f(XCIN ) = 32.768 kHz
Output transistors “off”
High-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN ) = 32.768 kHz
Output transistors “off”
Middle-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz
f(XCIN ) = stopped
Output transistors “off”
Middle-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN ) = stopped
Output transistors “off”
Low-speed mode, Vcc = 3 V,
f(XIN) = stopped
f(XCIN ) = 32.768 kHz
Output transistors “off”
Low-speed mode, Vcc = 3 V,
f(XIN) = stopped
f(XCIN ) = 32.768 kHz (in WIT state)
Output transistors “off”
Increment when A-D conversion is
executed
All oscillation stopped
Ta = 25 °C
(in STP state)
Output transistors “off” Ta = 85 °C
38B7 Group User’s Manual
Unit
Min.
µA
1
2
7.0
5.5
15
V
mA
1
mA
3
mA
1
mA
20
55
µA
8
20
µA
mA
0.6
0.1
1
µA
10
µA
3-5
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter charactristics
Table 3.1.6 A-D converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN ) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Symbol
Parameter
Test conditions
—
Resolution
—
Absolute accuracy (excluding quantization error)
Limits
Min.
VCC = VREF = 5.12 V
Unit
Typ.
Max.
10
Bits
±1
±2.5
LSB
62
tc(φ )
TCONV
Conversion time
61
IVREF
Reference input current
150
200
µA
I IA
Analog port input current
0.5
5.0
µA
RLADDER
Ladder resistor
35
VREF = 5.0 V
50
kΩ
3.1.5 D-A converter charactristics
Table 3.1.7 D-A converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to Vcc, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
–
tsu
RO
I VREF
Parameter
Test conditions
Resolution
Absolute accuracy
(excluding quantization error)
Setting time
Output resistor
Reference power source input current (Note)
Typ.
VCC = 4.0–5.5 V
VCC = 3.0–5.5 V
Note: Except ladder resistor for A-D converter
3-6
Limits
Min.
38B7 Group User’s Manual
1
2.5
Max.
8
1.0
2.5
3
4
3.2
Unit
Bits
%
%
µs
kΩ
mA
APPENDIX
3.1 Electrical characteristics
3.1.6 Timing requirements and switching characteristics
Table 3.1.8 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW (RESET)
tC (XIN)
tWH (XIN)
tWL (XIN)
tC (XCIN )
tWH (XCIN )
tWL (XCIN )
tC (CNTR)
tWH (CNTR)
tWL (CNTR)
tWH (INT)
tWL (INT)
tWH (INT2)
tWL (INT2)
tC (SCLK1 )
tWH (SCLK1 )
tWL (SCLK1 )
tsu(SIN1 -SCLK1 )
th (SCLK1-S IN1)
tC (SCLK2 )
tWH (SCLK2 )
tWL (SCLK2 )
tsu(RxD-S CLK2)
th (SCLK2-RxD)
tC (SCLK3 )
tWH (SCLK3 )
tWL (SCLK3 )
tsu(SIN3 -SCLK3 )
th (SCLK3-S IN3)
Parameter
Reset input “L” pulse width
Main clock input cycle time (X IN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0–CNTR 2 input cycle time
CNTR0–CNTR 2 input “H” pulse width
CNTR0–CNTR 2 input “L” pulse width
INT0 –INT4 input “H” pulse width (INT2 when noise filter is not used)
(Note 1)
INT0 –INT4 input “L” pulse width (INT 2 when noise filter is not used)
(Note 1)
INT2 input “H” pulse width (when noise filter is used) (Notes 1, 2)
INT2 input “L” pulse width (when noise filter is used) (Notes 1, 2)
Serial I/O1 clock input cycle time
Serial I/O1 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
Serial I/O3 clock input cycle time
Serial I/O3 clock input “H” pulse width
Serial I/O3 clock input “L” pulse width
Serial I/O3 input setup time
Serial I/O3 input hold time
Min.
2.0
238
60
60
20
5.0
5.0
4.0
1.6
1.6
80
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
80
ns
3
3
950
400
400
200
200
800
370
370
220
100
1000
400
400
200
200
CLKs
CLKs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: IIDCON2, IIDCON3 = “00” when noise filter is not used
IIDCON2, IIDCON3 = “01” or “10” when noise filter is used
2: Unit indicates sample clock number of noise filter.
38B7 Group User’s Manual
3-7
APPENDIX
3.1 Electrical characteristics
Table 3.1.9 Switching characteristics
(V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
tWH (S CLK)
tWL (SCLK)
td (SCLK1 -SOUT1)
tV (SCLK1-S OUT1)
td (SCLK2 -TxD)
tV (SCLK2-TxD)
td (SCLK3 -SOUT3)
tV (SCLK3-S OUT3)
tr (S CLK)
tf (SCLK)
tr (Pch–strg)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O3 output delay time (Note 3)
Serial I/O3 output valid time (Note 3)
Serial I/O clock output rising time
Serial I/O clock output falling time
P-channel high-breakdodwn-voltage output
rising time (Note 4)
P-channel high-breakdodwn-voltage output
rising time (Note 5)
CL = 100 pF
CL = 100 pF
tr (Pch–weak)
Notes 1: When
2: When
3: When
4: When
5: When
the
the
the
the
the
Limits
Min.
Typ.
t C(S CLK)/2–160
t C(S CLK)/2–160
55
1.8
µs
200
0
140
–30
200
0
40
40
CL = 100 pF
CL = 100 pF
CL = 100 pF
VEE = Vcc –43 V
CL = 100 pF
VEE = Vcc –43 V
High-breakdown voltage
P-channel open-drain output port
P66/SCLK21,
P67/SCLK22,
P92/SCLK3,
PB0/SCLK12,
PB4/SCLK11
P0, P1, P2, P3,
P4, P5, P60–P63
CL
CL
(Note)
VEE
Note: Ports P4, P5, P60–P63 need external resistors.
Fig. 3.1.1 Circuit for measuring output switching characteristics
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38B7 Group User’s Manual
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PB 5/S OUT1 P-channel output disable bit of the serial I/O1 control register (bit 7 of address 001A16) is “0”.
P65 /TxD P-channel output disable bit of the UART control register (bit 4 of address 003816) is “0”.
P91 /SOUT3 P-channel output disable bit of the serial I/O3 control register (bit 7 of address 0EEC16) is “0”.
high-breakdown voltage port drivability selection bit of the FLDC mode register (bit 7 of address 0EF4 16) is “0”.
high-breakdown voltage port drivability selection bit of the FLDC mode register (bit 7 of address 0EF4 16) is “1”.
Serial I/O clock output port
Max.
APPENDIX
3.1 Electrical characteristics
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
INT0–INT4
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XIN
0.8VCC
0.2VCC
tC(XCIN)
tWL(X CIN)
tWH(XCIN)
XCIN
0.8VCC
0.2VCC
tC(SCLK)
tf(SCLK)
SCLK
tWL(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
tsu(RxD-S CLK)
th(SCLK-SIN)
th(SCLK-RxD)
0.8VCC
0.2VCC
SIN, RxD
td(SCLK-SOUT)
td(SCLK-TxD)
tv(SCLK-SOUT)
tv(SCLK-TxD)
SOUT, TxD
Fig. 3.1.2 Timing diagram
38B7 Group User’s Manual
3-9
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
Standard characteristics described below are just examples. These are NOT guaranteed. For rated values,
refer to “3.1 Electrical characteristics”.
3.2.1 Power source current standard characteristics
7.0
Power source current
(mA)
6.0
5.0
Vcc = 5.5 V
4.0
3.0
Vcc = 4.0 V
2.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current standard characteristics
1400
1200
Power source current
(mA)
1000
Vcc = 5.5 V
800
600
Vcc = 4.0 V
400
200
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current standard characteristics (in wait mode)
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38B7 Group User's Manual
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristics
IOH
(mA)
-100
Port P0 0 IOH-V OH characteristics (25 °C)
(Same characteristics pins: P0, P1, P2, P3, P4, P5, P60 to P6 3)
-9 0
-8 0
-7 0
Vcc=5.5V
Vcc = 5.0 V
-6 0
-5 0
Vcc = 3.0 V
-4 0
-3 0
-20
-10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VOH (V)
Fig. 3.2.3 High-breakdown P-channel open-drain output port characteristics (25 °C)
IOH
(mA)
-100
Port P0 0 IOH-V OH characteristics (90 °C)
(Same characteristics pins: P0, P1, P2, P3, P4, P5, P60 to P6 3)
-9 0
-8 0
Vcc = 5.5 V
-7 0
V cc = 5.0 V
-6 0
-5 0
Vcc = 3.0 V
-4 0
-3 0
-2 0
-1 0
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VOH (V)
Fig. 3.2.4 High-breakdown P-channel open-drain output port characteristics (90 °C)
38B7 Group User's Manual
3-11
APPENDIX
3.2 Standard characteristics
IOH
(mA)
-100
Port P9 0 IOH -VOH characteristics (25 °C)
(Same characteristics pins: P64 to P6 7, P7, P8, P9, PA, PB)
-9 0
-8 0
-7 0
-6 0
-5 0
Vcc = 5.5 V
-4 0
Vcc = 5.0 V
-3 0
-20
-1 0
0
0.0
Vcc = 3.0 V
1.0
2.0
3.0
4.0
5.0
6.0
VOH (V)
Fig. 3.2.5 CMOS output port P-channel side characteristics (25 °C)
IOH
(mA)
-100
Port P9 0 IOH -VOH characteristics (90 °C)
(Same characteristics pins: P64 to P6 7, P7, P8, P9, PA, PB)
-90
-8 0
-7 0
-6 0
-5 0
Vcc = 5.5 V
-4 0
Vcc = 5.0 V
-3 0
-2 0
-1 0
Vcc = 3.0 V
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VOH (V)
Fig. 3.2.6 CMOS output port P-channel side characteristics (90 °C)
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38B7 Group User's Manual
APPENDIX
3.2 Standard characteristics
IOL
(mA)
100
Port P9 0 IOL-V OL characteristics (25 °C)
(Same characteristics pins: P64 to P67 , P7, P8, P9, PA, PB)
90
80
70
60
Vcc = 5.5 V
50
40
Vcc = 5.0 V
30
20
Vcc = 3.0 V
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VOL (V)
Fig. 3.2.7 CMOS output port N-channel side characteristics (25 °C)
IOL
(mA)
100
Port P9 0 IOL-V OL characteristics (90 °C)
(Same characteristics pins: P64 to P67 , P7, P8, P9, PA, PB)
90
80
70
60
50
Vcc = 5.5 V
40
Vcc = 5.0 V
30
20
Vcc=3.0V
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VOL (V)
Fig. 3.2.8 CMOS output port N-channel side characteristics (90 °C)
38B7 Group User's Manual
3-13
APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics
Figure 3.2.9 shows the A-D conversion standard characteristics.
The lower line on the graph indicates the absolute precision error. It expresses the deviation from the ideal
value. For example, the conversion of output code from 0016 to 01 16 occurs ideally at the point of AN 0 =
2.5 mV, but the measured value is –2 mV. Accordingly, the measured point of conversion is defined as “2.5
– 2 = 0.5 mV”.
The upper line on the graph indicates the width of input voltages equivalent to output codes. For example,
the measured width of the input voltage for output code 6016 is 6 mV, so that the differential nonlinear error
is defined as “6 – 5 = 1 mV (0.2 LSB)”.
M38B79MFH-G000FP A-D CONV. ERROR & STEP WIDTH
ERROR/1LSB WIDTH(mV)
ERROR/1LSB WIDTH(mV)
ERROR/1LSB WIDTH(mV)
ERROR/1LSB WIDTH(mV)
C38B79MFH-G000R-S52T 001 Sample No.1 Mode
VDD = 5.12 [V] : VREF = 5.12 [V]
XIN = 4 [MHz] : Ta = 25 [deg.]
Error (Absolute precision error)
1LSB Width
15
10
5
0
-5
-1 0
-1 5
0
16
32
48
64
80
96
112
128 144
STEP No.
160
176
192
208
224
240
256
272
288
304
320
336
352
368
384 400
STEP No.
416
432
448
464
480
496
512
528
544
560
576
592
608
624
640 656
STEP No.
672
688
704
720
736
752
768
784
800
816
832
848
864
880
896 912
STEP No.
928
944
960
976
992
15
10
5
0
-5
-1 0
-15
256
15
10
5
0
-5
-10
-15
512
15
10
5
0
-5
-1 0
-1 5
768
Fig. 3.2.9 A-D conversion standard characteristics
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38B7 Group User's Manual
1008 1024
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Change of relevant register settings
When switching an active edge of an external interrupt or switching an interrupt sources of an
interrupt vector address where two or more interrupt sources are allocated, the interrupt request bit
may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take
the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit, the active edge
switch bit, or the interrupt source select bit to “1”.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 3.3.1 Setting procedure of relevant registers
■ Reason
When setting the followings, the interrupt request bit may be set to “1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A 16)
•When switching interrupt sources of an interrupt vector address where
two or more interrupt sources are allocated
Related register: Interrupt source switch register (address 39 16)
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
38B7 Group User’s Manual
3-15
APPENDIX
3.3 Notes on use
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 2
to “0”. Figure 3.3.3 shows the structure of the
interrupt control register 2.
b7
0
b0
Interrupt control register
Address 003F16
Interrupt enable bits
Not used
Fix this bit to “0”.
Fig. 3.3.3 Structure of interrupt control register 2
3.3.2 Notes on I/O port
(1) Notes in standby state
In standby state✽1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using an optional built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying port latch of I/O port with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
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APPENDIX
3.3 Notes on use
•As for bit which
The pin state is
•As for bit which
The bit value is
is set for input port:
read in the CPU, and is written to this bit after bit managing.
is set for output port:
read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
(3) Pull-up/Pull-down control
When each port which has built-in pull-up/pull-down resistor is set to output port, pull-up/pull-down
control of corresponding port becomes invalid. (Pull-up/pull-down cannot be set.)
● Reason
Pull-up/pull-down control is valid only when each direction register is set to the input mode.
3.3.3 Notes on serial I/O1
(1) Clock
■ Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before perform the normal serial I/O transfer or the serial I/O automatic transfer.
■ Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit
before performing the normal serial I/O transfer or the serial I/O automatic transfer.
(2) Using serial I/O1 interrupt
Clear bit 3 of the interrupt request register 1 to “0” by software before enabling interrupts.
(3) State of S OUT1 pin
The S OUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the
SOUT1 pin when serial data is not transferred; either output active or high-impedance. However, when
selecting an external synchronous clock; the S OUT1 pin can become the high-impedance state by
setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.
(4) Serial I/O initialization bit
● Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a
serial transfer during transferring.
● When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is
not initialized. Set the value of each register by program.
38B7 Group User’s Manual
3-17
APPENDIX
3.3 Notes on use
(5) Handshake signal
■ S BUSY1 input signal
Input an “H” level to the SBUSY1 input and an “L” level signal to the SBUSY1 input in the initial state.
When the external synchronous clock is selected, switch the input level to the S BUSY1 input and
the SBUSY1 input while the serial I/O1 clock input is in “H” state.
■ S RDY1 input•output signal
When selecting the internal synchronous clock, input an “L” level to the S RDY1 input and an “H”
level signal to the S RDY1 input in the initial state.
(6) 8-bit serial I/O mode
■ When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O1 register are being
shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control
the clock externally.
(7) In automatic transfer serial I/O mode
■ Set of automatic transfer interval
● When the S BUSY1 output is used, and the S BUSY1 output and the SSTB1 output function as signals for
each transfer data set by the SBUSY1 output•S STB1 output function selection bit of serial I/O1 control
register 2; the transfer interval is inserted before the first data is transmitted/received, and after the
last data is transmitted/received. Accordingly, regardless of the contents of the SBUSY1 output•SSTB1
output function selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than
the value set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the S STB1 output, regardless of the contents of the SBUSY1 output•SSTB1 output function
selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value
set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the combined output of S BUSY1 and SSTB1 as the signal for each of all transfer data
set, the transfer interval after completion of transmission/reception of the last data becomes 2
cycles longer than the value set by the automatic transfer interval set bits.
● When selecting an external clock, the set of automatic transfer interval becomes invalid.
● Set the transfer interval of each 1-byte data transfer as the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system clock from clock rising of the last
bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 17 cycles or more of internal system clock from clock rising of the
last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 27 cycles or more of internal system clock from clock rising of the
last bit of 1-byte data.
■ Set of serial I/O1 transfer counter
● Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer
counter.
● When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,
wait for 5 or more cycles of internal system clock before inputting the transfer clock to the serial
I/O1 clock pin.
■ Serial I/O initialization bit
A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O
initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.
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38B7 Group User’s Manual
APPENDIX
3.3 Notes on use
Table 3.3.1 SIO1CON3 (address 001C16) setting example selecting internal synchronous clock
Serial I/O1 control register
Internal synchronous clock
selection bits (b7 to b5)
0 0 0 : f(X IN ) / 4
3, SIO1CON3 (address 001C 16)
Automatic transfer interval set bits
(b4 to b0)
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 1 0 : 4 cycles of transfer clocks
0 0 0 1 1 : 5 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
Not using
FLDC
Not using Using gradation display
gradation
display mode
mode
Usable
Prohibited
Prohibited
Usable
Prohibited
Prohibited
Usable
Prohibited
Prohibited
Usable
Usable
Usable
0 0 1 : f(X IN ) / 8
Usable
Prohibited
Prohibited
Usable
Usable
Usable
0 1 0 : f(X IN ) / 16
Usable
Usable
Usable
Table 3.3.2 SIO1CON3 (address 001C16) setting example selecting external synchronous clock
Serial I/O1 control register 3,
“n” cycles of transfer clocks
SIO1CON3 (address 001C 16),
Automatic transfer interval set bits
Not using FLDC
Not using gradation display mode
Using gradation display mode
Transfer clock ✕ n cycles ≥ 5 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 17 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 27 cycles of internal system clock
3.3.4 Notes on serial I/O2
(1) Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit
to “0” (serial I/O2 disabled).
➂ Stop of transmit/receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit
and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to
“0” (serial I/O2 disabled) (refer to (1), ➀).
38B7 Group User’s Manual
3-19
APPENDIX
3.3 Notes on use
(2) Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3) S RDY2 output of reception side
When signals are output from the SRDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
Fig. 3.3.4 Sequence of setting serial I/O2 control register again
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38B7 Group User’s Manual
APPENDIX
3.3 Notes on use
(5) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.
(7) Setting procedure when serial I/O2 transmit interrupt is used
When setting the transmit enable bit to “1”, the serial I/O2 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled,
take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been
executed.
➃Set the serial I/O1 tranmit interrupt enable bit to “1” (enabled).
(8) Using TxD pin
The P65/TxD P-channel output disable bit of UART control register is valid in both cases: using as
a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P6 5/
TxD pin as an N-channel open-drain output.
Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after
completing transmission.
3.3.5 Notes on FLD controller
● Set a value of 03 16 or more to the Toff1 time set register.
● When displaying in the gradation display mode, select the 16 timing mode by the timing number control
bit (bit 4 of FLDC mode register (address 0EF4 16) = “0”).
38B7 Group User’s Manual
3-21
APPENDIX
3.3 Notes on use
3.3.6 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the V SS line
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN ) is 250 kHz or more
• Do not execute the STP instruction and WIT instruction
3.3.7 Notes on D-A converter
(1) PB 0/DA state at reset
The PB0/DA pin becomes a high-impedance state at reset.
(2) Connection with low-impedance load
If connecting a D-A output with a load having a low impedance, use an external buffer. It is because
the D-A converter circuit does not include a buffer.
(3) Usable voltage
Vcc must be 3.0 V or more when using the D-A converter.
3.3.8 Notes on PWM
● For PWM 0 output, “L” level is output first.
● After data is set to the PWM register (low-order) and the PWM register (high-order), PWM waveform
corresponding to new data is output from next repetitive cycle.
PWM0 output data
change
Modified data is output from next
repetitive cycle.
Fig. 3.3.5 PWM0 output
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38B7 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.9 Notes on watchdog timer
● The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that
watchdog timer does not underflow during this term by writing to the watchdog timer control register
(address 0EEE 16) once before executing the STP instruction, etc.
● Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register
(address 0EEE16), it cannot be programmed to “0” again. This bit becomes “0” after reset.
3.3.10 Notes on reset
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.7 V.
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.11 Each port state during “L” state of RESET pin
Table 3.3.3 shows a pin state during “L” state of RESET pin.
Table 3.3.3 Pin state during “L” state of RESET pin
Pin name
Pin state
P0, P2
P1, P3
Output port (with pull-down resistor)
Input port (with pull-down resistor)
P4, P5, P6 0 to P6 3
Input port (without pull-down resistor) (Note)
P6 4 to P6 7, P7, P8 0 to P83,
Input port (floating)
P9, PA, PB 0 to PB6
Note: Whether built-in pull-down resistors are connected or not can be specified in ordering mask ROM.
38B7 Group User’s Manual
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APPENDIX
3.3 Notes on use
3.3.12 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.6 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
(S)
(S)+1
Fig. 3.3.7 Sequence of PLP instruction execution
3-24
Stored PS
Fig. 3.3.8 Stack memory contents after PHP
instruction execution
38B7 Group User’s Manual
APPENDIX
3.3 Notes on use
(2) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.9 Status flag at decimal calculations
(3) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
38B7 Group User’s Manual
3-25
APPENDIX
3.3 Notes on use
3.3.13 Notes on CPU reprogramming mode
(1) Transfer the CPU reprogramming mode control program to the internal RAM before selecting the
CPU reprogramming mode, and then, execute it on the internal RAM. Additionally, when the subroutine
or stack operation instruction is used in the control program, make sure in order not to destroy the
control program transferred to the internal RAM through the stack area.
(2) Be careful of the instruction description (specifying address, and so on) because the CPU reprogramming
mode control program is transferred to the internal RAM and executed on the internal RAM.
(3) Write to the watchdog timer control register periodically in order not to generate the watchdog timer
interrupt by the CPU reprogramming mode control program (refer to “2.9 Watchdog timer”).
3.3.14 Notes on flash memory version
The CNV SS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has
the multiplexed function to be a programmable power source pin (VPP pin) as well.
To improve the noise margin, connect the CNV SS pin to V SS through 1 to 10 kΩ resistance.
Even when the wiring of the CNVSS pin of the mask ROM version is connected to Vss through this resistor,
that will not affect operation.
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38B7 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.15 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or V SS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pin INT or others, select the VCC
pin or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or VSS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
38B7 Group User’s Manual
3-27
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20 mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 3.4.1 Wiring for the RESET pin
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38B7 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
(2) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
Fig. 3.4.2 Wiring for clock I/O pins
(3) Wiring to CNVss pin
Connect the CNVss pin to the Vss pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNVss pin. If a
potential difference is caused by the noise between pins CNVss and Vss, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNV SS
CNV SS
VSS
VSS
N.G.
O.K.
Fig. 3.4.3 Wiring for CNVss pin
38B7 Group User’s Manual
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APPENDIX
3.4 Countermeasures against noise
(4) Wiring to V PP pin of flash memory version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
Vss pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
V SS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the flash memory version is the power source input pin for the built-in flash
memory. When programming/erasing in the built-in flash memory, the impedance of the VPP pin
is low to allow the electric current for writing/erasing flow into the flash memory. Because of this,
noise can enter easily. If noise enters the V PP pin, abnormal instruction codes or data are read
from the built-in flash memory, which may cause a program runaway.
Approximately
5 kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.4 Wiring for the VPP pin of the flash memory version
3.4.2 Connection of bypass capacitor across V SS line and V CC line
Connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the VCC pin.
AA
AA
AA
AA
AA
VCC
VSS
N.G.
AA
AA
AA
AA
AA
VCC
VSS
O.K.
Fig. 3.4.5 Bypass capacitor across the V SS line and the V CC line
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38B7 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the V SS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.6 Analog signal line and a resistor and a capacitor
38B7 Group User’s Manual
3-31
APPENDIX
3.4 Countermeasures against noise
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.7 Wiring for a large current signal line
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently
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APPENDIX
3.4 Countermeasures against noise
(3) Oscillator protection using V SS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
A A
AAA
AAA
A
A
AAA
A
A
AA
AA
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 V SS pattern on the underside of an oscillator
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.10 Setup for I/O ports
38B7 Group User’s Manual
3-33
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
≤0
Return
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
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38B7 Group User’s Manual
APPENDIX
3.5 Control registers
3.5 Control registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0 to 7, 9, A)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1216, 1416)
b
0
1
2
3
4
5
6
7
Name
Port Pi0
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Functions
●In output mode
Write • • • • • • • • Port latch
Read • • • • • • • • Port latch
●In input mode
Write • • • • • • • • Port latch
Read • • • • • • • • Value of pin
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.1 Structure of Port Pi (i =0–7, 9, A)
Port P8
b7 b6 b5 b4 b3 b2 b1 b0
Port P8
(P8: address 1016)
b
Name
0 Port P80
1 Port P81
2 Port P82
3 Port P83
Functions
●In output mode
Write • • • • • • • • Port latch
Read • • • • • • • • Port latch
●In input mode
Write • • • • • • • • Port latch
Read • • • • • • • • Value of pin
4 Nothing is arranged for these bits. When these
5 bits are read out, the contents are undefined.
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.2 Structure of Port P8
38B7 Group User’s Manual
3-35
APPENDIX
3.5 Control registers
Port PB
b7 b6 b5 b4 b3 b2 b1 b0
Port PB
(PB: address 1616)
b
0
1
2
3
4
5
6
7
Name
Functions
Port PB0
●In output mode
Port PB1
Write • • • • • • • • Port latch
Port PB2
Read • • • • • • • • Port latch
●In input mode
Port PB3
Write • • • • • • • • Port latch
Port PB4
Read • • • • • • • • Value of pin
Port PB5
Port PB6
Nothing is arranged for this bit. When this bit is
read out, the contents are undefined.
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.3 Structure of Port PB
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 1, 3 to 7, 9, A)
[Addresses 0316, 0716, 0916, 0B16, 0D16, 0F16, 1316, 1516]
b
Name
0 Port Pi direction
register
1
2
3
4
5
6
7
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Fig. 3.5.4 Structure of Port Pi direction register (i = 1, 3–7, 9, A)
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38B7 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8 direction register
(P8D: address 1116)
b
Name
Functions
0
2
0
3
4
5
6
7
0 : Port P80 input mode
1 : Port P80 output mode
0 : Port P81 input mode
1 : Port P81 output mode
0 : Port P82 input mode
1 : Port P82 output mode
0 : Port P83 input mode
1 : Port P83 output mode
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
At reset R W
0 Port P8 direction
register
1
0
0
0
0
0
0
Fig. 3.5.5 Structure of Port P8 direction register
Port PB direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port PB direction register
(PBD: address 1716)
b
Name
Functions
0 Port PB direction
register
1
0
2
0
3
4
5
6
7
0 : Port PB0 input mode
1 : Port PB0 output mode
0 : Port PB1 input mode
1 : Port PB1 output mode
0 : Port PB2 input mode
1 : Port PB2 output mode
0 : Port PB3 input mode
1 : Port PB3 output mode
0 : Port PB4 input mode
1 : Port PB4 output mode
0 : Port PB5 input mode
1 : Port PB5 output mode
0 : Port PB6 input mode
1 : Port PB6 output mode
Nothing is arranged for this bit. When this bit is
read out, the contents are undefined.
At reset R W
0
0
0
0
0
✕
0
✕ ✕
Fig. 3.5.6 Structure of Port PB direction register
38B7 Group User’s Manual
3-37
APPENDIX
3.5 Control registers
Serial I/O1 automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 1816)
b
Functions
0 • Indicates the low-order 8 bits (0016 to FF16) of
1 the address storing the start data on the serial
2 I/O automatic transfer RAM.
3 • Data is written into the latch and read from the
4 decrement counter.
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.7 Structure of Serial I/O1 automatic transfer data pointer
Serial I/O1 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1•SC11: address 1916)
b
Name
0 Serial transfer
selection bits
1
2 Serial I/O1
synchronous clock
selection bits
(PB3/SSTB1 pin
control bits)
3
Functions
b1b0
0 0: Serial I/O disabled
(Pins PB0–PB6 pins
are I/O ports.)
0 1: 8-bit serial I/O
1 0: Not available
1 1: Automatic transfer
serial I/O (8 bits)
b3b2
0 0: Internal synchronous
clock (PB3 pin is I/O
port.)
0 1: External synchronous
clock (PB3 pin is I/O
port.)
1 0: Internal synchronous
clock (PB3 pin is
SSTB1 output.)
1 1: Internal synchronous
clock (PB3 pin is
SSTB1 output.)
0
0
0
0
4 Serial I/O
initialization bit
5 Transfer mode
selection bit
0: Serial I/O initialization
1: Serial I/O enabled
0: Full-duplex
(transmit/receive) mode
(PB6 pin is SIN1 input.)
1: Transmit-only mode
(PB6 pin is I/O port.)
0
6 Transfer direction
selection bit
0: LSB first
1: MSB first
0
7 Serial I/O1 clock pin 0: SCLK11 (PB0/SCLK12 pin
selection bit
is I/O port.)
1: SCLK12 (PB4/SCLK11 pin
is I/O port.)
Fig. 3.5.8 Structure of Serial I/O1 control register 1
3-38
At reset R W
38B7 Group User’s Manual
0
0
APPENDIX
3.5 Control registers
Serial I/O1 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 • SC12: address 1A16)
b
Name
Functions
0 PB1/SRDY1 •
PB2/SBUSY1 pin
control bits
At reset R W
0
b3b2b1b0
1
2
3
4
5
0 0 0 0: PB1, PB2 pins are I/O ports.
0 0 0 1: Not used
0 0 1 0: PB1 pin is SRDY1 output; PB2 pin is
I/O port.
0 0 1 1: PB1 pin is SRDY1 output; PB2 pin is
I/O port.
0 1 0 0: PB1 pin is I/O port; PB2 pin is
SBUSY1 input.
0 1 0 1: PB1 pin is I/O port; PB2 pin is
SBUSY1 input.
0 1 1 0: PB1 pin is I/O port; PB2 pin is
SBUSY1 output.
0 1 1 1: PB1 pin is I/O port; PB2 pin is
SBUSY1 output.
1 0 0 0: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 0 0 1: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 0 1 0: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 0 1 1: PB1 pin is SRDY1 input; PB2 pin is
SBUSY1 output.
1 1 0 0: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
1 1 0 1: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
1 1 1 0: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
1 1 1 1: PB1 pin is SRDY1 output; PB2 pin is
SBUSY1 input.
SBUSY1 output •
0: Functions as signal for
SSTB1 output
each 1-byte
function selection bit 1: Functions as signal for
(Valid in serial I/O1
each transfer data set
automatic transfer
mode)
Serial transfer
0: Serial transfer
status flag
completed
1: Serial transfer inprogress
0
0
0
0
0
6 SOUT1 pin control
0: Output active
bit (when serial data 1: Output high-impedance
is not transferred)
0
7 PB5/SOUT1 P-channel 0: CMOS 3 state (Poutput disable bit
channel output is valid.)
1: N-channel open-drain
output (P-channel output
is invalid.)
0
Fig. 3.5.9 Structure of Serial I/O1 control register 2
38B7 Group User’s Manual
3-39
APPENDIX
3.5 Control registers
Serial I/O1 register/Transfer counter
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 register/Transfer counter
(SIO1: address 1B16)
b
Name
Functions
At reset R W
•At function as serial I/O1
Undefined
0 •In 8-bit serial I/O
register:
mode:
This register becomes the
Serial I/O1 register
shift register to perform
1
Undefined
serial transmit/reception.
•In automatic transfer
Set transmit data to this
serial I/O mode:
register.
2 Transfer counter
Undefined
The serial transfer is started
by writing the transmit data.
3
4
5
6
7
•At function as transfer
counter:
Set (transfer byte number –
1) to this register.
When selecting an internal
clock, the automatic
transfer is started by writing
the transmit data.
(When selecting an external
clock, after writing a value
to this register, wait for 5 or
more cycles of the internal
system clock before
inputting the transfer clock
to the SCLK1 pin.)
Fig. 3.5.10 Structure of Serial I/O1 register/Transfer counter
3-40
38B7 Group User’s Manual
Undefined
Undefined
Undefined
Undefined
Undefined
APPENDIX
3.5 Control registers
Serial I/O1 control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 • SC13: address 1C16)
b
Name
Functions
0 Automatic transfer b4b3b2b1b0
0 0 0 0 0: 2 cycles of
interval set bits
transfer clock
(valid only when
0 0 0 0 1: 3 cycles of
1 selecting internal
transfer clock
synchronous clock)
to
1
1
1
1
0:
32
cycles of
2
transfer clock
1 1 1 1 1: 33 cycles of
3
transfer clock
4
5 Internal
synchronous clock
selection bits
6
7
At reset R W
0
0
0
0
Data is written into the
latch and read from the
decrement counter.
0
b7b6b5
0
0 0 0 : f(XIN)/4 or f(XCIN)/8
0 0 1 : f(XIN)/8 or
f(XCIN)/16
0 1 0 : f(XIN)/16 or
f(XCIN)/32
0 1 1 : f(XIN)/32 or
f(XCIN)/64
1 0 0 : f(XIN)/64 or
f(XCIN)/128
1 0 1 : f(XIN)/128 or
f(XCIN)/256
1 1 0 : f(XIN)/256 or
f(XCIN)/512
1 1 1 : Not used
0
0
Fig. 3.5.11 Structure of Serial I/O1 control register 3
38B7 Group User’s Manual
3-41
APPENDIX
3.5 Control registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 1D16)
b
Name
Functions
0 BRG count source
selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or
f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or
f(XCIN)/4
0
1 Serial I/O2
synchronous clock
selection bit
(SCS)
•In clock synchronous
mode
0: BRG output/4
1: External clock input
•In UART mode
0: BRG output/16
1: External clock input/16
0
2 SRDY2 output
enable bit (SRDY)
0: P67 pin operates as
normal I/O pin
1: P67 pin operates as
SRDY2 output pin
0
0: When transmit buffer
3 Transmit interrupt
source selection bit
has emptied
(TIC)
1: When transmit shift
operation is completed
0
4 Transmit enable bit
(TE)
5 Receive enable bit
(RE)
6 Serial I/O2 mode
selection bit (SIOM)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
0
7 Serial I/O2 enable
bit (SIOE)
0: Serial I/O2 disabled
(pins P64–P67 operate
as normal I/O pins)
1: Serial I/O2 enabled
(pins P64–P67 operate
as serial I/O pins)
0
Fig. 3.5.12 Structure of Serial I/O2 control register
3-42
At reset R W
38B7 Group User’s Manual
0
0
APPENDIX
3.5 Control registers
Serial I/O2 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 status register
(SIO2STS: address 1E16)
b
Name
0 Transmit buffer
empty flag (TBE)
1 Receive buffer full
flag (RBF)
2 Transmit shift
register shift
completion flag
(TSC)
Functions
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
3 Overrun error flag
(OE)
4 Parity error flag
(PE)
0: No error
1: Overrun error
0: No error
1: Parity error
5 Framing error flag 0: No error
1: Framing error
(FE)
6 Summing error flag 0: (OE) U (PE) U (FE) = 0
(SE)
1: (OE) U (PE) U (FE) = 1
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
At reset R W
0
0
0
0
0
0
0
1
Fig. 3.5.13 Structure of Serial I/O2 status register
Serial I/O2 transmit/receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 transmit/receive buffer register
(TB/RB: address 1F16)
b
Functions
0 This is the buffer register which is used to write
transmit data or to read receive data.
1
• At write : The value is written to the transmit
buffer register. The value cannot be
2
written to the receive buffer register.
3 • At read : The contents of the receive buffer
register is read out. When a
4
character bit length is 7 bits, the
5
MSB of data stored in the receive
buffer is “0”. The contents of the
6
transmit buffer register cannot be
7
read out.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.14 Structure of Serial I/O2 transmit/receive buffer register
38B7 Group User’s Manual
3-43
APPENDIX
3.5 Control registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3 to 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
0 • Set timer i count value.
1 • The value set in this register is written to both
2 the timer i and the timer i latch at one time.
3 • When the timer i is read out, the count value
4 of the timer i is read out.
5
6
7
1
1
1
1
1
1
1
1
Fig. 3.5.15 Structure of Timer i
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
At reset R W
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 the timer 2 and the timer 2 latch at one time.
3 • When the timer 2 is read out, the count value
4 of the timer 2 is read out.
5
6
7
1
0
0
0
0
0
0
0
Fig. 3.5.16 Structure of Timer 2
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register
(PWMCON: address 2616)
b
Name
Functions
0: I/O port
0 P96/PWM0 output
selection bit
1: PWM0 output
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read out,
3 the contents are “0”.
4
5
6
7
Fig. 3.5.17 Structure of PWM control register
3-44
38B7 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
Functions
0 • In timer 6 PWM1 mode
1
2
3
4
5
6
At reset R W
Undefined
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
Fig. 3.5.18 Structure of Timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
Name
0
Timer 1 count stop
bit
Timer 2 count stop
bit
Timer 1 count
source selection
bits
1
2
3
4 Timer 2 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: Timer 1 underflow
0 1: f(XCIN)
1 0: External count input
CNTR0
1 1: Not available
0: I/O port
6 Timer 1 output
selection bit (P75) 1: Timer 1 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 3.5.19 Structure of Timer 12 mode register
38B7 Group User’s Manual
3-45
APPENDIX
3.5 Control registers
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
Name
0
Timer 3 count stop
bit
Timer 4 count stop
bit
Timer 3 count
source selection
bits
1
2
3
4 Timer 4 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1
1 1: Not available
0: I/O port
6 Timer 3 output
selection bit (P76) 1: Timer 3 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 3.5.20 Structure of Timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
Name
0
Timer 5 count stop
bit
Timer 6 count stop
bit
Timer 5 count
source selection bit
Timer 6 operation
mode selection bit
Timer 6 count
source selection
bits
1
2
3
4
5
6 Timer 6 (PWM)
output selection bit
(P74)
Functions
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0: f(XIN)/8 or f(XCIN)/16
1: Timer 4 underflow
0: Timer mode
1: PWM mode
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 3.5.21 Structure of Timer 56 mode register
3-46
At reset R W
38B7 Group User’s Manual
0
0
0
0
0
0
APPENDIX
3.5 Control registers
D-A conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-A conversion register
(DA: address 2B16)
b
Functions
At reset R W
0 •This is a register for set of D-A conversion
output value.
1 • D-A conversion is performed automatically by
setting a value in this register.
2
0
3
0
4
0
5
0
6
0
7
0
0
0
Fig. 3.5.22 Structure of D-A conversion register
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-order, high-order)
(TXL, TXH: addresses 2C16, 2D16)
b
Functions
0 • Set timer X count value.
1 • When the timer X write control bit of the timer
X mode register 1 is “0”, the value is written to
2
timer X and the latch at one time.
3
When the timer X write control bit of the timer
X mode register 1 is “1”, the value is written
4
only to the latch.
5
• The timer X count value is read out by reading
6
this register.
7
At reset R W
1
1
1
1
1
1
1
1
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes.
2: Read both registers in order of TXH and TXL following.
3: Write both registers in order of TXL and TXH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 3.5.23 Structure of Timer X (low-order, high-order)
38B7 Group User’s Manual
3-47
APPENDIX
3.5 Control registers
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1: address 2E16)
b
Name
0 Timer X write
control bit
Functions
0 : Write value in latch and
counter
1 : Write value in latch only
0
b2 b1
1 Timer X count
0 0: f(XIN)/2 or f(XCIN)/4
source selection bits 0 1: f(XIN)/8 or f(XCIN)/16
1 0: f(XIN)/64 or f(XCIN)/128
2
1 1: Not available
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
4 Timer X operating
mode bits
5
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width
measurement mode
6 CNTR2 active edge 0 : •Start from “H” output in
pulse output mode
switch bit
•Count at rising edge in
event counter mode
•Measure “H” pulse
width in pulse width
measurement mode
1 : •Start from “L” output in
pulse output mode
•Count at falling edge in
event counter mode
•Measure “L” pulse
width in pulse width
measurement mode
7 Timer X stop
control bit
0 : Count operating
1 : Count stop
Fig. 3.5.24 Structure of Timer X mode register 1
3-48
At reset R W
38B7 Group User’s Manual
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 2
(TXM2: address 2F16)
b
Name
Functions
0 Real time port control
bit (P94)
1 Real time port control
bit (P95)
2 P94 data for real time
port
3 P95 data for real time
port
At reset R W
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: “L” output
1: “H” output
0
0: “L” output
1: “H” output
0
4 Nothing is arranged for these bits. These are
5 write disabled bits. When these bits are read
6 out, the contents are “0”.
7
0
0
0
0
0
Fig. 3.5.25 Structure of Timer X mode register 2
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination register
(IID: address 3016)
b
Functions
0 • This register stores a value which is obtained
by counting a following interval with the
1
counter sampling clock.
2
Rising interval
3
Falling interval
Both edges interval (Note)
4
(Selected by interrupt edge selection register)
5
• Read exclusive register
6
7
At reset R W
0
0
0
0
0
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) of
the interrupt interval determination control register is “00”, the
both-sided edge detection function cannot be used.
Fig. 3.5.26 Structure of Interrupt interval determination register
38B7 Group User’s Manual
3-49
APPENDIX
3.5 Control registers
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination control register
(IIDCON: address 3116)
b
Name
Functions
At reset R W
0: Stopped
0 Interrupt interval
determination circuit 1: Operating
operating selection
bit
0
1 Counter sampling
clock selection bit
2 Noise filter
sampling clock
3 selection bits (INT2)
0: f(XIN)/128 or f(XCIN)
1: f(XIN)/256 or f(XCIN)/2
0
b3 b2
0
4 One-sided/bothsided edge
detection selection
bit
0 0: Filter is not used.
0 1: f(XIN)/32 or f(XCIN)
1 0: f(XIN)/64 or f(XCIN)/2
1 1: f(XIN)/128 or f(XCIN)/4
0: One-sided edge
detection
1: Both-sided edge
detection (Note)
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
0
0
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) is
“00”, the both-sided edge detection function cannot be used.
Fig. 3.5.27 Structure of Interrupt interval determination control register
3-50
38B7 Group User’s Manual
APPENDIX
3.5 Control registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
3
Functions
b3 b2 b1 b0
0 0 0 0: PA0/AN0
0 0 0 1: PA1/AN1
0 0 1 0: PA2/AN2
0 0 1 1: PA3/AN3
0 1 0 0: PA4/AN4
0 1 0 1: PA5/AN5
0 1 1 0: PA6/AN6
0 1 1 1: PA7/AN7
1 0 0 0: P90/SIN3/AN8
1 0 0 1: P91/SOUT3/AN9
1 0 1 0: P92/SCLK3/AN10
1 0 1 1: P93/SRDY3/AN11
1 1 0 0: P94/RTP1/AN12
1 1 0 1: P95/RTP0/AN13
1 1 1 0: P96/PWM0/AN14
1 1 1 1: P97/BUZ02/AN15
At reset R W
0
0
0
0
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
1
0: DA output disabled
6 DA output enable
bit
1: DA output enabled
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
Fig. 3.5.28 Structure of AD/DA control register
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
0
1
2
3
4
5
6
7
Functions
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
Undefined
Note: Do not read this register during A-D conversion.
Fig. 3.5.29 Structure of A-D conversion register (low-order)
38B7 Group User’s Manual
3-51
APPENDIX
3.5 Control registers
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
Functions
0 This is A-D conversion result (high-order 8 bits) stored
1 bits. This is read exclusive register.
2
3
4
5
6
7
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 3.5.30 Structure of A-D conversion register (high-order)
PWM register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (high-order)
(PWMH: address 3516)
b
Functions
0 • High-order 8 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch each sub-period cycle (64 µs).
(At f(XIN) = 4 MHz)
2
• When this register is read out, the value of the
3
PWM register (high-order) is read out.
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Fig. 3.5.31 Structure of PWM register (high-order)
3-52
At reset R W
38B7 Group User’s Manual
Undefined
Undefined
Undefined
APPENDIX
3.5 Control registers
PWM register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (low-order)
(PWML: address 3616)
b
Functions
At reset R W
0 • Low-order 6 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch at each PWM cycle period
(4096 µs).
2
(At f(XIN) = 4 MHz)
3 • When this register is read out, the value of the
PWM latch (low-order 6 bits) is read out.
4
Undefined
5
Undefined
6 Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “0”.
7 • This bit indicates whether the transfer to the
PWM latch is completed.
0: Transfer is completed
1: Transfer is not completed
• This bit is set to “1” at writing.
Undefined
Undefined
Undefined
Undefined
Undefined
✕
Undefined
✕
Fig. 3.5.32 Structure of PWM register (low-order)
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator
(BRG: address 3716)
b
Functions
At reset R W
0 • Bit rate of the serial transfer is determined.
• This is the 8-bit counter and has the reload
1
register.
The count source is divided by n+1 owing to
2
specifying a value n.
3
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.33 Structure of Baud rate generator
38B7 Group User’s Manual
3-53
APPENDIX
3.5 Control registers
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 3816)
b
Name
Functions
0
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length
selection bit (STPS)
P65/TxD P-channel
output disable bit
(POFF)
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0
0: CMOS output (in output
mode)
1: N-channel open-drain
output (in output mode)
0
1
2
3
4
0
0
0
5 BRG clock switch bit 0: XIN or XCIN/2 (depending
on internal system clock)
1: XCIN
6 Serial I/O2 clock
0: SCLK21 (P67/SCLK22 pin is
used as I/O port or SRDY2
I/O pin selection bit
output pin.)
1: SCLK22 (P66/SCLK21 pin is
used as I/O port.)
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
Fig. 3.5.34 Structure of UART control register
3-54
At reset R W
38B7 Group User’s Manual
0
APPENDIX
3.5 Control registers
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916)
b
Name
Functions
0 INT3/serial I/O2
transmit interrupt
switch bit
0: INT3 intrrupt
1: Serial I/O2 transmit
interrupt
0:
INT
4 interrupt
1 INT4/A-D
conversion interrupt 1: A-D conversion intrerrupt
switch bit
0: INT1 intrrupt
2 INT1/serial I/O3
interrupt switch bit 1: Serial I/O3 interrupt
3 Nothing is arranged for these bits. These are write
4 disabled bits. When these bits are read out, the
contents are “0”.
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.35 Structure of Interrupt source switch register
38B7 Group User’s Manual
3-55
APPENDIX
3.5 Control registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE : address 3A16)
b
0
1
2
3
4
5
6
7
Name
Functions
INT0 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
INT1 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
INT2 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
INT3 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
INT4 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
CNTR0 pin edge
0 : Rising edge count
switch bit
1 : Falling edge count
CNTR1 pin edge
0 : Rising edge count
1 : Falling edge count
switch bit
Fig. 3.5.36 Structure of Interrupt edge selection register
3-56
38B7 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
Fix
this bit to “1”.
3
4 Port Xc switch bit
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bit
7 Internal system
clock selection bit
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
At reset R W
0
0
0
1
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
1: Stopped
0
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
1
0
0
Note: B6, b7 function in the CPU reprogramming mode is described below.
6 Main clock division
ratio selection bits
7
b7 b6
0 0: φ = f(XIN) (high-speed
mode)
0 1: φ = f(XIN)/4 (middlespeed mode)
1 0: φ = f(XCIN)/2 (lowspeed mode)
1 1: Not available
1
0
Fig. 3.5.37 Structure of CPU mode register
38B7 Group User’s Manual
3-57
APPENDIX
3.5 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
0 INT0 interrupt
request bit
Functions
0
✽
1 INT1/serial I/O3
0 : No interrupt request
interrupt request bit
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.38 Structure of Interrupt request register 1
3-58
At reset R W
0 : No interrupt request
issued
1 : Interrupt request issued
38B7 Group User’s Manual
APPENDIX
3.5 Control registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
Timer
6
interrupt
0 : No interrupt request issued
2
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.39 Structure of Interrupt request register 2
38B7 Group User’s Manual
3-59
APPENDIX
3.5 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
Timer
X interrupt
4
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
Fig. 3.5.40 Structure of Interrupt control register 1
3-60
At reset R W
0 INT0 interrupt
enable bit
1 INT1/serial I/O3
interrupt enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
38B7 Group User’s Manual
0
0
0
0
APPENDIX
3.5 Control registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit
1 Timer 5 interrupt
enable bit
2 Timer 6 interrupt
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/Serial I/O2
transmit interrupt
enable bit
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
At reset R W
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Fig. 3.5.41 Structure of Interrupt control register 2
38B7 Group User’s Manual
3-61
APPENDIX
3.5 Control registers
Serial I/O3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O3 control register
(SIO3CON: address 0EEC16)
b
Name
Functions
At reset R W
0 Internal synchronous b2b1b0
clock selection bits 000: f(XIN)/4 or f(XCIN)/8
001: f(XIN)/8 or f(XCIN)/16
010: f(XIN)/16 or f(XCIN)/32
1
011: f(XIN)/32 or f(XCIN)/64
110: f(XIN)/64 or
f(XCIN)/128
2
111: f(XIN)/128 or
f(XCIN)/256
0
3 Serial I/O3 port
selection bit
(P91, P92)
0
4
0
5
6
7
0: I/O port
1: SOUT3, SCLK3 signal
output
0: I/O port
SRDY3 output
1: SRDY3 signal output
selection bit (P93)
0:
LSB first
Transfer direction
1: MSB first
selection bit
Synchronous clock 0: External clock
selection bit
1: Internal clock
P91/SOUT3
0: CMOS output (in output
P-channel output
mode)
disable bit (P91)
1: N-channel open drain
output (in output mode)
0
0
0
0
0
Fig. 3.5.42 Structure of Serial I/O3 control register
Serial I/O3 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O3 register
(SIO3: address 0EED16)
b
Functions
This
isserial
the buffer
•In
8-bit
I/O register which is used to write
transmit data or to read receive data.
mode:
When
an internal clock, the serial
Serial selecting
I/O1 register
transfer is started by writing this register.
0
1
2
3
4 •In automatic transfer
serial I/O mode:
5 Transfer counter
6
7
Fig. 3.5.43 Structure of Serial I/O3 register
3-62
38B7 Group User’s Manual
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
APPENDIX
3.5 Control registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 0EEE16)
b
Name
Functions
0 Watchdog timer H
1 (high-order 6 bits of reading exclusive)
2
3
4
5
6 STP instruction
0: STP instruction enabled
disable bit
1: STP instruction disabled
7 Watchdog timer H
0: Watchdog timer L
count source
underflow
selection bit
1: f(XIN)/8 or f(XCIN)/16
At reset R W
1
1
1
1
1
1
0
0
Fig. 3.5.44 Structure of Watchdog timer control register
Pull-up control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 3
(PULL3: address 0EEF16)
b
0
1
2
3
4
5
6
7
Name
Ports PA0, PA1
pull-up control
Ports PA2, PA3
pull-up control
Ports PA4, PA5
pull-up control
Ports PA6, PA7
pull-up control
Ports PB0, PB1
pull-up control
Ports PB2, PB3
pull-up control
Ports PB4, PB5
pull-up control
Ports PB6
pull-up control
Functions
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.45 Structure of Pull-up control register 3
38B7 Group User’s Manual
3-63
APPENDIX
3.5 Control registers
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1
(PULL1: address 0EF016)
b
Name
Functions
0: No pull-up
0 Ports P64, P65
1: Pull-up
pull-up control
0: No pull-up
1 Ports P66, P67
1: Pull-up
pull-up control
0: No pull-up
2 Ports P70, P71
1: Pull-up
pull-up control
0: No pull-up
3 Ports P72, P73
pull-up control
1: Pull-up
0: No pull-up
4 Ports P74, P75
pull-up control
1: Pull-up
Ports
P7
6
,
P7
7
0: No pull-up
5
pull-up control
1: Pull-up
6 Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
7 out, the contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.46 Structure of Pull-up control register 1
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2
(PULL2: address 0EF116)
b
Name
Functions
0 Ports P80, P81 pull- 0: No pull-up
1: Pull-up
up control
1 Ports P82, P83 pull- 0: No pull-up
1: Pull-up
up control
2 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
3 Ports P90, P91 pull- 0: No pull-up
up control
1: Pull-up
4 Ports P92, P93 pull- 0: No pull-up
1: Pull-up
up control
5 Ports P94, P95 pull- 0: No pull-up
1: Pull-up
up control
6 Ports P96, P97 pull- 0: No pull-up
up control
1: Pull-up
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.47 Structure of Pull-up control register 2
3-64
38B7 Group User’s Manual
APPENDIX
3.5 Control registers
Port P0 digit output set switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 digit output set switch register
(P0DOR: address 0EF216)
b
0
1
2
3
4
5
6
7
Name
Port P00 FLD/Digit
switch bit
Port P01 FLD/Digit
switch bit
Port P02 FLD/Digit
switch bit
Port P03 FLD/Digit
switch bit
Port P04 FLD/Digit
switch bit
Port P05 FLD/Digit
switch bit
Port P06 FLD/Digit
switch bit
Port P07 FLD/Digit
switch bit
Functions
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.48 Structure of Port P0 digit output set switch register
Port P2 digit output set switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 digit output set switch register
(P2DOR: address 0EF316)
b
Name
0 Port P20 FLD/Digit
switch bit
1 Port P21 FLD/Digit
switch bit
2 Port P22 FLD/Digit
switch bit
3 Port P23 FLD/Digit
switch bit
4 Port P24 FLD/Digit
switch bit
5 Port P25 FLD/Digit
switch bit
6 Port P26 FLD/Digit
switch bit
Port
P27 FLD/Digit
7
switch bit
Functions
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
0: FLD output
1: Digit output
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.49 Structure of Port P2 digit output set switch register
38B7 Group User’s Manual
3-65
APPENDIX
3.5 Control registers
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
b
Name
Functions
At reset R W
0 Automatic display
control bit
0 : General-purpose mode
1 : Automatic display
mode
0
1 Display start bit
0 : Display stopped
1 : Display in progress (display
starts by writing “1”)
0
2 Tscan control bits
b3 b2
0
3
0 0 : FLD digit interrupt
(at rising edge of each
digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
1 1 : 3 ✕ Tdisp
FLD blanking interrupt (at
falling edge of last digit)
0
4 Timing number
control bit
0 : 16 timing mode
1 : 32 timing mode (Note 2)
0
5 Gradation display
mode selection
control bit
6 Tdisp counter count
source selection bit
0 : Not selected
1 : Selected (Notes 1, 2)
0
0 : f(XIN)/16
1 : f(XIN)/64
0
0 : Drivability strong
1 : Drivability weak
0
7 High-breakdown
voltage port drivability selection bit
Notes 1: When the gradation display mode is selected, the number of
timing is max. 16 timing. (Set “0” to the timing number control
bit (b4).)
2: When switching the timing number control bit (b4) or the
gradation display mode selection control bit (b5), set “0” to the
display start bit (b1) (display stop state) before that.
Fig. 3.5.50 Structure of FLDC mode register
3-66
38B7 Group User’s Manual
APPENDIX
3.5 Control registers
Tdisp time set register
b7 b6 b5 b4 b3 b2 b1 b0
Tdisp time set register
(TDISP: address 0EF516)
b
Functions
0
•Set the Tdisp time.
•When a value n is written to this register, Tdisp
time is expressed as Tdisp = (n + 1) ✕ count
source.
•When reading this register, the value in the
counter is read out.
0
(Example)
When the following condition is satisfied, Tdisp
becomes 804 µs {(200 + 1) ✕ 4 µs};
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source. )
•Tdisp time set register = 200 (C816).
0
1
2
3
4
At reset R W
0
0
0
5
0
6
0
7
0
Fig. 3.5.51 Structure of Tdisp time set register
38B7 Group User’s Manual
3-67
APPENDIX
3.5 Control registers
Toff1 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff1 time set register
(TOFF1: address 0EF616)
b
0
1
2
3
4
5
Functions
•Set the Toff1 time.
•When a value n1 is written to this register,
Toff1 time is expressed as Toff1 = n1 ✕ count
source.
(Example)
When the following condition is satisfied, Toff1
becomes 120 µs (= 30 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff1 time set register = 30 (1E16).
At reset R W
1
1
1
1
1
1
6
1
7
1
Note: Set value of 0316 or more.
Fig. 3.5.52 Structure of Toff1 time set register
Toff2 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff2 time set register
(TOFF2: address 0EF716)
b
Functions
0
•Set the Toff2 time.
•When a value n2 is written to this register,
Toff2 time is expressed as Toff2 = n2 ✕ count
source.
However, setting of Toff2 time is valid only for
the FLD port which is satisfied the following;
•gradation display mode
•value of FLD automatic display RAM (in
gradation display mode) = “1” (dark display).
1
(Example)
When the following condition is satisfied, Toff2
becomes 720 µs (= 180 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff2 time set register = 180 (B416).
1
1
2
3
4
5
6
7
At reset R W
1
1
1
1
1
1
Note: When the Toff2 control bit (b7) of the port P8FLD output control
register (address 0EFC16) is set to “1”, set value of 0316 or
more to the Toff2 control register.
Fig. 3.5.53 Structure of Toff2 time set register
3-68
38B7 Group User’s Manual
APPENDIX
3.5 Control registers
FLD data pointer/FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0
FLD data pointer/FLD data pointer reload register
(FLDDP: address 0EF816)
b
Functions
0
The start address of each data of FLD ports P6,
P5, P4, P3, P1, P0, and P2, which is
transferred from FLD automatic display RAM, is
set to this register.
The start address becomes the address adding
the value set to this register into the last data
address of each FLD port.
Set a value of (timing number – 1) to this
register.
1
2
3
4
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
The value which is set to this address is written
to the FLD data pointer reload register.
Undefined
When reading data from this address, the value
in the FLD data pointer is read.
Undefined
When bits 5 to 7 of this register is read, “0” is
always read.
Undefined
Fig. 3.5.54 Structure of FLD data pointer/FLD data pointer reload register
Port P4FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P4FLD/port switch register
(P4FPR: address 0EF916)
b
Name
0 Port P40 FLD/port
switch bit
1 Port P41 FLD/port
switch bit
2 Port P42 FLD/port
switch bit
3 Port P43 FLD/port
switch bit
4 Port P44 FLD/port
switch bit
5 Port P45 FLD/port
switch bit
6 Port P46 FLD/port
switch bit
7 Port P47 FLD/port
switch bit
Functions
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.55 Structure of Port P4FLD/port switch register
38B7 Group User’s Manual
3-69
APPENDIX
3.5 Control registers
Port P5FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5FLD/port switch register
(P5FPR: address 0EFA16)
b
0
1
2
3
4
5
6
7
Name
Port P50 FLD/port
switch bit
Port P51 FLD/port
switch bit
Port P52 FLD/port
switch bit
Port P53 FLD/port
switch bit
Port P54 FLD/port
switch bit
Port P55 FLD/port
switch bit
Port P56 FLD/port
switch bit
Port P57 FLD/port
switch bit
Functions
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.56 Structure of Port P5FLD/port switch register
Port P6FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6FLD/port switch register
(P6FPR: address 0EFB16)
b
Name
0 Port P60 FLD/port
switch bit
Port
P61 FLD/port
1
switch bit
2 Port P62 FLD/port
switch bit
3 Port P63 FLD/port
switch bit
4 Port P64 FLD/port
switch bit
5 Port P65 FLD/port
switch bit
6 Port P66 FLD/port
switch bit
7 Port P67 FLD/port
switch bit
Functions
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
0 : Normal port
1 : FLD port
Fig. 3.5.57 Structure of Port P6FLD/port switch register
3-70
38B7 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
FLD output control register
(FLDCON : address 0EFC16)
b
Name
Functions
At reset R W
0 : Output normally
0 P64–P67 FLD
1 : Reverse output
output reverse bit
1 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0 : Operating normally
2 P64–P67 Toff
1 : Toff invalid
invalid bit
0
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
4 P73 dimmer output 0 : Ordinary port
control bit
1 : Dimmer output
5 Generating/Not of
0 : Toff section not
generated
CMOS port Toff
section selection bit 1 : Toff section generated
6 Generating/Not of
0 : Toff section not
high-breakdown
generated
1 : Toff section generated
voltage port Toff
section selection bit
7 Toff2 SET/RESET 0 : Toff2 RESET; Toff1
SET
switch bit
1 : Toff2 SET; Tdisp
RESET
0
0
0
0
0
0
0
Fig. 3.5.58 Structure of FLD output control register
38B7 Group User’s Manual
3-71
APPENDIX
3.5 Control registers
Buzzer output control register
b7 b6 b5 b4 b3 b2 b1 b0
Buzzer output control register
(BUZCON: address 0EFD16)
b
Name
0 Output frequency
selection bits
1
2 Output port
selection bits
3
Functions
0
0 0: 1 kHz (f(XIN)/4096)
0 1: 2 kHz (f(XIN)/2048)
1 0: 4 kHz (f(XIN)/1024)
1 1: Not available
0
b3b2
0
0 0: P77 and P97 function
as ordinary ports.
0 1: P77/BUZ01 functions as
a buzzer output.
1 0: P97/BUZ02/AN15
functions as a buzzer
output.
1 1: Not available
4 Buzzer output
ON/OFF bit
0: Buzzer output OFF (“0”
output)
1: Buzzer output ON
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
Fig. 3.5.59 Structure of Buzzer output control register
3-72
At reset R W
b1b0
38B7 Group User’s Manual
0
0
0
0
0
APPENDIX
3.5 Control registers
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Flash memory control register
(FCON: address 0EFE16)
b
Name
Functions
0 CPU reprogramming 0: CPU reprogramming
mod is invalid. (Normal
mode select bit
operation mode)
(Note)
1: When applying 0 V or
VPPL to CNVSS/VPP pin,
CPU reprogramming
mode is invalid. When
applying VPPH to
CNVSS/VPP pin, CPU
reprogramming mode is
valid.
1 Erase/Program
busy flag
0: Erase and program are
completed or not have
been executed.
1: Erase/program is being
executed.
At reset R W
0
0
2 CPU reprogramming 0: CPU reprogramming
mode is invalid.
mode monitor flag
1: CPU reprogramming
mode is valid.
0
3 Fix this bit to “0”.
4 Erase/Program area b5 b4
0 0: Addresses 100016 to
select bits
FFFF16 (total 60 Kbytes)
0 1: Addresses 100016 to
7FFF16 (total 28 Kbytes)
5
1 0: Addresses 800016 to
FFFF16 (total 32 Kbytes)
1 1: Not available
6 Fix this bit to “0”.
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
0
Note: Bit 0 can be reprogrammed only when 0 V is applied to the
CNVSS/VPP pin.
Fig. 3.5.60 Structure of Flash memory control register
38B7 Group User’s Manual
3-73
APPENDIX
3.5 Control registers
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Flash command register
(FCMD: address 0EFF16)
b
Functions
At reset R W
0
0 Writing of software command
1 <Software command name> <Command code>
0
“0016”
0
2 •Read command
“4016”
0
3 •Program command
4 •Program verify command “C016”
0
•Erase command
“2016” + “2016”
5 •Erase verify command
0
“A016”
6 •Reset command
0
“FF16” + “FF16”
7
0
Note: The flash command register is write exclusive register.
Fig. 3.5.61 Structure of Flash command register
3-74
38B7 Group User’s Manual
APPENDIX
3.6 Package outline
3.6 Package outline
100P6S-A
MMP
EIAJ Package Code
QFP100-P-1420-0.65
Plastic 100pin 14✕20mm body QFP
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
81
1
b2
100
ME
HD
D
80
I2
Recommended Mount Pad
E
30
HE
Symbol
51
50
A
L1
c
A2
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
y
b
x
M
A1
F
e
L
Detail F
38B7 Group User’s Manual
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.65
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
0.1
–
–
0°
10°
–
–
–
0.35
1.3
–
–
14.6
–
–
20.6
–
–
3-75
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
ASL
C←
7
0
←0
IMM
# OP n
A
# OP n
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
06 5
2
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
#
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13
+ 4
20i
2
17
+ 5
20i
3
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03
+ 4
20i
2
07
+ 5
20i
3
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
BIT
A
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
3-76
V
M
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
38B7 Group User’s Manual
24 3
2
APPENDIX
3.7 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
7
5
4
3
2
1
0
N V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
38B7 Group User’s Manual
#
6
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
3-77
APPENDIX
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
00 7
1
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
CLC
C←0
This instruction clears C.
18 2
1
CLD
D←0
This instruction clears D.
D8 2
1
CLI
I←0
This instruction clears I.
58 2
1
CLT
T←0
This instruction clears T.
12 2
1
CLV
V←0
This instruction clears V.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
A
# OP n
BIT, A
# OP n
2
1B
+
20i
C9 2
38B7 Group User’s Manual
# OP n
BIT, ZP
# OP n
#
1F
+ 5
20i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
2
__
3-78
ZP
1A 2
1
APPENDIX
3.7 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
3
38B7 Group User’s Manual
3-79
APPENDIX
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's complement of the remainder is pushed onto the stack.
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
–M
M(X) ← M(X) V
49 2
A
# OP n
BIT, A
# OP n
2
ZP
# OP n
BIT, ZP
# OP n
45 3
2
E6 5
2
A5 3
2
3C 4
3
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (AD H, ADL)
PCH ← M (ADH, AD L + 1)
If addressing mode is ZP, IND
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
LDM
M ← nn
This instruction loads the immediate value in
M.
LDX
X←M
This instruction loads the contents of M in X.
A2 2
2
A6 3
2
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
2
A4 3
2
3-80
3A 2
38B7 Group User’s Manual
A9 2
2
1
#
APPENDIX
3.7 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
7
#
E2 16 2
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
B5 4
2
B6 4
B4 4
2
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
AC 4
41 6
6C 5
3 B9 5
3
3 BC 5
3
BE 5
3
3 B2 4
2
02 7
2
2 51 6
2
22 5
A1 6
2 B1 6
3
3
38B7 Group User’s Manual
2
2
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
3-81
APPENDIX
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
This instruction multiply Accumulator with the
memory specified by the Zero Page X address
mode and stores the high-order byte of the result on the Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
1
# OP n
BIT, ZP
# OP n
46 5
2
05 3
2
1
09 2
2
48 3
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
82 8
2
0
←C ←
RRF
7
→
3-82
# OP n
ZP
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
7
C→
RTS
BIT, A
M(S) ← A
S←S–1
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL . S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
designated by S in PCL. S is again
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
40 6
1
60 6
1
38B7 Group User’s Manual
#
APPENDIX
3.7 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
•
38B7 Group User’s Manual
•
•
•
•
•
•
•
3-83
APPENDIX
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
E9 2
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
SED
D←1
This instruction set D.
F8 2
1
SEI
I←1
This instruction set I.
78 2
1
SET
T←1
This instruction set T.
32 2
1
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
A
# OP n
BIT, A
# OP n
# OP n
2
E5 3
0B
+ 2
20i
42 2
ZP
BIT, ZP
# OP n
2
1
0F
+ 5
20i
85 4
2
1
STX
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X.
The contents of A does not change.
AA 2
1
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
A8 2
1
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64 3
2
TSX
X←S
This instruction transfers the contents of S in
X.
BA 2
1
TXA
A←X
This instruction stores the contents of X in A.
8A 2
1
TXS
S←X
This instruction stores the contents of X in S.
9A 2
1
TYA
A←Y
This instruction stores the contents of Y in A.
98 2
1
The WIT instruction stops the internal clock C2 2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
1
WIT
Notes 1
2
3
4
5
3-84
:
:
:
:
:
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
38B7 Group User’s Manual
#
2
APPENDIX
3.7 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
95 5
2
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
8D 5
2
96 5
94 5
ABS
3 9D 6
3 99 6
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
81 7
2 91 7
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
N V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
38B7 Group User’s Manual
3-85
APPENDIX
3.7 Machine instructions
Symbol
Contents
Symbol
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(AD H, ADL)
M(00, AD L)
Ai
Mi
OP
n
#
3-86
38B5 Group User's Manual
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in AD H is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
3.8 List of instruction code
3.8 List of instruction code
D7 – D 4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
IMM
ASL
A
SEB
0, A
—
ORA
ABS
ASL
ABS
SEB
0, ZP
ORA
DEC
ABS, Y
A
CLB
0, A
—
0000
0
BRK
ORA
JSR
IND, X ZP, IND
BBS
0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
CLB
ADC ROR
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
38B7 Group User’s Manual
3-87
APPENDIX
3.9 M35501FP
3.9 M35501FP
DESCRIPTION
FEATURES
The M35501FP generates digit signals for fluorescent display
when connected to the output port of a microcomputer. There are
up to 16 digit pins available, and more can be added by connecting additional M35501FPs. The number of fluorescent displays
can be increased easily by connecting the M35501FP to the
CMOS FLD output pins of an 8-bit microcomputer in
MITSUBISHI’s 38B7 Group. The M35501FP is suitable for fluorescent display control on household electric appliances, audio
products, etc.
●Digit output ............................................................. 16 (maximum)
•Up to 16 pins can be selected
•More digits available by connecting additional M35501FPs
•Output structure: high-breakdown voltage, P-channel opendrain; built-in pull-down resistor between digit output pins and
VEE pin
●Power-on reset circuit ........................................................ Built-in
●Power source voltage ................................................ 4.0 to 5.5 V
●Pull-down power source voltage ................................ Vcc – 43 V
●Operating temperature range ................................... –20 to 85 °C
●Package ............................................................................. 24P2E
●Power dissipation .............. 250 µW (at 100 kHz operation clock)
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
←
←
←
←
←
←
←
←
←
←
23
22
21
20
19
18
17
16
15
14
13
DIG9
DIG0
←
24
DIG8
VEE
→
DIG10
PIN CONFIGURATION (TOP VIEW)
→
→
→
SEL
OVFIN
OVFOUT
DIG15
DIG14
DIG13
DIG12
DIG11
VCC
→
CLK
7
→
VSS
6
→
4
←
5
←
3
←
2
←
1
RESET
M35501FP
8
9
10
11
12
Outline: 24P2E-A
24-pin plastic-molded SSOP
Fig. 3.9.1 Pin configuration of M35501FP
3-88
38B7 Group User’s Manual
APPENDIX
3.9 M35501FP
FUNCTIONAL BLOCK
DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG9 DIG8 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 VEE
OVFOUT 7
Shift register
OVFIN 6
VCC
3
VSS
1
RESET 4
Optional digit
counter
Power-on
reset
5
2
CLK SEL
Fig. 3.9.2 Functional block diagram
PIN DESCRIPTION
Table 3.9.1 Pin description
Pin
VCC, VSS
RESET
Name
Power source input
Reset input
CLK
Clock input
SEL
Select input
OVF IN
Overflow signal input
OVF OUT
Overflow signal output
DIG15 –
DIG0
Digit output
VEE
Pull-down power source input
Function
Apply 4.0–5.5 V to Vcc, and 0V to Vss.
Reset internal shift register (built-in power-on reset
circuit).
Digit output varies according to rising edge of clock
input.
Use when specifying the number of digits.
Input “H” when using one M35501FP. Connect to
OVFOUT pin of additional M35501FPs when using
multiple M35501FPs (to use 17 digits or more).
Leave open when using one M35501FP. Connect to
OVFIN pin of additional M35501FPs when using multiple
M35501FPs (to use 17 digits or more).
Output the digit output waveform of fluorescent
display. Leave open when not in use (VEE level
output).
Apply voltage to DIG0 –DIG15 pull-down resistors.
38B7 Group User’s Manual
Output Structure
–
CMOS input level
Built-in pull-up resistor
CMOS input level
Built-in pull-down resistor
CMOS input level
Built-in pull-down resistor
CMOS input level
Fig. No.
–
3
2
2
4
CMOS output
5
High-breakdown-voltage
P-channel open-drain output
Built-in pull-down resistor
–
1
–
3-89
APPENDIX
3.9 M35501FP
PORT BLOCK
(1) DIG0–DIG15
(2) SEL, CLK
Shift register
Pull-down transistor
VEE
(3) RESET
(4) OVFIN
Pull-up transistor
(5) OVFOUT
Shift register
Fig. 3.9.3 Port block diagram
3-90
38B7 Group User’s Manual
APPENDIX
3.9 M35501FP
USAGE
Three usages of the M35501FP are described below.
(1) 16-Digit Mode: 16 digits selected
The number of digits is set to 16 by fixing the OVF IN pin to “H” and
the SEL pin to “L.” Figure 3.9.5 shows the output waveform.
(2) Optional Digit Mode: 1-16 digits selectable
When the number of CLK pin rising edges during an “H” period of
the SEL pin is n and the OVFIN pin is fixed to “H,” the number of
digits set is n. If n is 16 or more, all 16 digits are set. Figure 3.9.6
shows the output waveform.
SEL pin
n
CLK pin
Fig. 3.9.4 Digit setting
(3) Cascade Mode: 17 digits or more selectable
17 digits or more can be used by connecting two M35501FPs or
more. Figure 3.9.7 shows an example using three M35501FPs, offering 33 to 48 digit outputs.
Cascade mode will not operate if all M35501FPs are in 16-digit
mode (SEL = “L”). Use the most significant M35501FP in the optional
digit mode for DIG output. Figure 3.9.8 shows the output waveform.
38B7 Group User’s Manual
3-91
APPENDIX
3.9 M35501FP
DIGIT OUTPUT WAVEFORM
SEL
“L”
CLK
DIG0
DIG1
DIG2
DIG13
DIG14
DIG15
OVFOUT
Fig. 3.9.5 16-digit mode output waveform
RESET
SEL
CLK
DIG0
DIG1
DIG2
DIG3
DIG4
“L”
DIG15
“L”
OVFOUT
Fig. 3.9.6 Optional digit mode output waveform
3-92
38B7 Group User’s Manual
APPENDIX
3.9 M35501FP
OVFIN(1)
RESET
CLK
Select signal
RESET
DIG 0
DIG 1
CLK
DIG 14
DIG 15
SEL
OVFOUT(1)
OVFIN(2)
RESET
DIG 16
DIG 17
CLK
DIG 30
DIG 31
SEL
OVFOUT(2)
OVFIN(3)
RESET
DIG 32
DIG 33
CLK
DIG 46
DIG 47
SEL
OVFOUT(3)
Fig. 3.9.7 Cascade mode connection example: 17 digits or more selected
CLK
RESET
DIG0
DIG1
DIG2
DIG15
OVFOUT(1)
DIG16
DIG17
DIG31
OVFOUT(2)
Fig. 3.9.8 Cascade mode output waveform
38B7 Group User’s Manual
3-93
APPENDIX
3.9 M35501FP
The number of fluorescent displays can be increased by connecting
the M35501FP to the CMOS FLD output pins on a 38B7 Group microcomputer.
Segment (high-breakdown-voltage: 52 pins + CMOS: 4 pins)
(1 pin used as CLK.)
P27–P20
P07–P00
M38B7X
P17–P10
P37–P30
Fluorescent Display (FLD)
P47–P40
P57–P50
P63–P60
P64
SEL
M35501
Digits
DIG0–DIG15
CLK
Fig. 3.9.9 Connection example with 38B7 Group microcomputer (1 to 16 digits)
This FLD controller can control up to 32 digits using the 32 timing
mode of the 38B7 Group microcomputer.
Segment (high-breakdown-voltage: 52 pins + CMOS: 4 pins)
(1 pin is used as CLK.)
P27–P20
P07–P00
P17–P10
M38B7X
P37–P30
Fluorescent Display (FLD)
P47–P40
P57–P50
P63–P60
P64
SEL
M35501
CLK
Digits
DIG0–DIG15
OVF OUT OVF IN
OVF IN OVF OUT
SEL
Digits
DIG16–DIG31
M35501
CLK
Fig. 3.9.10 Connection example with 38B7 Group microcomputer (17 to 32 digits)
3-94
38B7 Group User’s Manual
APPENDIX
3.9 M35501FP
RESET CIRCUIT
To reset the controller, the RESET pin should be held at “L” for 2
µs or more. Reset is released when the RESET pin is returned to
“H” and the power source voltage is between 4.0 V and 5.5 V.
Notes1: Perform the reset release when CLK input signal is “L.”
2: When setting the number of digits by SEL signal, optional digit
counter is set to “0” by reset.
RESET
CLK
DIG0
DIG1
DIG2
DIG3
Fig. 3.9.11 Digit output waveform when reset signal is input
38B7 Group User’s Manual
3-95
APPENDIX
3.9 M35501FP
POWER-ON RESET
Reset can be performed automatically during power on (power-on
reset) by the built-in power-on reset circuit. When using this circuit, set 100 µs or less for the period in which it takes to reach
minimum operation guaranteed voltage from reset.
If the rising time exceeds 100 µs, connect the capacitor between
the RESET pin and VSS at the shortest distance. Consequently,
the RESET pin should be held at “L” until the minimum operation
guaranteed voltage is reached.
VDD
Pull-up transistor
Power-on reset circuit
output voltage
RESET
pin
Power-on reset
circuit
Reset state
(Note)
Internal reset signal
Note:
This symbol represents a parasitic diode.
Applied voltage to the RESET pin must be VDD or less.
Reset released
Power-on
Fig. 3.9.12 Power-on reset circuit
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38B7 Group User’s Manual
APPENDIX
3.9 M35501FP
Table 3.9.2 Absolute maximum ratings
Symbol
VCC
VEE
VI
VI
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Pull-down power source voltage
Input voltage CLK, SEL, OVFIN
Input voltage RESET
Output voltage DIG0–DIG15
Output voltage OVFOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
Ratings
Unit
•All voltages are based on VSS.
•Output transistors are off.
–0.3 to 7.0
VCC –45 to VCC +0.3
–0.3 to V CC +0.3
–0.3 to V CC +0.3
VCC –45 to VCC +0.3
–0.3 to V CC +0.3
250
–20 to 85
–40 to 125
V
V
V
V
V
V
mW
°C
°C
Ta = 25 °C
Table 3.9.3 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VEE
VIH
VIH
VIL
VIL
Parameter
Power source voltage
Power source voltage
Pull-down power source voltage
“H” input voltage CLK, SEL, OVFIN
“H” input voltage RESET
“L” input voltage CLK, SEL, OVFIN
“L” input voltage RESET
Min.
4.0
Limits
Typ.
5.0
0
VCC –43
0.8V CC
0.8V CC
0
0
Max.
5.5
VSS
VCC
VCC
0.2V CC
0.2V CC
Unit
V
V
V
V
V
V
V
Table 3.9.4 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
I OH(peak)
I OH(peak)
I OL(peak)
I OH(avg)
I OH(avg)
I OL(avg)
CLK
Parameter
“H” peak output current DIG0 – DIG15 (Note 1)
“H” peak output current OVFOUT (Note 1)
“L” peak output current OVFOUT (Note 1)
“H” average current DIG0 – DIG15 (Note 2)
“H” average current OVFOUT (Note 2)
“L” average current OVFOUT (Note 2)
Clock input frequency
Limits
Min.
Typ.
Max.
–36
–10
10
–18
–5.0
5.0
2
Unit
mA
mA
mA
mA
mA
mA
MHz
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current is an average value measured over 100 ms.
38B7 Group User’s Manual
3-97
APPENDIX
3.9 M35501FP
Table 3.9.5 Electrical characteristics (V CC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
VOH
“H” output voltage
VOH
VOL
VT+ — VT–
“H” output voltage
“L” output voltage
Hysteresis
IIH
“H” input current
IIH
“H” input current
IIL
“L” input current
IIL
“L” input current
OVF IN
CLK, SEL
RESET
ILOAD
Output load current
DIG0 – DIG15
ILEAK
Output leakage current
DIG0– DIG15
ICC
Power source
3-98
DIG output
DIG0–DIG15
OVFOUT
OVFOUT
CLK, OVFIN
RESET
OVF IN
RESET
CLK, SEL
IOH = –18 mA
IOH = –10 mA
IOL = 10 mA
VCC = 5.0 V
Min.
VCC –2.0
Limits
Typ.
VCC –2.0
VI = V SS
VCC = 5.0 V
VEE = V CC –43 V
VOL = VCC
Output transistors are off.
VEE = V CC –43 V
VOL = VCC –43 V
Output transistors are off.
VCC = 5.0 V, CLK = 100 kHz
Output transistors are off.
38B7 Group User’s Manual
2.0
V
V
V
5.0
µA
140
µA
–5.0
µA
0.4
30
Unit
V
VI = V CC
VI = V CC
VCC = 5.0 V
VI = V SS
Max.
70
–60
–130
–185
µA
500
650
800
µA
–10
µA
50
µA
APPENDIX
3.9 M35501FP
Table 3.9.6 Timing requirements (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tw(RESET)
tc ( CLK)
twH( CLK)
twL ( CLK)
tsu( SEL)
th (SEL )
th (CLK )
Parameter
Min.
2
500
200
200
500
500
500
Reset input “L” pulse width
Clock input cycle time
Clock input “H” pulse width
Clock input “L” pulse width
Select input setup time
Select input hold time
Clock input setup time
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
tw(RESET)
vcc
RESET
Limits
Typ.
0.8V CC
vss
0.2V CC
tc(CLK)
twL(CLK)
twH(CLK)
vcc
CLK
0.2VCC
vss
0.8VCC
vcc
SEL
vss
vcc
CLK
vss
tsu(SEL)
th(SEL) th(CLK)
Fig. 3.9.13 Timing diagram
38B7 Group User’s Manual
3-99
APPENDIX
3.10 SFR memort map
3.10 SFR memory map
000016
Port P0 (P0)
002016
Timer 1 (T1)
002116
Timer 2 (T2)
000216
Port P1 (P1)
002216
Timer 3 (T3)
000316
Port P1 direction register (P1D)
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
Timer 5 (T5)
000116
002516
Timer 6 (T6)
000616
Port P3 (P3)
002616
PWM control register (PWMCON)
000716
Port P3 direction register (P3D)
002716
Timer 6 PWM register (T6PWM)
000816
Port P4 (P4)
002816
Timer 12 mode register (T12M)
000916
Port P4 direction register (P4D)
002916
Timer 34 mode register (T34M)
000A16
Port P5 (P5)
002A16
Timer 56 mode register (T56M)
000B16
Port P5 direction register (P5D)
002B16
D-A conversion register (DA)
000C16
Port P6 (P6)
002C16
Timer X (low-order) (TXL)
000D16
Port P6 direction register (P6D)
002D16
Timer X (high-order) (TXH)
000E16
Port P7 (P7)
002E16
Timer X mode register 1 (TXM1)
000F16
Port P7 direction register (P7D)
002F16
Timer X mode register 2 (TXM2)
001016
Port P8 (P8)
003016
Interrupt interval determination register (IID)
001116
Port P8 direction register (P8D)
003116
Interrupt interval determination control register (IIDCON)
001216
Port P9 (P9)
003216
AD/DA control register (ADCON)
001316
Port P9 direction register (P9D)
003316
A-D conversion register (low-order) (ADL)
001416
Port PA (PA)
003416
A-D conversion register (high-order) (ADH)
001516
Port PA direction register (PAD)
003516
PWM register (high-order) (PWMH)
001616
Port PB (PB)
003616
PWM register (low-order) (PWML)
001716
Port PB direction register (PBD)
003716
Baud rate generator (BRG)
001816
Serial I/O1 automatic transfer data pointer (SIO1DP)
003816
UART control register (UARTCON)
001916
Serial I/O1 control register 1 (SIO1CON1)
003916
Interrupt source switch register (IFR)
001A16
Serial I/O1 control register 2 (SIO1CON2)
003A16
Interrupt edge selection register (INTEDGE)
000516
001B16
Serial I/O1 register/Transfer counter (SIO1)
003B16
CPU mode register (CPUM)
001C16
Serial I/O1 control register 3 (SIO1CON3)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 status register (SIO2STS)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
003F16
Interrupt control register 2(ICON2)
0EEC16
Serial I/O3 control register (SIO3CON)
0EF616
Toff1 time set register (TOFF1)
0EED16
Serial I/O3 register (SIO3)
0EF716
Toff2 time set register (TOFF2)
0EEE16
Watchdog timer control register (WDTCON)
0EF816
FLD data pointer (FLDDP)
0EEF16
Pull-up control register 3 (PULL3)
0EF916
Port P4 FLD/Port switch register (P4FPR)
0EF016
Pull-up control register 1 (PULL1)
0EFA16
Port P5 FLD/Port switch register (P5FPR)
0EF116
Pull-up control register 2 (PULL2)
0EFB16
Port P6 FLD/Port switch register (P6FPR)
0EF216
Port P0 digit output set switch register (P0DOR)
0EFC16 FLD output control register (FLDCON)
0EF316
Port P2 digit output set switch register (P2DOR)
0EFD16 Buzzer output control register (BUZCON)
0EF416
FLDC mode register (FLDM)
0EFE16
Flash memory control register (FCON)
(Note)
0EF516
Tdisp time set register (TDISP)
0EFF16
Flash command register (FCMD)
(Note)
Note: Flash memory version only.
3-100
38B7 Group User’s Manual
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83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
*P27/FLD7
*P26/FLD6
*P25/FLD5
*P24/FLD4
*P23/FLD3
*P22/FLD2
*P21/FLD1
*P20/FLD0
VEE
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/DA
AVSS
VREF
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
C N VS S
RESET
P81/XCOUT
P80/XCIN
VS S
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
38B7 Group User’s Manual
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53
52
51
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
APPENDIX
3.11 Pin configuration
3.11 Pin configuration
M38B79MFH-XXXXFP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
Package type: 100P6S-A
*High-breakdown-voltage output port: Totaling 52
3-101
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
38B7 Group
Editioned by
Committee of editing of Mitsubishi Semiconductor User’s Manual
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©2003 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
38B7 Group
© 2003 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Jan. 2003.
Specifications subject to change without notice.