Renesas M38C36MCMXXXFS 8-bit single-chip microcomputer 740 family / 38000 sery Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
38C3
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
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making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
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REVISION DESCRIPTION LIST
Rev.
No.
1.0
38C3 Group User’s Manual
Revision Description
First Edition
Rev.
date
990412
(1/1)
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 38C3 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 38C3 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “740 Family
Software Manual.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR
MICROCOMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes a list of registers, and necessary information for systems development using
the microcomputer, the mask ROM confirmation (for mask ROM version), ROM programming confirmation,
and the mark specifications which are to be submitted when ordering.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
b
0
Name
Processor mode bits
1
Functions
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
Not available
10:
11:
0 : 0 page
1 : 1 page
0
0
2
Stack page selection bit
3
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
4
0
✕
5
Fix this bit to “0.”
0
0
b7 b6
6
Main clock division ratio selection
bits
7
: Bit in which nothing is arranged
0 0 : φ = XIN /2 (High-speed mode)
0 1 : φ = XIN /8 (Middle-speed mode)
1 0 : φ = XIN /8 (Middle-speed mode)
1 1 : φ = XIN (Double-speed mode)
1
0
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻ ••••••Contents determined by option at reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES .................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
Memory Type ............................................................................................................................ 1-7
Memory Size ............................................................................................................................. 1-7
Package ..................................................................................................................................... 1-7
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8
Central Processing Unit (CPU) .............................................................................................. 1-8
Memory .................................................................................................................................... 1-12
I/O Ports .................................................................................................................................. 1-14
Interrupts ................................................................................................................................. 1-19
Timers ...................................................................................................................................... 1-23
Serial I/O ................................................................................................................................. 1-28
A-D Converter ......................................................................................................................... 1-30
LCD Drive control circuit ....................................................................................................... 1-31
φ Clock Output Function ....................................................................................................... 1-37
ROM Correction Function (Mask ROM version only) ........................................................ 1-38
Reset Circuit ........................................................................................................................... 1-39
Clock Generating Circuit ....................................................................................................... 1-41
NOTES ON PROGRAMMING ..................................................................................................... 1-44
NOTES ON USE .......................................................................................................................... 1-44
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-45
DATA REQUIRED FOR ROM WRITING ORDERS ................................................................. 1-45
ROM PROGRAMMING METHOD .............................................................................................. 1-45
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-46
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Terminate unused pins .................................................................................................. 2-7
2.1.4 Notes on I/O port ........................................................................................................... 2-8
2.1.5 Termination of unused pins .......................................................................................... 2-9
2.2 Timer ....................................................................................................................................... 2-10
2.2.1 Memory map ................................................................................................................. 2-10
2.2.2 Relevant registers ........................................................................................................ 2-11
2.2.3 Timer application examples ........................................................................................ 2-19
2.2.4 Notes on timer A (PWM mode and IGBT output mode) ...................................... 2-31
2.3 Serial I/O ................................................................................................................................ 2-33
2.3.1 Memory map ................................................................................................................. 2-33
2.3.2 Relevant registers ........................................................................................................ 2-33
2.3.3 Serial I/O connection examples ................................................................................. 2-36
38C3 Group User’s Manual
1
Table of contents
2.3.4 Serial I/O’s modes ....................................................................................................... 2-38
2.3.5 Serial I/O application examples ................................................................................. 2-38
2.3.6 Notes on serial I/O ...................................................................................................... 2-51
2.4 LCD controller ...................................................................................................................... 2-52
2.4.1 Memory map ................................................................................................................. 2-52
2.4.2 Relevant registers ........................................................................................................ 2-53
2.4.3 LCD controller application examples ......................................................................... 2-54
2.4.4 Notes on LCD controller ............................................................................................. 2-58
2.5 A-D converter ....................................................................................................................... 2-59
2.5.1 Memory map ................................................................................................................. 2-59
2.5.2 Relevant registers ........................................................................................................ 2-59
2.5.3 A-D converter application examples .......................................................................... 2-62
2.5.4 Notes on A-D converter .............................................................................................. 2-64
2.6 ROM correct function ......................................................................................................... 2-65
2.6.1 Memory map ................................................................................................................. 2-65
2.6.2 Relevant registers ........................................................................................................ 2-66
2.6.3 ROM correct function application examples ............................................................. 2-67
2.7 Reset circuit ......................................................................................................................... 2-69
2.7.1 Connection example of reset IC ................................................................................ 2-69
2.7.2 Notes on reset circuit .................................................................................................. 2-70
2.8 Clock generating circuit .................................................................................................... 2-71
2.8.1 Relevant register .......................................................................................................... 2-71
2.8.2 Clock generating circuit application examples ......................................................... 2-72
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-2
3.1.3 Electrical characteristics ................................................................................................ 3-5
3.1.4 A-D converter characteristics ....................................................................................... 3-7
3.1.5 Timing requirements and switching characteristics ................................................... 3-8
3.1.6 Absolute maximum ratings (M version)..................................................................... 3-10
3.1.7 Recommended operating conditions (M version)..................................................... 3-10
3.1.8 Electrical characteristics (M version) ......................................................................... 3-14
3.1.9 A-D converter characteristics (M version) ................................................................ 3-16
3.1.10 Timing requirements and switching characteristics (M version) .......................... 3-17
3.2 Standard characteristics .................................................................................................... 3-20
3.2.1 Power source current standard characteristics ........................................................ 3-20
3.2.2 Port standard characteristics ...................................................................................... 3-21
3.3 Notes on use ........................................................................................................................ 3-26
3.3.1 Notes on interrupts ...................................................................................................... 3-26
3.3.2 Notes on timer A (PWM mode and IGBT output mode) ...................................... 3-27
3.3.3 Notes on serial I/O ...................................................................................................... 3-29
3.3.4 Notes on LCD controller ............................................................................................. 3-29
3.3.5 Notes on A-D converter .............................................................................................. 3-30
3.3.6 Notes on reset circuit .................................................................................................. 3-30
3.4 Countermeasures against noise ...................................................................................... 3-31
3.4.1 Shortest wiring length .................................................................................................. 3-31
3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................... 3-33
3.4.3 Wiring to analog input pins ........................................................................................ 3-34
3.4.4 Oscillator concerns ....................................................................................................... 3-34
3.4.5 Setup for I/O ports ....................................................................................................... 3-36
2
38C3 Group User’s Manual
Table of contents
3.4.6 Providing of watchdog timer function by software .................................................. 3-37
3.5 Control registers .................................................................................................................. 3-38
3.6 Mask ROM confirmation form........................................................................................... 3-58
3.7 ROM programming confirmation form ............................................................................ 3-62
3.8 Mark specification form ..................................................................................................... 3-66
3.9 Package outline ................................................................................................................... 3-67
3.10 Machine instructions ........................................................................................................ 3-68
3.11 List of instruction code ................................................................................................... 3-79
3.12 SFR memory map .............................................................................................................. 3-80
3.13 Pin configuration ............................................................................................................... 3-81
38C3 Group User’s Manual
3
List of figures
List of figures
CHAPTER 1 HARDWARE
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1 M38C34M6AXXXFP pin configuration .............................................................................. 1-2
2 Functional block diagram ................................................................................................... 1-3
3 Part numbering .................................................................................................................... 1-6
4 Memory expansion plan ..................................................................................................... 1-7
5 740 Family CPU register structure ................................................................................... 1-8
6 Register push and pop at interrupt generation and subroutine call ........................... 1-9
7 Structure of CPU mode register ..................................................................................... 1-11
8 Memory map diagram ...................................................................................................... 1-12
9 Memory map of special function register (SFR) .......................................................... 1-13
10 Structure of PULL register A and PULL register B ................................................... 1-14
11 Structure of port P8 output selection register ............................................................ 1-14
12 Port block diagram (1) ................................................................................................... 1-16
13 Port block diagram (2) ................................................................................................... 1-17
14 Port block diagram (3) ................................................................................................... 1-18
15 Interrupt control ............................................................................................................... 1-21
16 Structure of interrupt-related registers ......................................................................... 1-21
17 Connection example when using key input interrupt and port P8 block diagram 1-22
18 Structure of timer related register ................................................................................ 1-23
19 Block diagram of timer .................................................................................................. 1-24
20 Timing chart of timer 6 PWM 1 mode ........................................................................... 1-25
21 Block diagram of timer A .............................................................................................. 1-26
22 Structure of timer A related registers .......................................................................... 1-26
23 Timing chart of timer A PWM, IGBT output modes .................................................. 1-27
24 Block diagram of serial I/O ........................................................................................... 1-28
25 Structure of serial I/O control register ......................................................................... 1-29
26 Serial I/O timing (for LSB first) .................................................................................... 1-29
27 Structure of A-D control register .................................................................................. 1-30
28 Black diagram of A-D converter ................................................................................... 1-30
29 Structure of LCD related registers ............................................................................... 1-31
30 Block diagram of LCD controller/driver ....................................................................... 1-32
31 Example of circuit at each bias.................................................................................... 1-33
32 LCD display RAM map .................................................................................................. 1-34
33 LCD drive waveform (1/2 bias) .................................................................................... 1-35
34 LCD drive waveform (1/3 bias) .................................................................................... 1-36
35 Structure of φ output control register .......................................................................... 1-37
36 Structure of ROM correct address register ................................................................. 1-38
37 Structure of ROM correct data .................................................................................... 1-38
38 Structure of ROM correct enable register 1 ............................................................... 1-38
39 Reset circuit example .................................................................................................... 1-39
40 Reset sequence .............................................................................................................. 1-39
41 Internal status at reset .................................................................................................. 1-40
42 Ceramic resonator circuit .............................................................................................. 1-41
43 External clock input circuit ............................................................................................ 1-41
44 Clock generating circuit block diagram ....................................................................... 1-42
45 State transitions of system clock ................................................................................. 1-43
46 Programming and testing of One Time PROM version ............................................ 1-45
47 Timing chart after interrupt occurs ............................................................................... 1-47
38C3 Group User’s Manual
List of figures
Fig. 48 Time up to execution of interrupt processing routine ............................................... 1-47
Fig. 49 A-D conversion equivalent circuit ................................................................................. 1-49
Fig. 50 A-D conversion timing chart .......................................................................................... 1-49
CHAPTER 2 APPLICATION
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2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2
2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8) ........................................................ 2-3
2.1.3 Structure of port P7 ..................................................................................................... 2-3
2.1.4 Structure of Port P0 direction register and port P1 direction register ................. 2-4
2.1.5 Structure of Port Pi direction register (i = 2, 4, 5, 6, 8) ....................................... 2-4
2.1.6 Structure of Port P7 direction register ...................................................................... 2-5
2.1.7 Structure of PULL register A ...................................................................................... 2-5
2.1.8 Structure of PULL register B ...................................................................................... 2-6
2.1.9 Structure of Port P8 output selection register ......................................................... 2-6
2.2.1 Memory map of registers relevant to timers .......................................................... 2-10
2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11
2.2.3 Structure of Timer 2 .................................................................................................. 2-11
2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-12
2.2.5 Structure of Timer 12 mode register ....................................................................... 2-12
2.2.6 Structure of Timer 34 mode register ....................................................................... 2-13
2.2.7 Structure of Timer 56 mode register ....................................................................... 2-13
2.2.8 Structure of Timer A register (low-order, high-order) ........................................... 2-14
2.2.9 Structure of Compare register (low-order, high-order) .......................................... 2-14
2.2.10 Structure of Timer A mode register ...................................................................... 2-15
2.2.11 Structure of Timer A control register .................................................................... 2-15
2.2.12 Structure of Interrupt request register 1 ............................................................... 2-16
2.2.13 Structure of Interrupt request register 2 ............................................................... 2-17
2.2.14 Structure of Interrupt control register 1 ................................................................ 2-18
2.2.15 Structure of Interrupt control register 2 ................................................................ 2-18
2.2.16 Timers connection and setting of division ratios ................................................. 2-20
2.2.17 Relevant registers setting ....................................................................................... 2-21
2.2.18 Control procedure ..................................................................................................... 2-22
2.2.19 Peripheral circuit example ....................................................................................... 2-23
2.2.20 Timers connection and setting of division ratios ................................................. 2-23
2.2.21 Relevant registers setting ....................................................................................... 2-24
2.2.22 Control procedure ..................................................................................................... 2-24
2.2.23 Judgment method of valid/invalid of input pulses ............................................... 2-25
2.2.24 Relevant registers setting ....................................................................................... 2-26
2.2.25 Control procedure ..................................................................................................... 2-27
2.2.26 Timers connection and setting of division ratios ................................................. 2-28
2.2.27 Relevant registers setting ....................................................................................... 2-29
2.2.28 Control procedure ..................................................................................................... 2-30
2.2.29 PWM output and IGBT output (1) ......................................................................... 2-31
2.2.30 PWM output and IGBT output (2) ......................................................................... 2-31
2.2.31 PWM output and IGBT output (3) ......................................................................... 2-32
2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-33
2.3.2 Structure of Serial I/O control register 1 ................................................................ 2-33
2.3.3 Structure of Serial I/O control register 2 ................................................................ 2-34
2.3.4 Structure of Interrupt request register 1 ................................................................. 2-34
2.3.5 Structure of Interrupt control register 1 .................................................................. 2-35
2.3.6 Serial I/O connection examples (1) ......................................................................... 2-36
2.3.7 Serial I/O connection examples (2) ......................................................................... 2-37
38C3 Group User’s Manual
5
List of figures
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2.3.8 Serial I/O’s modes ..................................................................................................... 2-38
2.3.9 Connection diagram ................................................................................................... 2-38
2.3.10 Timing chart .............................................................................................................. 2-39
2.3.11 Registers setting relevant to transmission side ................................................... 2-40
2.3.12 Registers setting relevant to reception side ......................................................... 2-41
2.3.13 Control procedure of transmission side ................................................................ 2-41
2.3.14 Control procedure of reception side ...................................................................... 2-42
2.3.15 Connection diagram ................................................................................................. 2-43
2.3.16 Timing chart .............................................................................................................. 2-43
2.3.17 Relevant registers setting ....................................................................................... 2-44
2.3.18 Setting of transmission data ................................................................................... 2-44
2.3.19 Control procedure ..................................................................................................... 2-45
2.3.20 Connection diagram ................................................................................................. 2-46
2.3.21 Timing chart .............................................................................................................. 2-47
2.3.22 Relevant registers setting in master unit .............................................................. 2-48
2.3.23 Relevant registers setting in slave unit ................................................................ 2-48
2.3.24 Control procedure of master unit ........................................................................... 2-49
2.3.25 Control procedure of slave unit ............................................................................. 2-50
2.4.1 Memory map of registers relevant to LCD controller............................................ 2-52
2.4.2 Structure of Segment output enable register ......................................................... 2-53
2.4.3 Structure of LCD mode register ............................................................................... 2-53
2.4.4 LCD panel ................................................................................................................... 2-54
2.4.5 Segment allocation example ..................................................................................... 2-54
2.4.6 LCD display RAM map .............................................................................................. 2-55
2.4.7 LCD display RAM setting .......................................................................................... 2-55
2.4.8 Relevant registers setting ......................................................................................... 2-56
2.4.9 Control procedure ....................................................................................................... 2-57
2.5.1 Memory map of A-D converter relevant registers ................................................. 2-59
2.5.2 Structure of A-D control register .............................................................................. 2-59
2.5.3 Structure of A-D conversion register (low-order) ................................................... 2-60
2.5.4 Structure of A-D conversion register (high-order) ................................................. 2-60
2.5.5 Structure of Interrupt request register 2 ................................................................. 2-61
2.5.6 Structure of Interrupt control register 2 .................................................................. 2-61
2.5.7 Connection diagram ................................................................................................... 2-62
2.5.8 Setting of relevant registers ..................................................................................... 2-62
2.5.9 Control procedure ....................................................................................................... 2-63
2.6.1 Memory map of ROM correct function relevant registers .................................... 2-65
2.6.2 Structure of ROM correct enable register 1 ........................................................... 2-66
2.6.3 Connection diagram ................................................................................................... 2-67
2.6.4 Setting of relevant registers ..................................................................................... 2-67
2.6.5 Control procedure ....................................................................................................... 2-68
2.7.1 Example of power-on reset circuit ........................................................................... 2-69
2.7.2 RAM backup system example .................................................................................. 2-69
2.8.1 Structure of CPU mode register .............................................................................. 2-71
2.8.2 Connection diagram ................................................................................................... 2-72
2.8.3 Status transition diagram during power failure ...................................................... 2-73
2.8.4 Setting of relevant registers ..................................................................................... 2-74
2.8.5 Control procedure ....................................................................................................... 2-75
2.8.6 Structure of clock counter ......................................................................................... 2-76
2.8.7 Initial setting of relevant registers ........................................................................... 2-77
2.8.8 Setting of relevant registers after detecting power failure ................................... 2-78
2.8.9 Control procedure ....................................................................................................... 2-79
38C3 Group User’s Manual
List of figures
CHAPTER 3 APPENDIX
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3.1.1 Circuit for measuring output switching characteristics .......................................... 3-18
3.1.2 Timing chart ................................................................................................................ 3-19
3.2.1 Power source current standard characteristics ...................................................... 3-20
3.2.2 Power source current standard characteristics (in wait mode) ........................... 3-20
3.2.3 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C) .... 3-21
3.2.4 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (90 °C) .... 3-21
3.2.5 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C) .... 3-22
3.2.6 CMOS output port (P0, P1, P2, P3) N-channel side characteristics (90 °C) ... 3-22
3.2.7 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics
(25 °C) .......................................................................................................................... 3-23
Fig. 3.2.8 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics
(90 °C) .......................................................................................................................... 3-23
Fig. 3.2.9 CMOS output port (P4, P52–P57, P6, P70, P71) N-channel side characteristics (25 °C)
........................................................................................................................................................ 3-24
Fig. 3.2.10 CMOS output port (P4, P52–P57, P6, P7 0, P7 1) N-channel side characteristics
(90 °C) ....................................................................................................................... 3-24
Fig. 3.2.11 CMOS output port (P5 0, P8) N-channel side characteristics (25 °C) ............... 3-25
Fig. 3.2.12 CMOS output port (P5 0, P8) N-channel side characteristics (90 °C) ............... 3-25
Fig. 3.3.1 Sequence of switch detection edge......................................................................... 3-26
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-26
Fig. 3.3.3 Structure of interrupt control register 2 .................................................................. 3-27
Fig. 3.3.4 PWM output and IGBT output (1) ............................................................................ 3-27
Fig. 3.3.5 PWM output and IGBT output (2) ............................................................................ 3-28
Fig. 3.3.6 PWM output and IGBT output (3) ............................................................................ 3-28
Fig. 3.4.1 Selection of packages ............................................................................................... 3-31
Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-31
Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-32
Fig. 3.4.4 Wiring for the V PP pin of the One Time PROM and the EPROM version ......... 3-33
Fig. 3.4.5 Bypass capacitor across the VSS line and the V CC line ........................................ 3-33
Fig. 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-34
Fig. 3.4.7 Wiring for a large current signal line ...................................................................... 3-34
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-35
Fig. 3.4.9 V SS pattern on the underside of an oscillator ........................................................ 3-35
Fig. 3.4.10 Setup for I/O ports ................................................................................................... 3-36
Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-37
Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-38
Fig. 3.5.2 Structure of Port P0 direction register and Port P1 direction register ............... 3-38
Fig. 3.5.3 Structure of Port Pi direction register ..................................................................... 3-39
Fig. 3.5.4 Structure of Port P7 ................................................................................................... 3-39
Fig. 3.5.5 Structure of Port P7 direction register .................................................................... 3-40
Fig. 3.5.6 Structure of PULL register A .................................................................................... 3-40
Fig. 3.5.7 Structure of PULL register B .................................................................................... 3-41
Fig. 3.5.8 Structure of Port P8 output selection register ....................................................... 3-42
Fig. 3.5.9 Structure of Serial I/O control register 1 ................................................................ 3-43
Fig. 3.5.10 Structure of Serial I/O control register 2 .............................................................. 3-44
Fig. 3.5.11 Structure of Serial I/O register ............................................................................... 3-44
Fig. 3.5.12 Structure of Timer i ................................................................................................. 3-45
Fig. 3.5.13 Structure of Timer 2 ................................................................................................ 3-45
Fig. 3.5.14 Structure of Timer 6 PWM register ....................................................................... 3-46
Fig. 3.5.15 Structure of Timer 12 mode register ..................................................................... 3-46
38C3 Group User’s Manual
7
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
8
3.5.16
3.5.17
3.5.18
3.5.19
3.5.20
3.5.21
3.5.22
3.5.23
3.5.24
3.5.25
3.5.26
3.5.27
3.5.28
3.5.29
3.5.30
3.5.31
3.5.32
3.5.33
3.5.34
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
Structure
of
of
of
of
of
of
of
of
of
of
of
of
of
of
of
of
of
of
of
Timer 34 mode register ..................................................................... 3-47
Timer 56 mode register ..................................................................... 3-47
φ output control register .................................................................... 3-48
Timer A register (low-order, high-order) ......................................... 3-48
Compare register (low-order, high-order) ........................................ 3-49
Timer A mode register ...................................................................... 3-49
Timer A control register .................................................................... 3-50
A-D control register ............................................................................ 3-50
A-D conversion register (low-order) ................................................. 3-51
A-D conversion register (high-order) ............................................... 3-51
Segment output enable register ....................................................... 3-52
LCD mode register ............................................................................. 3-52
Interrupt edge selection register ...................................................... 3-53
CPU mode register ............................................................................ 3-53
Interrupt reqeust register 1 ............................................................... 3-54
Interrupt request register 2 ............................................................... 3-55
Interrupt control register 1 ................................................................ 3-56
Interrupt control register 2 ................................................................ 3-56
ROM correct enable register 1 ......................................................... 3-57
38C3 Group User’s Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description (1) ........................................................................................................... 1-4
2 Pin description (2) ........................................................................................................... 1-5
3 Support products ............................................................................................................. 1-7
4 Push and pop instructions of accumulator or processor status register ................. 1-9
5 Set and clear instructions of each bit of processor status register ....................... 1-10
6 List of I/O port function (1) .......................................................................................... 1-14
7 List of I/O port function (2) .......................................................................................... 1-15
8 Interrupt vector addresses and priority ...................................................................... 1-20
9 Function of P46/SCLK1 and P4 0/SCLK2 ..................................................................................................................................... 1-28
10 Maximum number of display pixels at each duty ratio .......................................... 1-31
11 Bias control and applied voltage to Vl1–V L3 .......................................................................................................... 1-33
12 Duty ratio control and common pins used ............................................................... 1-33
13 Programming adapter .................................................................................................. 1-45
14 Interrupt sources, vector addresses and interrupt priority ..................................... 1-46
15 Relative formula for a reference voltage V REF of A-D converter and V ref ..................... 1-48
16 Change of A-D conversion register during A-D conversion .................................. 1-48
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-7
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions ....................................................................... 3-2
3.1.3 Recommended operating conditions ....................................................................... 3-3
3.1.4 Recommended operating conditions ....................................................................... 3-4
3.1.5 Electrical characteristics ........................................................................................... 3-5
3.1.6 Electrical characteristics ........................................................................................... 3-6
3.1.7 A-D converter characteristics .................................................................................. 3-7
3.1.8 Timing requirements 1 .............................................................................................. 3-8
3.1.9 Timing requirements 2 .............................................................................................. 3-8
3.1.10 Switching characteristics 1 .................................................................................... 3-9
3.1.11 Switching characteristics 2 .................................................................................... 3-9
3.1.12 Absolute maximum ratings (M version) ............................................................. 3-10
3.1.13 Recommended operating conditions (M version) ............................................. 3-10
3.1.14 Recommended operating conditions (M version) ............................................. 3-11
3.1.15 Recommended operating conditions (M version) ............................................. 3-11
3.1.16 Recommended operating conditions (M version) ............................................. 3-12
3.1.17 Recommended operating conditions (M version) ............................................. 3-13
3.1.18 Electrical characteristics (M version).................................................................. 3-14
3.1.19 Electrical characteristics (M version).................................................................. 3-15
3.1.20 A-D converter characteristics (M version) ......................................................... 3-16
3.1.21 Timing requirements 1 (M version) .................................................................... 3-17
3.1.22 Timing requirements 2 (M version) .................................................................... 3-17
3.1.23 Switching characteristics 1 (M version) ............................................................. 3-18
3.1.24 Switching characteristics 2 (M version) ............................................................. 3-18
38C3 Group User’s Manual
9
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK
ORDERS
DATA REQUIRED FOR ROM WRITING
ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
●LCD drive control circuit
Bias ............................................................................ 1/1, 1/2, 1/3
Duty .................................................................... 1/1, 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●2 Clock generating circuit
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................... 4.0 to 5.5 V
In middle-speed mode ................................................ 2.5 to 5.5 V
(M version is 2.2✽ to 5.5 V)
In low-speed mode ..................................................... 2.5 to 5.5 V
(M version is 2.2✽ to 5.5 V)
●Power dissipation
In high-speed mode ........................................................... 32 mW
(at 8 MHz oscillation frequency)
In low-speed mode .............................................................. 45 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range ................................... – 20 to 85°C
✽ Mask ROM version only
The 38C3 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38C3 group has a LCD drive control circuit, a 10-channel A-D
converter, and a Serial I/O as additional functions.
The various microcomputers in the 38C3 group include variations of
internal memory size and packaging. For details, refer to the section
on part numbering.
For details on availability of microcomputers in the 38C3 group, refer
to the section on group expansion.
FEATURES
●Basic machine-language instructions ....................................... 71
●The minimum instruction execution time ............................. 0.5 µs
(at 8MHz oscillation frequency)
●Memory size
ROM .................................................................. 4 K to 48 K bytes
RAM ................................................................. 192 to 1024 bytes
●Programmable input/output ports ............................................. 57
●Software pull-up/pull-down resistors
..................................................... (Ports P0–P8 except Port P51)
●Interrupts ................................................... 16 sources, 16 vectors
(includes key input interrupt)
●Timers ............................................................ 8-bit ✕ 6, 16-bit ✕ 1
●A-D converter ................................................. 10-bit ✕ 8 channels
●Serial I/O ....................................... 8-bit ✕ 1 (Clock-synchronized)
APPLICATION
Camera, household appliances, consumer electronics, etc.
42
41
45
44
43
46
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
65
40
66
39
67
68
38
69
36
35
37
70
34
71
72
33
M38C34M6AXXXFP
73
32
74
31
75
30
76
77
29
78
27
79
26
25
28
24
23
22
21
20
18
19
17
16
13
14
15
12
9
10
11
8
5
6
7
4
3
P61/AN1
P60/AN0
P57/INT2
P56/INT1
P55/INT0
P54/CNTR1
P53/CNTR0
P52/PWM1
P51
RESET
P71/XcOUT
P70/XcIN
VSS
XIN
XOUT
VCC
P50/TAOUT
P87
P86
P85
P84
P83
P82
P81
2
80
1
P47/SRDY
P46/SCLK1
P45/SOUT
P44/SIN
P43/φ
P42/T3OUT
P41/T1OUT
P40/SCLK2
AVSS
VREF
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
61
64
63
P20/SEG0
P21/SEG1
P22/SEG2
P23/SEG3
P24/SEG4
P25/SEG5
P26/SEG6
P27/SEG7
P00/SEG8
P01/SEG9
P02/SEG10
P03/SEG11
P04/SEG12
P05/SEG13
P06/SEG14
P07/SEG15
P10/SEG16
P11/SEG17
P12/SEG18
P13/SEG19
P14/SEG20
P15/SEG21
P16/SEG22
P17/SEG23
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 M38C34M6AXXXFP pin configuration
1-2
38C3 Group User’s Manual
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM0
COM1
COM2
COM3
VL1
VL2
VL3
P80
XCIN
12 11
P7(2)
XCOUT
Subclock
output
I/O port P7
XCOUT
XCIN
Subclock
input
I/O port P6
(0V)
74 73
VREF
AVSS
2 75 76 77 78 79 80
P6(8)
PS
PCL
S
Y
X
A
A-D converter(10)
PCH
C P U
3
4
5
CNTR0,CNTR1
6
7
P5(8)
8
I/O port P5
✽ This is valid only in mask ROM version.
1
φ
Clock generating
circuit
9 17
16
10
15
14
I/O port P4
65 66 67 68 69 70 71 72
P4(8)
SI/O(8)
Timer 6(8)
Timer 5(8)
Timer A(16)
Timer 2(8)
Timer 4(8)
Timer 1(8)
PWM0,PWM1
✽
13
(0V)
VSS
ROM corrective
RAM
(8 bytes)
ROM
corrective
circuit
Timer 3(8)
ROM
φ
38C3 Group User’s Manual
INT0–INT2
Data bus
(5V)
VCC
Reset input
RESET
Main
clock
output
XOUT
Main
clock
input
XIN
T1OUT, T3OUT
FUNCTIONAL BLOCK DIAGRAM
Output port P3
33 34 35 36 37 38 39 40
P3(8)
LCD display
RAM
(16 bytes)
RAM
I/O port P2
57 58 59 60 61 62 63 64
P2(8)
LCD
drive control
circuit
Key-on wake-up
I/O port P1
41 42 43 44 45 46 47 48
P1(8)
P8(8)
I/O port P0
49 50 51 52 53 54 55 56
P0(8)
18 19 20 21 22 23 24 25
I/O port P8
VL1
VL2
VL3
COM0
COM1
COM2
29 COM3
30
31
32
26
27
28
HARDWARE
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
VCC, VSS
VREF
Name
RESET
XIN
Power source
Analog reference
voltage
Analog power
source
Reset input
Clock input
XOUT
Clock output
VL1 – VL3
LCD power
source
Common output
AVSS
COM0 –
COM3
P00/SEG8 –
P07/SEG15
I/O port P0
P10/SEG16 – I/O port P1
P17/SEG23
P20/SEG0 –
P27/SEG7
•
•
•
•
•
•
GND input pin for A-D converter.
Connect to VSS.
Reset input pin for active “L.”
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between XIN pin and XOUT pin.
Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
• Input 0 – VL3 voltage to LCD.
• LCD common output pins.
• COM1, COM2, and COM3 are not used at 1/1 duty ratio.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
• 8-bit I/O port.
• LCD segment pins
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each port to be individually
programmed as either input or output.
• Pull-down control is enabled.
I/O port P4
• 8-bit output port.
• CMOS state output.
• Pull-down control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
✽ Mask ROM version of M version is 2.2 V to 5.5 V.
1-4
Function except a port function
I/O port P2
P30/SEG24 – Output port P3
P37/SEG31
P40/SCLK2
P41/T1OUT
P42/T3OUT
P43/φ
P44/SIN,
P45/SOUT,
P46/SCLK1,
P47/SRDY
Function
• Apply voltage of 2.5✽ V to 5.5 V to VCC, and 0 V to VSS.
• Reference voltage input pin for A-D converter.
38C3 Group User’s Manual
• Serial I/O function pin
• Timer output pin
• Timer output pin
• φ output pin
• Serial I/O function pins
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2)
Pin
Name
P51
Input port P5
P50/TAOUT
P52/PWM1
P53/CNTR0,
P54/CNTR1
P55/INT0,
P56/INT1,
P57/INT2
P60/AN0 –
P67/AN7
I/O port P5
P70/XCIN,
P71/XCOUT
I/O port P7
P80 – P87
I/O port P8
I/O port P6
Function
•
•
•
•
•
•
1-bit input pin.
CMOS compatible input level.
7-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
2-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
8-bit I/O port.
TTL input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
38C3 Group User’s Manual
Function except a port function
• Timer A output pin
• PWM1 output (timer output) pin
• External count I/O pins
• External interrupt input pins
• A-D conversion input pins
• Sub-clock generating circuit I/O pins
• Key input (Key-on wake-up) interrupt
input pins
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product
M38C3
4
M
6 A
XXX
FP
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in One Time PROM
version shipped in blank and
EPROM version.
A : Standard(Note)
M : M version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
Note : Difference between standard and M version
• Standard : Port P50 /TAOUT pin remains set to the input mode until the direction
register is set to the output mode during reset and after
reset.
• M version : Port P50 /TAOUT pin remains set to the output mode (“L” output) until
the direction register is set to the input mode during reset
and after reset.
Fig. 3 Part numbering
1-6
38C3 Group User’s Manual
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 38C3 group as follows.
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions
Memory Size
ROM/PROM size ................................................ 16 K to 48 K bytes
RAM size ............................................................. 512 to 1024 bytes
Memory Expansion Plan
ROM size (bytes)
48K
M38C37ECA/ECM
44K
40K
Under development
36K
M38C34M8
32K
28K
24K
M38C34M6A/M6M
20K
Planning
16K
M38C33M4
12K
8K
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Products under development or planning : the development schedule and specification may be revised without notice.
Planning products may be stopped the development.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
As of December 1998
Table 3 Support products
Product name
M38C34M6AXXXFP
M38C37ECAXXXFP
M38C37ECAFP
M38C37ECAFS
M38C34M6MXXXFP
M38C37ECMXXXFP
M38C37ECMFP
M38C37ECMFS
(P) ROM size (bytes)
ROM size for User in ( )
24576 (24446)
RAM size
(bytes)
640
Package
80P6N-A
49152 (49022)
1024
24576 (24446)
640
49152 (49022)
1024
80D0
80P6N-A
80D0
38C3 Group User’s Manual
Remarks
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
[Stack Pointer (S)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack
page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program
when the user needs them during interrupts or subroutine calls.
[Index Register X (X)]
[Program Counter (PC)]
The index register X is an 8-bit register. In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
The 38C3 group uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
Stack pointer
b0
PCL
PCH
b7
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
1-8
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
38C3 Group User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic operation
and 3 flags which decide MCU operation. Branch operations can be
performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V)
flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not
valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
1-10
SEC
CLC
Z flag
_
_
I flag
D flag
SEI
CLI
SED
CLD
38C3 Group User’s Manual
B flag
_
_
T flag
V flag
SET
CLT
_
N flag
_
CLV
_
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the
internal system clock selection bit etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B 16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
Not used (returns “1” when read)
(Do not write “0” to this bit.)
Port XC switch bit
0 : I/O port
1 : X CIN, XCOUT
Main clock ( X IN –XOUT ) stop bit
0 : Operating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN )/2 (high-speed mode)
1 : f(XIN )/8 (middle-speed mode)
Internal system clock selection bit
0 : X IN-X OUT selected (middle-/high-speed mode)
1 : X CIN-X COUT selected (low-speed mode)
Fig. 7 Structure of CPU mode register
38C3 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Special Function Register (SFR) Area
Zero Page
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
Access to this area with only 2 bytes is possible in the special page
addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
192
00FF 16
004016
256
013F 16
005016
384
01BF16
512
023F 16
640
02BF16
768
033F 16
896
03BF16
1024
043F 16
SFR area 1
LCD display RAM area
ROM corrective RAM area
(Note 1)
Zero page
005816
RAM
010016
XXXX16
Reserved area
044016
Not used
0F00 16
0FFF16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ 16
4096
F000 16
F080 16
8192
E00016
E080 16
12288
D00016
D08016
16384
C00016
C08016
20480
B00016
B080 16
24576
A00016
A080 16
28672
900016
908016
32768
800016
808016
36864
700016
708016
40960
600016
608016
45056
500016
508016
49152
400016
408016
SFR area 2 (Note 1)
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ 16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
Reserved ROM area
FFFF 16
Note 1 : This is valid only in mask ROM version.
Fig. 8 Memory map diagram
1-12
38C3 Group User’s Manual
Special page
HARDWARE
FUNCTIONAL DESCRIPTION
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
002016 Timer 1 (T1)
002116 Timer 2 (T2)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
002216 Timer 3 (T3)
002316 Timer 4 (T4)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
002416 Timer 5 (T5)
000616 Port P3 (P3)
002616
000716
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
002716 Timer 6 PWM register (T6PWM)
002816 Timer 12 mode register (T12M)
002916 Timer 34 mode register (T34M)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
002A16 Timer 56 mode register (T56M)
002B16 φ output control register (CKOUT)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
002C16 Timer A register (low) (TAL)
002D16 Timer A register (high) (TAH)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
002E16 Compare register (low) (CONAL)
001016 Port P8 (P8)
001116 Port P8 direction register (P8D)
003016 Timer A mode register (TAM)
003116 Timer A control register (TACON)
001216
003216 A-D control register (ADCON)
001316
001416
003316 A-D conversion register (low) (ADL)
003416 A-D conversion register (high) (ADH)
001516
003516
001616 PULL register A (PULLA)
001716 PULL register B (PULLB)
003616
001816 Port P8 output selection register (P8SEL)
001916 Serial I/O control register 1 (SIOCON1)
003816 Segment output enable register (SEG)
002516 Timer 6 (T6)
002F16 Compare register (high) (CONAH)
003716
001A16 Serial I/O control register 2 (SIOCON2)
001B16 Serial I/O register (SIO)
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
001C16
001D16
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001E16
001F16
0F01 16 ROM correct enable register 1 (Note)
0F02 16 ROM correct high-order address register 1 (Note)
0F0316 ROM correct low-order address register 1 (Note)
0F0A16 ROM correct high-order address register 5 (Note)
0F0B16 ROM correct low-order address register 5 (Note)
0F0C16 ROM correct high-order address register 6 (Note)
0F04 16 ROM correct high-order address register 2 (Note)
0F0D16 ROM correct low-order address register 6 (Note)
0F05 16 ROM correct low-order address register 2 (Note)
0F0616 ROM correct high-order address register 3 (Note)
0F0E16 ROM correct high-order address register 7 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F10 16 ROM correct high-order address register 8 (Note)
0F07 16 ROM correct low-order address register 3 (Note)
0F08 16 ROM correct high-order address register 4 (Note)
0F11 16 ROM correct low-order address register 8 (Note)
0F0916 ROM correct low-order address register 4 (Note)
Note: This register is valid only in mask ROM version.
Fig. 9 Memory map of special function register (SFR)
38C3 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
[Direction Registers (ports P2, P4, P50, P52–P57,
and P6–P8)]
b7
b0
PULL register A
(PULLA : address 0016 16)
The I/O ports P2, P4, P50, P52–P57, and P6–P8 have direction registers which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
P00 –P07 pull-down
P10 –P17 pull-down
P20 –P27 pull-down
Not used
P70 , P71 pull-up
P80 –P87 pull-up
Not used (return “0” when read)
b7
b0
PULL register B
(PULLB : address 0017 16)
P40 –P43 pull-up
P44 –P47 pull-up
P50 , P52, P53 pull-up
P54 –P57 pull-up
[Direction Registers (ports P0 and P1)]
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
When “0” is written to the bit 0 of a direction register, that port becomes an input port. When “1” is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used.
P60 –P63 pull-up
P64 –P67 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output ports.
Fig. 10 Structure of PULL register A and PULL register B
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register
B (address 001716), ports except for ports P3 and P51 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with a
program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
b7
b0
Port P8 output selection register
(P8SEL : address 0018 16)
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 Output Selection
Ports P80 to P87 can be switched to N-channel open-drain output by
setting “1” to the port P8 output selection register.
Fig. 11 Structure of port P8 output selection register
Table 6 List of I/O port function (1)
Pin
P00/SEG8 –
P07/SEG15
Name
Port P0
Input/Output
Input/Output,
port unit
P10/SEG16 –
P17/SEG23
Port P1
Input/Output,
port unit
P20/SEG0 –
P27/SEG7
Port P2
Input/Output,
individual bits
P30/SEG24 –
P37/SEG31
Port P3
Output,
individual bits
1-14
I/O format
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
CMOS 3-state output
Non-port function
LCD segment output
CMOS 3-state output
LCD segment output
LCD segment output
LCD segment output
38C3 Group User’s Manual
Related SFRs
Ref. No.
PULL register A
(1)
Segment output enable register
PULL register A
Segment output enable register
PULL register A
Segment output enable register
Segment output enable reg(2)
ister
HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 List of I/O port function (2)
Pin
P40/SCLK2
Name
Port P4
Input/Output
Input/Output,
individual bits
I/O format
CMOS compatible input
level
CMOS 3-state output
Non-port function
Serial I/O function I/O
P41/T1OUT
Timer output
P42/T3OUT
Timer output
P43/φ
φ clock output
P44/SIN
P45/SOUT
P46/SCLK1
P47/SRDY
Serial I/O function I/O
P50/TAOUT
Port P5
P51
Input/Output,
individual bits
Input
P52/PWM1
Timer A output
PWM output
Timer 56 mode register
PULL register B
(4)
P53/CNTR0
P54/CNTR1
External count I/O
(12)
P55/INT0
P56/INT1
P57/INT2
P60/AN0
–
P67/AN7
External interrupt input
Interrupt edge selection register
PULL register B
Interrupt edge selection register
PULL register B
A-D control register
PULL register B
CPU mode register
PULL register A
(14)
P70/XCIN
Input/Output,
individual bits
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS compatible input
level
CMOS 3-state output
Related SFRs
Ref. No.
Serial I/O control registers
(3)
1, 2
PULL register B
Timer 12 mode register
(4)
PULL register B
Timer 34 mode register
(4)
PULL register B
φ output control register
(5)
PULL register B
Serial I/O control registers
(6)
1, 2
(7)
PULL register B
(8)
(9)
Timer A mode register
(10)
Timer A control register
PULL register B
(11)
Port P6
Input/Output,
individual bits
Port P7
Input/Output,
individual bits
P71/XCOUT
P80 – P87
Port P8
COM0 – COM3
Common
Input/Output,
individual bits
Output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
LCD common output
A-D converter input
Sub-clock generating
circuit I/O
(12)
(13)
(15)
Key input (key-on
wake-up) interrupt input
Interrupt control register 2
PULL register A
(17)
LCD mode register
(16)
Notes 1: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
2: For details of how to use double function ports as function I/O ports, refer to the applicable sections.
38C3 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
(1)Ports P0, P1, P2
(2)Port P3
VL2/VL3
VL2/VL3
VL1/VSS
VL1/VSS
Segment output enable bit
(Note)
Segment output enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
Pull-down control
Pull-down control
Segment output enable bit
Segment output enable bit
Note : Port P0, P1 direction registers are only bit 0.
(4)Ports P4 1, P42, P52
(3)Port P4 0
P-channel output disable bit
Pull-up control
Serial I/O mode selection bit
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Pull-up control
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Timer 1 output
Timer 3 output
Timer 6 output
Serial I/O clock output
(6)Port P4 4
(5)Port P4 3
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
φ output control bit
φ
Serial I/O input
Fig. 12 Port block diagram (1)
1-16
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(8)Port P4 6
(7)Port P4 5
Pull-up control
P-channel output disable bit
P-channel output disable bit
Serial I/O port selection bit
Serial I/O mode selection bit
Direction register
Data bus
Pull-up control
Direction register
Port latch
Data bus
Serial I/O output
Port latch
Serial I/O clock output
Serial I/O clock input
(9)Port P4 7
(10)Port P5 0
Pull-up control
Pull-up control
SRDY output enable bit
Timer A output enable bit
(Note)
Direction register
Direction register
Data bus
Port latch
Data bus
Serial I/O ready output
Port latch
Timer A output
(12)Ports P5 3–P57
(11)Port P5 1
Pull-up control
Data bus
Direction register
Data bus
Note: The initial value of M version becomes “1” (output).
Port latch
INT0–INT2 interrupt input
CNTR0,CNTR 1 interrupt input
Fig. 13 Port block diagram (2)
38C3 Group User’s Manual
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
(14)Port P7 0
(13)Port P6
Port selection • pull-up control
Pull-up control
Port Xc switch bit
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
A-D conversion input
Analog input pin selection bit
(15)Port P7 1
Sub-clock generating circuit input
(16)COM 0–COM3
Port selection • pull-up control
VL3
Port Xc switch bit
Direction register
VL2
VL1
Data bus
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
Port latch
Oscillator
Port P70
Port Xc switch bit
(17)Port P8
Pull-up control
P-channel output disable bit
Direction register
Data bus
Port latch
Key input (key-on wake-up) interrupt input
Fig. 14 Port block diagram (3)
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38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
Interrupts occur by sixteen sources: six external, nine internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Interrupts
When the active edge of an external interrupt (INT0 – INT2, CNTR0
or CNTR1) is set or an vector interrupt source where several interrupt
source is assigned to the same vector address is switched, the corresponding interrupt request bit may also be set. Therefore, take following sequence:
(1) Disable the interrupt.
(2) Change the active edge in interrupt edge selection register.
(3) Clear the set interrupt request bit to “0.”
(4) Enable the interrupt.
38C3 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Reset (Note 2)
INT0
1
2
INT1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
Interrupt Request
Generating Conditions
FFFB16
FFFA16
3
FFF916
FFF816
INT2
4
FFF716
FFF616
Serial I/O
5
FFF516
FFF416
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
6
7
8
9
10
11
12
13
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
CNTR1
14
FFE316
FFE216
Key input (Keyon wake-up)
A-D conversion
15
FFE116
FFE016
16
FFDF16
FFDE16
At reset
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At detection of either rising or falling edge of
INT2 input
At completion of serial I/O data transmit/receive
At timer A underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At falling of port P8 (at input) input logical level
AND
At completion of A-D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
1-20
38C3 Group User’s Manual
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Valid when A-D conversion interrupt
is selected
Non-maskable software interrupt
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A 16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit 0 : Falling edge active
INT2 interrupt edge selection bit 1 : Rising edge active
Not used (return “0” when read)
CNTR0 active edge switch bit 0 : Falling edge active, rising edge count
CNTR1 active edge switch bit 1 : Rising edge active, falling edge count
b7
b0
Interrupt request register 1
(IREQ1 : address 003C 16 )
b7
b0
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Serial I/O interrupt request bit
Timer A interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D 16 )
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Key input interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
Interrupt control register 1
(ICON1 : address 003E 16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Serial I/O interrupt enable bit
Timer A interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b0
Interrupt control register 2
(ICON2 : address 003F 16)
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
38C3 Group User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying “L” level to any
pin of port P8 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P80–P83.
Port PXx
“L” level output
PULL register A
Bit 5 = “1”
Port P87
direction register = “1”
✽
✽✽
✽
✽✽
Key input interrupt request
Port P87
latch
P87 output
Port P86
direction register = “1”
Port P86
latch
P86 output
✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽
Port P85
direction register = “1”
Port P85
latch
P85 output
Port P84
direction register = “1”
Port P84
latch
P84 output
P83 input
P82 input
Port P83
direction register = “0”
Port P83
latch
Port P8
Input reading circuit
Port P82
direction register = “0”
Port P82
latch
Port P81
direction register = “0”
P81 input
✽
P80 input
Port P81
latch
Port P80
direction register = “0”
✽✽
Port P80
latch
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 17 Connection example when using key input interrupt and port P8 block diagram
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38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
8-Bit Timer
The 38C3 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
The count can be stopped by setting the stop bit of each timer to “1.”
The system clock φ can be set to either the high-speed mode or lowspeed mode with the CPU mode register. At the same time, timer
internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 is output from the P41/T1OUT pin. The waveform polarity changes each time timer 1 overflows. The active edge
of the external clock CNTR0 can be switched with the bit 6 of the
interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2 is
set to “0116.”
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 is output from the P42/T3OUT pin. The waveform polarity changes each time timer 3 overflows. The active edge
of the external clock CNTR1 can be switched with the bit 7 of the
interrupt edge selection register.
b7
b0
Timer 12 mode register
(T12M: address 0028 16)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/16 or f(X CIN)/16
01 : f(XCIN)
10 : f(XIN)/32 or f(X CIN)/32
11 : f(XIN)/128 or f(X CIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR 0
11 : Not available
Timer 1 output selection bit (P4 1)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 34 mode register
(T34M: address 0029 16)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(X CIN)/128
Timer 4 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR 1
11 : Not available
Timer 3 output selection bit (P4 2)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 56 mode register
(T56M: address 002A 16)
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P52/PWM1 pin.
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/16 or f(X CIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P5 2)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 6 PWM1 Mode
Timer 6 can output a rectangular waveform with “H” duty cycle n/
(n+m) from the P52/PWM1 pin by setting the timer 56 mode register
(refer to Figure 20). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Fig. 18 Structure of timer related register
38C3 Group User’s Manual
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
XCIN
Timer 1 count source
“1”
“01” selection bit
Internal system clock
selection bit
“0”
FF16
Timer 1 (8)
1/16
XIN
RESET
Timer 1 latch (8)
1/2
“00”
1/32
“10”
STP instruction
Timer 1 interrupt request
Timer 1 count
stop bit
1/128
P41/T1OUT
“11”
P41 latch
1/2
Timer 1 output selection bit
Timer 2 latch (8)
“00”
P41 direction register
Timer 2 count source
selection bit
0116
Timer 2 (8)
Timer 2 interrupt request
“01”
Timer 2 count
stop bit
“10”
P53/CNTR0
Rising/Falling
active edge switch
CNTR0 interrupt request
Timer 3 latch (8)
“01”
“00”
P42/T3OUT
Timer 3 count source
selection bit
Timer 3 (8)
“10”
P42 latch
Timer 3 interrupt request
Timer 3 count
stop bit
“11”
1/2
Timer 3 output selection bit
Timer 4 latch (8)
“01”
P42 direction register
Timer 4 count source
selection bit
Timer 4 (8)
“00”
“10”
P54/CNTR1
Timer 4 interrupt request
Timer 4 count
stop bit
Rising/Falling
active edge switch
CNTR1 interrupt request
Timer 5 latch (8)
“1”
Timer 5 count source
selection bit
Timer 5 (8)
“0”
Timer 5 count
stop bit
“01”
Timer 6 count source
selection bit
Timer 5 interrupt request
Timer 6 latch (8)
Timer 6 (8)
“00”
Timer 6 count
stop bit
“10”
Timer 6 PWM register (8)
P52/PWM1
P52 latch
“1”
“0”
PWM
1/2
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P52 direction register
Fig. 19 Block diagram of timer
1-24
38C3 Group User’s Manual
Timer 6 interrupt request
HARDWARE
FUNCTIONAL DESCRIPTION
ts
Timer 6
count source
Timer 6
PWM mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n+m) and period : (n+m) ✕ ts) is output.
n: setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 20 Timing chart of timer 6 PWM1 mode
16-bit Timer
Timer A is a 16-bit timer that can be selected in one of four modes by
the timer A mode register and the timer A control register.
●Timer A
The timer A operates as down-count. When the timer contents reach
“000016”, an underflow occurs at the next count pulse and the timer
latch contents are reloaded. After that, the timer continues countdown. When the timer underflows, the interrupt request bit corresponding to the timer A is set to “1”.
(1) Timer mode
The count source can be selected by setting the timer A mode register.
types of delay time by a delay circuit.
When using this mode, set port P55 sharing the INT0 pin to input
mode and set port P50 sharing the TAOUT pin to output mode.
It is possible to force the timer A output to be “L” using pins INT1 and
INT2 by the timer A control register.
(4) PWM mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer A set value.
The “H” term is specified by the compare register set value.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(2) Pulse output mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TAOUT pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(3) IGBT output mode
After dummy output from the TAOUT pin, count starts with the INT0
pin input as a trigger. When the trigger is detected or the timer A
underflows, “H” is output from the the TAOUT pin.
When the count value corresponds with the compare register value,
the TAOUT output becomes “L”. When the INT0 signal becomes “H”,
the TAOUT output is forced to become “L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT 0 signal can use 4
38C3 Group User’s Manual
1-25
HARDWARE
Noise filter
(4-time same levels judgement)
INT0
Divider
Divider
Noise filter sampling
clock selection bit
XIN
Delay circuit
FUNCTIONAL DESCRIPTION
1/2
Internal trigger start
“00”, “01”, “11”
Timer A count source
selection bits
Timer A write control bit
Timer A (high-order) latch (8) Timer A (low-order) latch (8)
Timer A (high-order) (8)
“1”
INT1
Data bus
Timer A
operating
mode bits “10”
1/4
1/1
1/2
1/4
1/8
External trigger delay
time selection bits
0µs
“00”
4/f(X IN) “01”
8/f(X IN) “10”
16/f(X IN) “11”
Timer A underflow
interrupt request
Timer A (low-order) (8)
Timer A output
control bit 1
Match
“0”
Compare register (high-order) (8) Compare register (low-order) (8)
“1”
INT2
Timer A output
control bit 2
Timer A operating
mode bits
“00”, “01”, “11”
“0”
Timer A output
active edge
switch bit
“10”
“0”
R
QS
D
“1”
Q
IGBT output mode
PWM mode
P50/TAOUT
(Note) P50
direction
register
P50 latch
“0”
Q
Output selection bit
“1”
Timer A output
active edge
switch bit
Timer A start
signal
Pulse output mode
SS
T
Q
Note: The initial value of M version becomes “1” (output).
Fig. 21 Block diagram of timer A
b7
b7
b0
Timer A control register
(TACON : address 0031 16)
Timer A operating mode bits
00 : Timer mode
01 : Pulse output mode
10 : IGBT output mode
11 : PWM mode
Timer A write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch onl y
Timer A count source selection bits
0 0 : f(XIN)
0 1 : f(XIN)/2
1 0 : f(XIN)/4
1 1 : f(XIN)/8
Timer A output active edge switch bit
0 : Output starts with “L” level
1 : Output starts with “H” level
Timer A count stop bit
0 : Count operating
1 : Count stop
Timer A output selection bit (P5 0)
0 : I/O port
1 : Timer A output
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
0 0 : No delay
0 1 : ( 4/f(XIN))µs
1 0 : ( 8/f(XIN))µs
1 1 : (16/f(XIN))µs
Timer A output control bit 1 (P5 6)
0 : Not used
1 : INT1 interrupt used
Timer A output control bit 2 (P5 7)
0 : Not used
1 : INT2 interrupt used
Not used (returns “0” when read)
Fig. 22 Structure of timer A related registers
1-26
b0
Timer A mode register
(TAM : address 0030 16)
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
ts
Timer A count
source
Timer A
PWM mode
IGBT output mode
(n-m+1) ✕ ts
m ✕ ts
(n+1) ✕ ts
Note: PWM waveform (duty : (n-m+1)/(n+1) and period : (n+1) ✕ ts) is output.
n : setting value of Timer A
m : setting value of compare register
ts : period of Timer A count source
Fig. 23 Timing chart of timer A PWM, IGBT output modes
■Notes on Timer A
(1) Write order to timer A
• In the timer and pulse output modes, write to the timer A register
(low-order) first and to the timer A register (high-order) next. Do not
write to only one side.
• In the IGBT and PWM modes, write to the registers as follows:
the compare register (high- and low-order)
the timer A register (low-order)
the timer A register (high-order).
It is possible to use whichever order to write to the compare register
(high- and low-order). However, write both the compare register and
the timer A register at the same time.
(4) Set of timer A mode register
Set the write control bit to “1” (write to the latch only) when setting the
IGBT and PWM modes.
Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer A register (highorder).
(5) Output control function of timer A
When using the output control function (INT1 and INT2) in the IGBT
mode, set the levels of INT1 and INT2 to “H” in the falling edge active
or to “L” in the rising edge active before switching to the IGBT mode.
(2) Read order to timer A
• In all modes, read to the timer A register (high-order) first and to the
timer A register (low-order) next. Read order to the compare register is not specified.
• If reading to the timer A register during write operation or writing to
it during read operation, normal operation will not be performed.
(3) Write to timer A
• When writing a value to the timer A address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer A
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, an expected value may be set in the high-order counter.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it. Additionally, when performing write to the latch and the timer at the same time, the timer count
value may change large.
38C3 Group User’s Manual
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
I/O pins of serial I/O also operate as I/O port P4, and their function is
selected by the serial I/O control register 1 (address 001916).
The 38C3 group has a built-in 8-bit clock synchronous serial I/O. The
XIN
“0”
1/128
1/256
Synchronous clock
“1”
selection bit
SRDY Synchronous
“1”
circuit
SRDY output selection bit
SCLK
P47/SRDY
Data bus
1/64
P47 latch
“0”
Internal synchronous
clock selection bits
1/16
1/32
Divider
XCIN
1/8
Internal
system clock
“1” selection bit
“0”
External clock
P46 latch
“0”
P46/SCLK1
Serial I/O
interrupt request
Serial I/O counter (3)
“1”
Serial I/O port selection bit
P45 latch
“0”
P45/SOUT
“1”
Serial I/O port selection bit
Serial I/O shift register (8)
P44/SIN
P40 latch
“0”
P40/SCLK2
“1”
Serial I/O port selection bit
Fig. 24 Block diagram of serial I/O
[Serial I/O Control Registers 1, 2 (SIOCON1,
SIOCON2)] 001916, 001A16
Each of the serial I/O control registers 1, 2 contains 8 bits that select
various control parameters of serial I/O.
●Operation in serial I/O mode
Either an internal clock or an external clock can be selected as the
synchronous clock for serial I/O transfer. A dedicated divider is builtin as the internal clock, giving a choice of six clocks.
When internal clock is selected, serial I/O starts to transfer by a write
signal to the serial I/O register (address 001B16). After 8 bits have
been transferred, the SOUT pin goes to high impedance.
When external clock is selected, the clock must be controlled externally because the contents of the serial I/O register continue to shift
while the transfer clock is input. In this case, the SOUT pin does not
go to high impedance at the completion of data transfer.
The interrupt request bit is set at the end of the transfer of 8 bits,
regardless of whether the internal or external clock is selected.
1-28
When selecting internal clock and setting “1” to SIOCON20, the P40
pin can be also used as synchronous clock output pin SCLK2. At this
time, the SCLK1 pin can be used as I/O port.
Table 9 Function of P46/SCLK1 and P40/SCLK2
SIOCON16
SIOCON13
1
1
SIOCON20 P46/SCLK1 P40/SCLK2
0
SCLK1
P40
P46
SCLK2
1
SIOCON13: Serial I/O port selection bit
SIOCON16: Synchronous clock selection bit
SIOCON20: Synchronous clock output pin selection bit
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b7
b0
Serial I/O control register 1
(SIOCON1 : address 0019 16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(X IN)/8 or f(XCIN)/8
0 0 1 : f(X IN)/16 or f(X CIN)/16
0 1 0 : f(X IN)32 or f(X CIN)/32
0 1 1 : f(X IN)/64 or f(X CIN)/64
1 1 0 : f(X IN)/128 or f(X CIN)/128
1 1 1 : f(X IN)/256 or f(X CIN)/256
Serial I/O port selection bit (P4 0, P45, P46)
0 : I/O port
1 : SOUT, SCLK1, SCLK2 signal pin
SRDY output selection bit (P4 7)
0 : I/O port
1 : SRDY signal pin
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P-channel output disable bit (P4 0, P45, P46)
0 : CMOS output (in output mode)
1 : N-channel open-drain (in output mode)
Serial I/O control register 2
(SIOCON2: address 001A 16)
Synchronous clock output pin selection bit
0 : SCLK1
1 : SCLK2
Not used (returns “0” when read)
Fig. 25 Structure of serial I/O control register
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
(Note)
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O input
SIN
Receive enable signal
SRDY
Note: When internal clock is selected, the SOUT pin goes to high impedance after
transfer ends.
Interrupt request bit set
Fig. 26 Serial I/O timing (for LSB first)
38C3 Group User’s Manual
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
The 38C3 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion.
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 500 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
[A-D Conversion Register (AD)] 003316, 003416
One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 003416), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 003316).
During A-D conversion, do not read these registers.
b7
b0
A-D control register
(ADCON: address 0032 16)
Analog input pin selection bits
000: P6 0/AN0
001: P61/AN1
010: P6 2/AN2
011: P6 3/AN3
100: P6 4/AN4
101: P6 5/AN5
110: P6 6/AN6
111: P6 7/AN7
[A-D Control Register (ADCON)] 003216
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conversion.
A-D conversion is started by setting “0” in this bit.
Not used (returns “0” when read)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
b7
b0
[Channel Selector]
A-D conversion register (high-order)
(ADH: address 0034 16)
The channel selector selects one of the input ports P67/AN7–P60/
AN0 and inputs it to the comparator.
AD conversion result stored bits
[Comparator and Control Circuit]
b7
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to “1.”
b0
A-D conversion register (low-order)
(ADL: address 0033 16)
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 27 Structure of A-D control register
Data bus
b7
b0
A-D control register
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Channel selector
3
A-D control circuit
Comparator
A-D interrupt request
A-D conversion register (H)
A-D conversion register (L)
(Address 0034 16)
Resistor ladder
AV SS VREF
Fig. 28 Block diagram of A-D converter
1-30
(Address 0033 16)
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
LCD DRIVE CONTROL CIRCUIT
The 38C3 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
• LCD display RAM
• Segment output enable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for a LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
b7
segment output enable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 10 Maximum number of display pixels at each duty ratio
Duty ratio
1
2
3
4
Maximum number of display pixels
32 dots
or 8 segment LCD 4 digits
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
b0
Segment output enable register
(SEG : address 0038 16)
Segment output enable bit 0
0 : I/O ports P2 0–P23
1 : Segment output SEG 0–SEG3
Segment output enable bit 1
0 : I/O ports P2 4–P27
1 : Segment output SEG 4–SEG7
Segment output enable bit 2
0 : I/O ports P0 0–P03
1 : Segment output SEG 8–SEG11
Segment output enable bit 3
0 : I/O ports P0 4–P07
1 : Segment output SEG 12–SEG15
Segment output enable bit 4
0 : I/O ports P1 0–P13
1 : Segment output SEG 16–SEG19
Segment output enable bit 5
0 : I/O ports P1 4–P17
1 : Segment output SEG 20–SEG23
Segment output enable bit 6
0 : Output ports P3 0–P33
1 : Segment output SEG 24–SEG27
Segment output enable bit 7
0 : Output ports P3 4–P37
1 : Segment output SEG 28–SEG31
b7
b0
LCD mode register
(LM : address 0039 16)
Duty ratio selection bits
0 0 : 1 (use COM 0)
0 1 : 2 (use COM 0,COM 1)
1 0 : 3 (use COM 0–COM 2)
1 1 : 4 (use COM 0–COM 3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN )/32
1 : f(XIN )/8192 (f(X CIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 29 Structure of LCD related registers
38C3 Group User’s Manual
1-31
1-32
Fig. 30 Block diagram of LCD controller/driver
38C3 Group User’s Manual
P04 /SEG12
Segment Segment
driver
driver
P36 /SEG30 P37/SEG31
P20/SEG0 P21 /SEG1 P22/SEG2 P23 /SEG3
Selector Selector
Selector Selector Selector Selector
Bias control bit
VSS VL1 VL2 VL3
Bias control
LCD display RAM
Segment Segment Segment Segment
driver
driver
driver
driver
Address 004F16
Address 004116
Address 0040 16
Data bus
Common
driver
Common
driver
Common
driver
COM0 COM1 COM2 COM3
Common
driver
2
Timing controller
2
LCD circuit
divider division
ratio selection bits
Duty ratio selection bits
LCD enable bit
LCDCK
LCDCK count source
selection bit
f(XIN )/8192
“1”
(f(XCIN )/8192 in low-speed mode)
LCD
divider
f(XCIN )/32
“0”
HARDWARE
FUNCTIONAL DESCRIPTION
HARDWARE
FUNCTIONAL DESCRIPTION
Bias Control and Applied Voltage to LCD Power
Input Pins
Table 11 Bias control and applied voltage to VL1–VL3
Bias value
To the LCD power input pins (VL1–VL3), apply the voltage value shown
in Table 11 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by duty
ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When selecting 1-duty ratio, 1/1 bias can be used.
1/3 bias
1/2 bias
1/1 bias
(1-duty ratio)
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
VL3=VLCD
VL2=VL1=VSS
Note 1: VLCD is the maximum value of supplied voltage for the LCD panel.
Table 12 Duty ratio control and common pins used
Duty
ratio
1
2
3
4
Duty ratio selection bit
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Common pins used
COM0 (Note 1)
COM0, COM1 (Note 2)
COM0–COM2 (Note 3)
COM0–COM3
Notes 1: COM1, COM2, and COM3 are open.
2: COM2 and COM3 are open.
3: COM3 is open.
Contrast control
Contrast control
VL3
Contrast control
VL3
R1
VL3
R4
VL2
VL2
VL2
R2
VL1
VL1
R6
R4 = R5
R1 = R2 = R3
1/3 bias
VL1
R5
R3
1/2 bias
1/1 bias
Fig. 31 Example of circuit at each bias
38C3 Group User’s Manual
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
LCD Display RAM
LCD Drive Timing
Address 004016 to 004F16 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following
equation;
f(LCDCK)=
(frequency of count source for LCDCK)
(divider division ratio for LCD)
Frame frequency=
f(LCDCK)
duty ratio
Bit
7
6
5
4
3
1
SEG1
SEG3
SEG0
SEG2
004216
004316
004416
SEG5
SEG7
SEG9
SEG4
SEG6
SEG8
004516
004616
004716
004816
SEG11
SEG13
SEG10
SEG12
SEG15
SEG17
SEG19
SEG14
SEG16
SEG18
SEG21
SEG23
SEG25
SEG20
SEG22
SEG24
004916
004A16
004B16
004C16
004D16
004E16
004F16
COM3
0
SEG27
SEG26
SEG29
SEG28
SEG31
SEG30
COM2 COM1 COM0 COM3 COM2 COM1 COM0
Fig. 32 LCD display RAM map
1-34
2
Address
004016
004116
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Internal
signal
LCDCK
timing
1/4 duty
Voltage level
VL3
VL2=VL1
VSS
COM0
COM1
COM2
COM3
VL3
VSS
SEG0
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2=VL1
VSS
COM0
COM1
COM2
VL3
VSS
SEG0
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2=VL1
VSS
COM0
COM1
VL3
VSS
SEG0
ON
COM1
OFF
ON
OFF
ON
OFF
ON
OFF
COM0
COM1
COM0
COM1
COM0
COM1
COM0
1/1 duty (1/1 bias)
VL3
COM0
VL2=VL1=VSS
VL3
SEG0
VSS
OFF
ON
Fig. 33 LCD drive waveform (1/2 bias)
38C3 Group User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
Internal signal
LCDCK timing
1/4 duty
Voltage level
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
VL3
SEG0
VSS
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
VL3
SEG0
VSS
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 34 LCD drive waveform (1/3 bias)
1-36
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
φ CLOCK OUTPUT FUNCTION
The internal system clock φ can be output from port P43 by setting
the φ output control register. Set “1” to bit 3 of the port P4 direction
register when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002B 16)
φ output control bit
0 : Port function
1 : φ clock output
Not used (return “0” when read)
Fig. 35 Structure of φ output control register
38C3 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
ROM CORRECTION FUNCTION (Mask ROM
version only)
The 38C3 group has the ROM correction function correcting data at
the arbitrary addresses in the ROM area.
[ROM correct address register] 0F0216 – 0F1116
This is the register to store the address performing ROM correction.
There are two types of registers to correct up to 8 addresses: one is
the register to store the high-order address and the other is to store
the low-order address.
[ROM correct enable register 1 (RC1)] 0F0116
This is the register to enable the ROM correction function. When setting the bit corresponding to the ROM correction address to “1”, the
ROM correction function is enabled.
It becomes invalid to the addresses of which corresponding bit is “0”.
All bits are “0” at the initial state.
0F0216
ROM correct high-order address register 1
0F0316
ROM correct low-order address register 1
0F0416
ROM correct high-order address register 2
0F0516
ROM correct low-order address register 2
0F0616
ROM correct high-order address register 3
0F0716
ROM correct low-order address register 3
0F0816
ROM correct high-order address register 4
0F0916
ROM correct low-order address register 4
0F0A16
ROM correct high-order address register 5
0F0B16
ROM correct low-order address register 5
0F0C16 ROM correct high-order address register 6
0F0D16 ROM correct low-order address register 6
0F0E16
ROM correct high-order address register 7
0F0F16
ROM correct low-order address register 7
0F1016
ROM correct high-order address register 8
0F1116
ROM correct low-order address register 8
Fig. 36 Structure of ROM correct address register
[ROM correct data]
This is the register to store a correct data for the address specified by
the ROM correct address register.
■Notes on ROM correction function
1. To use the ROM correction function, transfer data to each ROM
correct data register in the initial setting.
2. Do not specify the same addresses in the ROM correct address
register.
005016
ROM correct data 1
005116
ROM correct data 2
005216
ROM correct data 3
005316
ROM correct data 4
005416
ROM correct data 5
005516
ROM correct data 6
005616
ROM correct data 7
005716
ROM correct data 8
Fig. 37 Structure of ROM correct data
b7
b0
ROM correct enable register 1(address 0F01 16)
RC1
ROM correct address 1 enable bit
0 : Disabled
1 : Enabled
ROM correct address 2 enable bit
0 : Disabled
1 : Enabled
ROM correct address 3 enable bit
0 : Disabled
1 : Enabled
ROM correct address 4 enable bit
0 : Disabled
1 : Enabled
ROM correct address 5 enable bit
0 : Disabled
1 : Enabled
ROM correct address 6 enable bit
0 : Disabled
1 : Enabled
ROM correct address 7 enable bit
0 : Disabled
1 : Enabled
ROM correct address 8 enable bit
0 : Disabled
1 : Enabled
Fig. 38 Structure of ROM correct enable register 1
1-38
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
Poweron
______
To reset the microcomputer,
RESET pin should be held at an “L” level
______
for 2 µs or more. Then the RESET pin is returned to an “H” level (the
power source voltage should be between 2.5 V and 5.5 V (M version:
2.2✽ V to 5.5 V), and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.5 V for VCC of 2.5 V (M version: less than 0.44 V for Vcc
of 2.2✽ V) when switching to the high-speed mode, a power source
voltage must be between 4.0 V and 5.5 V.
RESET
(Note)
Power source
voltage
0V
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.5 V
(M version is 2.2 V.)
RESET
VCC
Power source
voltage detection
circuit
Fig. 39 Reset circuit example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
?
?
Data
?
?
FFFC
ADL
FFFD
ADH, ADL
ADH
SYNC
XIN : about 8000 cycles
Note 1: The frequency relation of f(X IN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 40 Reset sequence
38C3 Group User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
(1) Port P0
000016
0016
(34) Timer A register (high-order)
002D16
FF16
(2) Port P0 direction register
000116
0016
(35) Compare register (low-order)
002E16
0016
(3) Port P1
000216
0016
(36) Compare register (high-order)
002F16
0016
(4) Port P1 direction register
000316
0016
(37) Timer A mode register
003016
0016
(5) Port P2
000416
0016
(38) Timer A control register
003116
0016
(6) Port P2 direction register
000516
0016
(39) A-D control register
003216
1016
(7) Port P3
000616
0016
(40) Segment output enable register
003816
0016
(8) Port P4
000816
0016
(41) LCD mode register
003916
0016
(9) Port P4 direction register
000916
0016
(42) Interrupt edge selection register
003A16
0016
(10) Port P5
000A16
0016
(43) CPU mode register
003B16 0 1 0 0 1 0 0 0
(11) Port P5 direction register
000B16
0016
(44) Interrupt request register 1
003C16
0016
(12) Port P6
000C16
0016
(45) Interrupt request register 2
003D16
0016
(13) Port P6 direction register
000D16
0016
(46) Interrupt control register 1
003E16
0016
(14) Port P7
000E16
0016
(47) Interrupt control register 2
003F16
0016
(15) Port P7 direction register
000F16
0016
(48) ROM correct enable register 1
0F0116
0016
(16) Port P8
001016
0016
0F0216
FF16
(17) Port P8 direction register
001116
0016
0F0316
FF16
(18) PULL register A
001616
0F16
0F0416
FF16
(19) PULL register B
001716
0016
0F0516
FF16
(20) Port P8 output selection register 001816
0016
0F0616
FF16
(21) Serial I/O control register 1
001916
0016
0F0716
FF16
(22) Serial I/O control register 2
001A16
0016
0F0816
FF16
(23) Timer 1
002016
FF16
0F0916
FF16
(24) Timer 2
002116
0116
0F0A16
FF16
(25) Timer 3
002216
FF16
0F0B16
FF16
(26) Timer 4
002316
FF16
0F0C16
FF16
(27) Timer 5
002416
FF16
0F0D16
FF16
(28) Timer 6
002516
FF16
0F0E16
FF16
(29) Timer 12 mode register
002816
0016
0F0F16
FF16
(30) Timer 34 mode register
002916
0016
0F1016
FF16
(31) Timer 56 mode register
002A16
0016
0F1116
FF16
(32) φ output control register
002B16
0016
(49) ROM correct high-order address
register 1
(50) ROM correct low-order address
register 1
(51) ROM correct high-order address
register 2
(52) ROM correct low-order address
register 2
(53) ROM correct high-order address
register 3
(54) ROM correct low-order address
register 3
(55) ROM correct high-order address
register 4
(56) ROM correct low-order address
register 4
(57) ROM correct high-order address
register 5
(58) ROM correct low-order address
register 5
(59) ROM correct high-order address
register 6
(60) ROM correct low-order address
register 6
(61) ROM correct high-order address
register 7
(62) ROM correct low-order address
register 7
(63) ROM correct high-order address
register 8
(64) ROM correct low-order address
register 8
(65) Processor status register
(33) Timer A register (low-order)
002C16
FF16
(66) Program counter
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
In the M version, bit 0 of the port P5 direction register becomes “1.”
Fig. 41 Internal status at reset
1-40
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
The 38C3 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor
exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
Oscillation control
(1) Stop mode
Frequency control
(1) Middle-speed mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 16 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize.
The internal system clock is the frequency of XIN divided by 8. After
reset, this mode is selected.
(2) Wait mode
(2) High-speed mode
The internal system clock is the frequency of XIN divided by 2.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of XIN and XCIN are the same as the state
before executing the WIT instruction. The internal system clock restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
■Notes on clock generating circuit
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
XCIN
XCOUT
Rf
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 42 Ceramic resonator circuit
XCIN
XIN
XCOUT
Rf
CCIN
Rd
XOUT
open
External oscillation circuit
CCOUT
VCC
VSS
Fig. 43 External clock input circuit
38C3 Group User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
XCOUT
XCIN
“1”
“0”
Port XC switch bit
XIN
XOUT
Internal system clock selection bit
(Note)
Low-speed mode
“1”
1/2
“0”
Middle-/High-speed mode
Timer 2
Timer 1
1/2
1/4
Main clock division ratio selection bit
Middle-speed mode
“1”
Timing φ
(Internal system clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
S
R
STP instruction
WIT
instruction
Q
R
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port X C switch bit to “1” .
Fig. 44 Clock generating circuit block diagram
1-42
38C3 Group User’s Manual
Q
S
R
STP instruction
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
High-speed mode
“0
“1”
CM4
4 “0”
CM
6
0”
”
M “
“1 C
”
“1
Middle-speed mode
((f(φ)=1 MHz)
(f(φ) =4 MHz)
CM7=0(8 MHz selected)
CM6=0(high-speed)
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
“0”
“1
”
” CM
4
CM
“1
6
”
“0
”
CM4
“0”
CM7=0(8 MHz selected)
CM6=1(middle-speed)
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
“0”
CM 6
“1”
“1”
Middle-speed mode
(f(φ)=1 MHz)
High-speed mode
CM 6
“1”
(f(φ) =4 MHz)
CM7=0(8 MHz selected)
CM6=0(high-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“0”
“1”
“1”
CM 7
CM 7
“0”
“0”
CM7=0(8 MHz selected)
CM6=1(middle-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
CM
1”
6
“1
”
”
“0
“
“0”
” CM
5
CM
“1
6
”
“0
”
b7
Low-speed mode
Low-speed mode
((f(φ)=16 kHz)
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“0
”
“0
C
M
5
CM 5
“0”
”
“1
“0”
CM 5
“1”
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“1”
(f(φ) =16 kHz)
CM 6
“1”
Low-speed mode
((f(φ)=16 kHz)
(f(φ) =16 kHz)
CM 6
“1”
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
b4
CPU mode register
(CPUM : address 003B 16)
CM4 : Port Xc switch bit
0: I/O port function
1: X CIN-XCOUT oscillating function
CM5 : Main clock (X IN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(X IN)/2(High-speed mode)
1: f(X IN)/8 (Middle-speed mode)
CM7: Internal system clock selection bit
0: X IN–XOUT selected (Middle-/High-speed mode)
1: X CIN–XCOUT selected (Low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended.
3: Timer,LCD operate in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting Timer 1 and Timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode.
7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 45 State transitions of system clock
38C3 Group User’s Manual
1-43
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING
Processor Status Register
A-D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
• The execution of these instructions does not change the contents
of the processor status register.
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same half of the XIN
frequency in high-speed mode.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
NOTES ON USE
Notes on Built-in EPROM Version
The P51 pin of the One Time PROM version or the EPROM version
functions as the power source input pin of the internal EPROM.
Therefore, this pin is set at low input impedance, thereby being affected easily by noise.
To prevent a malfunction due to noise, insert a resistor (approx. 5 kΩ)
in series with the P51 pin.
Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register
as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
• Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
• Using an internal clock
When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before
executing a serial I/O transfer and serial I/O automatic transfer.
1-44
38C3 Group User’s Manual
HARDWARE
DATA REQUIRED FOR MASK ORDERS AND ROM WRITING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
The built-in PROM of the blank One Time PROM version and built-in
EPROM version can be read or programmed with a general-purpose
PROM programmer using a special programming adapter.
DATA REQUIRED FOR ROM WRITING ORDERS
The following are necessary when ordering a ROM writing:
1. ROM Writing Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
Table 13 Programming adapter
Package
80P6N-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 46 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 46 Programming and testing of One Time PROM version
38C3 Group User’s Manual
1-45
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
38C3 group permits interrupts on the basis of 16 sources.
It is vector interrupts with a fixed priority system. Accordingly, when
two or more interrupt requests occur during the same sampling, the
higher-priority interrupt is accepted first. This priority is determined
by hardware, but various priority processing can be performed by
software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to
Table 14.
Table 14 Interrupt sources, vector addresses and interrupt priority
Interrupt Source Priority
Vector Addresses (Note 1)
Low
High
FFFC16
FFFD16
Interrupt Request
Generating Conditions
Remarks
At reset
Non-maskable
FFFB16
FFFA16
At detection of either rising or falling edge
of INT0 input
External interrupt
(active edge selectable)
3
FFF916
FFF816
At detection of either rising or falling edge
of INT1 input
External interrupt
(active edge selectable)
INT2
4
FFF716
FFF616
At detection of either rising or falling edge
of INT2 input
External interrupt
(active edge selectable)
Serial I/O
5
FFF516
FFF416
At completion of serial I/O data transmit/receive
Valid when serial I/O is selected
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
6
7
8
9
10
11
12
13
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
At timer A underflow
At timer 1 underflow
At timer 6 underflow
At detection of either rising or falling edge
of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
14
FFE316
FFE216
At detection of either rising or falling edge
of CNTR1 input
External interrupt
(active edge selectable)
Key input (Keyon wake-up)
A-D conversion
15
FFE116
FFE016
At falling of port P8 (at input) input logical
level AND
External interrupt
(falling valid)
16
FFDF16
FFDE16
At completion of A-D conversion
Valid when A-D conversion interrupt is
selected
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
Reset (Note 2)
INT0
1
2
INT1
At timer 2 underflow
At timer 4 underflow
At timer 5 underflow
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
1-46
STP release timer underflow
At timer 3 underflow
38C3 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution.
Figure 47 shows a timing chart after an interrupt occurs, and Figure
48 shows the time up to execution of the interrupt processing routine.
φ
SYNC
RD
WR
Address bus
PC
Data bus
Not used
S, SPS
S-1, SPS S-2, SPS
PCH
P CL
PS
BH
BL
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal which cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “0116”
Fig. 47 Timing chart after interrupt occurs
Interrupt request occurs
Interrupt operation starts
Waiting time for
pipeline postprocessing
Main routine
0 to 16 cycles
2 cycles
Push onto
stack vector
fetch
Interrupt processing routine
5 cycles
7 to 23 cycles (4 MHz, 1.75 µs to 5.75 µs)
Fig. 48 Time up to execution of interrupt processing routine
38C3 Group User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
A-D conversion is started by setting AD conversion completion bit to
“0.” During A-D conversion, internal operations are performed as follows.
1. After the start of A-D conversion, A-D conversion register goes to
“0016.”
2. The highest-order bit of A-D conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit of
A-D conversion register becomes “1.” When Vref > VIN, the highest-order bit becomes “0.”
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(X IN) = 8
MHz) after it is started, and the result of the conversion is stored into
the A-D conversion register.
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
Table 15 Relative formula for a reference voltage V REF of A-D
converter and Vref
When n = 0
Vref = 0
VREF
✕n
1024
n: Value of A-D converter (decimal numeral)
When n = 1 to 1023
Vref =
Table 16 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
Second comparison
✽1
1
0
0
0
0
0
0
0
0
Third comparison
✽1 ✽ 2
1
0
0
0
0
0
0
0
After completion of tenth
comparison
~
~
~
~
A result of A-D conversion
✽ 1 ✽2
✽3 ✽ 4 ✽5 ✽ 6
✽7 ✽8 ✽9 ✽10
✽1–✽10: A result of the first comparison to the tenth comparison
1-48
0
38C3 Group User’s Manual
VREF
2
VREF
±
2
VREF
4
VREF
±
2
VREF
4
±
VREF
8
VREF
±
2
VREF
4
±
••••
±
VREF
1024
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 49 shows the A-D conversion equivalent circuit, and Figure
50 shows the A-D conversion timing chart.
VCC
VSS
About 2 kΩ
VCC
VSS
V IN
AN0
Sampling
clock
AN1
C
AN2
Chopper
amplifier
AN3
AN4
A-D conversion register (high-order)
AN5
AN6
AN7
A-D conversion register
(low-order)
b2 b1 b0
A-D control
register
AD conversion interrupt request
Vref
VREF
Built-in
D-A converter
Reference
clock
AVSS
Fig. 49 A-D conversion equivalent circuit
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 50 A-D conversion timing chart
38C3 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
MEMORANDUM
1-50
38C3 Group User’s Manual
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
I/O port
Timer
Serial I/O
LCD controller
A-D converter
ROM correct function
Reset circuit
Clock generating circuit
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory map
Address
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
000A16
000B16
Port P5 (P5)
Port P5 direction register (P5D)
000C16
Port P6 (P6)
000D16
Port P6 direction register (P6D)
000E16
Port P7 (P7)
000F16
Port P7 direction register (P7D)
001016
Port P8 (P8)
001116
Port P8 direction register (P8D)
001616
PULL register A (PULLA)
001716
PULL register B (PULLB)
001816
Port P8 output selection register (P8SEL)
Fig. 2.1.1 Memory map of I/O port relevant registers
2-2
38C3 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 1016)
b
0
1
2
3
4
5
6
7
Name
Port Pi0
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8)
Port P7
b7 b6 b5 b4 b3 b2 b1 b0
Port P7
(P7: address 0E16)
b
Name
0 Port P70
1 Port P71
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 2.1.3 Structure of port P7
38C3 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
Port P0 direction register, Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 direction register (P0D: address 0116)
Port P1 direction register (P1D: address 0316)
b
Name
0 Ports P0/P1
direction register
Functions
0 : All bits of ports P0/P1
input mode
1 : All bits of ports P0/P1
output mode
1 Nothing is arranged for these bits. When these
2 bits are read out, the contents are undefined.
3
4
5
6
7
At reset R W
0
✕
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Note: Ports P0 and P1 are switched to input and output by each port.
When b0 of corresponding port direction register is set to “0”, all
8 bits of port become input port. When b0 of corresponding port
direction register is set to “1”, all 8 bits of port become output
port. Nothing is arranged for b1 to b7 of port P0 and port P1
direction registers. These are write disabled bits.
Fig. 2.1.4 Structure of Port P0 direction register and port P1 direction register
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 2, 4, 5, 6, 8)
(PiD: addresses 0516, 0916, 0B16, 0D16, 1116)
b
Name
Functions
At reset R W
0 Port Pi direction
register
1
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
(Note)
0
2
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
3
4
5
6
7
0
0
0
0
0
0
Note: Bit 1 of the port P5 direction register (address 0B16) does not have
direction register function, because P51 is an input port. When writing to
bit 1 of the port P5 direction register, write “0” to the bit.
Fig. 2.1.5 Structure of Port Pi direction register (i = 2, 4, 5, 6, 8)
2-4
38C3 Group User’s Manual
APPLICATION
2.1 I/O port
Port P7 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P7 direction register
(P7D: address 0F16)
b
Name
Functions
0 Port P7 direction
register
1
0 : Port P70 input mode
1 : Port P70 output mode
0 : Port P71 input mode
1 : Port P71 output mode
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
✕
0
✕
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 2.1.6 Structure of Port P7 direction register
PULL register A
b7 b6 b5 b4 b3 b2 b1 b0
PULL register A
(PULLA: address 1616)
b
Name
Functions
At reset R W
Port P00–P07
0: No pull-down control
1: Pull-down control
pull-down control
0: No pull-down control
Port P10–P17
1: Pull-down control
pull-down control
0: No pull-down control
Port P20–P27
1: Pull-down control
pull-down control
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
0: No pull-up control
4 Port P70, P71
1: Pull-up control
pull-up control
5 Port P80–P87
0: No pull-up control
1: Pull-up control
pull-up control
6 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
1
2
3
1
1
1
0
0
Note: The pin which is set to output port is cut off from pull-up control.
Fig. 2.1.7 Structure of PULL register A
38C3 Group User’s Manual
2-5
APPLICATION
2.1 I/O port
PULL register B
b7 b6 b5 b4 b3 b2 b1 b0
PULL register B
(PULLB: address 1716)
b
Name
Functions
At reset R W
0: No pull-up control
0 Port P40–P43
1: Pull-up control
pull-up control
0: No pull-up control
1 Port P44–P47
1: Pull-up control
pull-up control
0: No pull-up control
2 Port P50, P52, P53
1: Pull-up control
pull-up control
3 Port P54–P57
0: No pull-up control
1: Pull-up control
pull-up control
0: No pull-up control
4 Port P60–P63
1: Pull-up control
pull-up control
5 Port P64–P67
0: No pull-up control
1: Pull-up control
pull-up control
6 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
0
0
0
Note: The pin which is set to output port is cut off from pull-up control.
Fig. 2.1.8 Structure of PULL register B
Port P8 output selection register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8 output selection register (P8SEL: address 1816)
b
Name
Functions
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
1
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
2
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
3
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
4
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
5
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
6
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
7
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
Fig. 2.1.9 Structure of Port P8 output selection register
2-6
At reset R W
0 Port P8 output
selection register
38C3 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Pins
P3
Termination
Open at “H” output state.
P0, P1, P2, P4, • Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to
P50, P52–P57, P6, 10 kΩ.
P7, P8
• Set to the output mode and open at “L” or “H” output state.
P5 1
Connect to V CC or VSS through a resistor of 1 kΩ to 10 kΩ.
VL 1–VL3
Connect to Vss (GND).
COM 0–COM3
Open
VREF
Open
XOUT
Open (only when using external clock)
Connect to VSS (GND).
AVSS
38C3 Group User’s Manual
2-7
APPLICATION
2.1 I/O port
2.1.4 Notes on I/O port
(1) Notes in standby state
In standby state]1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
l Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
]1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying port latch of I/O port with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ]2, the value of the
unspecified bit may be changed.
l Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
]2 Bit managing instructions: SEB and CLB instructions
(3) Pull-up/Pull-down control
When each port which has built-in pull-up/pull-down resistor (P0, P1, P2, P4, P50, P52–P57, P6, P7,
P8) is set to output port, pull-up/pull-down control of corresponding port become invalid. (Pull-up/Pulldown cannot be set.)
l Reason
Pull-up control is valid only when each direction register is set to the input mode.
2-8
38C3 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or VSS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pin INT or others, select the V CC
pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
38C3 Group User’s Manual
2-9
APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
002016
Timer 1 (T1)
002116
Timer 2 (T2)
002216
Timer 3 (T3)
002316
Timer 4 (T4)
002416
Timer 5 (T5)
002516
Timer 6 (T6)
002716
Timer 6 PWM register (T6PWM)
002816
Timer 12 mode register (T12M)
002916
Timer 34 mode register (T34M)
002A16
Timer 56 mode register (T56M)
002C16
Timer A register (low-order) (TAL)
002D16
Timer A register (high-order) (TAH)
002E16
Compare register (low-order) (CONAL)
002F16
Compare register (high-order) (CONAH)
003016
Timer A mode register (TAM)
003116
Timer A control register (TACON)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
2-10
38C3 Group User’s Manual
APPLICATION
2.2 Timer
2.2.2 Relevant registers
(1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
0 • Set timer i count value.
1 • The value set in this register is written to both
2 the timer i and the timer i latch at one time.
3 • When the timer i is read out, the count value
4 of the timer i is read out.
5
6
7
At reset R W
1
1
1
1
1
1
1
1
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 the timer 2 and the timer 2 latch at one time.
3 • When the timer 2 is read out, the count value
4 of the timer 2 is read out.
5
6
7
At reset R W
1
0
0
0
0
0
0
0
Fig. 2.2.3 Structure of Timer 2
38C3 Group User’s Manual
2-11
APPLICATION
2.2 Timer
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
0
1
2
3
4
5
6
Functions
• In timer 6 PWM1 mode
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
Fig. 2.2.4 Structure of Timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
Name
0
Timer 1 count stop
bit
Timer 2 count stop
bit
Timer 1 count
source selection
bits
1
2
3
4 Timer 2 count
source selection
bits
5
Functions
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
0 0: f(XIN)/16 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
b5 b4
0 0: Timer 1 underflow
0 1: f(XCIN)
1 0: External count input
CNTR0
1 1: Not available
0: I/O port
6 Timer 1 output
selection bit (P41) 1: Timer 1 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 2.2.5 Structure of Timer 12 mode register
2-12
At reset R W
38C3 Group User’s Manual
0
0
0
0
0
0
APPLICATION
2.2 Timer
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
Name
0
Timer 3 count stop
bit
Timer 4 count stop
bit
Timer 3 count
source selection
bits
1
2
3
4 Timer 4 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1
1 1: Not available
0: I/O port
6 Timer 3 output
selection bit (P42) 1: Timer 3 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 2.2.6 Structure of Timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
Name
0
Timer 5 count stop
bit
Timer 6 count stop
bit
Timer 5 count
source selection bit
Timer 6 operation
mode selection bit
Timer 6 count
source selection
bits
1
2
3
4
5
Functions
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0: f(XIN)/16 or f(XCIN)/16
1: Timer 4 underflow
0: Timer mode
1: PWM mode
b5 b4
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
6 Timer 6 (PWM)
output selection bit
(P52)
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.2.7 Structure of Timer 56 mode register
38C3 Group User’s Manual
2-13
APPLICATION
2.2 Timer
(2) 16-bit timer
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer A register (low-order, high-order)
(TAL, TAH: addresses 2C16, 2D16)
b
Functions
At reset R W
0 • Set timer A count value.
1 • When the timer A write control bit of the timer
A mode register is “0”, the value is written to
2
timer A and the latch at one time.
3
When the timer A write control bit of the timer
A mode register is “1”, the value is written only
4
to the latch.
5
• The timer A count value is read out by reading
6
this register.
7
1
1
1
1
1
1
1
1
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes.
2: Read both registers in order of TAH and TAL following.
3: Write both registers in order of TAL and TAH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 2.2.8 Structure of Timer A register (low-order, high-order)
Compare register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Compare register (low-order, high-order)
(CONAL, CONAH: addresses 2E16, 2F16)
b
Functions
At reset R W
0 • Set compare register value.
0
1
0
2
3
0
4
0
5
0
6
7
0
0
0
Note: Write registers in order of CONAH, CONAL, TAL, and TAH
following.
Fig. 2.2.9 Structure of Compare register (low-order, high-order)
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38C3 Group User’s Manual
APPLICATION
2.2 Timer
Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A mode register
(TAM: address 3016)
b
Name
0 Timer A operating
mode bits
1
2 Timer A write control
bit
3 Timer A count source
selection bits
4
5 Timer A output active
edge switch bit
Functions
b1b0
At reset R W
0 0: Timer mode
0 1: Pulse output mode
1 0: IGBT output mode
1 1: PWM mode
0
0: Write data to both timer
latch and timer
1: Write data to timer latch
0
b4b3
0
0 0: f(XIN)
0 1: f(XIN)/2
1 0: f(XIN)/4
1 1: f(XIN)/8
0: Output starts with “L” level
1: Output starts with “H” level
6 Timer A count stop bit 0: Count operating
0
0
0
0
1: Count stop
7 Timer A output
selection bit (P50)
0: I/O port
1: Timer A output
0
Fig. 2.2.10 Structure of Timer A mode register
Timer A control register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A control register
(TACON: address 3116)
b
Name
0 Noise filter sampling
clock selection bit
1 External trigger delay
time selection bits
2
Functions
0: f(XIN)/2
1: f(XIN)/4
0
b2b1
0
0 0: No delay
0 1: (4/f(XIN))µs
1 0: (8/f(XIN))µs
1 1: (16/f(XIN))µs
3 Timer A output control 0: Not used
bit 1 (P56)
0
0
1: INT1 interrupt used
4 Timer A output control 0: Not used
bit 2 (P57)
At reset R W
0
1: INT2 interrupt used
5 Nothing is arranged for these bits. These are write
6 disabled bits. When these bits are read out, the
7 contents are “0”.
0
0
0
Fig. 2.2.11 Structure of Timer A control register
38C3 Group User’s Manual
2-15
APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
3 Serial I/O interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
4 Timer A interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.12 Structure of Interrupt request register 1
2-16
At reset R W
0 INT0 interrupt
request bit
38C3 Group User’s Manual
APPLICATION
2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
Timer
6
interrupt
0 : No interrupt request issued
2
1 : Interrupt request issued
request bit
0 : No interrupt request issued
3 CNTR0 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
4 CNTR1 interrupt
1 : Interrupt request issued
request bit
Key
input
interrupt
0 : No interrupt request issued
5
1 : Interrupt request issued
request bit
0 : No interrupt request issued
6 AD conversion
interrupt request bit 1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.13 Structure of Interrupt request register 2
38C3 Group User’s Manual
2-17
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
0 INT0 interrupt
enable bit
1 INT1 interrupt
enable bit
2 INT2 interrupt
enable bit
3 Serial I/O interrupt
enable bit
4 Timer A interrupt
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.2.14 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
0 Timer 4 interrupt
0 : Interrupt disabled
enable bit
1 : Interrupt enabled
1 Timer 5 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
2 Timer 6 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
3 CNTR0 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0 : interrupt disabled
4 CNTR1 interrupt
1 : Interrupt enabled
enable bit
5 Key input interrupt 0 : interrupt disabled
1 : Interrupt enabled
enable bit
6 AD conversion
0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
Fig. 2.2.15 Structure of Interrupt control register 2
2-18
38C3 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of event interval (Timer 1 to Timer 6, Timer A: timer mode)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs.
<Use>
•Generating of an output signal timing
•Generating of a wait time
[Function 2] Control of cyclic operation (Timer 1 to Timer 6, Timer A: timer mode)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generating of cyclic interrupts
•Clock function (measurement of 1 s); see “(2) Timer application example 1”
•Control of a main routine cycle
[Function 3] Output of rectangular waveform
(Timer 1, Timer 3, Timer 6, Timer A: pulse output mode)
The output level of the T1OUT pin, T3OUT pin, PWM 1 pin or TAOUT pin is inverted each time the timer
underflows.
<Use>
•Piezoelectric buzzer output; see “(3) Timer application example 2”
•Generating of the remote control carrier waveforms
[Function 4] Count of external pulses (Timer 2, Timer 4)
External pulses input to the CNTR 0 pin, CNTR1 pin are counted as the timer count source (in the
event counter mode).
<Use>
•Frequency measurement; see “(4) Timer application example 3”
•Division of external pulses
•Generating of interrupts due to a cycle using external pulses as the count source; count of a reel pulse
[Function 5] Output of PWM signal (Timer 6)
“H” interval and “L” interval are specified, respectively, and the output of pulses from P52/PWM 1
pin is repeated.
<Use>
•Control of electric volume
[Function 6] Output of IGBT control signal (Timer A: IGBT output mode)
The external signal which is input to INT0 pin is used as trigger, and the period and “H” interval
are specified, respectively, and the output of pulses from P50/TA OUT pin is repeated.
<Use>
•IGBT control of IH heat equipment; see “(5) Timer application example 4”
•IGBT control to magnetron
[Function 7] Output of PWM signal (Timer A: PWM mode)
The cycle and “H” interval are specified, respectively, and the output of pulses from P50/TAOUT pin
is repeated.
<Use>
•Control of electric volume
•IGBT control of IH heat equipment
38C3 Group User’s Manual
2-19
APPLICATION
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 1 s)
Outline: The input clock is divided by the timer so that the clock can count up at 1 s intervals.
Specifications: •The clock f(X IN) = 4.19 MHz (222 Hz) is divided by the timer.
•The timer 3 interrupt request bit is checked in main routine, and if the interrupt
request is issued, the clock is counted up.
• The timer 1 interrupt occurs every 244 µs to execute processing of other interrupts.
Figure 2.2.16 shows the timers connection and setting of division ratios; Figure 2.2.17 shows the
relevant registers setting; Figure 2.2.18 shows the control procedure.
Timer 1 count
source selection bit
f(XIN)
4.19 MHz
1/16
Timer 1
Timer 2
Timer 3
1/64
1/256
1/16
Timer 3 interrupt request bit
0/1
1 second
0/1
244 µs
Timer 1 interrupt
request bit
Fig. 2.2.16 Timers connection and setting of division ratios
2-20
38C3 Group User’s Manual
0 : No interrupt request issued
1 : Interrupt request issued
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
T12M
b0
0 0 0 0 0 0 0 1
Timer 1 count stop; Clear to “0” when starting count.
Timer 2 count: In progress
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1’s underflow
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
T34M
0 0
b0
0 1
0
Timer 3 count: In progress
Timer 3 count source: Timer 2’s underflow
Timer 3 output selection: I/O port
Timer 1 (address 2016)
b7
T1
b0
3F16
Timer 2 (address 2116)
b7
T2
b0
Set “division ratio – 1”.
[ T1 = 63 (3F16), T2 = 255 (FF16), T3 = 15 (0F16) ]
FF16
Timer 3 (address 2216)
b7
T3
b0
0F16
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0 0 1
Timer 1 interrupt: Enabled
Timer 2 interrupt: Disabled
Timer 3 interrupt: Disabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
Timer 1 interrupt request (becomes “1” at 244 µs intervals)
Timer 2 interrupt request
Timer 3 interrupt request (becomes “1” at 1 s intervals)
Fig. 2.2.17 Relevant registers setting
38C3 Group User’s Manual
2-21
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
.....
•All interrupts disabled
T12M
T34M
IREQ1
ICON1
(address 2816)
(address 2916)
(address 3C16)
(address 3E16)
000000012
00XX01X02
000XXXXX2
001XXXXX2
•Connection of Timers 1 to 3
(address 2016)
(address 2116)
(address 2216)
3 F1 6
FF16
0 F1 6
•Setting “Division ratio – 1” to Timers 1 to 3
•Setting of Interrupt request bits of Timers 1 to 3 to “0”
•Timer 1 interrupt enabled, Timers 2 and 3 interrupts disabled
.....
T1
T2
T3
.....
T12M
(address 2816), bit0
0
•Timer count start
.....
CLI
•Interrupts enabled
Y
Clock is stopped ?
•Judgment whether time is not set or time is being set
N
0
IREQ1 (address 3C16), bit7 ?
•Confirmation that 1 sec. has passed
(Check of Timer 3 interrupt request bit)
1
IREQ1 (address 3C16), bit7
•Interrupt request bit cleared
(Clear it by software when not using the interrupt.)
0
✽
Clock count up
Second to Year
•Clock count up
Main processing
.....
•Adjust the main processing so that all processing in the loop ✽ will
be processed within 1 second period.
<Procedure for end of clock setting> (Note)
T2
T3
IREQ1
(address 2116)
(address 2216)
(address 3C16), bit7
FF16
0 F1 6
0
•Set Timers again when starting clock from 0 second after
end of clock setting.
The procedure is Timer 2 setting followed by Timer 3 setting.
•Do not set Timer 1 again because Timer 1 is used to
generate the interrupt at 244 µs intervals.
Note : Perform proc edure f or end o f clock sett ing o nly when end of
clock sett ing.
Fig. 2.2.18 Control procedure
2-22
38C3 Group User’s Manual
APPLICATION
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (222 Hz) into about
2 kHz (2048 Hz), is output from the P4 2/T3 OUT pin.
•The level of the P4 2/T3 OUT pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.2.19 shows a peripheral circuit example, and Figure 2.2.20 shows the timers connection and
setting of division ratios. Figures 2.2.21 shows the relevant registers setting, and Figure 2.2.22
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
T3OUT output
T3OUT
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the underflow
output period of the timer 3 can be 244 µs. 38C3 Group
Fig. 2.2.19 Peripheral circuit example
Timer 3 count source
selection bit
Timer 3
f(XIN)
4.19 MHz
1/16
1/64
Fixed
1/2
T3OUT
Fig. 2.2.20 Timers connection and setting of division ratios
38C3 Group User’s Manual
2-23
APPLICATION
2.2 Timer
Timer 34 mode register (address 2916)
b7
T34M
b0
0 1
0 0
0
Timer 3 count: In progress
Timer 3 count source: f(XIN)/16
Timer 3 output selection: Buzzer output in progress = “1”
Buzzer output stopped = “0”
Timer 3 (address 2216)
b7
b0
Set “division ratio – 1”; 63 (3F16).
3F16
T3
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0
Timer 3 interrupt: Disabled
Fig. 2.2.21 Relevant registers setting
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
•All interrupts disabled
.....
P4D
P4
(address 0916), bit6
(address 0816), bit6
•Port stat e setting at buzzer output stopped; “H” level output
1
1
.....
ICON1 (address 3E16), bit7
T34M (address 2916)
T3
(address 2216)
0
00XX00X02
3 F1 6
•Timer 3 interrupt disabled
•T3OUT output stopped; Buzzer output stopped
.....
•Interrupts enabled
CLI
Main processing
.....
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Yes
Buzzer request ?
No
T34M
T3
(address 2916), bit 6
(address 2216)
0
3 F1 6
T34M (address 2916), bit 6
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.2.22 Control procedure
2-24
1
38C3 Group User’s Manual
APPLICATION
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P5 4/CNTR 1 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P5 4/CNTR 1 pin and counted by the timer 4.
•A count value of timer 4 is read out at about 2 ms intervals, the timer 1 interrupt
interval. When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid count.
Figure 2.2.23 shows the judgment method of valid/invalid of input pulses; Figure 2.2.24 shows the
relevant registers setting; Figure 2.2.25 shows the control procedure.
Input pulse
@
@
@
@
71.4 µs or more
(less than 14 kHz)
@
@
@
@
71.4 µs
(14 kHz)
@
50 µs
(20 kHz)
Valid
Invalid
2 ms = 28 counts
71.4 µs
@
@
@
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
Fig. 2.2.23 Judgment method of valid/invalid of input pulses
38C3 Group User’s Manual
2-25
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
T12M
b0
0 0
0 0
1
Timer 1 count stop; Clear to “0” when starting count.
Timer 1 count source: f(XIN)/16
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
T34M
0
b0
1 0
0
Timer 4 count: In progress
Timer 4 count source: External count input CNTR1
Timer 1 (address 2016)
b7
b0
T1
Set “division ratio – 1”; 63 (3F16).
3 F1 6
Timer 4 (address 2316)
b7
b0
T4
Set 255 (FF16) just before counting pulses.
(After a certain time has passed, the number of
input pulses is decreased from this value.)
FF16
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer 1 interrupt: Enabled
Interrupt control register 2 (address 3F16)
b7
b0
0
ICON2
Timer 4 interrupt: Disabled
Interrupt request register 2 (address 3D16)
b7
IREQ2
b0
0
Timer 4 interrupt request
( “1” of this bit when reading the count value
indicates the 256 or more pulses input in the
condition of Timer 4 = 255)
Fig. 2.2.24 Relevant registers setting
2-26
38C3 Group User’s Manual
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
•All interrupts disabled
SEI
.....
T12M (address 2816)
(address 2016)
T1
T34M (address 2916)
(address 2316)
T4
ICON1 (address 3E16), bit 5
ICON2 (address 3F16), bit 0
•Set div ision rat io s o that Timer 1 inte rrupt will oc cur at 244 µs interv als .
•External pulses input from CNTR1 pin selected as Timer 4’s count source
•Setting Timer 4 count value
•Timer 1 interrupt enabled
•Timer 4 interrupt disabled
0
•Timer 1 count start
.....
00XX00X12
3 F1 6
0X10XX0X2
FF16
1
0
T12M (address 2816), bit 0
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
1/8
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Notes 1: When using Index X mode flag (T)
2: When using Decimal mode flag (D)
•Pus hing regis ters u sed in in terrupt process routine
1
IREQ2 (address 3D16), bit 0 ?
(A)
•Set so that pulse judgment process will be performed once each time
Timer 1 interrupt occurs 8 times, at 2 ms intervals.
T4 (address 2316)
•Processing as out of range when the count value is 256 or more
•Count value read
•Storing count value into Accumulator (A)
In range
214 < (A) < 228
•Compare the read value with
reference value.
•Store the comparison result to flag Fpulse.
Out of range
Fpulse
Fpulse
0
T4
(address 2316)
IREQ2 (address 3D16), bit 0
FF16
0
1
•Initialization of counter value
•Timer 4 interrupt request bit cleared
Process judgment result
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.25 Control procedure
38C3 Group User’s Manual
2-27
APPLICATION
2.2 Timer
(5) Timer application example 4: Output of IGBT control signal
Outline: Synchronized variable PWM signal is output in “H” term.
When a signal is input to INT0 pin before timer underflow during “L” output, timer restarts.
Specifications: •The signal, of which “H” level width is 5 µs and cycle is 20 µs, is output from the
P5 0/TAOUT pin.
However, if “H” is input to INT0 pin during “L” output, timer restarts from “H” output.
<Example>
When f(X IN) = 8 MHz, the count source is 125 ns.
Figure 2.2.26 shows the timers connection and setting of division ratio; Figure 2.2.27 shows the
relevant registers setting; Figure 2.2.28 shows the control procedure.
f(XIN) = 8 MHz
Timer A count source
selection bit
Timer A
Timer A interrupt
request bit
1/1
1/160
Timer A restart
20 µs
125 ns
Fig. 2.2.26 Timers connection and setting of division ratios
2-28
38C3 Group User’s Manual
APPLICATION
2.2 Timer
Timer A mode register (address 3016)
b7
TAM
b0
1 1 0 0 0 1 1 0
IGBT output mode
Writing of latch only
Timer A count source: f(XIN)
Timer A output active edge: Starting from “L” output ✽1
Timer A count stop; Clear to “0” when count starts
Timer A output selection: Timer A output
Timer A control register (address 3116)
b7
b0
TACON
0 0 0
Noise filter: f(XIN)/2
External trigger delayed: No delay
Compare register (low-order) (address 2E16)
b7
b0
7716
CONAL
Compare register (high-order) (address 2F16)
b7
CONAH
Set “119 (007716)” before start of timer A.
b0
0016
Timer A register (low-order) (address 2C16)
b7
TAL
b0
9 F1 6
Timer A register (high-order) (address 2D16)
b7
TAH
Set “159 (009F16)” before start of timer A.
b0
0016
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0
0
INT0 interrupt: Disabled
Timer A interrupt: Disabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
Timer A interrupt request (becomes “1” when Timer A underflows) ✽2
✽1 Use this bit with “0” (start from “L” output) in the IGBT output mode.
✽2 This bit becomes “1” even when a signal is input from the INT0 pin in the IGBT output mode.
Fig. 2.2.27 Relevant registers setting
38C3 Group User’s Manual
2-29
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
TAM
TACON
CONAL
CONAH
TAL
TAH
ICON1
(address 3016)
(address 3116)
(address 2E16)
(address 2F16)
(address 2C16)
(address 2D16)
(address 3E16)
110001102
XXXXX0002
7716
0016
9F16
0016
XXX0XXX02
•Timer A: IGBT output mode
•Noise filter: f(XIN); External trigger delayed: No delay
•Setting compare register value
“H” width 5 µs
•Setting timer A count value
•Timer A, INT0 interrupt: Disabled
.....
•Interrupts enabled
CLI
.....
TAM
(address 3016), bit 6
0
•Timer A count start
009F16
007716
000016
P50/TAOUT
Timer A start
Match with
compare
register
Timer A
underflow
Input from
INT0 pin
Fig. 2.2.28 Control procedure
2-30
[
38C3 Group User’s Manual
Cycle 20 µs setting
]
APPLICATION
2.2 Timer
2.2.4 Notes on timer A (PWM mode and IGBT output mode)
(1) When timer starts first or last value of compare register is “000016”
After “L” level (timer A output active edge switch bit is “0”; when starting from “L” output) is output
during 2 cycles (until timer underflows two times), PWM output or IGBT output starts.
Reason: When data is written to timer A and compare register, value of timer A and value of
compare register are renewed at timer underflow. In case of this, compare register value
and timer value are compared before renewal, so that they are judged to be equal, and
TA OUT output becomes “L”. (Timer A output active edge switch bit = “0”: when starting from
“L” output)
Timer A underflow should cause “H” output, but the match have the priority. (see “Figure
2.2.29”)
Compare register value is value which is written at ➀
Compare register value is
“000016”
(last value or initial value)
➀
Timer A start
Timer A underflow
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.29 PWM output and IGBT output (1)
(2) When compare register is set to “000016” (last value is except “000016”)
Next 1 cycle of the cycle in which data is written to timer A and compare register is output “H”, and
“L” is output from the next cycle. (timer A output active edge switch bit = “0”: when starting from “L”
output)
(see “Figure 2.2.30”)
Compare register value is
last value
Timer A underflow
Compare register value is “000016”
Timer A underflow
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.30 PWM output and IGBT output (2)
38C3 Group User’s Manual
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APPLICATION
2.2 Timer
(3) When timer A and compare register have same value
TAOUT output becomes “H” with underflow immediately after data is written to timer A and compare
register. TA OUT output becomes “L” when timer A is reloaded and the value matches with compare
register. This “H” output width becomes 1 count of timer A count source. (timer A output active edge
switch bit =“0”: when starting from “L” output) (see “Figure 2.2.31”)
Timer A value–compare register value
Timer A count source
1 count width
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.31 PWM output and IGBT output (3)
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38C3 Group User’s Manual
Timer A underflow
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
001916 Serial I/O control register 1 (SIOCON1)
001A16 Serial I/O control register 2 (SIOCON2)
001B16 Serial I/O register (SIO)
003C16 Interrupt request register 1 (IREQ1)
003D16
003E16 Interrupt control register 1 (ICON1)
Fig. 2.3.1 Memory map of registers relevant to Serial I/O
2.3.2 Relevant registers
Serial I/O control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 1
(SIOCON1: address 1916)
b
Name
0 Internal
synchronous clock
1 selection bits
2
Functions
b2b1b0
0 0 0: f(XIN)/8 or f(XCIN)/8
0 0 1: f(XIN)/16 or f(XCIN)/16
0 1 0: f(XIN)/32 or f(XCIN)/32
0 1 1: f(XIN)/64 or f(XCIN)/64
1 1 0: f(XIN)/128 or f(XCIN)/128
1 1 1: f(XIN)/256 or f(XCIN)/256
At reset R W
0
0
0
3 Serial I/O port
selection bit
(P40, P45, P46)
0: I/O port
1: SOUT, SCLK1, SCLK2
signal pin
0
4 SRDY output
selection bit (P47)
5 Transfer direction
selection bit
6 Synchronous clock
selection bit
7 P-channel output
disable bit
(P40, P45, P46)
0: I/O port
1: SRDY signal pin
0: LSB first
1: MSB first
0: External clock
1: Internal clock
0: CMOS output
(in output mode)
1: N-channel open-drain
output (in output mode)
0
0
0
0
Fig. 2.3.2 Structure of Serial I/O control register 1
38C3 Group User’s Manual
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APPLICATION
2.3 Serial I/O
Serial I/O control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 2
(SIOCON2: address 1A16)
b
Name
Functions
0 Synchronous clock 0: SCLK1
output pin selection 1: SCLK2
bit
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read
3 out, the contents are “0”.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
Fig. 2.3.3 Structure of Serial I/O control register 2
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
3 Serial I/O interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
4 Timer A interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.4 Structure of Interrupt request register 1
2-34
At reset R W
0 INT0 interrupt
request bit
38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
0 INT0 interrupt
enable bit
1 INT1 interrupt
enable bit
2 INT2 interrupt
enable bit
3 Serial I/O interrupt
enable bit
4 Timer A interrupt
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.3.5 Structure of Interrupt control register 1
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APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.6 shows connection examples with peripheral ICs equipped with the CS pin.
(1) Only transmission
(Using SIN pin as I/O port)
Port
(2) Transmission and reception
CS
Port
CS
SCLK1
CLK
SCLK1
CLK
SOUT
DATA
SOUT
IN
S IN
Peripheral IC
38C3 group
38C3 group
(3) Transmission and reception
(When connecting SIN1 with SOUT1)
(When connecting IN with OUT in
peripheral IC)
Port
OUT
Peripheral IC
(EEPROM etc.)
(4) Connection of plural IC
Port
CS
CS
SCLK1
CLK
SCLK1
CL K
SOUT
IN
SOUT
IN
S IN
38C3 group✽1
S IN
OUT
Port
Peripheral IC ✽2
(EEPROM etc.)
O UT
Peripheral IC 1
38C3 group
✽1: Select an N-channel open-drain output for SOUT pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.6 Serial I/O connection examples (1)
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38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.7 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK1
CLK
SCLK1
CLK
SOUT
IN
SOUT
IN
S IN
38C3 group
OUT
S IN
Microcomputer
38C3 group
(3) Using SRDY signal output function
(Selecting external clock)
OUT
Microcomputer
(4) Using switch function of CLK signal output
pins, SCLK2 (Selecting internal clock)
SRDY
RDY
SCLK1
CLK
SCLK1
CLK
SOUT
IN
SOUT
IN
S IN
38C3 group
S IN
OUT
SCLK2
OUT
Microcomputer
38C3 group
Microcomputer
CLK
IN
OUT
Peripheral IC
Fig. 2.3.7 Serial I/O connection examples (2)
38C3 Group User’s Manual
2-37
APPLICATION
2.3 Serial I/O
2.3.4 Serial I/O’s modes
38C3 Group can use clock synchronous serial I/O.
Figure 2.3.8 shows the serial I/O’s modes.
Select SCLK1 as synchronous clock output pin
Internal clock
Select SCLK2 as synchronous clock output pin
Serial I/O
Clock synchronous serial I/O
Output SRDY signal
External clock
Not output SRDY signal
Fig. 2.3.8 Serial I/O’s modes
2.3.5 Serial I/O application examples
(1) Communication (transmission/reception) using clock synchronous serial I/O
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The SRDY signal is used for communication control.
Figure 2.3.9 shows a connection diagram, and Figure 2.3.10 shows a timing chart.
P55/INT0
SRDY
SCLK1
SCLK1
SOUT
SIN
38C3 group
38C3 group
Fig. 2.3.9 Connection diagram
Specifications : •
•
•
•
2-38
Use of serial I/O in clock synchronous serial I/O
Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
Use of S RDY (receivable signal)
The reception side outputs the SRDY signal at intervals of 2 ms (generated by the
timer), and 2-byte data is transferred from the transmission side to the reception
side.
38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
•••
SRDY
SCLK1
SOUT
•••
D0 D1 D2 D3 D4 D5 D6 D7
D 0 D 1 D 2 D 3 D4 D 5 D 6 D 7
D0 D1
•••
2 ms
Fig. 2.3.10 Timing chart
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2-39
APPLICATION
2.3 Serial I/O
Figure 2.3.11 shows the registers setting relevant to the transmission side, and Figure 2.3.12 shows
the registers setting relevant to the reception side.
Transmission side
Serial I/O control register 1 (address 001916)
SIOCON1 0 1 0 0 1 0 1 0
Internal synchronous clock: f(XIN)/32
SOUT, SCLK1, SCLK2 selected
SRDY output not used
LSB first
Internal clock
CMOS output
Serial I/O control register 2 (address 001A16)
SIOCON2
0
Synchronous clock output pin selection bit: SCLK1 selected
Not used (“0” at reading)
Interrupt edge selection register (address 003A16)
INTEDGE
0
INT0 falling edge active
Fig. 2.3.11 Registers setting relevant to transmission side
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38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
Reception side
Serial I/O control register 1 (address 001916)
SIOCON1
0 0 1
SRDY output used
LSB first
External clock
Fig. 2.3.12 Registers setting relevant to reception side
Figure 2.3.13 shows a control procedure of the transmission side, and Figure 2.3.14 shows a control
procedure of the reception side.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIOCON1 (address 001916)
SIOCON2 (address 001A16)
INTEDGE (address 003A16), bit 0
Serial I/O setting
010010102
XXXXXXX02
0
.....
0
IREQ1 (address 003C16), bit 0 ?
INT0 falling edge detection
1
IREQ1 (address 003C16), bit 0, bit 3
0
Transmission of the
first byte data
SIO (address 001B16)
Transmission data write
0
IREQ1 (address 003C16), bit 3 ?
Connection of completion of transmitting
(Serial I/O interrupt request flag)
1
IREQ1 (address 003C16), bit 3
0
Transmission of the
second byte data
SIO (address 001B16)
IREQ1 (address 003C16), bit 3 ?
Transmission data write
0
Judgment of completion of transmitting
(Serial I/O interrupt request flag)
1
Fig. 2.3.13 Control procedure of transmission side
38C3 Group User’s Manual
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APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON1 (address 001916)
X0011XXX2
• Serial I/O setting
.....
0
2ms has passed ?
1
SIO (address 001B16)
• SRDY output
SRDY signal is output by writing data to
SIO.
When using SRDY, set SRDY output
selection bit (bit 4) of SIOCON1 to “1.”
Dummy data
IREQ1 (address 003C16), bit 3 ?
• An interval of 2 ms generated by Timer.
0
• Judgment of completion of receiving
(Serial I/O interrupt request)
1
Read out reception data from
SIO (address 001B16)
• Reception of data
IREQ1 (address 003C16), bit 3 ?
0
• Judgment of completion of receiving
(Serial I/O interrupt request)
1
Read out reception data from
SIO (address 001B16)
• Reception of data
Fig. 2.3.14 Control procedure of reception side
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38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting port P5 7 with the CS pin of a peripheral IC.
Figure 2.3.15 shows a connection diagram, and Figure 2.3.16 shows a timing chart.
CS
P57
CS
CLK
SCLK1
CLK
DATA
SOUT
DATA
38C3 group
Peripheral IC
Fig. 2.3.15 Connection diagram
Specifications : • Use of serial I/O in clock synchronous serial I/O
• Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of serial I/O interrupt
• Port P57 is connected with the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P57 is controlled by software.
CS
CLK
DATA
D O0
DO1
D O2
D O3
Fig. 2.3.16 Timing chart
38C3 Group User’s Manual
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APPLICATION
2.3 Serial I/O
Figure 2.3.17 shows the relevant registers setting and Figure 2.3.18 shows the setting of transmission
data.
Serial I/O control register 1 (address 001916)
SIOCON1 0 1 0 0 1 0 1 0
Synchronous clock: f(XIN)/32
SOUT, SCLK1, SCLK2 signal pin
SRDY output not used
LSB first
Internal clock
CMOS output
Serial I/O control register 2 (address 001A16)
0
SIOCON2
Synchronous clock output pin: SCLK1
Interrupt control register 1 (address 003E16)
0
ICON1
Serial I/O interrupt: Disabled
Interrupt request register 1 (address 003C16)
IREQ
0
Serial I/O interrupt request cleared
Confirm transmission completion of 1-byte unit.
Fig. 2.3.17 Relevant registers setting
Serial I/O register (001B16)
Set a transmission data.
Confirm that transmission of the previous data is
completed, where bit 3, the serial I/O interrupt
request bit of the interrupt request register, is “1”;
before writing data.
SIO
Fig. 2.3.18 Setting of transmission data
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38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
Figure 2.3.19 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIOCON1 (address 001916)
SIOCON2 (address 001A16)
ICON1 (address 003E16), bit 3
P5 (address 000A16), bit 7
P5D (address 000B16), bit 7
Serial I/O setting
010010102
XXXXXXX02
0
1
1
Serial I/O interrupt: Disabled
CS signal output level to “H” setting
CS signal output port setting
.....
P5 (address 000A16), bit 7
0
IREQ1 (address 003C16), bit 3
CS signal output level to “L” setting
0
Serial I/O interrupt request bit to “0” setting
Transmission data write
(Start of 1-byte data transmission)
Transmission data
SIO (address 001B16)
IREQ1 (address 003C16), bit 3 ?
0
Judgment of completion of transmitting 1-byte
data
1
N
All data has been transmitted ?
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
Y
P5 (address 000A16), bit 7
1
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
Fig. 2.3.19 Control procedure
38C3 Group User’s Manual
2-45
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.3.20 shows a connection diagram.
SCLK1
SCLK1
S IN
SOUT
SOUT
SIN
38C3 group
(master side)
38C3 group
(slave side)
Fig. 2.3.20 Connection diagram
Specifications: •
•
•
•
•
•
•
•
Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32.)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 bytes/block each
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Transfer direction : LSB first
Limitations of the specifications:
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O interrupt
request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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38C3 Group User’s Manual
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.21. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 bytes) is received, the clock is ignored.
Figure 2.3.22 shows the relevant registers setting in the master unit and Figure 2.3.23 shows the
relevant registers setting in the slave unit.
D0
D1
D2
D7
D0
Byte cycle
Block transfer term
Interval between blocks
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.3.21 Timing chart
38C3 Group User’s Manual
2-47
APPLICATION
2.3 Serial I/O
Master unit
Serial I/O control register 1 (address 001916)
SIOCON1
0 1 0 0 1 0 1 0
Synchronous clock : f(XIN)/32
SOUT, SCLK1, SCLK2 signal pin
SRDY output not used
LSB first
Internal clock
CMOS output
Serial I/O control register 2 (address 001A16)
SIOCON2
0
Synchronous clock output pin: SCLK1
Fig. 2.3.22 Relevant registers setting in master unit
Slave unit
Serial I/O control register 1 (address 001916)
SIOCON1
0 0 0 0 1
SOUT, SCLK1, SCLK2 signal pin
SRDY output not used
LSB first
Synchronous clock: External clock
CMOS output
Serial I/O control register 2 (address 001A16)
SIOCON2
0
Synchronous clock input pin: SCLK1
Fig. 2.3.23 Relevant registers setting in slave unit
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APPLICATION
2.3 Serial I/O
Control procedure by software:
● Control in the master unit
After setting the relevant registers shown in Figure 2.3.22, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the serial I/O register.
To perform the communication in the timing shown in Figure 2.3.21, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O interrupt
request bit is set to “1,” or before the next transmission data is written to the serial I/O register.
Figure 2.3.24 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Pushing the register used in the interrupt
processing routine into the stack
●
Within a block transfer
period?
N
Generating a certain block interval by
using a timer or other functions
Y
Count a block interval counter
Read a reception data
Complete to transfer
a block?
Y
Start a block transfer?
Check of the block interval counter and
determination to start a block transfer
N
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
●
●
Popping registers which is pushed to stack
R TI
Fig. 2.3.24 Control procedure of master unit
38C3 Group User’s Manual
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APPLICATION
2.3 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.3.23, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O interrupt occurs each
time an 8-bit synchronous clock is received.
In the serial I/O interrupt processing routine, the data to be transmitted next is written to the serial
I/O register after the received data is read out.
However, if no serial I/O interrupt occurs for a certain time (heading adjustment time or more), the
following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the serial I/O register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.25 shows a control procedure of the slave unit using the serial I/O interrupt and any
timer interrupt (for heading adjustment).
Serial I/O reception interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
Within a block transfer
term?
N
Pushing the register used in
the interrupt processing
routine into the stack
Confirmation of the received
byte counter to judge the
block transfer term
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Heading adjustment
counter – 1
Y
N
Heading adjustment
counter = 0?
Read a reception data
Pushing the register used
in the interrupt processing
routine into the stack.
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte
counter ≥ 8?
A received byte counter
N
0
Y
Pop registers
Write a transmission data
Write dummy data (FF16)
●
Popping registers which is
pushed to stack
R TI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
R TI
●
Popping registers which is
pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.3.25 Control procedure of slave unit
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APPLICATION
2.3 Serial I/O
2.3.6 Notes on serial I/O
(1) Selecting external synchronous clock
When an external synchronous clock is selected, the contents of serial I/O register are being shifted
continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control the clock
externally.
(2) Transmission data wiritng
When an external clock is used as the synchronous clock, write the transmit data to the serial I/O
shift register at “H” level of transfer clock input.
38C3 Group User’s Manual
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APPLICATION
2.4 LCD controller
2.4 LCD controller
This paragraph explains the registers setting method and the notes relevant to the LCD controller.
2.4.1 Memory map
003816 Segment output enable register (SEG)
003916 LCD mode register (LM)
Fig. 2.4.1 Memory map of registers relevant to LCD controller
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APPLICATION
2.4 LCD controller
2.4.2 Relevant registers
Segment output enable register
b7 b6 b5 b4 b3 b2 b1 b0
Segment output enable register
(SEG: address 3816)
b
Name
0 Segment output
enable bit 0
1 Segment output
enable bit 1
2 Segment output
enable bit 2
3 Segment output
enable bit 3
4 Segment output
enable bit 4
5 Segment output
enable bit 5
6 Segment output
enable bit 6
7 Segment output
enable bit 7
Functions
0: I/O ports P20–P23
1: Segment output SEG0–SEG3
0: I/O ports P24–P27
1: Segment output SEG4–SEG7
0: I/O ports P00–P03
1: Segment output SEG8–SEG11
0: I/O ports P04–P07
1: Segment output SEG12–SEG15
0: I/O ports P10–P13
1: Segment output SEG16–SEG19
0: I/O ports P14–P17
1: Segment output SEG20–SEG23
0: Output ports P30–P33
1: Segment output SEG24–SEG27
0: Output ports P34–P37
1: Segment output SEG28–SEG31
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.2 Structure of Segment output enable register
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
LCD mode register
(LM: address 3916)
b
Name
0 Duty ratio selection
Functions
b1b0
At reset R W
0 0: 1 (use COM0)
0 1: 2 (use COM0, COM1)
1 0: 3 (use COM0–COM2)
1 1: 4 (use COM0–COM3)
0
2 Bias control bit
0: 1/3 bias
1: 1/2 bias
0
3 LCD enable bit
0: LCD OFF
1: LCD ON
0
bits
1
4 Fix “0” to this bit.
5 LCD circuit divider
b6b5
division ratio selection 0 0: Clock input
0 1: 2 division of clock input
bits
6
1 0: 4 division of clock input
1 1: 8 division of clock input
0: f(XCIN)/32
LCDCK
count
source
7
1: f(XIN)/8192 (f(XCIN)/8192 in
selection bit (Note)
low-speed mode)
0
0
0
0
0
Note: LCDCK is a clock for a LCD timing controller.
Fig. 2.4.3 Structure of LCD mode register
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APPLICATION
2.4 LCD controller
2.4.3 LCD controller application examples
Outline: A LCD panel display data by using the LCD controller.
’
AUTO
SLOW
PRINT
Fig. 2.4.4 LCD panel
Specifications: •Use of segment output SEG 0 to SEG13
•Setting of port P1 to I/O port, setting of port P3 to output
•Frame frequency = 61 Hz
•Duty ratio number = 4, Bias value = 1/3
Figure 2.4.5 shows the segment allocation example.
1
2
3
4
5
6
’
AUTO
SLOW
Fig. 2.4.5 Segment allocation example
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38C3 Group User’s Manual
PRINT
7
APPLICATION
2.4 LCD controller
Setting of LCD display RAM:
Bit
Address
7
6
5
4
3
2
1
0
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
004016
SEG1
SEG0
004116
SEG3
SEG2
004216
SEG5
SEG4
004316
SEG7
SEG6
004416
SEG9
SEG8
004516
SEG11
SEG10
004616
SEG13
SEG12
004716
SEG15
SEG14
004816
SEG17
SEG16
004916
SEG19
SEG18
004A16
SEG21
SEG20
004B16
SEG23
SEG22
004C16
SEG25
SEG24
004D16
SEG27
SEG26
004E16
SEG29
SEG28
004F16
SEG31
SEG30
Fig. 2.4.6 LCD display RAM map
a
Bit
Address
004016
7
6
5
4
3
2
1
0
f
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
g
f
e
d
c
b
a
1
g
f
e
d
c
b
a
2
004216
g
f
e
d
c
b
a
3
004316
g
f
e
d
c
b
a
4
004416
g
f
e
d
c
b
a
5
004516
g
f
e
d
c
b
a
6
7
004116
004616
’
PRINT
SLOW AUTO
g
b
c
e
d
Fig. 2.4.7 LCD display RAM setting
38C3 Group User’s Manual
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APPLICATION
2.4 LCD controller
Figure 2.4.8 shows the relevant registers setting.
Segment output enable register (address 003816)
SEG 0 0 0 0 1 1 1 1
Segment output: SEG0–SEG3
Segment output: SEG4–SEG7
Segment output: SEG8–SEG11
Segment output: SEG12–SEG15
I/O port: P10–P13
I/O port: P14–P17
Output port: P30–P33
Output port: P34–P37
LCD mode register (address 003916)
LM
1 1 0 0 0 0 1 1
4 (use COM0–COM3)
1/3 bias
LCD OFF (after setting data to LCDRAM, turn on)
Not used (Always set “0”.)
4 (Note)
f(XIN)/8192 (Note)
Note: Frame frequency = f(LCDCK)/division ratio
f(LCDCK) = count source frequency for LCDCK/LCD circuit division ratio
From the above, the frame frequency at f(XIN) = 8 MHz is as follows:
Frame frequency = {(8 ✕ 106/8192)/4}/4 ≅ 61.035 Hz
Fig. 2.4.8 Relevant registers setting
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38C3 Group User’s Manual
APPLICATION
2.4 LCD controller
Control procedure: Figure 2.4.9 shows the control procedure of relevant registers to turn on all the LCD
display in Figure 2.4.4.
RESET
Initialization
CLT
CLD
...
SEI
...
•All interrupts disabled
(address 003816)
(address 003916)
000011112
110000112
•Setting of segment output/port
•Setting of LCD mode register
LCDRAM0
LCDRAM1
LCDRAM2
LCDRAM3
LCDRAM4
LCDRAM5
LCDRAM6
(address 004016)
(address 004116)
(address 004216)
(address 004316)
(address 004416)
(address 004516)
(address 004616)
111111112
111111112
111111112
111111112
011111112
011111112
111111112
•Setting of value to LCDRAM
(Set “1” to turn on bit and set “0” to turn off bit.)
1
•LCD turn on
…
…
SEG
LM
(address 003916), bit 3
…
LM
•Interrupt enabled
CLI
When switching LCD turn on
(turn off) segment
LCDRAMX (address 004X16)
XXXXXXXX2
•Rewriting of bits corresponding to LCD turn on (turn off)
segments
Fig. 2.4.9 Control procedure
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APPLICATION
2.4 LCD controller
2.4.4 Notes on LCD controller
●When switching from the high-speed or middle-speed mode to the low-speed mode, switch the mode in
the following order:
(1) 32 kHz oscillation selected (bit 4 of CPU mode register (address 003B 16 ) = “1”)
(2) Count source for LCDCK = f(X CIN)/32 (bit 7 of LCD mode register (address 0039 16 ) = “0”)
(3) Internal system clock: XCIN-X COUT selected (bit 7 of CPU mode register (address 003B16 ) = “1”)
(4) Main clock X IN–X OUT stopped (bit 5 of CPU mode register (address 003B 16) = “1”)
Execute the setting (2) after the oscillation at 32 kHz (setting (1)) becomes completely stable.
●If the STP instruction is executed while the LCD is turned on by setting bit 3 of the LCD mode register
(address 0039 16) to “1”, a DC voltage is applied to the LCD. For this reason, do not execute the STP
instruction while the LCD is lighting.
●When the LCD is not used, open the segment and the common pins.
Connect VL1–V L3 to VSS.
●For the following products, if the LCD enable bit of the LCD mode register (bit 3 of address 0039 16) is
set to “0”, all LCDs cannot be turned off. To turn off all LCDs, set “0” (turn off) to all corresponding LCD
display RAM.
Corresponding products: M38C34M6AXXXFP, M38C34M6MXXXFP, M38C37ECAXXXFP,
M38C37ECMXXXFP, M38C37ECAFP, M38C37ECMFP, M38C37ECAFS,
M38C3ECMFS, M38C37RFS, M38C37RMFS
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APPLICATION
2.5 A-D converter
2.5 A-D converter
This paragraph describes the setting method of A-D converter relevant registers, notes etc.
2.5.1 Memory map
Address
003216 A-D control register (ADCON)
003316 A-D conversion register (low-order) (ADL)
003416 A-D conversion register (high-order) (ADH)
003D16 Interrupt request register 2 (IREQ2)
003F16 Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory map of A-D converter relevant registers
2.5.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
Functions
b2 b1 b0
0 0 0: P60/AN0
0 0 1: P61/AN1
0 1 0: P62/AN2
0 1 1: P63/AN3
1 0 0: P64/AN4
1 0 1: P65/AN5
1 1 0: P66/AN6
1 1 1: P67/AN7
3 Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
At reset R W
0
0
0
0
1
0
0
0
Fig. 2.5.2 Structure of A-D control register
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APPLICATION
2.5 A-D converter
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
0
1
2
3
4
5
6
7
Functions
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 2.5.3 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
0
1
2
3
4
5
6
7
Functions
Note: Do not read this register during A-D conversion.
Fig. 2.5.4 Structure of A-D conversion register (high-order)
2-60
At reset R W
This is A-D conversion result (high-order 8 bits) stored Undefined
bits. This is read exclusive register.
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
38C3 Group User’s Manual
APPLICATION
2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
1
2
3
4
5
6
7
Name
Functions
At reset R W
Timer 4 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Timer 5 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Timer 6 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
CNTR0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
CNTR1 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Key input interrupt 0 : No interrupt request issued
1 : Interrupt request issued
request bit
AD conversion
0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.5.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
0 Timer 4 interrupt
0 : Interrupt disabled
enable bit
1 : Interrupt enabled
1 Timer 5 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
2 Timer 6 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
3 CNTR0 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0 : interrupt disabled
4 CNTR1 interrupt
1 : Interrupt enabled
enable bit
5 Key input interrupt 0 : interrupt disabled
1 : Interrupt enabled
enable bit
6 AD conversion
0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.5.6 Structure of Interrupt control register 2
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APPLICATION
2.5 A-D converter
2.5.3 A-D converter application examples
(1) Read-in of analog signal
Outline: The analog input voltage from a sensor is converted to digital values.
Figure 2.5.7 shows a connection diagram, and Figure 2.5.8 shows the setting of relevant registers.
P60/AN0
Sensor
38C3 Group
Fig. 2.5.7 Connection diagram
Specifications: •Conversion of analog input voltage input from sensor to digital values
•Use of P6 0/AN 0 pin as analog input pin
A-D control register (address 003216)
ADCON
0
0 0 0
Analog input pin : P60/AN0 selected
A-D conversion start
A-D conversion register (high-order) (address 003416)
ADH
(Read-only)
A result of A-D conversion is stored (Note).
A-D conversion register (low-order) (address 003316)
A DL
(Read-only)
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out both registers in order of ADH (address
003416) and ADL (address 003316) following.
Fig. 2.5.8 Setting of relevant registers
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APPLICATION
2.5 A-D converter
Control procedure: A-D converter is started by performing register setting shown Figure 2.5.8.
Figure 2.5.9 shows the control procedure.
ADCON (address 003216), bit 0–bit 2 ← 0002
←0
ADCON (address 003216), bit 4
• P60/AN0 pin selected as analog input pin
• A-D conversion start
0
ADCON (address 003216), bit 4 ?
• Judgment of A-D conversion completion
1
Read out ADH (address 003416)
• Read out of high-order (b9–b2) conversion result
Read out ADL (address 003316)
• Read out of low-order (b1, b0) conversion result
Fig. 2.5.9 Control procedure
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APPLICATION
2.5 A-D converter
2.5.4 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AV SS : Connect to the V SS line.
● Reason
If the AVSS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN ) is 500 kHz or more.
• Use clock divided by main clock (f(X IN)) as internal system clock.
• Do not execute the STP instruction and WIT instruction.
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APPLICATION
2.6 ROM correct function
2.6 ROM correct function
This paragraph describes the setting method of ROM correct function relevant registers, notes etc.
2.6.1 Memory map
Address
005016
ROM correct data 1
005116
ROM correct data 2
005216
005316
ROM correct data 3
ROM correct data 4
005416
ROM correct data 5
005516
005616
ROM correct data 6
005716
ROM correct data 8
ROM correct data 7
0F0116 ROM correct enable register 1 (RC1) (Note)
0F0216 ROM correct high-order address register 1 (Note)
0F0316 ROM correct low-order address register 1 (Note)
0F0416 ROM correct high-order address register 2 (Note)
0F0516 ROM correct low-order address register 2 (Note)
0F0616 ROM correct high-order address register 3 (Note)
0F0716 ROM correct low-order address register 3 (Note)
0F0816 ROM correct high-order address register 4 (Note)
0F0916 ROM correct low-order address register 4 (Note)
0F0A16 ROM correct high-order address register 5 (Note)
0F0B16 ROM correct low-order address register 5 (Note)
0F0C16 ROM correct high-order address register 6 (Note)
0F0D16 ROM correct low-order address register 6 (Note)
0F0E16 ROM correct high-order address register 7 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F1016 ROM correct high-order address register 8 (Note)
0F1116 ROM correct low-order address register 8 (Note)
Note: This register is valid only in mask ROM version.
Fig. 2.6.1 Memory map of ROM correct function relevant registers
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APPLICATION
2.6 ROM correct function
2.6.2 Relevant registers
ROM correct enable register 1
b7 b6 b5 b4 b3 b2 b1 b0
ROM correct enable register 1
(RC1: address 0F0116)
b
Name
0
ROM correct
address 1 enable bit
ROM correct
address 2 enable bit
ROM correct
address 3 enable bit
ROM correct
address 4 enable bit
ROM correct
address 5 enable bit
ROM correct
address 6 enable bit
ROM correct
address 7 enable bit
ROM correct
address 8 enable bit
1
2
3
4
5
6
7
Functions
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
Fig. 2.6.2 Structure of ROM correct enable register 1
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At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.6 ROM correct function
2.6.3 ROM correct function application examples
Outline: When the contents of ROM would be corrected, the contents of ROM can be changed artificially
by connecting E2PROM to the externals and storing the contents (correct address, correct data)
to the ROM correct function relevant registers.
P46
SCLK1
CLK
CLK
OUT
P44
SIN
DATA
P47
P47
CS
E2PROM
P51
P51
38C3 group
38C3 group
●When ROM correct is unnecessary
CS
●When ROM correct is necessary
Fig. 2.6.3 Connection diagram
Specifications: ●If ROM correct is necessary, make P51 pull-up. If ROM correct is unnecessary, make P5 1
pull-down.
●Use of serial I/O as communication with E 2PROM
●Connection of clock and S CLK1, connection of CS pin and P4 7
Port P4 direction register (address 000916)
P4D
1 1
1
Set P44, P46, P47 to output ports.
When ROM correct is unnecessary
When ROM correct is necessary
Port P4 (address 000816)
P4
0 0
Serial I/O control register 1 (address 001916)
SIOCON1
0
1
0 1
Set “L” output as
termination of
unused pins
SOUT, SCLK1, SCLK2
signal pins
I/O port
Internal clock
Serial I/O control register 2 (address 001A16)
0
SIOCON2
SCLK1
Port P4 (address 000816)
P4
Set CS signal
to E2PROM
Fig. 2.6.4 Setting of relevant registers
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APPLICATION
2.6 ROM correct function
Control procedure:
RESET
Initialization
.....
P4D (address 000916)
P4 (address 000816)
Setting of port direction register
“L” output as termination of unused pins
11X1XXXX2
00X0XXXX2
N
E2PROM is connected ?
(P51 = “H” ?)
Y
SIOCON1 (address 001916)
SIOCON2 (address 001A16)
P4 (address 000816), bit 7
X1X01XXX2
XXXXXXX02
1
Setting of serial I/O
SCLK1 selected
CS signal output
Data corresponding to the following
registers, which have been set to
E2PROM beforehand, is read and the data
is stored to each register:
•ROM correct enable register 1
•ROM correct address registers 1–8
•ROM correct data 1–8
P4 (address 000816), bit 7
0
.....
Main processing
.....
✽ (Note)
N
ROM correct is enabled ?
(RC1, X = “H” ?)
Y
ROM correct
address X
Correct data X
Note: ✽ shows the internal operation of microcomputer.
Fig. 2.6.5 Control procedure
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APPLICATION
2.7 Reset circuit
2.7 Reset circuit
____________
The reset state is caused by applying
an “L” level to the RESET pin. After that, the reset state is released
____________
by applying an “H” level to the RESET pin, so that the program is executed in the middle-speed mode from
the contents of the reset vector address.
2.7.1 Connection example of reset IC
Figure 2.7.1 shows the example of power-on reset circuit. Figure 2.7.2 shows the system example which
switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT
interrupt.
VCC
Power source
M62022L
Output
RESET
Delay capacity
0.1µF
GND
VSS
38C3 Group
Fig. 2.7.1 Example of power-on reset circuit
System power
source voltage
+ 5V
VCC
VCC1
RESET
VCC2
INT
RESET
INT
VSS
V1
GND
Cd
38C3 Group
M62009L, M62009P, M62009FP
Fig. 2.7.2 RAM backup system example
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APPLICATION
2.7 Reset circuit
2.7.2 Notes on reset circuit
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.5 V (Note).
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
Note: M version of mask ROM version is 2.2 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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APPLICATION
2.8 Clock generating circuit
2.8 Clock generating circuit
This paragraph describes the setting method of clock generating circuit relevant registers, application examples
etc.
2.8.1 Relevant register
Figure 2.8.1 shows the structure of the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16)
b
Name
0 Processor mode
bits
1
2
3
4
5
6
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
Stack page
0 : Page 0
1 : Page 1
selection bit
Nothing is arranged for this bit. When this bit is read
out, the contents are “1”. Do not write “0” to this bit.
Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillation
function
Main clock (XIN0: Oscillating
1: Stopped
XOUT) stop bit
0:
f(XIN)/2 (high-speed
Main clock division
mode)
ratio selection bit
1: f(XIN)/8 (middle-speed
mode)
7 Internal system
clock selection bit
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
At reset R W
0
0
0
1
0
0
1
0
Fig. 2.8.1 Structure of CPU mode register
38C3 Group User’s Manual
2-71
APPLICATION
2.8 Clock generating circuit
2.8.2 Clock generating circuit application examples
(1) Status transition during power failure
Outline: The clock is counted up every one second by using the timer interrupt during a power
failure.
Power failure detection signal
Input port
( N o t e)
38C3 Group
Note: Signal is detected by inputting to each input port,
interrupt input pin, and analog input pin.
Fig. 2.8.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(X IN) = 8 MHz, f(X CIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level on the external
Output port: Fixed to output level that does not cause current flow to the external
(Example) When a circuit turns on LED at “L” output level, fix the
output level to “H”.
I/O port: Input port → Fixed to “H” or “L” level on the external
Output port → Output of data that does not consume current
VREF: Stop to supply to reference voltage input pin by external circuit
2-72
38C3 Group User’s Manual
APPLICATION
2.8 Clock generating circuit
Figure 2.8.3 shows the status transition diagram during power failure and Figure 2.8.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
XCIN
Internal
system clock
Middle-speed
mode
High-speed mode
Change internal system
clock to high-speed
mode
Low-speed mode
After detecting, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
XCIN-XCOUT oscillation function selected
Fig. 2.8.3 Status transition diagram during power failure
38C3 Group User’s Manual
2-73
APPLICATION
2.8 Clock generating circuit
CPU mode register (address 003B16)
CP UM
0 0 0 0
0 0
Main clock: High-speed mode (f(XIN)) (Note 1)
CPU mode register (address 003B16)
CP UM
0 0 0 1
0 0
(Note 2)
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16)
CP UM
1 0 0 1
0 0
(Note 2)
Internal system clock: Low-speed mode (f(XCIN))
CPU mode register (address 003B16)
CP UM
1 0 1 1
0 0
(Note 2)
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the highspeed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.8.4 Setting of relevant registers
2-74
38C3 Group User’s Manual
APPLICATION
2.8 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 003B16), bit 6
CPUM (address 003B16), bit 4
0
1
When selecting main clock f(XIN) (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
••••
N
Detect power failure ?
≈
Y
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
1 (Note)
1 (Note)
Set so that timer interrupt occurs every one
second
Execute WIT instruction
N
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN) oscillation stopped
At a power failure, clock count is performed during
timer interrupt processing (every second).
Return condition from power failure
concluded ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.8.5 Control procedure
38C3 Group User’s Manual
2-75
APPLICATION
2.8 Clock generating circuit
(2) Counting without clock error during power failure
Outline: It keeps counting without clock error during a power failure.
Specifications: •Reducing power consumption as low as possible while maintaining clock function
•Clock: f(X IN) = 4.19 MHz
•Sub clock: f(X CIN) = 32.768 kHz
•Use of Timer 3 interrupt
For the peripheral circuit and the status transition during a power failure, refer to “Figures 2.8.2 and
2.8.3”.
Figure 2.8.6 shows the structure of clock counter, Figures 2.8.7 and 2.8.8 show the setting of
relevant registers.
Timer 1 interrupt
Timer 1
f(XIN) = 4.19 MHz
1/16
1/64
Base counter
244 µs
1/256
1 second counter
Timer 1
f(XCIN) = 32.768 kHz
1/8
244 µs
1 minute counter
1 second
1/16
When the system returns from a
power failure, add the time taken
for the switching processing for the
return.
<At power failure>
Timer 3 interrupt
Timer 2
Timer 3
1/256
1/16
1/60
Minute/Time/Day/
Month/Year
: Software timer
: Hardware timer
Fig. 2.8.6 Structure of clock counter
2-76
38C3 Group User’s Manual
APPLICATION
2.8 Clock generating circuit
CPU mode register (address 003B16)
CP UM
0 0 0 1
0 0
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16)
CP UM
1
0 0 1
0 0
Internal system clock: f(XIN) (high-speed mode)
Timer 1 (address 002016)
T1
Set (Division ratio -1); 63 (3F16)
3F16
Timer 12 mode register (address 002816)
T12M
0 0 0 0 0 0 0 0
Timer 1 count: Operating
Timer 2 count: Operating
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1 underflow
P41 I/O port
Timer 34 mode register (address 002916)
T34M
0 0
0 1
0
Timer 3 count: Operating
Timer 3 count source: Timer 2 underflow
P42 I/O port
Interrupt request register 1 (address 003C16)
IREQ1
0
0
Set “0” to timer 1 interrupt request bit
Set “0” to timer 3 interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
1
Timer 1 interrupt: Enabled
Fig. 2.8.7 Initial setting of relevant registers
38C3 Group User’s Manual
2-77
APPLICATION
2.8 Clock generating circuit
Timer 12 mode register (address 002816)
T12M
0 1
Timer 1 count source: f(XCIN)
CPU mode register (address 003B16)
CP UM
1 0 0 1
0 0
Internal system clock: f(XCIN) (low-speed mode)
CPU mode register (address 003B16)
CP UM
1
0 1 1
0 0
Main clock: f(XIN): Stopped
Interrupt control register 1 (address 003E16)
ICON1
1
0
Timer 1 interrupt: Disabled
Timer 3 interrupt: Enabled
Timer 1 (address 002016)
T1
0716
Timer 2 (address 002116)
T2
FF16
Set (Division ratio – 1)
(T1 = 7 (0716), T2 = 255 (FF16), T3 = 15 (0F16))
Timer 3 (address 002216)
T3
0F16
Fig. 2.8.8 Setting of relevant registers after detecting power failure
2-78
38C3 Group User’s Manual
APPLICATION
2.8 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 003B16), bit 4
CPUM (address 003B16), bit 6
T1 (address 002016)
T12M (address 002816)
T34M (address 002916)
IREQ1 (address 003C16), bit 7, bit 5
Base counter (internal RAM)
1 second counter (internal RAM)
ICON1 (address 003E16), bit 5
1
0
3F16
000010002
00XX01X02
0,0
FF16
0F16
1
Port XC: XCIN-XCOUT oscillation function
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
••••
N
Detect power failure ?
≈
Y
0, 1
0
1 (Note)
1 (Note)
0, 0
0716
3F16
0F16
Timer 1 count source: f(XCIN)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 3 interrupt every second
Generation of one second by hardware timer during
power failure
Timer 3 interrupt routine
Push registers to stack etc.
••••
T12M (address 002816), bit 3, bit 2
ICON1 (address 003E16), bit 5
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
IREQ1 (address 003C16), bit 7, bit 5
T1 (address 002016)
T2 (address 002116)
T3 (address 002216)
Count 1 minute (internal RAM) counter
ICON1 (address 003E16), bit 7
1
Execute WIT instruction
Timer 3 interrupt: Enabled
Timer 3 interrupt occurs every second
(return from wait mode)
1 minute counter overflow ?
N
Y
Modify time, day, month, year
N
Return condition for power failure is
satisfied ?
≈
Y
Return processing from power failure
Note: Do not switch at one time.
R TI
≈
Fig. 2.8.9 Control procedure
38C3 Group User’s Manual
2-79
APPLICATION
2.8 Clock generating circuit
MEMORANDUM
2-80
38C3 Group User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 Control registers
3.6 Mask ROM confirmation form
3.7 ROM programming confirmation form
3.8 Mark specification form
3.9 Package outline
3.10 Machine instructions
3.11 List of instruction code
3.12 SFR memory map
3.13 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VCC
VI
VI
VI
VI
VI
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67, P70,
P71, P80–P87
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, XIN
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37
VO
VO
VO
Output voltage COM0–COM3
Output voltage P40–P47, P50, P52–P57, P60–P67,
P70, P71, P80–P87
Output voltage XOUT
Pd
Topr
Tstg
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on
Vss. Output transistors
are cut off.
At output port
At segment output
Ta = 25°C
Ratings
–0.3 to 7.0
–0.3 to VCC+0.3
Unit
V
V
–0.3 to VL2
VL1 to VL3
VL2 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
V
V
V
V
V
V
V
V
–0.3 to VCC+0.3
300
–20 to 85
–40 to 125
V
mW
°C
°C
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Power source voltage
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage
P00–P07, P10–P17, P20–P27
“H” input voltage
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
“H” input voltage
P80–P87
“H” input voltage
RESET
“H” input voltage
XIN
“L” input voltage
P00–P07, P10–P17, P20–P27
“L” input voltage
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
“L” input voltage
P80–P87
“L” input voltage
RESET
“L” input voltage
XIN
3-2
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
38C3 Group User’s Manual
Limits
Min.
4.0
2.5
2.5
Typ.
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
VCC
2.0
0
AVSS
0.7VCC
0.8VCC
0.4VCC
0.8VCC
0.8VCC
0
0
0
0
0
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.16VCC
0.2VCC
0.2VCC
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
Parameter
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
“H” total peak output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total peak output current (Note 1)
P80–P87, P50
“L” total peak output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
“H” total average output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total average output current (Note 1)
P80–P87, P50
“L” total average output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37
“H” peak output current (Note 2)
P40–P47, P50, P52–P57, P60–P67, P70, P71
P80–P87
“L” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37
“L” peak output current (Note 2)
P40–P47, P52–P57, P60–P67, P70, P71
“L” peak output current (Note 2)
P80–P87, P50
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37
“H” average output current (Note 3)
P40–P47, P50, P52–P57, P60–P67, P70, P71
P80–P87
“L” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37
“L” average output current (Note 3)
P40–P47, P52–P57, P60–P67, P70, P71
“L” average output current (Note 3)
P80–P87, P50
Min.
Limits
Typ.
Max.
Unit
–60
mA
–30
mA
40
mA
80
mA
40
mA
–30
mA
–15
mA
20
mA
40
mA
20
mA
–4.0
mA
–10
mA
5.0
mA
10
mA
30
mA
–2.0
mA
–5.0
mA
2.5
mA
5.0
mA
15
mA
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
38C3 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.4 Recommended operating conditions
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Parameter
Input frequency (duty cycle 50%)
Main clock input oscillation frequency (Note 4)
Min.
Limits
Typ.
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(VCC ≤ 4.0 V)
Middle-speed mode
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
MHz
MHz
MHz
(4✕VCC)–8
MHz
8.0
50
MHz
kHz
Notes 4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3-4
38C3 Group User’s Manual
Unit
Max.
4.0
(2✕VCC)–4
8.0
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.5 Electrical characteristics
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VOL
VOL
VT+–VTVT+–VTVT+–VTIIH
IIH
IIH
IIH
IIL
IIL
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
“H” output voltage
P40–P47, P50, P52–P57,
P60–P67, P70, P71,
P80–P87
“L” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
(Note)
“L” output voltage
P40–P47, P52–P57, P60–P67,
P70, P71
(Note)
“L” output voltage
P80–P87, P50
Hysteresis
INT0–INT2, CNTR0, CNTR1, P80–P87
Hysteresis SCLK1, SIN
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27
“H” input current
P40–P47, P50–P57, P60–P67,
P70, P71, P80–P87
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27, P51
“L” input current
P40–P47, P50, P52–P57,
P60–P67, P70, P71, P80–P87
IIL
IIL
Test conditions
“L” input current RESET
“L” input current XIN
IOH = –2.0 mA
IOH = –0.6 mA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 2.5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 5.0 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
Min.
VCC–2.0
VCC–1.0
Limits
Typ.
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
2.0
0.5
1.0
V
V
V
2.0
0.5
1.0
V
V
V
2.0
0.5
V
V
0.5
0.5
V
V
5.0
µA
30
70
140
µA
6.0
25
45
µA
5.0
µA
5.0
–5.0
µA
µA
µA
–5.0
µA
VI = VCC
VI = VCC
4.0
VI = VSS
Pull-up “off”
VCC = 5.0 V, VI = VSS
Pull-up “on”
VCC = 3.0 V, VI = VSS
Pull-up “on”
VI = VSS
VI = VSS
Unit
V
V
IOL = 15 mA
RESET:
VCC = 2.5 V – 5.5 V
VI = VCC
Pull-down “off”
VCC = 5.0 V, VI = VCC
Pull-down “on”
VCC = 3.0 V, VI = VCC
Pull-down “on”
VI = VCC
Max.
–30
–70
–140
µA
–6
–25
–45
µA
–5
µA
µA
–4
Note: When “1” is set to the port XC switch bit (bit 4 of address 003B16) of the CPU mode register, the drive ability of Port P71 is different from the value above
mentioned.
38C3 Group User’s Manual
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.6 Electrical characteristics
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VRAM
ICC
3-6
Parameter
RAM hold voltage
Power source current
Test conditions
When clock is stopped
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter in operating
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter stopped
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
(in WIT state)
Output transistors “off”
All oscillation stopped
Ta = 25 °C
(in STP state)
Output transistors “off” Ta = 85 °C
38C3 Group User’s Manual
Min.
2.0
Limits
Typ.
Unit
6.4
Max.
5.5
13
1.6
3.2
mA
15
22
µA
4.5
9.0
µA
0.1
1.0
µA
10
µA
V
mA
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.7 A-D converter characteristics
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-speed/high-speed mode)
Symbol
Parameter
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Reference input current
Analog port input current
Ladder resistor
Tconv
IVREF
IIA
RLADDER
Test conditions
Min.
VCC = VREF = 5.12 V
VREF = 5 V
38C3 Group User’s Manual
Limits
Typ.
±1
61
50
150
0.5
35
Max.
10
±2.5
62
200
5.0
Unit
Bits
LSB
tc(φ)
µA
µA
kΩ
3-7
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements and switching characteristics
Table 3.1.8 Timing requirements 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 3.1.9 Timing requirements 2
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
3-8
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
38C3 Group User’s Manual
Min.
2
125
45
40
500/(VCC–2)
250/(VCC–2)–20
250/(VCC–2)–20
230
230
2000
950
950
400
200
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
APPENDIX
3.1 Electrical characteristics
Table 3.1.10 Switching characteristics 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
CMOS output falling time
Min.
tc(SCLK)/2–30
tc(SCLK)/2–30
(Note 1)
(Note 1)
Typ.
Max.
140
–30
(Note 2)
(Note 2)
10
10
30
30
30
30
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
Table 3.1.11 Switching characteristics 2
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
CMOS output falling time
Min.
tC(SCLK)/2–50
tC(SCLK)/2–50
(Note 1)
(Note 1)
(Note 2)
(Note 2)
350
–30
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
38C3 Group User’s Manual
3-9
APPENDIX
3.1 Electrical characteristics
3.1.6 Absolute maximum ratings (M version)
Table 3.1.12 Absolute maximum ratings (M version)
Symbol
VCC
VI
VI
VI
VI
VI
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67, P70,
P71, P80–P87
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, XIN
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37
VO
VO
Output voltage COM0–COM3
Output voltage P40–P47, P50, P52–P57, P60–P67,
P70, P71, P80–P87
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
VO
Pd
Topr
Tstg
Conditions
All voltages are based on
Vss. Output transistors
are cut off.
At output port
At segment output
Ta = 25°C
Ratings
–0.3 to 7.0
–0.3 to VCC+0.3
Unit
V
V
–0.3 to VL2
VL1 to VL3
VL2 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
V
V
V
V
V
V
V
V
–0.3 to VCC+0.3
300
–20 to 85
–40 to 125
V
mW
°C
°C
3.1.7 Recommended operating conditions (M version)
Table 3.1.13 Recommended operating conditions (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage
VSS
VREF
AVSS
VIA
Power source voltage
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
3-10
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
Limits
Min.
4.0
2.2
2.2
Typ.
5.0
5.0
5.0
0
2.0
Max.
5.5
5.5
5.5
VCC
0
AVSS
38C3 Group User’s Manual
VCC
Unit
V
V
V
V
V
V
V
APPENDIX
3.1 Electrical characteristics
Table 3.1.14 Recommended operating conditions (M version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Parameter
“H” input voltage
P00–P07, P10–P17, P20–P27
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
P80–P87
RESET
XIN
P00–P07, P10–P17, P20–P27
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
P80–P87
RESET
XIN
Limits
Min.
0.7VCC
0.8VCC
0.4VCC
0.8VCC
0.8VCC
0
0
0
0
0
Typ.
Max.
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.16VCC
0.2VCC
0.2VCC
Unit
V
V
V
V
V
V
V
V
V
V
Table 3.1.15 Recommended operating conditions (M version)
(Vcc = 2.2 to 2.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VIH
“H” input voltage
P00–P07, P10–P17, P20–P27
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
P80–P87
RESET
XIN
P00–P07, P10–P17, P20–P27
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
P80–P87
RESET
XIN
38C3 Group User’s Manual
Limits
Min.
0.8VCC
0.95VCC
0.5VCC
0.95VCC
0.95VCC
0
0
0
0
0
Typ.
Max.
VCC
VCC
VCC
VCC
VCC
0.2VCC
0.05VCC
0.1VCC
0.05VCC
0.05VCC
Unit
V
V
V
V
V
V
V
V
V
V
3-11
APPENDIX
3.1 Electrical characteristics
Table 3.1.16 Recommended operating conditions (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
Parameter
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
“H” total peak output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total peak output current (Note 1)
P80–P87, P50
“L” total peak output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
“H” total average output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total average output current (Note 1)
P80–P87, P50
“L” total average output current (Note 1)
P40–P47, P52–P57, P60–P67, P70, P71
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37
“H” peak output current (Note 2)
P40–P47, P50, P52–P57, P60–P67, P70, P71
P80–P87
“L” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37
“L” peak output current (Note 2)
P40–P47, P52–P57, P60–P67, P70, P71
“L” peak output current (Note 2)
P80–P87, P50
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37
“H” average output current (Note 3)
P40–P47, P50, P52–P57, P60–P67, P70, P71
P80–P87
“L” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37
“L” average output current (Note 3)
P40–P47, P52–P57, P60–P67, P70, P71
“L” average output current (Note 3)
P80–P87, P50
Min.
Limits
Typ.
Max.
Unit
–60
mA
–30
mA
40
mA
80
mA
40
mA
–30
mA
–15
mA
20
mA
40
mA
20
mA
–4.0
mA
–10
mA
5.0
mA
10
mA
30
mA
–2.0
mA
–5.0
mA
2.5
mA
5.0
mA
15
mA
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
3-12
38C3 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
Table 3.1.17 Recommended operating conditions (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Parameter
Input frequency (duty cycle 50%)
Main clock input oscillation frequency (Note 4)
Min.
Limits
Typ.
(4.0 V ≤ VCC ≤ 5.5 V)
(2.2 V ≤ VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
Max.
4.0
Unit
(2✕VCC)–4
8.0
MHz
MHz
MHz
(4✕VCC)–8
MHz
8.0
50
MHz
kHz
Notes 4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
38C3 Group User’s Manual
3-13
APPENDIX
3.1 Electrical characteristics
3.1.8 Electrical characteristics (M version)
Table 3.1.18 Electrical characteristics (M version)
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VOL
VOL
V T+–VTV T+–VTV T+–VTIIH
IIH
IIH
IIH
IIL
IIL
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
“H” output voltage
P40–P47, P50, P52–P57,
P60–P67, P70, P71,
P80–P87
“L” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
(Note)
“L” output voltage
P40–P47, P52–P57, P60–P67,
P70, P71
(Note)
“L” output voltage
P80–P87, P50
Hysteresis
INT0–INT2, CNTR0, CNTR1, P80–P87
Hysteresis SCLK1, SIN
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27
“H” input current
P40–P47, P50–P57, P60–P67,
P70, P71, P80–P87
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27, P51
“L” input current
P40–P47, P50, P52–P57,
P60–P67, P70, P71, P80–P87
IIL
IIL
Test conditions
“L” input current RESET
“L” input current XIN
IOH = –2.0 mA
IOH = –0.6 mA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 2.5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 5.0 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
Min.
VCC–2.0
VCC–1.0
Limits
Typ.
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
2.0
0.5
1.0
V
V
V
2.0
0.5
1.0
V
V
V
2.0
0.5
V
V
0.5
0.5
V
V
5.0
µA
30
70
140
µA
6.0
25
45
µA
5.0
µA
5.0
–5.0
µA
µA
µA
–5.0
µA
VI = VCC
VI = VCC
4.0
VI = VSS
Pull-up “off”
VCC = 5.0 V, VI = VSS
Pull-up “on”
VCC = 3.0 V, VI = VSS
Pull-up “on”
VI = VSS
VI = VSS
Unit
V
V
IOL = 15 mA
RESET:
VCC = 2.2 V – 5.5 V
VI = VCC
Pull-down “off”
VCC = 5.0 V, VI = VCC
Pull-down “on”
VCC = 3.0 V, VI = VCC
Pull-down “on”
VI = VCC
Max.
–30
–70
–140
µA
–6
–25
–45
µA
–5
µA
µA
–4
Note: When “1” is set to the port XC switch bit (bit 4 of address 003B16) of the CPU mode register, the drive ability of Port P71 is different from the value above
mentioned.
3-14
38C3 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
Table 3.1.19 Electrical characteristics (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VRAM
ICC
Parameter
RAM hold voltage
Power source current
Test conditions
When clock is stopped
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter in operating
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter stopped
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
(in WIT state)
Output transistors “off”
All oscillation stopped
Ta = 25 °C
(in STP state)
Output transistors “off” Ta = 85 °C
38C3 Group User’s Manual
Min.
2.0
Limits
Typ.
Unit
6.4
Max.
5.5
13
1.6
3.2
mA
15
22
µA
4.5
9.0
µA
0.1
1.0
µA
10
µA
V
mA
3-15
APPENDIX
3.1 Electrical characteristics
3.1.9 A-D converter characteristics (M version)
Table 3.1.20 A-D converter characteristics (M version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-speed/high-speed mode)
Symbol
Parameter
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Reference input current
Analog port input current
Ladder resistor
Tconv
IVREF
IIA
RLADDER
3-16
Test conditions
Min.
VCC = VREF = 5.12 V
VREF = 5 V
38C3 Group User’s Manual
Limits
Typ.
±1
61
50
150
0.5
35
Max.
10
±2.5
62
200
5.0
Unit
Bits
LSB
tc(φ)
µA
µA
kΩ
APPENDIX
3.1 Electrical characteristics
3.1.10 Timing requirements and switching characteristics (M version)
Table 3.1.21 Timing requirements 1 (M version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 3.1.22 Timing requirements 2 (M version)
(Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
38C3 Group User’s Manual
Min.
2
125
45
40
500/(VCC–2)
250/(VCC–2)–20
250/(VCC–2)–20
230
230
2000
950
950
400
200
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-17
APPENDIX
3.1 Electrical characteristics
Table 3.1.23 Switching characteristics 1 (M version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter
Min.
tc(SCLK)/2–30
tc(SCLK)/2–30
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
CMOS output falling time
(Note 1)
(Note 1)
Typ.
Max.
140
–30
(Note 2)
(Note 2)
10
10
30
30
30
30
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
Table 3.1.24 Switching characteristics 2 (M version)
(Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter
Symbol
Min.
tC(SCLK)/2–50
tC(SCLK)/2–50
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
CMOS output falling time
(Note 1)
(Note 1)
350
–30
(Note 2)
(Note 2)
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
N-channel open-drain output
CMOS output
Note: When bit 7 of the serial I/O control register 1 (address 0019 16) is “ 1.”
(N-channel open-drain output mode)
Fig. 3.1.1 Circuit for measuring output switching characteristics
3-18
38C3 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
twL(INT)
twH (INT)
INT0 – INT2
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
SCLK
tWL(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
th(SCLK-SIN)
0.8VCC
0.2VCC
SIN
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
Fig. 3.1.2 Timing chart
38C3 Group User’s Manual
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APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current standard characteristics
Measuring conditions: 25 °C, f(XCIN) = 32.768 kHz, at A-D converter operating, in high-speed mode
Power source current (mA)
Rectangular waveform input
10.0
Vcc = 5.5 V
9.0
8.0
7.0
Vcc = 5.0 V
6.0
5.0
Vcc = 4.0 V
4.0
3.0
2.0
1.0
0.0
0
2
4
6
8
10
12
Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current standard characteristics
Measuring conditions: 25 °C, f(XCIN) = 32.768 kHz, at A-D conversion completed, in high-speed mode
Power source current (mA)
Rectangular waveform input
3.0
2.5
Vcc = 5.5 V
2.0
Vcc = 5.0 V
1.5
Vcc = 4.0 V
1.0
0.5
0.0
0
2
4
6
8
10
12
Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current standard characteristics (in wait mode)
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38C3 Group User's Manual
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristics
Port P00 IOH–VOH characteristics (25 °C)
(Same characteristics pins: P00–P07, P10–P17, P20–P27, P30–P37)
IOH (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
Vcc = 5.5 V
-10
Vcc = 2.5 V
Vcc = 5.0 V
0
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.3 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C)
Port P00 IOH–VOH characteristics (90 °C)
(Same characteristics pins: P00–P07, P10–P17, P20–P27, P30–P37)
IOH (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
Vcc = 5.5 V
-10
Vcc = 2.5 V
Vcc = 5.0 V
0
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.4 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (90 °C)
38C3 Group User's Manual
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APPENDIX
3.2 Standard characteristics
Port P00 IOL–VOL characteristics (25 °C)
(Same characteristics pins: P00–P07, P10–P17, P20–P27, P30–P37)
IOL (mA)
100
90
80
70
60
Vcc = 5.5 V
50
Vcc = 5.0 V
40
30
20
Vcc = 2.5 V
10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.5 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C)
Port P00 IOL–VOL characteristics (90 °C)
(Same characteristics pins: P00–P07, P10–P17, P20–P27, P30–P37)
IOL (mA)
100
90
80
70
60
50
Vcc = 5.5 V
40
Vcc = 5.0 V
30
20
Vcc = 2.5 V
10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.6 CMOS output port (P0, P1, P2, P3) N-channel side characteristics (90 °C)
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APPENDIX
3.2 Standard characteristics
IOH (mA)
Port P40 IOH–VOH characteristics (25 °C)
(Same characteristics pins: P40–P47, P50, P52–P57, P60–P67, P70, P71, P80–P87)
-100
-90
-80
-70
-60
-50
-40
-30
-20
Vcc = 5.5 V
Vcc = 5.0 V
-10
Vcc = 2.5 V
0
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.7 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics (25 °C)
Port P40 IOH–VOH characteristics (90 °C)
(Same characteristics pins: P40–P47, P50, P52–P57, P60–P67, P70, P71, P80–P87)
IOH (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
Vcc = 5.0 V
Vcc = 5.5 V
-10
Vcc = 2.5 V
0
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.8 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics (90 °C)
38C3 Group User's Manual
3-23
APPENDIX
3.2 Standard characteristics
Port P40 IOL–VOL characteristics (25 °C)
(Same characteristics pins: P40–P47, P52–P57, P60–P67, P70, P71)
IOL (mA)
100
90
Vcc = 5.5 V
80
Vcc = 5.0 V
70
60
50
40
30
20
Vcc = 2.5 V
10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.9 CMOS output port (P4, P52–P57, P6, P70 , P71) N-channel side characteristics (25 °C)
Port P40 IOL–VOL characteristics (90 °C)
(Same characteristics pins: P40–P47, P52–P57, P60–P67, P70, P71)
IOL (mA)
100
90
80
Vcc = 5.5 V
70
Vcc = 5.0 V
60
50
40
30
20
Vcc = 2.5 V
10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.10 CMOS output port (P4, P52–P57, P6, P70, P71) N-channel side characteristics (90 °C)
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38C3 Group User's Manual
APPENDIX
3.2 Standard characteristics
Port P80 IOL–VOL characteristics (25 °C)
(Same characteristics pins: P80–P87, P50)
IOL (mA)
100
90
Vcc = 5.5 V
80
Vcc = 5.0 V
70
60
50
40
30
Vcc = 2.5 V
20
10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.11 CMOS output port (P50, P8) N-channel side characteristics (25 °C)
Port P80 IOL–VOL characteristics (90 °C)
(Same characteristics pins: P80–P87, P50)
IOL (mA)
100
90
80
Vcc = 5.5 V
70
Vcc = 5.0 V
60
50
40
30
Vcc = 2.5 V
20
10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.12 CMOS output port (P50, P8) N-channel side characteristics (90 °C)
38C3 Group User's Manual
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APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following
sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.1 Sequence of switch detection edge
■ Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
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APPENDIX
3.3 Notes on use
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 2
to “0”. Figure 3.3.3 shows the structure of the
interrupt control register 2.
b7
b0
Interrupt control register 2
Address 003F16
0
Interrupt enable bits
Not used
Fix this bit to “0”.
Fig. 3.3.3 Structure of interrupt control register 2
3.3.2 Notes on timer A (PWM mode and IGBT output mode)
(1) When timer starts first or last value of compare register is “000016”
After “L” level (timer A output active edge switch bit is “0”; when starting from “L” output) is output
during 2 cycles (until timer underflows two times), start PWM output or IGBT output.
Reason: When data is written to timer A and compare register, value of timer A and value of
compare register are renewed at timer underflow. In case of this, compare register value
and timer value are compared before renewal so that they are judged to be equal, and
TAOUT output becomes “L”. (Timer A output switch bit = “0”: when starting from “L” output)
Timer A underflow should be “H” output, but the match have the priority. (see “Figure
3.3.4”)
Compare register value is value which is written at ➀
Compare register value is
“000016”
(last value or initial value)
➀
Timer A start
Timer A underflow
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 3.3.4 PWM output and IGBT output (1)
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APPENDIX
3.3 Notes on use
(2) When compare register is set to “000016” (last value is except “000016”)
Next 1 cycle of the cycle which data is written to timer A and compare register is output “H”, and
“L” is output from the next cycle. (timer A output switch bit = “0”: when starting from “L” output)
(see “Figure 3.3.5”)
Compare register value is
last value
Timer A underflow
Compare register value is “000016”
Timer A underflow
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 3.3.5 PWM output and IGBT output (2)
(3) When timer A and compare register are same value
TAOUT output becomes “H” with underflow immediately after data is written to timer A and compare
register. And TA OUT output becomes “L” when timer A is reloaded and the value matches with
compare register. This “H” output width becomes 1 count of timer A count source. (timer A output
switch bit =“0”: when starting from “L” output) (see “Figure 3.3.6”)
Timer A value–compare register value
Timer A count source
1 count width
Timer A underflow
Timer A value
compare register value
writing
Fig. 3.3.6 PWM output and IGBT output (3)
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38C3 Group User’s Manual
Timer A underflow
APPENDIX
3.3 Notes on use
3.3.3 Notes on serial I/O
(1) Selecting external synchronous clock
When an external synchronous clock is selected, the contents of serial I/O register are being shifted
continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control the clock
externally.
(2) Transmission data writing
When an external clock is used as the synchronous clock, write the transmit data to the serial I/O
shift register at “H” level of transfer clock input.
3.3.4 Notes on LCD controller
●When switching from the high-speed or middle-speed mode to the low-speed mode, switch the mode in
the following order:
(1) 32 kHz oscillation selected (bit 4 of CPU mode register (address 003B 16) = “1”)
(2) Count source for LCDCK = f(X CIN)/32 (bit 7 of LCD mode register (address 0039 16) = “0”)
(3) Internal system clock: XCIN-X COUT selected (bit 7 of CPU mode register (address 003B16) = “1”)
(4) Main clock X IN–XOUT stopped (bit 5 of CPU mode register (address 003B 16) = “1”)
Execute the setting (2) after the oscillation at 32 kHz (setting (1)) becomes completely stable.
●If the STP instruction is executed while the LCD is turned on by setting bit 3 of the LCD mode register
(address 0039 16 ) to “1”, a DC voltage is applied to the LCD. For this reason, do not execute the STP
instruction while the LCD is lighting.
●When the LCD is not used, open the segment and the common pins.
Connect V L1 to V L3 to V SS.
●For the following products, if the LCD enable bit of the LCD mode register (bit 3 of address 0039 16) is
set to “0”, all LCDs cannot be turned off. When all LCDs are turned off, set “0” (turn off) to all corresponding
LCD display RAM.
Corresponding products: M38C34M6AXXXFP, M38C34M6MXXXFP, M38C37ECAXXXFP,
M38C37ECMXXXFP, M38C37ECAFP, M38C37ECMFP, M38C37ECAFS,
M38C3ECMFS, M38C37RFS, M38C37RMFS
38C3 Group User’s Manual
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APPENDIX
3.3 Notes on use
3.3.5 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the V SS line.
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN ) is 500 kHz or more.
• Use clock divided by main clock (f(X IN)) as internal system clock.
• Do not execute the STP instruction and WIT instruction.
3.3.6 Notes on reset circuit
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.5 V (Note).
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
Note: M version of mask ROM version is 2.2 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
38C3 Group User’s Manual
3-31
APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
Fig. 3.4.3 Wiring for clock I/O pins
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APPENDIX
3.4 Countermeasures against noise
(4) Wiring to V PP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the V PP pin the shortest possible in series. When not
connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest
possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the One Time PROM and the EPROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low
to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily.
If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in PROM,
which may cause a program runaway.
Approximately
5 kΩ
P51/VPP
RESET
Fig. 3.4.4 Wiring for the V PP pin of the One Time PROM and the EPROM version
3.4.2 Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1 µ F bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the V CC pin.
AA
AA
AA
AA
AA
VCC
VSS
N.G.
AA
AA
AA
AA
AA
VCC
VSS
O.K.
Fig. 3.4.5 Bypass capacitor across the VSS line and the VCC line
38C3 Group User’s Manual
3-33
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the V SS pin is grounded at a position far away from
the V SS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.6 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.7 Wiring for a large current signal line
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APPENDIX
3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently
(3) Oscillator protection using V SS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
AAAAAAA
AAA
AAAAAA
A
AA
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 VSS pattern on the underside of an oscillator
38C3 Group User’s Manual
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APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.10 Setup for I/O ports
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APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
≤0
Return
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
38C3 Group User’s Manual
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APPENDIX
3.5 Control registers
3.5 Control registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 1016)
b
0
1
2
3
4
5
6
7
Name
Port Pi0
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.1 Structure of Port Pi
Port P0 direction register, Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 direction register (P0D: address 0116)
Port P1 direction register (P1D: address 0316)
b
Name
0 Ports P0/P1
direction register
Functions
0 : All bits of ports P0/P1
input mode
1 : All bits of ports P0/P1
output mode
1 Nothing is arranged for these bits. When these
2 bits are read out, the contents are undefined.
3
4
5
6
7
At reset R W
0
✕
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Note: Ports P0 and P1 are switched to input and output by each port.
When b0 of corresponding port direction register is set to “0”, all
8 bits of port become input port. When b0 of corresponding port
direction register is set to “1”, all 8 bits of port become output
port. Nothing is arranged for b1 to b7 of port P0 and port P1
direction registers. These are write disabled bits.
Fig. 3.5.2 Structure of Port P0 direction register and Port P1 direction register
3-38
38C3 Group User’s Manual
APPENDIX
3.5 Control registers
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 2, 4, 5, 6, 8)
(PiD: addresses 0516, 0916, 0B16, 0D16, 1116)
b
Name
Functions
At reset R W
0 Port Pi direction
register
1
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
(Note)
0
2
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
3
4
5
6
7
0
0
0
0
0
0
Note: Bit 1 of the port P5 direction register (address 0B16) does not have
direction register function, because P51 is an input port. When writing to
bit 1 of the port P5 direction register, write “0” to the bit.
Fig. 3.5.3 Structure of Port Pi direction register
Port P7
b7 b6 b5 b4 b3 b2 b1 b0
Port P7
(P7: address 0E16)
b
Name
0 Port P70
1 Port P71
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.4 Structure of Port P7
38C3 Group User’s Manual
3-39
APPENDIX
3.5 Control registers
Port P7 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P7 direction register
(P7D: address 0F16)
b
Name
Functions
0 Port P7 direction
register
1
0 : Port P70 input mode
1 : Port P70 output mode
0 : Port P71 input mode
1 : Port P71 output mode
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
✕
0
✕
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.5 Structure of Port P7 direction register
PULL register A
b7 b6 b5 b4 b3 b2 b1 b0
PULL register A
(PULLA: address 1616)
b
Name
Functions
At reset R W
0: No pull-down control
0 Port P00–P07
1: Pull-down control
pull-down control
0: No pull-down control
1 Port P10–P17
1: Pull-down control
pull-down control
0: No pull-down control
2 Port P20–P27
1: Pull-down control
pull-down control
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
0: No pull-up control
4 Port P70, P71
1: Pull-up control
pull-up control
5 Port P80–P87
0: No pull-up control
1: Pull-up control
pull-up control
6 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
1
1
1
0
0
Note: The pin which is set to output port is cut off from pull-up control.
Fig. 3.5.6 Structure of PULL register A
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38C3 Group User’s Manual
APPENDIX
3.5 Control registers
PULL register B
b7 b6 b5 b4 b3 b2 b1 b0
PULL register B
(PULLB: address 1716)
b
Name
Functions
At reset R W
0: No pull-up control
0 Port P40–P43
1: Pull-up control
pull-up control
0: No pull-up control
1 Port P44–P47
1: Pull-up control
pull-up control
0: No pull-up control
2 Port P50, P52, P53
1: Pull-up control
pull-up control
3 Port P54–P57
0: No pull-up control
1: Pull-up control
pull-up control
0: No pull-up control
4 Port P60–P63
1: Pull-up control
pull-up control
5 Port P64–P67
0: No pull-up control
1: Pull-up control
pull-up control
6 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
0
0
0
Note: The pin which is set to output port is cut off from pull-up control.
Fig. 3.5.7 Structure of PULL register B
38C3 Group User’s Manual
3-41
APPENDIX
3.5 Control registers
Port P8 output selection register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8 output selection register (P8SEL: address 1816)
b
Name
Functions
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
1
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
2
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
3
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
4
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
5
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
6
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
7
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
Fig. 3.5.8 Structure of Port P8 output selection register
3-42
At reset R W
0 Port P8 output
selection register
38C3 Group User’s Manual
APPENDIX
3.5 Control registers
Serial I/O control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 1
(SIOCON1: address 1916)
b
Name
0 Internal
synchronous clock
1 selection bits
2
Functions
b2b1b0
0 0 0: f(XIN)/8 or f(XCIN)/8
0 0 1: f(XIN)/16 or f(XCIN)/16
0 1 0: f(XIN)/32 or f(XCIN)/32
0 1 1: f(XIN)/64 or f(XCIN)/64
1 1 0: f(XIN)/128 or f(XCIN)/128
1 1 1: f(XIN)/256 or f(XCIN)/256
At reset R W
0
0
0
3 Serial I/O port
selection bit
(P40, P45, P46)
0: I/O port
1: SOUT, SCLK1, SCLK2
signal pin
0
4 SRDY output
selection bit (P47)
5 Transfer direction
selection bit
6 Synchronous clock
selection bit
7 P-channel output
disable bit
(P40, P45, P46)
0: I/O port
1: SRDY signal pin
0: LSB first
1: MSB first
0: External clock
1: Internal clock
0: CMOS output
(in output mode)
1: N-channel open-drain
output (in output mode)
0
0
0
0
Fig. 3.5.9 Structure of Serial I/O control register 1
38C3 Group User’s Manual
3-43
APPENDIX
3.5 Control registers
Serial I/O control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 2
(SIOCON2: address 1A16)
b
Name
Functions
0 Synchronous clock 0: SCLK1
output pin selection 1: SCLK2
bit
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read
3 out, the contents are “0”.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.10 Structure of Serial I/O control register 2
Serial I/O register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O register
(SIO: address 1B16)
b
Name
0 Serial I/O register
1
2
3
4
5
6
7
Functions
This register becomes shift
register.
Set transmit data to this
register.
The serial transfer is started
by writing the transmit data.
Fig. 3.5.11 Structure of Serial I/O register
3-44
38C3 Group User’s Manual
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
APPENDIX
3.5 Control registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
0 • Set timer i count value.
1 • The value set in this register is written to both
2 the timer i and the timer i latch at one time.
3 • When the timer i is read out, the count value
4 of the timer i is read out.
5
6
7
At reset R W
1
1
1
1
1
1
1
1
Fig. 3.5.12 Structure of Timer i
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 the timer 2 and the timer 2 latch at one time.
3 • When the timer 2 is read out, the count value
4 of the timer 2 is read out.
5
6
7
At reset R W
1
0
0
0
0
0
0
0
Fig. 3.5.13 Structure of Timer 2
38C3 Group User’s Manual
3-45
APPENDIX
3.5 Control registers
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
0
1
2
3
4
5
6
Functions
• In timer 6 PWM1 mode
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
Fig. 3.5.14 Structure of Timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
Name
0 Timer 1 count stop
bit
1 Timer 2 count stop
bit
2 Timer 1 count
source selection
3 bits
4 Timer 2 count
source selection
bits
5
Functions
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
0 0: f(XIN)/16 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
b5 b4
0 0: Timer 1 underflow
0 1: f(XCIN)
1 0: External count input
CNTR0
1 1: Not available
0: I/O port
6 Timer 1 output
selection bit (P41) 1: Timer 1 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 3.5.15 Structure of Timer 12 mode register
3-46
At reset R W
38C3 Group User’s Manual
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
Name
0 Timer 3 count stop
bit
1 Timer 4 count stop
bit
2 Timer 3 count
source selection
3 bits
4 Timer 4 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1
1 1: Not available
0: I/O port
6 Timer 3 output
selection bit (P42) 1: Timer 3 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 3.5.16 Structure of Timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
Name
0 Timer 5 count stop
bit
1 Timer 6 count stop
bit
2 Timer 5 count
source selection bit
3 Timer 6 operation
mode selection bit
4 Timer 6 count
source selection
5 bits
Functions
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0: f(XIN)/16 or f(XCIN)/16
1: Timer 4 underflow
0: Timer mode
1: PWM mode
b5 b4
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
6 Timer 6 (PWM)
output selection bit
(P52)
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.17 Structure of Timer 56 mode register
38C3 Group User’s Manual
3-47
APPENDIX
3.5 Control registers
φ output control register
b7 b6 b5 b4 b3 b2 b1 b0
φ output control register
(CKOUT: address 2B16)
b
Name
Functions
0 φ output control bit 0: Port function
(P43)
1: φ clock output
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read out,
3 the contents are “0”.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.18 Structure of φ output control register
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer A register (low-order, high-order)
(TAL, TAH: addresses 2C16, 2D16)
b
Functions
0 • Set timer A count value.
1 • When the timer A write control bit of the timer
A mode register is “0”, the value is written to
2
timer A and the latch at one time.
3
When the timer A write control bit of the timer
A mode register is “1”, the value is written only
4
to the latch.
5
• The timer A count value is read out by reading
6
this register.
7
At reset R W
1
1
1
1
1
1
1
1
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes.
2: Read both registers in order of TAH and TAL following.
3: Write both registers in order of TAL and TAH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 3.5.19 Structure of Timer A register (low-order, high-order)
3-48
38C3 Group User’s Manual
APPENDIX
3.5 Control registers
Compare register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Compare register (low-order, high-order)
(CONAL, CONAH: addresses 2E16, 2F16)
b
Functions
At reset R W
0 • Set compare register value.
0
1
0
2
3
0
4
0
5
0
6
7
0
0
0
Note: Write registers in order of CONAH, CONAL, TAL, and TAH
following.
Fig. 3.5.20 Structure of Compare register (low-order, high-order)
Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A mode register
(TAM: address 3016)
b
Name
0 Timer A operating
mode bits
1
2 Timer A write control
bit
3 Timer A count source
selection bits
4
5 Timer A output active
edge switch bit
Functions
b1b0
At reset R W
0 0: Timer mode
0 1: Pulse output mode
1 0: IGBT output mode
1 1: PWM mode
0
0: Write data to both timer
latch and timer
1: Write data to timer latch
0
b4b3
0
0 0: f(XIN)
0 1: f(XIN)/2
1 0: f(XIN)/4
1 1: f(XIN)/8
0: Output starts with “L” level
1: Output starts with “H” level
6 Timer A count stop bit 0: Count operating
0
0
0
0
1: Count stop
7 Timer A output
selection bit (P50)
0: I/O port
1: Timer A output
0
Fig. 3.5.21 Structure of Timer A mode register
38C3 Group User’s Manual
3-49
APPENDIX
3.5 Control registers
Timer A control register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A control register
(TACON: address 3116)
b
Name
0 Noise filter sampling
clock selection bit
1 External trigger delay
time selection bits
2
Functions
0: f(XIN)/2
1: f(XIN)/4
0
b2b1
0
0 0: No delay
0 1: (4/f(XIN))µs
1 0: (8/f(XIN))µs
1 1: (16/f(XIN))µs
3 Timer A output control 0: Not used
bit 1 (P56)
0
0
1: INT1 interrupt used
4 Timer A output control 0: Not used
bit 2 (P57)
At reset R W
0
1: INT2 interrupt used
5 Nothing is arranged for these bits. These are write
6 disabled bits. When these bits are read out, the
7 contents are “0”.
0
0
0
Fig. 3.5.22 Structure of Timer A control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
Functions
b2 b1 b0
0 0 0: P60/AN0
0 0 1: P61/AN1
0 1 0: P62/AN2
0 1 1: P63/AN3
1 0 0: P64/AN4
1 0 1: P65/AN5
1 1 0: P66/AN6
1 1 1: P67/AN7
3 Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
Fig. 3.5.23 Structure of A-D control register
3-50
38C3 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
0
1
2
3
4
5
6
7
Functions
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 3.5.24 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
This is A-D conversion result (high-order 8 bits) stored Undefined
bits. This is read exclusive register.
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 3.5.25 Structure of A-D conversion register (high-order)
38C3 Group User’s Manual
3-51
APPENDIX
3.5 Control registers
Segment output enable register
b7 b6 b5 b4 b3 b2 b1 b0
Segment output enable register
(SEG: address 3816)
b
Name
0 Segment output
enable bit 0
1 Segment output
enable bit 1
2 Segment output
enable bit 2
3 Segment output
enable bit 3
4 Segment output
enable bit 4
5 Segment output
enable bit 5
6 Segment output
enable bit 6
7 Segment output
enable bit 7
Functions
0: I/O ports P20–P23
1: Segment output SEG0–SEG3
0: I/O ports P24–P27
1: Segment output SEG4–SEG7
0: I/O ports P00–P03
1: Segment output SEG8–SEG11
0: I/O ports P04–P07
1: Segment output SEG12–SEG15
0: I/O ports P10–P13
1: Segment output SEG16–SEG19
0: I/O ports P14–P17
1: Segment output SEG20–SEG23
0: Output ports P30–P33
1: Segment output SEG24–SEG27
0: Output ports P34–P37
1: Segment output SEG28–SEG31
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.26 Structure of Segment output enable register
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
LCD mode register
(LM: address 3916)
b
Name
0 Duty ratio selection
bits
Functions
b1b0
0 0: 1 (use COM0)
0 1: 2 (use COM0, COM1)
1 0: 3 (use COM0–COM2)
1 1: 4 (use COM0–COM3)
0
2 Bias control bit
0: 1/3 bias
1: 1/2 bias
0
3 LCD enable bit
0: LCD OFF
1: LCD ON
0
1
4 Fix “0” to this bit.
5 LCD circuit divider
b6b5
division ratio selection 0 0: Clock input
0 1: 2 division of clock input
bits
6
1 0: 4 division of clock input
1 1: 8 division of clock input
7 LCDCK count source 0: f(XCIN)/32
1: f(XIN)/8192 (f(XCIN)/8192 in
selection bit (Note)
low-speed mode)
Note: LCDCK is a clock for a LCD timing controller.
Fig. 3.5.27 Structure of LCD mode register
3-52
At reset R W
38C3 Group User’s Manual
0
0
0
0
0
APPENDIX
3.5 Control registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16)
b
Name
Functions
At reset R W
0 INT0 interrupt edge 0: Falling edge active
1: Rising edge active
selection bit
1 INT1 interrupt edge 0: I/O ports P24–P27
1: Segment output SEG4–SEG7
selection bit
INT
2
interrupt
edge
0: I/O ports P00–P03
2
1: Segment output SEG8–SEG11
selection bit
3 Nothing is arranged for these bits. These are
4 write disabled bits. When these bits are read out,
5 the contents are “0”.
6 CNTR0 active edge 0: Falling edge active,
switch bit
rising edge count
1: Rising edge active,
falling edge count
0
7 CNTR1 active edge 0: Falling edge active,
switch bit
rising edge count
1: Rising edge active,
falling edge count
0
0
0
0
0
0
0
Fig. 3.5.28 Structure of Interrupt edge selection register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16)
b
Name
0 Processor mode
bits
1
Functions
b1 b0
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
2 Stack page
selection bit
3 Nothing is arranged for this bit. When this bit is
read out, the contents is “1”. Do not write “0” to
this bit.
4 Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
5 Main clock (XIN1: Stopped
XOUT) stop bit
6 Main clock division 0: f(XIN)/2 (high-speed
mode)
ratio selection bit
1: f(XIN)/8 (middle-speed
mode)
7 Internal system
clock selection bit
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
At reset R W
0
0
0
1
0
0
1
0
Fig. 3.5.29 Structure of CPU mode register
38C3 Group User’s Manual
3-53
APPENDIX
3.5 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
3 Serial I/O interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
4 Timer A interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.30 Structure of Interrupt request register 1
3-54
At reset R W
0 INT0 interrupt
request bit
38C3 Group User’s Manual
APPENDIX
3.5 Control registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit
Timer
5
interrupt
0 : No interrupt request issued
1
1 : Interrupt request issued
request bit
0 : No interrupt request issued
2 Timer 6 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
3 CNTR0 interrupt
1 : Interrupt request issued
request bit
1
interrupt
CNTR
0 : No interrupt request issued
4
1 : Interrupt request issued
request bit
5 Key input interrupt 0 : No interrupt request issued
1 : Interrupt request issued
request bit
0 : No interrupt request issued
6 AD conversion
interrupt request bit 1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.31 Structure of Interrupt request register 2
38C3 Group User’s Manual
3-55
APPENDIX
3.5 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
0
INT0 interrupt
enable bit
INT1 interrupt
enable bit
INT2 interrupt
enable bit
Serial I/O interrupt
enable bit
Timer A interrupt
enable bit
Timer 1 interrupt
enable bit
Timer 2 interrupt
enable bit
Timer 3 interrupt
enable bit
1
2
3
4
5
6
7
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.32 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
0 Timer 4 interrupt
0 : Interrupt disabled
enable bit
1 : Interrupt enabled
1 Timer 5 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
2 Timer 6 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
3 CNTR0 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0 : interrupt disabled
4 CNTR1 interrupt
1 : Interrupt enabled
enable bit
5 Key input interrupt 0 : interrupt disabled
1 : Interrupt enabled
enable bit
6 AD conversion
0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
Fig. 3.5.33 Structure of Interrupt control register 2
3-56
38C3 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
ROM correct enable register 1
b7 b6 b5 b4 b3 b2 b1 b0
ROM correct enable register 1
(RC1: address 0F0116)
b
Name
0 ROM correct
address 1 enable bit
1 ROM correct
address 2 enable bit
2 ROM correct
address 3 enable bit
3 ROM correct
address 4 enable bit
4 ROM correct
address 5 enable bit
5 ROM correct
address 6 enable bit
6 ROM correct
address 7 enable bit
7 ROM correct
address 8 enable bit
Functions
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.34 Structure of ROM correct enable register 1
38C3 Group User’s Manual
3-57
APPENDIX
3.6 Mask ROM confirmation form
3.6 Mask ROM confirmation form
GZZ-SH56-24B<91A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Microcomputer name:
M38C34M6AXXXFP
Ordering by EPROMs
Specify the type of EPROMs submitted.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38C34M6A’
data
ROM (24K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address A08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38C34M6A’
data
ROM (24K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38C34M6A”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-58
38C3 Group User’s Manual
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘C’ = 43 16
‘3’ = 33 16
‘4’ = 34 16
‘M’ = 4D16
‘6’ = 36 16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘A’ = 4116
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH56-24B<91A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38C34M6A’
*= $0000
.BYTE ‘M38C34M6A’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the
responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N for M38C34M6AXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
38C3 Group User’s Manual
3-59
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH56-25B<91A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Microcomputer name:
M38C34M6MXXXFP
Ordering by EPROMs
Specify the type of EPROMs submitted.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38C34M6M’
data
ROM (24K-130) bytes
In the address space of the microcomputer, the internal
ROM area is from address A08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38C34M6M’
data
ROM (24K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38C34M6M”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-60
38C3 Group User’s Manual
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘C’ = 43 16
‘3’ = 33 16
‘4’ = 34 16
‘M’ = 4D16
‘6’ = 36 16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH56-25B<91A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38C34M6M’
*= $0000
.BYTE ‘M38C34M6M’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the
responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N for M38C34M6MXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
38C3 Group User’s Manual
3-61
APPENDIX
3.7 ROM programming confirmation form
3.7 ROM programming confirmation form
GZZ-SH56-29B<91A0>
ROM number
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce writing to PROM based on
this data. We shall assume the responsibility for errors only if the written PROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
EPROM address
(hexadecimal notation)
EPROM type (indicate the type used)
27512
EPROM address
000016
000F16
001016
Product name
ASCII code :
‘M38C37ECA’
407F16
408016
Data
ROM 48K-130 bytes
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
Address
Address
000016
000816
‘M’ = 4D16
‘ A ’ =4116
(1) Set the data in the unused area (the shaded area of
000116
‘3’ = 3316
000916
FF16
the diagram) to “FF16”.
000216
000A16
‘8’ = 3816
FF16
(2) The ASCII codes of the product name “M38C37ECA”
000316
‘C’ = 4316
000B16
FF16
must be entered in addresses 000016 to 000816. And
000416
000C16
‘3’ = 3316
FF16
000516
‘7’ = 3716
000D16
FF16
set the data “FF16” in addresses 000916 to 000F16.
000616
000E16
‘E’ = 4516
FF16
The ASCII codes and addresses are listed to the right
‘C’ = 4316
FF16
000716
000F16
in hexadecimal notation.
(1/2)
3-62
38C3 Group User’s Manual
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH56-29B<91A0>
ROM number
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE ‘M38C37ECA’
Note : If the name of the product written to the EPROMs does not match the name of the writing to PROM confirmation
form, the ROM will not be processed.
Ordering by floppy disk
We will produce writing to PROM based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the written PROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
80P6N mark specification form and attach it to the writing to PROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
38C3 Group User’s Manual
3-63
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH56-30B<91A0>
ROM number
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce writing to PROM based on
this data. We shall assume the responsibility for errors only if the written PROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
EPROM address
(hexadecimal notation)
EPROM type (indicate the type used)
27512
EPROM address
000016
000F16
001016
Product name
ASCII code :
‘M38C37ECM’
407F16
408016
Data
ROM 48K-130 bytes
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
Address
Address
‘M’ = 4D16
‘ M ’ =4D16
000016
000816
000116
000916
‘3’ = 3316
FF16
(1) Set the data in the unused area (the shaded area of
000216
‘8’ = 3816
000A16
FF16
the diagram) to “FF16”.
000316
000B16
‘C’ = 4316
FF16
(2) The ASCII codes of the product name “M38C37ECM”
000416
‘3’ = 3316
000C16
FF16
must be entered in addresses 000016 to 000816. And
000516
000D16
‘7’ = 3716
FF16
set the data “FF16” in addresses 000916 to 000F16.
000616
‘E’ = 4516
000E16
FF16
The ASCII codes and addresses are listed to the right
‘C’ = 4316
FF16
000716
000F16
in hexadecimal notation.
(1/2)
3-64
38C3 Group User’s Manual
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH56-30B<91A0>
ROM number
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE ‘M38C37ECM’
Note : If the name of the product written to the EPROMs does not match the name of the writing to PROM confirmation
form, the ROM will not be processed.
Ordering by floppy disk
We will produce writing to PROM based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the written PROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
80P6N mark specification form and attach it to the writing to PROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
38C3 Group User’s Manual
3-65
APPENDIX
3.8 Mark specification form
3.8 Mark specification form
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
25
80
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
25
80
1
24
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas, periods and so on.
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
C. Special Mark Required
64
41
65
40
80
25
1
Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box below.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
24
Special character fonts required
3-66
38C3 Group User’s Manual
APPENDIX
3.9 Package outline
3.9 Package outline
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
HD
D
b2
1
ME
65
80
64
I2
E
24
HE
Recommended Mount Pad
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
41
A
40
25
c
A2
L1
b
F
A1
e
L
b2
I2
MD
ME
Detail F
y
80D0
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.8
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
0.1
–
–
0°
10°
–
0.5
–
–
–
–
1.3
14.6
–
–
–
–
20.6
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
21.0±0.2
Weight(g)
18.4±0.15
3.32MAX
0.8TYP
1.78TYP
0.6TYP
64
41
65
INDEX
0.5TYP
38C3 Group User’s Manual
0.8TYP
12.0±0.15
1.2TYP
15.6±0.2
0.8TYP
40
25
80
24
1.2TYP
1
3-67
APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
A
# OP n
Addressing mode
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
#
ZP, X
ZP, Y
OP n
# OP n
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
75 4
2
6D 4
3 7D 5
3 79 5
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
06 5
2
16 6
2
0E 6
3 1E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13 4
+
20i
2
17 5
+
20i
3
•
•
•
•
•
•
•
•
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03 4
+
20i
2
07 5
+
20i
3
•
•
•
•
•
•
•
•
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
90 2
2
•
•
•
•
•
•
•
•
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
B0 2
2
•
•
•
•
•
•
•
•
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
F0 2
2
•
•
•
•
•
•
•
•
BIT
A
M7 M6 •
•
•
•
Z
•
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
30 2
2
•
•
•
•
•
•
•
•
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
D0 2
2
•
•
•
•
•
•
•
•
3-68
V
M
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
38C3 Group User’s Manual
24 3
2
2C 4
3
38C3 Group User’s Manual
3-69
APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
Addressing mode
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
10 2
2
•
•
•
•
•
•
•
•
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
80 4
2
•
•
•
•
•
•
•
•
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
•
•
•
1
•
1
•
•
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
50 2
2
•
•
•
•
•
•
•
•
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
70 2
2
•
•
•
•
•
•
•
•
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
CLC
C←0
This instruction clears C.
18 2
1
•
•
•
•
•
•
•
0
CLD
D←0
This instruction clears D.
D8 2
1
•
•
•
•
0
•
•
•
CLI
I←0
This instruction clears I.
58 2
1
•
•
•
•
•
0
•
•
CLT
T←0
This instruction clears T.
12 2
1
•
•
0
•
•
•
•
•
CLV
V←0
This instruction clears V.
B8 2
1
•
0
•
•
•
•
•
•
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
C
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
•
•
•
•
•
Z
•
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
00 7
1
1B 2
+
20i
C9 2
1
1F 5
+
20i
2
C5 3
2
44 5
2
2
E4 3
2
EC 4
3
N
•
•
•
•
•
Z
C
2
C4 3
2
CC 4
3
N
•
•
•
•
•
Z
C
C6 5
2
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
2
D5 4
2
CD 4
3 DD 5
3 D9 5
3
C1 6
2 D1 6
2
__
3-70
38C3 Group User’s Manual
1A 2
1
D6 6
2
3
38C3 Group User’s Manual
3-71
APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
BIT, A
# OP n
Addressing mode
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
N
•
•
•
•
•
Z
•
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
N
•
•
•
•
•
Z
•
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's complement of the remainder is pushed onto the stack.
•
•
•
•
•
•
•
•
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
When T = 1
–M
M(X) ← M(X) V
E2 16 2
49 2
2
45 3
2
55 4
2
4D 4
3 5D 5
3 59 5
E6 5
2
F6 6
2
EE 6
3 FE 7
3
3
41 6
2 51 6
2
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
N
•
•
•
•
•
Z
•
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
N
•
•
•
•
•
Z
•
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
4C 3
3
•
•
•
•
•
•
•
•
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
20 6
3
•
•
•
•
•
•
•
•
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
AD 4
3 BD 5
N
•
•
•
•
•
Z
•
LDM
M ← nn
This instruction loads the immediate value in
M.
•
•
•
•
•
•
•
•
LDX
X←M
This instruction loads the contents of M in X.
A2 2
N
•
•
•
•
•
Z
•
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
N
•
•
•
•
•
Z
•
3-72
3A 2
38C3 Group User’s Manual
A9 2
2
1
A5 3
2
3C 4
3
2
A6 3
2
2
A4 3
2
B5 4
2
B6 4
B4 4
2
2 AE 4
AC 4
6C 5
3 B9 5
3
3 BC 5
BE 5
3
3 B2 4
2
02 7
2
22 5
A1 6
2 B1 6
3
3
38C3 Group User’s Manual
2
2
3-73
APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
This instruction multiply Accumulator with the
memory specified by the Zero Page X address
mode and stores the high-order byte of the result on the Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
1
# OP n
46 5
BIT, ZP
# OP n
2
#
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
1
09 2
2
05 3
2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
48 3
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
82 8
2
•
•
•
•
•
•
•
•
0
←C ←
RRF
7
→
3-74
# OP n
ZP
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
7
C→
RTS
BIT, A
Processor status register
M(S) ← A
S←S–1
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
Addressing mode
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
d e s i g n a t e d b y S i n P C L. S i s a g a i n
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
(Value saved in stack)
(Value saved in stack)
40 6
1
60 6
1
•
38C3 Group User’s Manual
38C3 Group User’s Manual
•
•
•
•
•
•
•
3-75
APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
E9 2
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
A
# OP n
Addressing mode
BIT, A
# OP n
ZP
# OP n
E5 3
2
BIT, ZP
# OP n
#
2
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
•
•
•
•
•
•
•
1
SED
D←1
This instruction set D.
F8 2
1
•
•
•
•
1
•
•
•
SEI
I←1
This instruction set I.
78 2
1
•
•
•
•
•
1
•
•
SET
T←1
This instruction set T.
32 2
1
•
•
1
•
•
•
•
•
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
0B 2
+
20i
1
0F 5
+
20i
85 4
42 2
2
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X.
The contents of A does not change.
AA 2
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
A8 2
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
TSX
X←S
This instruction transfers the contents of S in
X.
BA 2
TXA
A←X
This instruction stores the contents of X in A.
TXS
S←X
TYA
A←Y
Notes 1
2
3
4
5
3-76
:
:
:
:
:
95 5
8D 5
2
3 9D 6
3 99 6
3
81 7
2 91 7
1
STX
WIT
2
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
1
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
8A 2
1
N
•
•
•
•
•
Z
•
This instruction stores the contents of X in S.
9A 2
1
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in A.
98 2
1
N
•
•
•
•
•
Z
•
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
C2 2
1
•
•
•
•
•
•
•
•
64 3
96 5
2
94 5
2
2
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
38C3 Group User’s Manual
38C3 Group User’s Manual
3-77
APPENDIX
3.10 Machine instructions
Symbol
Contents
Symbol
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
3-78
38C3 Group User's Manual
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
3.11 List of instruction code
3.11 List of instruction code
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
BBS
ORA
JSR
IND, X ZP, IND 0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ROR
CLB
ADC
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
38C3 Group User’s Manual
3-79
APPENDIX
3.12 SFR memory map
3.12 SFR memory map
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
002016 Timer 1 (T1)
002116 Timer 2 (T2)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
002216 Timer 3 (T3)
002316 Timer 4 (T4)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
002416 Timer 5 (T5)
000616 Port P3 (P3)
002616
000716
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
002716 Timer 6 PWM register (T6PWM)
002816 Timer 12 mode register (T12M)
002916 Timer 34 mode register (T34M)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
002A16 Timer 56 mode register (T56M)
002B16 φ output control register (CKOUT)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
002C16 Timer A register (low) (TAL)
002D16 Timer A register (high) (TAH)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
002E16 Compare register (low) (CONAL)
001016 Port P8 (P8)
001116 Port P8 direction register (P8D)
003016 Timer A mode register (TAM)
003116 Timer A control register (TACON)
001216
003216 A-D control register (ADCON)
001316
001416
003316 A-D conversion register (low) (ADL)
003416 A-D conversion register (high) (ADH)
001516
003516
001616 PULL register A (PULLA)
001716 PULL register B (PULLB)
003616
001816 Port P8 output selection register (P8SEL)
001916 Serial I/O control register 1 (SIOCON1)
003816 Segment output enable register (SEG)
002516 Timer 6 (T6)
002F16 Compare register (high) (CONAH)
003716
001A16 Serial I/O control register 2 (SIOCON2)
001B16 Serial I/O register (SIO)
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
001C16
001D16
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001E16
001F16
0F01 16 ROM correct enable register 1 (Note)
0F02 16 ROM correct high-order address register 1 (Note)
0F0316 ROM correct low-order address register 1 (Note)
0F0A16 ROM correct high-order address register 5 (Note)
0F0B16 ROM correct low-order address register 5 (Note)
0F0C16 ROM correct high-order address register 6 (Note)
0F04 16 ROM correct high-order address register 2 (Note)
0F0D16 ROM correct low-order address register 6 (Note)
0F05 16 ROM correct low-order address register 2 (Note)
0F0616 ROM correct high-order address register 3 (Note)
0F0E16 ROM correct high-order address register 7 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F10 16 ROM correct high-order address register 8 (Note)
0F07 16 ROM correct low-order address register 3 (Note)
0F08 16 ROM correct high-order address register 4 (Note)
0F11 16 ROM correct low-order address register 8 (Note)
0F0916 ROM correct low-order address register 4 (Note)
Note: This register is valid only in mask ROM version.
3-80
38C3 Group User’s Manual
APPENDIX
3.13 Pin configuration
41
43
42
45
44
46
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
65
40
66
39
67
68
38
37
69
36
35
34
70
71
72
33
M38C34M6AXXXFP
73
32
74
31
75
30
76
77
29
28
78
27
79
26
25
24
22
23
21
20
18
19
17
16
13
14
15
12
9
10
11
8
5
6
7
4
3
2
1
80
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM0
COM1
COM2
COM3
VL1
VL2
VL3
P80
P61/AN1
P60/AN0
P57/INT2
P56/INT1
P55/INT0
P54/CNTR1
P53/CNTR0
P52/PWM1
P51
RESET
P71/XcOUT
P70/XcIN
VSS
XIN
XOUT
VCC
P50/TAOUT
P87
P86
P85
P84
P83
P82
P81
P47/SRDY
P46/SCLK1
P45/SOUT
P44/SIN
P43/φ
P42/T3OUT
P41/T1OUT
P40/SCLK2
AVSS
VREF
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
61
64
63
P20/SEG0
P21/SEG1
P22/SEG2
P23/SEG3
P24/SEG4
P25/SEG5
P26/SEG6
P27/SEG7
P00/SEG8
P01/SEG9
P02/SEG10
P03/SEG11
P04/SEG12
P05/SEG13
P06/SEG14
P07/SEG15
P10/SEG16
P11/SEG17
P12/SEG18
P13/SEG19
P14/SEG20
P15/SEG21
P16/SEG22
P17/SEG23
3.13 Pin configuration
(Top view)
Package type: 80P6N-A
80-pin plastic molded QFP
38C3 Group User’s Manual
3-81
APPENDIX
3.13 Pin configuration
MEMORANDUM
3-82
38C3 Group User’s Manual
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
38C3 Group
Apr. First Edition 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
38C3 Group
© 1999 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Apr. 1999.
Specifications subject to change without notice.