256MB, 512MB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 256Mb F-die 64/72-bit Non-ECC/ECC INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered DIMM Ordering Information Part Number Density Organization M378T3253FG(Z)3-CE6/D5/CC 256MB 32Mx64 M378T3253FG(Z)0-CE6/D5/CC 256MB 32Mx64 M378T6453FG(Z)3-CE6/D5/CC 512MB M378T6453FG(Z)0-CE6/D5/CC 512MB Component Composition Number of Rank Height 32Mx8(K4T56083QF)*8 1 30mm 32Mx8(K4T56083QF)*8 1 30mm 64Mx64 32Mx8(K4T56083QF)*16 2 30mm 64Mx64 32Mx8(K4T56083QF)*16 2 30mm x64 Non ECC x72 ECC M391T3253FG(Z)3-CE6/D5/CC 256MB 32Mx72 32Mx8(K4T56083QF)*9 1 30mm M391T3253FG(Z)0-CE6/D5/CC 256MB 32Mx72 32Mx8(K4T56083QF)*9 1 30mm M391T6453FG(Z)3-CE6/D5/CC 512MB 64Mx72 32Mx8(K4T56083QF)*18 2 30mm M391T6453FG(Z)0-CE6/D5/CC 512MB 64Mx72 32Mx8(K4T56083QF)*18 2 30mm Note: “Z” of Part number(11th digit) stand for Lead-free products. Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products. Features • Performance range E6(DDR2-667) D5(DDR2-533) CC(DDR2-400) Unit Speed@CL3 400 400 400 Mbps Speed@CL4 533 533 400 Mbps Speed@CL5 667 - - Mbps CL-tRCD-tRP 5-5-5 4-4-4 3-3-3 CK • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin • 4 Banks • Posted CAS • Programmable CAS Latency: 3, 4, 5 • Programmable Additive Latency: 0, 1 , 2 , 3 and 4 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature • Package: 60ball FBGA - 32Mx8 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 32Mx8(256Mb) based Module A0-A12 A0-A9 BA0-BA1 A10 Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM x64 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5 2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC 3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS 4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46 5 VSS 125 DM0 35 VSS 155 DM3 95 DQ42 215 DQ47 KEY 6 DQS0 126 NC 36 DQS3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS 7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK0 97 VSS 217 DQ52 DQ53 8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS 10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2 CK2 11 VSS 131 DQ12 41 VSS 161 NC 70 A10/AP 190 BA1 101 SA2 221 12 DQ8 132 DQ13 42 NC 162 NC 71 BA0 191 VDDQ 102 222 VSS 13 DQ9 133 VSS 43 NC 163 VSS 72 VDDQ 192 RAS 103 NC, TEST2 VSS 223 DM6 14 VSS 134 DM1 44 VSS 164 NC 73 WE 193 S0 104 DQS6 224 NC 15 DQS1 135 NC 45 NC 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS 16 DQS1 136 VSS 46 NC 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54 17 VSS 137 CK1 47 VSS 167 NC 76 S1 196 107 DQ50 227 DQ55 18 NC 138 CK1 48 NC 168 NC 77 ODT1 197 NC VDD 108 DQ51 228 VSS 19 NC 139 VSS 49 NC 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60 DQ61 20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS 22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7 23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS7 233 NC 24 DQ16 144 DQ21 54 NC 174 NC 83 DQS4 203 NC 114 DQS7 234 VSS 25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62 26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63 27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS 28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD 29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0 30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 120 SCL 240 SA1 90 DQ41 210 DQ45 VSS NC = No Connect, RFU = Reserved for Future Use 1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM x72 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5 2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC 3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS 4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46 5 VSS 125 DM0 35 VSS 155 DM3 95 DQ42 215 DQ47 KEY 6 DQS0 126 NC 36 DQS3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS 7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK0 97 VSS 217 DQ52 8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS 10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2 CK2 11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC, TEST2 222 VSS 13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6 14 VSS 134 DM1 44 VSS 164 DM8 73 WE 193 S0 104 DQS6 224 NC 15 DQS1 135 NC 45 DQS8 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS 16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54 17 VSS 137 CK1 47 VSS 167 CB6 76 S1 196 NC 107 DQ50 227 DQ55 18 NC 138 CK1 48 CB2 168 CB7 77 ODT1 197 VDD 108 DQ51 228 VSS 19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60 DQ61 20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS 22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7 23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS7 233 NC 24 DQ16 144 DQ21 54 NC 174 NC 83 DQS4 203 NC 114 DQS7 234 VSS 25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62 26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63 27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS 28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD 29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0 30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1 90 DQ41 210 VSS NC = No Connect, RFU = Reserved for Future Use 1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Pin Description Pin Name Description Pin Name Description A0-A12 DDR2 SDRAM address bus CK0, CK1, CK2 DDR2 SDRAM clocks (positive line of differential pair) BA0, BA1 DDR2 SDRAM bank select CK0, CK1, CK2 DDR2 SDRAM clocks (negative line of differential pair) RAS DDR2 SDRAM row address strobe SCL I2C serial bus clock for EEPROM CAS DDR2 SDRAM column address strobe SDA I2C serial bus data line for EEPROM WE DDR2 SDRAM wirte enable S0, S1 DIMM Rank Select Lines SA0-SA2 VDD* I2C serial address select for EEPROM DDR2 SDRAM core power supply CKE0,CKE1 DDR2 SDRAM clock enable lines VDDQ* DDR2 SDRAM I/O Driver power supply ODT0, ODT1 On-die termination control lines VREF DDR2 SDRAM I/O reference supply VSS Power supply return (ground) DQ0 - DQ63 CB0 - CB7 DIMM memory data bus DIMM ECC check bits VDDSPD DQS0 - DQS8 DDR2 SDRAM data strobes NC DM(0-8) DDR2 SDRAM data masks RESET DQS0-DQS8 DDR2 SDRAM differential data strobes TEST Serial EEPROM positive power supply Spare Pins(no connect) Not used on UDIMM Used by memory bus analysis tools (unused on memory DIMMs) * The VDD and VDDQ pins are tied to the single power-plane on PCB. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Input/Output Functional Description Type Function CK0-CK2 CK0-CK2 Symbol Input CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing) CKE0-CKE1 Input Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode S0-S1 Input Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disbled, new command are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks RAS, CAS, WE Input RAS, CAS, and WE (ALONG WITH CS) define the command being entered. ODT0-ODT1 Input When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the Extended Mode Register Set (EMRS). VREF Supply Reference voltage for SSTL 18 inputs. VDDQ Supply Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA0-BA1 Input Selects which SDRAM BANK of four is activated. During a Bank Activate command cycle, Address input defines the row address (RA0-RA13) During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to precharge. A0-A13 Input DQ0-DQ63 CB0-CB7 In/Out Data and Check Bit Input/Output pins. DM0-DM8 Input DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. VDD,VSS Supply Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. DQS0-DQS8 DQS0-DQS8 In/Out Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM SA0-SA2 Input These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM address range. SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup on the system board. SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup onthe system board. VDD SPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs) M378T3253FG(Z)3 / M378T3253FG(Z)0 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQS1 DQS1 DM1 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS D4 DQS5 DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DQS2 DQS2 DM2 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS D5 DQS6 DQS6 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQS3 DQS3 DM3 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS D6 DQS7 DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NU/ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS D3 Serial PD SCL SDA WP A0 SA0 BA0 - BA1 A0 - A12 RAS A1 SA1 DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 A2 SA2 VDDSPD Serial PD VDD/VDDQ D0 - D7 VREF D0 - D7 VSS BA0-BA1 : DDR2 SDRAMs D0 - D7 A0-A12 : DDR2 SDRAMs D0 - D7 CAS : DDR2 SDRAMs D0 - D7 CKE0 CKE : DDR2 SDRAMs D0 - D7 WE DQS DQS D7 * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 2 DDR2 SDRAMs 3 DDR2 SDRAMs 3 DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams RAS : DDR2 SDRAMs D0 - D7 CAS ODT0 D0 - D7 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WE : DDR2 SDRAMs D0 - D7 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%. ODT : DDR2 SDRAMs D0 - D7 Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Functional Block Diagram: 256MB, 32Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs) M391T3253FG(Z)3 / M391T3253FG(Z)0 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQS1 DQS1 DM1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DQS2 DQS2 DM2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM D2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D5 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 DQS8 DQS8 DM8 DQS DQS D6 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS D7 Serial PD DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS SCL DQS DQS BA0-BA1 : DDR2 SDRAMs D0 - D8 A0-A12 : DDR2 SDRAMs D0 - D8 RAS : DDR2 SDRAMs D0 - D8 CAS CAS : DDR2 SDRAMs D0 - D8 CKE : DDR2 SDRAMs D0 - D8 WE : DDR2 SDRAMs D0 - D8 SDA WP D8 CKE0 ODT0 DQS DQS DQS7 DQS7 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 WE CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQS3 DM3 RAS D4 DQS6 DQS6 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A0 - A12 DQS DQS DQS5 DQS5 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 - BA1 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A0 A1 A2 SA0 SA1 SA2 VDDSPD Serial PD VDD/VDDQ D0 - D8 VREF D0 - D8 VSS D0 - D8 * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 3 DDR2 SDRAMs 3 DDR2 SDRAMs 3 DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%. ODT : DDR2 SDRAMs D0 - D8 Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Functional Block Diagram: 512B, 64Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs) M378T6453FG(Z)3 / M378T6453FG(Z)0 S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 DQS DQS DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 DQS1 DQS1 DM1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS DQS D12 DQS5 DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 DQS DQS DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DQS2 DQS2 DM2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DQS DQS D13 DQS6 DQS6 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 DQS DQS DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DQS3 DQS3 DM3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS DQS D14 DQS7 DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 - A12 D3 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Serial PD VDD/VDDQ D0 - D15 VREF D0 - D15 DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 BA0-BA1 : DDR2 SDRAMs D0 - D15 A0-A12 : DDR2 SDRAMs D0 - D15 CKE : DDR2 SDRAMs D0 - D7 CKE1 CKE : DDR2 SDRAMs D8 - D15 RAS RAS : DDR2 SDRAMs D0 - D15 CAS CAS : DDR2 SDRAMs D0 - D15 WE WE : DDR2 SDRAMs D0 - D15 ODT : DDR2 SDRAMs D0 - D7 ODT : DDR2 SDRAMs D8 - D15 CS D7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS D15 Serial PD SCL SDA WP A0 A1 A2 SA0 SA1 SA2 D0 - D15 CKE0 ODT0 ODT1 DQS DQS D11 VDDSPD VSS BA0 - BA1 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 4 DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs) M391T6453FG(Z)3 / M391T6453FG(Z)0 S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 CS DQS DQS DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQS1 DQS1 DM1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 CS DQS DQS DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 DQS2 DQS2 DM2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS3 DQS3 DM3 DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS DQS D13 CS DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DQS DQS D14 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS DQS D15 DQS7 DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 CS DQS DQS DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D12 DQS8 DQS8 DM8 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 DQS DQS D16 Serial PD DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D8 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CKE : DDR2 SDRAMs D0 - D8 CKE : DDR2 SDRAMs D9 - D17 RAS RAS : DDR2 SDRAMs D0 - D17 CAS CAS : DDR2 SDRAMs D0 - D17 WE WE : DDR2 SDRAMs D0 - D17 ODT : DDR2 SDRAMs D0 - D8 ODT : DDR2 SDRAMs D9 - D17 SDA WP D17 A0-A12 : DDR2 SDRAMs D0 - D17 CKE0 SCL DQS DQS BA0-BA1 : DDR2 SDRAMs D0 - D17 CKE1 ODT0 ODT1 DQS DQS DQS6 DQS6 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A0 - A12 CS DQS5 DQS5 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 - BA1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A0 A1 A2 SA0 SA1 SA2 * Clock Wiring VDDSPD Serial PD VDD/VDDQ D0 - D17 VREF D0 - D17 VSS D0 - D17 Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 6 DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Absolute Maximum DC Ratings Symbol Rating Units Notes Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1 Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1 -55 to +100 °C 1, 2 VDD VIN, VOUT TSTG Parameter Storage Temperature Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1.8) Symbol Parameter Rating Min. Typ. Max. 1.7 1.8 1.9 Units Notes VDD Supply Voltage VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4 VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2 Termination Voltage VREF-0.04 VREF VREF+0.04 V 3 VTT V Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Operating Temperature Condition Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 °C 1, 2, 3 Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported. 3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. Input DC Logic Level Symbol Parameter Min. Max. Units VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V VIL(DC) DC input logic low VDDQ- 0.3 VREF - 0.125 V Notes Input AC Logic Level DDR2-400, DDR2-533 Symbol Parameter VIH (AC) AC input logic high VIL (AC) AC input logic low Min. DDR2-667 Max. Min. VREF + 0.250 - VREF + 0.200 - VREF - 0.250 Max. Units Notes V VREF - 0.200 V AC Input Test Conditions Symbol VREF VSWING(MAX) SLEW Condition Value Units 0.5 * VDDQ V 1 Input signal maximum peak to peak swing 1.0 V 1 Input signal minimum slew rate 1.0 V/ns 2, 3 Input reference voltage Notes Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions. VDDQ VIH(AC) min VIH(DC) min VSWING(MAX) VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = delta TR VREF - VIL(AC) max delta TF Rising Slew = VSS VIH(AC) min - VREF delta TR < AC Input Test Signal Waveform > Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD5B Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions Fast PDN Exit MRS(12) = 0mA mA Slow PDN Exit MRS(12) = 1mA mA Normal mA Low Power mA Notes mA Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Operating Current Table(1-1) (TA=0oC, VDD= 1.9V) M378T3253FG(Z)3 / M378T3253FG(Z)0 : 256MB(32Mx8 *8) Module IDD6 Symbol E6 (DDR2-667@CL=5) D5 (DDR2-533@CL=4) CC (DDR2-400@CL=3) Unit IDD0 840 800 760 mA IDD1 920 880 800 mA IDD2P 64 64 64 mA IDD2Q 240 200 200 mA IDD2N 280 240 240 mA IDD3P-F 280 240 240 mA IDD3P-S 120 120 120 mA IDD3N 600 560 520 mA IDD4W 1,680 1,400 1,080 mA IDD4R 1,480 1,280 1,040 mA IDD5B 1,360 1,320 1,280 mA 40 40 40 mA 2,120 2,040 2,040 mA Normal IDD7 Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M378T6453FG(Z)3 / M378T6453FG(Z)0 : 512MB(32Mx8 *16) Module IDD6 Symbol E6 (DDR2-667@CL=5) D5 (DDR2-533@CL=4) CC (DDR2-400@CL=3) Unit IDD0 1,440 1,360 1,280 mA IDD1 1,520 1,440 1,320 mA IDD2P 128 128 128 mA IDD2Q 480 400 400 mA IDD2N 560 480 480 mA IDD3P-F 560 480 480 mA IDD3P-S 240 240 240 mA IDD3N 1,200 1,120 1,040 mA IDD4W 2,280 1,960 1,600 mA IDD4R 2,080 1,840 1,560 mA IDD5B 1,960 1,880 1,800 mA 80 80 80 mA 2,720 2,600 2,560 mA Normal IDD7 Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Operating Current Table(1-2) (TA=0oC, VDD= 1.9V) M391T3253FG(Z)3 / M391T3253FG(Z)0 : 256MB(32Mx8 *9) ECC Module Symbol E6 (DDR2-667@CL=5) D5 (DDR2-533@CL=4) CC (DDR2-400@CL=3) Unit IDD0 945 900 855 mA IDD1 1,035 990 900 mA IDD2P 72 72 72 mA IDD2Q 270 225 225 mA mA IDD2N 315 270 270 IDD3P-F 315 270 270 mA IDD3P-S 135 135 135 mA IDD3N 675 630 585 mA IDD4W 1,890 1,575 1,215 mA IDD4R 1,665 1,440 1,170 mA IDD5B 1,530 1,485 1,440 mA IDD6 Normal IDD7 45 45 45 mA 2,385 2,295 2,295 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M391T6453FG(Z)3 / M391T6453FG(Z)0 : 512MB(32Mx8 *18) ECC Module IDD6 Symbol E6 (DDR2-667@CL=5) D5 (DDR2-533@CL=4) CC (DDR2-400@CL=3) Unit IDD0 1,620 1,530 1,440 mA IDD1 1,710 1,620 1,485 mA IDD2P 144 144 144 mA IDD2Q 540 450 450 mA IDD2N 630 540 540 mA IDD3P-F 630 540 540 mA IDD3P-S 270 270 270 mA IDD3N 1,350 1,260 1,170 mA IDD4W 2,565 2,205 1,800 mA IDD4R 2,340 2,070 1,755 mA IDD5B 2,205 2,115 2,025 mA 90 90 90 mA 3,060 2,925 2,880 mA Normal IDD7 Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC) Parameter Non-ECC Input capacitance, CK and CK Min Symbol Max M378T3253FG(Z)3 M378T3253FG(Z)0 Min Max M378T6453FG(Z)3 CCK0 - 24 - 26 CCK1 - 25 - 28 CCK2 - 25 - 28 Input capacitance, CKE and CS CI1 - 42 - 42 Input capacitance, Addr,RAS,CAS,WE CI2 - 42 - 42 Input/output capacitance, DQ, DM, DQS, DQS CIO - 6 - 10 ECC Symbol M391T3253FG(Z)3 M391T3253FG(Z)0 M391T6453FG(Z)3 M391T6453FG(Z)0 CCK0 - 25 - 28 CCK1 - 25 - 28 CCK2 - 25 - 28 Input capacitance, CKE and CS CI1 - 44 - 44 Input capacitance, Addr,RAS,CAS,WE CI2 - 44 - 44 Input/output capacitance, DQ, DM, DQS, DQS CIO - 6 - 10 Input capacitance, CK and CK Units M378T6453FG(Z)0 pF Units pF * DM is internally loaded to match DQ and DQS identically. Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Electrical Characteristics & AC Timing for DDR2-667/533/400 SDRAM (0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V) Refresh Parameters by Device Density Parameter Symbol Refresh to active/Refresh command time tRFC Average periodic refresh interval tREFI 256Mb 512Mb 1Gb 2Gb 4Gb Units 75 105 127.5 195 tbd ns 0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 7.8 µs 85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 3.9 µs Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Speed DDR2-667(E6) DDR2-533(D5) DDR2-400(CC) 5 - 5- 5 4-4-4 3-3-3 Bin (CL - tRCD - tRP) Units Parameter min max min max min max tCK, CL=3 5 8 5 8 5 8 ns tCK, CL=4 3.75 8 3.75 8 5 8 ns tCK, CL=5 3 8 - - - - ns tRCD 15 15 15 ns tRP 15 15 15 ns tRC 54 tRAS 39 55 55 40 70000 ns 40 70000 ns 70000 Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter Symbol DDR2-667 DDR2-533 DDR2-400 min max min max min max Units Notes DQ output access time from CK/CK tAC -450 +450 -500 +500 -600 +600 DQS output access time from CK/CK tDQSCK -400 +400 -450 +450 -500 +500 ps ps CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) x min(tCL, tCH) x min(tCL, tCH) x ps Clock cycle time, CL=x tCK 3000 8000 3750 8000 5000 8000 ps 24 DQ and DM input hold time tDH 175 x 225 x 275 x ps 15,16,17 DQ and DM input setup time tDS 50 x 100 x 150 x ps 15,16,17 Control & Address input pulse width for each input tIPW 0.6 x 0.6 x 0.6 x tCK DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x 0.35 x tCK Data-out high-impedance time from CK/CK tHZ DQS low-impedance time from CK/CK tLZ(DQS) DQ low-impedance time from CK/CK 20,21 x tAC max x tAC max x tAC max ps tAC min tAC max tAC min tAC max tAC min tAC max ps 27 tLZ(DQ) 2*tAC min tAC max 2* tACmin tAC max 2* tACmin tAC max ps 27 DQS-DQ skew for DQS and associated DQ signals tDQSQ x 250 x 300 x 350 ps 22 DQ hold skew factor tQHS x 350 x 400 x 450 ps 21 DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x tHP - tQHS x ps Write command to first DQS latching transition tDQSS WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK DQS input high pulse width tDQSH 0.35 x 0.35 x 0.35 x tCK Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs Parameter Symbol DDR2 SDRAM DDR2-667 DDR2-533 DDR2-400 min max min max min max Units Notes DQS input low pulse width tDQSL 0.35 x 0.35 x 0.35 x tCK DQS falling edge to CK setup time tDSS 0.2 x 0.2 x 0.2 x tCK DQS falling edge hold time from CK tDSH 0.2 x 0.2 x 0.2 x tCK Mode register set command cycle time tMRD 2 x 2 x 2 x tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 x 0.35 x 0.35 x tCK Address and control input hold time tIH 275 x 375 x 475 x ps 14,16,18 Address and control input setup time tIS 200 x 250 x 350 x ps 14,16,18 Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 28 Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 28 Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x 7.5 x ns 12 Active to active command period for 2KB page size products tRRD 10 x 10 x 10 x ns 12 19 Four Activate Window for 1KB page size products tFAW 37.5 37.5 37.5 Four Activate Window for 2KB page size products tFAW 50 50 50 ns CAS to CAS command delay tCCD 2 2 2 tCK Write recovery time tWR 15 x 15 x 15 x ns Auto precharge write recovery + precharge time tDAL tWR+tRP x tWR+tRP x tWR+tRP x tCK Internal write to read command delay tWTR 7.5 x 7.5 x 10 x ns Internal read to precharge command delay tRTP 7.5 7.5 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 Exit precharge power down to any non-read command tXP 2 x 2 x 2 x tCK Exit active power down to read command tXARD 2 x 2 x 2 x tCK 9 Exit active power down to read command (Slow exit, Lower power) tXARDS 9, 10 CKE minimum pulse width (high and low pulse width) ODT turn-on delay 200 ns 200 6 - AL 6 - AL tCK tCKE 3 3 3 tCK tAOND 2 2 tAC(max)+ 0.7 2 tAC(min) tAC(max)+ 1 2 2 tCK tAC(min) tAC(max)+ 1 ns 2tCK+tAC (max)+1 ns 2.5 tAC(min) ODT turn-on tAON tAC(min) ODT turn-on(Power-Down mode) tAONPD tAC(min)+ 2tCK+tAC( tAC(min)+ 2tCK+tAC( tAC(min)+ 2 max)+1 2 max)+1 2 ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 2.5 tCK tAC(min) tAC(max)+ 0.6 tAC(max)+ 0.6 ns 2.5tCK+ 2.5tCK+ tAC(min)+ tAC(min)+ tAC(max)+ tAC(max)+ 2 2 1 1 ns ODT turn-off tAOF tAC(min) tAC(max)+ 0.6 ODT turn-off (Power-Down mode) tAOFPD tAC(min)+ 2 2.5tCK+tA C(max)+1 ODT to power down entry latency tANPD 3 3 3 ODT power down exit latency tAXPD 8 8 8 OCD drive mode output delay tOIT 0 Minimum time clocks remains ON after CKE asynchronously tDelay drops LOW tIS+tCK +tIH 12 0 tIS+tCK +tIH 12 0 tIS+tCK +tIH 11 tCK 6 - AL 2 23 13, 25 26 tCK tCK 12 ns ns 24 Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Physical Dimensions: 32Mbx8 based 32Mx64/x72 Module(1 Rank) M378T3253FG(Z)3 / M391T3253FG(Z)3 M378T3253FG(Z)0 / M391T3253FG(Z)0 Units : Millimeters 133.35 (2X)4.00 131.35 128.95 N/A 10.00 (for x64) ECC SPD 30.00 (2) 2.50 17.80 2.30 (for x72) B A 63.00 2.7 55.00 1.270 ± 0.10 4.00 4.00 3.00 2.50±0.20 5.00 0.80±0.05 3.80 2.50 1.50±0.10 Detail A 0.20 1.00 4.00 Detail B The used device is 32M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T56083QF Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Physical Dimensions: 32Mbx8 based 64Mx64/x72 Module(2 Ranks) M378T6453FG(Z)3 / M391T6453FG(Z)3 M378T6453FG(Z)0 / M391T6453FG(Z)0 Units : Millimeters 133.35 (2X)4.00 131.35 128.95 10.00 N/A (for x64) SPD 30.00 ECC (2) 2.50 A 17.80 2.30 (for x72) B 63.00 4.00 55.00 N/A (for x64) ECC (for x72) 1.270 ± 0.10 4.00 4.00 3.00 2.50±0.20 5.00 0.80±0.05 3.80 2.50 1.50±0.10 Detail A 0.20 1.00 4.00 Detail B The used device is 32M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T56083QF Rev. 1.3 Aug. 2005 256MB, 512MB Unbuffered DIMMs DDR2 SDRAM Revision History Revision 1.0 (Jan. 2004) - Initial Release Revision 1.1 (Jun. 2004) - Added lead-free part number in the ordering information - Changed IDD2P Revision 1.2 (Jan. 2005) - Revised tIH value of 667 speed Revision 1.3 (Aug. 2005) - Added Dummy Pad PCB product part number in ordering information Rev. 1.3 Aug. 2005