AMD M41000007F 32 megabit (2 m x 16-bit) cmos 1.8 volt-only, simultaneous operation, page mode flash memory and 8 mbit (1 m x 8-bit/512 k x 16-bit) static ram Datasheet

Am41PDS3228D
Data Sheet
-XO\
7KHIROORZLQJGRFXPHQWVSHFLILHV6SDQVLRQPHPRU\SURGXFWVWKDWDUHQRZRIIHUHGE\ERWK$GYDQFHG
0LFUR'HYLFHVDQG)XMLWVX$OWKRXJKWKHGRFXPHQWLVPDUNHGZLWKWKHQDPHRIWKHFRPSDQ\WKDWRULJ
LQDOO\ GHYHORSHG WKHVSHFLILFDWLRQ WKHVH SURGXFWV ZLOO EHRIIHUHG WR FXVWRPHUVRIERWK $0' DQG
)XMLWVX
Continuity of Specifications
7KHUHLVQRFKDQJHWRWKLVGDWDVKHHWDVDUHVXOWRIRIIHULQJWKHGHYLFHDVD6SDQVLRQSURGXFW$Q\
FKDQJHVWKDWKDYHEHHQPDGHDUHWKHUHVXOWRIQRUPDOGDWDVKHHWLPSURYHPHQWDQGDUHQRWHGLQWKH
GRFXPHQWUHYLVLRQVXPPDU\ZKHUHVXSSRUWHG)XWXUHURXWLQHUHYLVLRQVZLOORFFXUZKHQDSSURSULDWH
DQGFKDQJHVZLOOEHQRWHGLQDUHYLVLRQVXPPDU\
Continuity of Ordering Part Numbers
$0'DQG)XMLWVXFRQWLQXHWRVXSSRUWH[LVWLQJSDUWQXPEHUVEHJLQQLQJZLWK³$P´DQG³0%0´7RRUGHU
WKHVHSURGXFWVSOHDVHXVHRQO\WKH2UGHULQJ3DUW1XPEHUVOLVWHGLQWKLVGRFXPHQW
For More Information
3OHDVH FRQWDFW \RXU ORFDO $0' RU )XMLWVX VDOHV RIILFH IRU DGGLWLRQDO LQIRUPDWLRQ DERXW 6SDQVLRQ
PHPRU\VROXWLRQV
Publication Number 26014 Revision A
Amendment +1 Issue Date May 13, 2003
PRELIMINARY
Am41PDS3228D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
—
—
—
—
■ Power supply voltage of 1.8 to 2.2 volt
■ High performance
— Access time as fast as 100 ns flash, 70 ns SRAM
■ Package
24 mA active read current at 10 MHz for initial page read
0.5 mA active read current at 10 MHz for intra-page read
1 mA active read current at 20 MHz for intra-page read
200 nA in standby or automatic sleep mode
■ Minimum 1 million write cycles guaranteed per sector
■ 20 year data retention at 125°C
— 73-Ball FBGA
— Reliable operation for the life of the system
■ Operating Temperature
SOFTWARE FEATURES
— –40°C to +85°C
Flash Memory Features
■ Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
ARCHITECTURAL ADVANTAGES
■ Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
— Zero latency between read and write operations
■ Erase Suspend/Erase Resume
■ Data# Polling and Toggle Bits
■ Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■ Page Mode Operation
— 4 word page allows fast asynchronous reads
HARDWARE FEATURES
■ Dual Bank architecture
— One 4 Mbit bank and one 28 Mbit bank
■ SecSi (Secured Silicon) Sector: Extra 64 KByte sector
— Factory locked and identifiable: 16 byte Electronic Serial
Number available for factory secure, random ID; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
— Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
■ Any combination of sectors can be erased
■ Ready/Busy# output (RY/BY#)
■ Hardware reset pin (RESET#)
■ WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
■ Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
■ Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■ Top or bottom boot block
■ Manufactured on 0.23 µm process technology
■ Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
■ High performance
— Random access time of 100 ns at 1.8 V to 2.2 V VCC
■ Ultra low power consumption (typical values)
SRAM Features
■ Power dissipation
— Operating: 2 mA typical
— Standby: 0.5 µA typical
■
■
■
■
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.0 to 2.2 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
— 2.5 mA active read current at 1 MHz for initial page read
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 26104 Rev: A Amendment/+1
Issue Date: May 13, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash
memory organized as 2,097,152 words of 16 bits
each. The device is designed to be programmed in
system with standard system 1.8 V VCC supply. This
d evice ca n a lso be re prog ra mm ed in stand ard
EPROM programmers.
The Am29PDS322D offers fast page access time of
40 ns with random access time of 100 ns (at 1.8 V to
2.2 V VCC), allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls. The
page size is 4 words.
The device requires only a single 1.8 volt power supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The device is divided as shown in the following table:
Bank 1 Sectors
Quantity
Size
8
4 Kwords
7
32 Kwords
Bank 2 Sectors
Quantity
Size
56
32 Kwords
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is a n a d v a n t a g e c o m p a re d to sy st e m s w h e re
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software
does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
Am29PDS322D Features
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The SecSi (Secured Silicon) Sector is an extra 64
KByte sector capable of being permanently locked by
AMD or customers. The SecSi Indicator Bit (DQ7) is
permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a
factory locked part.
Hardware data protection measures include a low
V CC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
Th e system can also place the de vice into the
standby mode. Power consumption is greatly reduced in both modes.
4 Mbits total
2
28 Mbits total
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations. . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = VCC 10
Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = VSS 11
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Requirements for Reading Array Data ................................... 12
Read Mode ............................................................................. 12
Random Read (Non-Page Mode Read) .............................. 12
Page Mode Read .................................................................... 12
Table 3. Page Word Mode ..............................................................12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 13
Simultaneous Read/Write Operations with Zero Latency ....... 13
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 14
Table 4. Am29PDS322DT Top Boot Sector Addresses ..................14
Table 5. Am29PDS322DT Top Boot SecSi Sector Address ...........15
Table 6. Am29PDS322DB Bottom Boot Sector Addresses ............15
Am29PDS322DB Bottom Boot SecSi Sector Address.................... 17
Autoselect Mode ..................................................................... 17
Sector/Sector Block Protection and Unprotection .................. 17
Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................................17
Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection .............................................................................18
Write Protect (WP#) ................................................................ 18
Temporary Sector/Sector Block Unprotect ............................. 18
Figure 1. Temporary Sector Unprotect Operation........................... 19
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms .............................................................................................. 20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Factory Locked: SecSi Sector Programmed and Protected
at the Factory ...................................................................... 21
Hardware Data Protection ...................................................... 21
Low VCC Write Inhibit ........................................................... 21
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Flash Command Definitions . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 22
Autoselect Command Sequence ............................................ 22
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23
Word Program Command Sequence ..................................... 23
Unlock Bypass Command Sequence .................................. 23
Figure 3. Unlock Bypass Algorithm ................................................. 24
Figure 4. Program Operation .......................................................... 24
May 13, 2002
Chip Erase Command Sequence ........................................... 24
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ........................... 25
Figure 5. Erase Operation.............................................................. 26
Table 10. Am29PDS322D Command Definitions ........................... 27
Flash Write Operation Status . . . . . . . . . . . . . . . 28
DQ7: Data# Polling ................................................................. 28
Figure 6. Data# Polling Algorithm .................................................. 28
RY/BY#: Ready/Busy# ............................................................ 29
DQ6: Toggle Bit I .................................................................... 29
Figure 7. Toggle Bit Algorithm........................................................ 29
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer ....................................................... 30
Table 11. Write Operation Status ................................................... 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32
Industrial (I) Devices ............................................................ 32
VCCf/VCC s Supply Voltage ................................................... 32
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33
CMOS Compatible .................................................................. 33
SRAM DC and Operating Characteristics . . . . . 34
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 35
Figure 11. Typical ICC1 vs. Frequency ............................................ 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup.................................................................... 36
Table 12. Test Specifications ......................................................... 36
Key To Switching Waveforms . . . . . . . . . . . . . . . 36
Figure 13. Input Waveforms and Measurement Levels ................. 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM CE#s Timing ................................................................ 37
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash ................................................................ 37
Figure 15. Conventional Read Operation Timings ......................... 38
Figure 16. Page Mode Read Timings ............................................ 39
Hardware Reset (RESET#) .................................................... 40
Figure 17. Reset Timings ............................................................... 40
Flash Erase and Program Operations .................................... 41
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
Figure 22. Data# Polling Timings (During Embedded Algorithms).
Figure 23. Toggle Bit Timings (During Embedded Algorithms)......
Figure 24. DQ2 vs. DQ6.................................................................
42
42
43
44
44
45
45
Temporary Sector/Sector Block Unprotect ............................. 46
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram.............................................................................. 46
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram.............................................................................. 47
Alternate CE#f Controlled Erase and Program Operations .... 48
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings............................................................................... 49
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 50
Read Cycle ............................................................................. 50
Figure 28. SRAM Read Cycle—Address Controlled...................... 50
Figure 29. SRAM Read Cycle ........................................................ 51
Am41PDS3228D
3
P R E L I M I N A R Y
Write Cycle ............................................................................. 52
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. SRAM Write Cycle—WE# Control ................................. 52
Figure 31. SRAM Write Cycle—CE1#s Control .............................. 53
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ................ 54
Figure 33. CE1#s Controlled Data Retention Mode....................... 56
Figure 34. CE2s Controlled Data Retention Mode......................... 56
Flash Erase And Programming Performance . . 55
Flash Latchup Characteristics . . . . . . . . . . . . . . 55
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55
4
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (February 21, 2002) .............................................. 58
Revision A+1 (May 13, 2002) ................................................. 58
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Am41PDS3228D
Flash Memory
Standard Voltage Range: VCC
= 1.8–2.2 V
Speed Options
SRAM
10
11
10, 11
Max Access Time (ns)
100
110
70
CE# Access (ns)
100
110
70
OE# Access (ns)
35
40
35
Max Page Address Access Time (ns)
40
45
N/A
MCP BLOCK DIAGRAM
VCCf
A20 to A0
VSS
RY/BY#
A20 to A0
WP#/ACC
RESET#
CE#f
32 M Bit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs/VCCQ
VSS/VSSQ
A0
toto
A19
A18
A0
SA
LB#s
UB#s
WE#
OE#
CE1#s
CE2s
CIOs
May 13, 2002
8 M Bit
Static RAM
DQ15 to DQ0
Am41PDS3228D
5
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
RY/BY#
X-Decoder
A20–A0
WE#
CE#
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
Control
DQ15–DQ0
Lower Bank Address
Lower Bank
Latches and
Control Logic
A20–A0
Y-Decoder
A20–A0
X-Decoder
DQ15–DQ0
RESET#
Upper Bank
DQ15–DQ0
A20–A0
Y-Decoder
Upper Bank Address
A20–A0
Latches and Control Logic
OE#
VCC
VSS
OE#
6
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
CONNECTION DIAGRAM
73-Ball FBGA
Top View
A1
A10
NC
NC
B1
B5
B6
B10
NC
NC
NC
NC
C5
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
D3
D4
D7
D8
D9
A3
A6
UB#
A19
A12
A15
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RY/BY#
A20
A9
A13
NC
F1
F2
F3
F4
F7
F8
F9
F10
NC
A1
A4
A17
A10
A14
NC
NC
G1
G2
G3
G4
G7
G8
G9
G10
NC
A0
VSS
DQ1
DQ6
SA
A16
NC
H2
H3
H4
H5
H6
H7
H8
H9
CE#f
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
NC
J2
J3
J4
J5
J6
J7
J8
J9
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ8
DQ2
DQ11
CIOs
DQ5
DQ14
L1
L5
L6
L10
NC
NC
NC
NC
CE1#s
D6
RESET# CE2s
M1
M10
NC
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP,
May 13, 2002
SRAM only
Shared
C1
D5
Flash only
SSOP). The package and/or data integrity may be
compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Am41PDS3228D
7
P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A18–A0
= 19 Address Inputs (Common)
A20–A19
= 2 Address Inputs (Flash)
SA
= Highest Order Address Pin (SRAM)
Byte mode
A20–A19
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
SA
CE#f
= Chip Enable (Flash)
CE1#s
= Chip Enable 1 (SRAM)
CE2s
= Chip Enable 2 (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output (Flash)
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
CIOs
= I/O Configuration (SRAM)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
19
A18–A0
CE#f
DQ15–DQ0
CE1#s
CE2s
OE#
RY/BY#
WE#
WP#/ACC
RESET#
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
VCCf
= Flash 1.8 volt-only single power
supply (see Product Selector Guide
for speed options and voltage supply tolerances)
VCCs
= SRAM Power Supply
VSS
= Device Ground (Common)
NC
= Pin Not Connected Internally
8
16 or 8
Am41PDS3228D
UB#s
LB#s
CIOs
May 13, 2002
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am41PDS322
8
D
T
10
I
T
TAPE AND REEL
T
=
7 inches
S
=
13 inches
TEMPERATURE RANGE
I
=
Industrial (–40°C to +85°C)
SPEED OPTION
See “Product Selector Guide” on page 5
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
PROCESS TECHNOLOGY
D
=
0.23 µm
SRAM DEVICE DENSITY
8
=
8 Mbits
AMD DEVICE NUMBER/DESCRIPTION
Am41PDS3228D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
Valid Combinations
Valid Combinations
Order Number
Package Marking
Am41PDS3228DT10I
Am41PDS3228DB10I
M41000007F
M41000007G
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly released combinations
T, S
Am41PDS3228DT11I
Am41PDS3228DB11I
May 13, 2002
M41000007H
M41000007I
Am41PDS3228D
9
P R E L I M I N A R Y
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory locat io n. Th e re g ist e r is a la t ch u se d t o st or e t h e
commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The state machine outputs dictate the function
of the device. Tables 1–2 list the device bus operations, the inputs and control levels they require, and
the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = VCC
Operation
CE1#s
CE2s
H
X
X
L
H
X
X
L
VCC ±
0.3 V
H
X
X
L
Output Disable
L
L
H
Flash Hardware
Reset
X
H
X
X
L
H
X
Sector Protect
(Note 5)
L
(Notes 1, 2)
CE#f
Read from Flash
L
Write to Flash
L
Standby
Sector Unprotect
(Note 5)
L
Temporary Sector
Unprotect
X
Read from SRAM
H
Write to SRAM
H
X
L
H
X
X
L
H
X
X
L
L
H
L
H
OE# WE#
SA
Addr.
LB#s
UB#s
(Note 3)
(Note 3)
RESET#
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
L
H
X
AIN
X
X
H
L/H
DOUT
DOUT
H
L
X
AIN
X
X
H
(Note 4)
DIN
DIN
X
X
X
X
X
X
VCC ±
0.3 V
H
High-Z
High-Z
H
H
X
X
L
X
H
H
X
X
X
L
H
L/H
High-Z
High-Z
X
X
X
X
X
X
L
L/H
High-Z
High-Z
H
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
VID
L/H
DIN
X
X
X
VID
(Note 6)
DIN
X
X
VID
(Note 6)
DIN
High-Z
DOUT
DOUT
H
X
High-Z
DOUT
H
L
X
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
X
X
X
L
L
L
H
X
AIN
H
L
L
H
DOUT
High-Z
L
L
DIN
DIN
X
L
X
AIN
H
L
L
H
H
L/H
High-Z
DIN
DIN
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH , VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH , the two outermost boot sector protection depends
on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If
WP#/ACC = VHH, all sectors will be unprotected.
10
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
Table 2.
Operation
(Notes 1, 2)
CE#f
Read from Flash
L
Write to Flash
L
Standby
Output Disable
Flash Hardware
Reset
VCC ±
0.3 V
L
X
Sector Protect (Note
5)
L
Sector Unprotect
(Note 5)
L
Temporary Sector
Unprotect
X
Read from SRAM
Write to SRAM
Device Bus Operations—SRAM Byte Mode, CIOs = VSS
CE1#s
CE2s
H
X
X
L
H
X
X
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
OE# WE#
SA
Addr.
LB#s
UB#s
RESET#
(Note 3) (Note 3)
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
L
H
X
AIN
X
X
H
L/H
DOUT
DOUT
H
L
X
AIN
X
X
H
(Note 3)
DIN
DIN
X
X
X
X
X
X
VCC ±
0.3 V
H
High-Z
High-Z
H
H
SA
X
DNU
DNU
H
L/H
High-Z
High-Z
X
X
X
X
X
X
L
L/H
High-Z
High-Z
X
X
VID
L/H
DIN
X
H
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
H
L
X
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
VID
(Note 6)
DIN
X
X
X
X
AIN
X
X
VID
(Note 6)
DIN
High-Z
X
L
H
X
X
L
H
L
H
L
H
SA
AIN
X
X
H
X
DOUT
High-Z
H
L
H
X
L
SA
AIN
X
X
H
X
DIN
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH , VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = VIL or VIH, SA = SRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH , the two outermost boot sector protection depends on
whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC =
VHH, all sectors will be unprotected.
May 13, 2002
Am41PDS3228D
11
P R E L I M I N A R Y
FLASH DEVICE BUS OPERATIONS
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” for more
information. Refer to the AC Read-Only Operations
table for timing specifications and to Figure 15 for the
timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
Read Mode
Random Read (Non-Page Mode Read)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selection. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
Page Mode Read
The device is capable of fast Page mode read and is
compatible with the Page mode Mask ROM read operation. This mode provides faster read access speed
for random locations within a page. The Page size of
the device is 4 words. The appropriate Page is selected by the higher address bits A20–A0 and the LSB
bits A1–A0 determine the specific word within that
page. This is an asynchronous operation with the microprocessor supplying the specific word location.
The random or initial page access is equal to tACC or
tCE and subsequent Page read accesses (as long as
the locations specified by the microprocessor fall
12
within that Page) are equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Here again, CE# selects
the device and OE# is the output control and should be
used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by
keeping A20–A2 constant and changing A1–A0 to select the specific word within that page. See Figure 16
for timing specifications.
The following table determines the specific word within
the selected page:
Table 3. Page Word Mode
Word
A1
A0
Word 0
0
0
Word 1
0
1
Word 2
1
0
Word 3
1
1
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 3 indicates the address
space that each sector occupies.
ICC2f in the DC Characteristics table represents the active current specification for the write mode. The Measurements performed by placing a 50Ω termination on
the data pin with a bias of VCC/2. The time from OE#
high to the data bus driven to VCC/2 is taken as tDFAC
Characteristics. section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal operation.
this mode when addresses remain stable for t ACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Autoselect Functions
Automatic sleep mode current is drawn when CE# =
V SS ± 0.3 V and all inputs are held at VCC ± 0.3 V. If
CE# and RESET# voltages are not held within these
tolerances, the automatic sleep mode current will be
greater.
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autosel ect Comm and S equence sec tions fo r m ore
information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
with in the same bank (e xce pt the sector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the Flash DC Characteristics
t a b le re p r e se n t t h e cu r re n t s p e cif ic a t io n s fo r
read-while-program and read-while-erase,
respectively.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
V IH .) If CE#f and RESET# are held at V IH , but not
within V CC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The device requires standard access time (t CE ) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC5f in the Flash DC Characteristics table represents
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V SS ± 0.3 V, the device draws CMOS standby current (ICC3 f). If RESET#
is held at V IL but not within VSS ± 0.3 V, the standby
current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus mon itor RY/BY# to de term ine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded
Algorithms). The system can read data t RH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 17 for the timing diagram.
ICC3 in the Flash DC Characteristics table represents
the standby current specification.
Output Disable Mode
Automatic Sleep Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
May 13, 2002
Am41PDS3228D
13
P R E L I M I N A R Y
Table 4.
Bank 2
Bank
14
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
Am29PDS322DT Top Boot Sector Addresses
Sector Address
A20–A12
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
Sector Size
(Kwords)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Am41PDS3228D
(x16)
Address Range
000000h–07FFFh
008000h–0FFFFh
010000h–17FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
May 13, 2002
P R E L I M I N A R Y
Table 4.
Bank 1
Bank 2
Bank
Sector
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Am29PDS322DT Top Boot Sector Addresses (Continued)
Sector Address
A20–A12
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
Table 5.
Bank 1
Bank
May 13, 2002
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
(x16)
Address Range
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
Am29PDS322DT Top Boot SecSi Sector Address
Sector Address A20–A12
111111xxx
Table 6.
Sector Size
(Kwords)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
Sector Size
32
(x16) Address Range
1F8000h–1FFFFh
Am29PDS322DB Bottom Boot Sector Addresses
Sector Address
A20–A12
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
Sector Size
(Kwords)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
Am41PDS3228D
(x16)
Address Range
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
15
P R E L I M I N A R Y
Table 6.
Bank 2
Bank
16
Sector
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
Am29PDS322DB Bottom Boot Sector Addresses (Continued)
Sector Address
A20–A12
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
111000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
Sector Size
(Kwords)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Am41PDS3228D
(x16)
Address Range
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
May 13, 2002
P R E L I M I N A R Y
Table 6.
Bank 2
Bank
Sector
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Am29PDS322DB Bottom Boot Sector Addresses (Continued)
Sector Address
A20–A12
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
Sector Size
(Kwords)
32
32
32
32
32
32
32
32
(x16)
Address Range
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Table 7. Am29PDS322DB Bottom Boot SecSi Sector Address
Sector Address
A20–A12
000000xxx
Sector Size
32
Autoselect Mode
Table 8.
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This
mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming
algorithm.
The autoselect codes can also be accessed in-system
through the command register. The host system can
issue the autoselect command via the command register, as shown in Table 10. This method does not
require V ID . Refer to the Autoselect Command Sequence section for more information.
Sector/Sector Block Protection and
Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
8 and 9).
May 13, 2002
Sector
Group
(x16)
Address Range
00000h-07FFFh
Top Boot Sector/Sector Block Addresses
for Protection/Unprotection
Sectors
A20–A12
Sector/
Sector Block Size
SGA0
SA0
000000XXX
64 (1x64) Kbytes
SGA1
SA1–SA3
00001XXXX
192 (3x64) Kbytes
SGA2
SA4–SA7
0001XXXXX
256 (4x64) Kbytes
SGA3
SA8–SA11
0010XXXXX
256 (4x64) Kbytes
SGA4
SA12–SA15
0011XXXXX
256 (4x64) Kbytes
SGA5
SA16–SA19
0100XXXXX
256 (4x64) Kbytes
SGA6
SA20–SA23
0101XXXXX
256 (4x64) Kbytes
SGA7
SA24–SA27
0110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
SGA8
SA28–SA31
0111XXXXX
SGA9
SA32–SA35
1000XXXXX
256 (4x64) Kbytes
SGA10
SA36–SA39
1001XXXXX
256 (4x64) Kbytes
SGA11
SA40–SA43
1010XXXXX
256 (4x64) Kbytes
SGA12
SA44–SA47
1011XXXXX
256 (4x64) Kbytes
SGA13
SA48–SA51
1100XXXXX
256 (4x64) Kbytes
SGA14
SA52–SA55
1101XXXXX
256 (4x64) Kbytes
SGA15
SA56–SA59
1110XXXXX
256 (4x64) Kbytes
SGA16
SA60–SA62
111100XXX
192 (3x64) Kbytes
SGA17
SA63
111111000
8 Kbytes
SGA18
SA64
111111001
8 Kbytes
SGA19
SA65
111111010
8 Kbytes
SGA20
SA66
111111011
8 Kbytes
SGA21
SA67
111111100
8 Kbytes
SGA22
SA68
111111101
8 Kbytes
SGA23
SA69
111111110
8 Kbytes
SGA24
SA70
111111111
8 Kbytes
Am41PDS3228D
17
P R E L I M I N A R Y
Table 9. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
Sector
Group
Sectors
A20–A12
Sector/Sector
Block Size
SGA0
SA70
111111XXX
64 (1x64) Kbytes
SGA1
SA69–SA67
11110XXXX
192 (3x64) Kbytes
SGA2
SA66–SA63
1110XXXXX
256 (4x64) Kbytes
SGA3
SA62–SA59
1101XXXXX
256 (4x64) Kbytes
SGA4
SA58–SA55
1100XXXXX
256 (4x64) Kbytes
SGA5
SA54–SA51
1011XXXXX
256 (4x64) Kbytes
SGA6
SA50–SA47
1010XXXXX
256 (4x64) Kbytes
SGA7
SA46–SA43
1001XXXXX
256 (4x64) Kbytes
SGA8
SA42–SA39
1000XXXXX
256 (4x64) Kbytes
SGA9
SA38–SA35
0111XXXXX
256 (4x64) Kbytes
SGA10
SA34–SA31
0110XXXXX
256 (4x64) Kbytes
SGA11
SA30–SA27
0101XXXXX
256 (4x64) Kbytes
SGA12
SA26–SA23
0100XXXXX
256 (4x64) Kbytes
SGA13
SA22–SA19
0011XXXXX
256 (4x64) Kbytes
SGA14
SA18–SA15
0010XXXXX
256 (4x64) Kbytes
SGA15
SA14–SA11
0001XXXXX
256 (4x64) Kbytes
SGA16
SA10–SA8
000011XXX
192 (3x64) Kbytes
SGA17
SA7
000000111
8 Kbytes
SGA18
SA6
000000110
8 Kbytes
SGA19
SA5
000000101
8 Kbytes
SGA20
SA4
000000100
8 Kbytes
SGA21
SA3
000000011
8 Kbytes
SGA22
SA2
000000010
8 Kbytes
SGA23
SA1
000000001
8 Kbytes
SGA24
SA0
000000000
8 Kbytes
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection and unprotection requires VID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
18
It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode
section for details.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using V ID. This function is one of two provided by the
WP#/ACC pin.
If the system asserts V IL on the WP#/ACC pin, the device disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block
Protection and Unprotection”. The two outermost 8
Kbyte boot sectors are the two sectors containing the
lowest addresses in a top-boot-configured device, or
the two sectors containing the highest addresses in a
top-boot-configured device.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these two
sectors depends on whether they were last protected
or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”.
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
8).
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to V ID (9 V – 11 V). During this mode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 shows the timing diagrams,
for this feature.
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once
again.
Figure 1.
Temporary Sector Unprotect Operation
May 13, 2002
Am41PDS3228D
19
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
Temporary Sector
Unprotect Mode
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Reset
PLSCNT = 1
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
Yes
No
Yes
Protect another
sector?
Device failed
PLSCNT
= 1000?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2.
20
In-System Sector/Sector Block Protect and Unprotect Algorithms
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 64 KBytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either
f a cto ry lo cked o r cu sto m e r lo cka b le. Th e f a ctory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize that
sector in any manner they choose. The customer-lockable version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0).
This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to the boot sectors instead of the
SecSi sector
Factory Locked: SecSi Sector Programmed and
Protected at the Factory
In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with one of the
following:
■ A random, secure ESN only
■ Customer code through the ExpressFlash service
■ Both a random, secure ESN and customer code
through the ExpressFlash service.
In devices that have an ESN, a Bottom Boot device
will have the 16-byte ESN in the lowest addressable
memory area at addresses 000000h–000007h. In the
Top Boot device the starting address of the ESN will
be at the bottom of the lowest 8 Kbyte boot sector at
addresses 1F8000h–1F8007h.
May 13, 2002
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s
factory with the permanently locked. Contact an AMD
representative for details on using AMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the Factory
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space,
expanding the size of the available Flash array by 64
Kbytes. The SecSi Sector can be read, programmed,
and erased as often as required. The SecSi Sector area
can be protected using one of the following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sector/Sector Block Protection and Unprotection” section.
Once the SecSi Sector is locked and verified, the syste m m u st w rit e t h e E xit S e cSi S e c to r R e g io n
command sequence to return to reading and writing
the remainder of the array.
The SecSi Sector protection must be used with caution since, once protected, there is no procedure
available for unprotecting the SecSi Sector area and
none of the bits in the SecSi Sector memory space
can be modified in any way.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for command definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V CC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When V CC is less than VLKO, the device does not accept any write cycles. This protects data during V CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO.
Am41PDS3228D
21
P R E L I M I N A R Y
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
is greater than VLKO.
CE#f and WE# must be a logical zero while OE# is a
logical one.
Write Pulse “Glitch” Protection
If WE# = CE#f = V IL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Noise pulses of less than 5 ns (typical) on OE#, CE#f
or WE# do not initiate a write cycle.
Power-Up Write Inhibit
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle,
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
MCP Device Bus Operations section for more information. The Read-Only Operations table provides the
read parameters, and Figure 15 shows the timing diagram.
22
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the device entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10 shows the address and data requirements.
The autoselect command sequence may be written to
an address that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing.
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode,
and the system may read any number of autoselect
codes without reinitiating the command sequence.
Table 10 shows the address and data requirements for
the command sequence. To determine sector protection information, the system must write to the appropriate sector group address (SGA). Tables 4 and 6 show
the address range associated with each sector.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the device to normal operation. Table 10 shows the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that a hardware reset (RESET#=V IL ) will reset the device to
reading array data.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and addresses are no longer latched. The system can deter-
May 13, 2002
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status
bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program comma nd se quence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting in faster
total programming time. Table 10 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to reading array data. See Figure
3 for the unlock bypass algorithm.
Am41PDS3228D
23
P R E L I M I N A R Y
Figure 4 illustrates the algorithm for the program operation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for
parameters, and Figure 18 for timing diagrams.
Start
555h/AAh
Set
Unlock
Bypass
Mode
2AAh/55h
START
555h/20h
Write Program
Command Sequence
XXXh/A0h
Program Address/Program Data
Embedded
Program
algorithm
in progress
Data# Polling Device
Verify Byte?
No
Yes
Increment
Address
No
Data Poll
from System
Verify Data?
In
Unlock
Bypass
Program
Last Address
?
No
Yes
Increment Address
No
Last Address?
Yes
Yes
Programming Completed
Programming
Completed
(BA) XXXh/90h
XXXh/00h
Figure 3.
Reset
Unlock
Bypass
Mode
Unlock Bypass Algorithm
Figure 4. Program Operation
Chip Erase Command Sequence
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
24
Note: See Table 10 for program command sequence.
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Flash Write Operation Status
section for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase operation. Refer to the Flash Erase and Program Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase
ad dress and comma nd following the excee ded
time-out may or may not be accepted. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
S ec t or E r a s e or E r a s e S u s pe n d du r i ng th e
time-out period resets the device to the read
mode. The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
May 13, 2002
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.
Refer to the Flash Write Operation Status section for
information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase operation. Refer to the Flash Erase and Program Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Note that unlock bypass programming is not allowed when the
device is erase-suspended.
Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
de t e rm in e if a se ct o r is a ct ive ly e ra si ng o r is
Am41PDS3228D
25
P R E L I M I N A R Y
erase-suspended. Refer to the Flash Write Operation
Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Flash Write Operation Status section for
more information.
START
Write Erase
Command Sequence
(Notes 1, 2)
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
Data Poll to Erasing
Bank from System
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 5. Erase Operation
26
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
Table 10.
Cycles
Bus Cycles (Notes 2–5)
Addr
Read (Note 6)
1
RA
Reset (Note 7)
Autoselect (Note 8)
Command
Sequence
(Note 1)
Am29PDS322D Command Definitions
First
Second
Data
RD
Third
Fourth
Fifth
Addr
Data
Addr
Data
Addr
Data
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
0001
Device ID (Note 9)
4
555
AA
2AA
55
555
90
X01
227E
SecSi Sector Factory
Protect (Note 10)
4
555
AA
2AA
55
555
90
X03
80/00
Sector Group Protect Verify
(Note 11)
4
555
AA
2AA
55
555
90
(SGA)
X02
XX00/
XX01
88
Sixth
Addr
Data
Addr
Data
X0E
2206
X0F
2201/
2200
Enter SecSi Sector Region
3
555
AA
2AA
55
555
Exit SecSi Sector Region
4
555
AA
2AA
55
555
90
XXX
00
Program
4
555
AA
2AA
55
555
A0
PA
PD
3
Unlock Bypass Program (Note 12) 2
Unlock Bypass Reset (Note 13)
2
555
AA
2AA
55
555
20
XXX
A0
PA
PD
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 14)
1
BA
B0
Erase Resume (Note 15)
1
BA
30
Unlock Bypass
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SGA = Address of the sector group to be verified (in autoselect mode)
or erased. Address bits A20–A12 uniquely select any sector.
Notes:
1.
9.
See Table 1 for description of bus operations.
2. All values are in hexadecimal.
The device ID must be read across the fourth, fifth and sixth
cycles. The sixth cycle specifies 2201h for top boot or 2200h for
bottom boot.
3. Except for the read cycle and the fourth and fifth cycle of the
autoselect command sequence, all bus cycles are write cycles.
10. The data is 80h for factory locked and 00h for not factory locked.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
11. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
5. Unless otherwise noted, address bits A20–A12 are don’t cares in
unlock sequence.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
6. No unlock or command cycles required when device is in read
mode.
13. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
May 13, 2002
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
Am41PDS3228D
27
P R E L I M I N A R Y
FLASH WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 11 and the following subsections describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ6–DQ0 may be still
invalid. Valid data on DQ7–DQ0 will appear on successive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 22
in the Flash AC Characteristics section shows the
Data# Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host syst e m wh e t h er an E m b e d d e d P r o gr am o r E ra se
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to reading
array data.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
28
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then
the bank returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am41PDS3228D
Figure 6. Data# Polling Algorithm
May 13, 2002
P R E L I M I N A R Y
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm. Figure 23 in
the “Measurements performed by placing a 50Ω termination on the data pin with a bias of V CC /2. The time
from OE# high to the data bus driven to VCC/2 is taken
as tDFAC Characteristics.” section shows the toggle bit
timing diagrams. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
START
Table 11 shows the outputs for RY/BY#.
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Read DQ7–DQ0
Toggle Bit
= Toggle?
Yes
No
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
May 13, 2002
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
No
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Am41PDS3228D
Figure 7.
Toggle Bit Algorithm
29
P R E L I M I N A R Y
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ6 in
graphical form.
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previously in the erase-suspend-program mode).
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
30
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the system software should check the status of DQ3 prior to
and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 11 shows the status of DQ3 relative to the other
status bits.
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
Table 11.
Standard
Mode
Erase
Suspend
Mode
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
Read
Non-Erase
Suspended Sector
Erase-Suspend-Program
Write Operation Status
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
DQ5
(Note 1)
0
0
DQ3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
RY/BY#
0
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
May 13, 2002
Am41PDS3228D
31
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
Voltage with Respect to Ground
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
VCCf/VCCs Supply Voltage
VCCf/VCCs for standard voltage range . . 1.8 V to 2.2 V
VCCf/VCCs (Note 1) . . . . . . . . . . . . –0.3 V to +2.5 V
RESET# (Note 2) . . . . . . . . . . . . . –0.5 V to +11 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O p in s may
overshoot V SS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 8. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 9.
2. Minimum DC input voltage on pins OE#, RESET#, and
WP#/ACC is –0.5 V. During voltage transitions, OE#,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 8. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of t he device to absolut e maximum rat ing
conditions for extended periods may affect device reliability.
20 ns
20 ns
+0.8 V
20 ns
VCC
+2.0 V
VCC
+0.5 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Negative
Overshoot Waveform
32
20 ns
Figure 9. Maximum Positive
Overshoot Waveform
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
±1.0
µA
ILIT
RESET# Input Load Current
VCC = VCC max; RESET# = 12.5 V
35
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
±1.0
µA
ILIA
ACC Input Leakage Current
VCC = VCC max, WP#/ACC = VACC max
35
µA
1 MHz
2.5
3
10 MHz
24
28
15
30
mA
ICC1f
Flash VCC Active Inter-Page Read Current
(Notes 1, 2)
ICC2f
Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH
ICC3f
Flash VCC Standby Current (Note 2)
VCC f = VCC max, CE#f,
RESET# = VCC ± 0.3 V
0.2
5
µA
ICC4f
Flash VCC Reset Current (Note 2)
VCC f = VCC max, WP#/ACC = VCCf ± 0.3 V,
RESET# = VSS ± 0.3 V
0.1
5
µA
ICC5f
Flash VCC Automatic Sleep Mode Current
(Notes 2, 4)
VCC f = VCC max, CE#f = VSS ± 0.3 V;
RESET# = VCC ± 0.3 V,
VIN = VCC ± 0.3 V or VSS ± 0.3 V
0.2
5
µA
ICC6f
Flash VCC Active Read-While-Program
Current (Notes 1, 2, 5)
CE#f = VIL, OE# = VIH
30
55
mA
ICC7f
Flash VCC Active Read-While-Erase Current
CE#f = VIL, OE# = VIH
(Notes 1, 2, 5)
30
55
mA
ICC8f
Flash VCC Active
Program-While-Erase-Suspended Current
(Note 2)
CE#f = VIL, OE# = VIH
17
35
mA
ICC9f
Flash VCC Active Intra-Page Read Current
CE#f = VIL, OE# = VIH
10 MHz
0.5
1
20 MHz
1
2
IACC
WP#/ACC Accelerated Program Current
VCC = VCCMax, WP#/ACC = VACCMax
12
20
VIL
Input Low Voltage
–0.5
0.2 x VCC
V
VIH
Input High Voltage
0.8 x VCC
VCC + 0.3
V
CE#f = VIL, OE# = VIH,
mA
mA
mA
VACC/VHH
Voltage for WP#/ACC Program Acceleration
and Sector Protection/Unprotection
8.5
9.5
V
VID
Voltage for Sector Protection, Autoselect and
Temporary Sector Unprotect
9
11
V
VOL
Output Low Voltage
0.1
V
VOH1
VOH2
VLKO
Output High Voltage
IOL = 4.0 mA, VCCf = VCCs = VCC min
IOH = –2.0 mA, VCC f = VCCs = VCC min
IOH = –100 µA, VCC = VCC min
Flash Low VCC Lock-Out Voltage (Note 5)
0.85 x VCC
V
VCC–0.1
1.2
1.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2.
3.
4.
5.
Maximum ICC specifications are tested with VCC = VCC max.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA.
Not 100% tested.
May 13, 2002
Am41PDS3228D
33
P R E L I M I N A R Y
SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
ILI
Input Leakage Current
VIN = VSS to VCC
–1.0
1.0
µA
ILO
Output Leakage Current
CE1#s = VIH, CE2s = VIL or OE# =
VIH or WE# = V IL, VIO= VSS to VCC
–1.0
1.0
µA
ICC
Operating Power Supply Current
IIO = 0 mA, CE1#s = V IL, CE2s =
WE# = VIH, V IN = V IH or V IL
2
mA
ICC1s
Average Operating Current
Cycle time = 1 µs, 100% duty,
IIO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ V CC – 0.2 V, VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
2
mA
ICC2s
Average Operating Current
Cycle time = Min., IIO = 0 mA,
100% duty, CE1#s = VIL, CE2s =
VIH, VIN = VIL = or VIH
17
mA
VOL
Output Low Voltage
IOL = 0.1 mA
0.2
V
VOH
Output High Voltage
IOH = –0.1 mA
1.4
Standby Current (CMOS)
CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –
0.2 V (CE1#s controlled) or CE2 ≤
0.2 V (CE2s controlled), CIOs =
VSS or VCC, Other input = 0 ~ VCC
0.5
ISB1
V
8
µA
Note: Typical values measured at VCC = 2.0 V, TA = 25°C. Not 100% tested.
34
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
Zero-Power Flash
25
Supply Current in mA
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
18
2.0 V
15
Supply Current in mA
12
9
6
3
0
1
2
3
4
5
6
7
8
Frequency in MHz
Note: T = 25 °C
Figure 11.
May 13, 2002
Typical ICC1 vs. Frequency
Am41PDS3228D
35
P R E L I M I N A R Y
TEST CONDITIONS
Table 12.
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent
Figure 12.
Test Specifications
100, 110 ns
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
2.0
V
Input timing measurement reference
levels
1.0
V
Output timing measurement
reference levels
1.0
V
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
2.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.0 V
Measurement Level
1.0 V
Output
0.0 V
Figure 13.
36
Input Waveforms and Measurement Levels
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM CE#s Timing
Parameter
Test Setup
JEDEC
Std
Description
—
tCCR
CE#s Recover Time
—
Min
All Speeds
Unit
0
ns
CE#f
tCCR
tCCR
tCCR
tCCR
CE1#s
CE2s
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash
May 13, 2002
Am41PDS3228D
37
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Option
JEDEC
Std
Description
Test Setup
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tPRC
Page Read Cycle
tPACC
Page Address to Output Delay
10
11
Unit
Min
100
110
ns
Max
100
110
ns
Min
40
45
ns
CE#, OE# = VIL
Max
40
45
ns
OE# = VIL
Max
100
110
ns
35
45
ns
CE#, OE# = VIL
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold
Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC /2. The time from OE# high to the
data bus driven to VCC/2 is taken as tDF AC Characteristics.
tRC
Addresses Stable
Addresses
tACC
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 15.
38
Conventional Read Operation Timings
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Same page Addresses
A20 to A2
A1 to A0
Ab
Ac
tRC
tACC
tPRC
tPRC
tOE
tOEH
WE#
Output
High-Z
Figure 16.
May 13, 2002
Ad
tCE
CE#
OE#
Aa
tDF
tPACC
tPACC
tPACC
tOH
tOH
tOH
Da
Db
Dc
tOH
Dd
Page Mode Read Timings
Am41PDS3228D
39
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
Description
JEDEC
All Speeds
Unit
Std
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
200
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#f, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#f, OE#
RESET#
tRP
Figure 17.
40
Reset Timings
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Flash Erase and Program Operations
Parameter
Speed Options
Unit
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time (WE# to Address)
Min
0
ns
tASO
Address Setup Time to OE# or CE#f Low During Toggle Bit
Polling
Min
15
ns
tAH
Address Hold Time (WE# to Address)
Min
60
ns
tAHT
Address Hold Time From CE#f or OE# High During Toggle Bit
Polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
60
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
Read
Min
0
ns
tOEH
OE# Hold Time
Toggle and Data# Polling
Min
20
ns
tOEPH
Output Enable High During Toggle Bit Polling
Min
20
ns
tGHEL
tGHEL
Read Recovery Time Before Write (OE# High to CE#f Low)
Min
0
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time (CE#f to WE#)
Min
0
ns
tELWL
tCS
CE#f Setup Time (WE# to CE#f)
Min
0
ns
tEHWH
tWH
WE# Hold Time (CE#f to WE#)
Min
0
ns
tWHEH
tCH
CE#f Hold Time (CE#f to WE#)
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
60
ns
tELEH
tCP
CE#f Pulse Width
Min
60
ns
tWHDL
tWPH
Write Pulse Width High
Min
60
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWLAX
10
11
100
110
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
11
µs
tWHWH1
tWHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
5
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
tVCS
VCCf Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time From RY/BY#
Min
0
ns
Program/Erase Valid To RY/BY# Delay
Max
90
ns
tBUSY
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
May 13, 2002
Am41PDS3228D
41
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#f
tCH
tGHWL
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCCf
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 18.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
Figure 19.
42
tVHH
Accelerated Program Timing Diagram
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SADD
VA
555h for chip erase
tAH
CE#f
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCCf
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”).
Figure 20. Chip/Sector Erase Operation Timings
May 13, 2002
Am41PDS3228D
43
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Addresses
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tCPH
tACC
tCE
CE#f
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Data
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE#f Controlled Write Cycles
Figure 21. Back-to-back Read/Write Cycle Timings
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#f
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ6–DQ0
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 22.
44
Data# Polling Timings (During Embedded Algorithms)
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#f
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
tOE
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
DQ6/DQ2
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24.
May 13, 2002
DQ2 vs. DQ6
Am41PDS3228D
45
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
JEDEC
All Speed Options
Unit
Min
500
ns
VHH Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET# Setup Time for Temporary
Sector/Sector Block Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector/Sector Block Unprotect
Min
4
µs
Std
Description
tVIDR
V ID Rise and Fall Time (See Note)
tVHH
Note: Not 100% tested.
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#f
WE#
tRRB
tRSP
RY/BY#
Figure 25.
46
Temporary Sector/Sector Block Unprotect
Timing Diagram
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
VID
VIH
RESET#
SADD, A6,
A1, A0
Valid*
Valid*
Sector/Sector Block Protect or Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#f
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram
May 13, 2002
Am41PDS3228D
47
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed Options
Unit
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time (WE# to Address)
Min
0
ns
tASO
Address Setup Time to CE#f Low During Toggle
Bit Polling
Min
15
ns
tAH
Address Hold Time
Min
60
ns
tAHT
Address Hold time from CE#f or OE# High During
Toggle Bit Polling
Min
0
ns
tDVEH
tDS
Data Setup Time
Min
60
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE#f Pulse Width
Min
60
ns
tEHEL
tCPH
CE#f Pulse Width High
Min
60
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
16
µs
tWHWH1
tWHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
5
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
tELAX
10
11
100
110
ns
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
48
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SADD for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#f
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 27.
May 13, 2002
Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
Am41PDS3228D
49
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Read Cycle
Parameter
Symbol
Description
10, 11
Unit
tRC
Read Cycle Time
Min
70
ns
tAA
Address Access Time
Max
70
ns
tCO1, tCO2
Chip Enable to Output
Max
70
ns
tOE
Output Enable Access Time
Max
35
ns
tBA
LB#s, UB#s to Access Time
Max
70
ns
Chip Enable (CE1#s Low and CE2s High) to Low-Z Output
Min
10
ns
tBLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
tOLZ
Output Enable to Low-Z Output
Min
5
ns
tHZ1, tHZ2
Chip Disable to High-Z Output
Max
25
ns
tBHZ
UB#s, LB#s Disable to High-Z Output
Max
25
ns
tOHZ
Output Disable to High-Z Output
Max
25
ns
tOH
Output Data Hold from Address Change
Min
10
ns
tLZ1, tLZ2
tRC
Address
tOH
Data Out
tAA
Data Valid
Previous Data Valid
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 28.
50
SRAM Read Cycle—Address Controlled
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
tRC
Address
tAA
tCO1
CS#1
CS2
tOH
tCO2
tHZ
tBA
UB#, LB#
tBHZ
tOE
OE#
tOLZ
tBLZ
Data Out
High-Z
tOHZ
tLZ
Data Valid
Figure 29.
SRAM Read Cycle
Notes:
1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
May 13, 2002
Am41PDS3228D
51
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Write Cycle
Parameter
Symbol
Description
10, 11
Unit
tWC
Write Cycle Time
Min
70
ns
tCw
Chip Enable to End of Write
Min
60
ns
tAS
Address Setup Time
Min
0
ns
tAW
Address Valid to End of Write
Min
60
ns
tBW
UB#s, LB#s to End of Write
Min
60
ns
tWP
Write Pulse Time
Min
50
ns
tWR
Write Recovery Time
Min
0
ns
Min
0
tWHZ
Write to Output High-Z
Max
20
tDW
Data to Write Time Overlap
Min
30
ns
tDH
Data Hold from Write Time
Min
0
ns
tOW
End Write to Output Low-Z
min
5
ns
ns
tWC
Address
tCW
(See Note 2)
CS1#s
tWR (See Note 3)
tAW
CS2s
tCW
(See Note 2)
tBW
UB#s, LB#s
WE#
Data In
tWP
(See Note 5)
tAS
(See Note 4)
tDW
High-Z
High-Z
Data Valid
tWHZ
Data Out
tDH
tOW
Data Undefined
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 30.
52
SRAM Write Cycle—WE# Control
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
tWC
Address
tAS (See Note 2 ) tCW
(See Note 3)
tWR (See Note 4)
CE1#s
tAW
CE2s
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tDW
Data Valid
Data In
Data Out
tDH
High-Z
High-Z
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 31.
May 13, 2002
SRAM Write Cycle—CE1#s Control
Am41PDS3228D
53
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
tWC
Address
tCW
(See Note 2)
CE1#s
tWR (See Note 3)
tAW
tCW (See Note 2)
CE2s
tBW
UB#s, LB#s
tAS
(See Note 4)
WE#
tWP
(See Note 5)
tDW
Data In
tDH
Data Valid
Data Out
High-Z
High-Z
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 32.
54
SRAM Write Cycle—UB#s and LB#s Control
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1
10
sec
Chip Erase Time
93
Excludes 00h programming
prior to erasure (Note 4)
Word Program Time
16
Accelerated Byte/Word Program Time
5
Chip Program Time
(Note 3)
20
Word Mode
sec
360
Excludes system level
overhead (Note 5)
µs
µs
100
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
FLASH LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter
Symbol
CIN
Description
Input Capacitance
Test Setup
Typ
Max
Unit
VIN = 0
11
14
pF
VOUT = 0
12
16
pF
COUT
Output Capacitance
CIN2
Control Pin Capacitance
VIN = 0
14
16
pF
CIN3
WP#/ACC Pin Capacitance
VIN = 0
17
20
pF
Note: 7.Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
May 13, 2002
Am41PDS3228D
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
55
P R E L I M I N A R Y
SRAM DATA RETENTION
Parameter
Symbol
Parameter Description
VDR
VCC for Data Retention
CS1#s ≥ VCC – 0.2 V (Note 1)
IDR
Data Retention Current
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
tSDR
Data Retention Set-Up Time
tRDR
Recovery Time
Test Setup
See data retention waveforms
Min
Typ
1.0
0.5
(Note 2)
Max
Unit
2.2
V
6
µA
0
ns
tRC
ns
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC.
2. Typical values are not 100% tested.
VCC
Data Retention Mode
tSDR
tRDR
1.8V
1.4V
VDR
CE1#s ≥ VCC - 0.2 V
CE1#s
GND
Figure 33.
CE1#s Controlled Data Retention Mode
Data Retention Mode
VCC
1.8 V
CE2s
tSDR
tRDR
VDR
CE2s < 0.2 V
0.4 V
GND
Figure 34.
56
CE2s Controlled Data Retention Mode
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm
May 13, 2002
Am41PDS3228D
57
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (February 21, 2002)
Figure 30, SRAM Write Cycle—WE# Control
Initial release.
Corrected tBW in Data Out waveform to tWHZ.
Revision A+1 (May 13, 2002)
Distinctive Characteristics
Modified text in “High Performance” bullet. Deleted
reference to 48-ball FBGA package.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
58
Am41PDS3228D
May 13, 2002