STMicroelectronics M58BW032DB55ZA3T 32 mbit (1mb x32, boot block, burst) 3.3v supply flash memory Datasheet

M58BW032BT, M58BW032BB
M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst)
3.3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■
■
■
SUPPLY VOLTAGE
– VDD = 3.0V to 3.6V for Program, Erase
and Read
– VDDQ = VDDQIN = 1.6V to 3.6V for I/O
Buffers
HIGH PERFORMANCE
– Access Time: 45, 55 and 60ns
– 75MHz Effective Zero Wait-State Burst
Read
– Synchronous Burst Reads
– Asynchronous Page Reads
MEMORY ORGANIZATION
– Eight 64 Kbit small parameter Blocks
Figure 1. Packages
PQFP80 (T)
– Four 128Kbit large parameter Blocks (of
which one is OTP)
BGA
– Sixty-two 512Kbit main Blocks
■
■
■
■
■
■
HARDWARE BLOCK PROTECTION
– WP pin Lock Program and Erase
– VPEN signal for Program/Erase Enable
SOFTWARE BLOCK PROTECTION
– Tuning Protection to Lock Program and
Erase with 64-bit User Programmable
Password (M58BW032B version only)
SECURITY
– 64-bit Unique Device Identifier (UID)
FAST PROGRAMMING
– Write to Buffer and Program capability
OPTIMIZED FOR FDI DRIVERS
– Common Flash Interface (CFI)
– Fast Program/Erase Suspend feature in
each block
LOW POWER CONSUMPTION
– 100µA Typical Standby
November 2004
LBGA80 (ZA)
10 x 8 ball array
■
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M58BW032xT: 8838h
– Bottom Device Code M58BW032xB:
8837h
OPERATING TEMPERATURE RANGE
– Automotive (Grade 3): –40 to 125°C
– Industrial (Grade 6): –40 to 90°C
1/60
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. LBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. PQFP Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Tuning Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB . . . . . . . . . . . . . . . . . . . 12
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable (GD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program/Erase Enable (VPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Supply Voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ground (VSS and VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Don’t Use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Reset/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Synchronous Burst Read Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby Disable Bit (M14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Y-Latency Bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Wrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Example Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Erase All Main Blocks Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Buffer and Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tuning Protection Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tuning Protection Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Set Block Protection Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clear Block Protection Configuration Register Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 27
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program/ Write to Buffer and Program/Tuning Protection Unlock Status (Bit 4) . . . . . . . . . . 28
VPEN Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6. AC Measurement Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Asynchronous Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . . 34
Figure 10.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11.Asynchronous Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12.Asynchronous Latch Controlled Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . . 38
Figure 13.Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . . . 39
Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14.Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . . . 40
Figure 15.Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . . 41
Figure 16.Synchronous Burst Read - Burst Address Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17.Reset, Power-Down and Power-up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Reset, Power-Down and Power-up AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18.LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline . . . . . . 43
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . 43
Figure 19.PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline . . . . . . . . . . . . . . . . . . . . . 44
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data. . . . . . . . . . . . . . 44
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A.FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 23.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 24.Unlock Device and Change Tuning Protection Code Flowchart . . . . . . . . . . . . . . . . . . . 50
4/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 25.Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . 51
Figure 26.Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . . 52
Figure 27.Power-up Sequence to Burst the Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28.Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . . 54
Figure 29.Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . . 55
Figure 30.Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . . 56
Figure 31.Command Interface and Program Erase Controller Flowchart (d) . . . . . . . . . . . . . . . . . 57
Figure 32.Command Interface and Program Erase Controller Flowchart (e) . . . . . . . . . . . . . . . . . 58
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SUMMARY DESCRIPTION
The M58BW032B/D is a 32Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a DoubleWord basis using a 3.0V to 3.6V VDD supply for the
circuit and a VDDQ supply down to 1.6V for the Input and Output buffers.
The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read Interface
allows a high data transfer rate controlled by the
Burst Clock, K, signal. It is capable of bursting
fixed or unlimited lengths of data. The burst type,
latency and length are configurable and can be
easily adapted to a large variety of system clock
frequencies and microprocessors. All Writes are
Asynchronous. On power-up the memory defaults
to Read mode with an Asynchronous Bus.
The device features an asymmetrical block architecture. The M58BW032B/D has an array of 62
main blocks of 512 Kbits each, plus 4 large parameter blocks of 128Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small
parameter blocks are located either at the top
(M58BW032BT, M58BW032DT) or at the bottom
(M58BW032BB, M58BW032DB) of the address
space. The first large parameter block is referred
to as Boot Block and can be used either to store a
boot code or parameters. The memory array organization is detailed in Tables 2, Top Boot Block Addresses and 3, Bottom Boot Block Addresses.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are required to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
Erase can be suspended in order to perform either
Read or Program in any other block and then resumed. Program can be suspended to Read data
in any other block and then resumed. Each block
6/60
can be programmed and erased over 100,000 cycles.
All blocks are protected during power-up. The
M58BW032B features four different levels of hardware and software block protection to avoid unwanted program/erase operations:
■
Write/Protect Enable input, WP, provides a
hardware protection of a combination of
blocks from program or erase operations. The
Block Protection configuration can be defined
individually by issuing a Set Block Protection
Configuration Register or Clear Block
Protection Configuration Register commands.
■
All Program or Erase operations are blocked
when Reset, RP, is held low.
■
A Program/Erase Enable input, VPEN, is used
to protect all blocks, preventing Program and
Erase operations from affecting their data.
■
The Program and Erase commands can be
password protected by the Tuning Protection
command.
The M58BW032D offers the same protection features with the exception of the Tuning Block Protection which is disabled in the factory.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consumption is reduced to the standby level, the device is
write protected and both the Status and Burst Configuration Registers are cleared. A recovery time is
required when the RP input goes High.
A manufacturer and device code are available.
They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of
the memory.
Finally, the M58BW032B/D features a Unique Device Identifier (UID) which is programmed by ST. It
is unique for each die and can be used to implement cryptographic algorithms to improve security.
The memory is offered in PQFP80 (14 x 20mm)
and LBGA80 (1.0mm pitch) packages and it is
supplied with all the bits erased (set to ’1’).
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A19
Address inputs
DQ0-DQ7
Data Input/Output, Command Input
DQ8-DQ15
Data Input/Output, Burst Configuration
Register
DQ16-DQ31
Data Input/Output
B
Burst Address Advance
E
Chip Enable
G
Output Enable
K
Burst Clock
L
Latch Enable
R
Valid Data Ready
RP
Reset /Power-Down
GD
W
Write Enable
W
GD
Output Disable
WP
Write Protect
VDD
Supply Voltage
VDDQ
Power Supply for Output Buffers
VDDQIN
Power Supply for Input Buffers only
VPEN
Program/Erase Enable
VSS
Ground
VSSQ
Input/Output Ground
NC
Not Connected Internally
DU
Don’t Use as Internally Connected
VDD VDDQ VDDQIN VPEN
A0-A19
DQ0-DQ31
K
L
E
RP
M58BW032BT
M58BW032BB
M58BW032DT
M58BW032DB
R
G
WP
B
VSS
VSSQ
AI08918b
7/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 3. LBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A15
A14
VDD
VPEN
VSS
A6
A3
A2
B
A16
A13
A12
A9
A8
A5
A4
A1
C
A17
A18
A11
A10
NC
A7
DU
A0
D
DQ3
DQ0
A19
DU
NC
DQ31
DQ30
DQ29
E
VDDQ
DQ4
DQ2
DQ1
DQ27
DQ28
DQ26
VDDQ
F
VSSQ
DQ7
DQ6
DQ5
NC
DQ25
DQ24
VSSQ
G
VDDQ
DQ8
DQ10
DQ9
DQ22
DQ21
DQ23
VDDQ
H
DQ13
DQ12
DQ11
WP
DQ17
DQ19
DQ18
DQ20
J
DQ15
DQ14
L
B
E
G
R
DQ16
K
VDDQIN
RP
K
VSS
VDD
W
GD
DU
AI08920b
8/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
1
64
53
40
41
DQ15
DQ14
DQ13
DQ12
VSSQ
VDDQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
VSSQ
VDDQ
DQ3
DQ2
DQ1
DQ0
A19
A18
A17
A16
VSS
VPEN
VDD
A9
A10
A11
A12
A13
A14
A15
24
25
12
32
M58BW032BT
M58BW032BB
M58BW032DT
M58BW032DB
A3
A4
A5
A6
A7
A8
DQ16
DQ17
DQ18
DQ19
VDDQ
VSSQ
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
VDDQ
VSSQ
DQ28
DQ29
DQ30
DQ31
DU
A0
A1
A2
65
80
73
DU
R
GD
WP
W
G
E
VDD
B
VSS
L
NC
NC
K
RP
VDDQIN
Figure 4. PQFP Connections (Top view through package)
AI08919c
9/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Block Protection
The M58BW032B features four different levels of
block protection. The M58BW032D has the same
block protection with the exception of the Tuning
Block Protection, which is disabled in the factory.
■
Write Protect Pin, WP, - When WP is Low,
VIL, the protection status that has been
configured in the Block Protection
Configuration Register is activated. The Block
Protection Configuration Register is volatile.
Any combination of blocks is possible. Any
attempt to program or erase a protected block
will be ignored and will return an error in the
Status Register (see Table 11., Status
Register Bits).
■
Reset/Power-Down Pin, RP, - If the device is
held in reset mode (RP at VIL), no program or
erase operations can be performed on any
block.
■
Program/Erase Enable, VPEN, - VPEN
protects all blocks preventing Program and
Erase operations from affecting their data.
Program/Erase Enable must be kept High
(VIH) during all Program/Erase Controller
operations, otherwise the operations is not
guaranteed to succeed and data may become
corrupt.
■
Tuning Block Protection - M58BW032B
features a 64 bit password protection for
program and erase operations for a fixed
number of blocks After power-up or reset the
device is tuning protected. An Unlock
command is provided to allow program or
erase operations in all the blocks.
After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. They do not affect the Tuning
10/60
Block Protection. When the two protections are
disabled, WP and RP at VIH, the blocks locked by
the Tuning Block Protection cannot be modified.
All blocks are protected at power-up.
Tuning Block Protection
The Tuning Block Protection is a software feature
to protect blocks from program or erase operations. It allows the user to lock program and erase
operations with a user definable 64 bit code. It is
only available on the M58BW032B version.
The code is written once in the Tuning Protection
Register and cannot be erased. When shipped the
flash memory will have the Tuning Protection
Code bits set to ‘1'. The user can program a ‘0’ in
any of the 64 positions. Once programmed it is not
possible to reset a bit to ‘1’ as the cells cannot be
erased. The Tuning Protection Register can be
programmed at any moment (after providing the
correct code), however once all bits are set to ‘0’
the Tuning Protection Code can no longer be altered.
The Tuning Protection Code locks the program
and erase operations of all the blocks except for
blocks 12 and 13 for the bottom configuration, and
blocks 60 and 61 for the top configuration.
The tuning blocks are "locked" if the tuning protection code has not been provided, and “unlocked"
once the correct code has been provided. The tuning blocks are locked after reset or power-up. The
tuning protection status can be monitored in the
Status Register. Refer to the Status Register section.
Refer to the Command Interface section for the
Tuning Protection Block Unlock and Tuning Protection Program commands. See Appendix A, Figure 24, 25 and 26 for suggested flowcharts for
using the Tuning Block Protection commands.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 2. Top Boot Block Addresses,
M58BW032BT, M58BW032DT
#
Size (Kbit)
Address Range(1)
TP(2)
73
128
FF000h-FFFFh
yes
72
128
FE000h-FEFFFh(3)
yes
71
128
FD000h-FDFFFh
yes
70
128
FC000h-FCFFFh
yes
69
64
FB800h-FBFFFh
yes
68
64
FB000h-FB7FFh
yes
67
64
FA800h-FAFFFh
yes
66
64
FA000h-FA7FFh
yes
65
64
F9800h-F9FFFh
yes
64
64
F9000h-F97FFh
yes
63
64
F8800h-F8FFFh
yes
62
64
F8000h-F87FFh
yes
61
512
F4000h-F7FFFh
no
60
512
F0000h-F3FFFh
no
59
512
EC000h-EFFFFh
yes
58
512
E8000h-EBFFFh
yes
57
512
E4000h-E7FFFh
yes
56
512
E0000h-E3FFFh
yes
55
512
DC000h-DFFFFh
yes
54
512
D8000h-DBFFFh
yes
53
512
D4000h-D7FFFh
yes
52
512
D0000h-D3FFFh
yes
51
512
CC000h-CFFFFh
yes
50
512
C8000h-CBFFFh
yes
49
512
C4000h-C7FFFh
yes
48
512
C0000h-C3FFFh
yes
47
512
BC000h-BFFFFh
yes
46
512
B8000h-BBFFFh
yes
45
512
B4000h-B7FFFh
yes
44
512
B0000h-B3FFFh
yes
43
512
AC000h-AFFFFh
yes
42
512
A8000h-ABFFFh
yes
41
512
A4000h-A7FFFh
yes
40
512
A0000h-A3FFFh
yes
39
512
9C000h-9FFFFh
yes
38
512
98000h-9BFFFh
yes
37
512
94000h-97FFFh
yes
#
Size (Kbit)
Address Range(1)
TP(2)
36
512
90000h-93FFFh
yes
35
512
8C000h-8FFFFh
yes
34
512
88000h-8BFFFh
yes
33
512
84000h-87FFFh
yes
32
512
80000h-83FFFh
yes
31
512
7C000h-7FFFFh
yes
30
512
78000h-7BFFFh
yes
29
512
74000h-77FFFh
yes
28
512
70000h-73FFFh
yes
27
512
6C000h-6FFFFh
yes
26
512
68000h-6BFFFh
yes
25
512
64000h-67FFFh
yes
24
512
60000h-63FFFh
yes
23
512
5C000h-53FFFFh
yes
22
512
58000h-5BFFFh
yes
21
512
54000h-57FFFh
yes
20
512
50000h-53FFFh
yes
19
512
4C000h-4FFFFh
yes
18
512
48000h-4BFFFh
yes
17
512
44000h-47FFFh
yes
16
512
40000h-43FFFh
yes
15
512
3C000h-3FFFFh
yes
14
512
38000h-3BFFFh
yes
13
512
34000h-37FFFh
yes
12
512
30000h-33FFFh
yes
11
512
2C000h-2FFFFh
yes
10
512
28000h-2BFFFh
yes
9
512
24000h-27FFFh
yes
8
512
20000h-23FFFh
yes
7
512
1C000h-1FFFFh
yes
6
512
18000h-1BFFFh
yes
5
512
14000h-17FFFh
yes
4
512
10000h-13FFFh
yes
3
512
0C000h-0FFFFh
yes
2
512
08000h-0BFFFh
yes
1
512
04000h-07FFFh
yes
0
512
00000h-03FFFh
yes
Note: 1. Addresses are indicated in 32-bit addressing.
2. TP = Tuning Protected Block, only available for the
M58BW032B.
3. OTP Block.
11/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 3. Bottom Boot Block Addresses,
M58BW032BB, M58BW032DB
#
Size (Kbit)
Address Range(1)
TP(2)
73
512
FC000h-FFFFFh
yes
72
512
F8000h-FBFFFh
yes
71
512
F4000h-F7FFFh
yes
70
512
F0000h-F3FFFh
yes
69
512
EC000h-EFFFFh
yes
68
512
E8000h-EBFFFh
yes
67
512
E4000h-E7FFFh
yes
66
512
E0000h-E3FFFh
yes
65
512
DC000h-DFFFFh
yes
64
512
D8000h-DBFFFh
yes
63
512
D4000h-D7FFFh
yes
62
512
D0000h-D3FFFh
yes
61
512
CC000h-CFFFFh
yes
60
512
C8000h-CBFFFh
yes
59
512
C4000h-C7FFFh
yes
58
512
C0000h-C3FFFh
yes
57
512
BC000h-BFFFFh
yes
56
512
B8000h-BBFFFh
yes
55
512
B4000h-B7FFFh
yes
54
512
B0000h-B3FFFh
yes
53
512
AC000h-AFFFFh
yes
52
512
A8000h-ABFFFh
yes
51
512
A4000h-A7FFFh
yes
50
512
A0000h-A3FFFh
yes
49
512
9C000h-9FFFFh
yes
48
512
98000h-9BFFFh
yes
47
512
94000h-97FFFh
yes
46
512
90000h-93FFFh
yes
45
512
8C000h-8FFFFh
yes
44
512
88000h-8BFFFh
yes
43
512
84000h-87FFFh
yes
42
512
80000h-83FFFh
yes
41
512
7C000h-7FFFFh
yes
40
512
78000h-7BFFFh
yes
39
512
74000h-77FFFh
yes
38
512
70000h-73FFFh
yes
37
512
6C000h-6FFFFh
yes
36
512
68000h-6BFFFh
yes
12/60
#
Size (Kbit)
Address Range(1)
TP(2)
35
512
64000h-67FFFh
yes
34
512
60000h-63FFFh
yes
33
512
5C000h-53FFFFh
yes
32
512
58000h-5BFFFh
yes
31
512
54000h-57FFFh
yes
30
512
50000h-53FFFh
yes
29
512
4C000h-4FFFFh
yes
28
512
48000h-4BFFFh
yes
27
512
44000h-47FFFh
yes
26
512
40000h-43FFFh
yes
25
512
3C000h-3FFFFh
yes
24
512
38000h-3BFFFh
yes
23
512
34000h-37FFFh
yes
22
512
30000h-33FFFh
yes
21
512
2C000h-2FFFFh
yes
20
512
28000h-2BFFFh
yes
19
512
24000h-27FFFh
yes
18
512
20000h-23FFFh
yes
17
512
1C000h-1FFFFh
yes
16
512
18000h-1BFFFh
yes
15
512
14000h-17FFFh
yes
14
512
10000h-13FFFh
yes
13
512
0C000h-0FFFFh
no
12
512
08000h-0BFFFh
no
11
64
07800h-07FFFh
yes
10
64
07000h-077FFh
yes
9
64
06800h-06FFFh
yes
8
64
06000h-067FFh
yes
7
64
05800h-05FFFh
yes
6
64
05000h-057FFh
yes
5
64
04800h-04FFFh
yes
4
64
04000h-047FFh
yes
3
128
03000h-03FFFh
yes
2
128
02000h-02FFFh
yes
1
128
01000h-01FFFh(3)
yes
0
128
00000h-00FFFh
yes
Note: 1. Addresses are indicated in 32-bit Word addressing.
2. TP = Tuning Protected Block, only available for the
M58BW032B.
3. OTP Block.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A19). The Address Inputs
are used to select the cells to access in the memory array during Bus Read operations either to
read or to program data to. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be Low when selecting the addresses.
The address inputs are latched on the rising edge
of Latch Enable L or Burst Clock K, whichever occurs first, in a read operation.The address inputs
are latched on the rising edge of Chip Enable,
Write Enable or Latch Enable, whichever occurs
first in a Write operation. The address latch is
transparent when Latch Enable is Low, VIL. The
address is internally latched in an Erase or Program operation.
Data Inputs/Outputs (DQ0-DQ31). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
Low, VIL, and Output Disable is at VIH, the data
bus outputs data from the memory array, the Electronic Signature, the Block Protection Configuration Register, the CFI Information or the contents
of Burst Configuration Register or Status Register.
The data bus is high impedance when the device
is deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/PowerDown at VIL. The Status Register content is output
on DQ0-DQ7 and DQ8-DQ31 are at VIL.
Chip Enable (E). The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at
VIH deselects the memory and reduces the power
consumption to the Standby level.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation, when Output Disable GD is at
VIH. When Output Enable G is at VIH, the outputs
are high impedance independently of Output Disable.
Output Disable (GD). The Output Disable, GD,
deactivates the data output buffers. When Output
Disable, GD, is at VIH, the outputs are driven by
the Output Enable. When Output Disable, GD, is
at VIL, the outputs are high impedance independently of Output Enable. The Output Disable pin
must be connected to an external pull-up resistor
as there is no internal pull-up resistor to drive the
pin.
Write Enable (W). The Write Enable, W, input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write Enable (also see Latch Enable, L).
Reset/PowerReset/Power-Down (RP). The
Down, RP, is used to apply a hardware reset to the
memory. A hardware reset is achieved by holding
Reset/Power-Down Low, VIL, for at least tPLPH.
Writing is inhibited to protect data, the Command
Interface and the Program/Erase Controller are reset. The Status Register information is cleared and
power consumption is reduced to the standby level
(IDD1). The device acts as deselected, that is the
data outputs are high impedance.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read operations after a delay of tPHEL or Bus Write operations after
tPHWL.
If Reset/Power-Down goes Low, VIL, during a
Block Erase, a Program or a Tuning Protection
Program the operation is aborted, in a time of tPLRH maximum, and data is altered and may be corrupted.
During Power-up power should be applied simultaneously to VDD and VDDQ(IN) with RP held at VIL.
When the supplies are stable RP is taken to VIH.
Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an
erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous
Random Read.
See Table 21 and Figure 17., Reset, Power-Down
and Power-up AC Waveform, for more details.
Program/Erase Enable (VPEN). The Program./
Erase Enable input, VPEN, protects all blocks, preventing Program and Erase operations from modifying the data. Program/Erase Enable must be
kept High (VIH) during all operations when the Program/Erase Controller is active, otherwise the operation is not guaranteed to succeed and data may
become corrupt.
Latch Enable (L). The Bus Interface can be configured to latch the Address Inputs on the rising
edge of Latch Enable, L, for Asynchronous Latch
13/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Enable Controlled Read or Write or Synchronous
Burst Read operations. In Synchronous Burst
Read operations the address is latched on the active edge of the Clock when Latch Enable is Low,
VIL. Once latched, the addresses may change
without affecting the address used by the memory.
When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for
Asynchronous Random Read and Write operations.
Burst Clock (K). The Burst Clock, K, is used to
synchronize the memory with the external bus during Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. In
Synchronous Burst Read mode the address is
latched on the first rising clock edge when Latch
Enable is Low, VIL, or on the rising edge of Latch
Enable, whichever occurs first.
During Asynchronous bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during Synchronous Burst Read operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X-latency
time has expired. If Burst Address Advance is
Low, VIL, the internal address counter advances. If
Burst Address Advance is High, VIH, the internal
address counter does not change; the same data
remains on the Data Inputs/Outputs and Burst Address Advance is not sampled until the Y-latency
expires.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R). The Valid Data Ready
output, R, can be used during Synchronous Burst
Read operations to identify if the memory is ready
to output data or not. The Valid Data Ready output
can be configured to be active on the clock edge
of the invalid data read cycle or one cycle before.
Valid Data Ready, at VIH, indicates that new data
14/60
is or will be available. When Valid Data Ready is
Low, VIL, the previous data outputs remain active.
Write Protect (WP). The Write Protect, WP, provides protection against program or erase operations. When Write Protect, WP, is at VIL, the
protection status that has been configured in the
Block Protection Configuration Register is activated. Program and erase operations to protected
blocks are disabled. When Write Protect WP is at
VIH all the blocks can be programmed or erased, if
no other protection is used.
Supply Voltage (VDD). The Supply Voltage, VDD,
is the core power supply. All internal circuits draw
their current from the VDD pin, including the Program/Erase Controller.
Output Supply Voltage (VDDQ). The Output Supply Voltage, VDDQ, is the output buffer power supply
for all operations (Read, Program and Erase) used
for DQ0-DQ31 when used as outputs.
Input Supply Voltage (VDDQIN). The Input Supply Voltage, VDDIN, is the power supply for all input
signal. Input signals are: K, B, L, W, GD, G, E, A0A18 and D0-D31, when used as inputs.
Ground (VSS and VSSQ). The Ground VSS is the
reference for the internal supply voltage VDD. The
Ground VSSQ is the reference for the output and
input supplies VDDQ, and VDDQIN. It is essential to
connect VSS and VSSQ together.
Note: A 0.1µF capacitor should be connected
between the Supply Voltages, VDD, VDDQ and
VDDIN and the Grounds, VSS and VSSQ to decouple the current surges from the power supply.
The PCB track widths must be sufficient to carry the currents required during all operations
of the parts, see Table 15., DC Characteristics,
for maximum current supply requirements.
Don’t Use (DU). This pin should not be used as it
is internally connected. Its voltage level can be between VSS and VDDQ or leave it unconnected.
Not Connected (NC). This pin is not physically
connected to the device.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
BUS OPERATIONS
Each bus operations that controls the memory is
described in this section, see Tables 4 and 5 Bus
Operations, for a summary. The bus operation is
selected through the Burst Configuration Register;
the bits in this register are described at the end of
this section.
On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write. No synchronous operation
can be performed until the Burst Control Register
has been configured.
The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read in
asynchronous mode regardless of the Burst Control Register settings.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus Operations
For asynchronous bus operations refer to Table 4
together with the following text.
Asynchronous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Block Protection Configuration Register, Status Register,
CFI and Burst Configuration Register) in the Command Interface. A valid bus operation involves setting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable and
Output Enable and keeping Write Enable and Output Disable High, VIH. The Data Inputs/Outputs
will output the value, see Figure 8., Asynchronous
Bus Read AC Waveforms, and Table
16., Asynchronous Bus Read AC Characteristics.,
for details of when the output becomes valid.
Asynchronous Read is the default read mode
which the device enters on power-up or on return
from Reset/Power-Down.
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip Enable and Latch Enable Low, VIL and keeping Write
Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address Inputs can change. Set Output Enable Low,
VIL, to read the data on the Data Inputs/Outputs;
see Figure Figure 9., Asynchronous Latch Controlled Bus Read AC Waveforms and Table
17., Asynchronous Latch Controlled Bus Read AC
Characteristics, for details on when the output becomes valid.
Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
Asynchronous Page Read. Asynchronous
Page Read operations are used to read from several addresses within the same memory page.
Each memory page is 4 Double-Words and is addressed by the address inputs A0 and A1.
Data is read internally and stored in the Page Buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different
timings. The first read operation within the page
has identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings apply again. Page Read does not support Latched
Controlled Read.
See Figure 10., Asynchronous Page Read AC
Waveforms, and Table 18., Asynchronous Page
Read AC Characteristics, for details on when the
outputs become valid.
Asynchronous Bus Write. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address Inputs, and setting Chip Enable, Write Enable and
Latch Enable Low, VIL, and Output Enable High,
VIH, or Output Disable Low, VIL. The Address Inputs are latched by the Command Interface on the
rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and Input Data are
latched on the rising edge of Chip Enable, E, or
Write Enable, W, whichever occurs first. Output
Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write
operation.
See Figure 11., Asynchronous Write AC Waveform, and Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the
timing requirements.
15/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Asynchronous Latch Controlled Bus Write.
Asynchronous Latch Controlled Bus Write operations write to the Command Interface in order to
send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
VIL. The Address Inputs are latched by the Command Interface on the rising edge of Latch Enable,
Write Enable or Chip Enable, whichever occurs
first. Commands and Input Data are latched on the
rising edge of Chip Enable, E, or Write Enable, W,
whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole
Asynchronous Bus Write operation.
See Figure 12., Asynchronous Latch Controlled
Write
AC
Waveform,
and
Table
19., Asynchronous Write and Latch Controlled
Write AC Characteristics, for details of the timing
requirements.
Output Disable. The data outputs are high impedance when the Output Enable, G, is at VIH or
Output Disable, GD, is at VIL.
Standby. When Chip Enable is High, VIH, and the
Program/Erase Controller is idle, the memory enters Standby mode, the power consumption is reduced to the standby level (IDD1) and the Data
Inputs/Outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable or Output Disable inputs.
The Standby mode can be disabled by setting the
Standby Disable bit (M14) of the Burst Configuration Register to ‘1’ (see Table 15., DC Characteristics).
Reset/Power-Down. The memory is in Reset/
Power-Down mode when Reset/Power-Down,
RP, is at VIL. The power consumption is reduced
to the standby level (IDD1) and the outputs are high
impedance, independent of the Chip Enable, E,
Output Enable, G, Output Disable, GD, or Write
Enable, W, inputs. In this mode the device is write
protected and both the Status and the Burst Configuration Registers are cleared. A recovery time is
required when the RP input goes High.
Table 4. Asynchronous Bus Operations
Bus Operation
Step
E
G
GD
W
RP
L
A0-A19
DQ0-DQ31
VIL
VIL
VIH
VIH
VIH
VIL
Address
Data Output
Address Latch
VIL
VIH
VIH
VIL
VIH
VIL
Address
High Z
Read
VIL
VIL
VIH
VIH
VIH
VIH
X
Data Output
Asynchronous Page Read
VIL
VIL
VIH
VIH
VIH
X
Address
Data Output
Asynchronous Bus Write
VIL
VIH
X
VIL
VIH
VIL
Address
Data Input
Address Latch
VIL
VIH
X
VIH
VIH
VIL
Address
High Z
Write
VIL
VIH
X
VIL
VIH
VIH
X
Data Input
Output Disable, G
VIL
VIH
VIH
VIH
VIH
X
X
High Z
Output Disable, GD
VIL
VIL
VIL
VIH
VIH
X
X
High Z
Standby
VIH
X
X
X
VIH
X
X
High Z
X
X
X
X
VIL
X
X
High Z
Asynchronous Bus Read(2)
Asynchronous Latch
Controlled Bus Read
Asynchronous Latch
Controlled Bus Write
Reset/Power-Down
Note: 1. X = Don’t Care
2. Data, Manufacturer Code, Device Code, Burst Configuration Register, Standby Status and Block Protection Configuration Register
are read using the Asynchronous Bus Read command.
16/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Synchronous Bus Operations
For synchronous bus operations refer to Table 5
together with the following text.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memory at specific times synchronized to an external reference clock. The valid edge of the Clock signal is
the rising edge. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figure 5 for examples of
synchronous burst operations.
In continuous burst read, one burst read operation
can access the entire memory sequentially by
keeping the Burst Address Advance B at VIL for
the appropriate number of clock cycles. At the end
of the memory address space the burst read restarts from the beginning at address 000000h.
A valid Synchronous Burst Read operation begins
when the Burst Clock is active and Chip Enable
and Latch Enable are Low, VIL. The burst start address is latched and loaded into the internal Burst
Address Counter on the valid Burst Clock K edge
or on the rising edge of Latch Enable, whichever
occurs first.
After an initial memory latency time, the memory
outputs data each clock cycle (or two clock cycles
depending on the value of M9). The Burst Address
Advance B input controls the memory burst output.
The second burst output is on the next clock valid
edge after the Burst Address Advance B has been
pulled Low.
Valid Data Ready, R, monitors if the memory burst
boundary is exceeded and the Burst Controller of
the microprocessor needs to insert wait states.
When Valid Data Ready is Low on the rising clock
edge, no new data is available and the memory
does not increment the internal address counter at
the active clock edge even if Burst Address Advance, B, is Low.
Valid Data Ready may be configured (by bit M8 of
Burst Configuration Register) to be valid immediately at the rising clock edge or one data cycle before the rising clock edge.
Synchronous Burst Read will be suspended if
Burst Address Advance, B, goes High, VIH.
If Output Enable is at VIL and Output Disable is at
VIH, the last data is still valid.
If Output Enable, G, is at VIH or Output Disable,
GD, is at VIL, but the Burst Address Advance, B, is
at VIL the internal Burst Address Counter is incremented at each Burst Clock K rising edge.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 13, 14,
15 and 16, and Table 20.
Synchronous Burst Read Suspend. During a
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address
Advance going High, VIH, stops the burst counter
and the Output Enable going High, VIH, inhibits the
data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable
Low.
Table 5. Synchronous Burst Read Bus Operations
E
G
GD
RP
K
L
B
A0-A19
DQ0-DQ31
Address Latch
VIL
VIH
X
VIH
R(3)
VIL
X
Address Input
Read
VIL
VIL
VIH
VIH
R(3)
VIH
VIL
Data Output
Read Suspend
VIL
VIH
X
VIH
X
VIH
VIH
High Z
Read Resume
VIL
VIL
VIH
VIH
R(3)
VIH
VIL
Data Output
Burst Address Advance
VIL
VIH
X
VIH
R(3)
VIH
VIL
High Z
Read Abort, E
VIH
X
X
VIH
X
X
X
High Z
X
X
X
VIL
X
X
X
High Z
Bus Operation
Synchronous Burst
Read(2)
Step
Read Abort, RP
Note: 1. X = Don't Care, VIL or VIH.
2. M15 = 0, Bit M15 is in the Burst Configuration Register.
3. R= Rising Edge.
17/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Burst Configuration Register
The Burst Configuration Register is used to configure the type of bus access that the memory will
perform.
The Burst Configuration Register is set through
the Command Interface and will retain its information until it is re-configured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register bits are described in Table 6. They specify the selection of
the burst length, burst type, burst X and Y latencies and the Read operation. Refer to Figure 5 for
examples of synchronous burst configurations.
Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous accesses.
Standby Disable Bit (M14). The Standby Disable Bit, M14, is used to disable the Standby
mode. When the Standby bit is ‘1’, the device will
not enter Standby mode when Chip Enable goes
High, VIH.
X-Latency Bits (M13-M11). The X-Latency bits
are used during Synchronous Bus Read operations to set the number of clock cycles between
the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table
6., Burst Configuration Register. The X-Latency
bits should also be selected in accordance with
Note: 1. below Table 6., Burst Configuration Register.
Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table
18/60
6., Burst Configuration Register and Note 2.for
valid combinations of the Y-Latency, the X-Latency and the Clock frequency.
Valid Data Ready Bit (M8). The
Valid
Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. When the Valid Data Ready
bit is ’0’ the Valid Data Ready output pin is driven
Low for the rising clock edge when invalid data is
output on the bus. When the Valid Data Ready bit
is ’1’ the Valid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Wrap Burst Bit (M3). The burst reads can be
confined inside the 4 or 8 Word boundary (wrap) or
overcome the boundary (no wrap). The Wrap
Burst bit is used to select between wrap and no
wrap. When the Wrap Burst bit is set to ‘0’ the
burst read wraps; when it is set to ‘1’ the burst read
does not wrap.
Burst Length Bit (M2-M0). The Burst Length bits
set the maximum number of Double-Words that
can be output during a Synchronous Burst Read
operation before the address wraps. Burst lengths
of 4 or 8 and continuous burst are available.
Table 6., Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Table 7., Burst Type Definition,
gives the sequence of addresses output from a
given starting address for each length.
If either a Continuous or a No Wrap Burst Read
has been initiated the device will output data synchronously. Depending on the starting address,
the device activates the Valid Data Ready output
to indicate that a delay is necessary before the
data is output. If the starting address is aligned to
a 4 Double Word boundary, the continuous burst
mode will run without activating the Valid Data
Ready output. If the starting address is not aligned
to a 4 Double Word boundary, Valid Data Ready is
activated to indicate that the device needs an internal delay to read the successive words in the array.
M10, M7 to M4 are reserved for future use.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 6. Burst Configuration Register
Bit
M15
M14
M13-M11
Description
0
Synchronous Burst Read
1
Asynchronous Read (Default at power-up)
0
Standby Mode Enabled (Default at power-up)
1
Standby Mode Disabled
001
3
010
4
011
5
100
6
101
7
110
8
0
One Burst Clock cycle
1
Two Burst Clock cycles
0
R valid Low during valid Burst Clock edge
1
R valid Low one data cycle before valid Burst Clock edge
0
Wrap
1
No Wrap
001
4 Double-Words
010
8 Double-Words
111
Continuous
Standby Disable
X-Latency (1)
Reserved
M9
Y-Latency (2)
Valid Data Ready
M7-M4
Reserved
M3
Wrapping
M2-M0
Description
Read Select
M10
M8
Value
Burst Length
Note: 1. X latencies can be calculated as: (tAVQV – tLLKH + tKHQV) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK
is the clock period), , where tLLKH is the value given by the master microcontroller timing specifications.
2. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tKHQV < Y tK.
3. tSYSTEM MARGIN is the time margin required for the calculation.
19/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 7. Burst Type Definition
M3
Starting
Address
x4
Sequential
x8
Sequential
Continuous
0
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10..
0
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11..
0
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12..
0
3
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13..
0
4
–
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-2-13-14..
0
5
–
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14..
0
6
–
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15..
0
7
–
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-16..
0
8
–
–
8-9-10-11-12-13-14-15-16-17..
1
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10..
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11..
1
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12..
1
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13..
1
4
4-5-6-7
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14..
1
5
5-6-7-8
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-14..
1
6
6-7-8-9
6-7-8-9-10-11-12-13
6-7-8-9-10-11-12-13-14-15..
1
7
7-8-9-10
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-16..
1
8
8-9-10-11
8-9-10-11-12-13-14-15
8-9-10-11-12-13-14-15-16-17..
20/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 5. Example Burst Configuration X-1-1-1
0
1
2
3
4
5
6
7
8
9
K
ADD
VALID
L
DQ
3-1-1-1
DQ
4-1-1-1
DQ
DQ
DQ
DQ
5-1-1-1
6-1-1-1
7-1-1-1
8-1-1-1
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
AI03841b
21/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. The Commands are summarized in Table
8., Commands. Refer to Table 8 in conjunction
with the text descriptions below.
Read Memory Array Command
The Read Memory Array command returns the
memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command
and return the memory to Read mode. Subsequent read operations will output the addressed
memory array data. Once the command is issued
the memory remains in Read mode until another
command is issued. From Read mode Bus Read
commands will access the memory array.
Read Electronic Signature Command
The Read Electronic Signature command is used
to read the Manufacturer Code, the Device Code,
the Block Protection Configuration Register and
the Burst Configuration Register. One Bus Write
cycle is required to issue the Read Electronic Signature command. Once the command is issued,
subsequent Bus Read operations, depending on
the address specified, read the Manufacturer
Code, the Device Code, the Block Protection Configuration or the Burst Configuration Register until
another command is issued; see Table 9., Read
Electronic Signature.
Read Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area. One Bus Write cycle is required to issue the
Read Query Command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the
Common Flash Interface Memory Area.
Read Status Register Command
The Read Status Register command is used to
read the Status Register. One Bus Write cycle is
required to issue the Read Status Register command. Once the command is issued subsequent
Bus Read operations read the Status Register until another command is issued.
The Status Register information is present on the
output data bus (DQ0-DQ7) when Chip Enable E
and Output Enable G are at VIL and Output Disable is at VIH.
An interactive update of the Status Register bits is
possible by toggling Output Enable or Output Disable. It is also possible during a Program or Erase
operation, by disactivating the device with Chip
Enable at VIH and then reactivating it with Chip Enable and Output Enable at VIL and Output Disable
at VIH.
22/60
The content of the Status Register may also be
read at the completion of a Program, Erase or
Suspend operation. During a Block Erase, Program, Tuning Protection Program or Tuning Protection Unlock command, DQ7 indicates the
Program/Erase Controller status. It is valid until
the operation is completed or suspended.
See the section on the Status Register and Table
11 for details on the definitions of the Status Register bits.
Clear Status Register Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One Bus Write is required to issue the Clear
Status Register command. Once the command is
issued the memory returns to its previous mode,
subsequent Bus Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program, Erase, Block Protect or Block Unprotect
command is issued. If any error occurs then it is
essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or
Resume command.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ‘1’. All
previous data in the block is lost. If the block is protected then the Erase operation will abort, the data
in the block will not be changed and the Status
Register will output the error.
Two Bus Write operations are required to issue the
command; the first write cycle sets up the Block
Erase command, the second write cycle confirms
the Block erase command and latches the block
address in the internal state machine and starts
the Program/Erase Controller. The sequence is
aborted if the Confirm command is not given and
the device will output the Status Register Data with
bits 4 and 5 set to '1'.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Erase operation the memory will only accept the
Read Status Register command and the Program/
Erase Suspend command. All other commands
will be ignored.
The command can be executed using VDD. If VPEN
is at VIH, the operation can be performed. If VPEN
goes below VIH, the operation aborts, the VPEN
Status bit in the Status Register is set to ‘1’ and the
command must be re-issued.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Typical Erase times are given in Table 10.
See Appendix A, Figure 22., Block Erase Flowchart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Erase All Main Blocks Command
The Erase All Main Blocks command is used to
erase all 63 Main Blocks, without affecting the Parameter Blocks.
Issuing the Erase All Main Blocks command sets
every bit in each Main Block to '1'. All data previously stored in the Main Blocks are lost.
Two Bus Write cycles are required to issue the
Erase All Main Blocks command. The first cycle
sets up the command, the second cycle confirms
the command and starts the Program/Erase Controller. If the Confirm Command is not given the
sequence is aborted, and Status Register bits 4
and 5 are set to '1'.
If the address given in the second cycle is located
in a protected block, the Erase All Main Blocks operation aborts. The data remains unchanged in all
blocks and the Status Register outputs the error.
Once the Erase All Main Blocks command has
been issued, subsequent Bus Read operations
output the Status Register. See the STATUS
REGISTER section for details.
During an Erase All Main Blocks operation, only
the Read Status Register command is accepted
by the memory; any other command are ignored.
Erase All Main Blocks, once started, cannot be
suspended.
The Erase All Main Blocks command can be executed using VDD. If VPEN is at VIH, the operation
will be performed. If VPEN is lower than VIH the operation aborts and the Status Register VPEN bit (bit
3) is set to '1'.
Program Command
The Program command is used to program the
memory array. Two Bus Write operations are required to issue the command; the first write cycle
sets up the Program command, the second write
cycle latches the address and data to be programmed and starts the Program/Erase Controller. A program operation can be aborted by writing
FFFFFFFFh to any address after the program setup command has been given.
The Program command is also used to program
the OTP block. Refer to Table 8., Commands, for
details of the address.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Program operation the memory will only accept
the Read Status Register command and the Pro-
gram/Erase Suspend command. All other commands will be ignored.
If Reset/Power-down, RP, falls to VIL during programming the operation will be aborted.
The command can be executed using VDD. If VPEN
is at VIH, the operation can be performed. If VPEN
goes below VIH, the operation aborts, the VPEN
Status bit in the Status Register is set to ‘1’ and the
command must be re-issued.
See Appendix A, Figure 20., Program Flowchart
and Pseudo Code, for a suggested flowchart on
using the Program command.
Write to Buffer and Program Command
The Write to Buffer and Program Command
makes use of the device’s double Word (32 bit)
Write Buffer to speed up programming.
Up to eight Double Words can be loaded into the
Write Buffer and programmed into the memory.
Four successive steps are required to issue thecommand.
1. One Bus Write operation is required to set up
the Write to Buffer and Program Command.
Any Bus Read operations will start to output
the Status Register after the 1st cycle.
2. Use one Bus Write operation to write the
selected memory Block Address (any address
in the block where the values will be
programmed can be used) along with the
value N on the Data Inputs/Outputs, where
N+1 is the number of Words to be
programmed. The maximum value of N+1 is 8
Words.
3. Use N+1 Bus Write operations to load the
address and data for each Word into the Write
Buffer. The address must be between Start
Address and Start Address plus N, where
Start Address is the first word address.
4. Finally, use one Bus Write operation to issue
the final cycle to confirm the command and
start the Program operation.
If any address is outside the block boundaries or if
the correct sequence is not followed, Status Register bits 4 and 5 are set to ‘1’ and the operation will
abort without affecting the data in the memory array. A protected block must be unprotected using
the Blocks Unprotect command.
During a Write to Buffer and Program operation
the memory will only accept the Read Status Register and the Program/Erase Suspend commands.
All other commands are ignored. The Write to
Buffer and Program command can be executed
using VDD. If VPEN is at VIH, the operation will be
performed. If VPEN is lower than VIH the operation
aborts and the Status Register VPEN bit (bit 3) is
set to '1'.
23/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
The Status Register should be cleared before reissuing the command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. The command will only be accepted during a Program or
Erase operation. It can be issued at any time during a program or erase operation. The command
is ignored if the device is already in suspend
mode.
One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will continue to output the Status Register until another
command is issued.
During the polling period between issuing the Program/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the
Program/Erase Suspend command and the Program/Erase Controller pausing see Table 10.
During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended
operation was Erase then the Program, the Write
to Buffer and Program, the Set/Clear Block Protection Configuration Register and the Program Suspend commands will also be accepted. When a
program operation is completed inside a Block
Erase Suspend the Read Memory Array command
must be issued to reset the device in Read mode,
then the Erase Resume command can be issued
to complete the whole sequence. Only the blocks
not being erased may be read or programmed correctly.
See Appendix A, Figure 21., Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
23., Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
24/60
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the Program/Erase Resume command.
See Appendix A, Figure 21., Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
23., Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Set Burst Configuration Register Command.
The Set Burst Configuration Register command is
used to write a new value to the Burst Configuration Register which defines the burst length, type,
X and Y latencies, Synchronous/Asynchronous
Read mode.
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. The first
cycle writes the setup command. The second cycle writes the address where the new Burst Configuration Register content is to be written, and
confirms the command. If the command is not confirmed, the sequence is aborted and the device
outputs the Status Register with bits 4 and 5 set to
‘1’. Once the command is issued the memory returns to Read mode as if a Read Memory Array
command had been issued.
The value for the Burst Configuration Register is
always presented on A0-A15. M0 is on A0, M1 on
A1, etc.; the other address bits are ignored.
Tuning Protection Unlock Command
The Tuning Protection Unlock command unlocks
the tuning protected blocks by writing the 64bit
Tuning Protection Code (M58BW032B only). After
a reset or power-up the blocks are locked and so
a Tuning Protection Unlock command must be issued to allow program or erase operations on tuning protected block or to program a new Tuning
Protection Code. Read operations output the Status Register content after the unlock operation has
started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to unlock the device.
■
The first write cycle issues the Tuning
Protection Unlock Setup command (78h).
■
The second write cycle inputs the first 32 bits
of the tuning protection code on the data bus,
at address 00000h.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal register. If b7 = ‘1’, the device is ready to accept the
second part of the code. This does not mean that
the first 32 bits match the tuning protection code,
simply that it was correctly stored for the comparing. If b7 = ‘0’, the user must wait for this bit setting
(refer to write cycle AC timings).
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
The third write cycle re-issues the Tuning
Protection Unlock Setup command (78h).
■
The fourth write cycle inputs the second 32
bits of the code at address 00001h.
Bit 7 of the Status Register should again be
checked to verify that the device has successfully
stored the second part of the code. When the device is ready (b7 = ‘1’), the tuning protection status
can be monitored on Status Register bit0. If b0 =
‘0’ the device is locked; b0 = ‘1’ the device is unlocked. If the device is still locked a Read Memory
Array command must be issued before re-issuing
the Tuning Protection Unlock command.
Device locked means that the 64 bit password is
wrong. If the unlock operation is attempted using a
wrong code on an already unlocked device, the
device becomes locked. Status register bit 4 is set
to '1' if there has been a verify failure.
Tuning Protection Unlock command aborts if VPEN
drops below VIH or RP goes to VIL.
Once the device is successfully unlocked, a Read
Memory Array command must be issued to return
the memory to read mode before issuing any other
commands. The user can then program or erase
all blocks, depending on WP and VPEN status and
on the protection status of each block. At this
point, it is also possible to configure a new protection code. To write a new protection code into the
device tuning register, the user must perform the
Tuning Protection Program sequence. The device
can be re-locked with a reset or power-down.
See Appendix A, Figure 24, 25 and 26 for suggested flowcharts for using the Tuning Protection Unlock command.
Tuning Protection Program Command.
The Tuning Protection Program command is used
to program a new Tuning Protection Code which
can be configured by the designer of the application (M58BW032B only). The device should be unlocked by the Tuning Protection Unlock command
before issuing the Tuning Protection Program
command.
Read operations output the Status Register content after the program operation has started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to program the code.
■
The first write cycle issues the Tuning
Protection Program Setup command (48h).
■
The second write cycle inputs the first 32 bits
of the new tuning protection code on the data
bus, at address 00000h.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal register. If b7 = ‘1’, the device is ready to accept the
■
second part of the code. If b7 = ‘0’, the user must
wait for this bit setting (refer to write cycle AC timings).
■
The third write cycle re-issues the Tuning
Protection Program Setup command (48h).
■
The fourth write cycle inputs the second 32
bits of the new code at address 00001h.
Bit 7 of the Status Register should again be
checked to verify that the device has successfully
stored the second part of the code. When the device is ready (b7 = ‘1’). After completion Status
Register bit 4 is set to '1' if there has been a program failure.
Programming aborts if VPEN drops below VIH or
RP goes to VIL.
A Read Memory Array command must be issued
to return the memory to read mode before issuing
any other commands. Once the code has been
changed a device reset or power-down will make
the protection active with the new code.
See Appendix A, Figure 24, 25 and 26 for suggested flowcharts for using the Tuning Protection Program command.
Set Block Protection Configuration Register
Command
The Set Block Protection Configuration Register
command is used to configure the Block Protection Configuration Register to ‘Protected’, for a
specific block. Protected blocks are fully protected
from program or erase when WP pin is Low, VIL.
The status of a protected block can be changed to
‘Unprotected’ by using the Clear Block Protection
Configuration Register command. At power-up, all
block are configured as ‘Protected’.
Two bus operations are required to issue a Set
Block Protection Configuration Register command:
■
The first cycle writes the setup command
■
The second write cycle specifies the address
of the block to protect and confirms the
command. If the command is not confirmed,
the sequence is aborted and the device
outputs the Status Register with bits 4 and 5
set to ‘1’.
To protect multiple blocks, the Set Block Protection Configuration Register command must be repeated for each block.
Any attempt to re-protect a block already protected
does not change its status.
Clear Block Protection Configuration Register
Command.
The Clear Block Protection Configuration Register
command is used to configure the Block Protection Configuration Register to ‘Unprotected’, for a
25/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
specific block thus allowing program/erase operations to this block, regardless of the WP pin status.
Two bus operations are required to issue a Clear
Block Protection Configuration Register command:
■
The first cycle writes the setup command
■
The second write cycle specifies the address
of the block to unprotect and confirms the
command. If the command is not confirmed,
the sequence is aborted and the device
outputs the Status Register with bits 4 and 5
set to ‘1’.
To unprotect multiple blocks, the Clear Block Protection Configuration Register command must be
repeated for each block.
Any attempt to unprotect a block already unprotected does not affect its status.
Command
Cycles
Table 8. Commands
Bus Operations
1st Cycle
Op.
2nd Cycle
Addr. Data
Op.
3rd Cycle
Addr. Data
Read Memory Array
≥ 2 Write
X
FFh Read
Read Electronic Signature(2)
≥ 2 Write
X
90h Read IDA(1) IDD(1)
Write
X
70h
≥ 2 Write
X
98h Read
50h
Read Status Register
Read Query
1
RA
RA
RD
1
Write
X
Block Erase
2
Write
55h
20h Write
BA
D0h
Erase All Main Blocks
2
Write
55h
80h Write
AAh
D0h
any block
2
Write
AAh
40h
Write
10h
PA
PD
OTP Block
2
Write
AAh
40h Write
PA
PD
N+4 Write
AAh
E8h Write
BA
N
Write to Buffer and Program
Op. Addr. Data Op. Addr. Data
RD
Clear Status Register
Program
4th Cycle
Write
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Set Burst Configuration
Register
≥3
Write
X
60h Write BCRh
Tuning Protection Program(3)
4
Write
AAh
Tuning Protection Unlock(3)
4
Write
X
78h Write TPAh TPCh Write
Set Block Protection
Configuration Register
2
Write
X
60h Write
BA
01h
Clear Block Protection
Configuration Register
2
Write
X
60h Write
BA
D0h
03h
PA
Read RA
PD Write
X
D0h
RD
48h Write TPAh TPCh Write AAh 48h Write TPAh TPCh
X
78h Write TPAh TPCh
Note: 1. X Don’t Care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status Register
Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register value, TPA = Tuning Protection Address, TPC = Tuning Protection Code, N+1 number of Words to program, BA
Block address.
2. The Manufacturer Code, the Device Code, the Burst Configuration Register, and the Block Protection Configuration Register of
each block are read using the Read Electronic Signature command.
3. Cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code.
26/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 9. Read Electronic Signature
Code
Device
A19-A0
DQ31-DQ0
Manufacturer
All
00000h
00000020h
M58BW032xT(1)
00001h
00008838h
M58BW032xB(1)
00001h
00008837h
00005h
BCR(2)
Device
Burst Configuration
Register
Block Protection
Configuration Register
00000000h (Unprotected)
SBA+02h(3)
All
00000001h (Protected)
Note: 1. x= B or D version of the device.
2. BCR= Burst Configuration Register.
3. SBA is the start address of each block.
Table 10. Program, Erase Times and Program Erase Endurance Cycles
M58BW032B/D
Parameters
Unit
Min
Typ
Max
15
20
s
TBD
TBD
µs
512 Kbit Block Erase
1
2
s
256 Kbit Block Erase
0.8
1.6
s
64 Kbit Block Erase
0.6
1.2
s
Program Suspend Latency Time
3
10
µs
Erase Suspend Latency Time
10
30
µs
100,000
cycles
Full Chip Program
Double Word Program
Program/Erase Cycles (per Block)
Note: TA = –40 to 125°C, VDD = 3.0V to 3.6V, VDDQ = 1.6V to VDD
27/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Tuning Protection operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Register command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Program/Erase Resume commands. The
Status Register can be read from any address.
The contents of the Status Register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or
by dis-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, VIL, and
Output Disable, VIH.) the device.
The Status Register bits are summarized in Table
11., Status Register Bits. Refer to Table 11 in conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7)
The Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Status bit is set to ‘0’, the Program/Erase Controller is
active; when bit7 is set to ‘1’, the Program/Erase
Controller is inactive.
The Program/Erase Controller Status is set to ‘0’
immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller pauses the bit is set to ‘1’.
During Program and Erase operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Program/Erase Controller completes the operation
and the bit is set to ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status (bit5), Program/Tuning
Protection Unlock status (bit4) bits should be tested for errors.
Erase Suspend Status (Bit 6)
The Erase Suspend Status bit indicates that an
Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status
should only be considered valid when the Program/Erase Controller Status bit is set to ‘1’ (Program/Erase Controller inactive); after a Program/
Erase Suspend command is issued the memory
may still complete the operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is set to ‘0’,
the Program/Erase Controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued
28/60
and the memory is waiting for a Program/Erase
Resume command.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5)
The Erase Status bit can be used to identify if the
memory has failed to verify that the block has
erased correctly. The Erase Status bit should be
read once the Program/Erase Controller Status bit
is High (Program/Erase Controller inactive).
When the Erase Status bit is set to ‘0’, the memory
has successfully verified that the block has erased
correctly. When the Erase Status bit is set to ‘1’,
the Program/Erase Controller has applied the
maximum number of pulses to the block and still
failed to verify that the block has erased correctly.
Once set to ‘1’, the Erase Status bit can only be reset to ‘0’ by a Clear Status Register command or a
hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program/ Write to Buffer and Program/Tuning
Protection Unlock Status (Bit 4)
The Program/Write to Buffer and Program/Tuning
Protection Unlock Status bit is used to identify a
Program failure, a Write to Buffer and Program
failure or a Tuning Protection Code verify failure.
Bit4 should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller
inactive).
When bit4 is set to ‘0’ the memory has successfully verified that the device has programmed correctly or that the correct Tuning Protection Code
has been written. When bit4 is set to ‘1’ the device
has failed to verify that the data has been programmed correctly or that the correct Tuning Protection code has been written.
Once set to 1’, the Program Status bit can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
VPEN Status (Bit 3). The VPEN Status bit can be
used to identify if a program or erase operation
has been attempted when VPEN is Low, VIL.
When Bit 3 is set to ‘0’ no program or erase operations have been attempted with VPEN Low, VIL,
since the last Clear Status Register command, or
hardware reset.
When Bit 3 is set to ‘1’ a program or erase operation has been attempted with VPEN Low, VIL.
Once set to ‘1’, Bit 3 can only be reset by an Clear
Status Register command or a hardware reset. If
set to ‘1’ it should be reset before a new program
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
or erase command is issued, otherwise the new
command will appear to fail.
Program Suspend Status (Bit 2)
The Program Suspend Status bit indicates that a
Program operation has been suspended and is
waiting to be resumed. The Program Suspend
Status should only be considered valid when the
Program/Erase Controller Status bit is set to ‘1’
(Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the
memory may still complete the operation rather
than entering the Suspend mode.
When the Program Suspend Status bit is set to ‘0’,
the Program/Erase Controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued
and the memory is waiting for a Program/Erase
Resume command.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1)
The Block Protection Status bit can be used to
identify if a Program or Erase operation has tried
to modify the contents of a protected block.
When the Block Protection Status bit is set to ‘0’,
no Program or Erase operations have been attempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is set to ‘1’, a
Program or Erase operation has been attempted
on a protected block.
Once set to ‘1’, the Block Protection Status bit can
only be reset Low by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Tuning Protection Status (Bit 0)
The Tuning Protection Status bit indicates if the
device is locked (Tuning Protection is enabled) or
unlocked (Tuning Protection is disabled).
When the Tuning Protection Status bit is set to ‘0’
the device is locked, when it is set to ‘1’ the device
is unlocked. After a reset or power-up the device is
locked and so bit0 is set to ‘0’.
The Tuning Protection Status bit is set to ‘1’ for the
M58BW032D version.
Table 11. Status Register Bits
Bit
Name
7
Logic Level
Definition
’1’
Ready
’0’
Busy
’1’
Suspended
’0’
In Progress or Completed
’1’
Erase Error
’0’
Erase Success
’1’
Program Error
’0’
Program Success
‘0’
no program or erase attempted
‘1’
program or erase attempted
’1’
Suspended
’0’
In Progress or Completed
’1’
program/erase on protected block,
abort
’0’
No operations to protected blocks
’1’
Tuning Protection Disabled(1)
’0’
Tuning Protection Enabled
Program/Erase Controller Status
6
Erase Suspend Status
5
Erase Status
4
Program Status,
Tuning Protection Unlock Status
3
VPEN Status bit
2
Program Suspend Status
1
Erase/Program in a Protected
Block
0
Tuning Protection Status
Note: 1. For the M58BW032D version the Tuning Protection Status bit is always set to ‘1’.
29/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
MAXIMUM RATING
Stressing the device above the ratings listed in Table 12., Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 12. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
Temperature Under Bias
–40
125
°C
TSTG
Storage Temperature
–55
155
°C
TLEAD
Lead Temperature during Soldering(1)
TBD
°C
VIO
VDD, VDDQ, VDDQIN
Input or Output Voltage
–0.6
VDDQ +0.6
VDDQIN +0.6
V
Supply Voltage
–0.6
4.2
V
Note: 1. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes.
30/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment
Conditions
summarized
in
Table
13., Operating and AC Measurement Conditions.
Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 13. Operating and AC Measurement Conditions
Value
Parameter
Units
Min
Max
Supply Voltage (VDD)
3.0
3.6
V
Input/Output Supply Voltage (VDDQ)
2.4
3.6
V
Grade 6
–40
90
°C
Grade 3
–40
125
°C
Ambient Temperature (TA)
Load Capacitance (CL)
30
pF
Clock Rise and Fall Times
3
ns
Input Rise and Fall Times
3
ns
Input Pulses Voltages
Input and Output Timing Ref. Voltages
Figure 6. AC Measurement Input Output
Waveform
VDDQ
VDDQIN
0 to VDDQ
V
VDDQ/2
V
Figure 7. AC Measurement Load Circuit
VDDQ/2
VDDQIN/2
DEVICE
UNDER
TEST
OUT
CL
0V
AI04153
CL includes JIG capacitance
AI04154b
Note: VDD = VDDQ.
Table 14. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Typ
Max
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
Note: 1. TA = 25°C, f = 1 MHz
2. Sampled only, not 100% tested.
31/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 15. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V≤ VIN ≤ VDDQ
±1
µA
ILO
Output Leakage Current
0V≤ VOUT ≤VDDQ
±5
µA
E = VIL, G = VIH, fadd = 6MHz
50
mA
E = VIL, G = VIH, fclock =
75MHz
50
mA
E = RP = VDD ± 0.2V
100
µA
Program, Erase in progress
30
mA
E = VIH
40
µA
–0.5
0.2VDDQIN
V
IDD(1)
Supply Current (Random Read)
IDDB(1)
Supply Current (Burst Read)
IDD1(1)
Supply Current (Standby)
IDD2(1)
Supply Current (Program or Erase)
IDD3(1)
Supply Current
(Erase/Program Suspend)
VIL
Input Low Voltage
VIH
Input High Voltage (for DQ lines)
0.8VDDQIN
VDDQ +0.3
V
VIH
Input High Voltage (for Input only
lines)
0.8VDDQIN
3.6
V
VOL
Output Low Voltage
0.1
V
VOH
Output High Voltage CMOS
VLKO
VDD Supply Voltage (Erase and
Program lockout)
IOL = 100µA
IOH = –100µA
VDDQ –0.1
V
2.2
Note: 1. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to ‘1’.
32/60
V
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 8. Asynchronous Bus Read AC Waveforms
tAVAV
A0-A19
VALID
tAVQV
tEHLX
tLLEL
L
tELQX
tELQV
tAXQX
E
tGLQX
tGLQV
tEHQX
tEHQZ
G
GD
tGHQX
tGHQZ
DQ0-DQ31
OUTPUT
See also Page Read
AI08921
Table 16. Asynchronous Bus Read AC Characteristics.
M58BW032
Symbol
Parameter
Test Condition
Unit
45
55
60
tAVAV
Address Valid to Address Valid
E = VIL, G = VIL
Min
45
55
60
ns
tAVQV
Address Valid to Output Valid
E = VIL, G = VIL
Max
45
55
60
ns
tAXQX
Address Transition to Output Transition
E = VIL, G = VIL
Min
0
ns
tEHLX
Chip Enable High to Latch Enable Transition
Min
0
ns
tEHQX
Chip Enable High to Output Transition
G = VIL
Min
0
ns
tEHQZ
Chip Enable High to Output Hi-Z
G = VIL
Max
20
ns
tELQV(1)
Chip Enable Low to Output Valid
G = VIL
Max
45
tELQX
Chip Enable Low to Output Transition
G = VIL
Min
0
ns
tGHQX
Output Enable High to Output Transition
E = VIL
Min
0
ns
tGHQZ
Output Enable High to Output Hi-Z
E = VIL
Max
15
ns
tGLQV
Output Enable Low to Output Valid
E = VIL
Max
15
ns
tGLQX
Output Enable to Output Transition
E = VIL
Min
0
ns
tLLEL
Latch Enable Low to Chip Enable Low
Min
0
ns
55
60
ns
Note: 1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV.
33/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms
A0-A19
VALID
tAVLL
L
tLHAX
tLHLL
tLLLH
tEHLX
tELLL
E
tEHQX
tEHQZ
tGLQX
tGLQV
G
tLLQX
tLLQV
tGHQX
GHQZ
DQ0-DQ31
OUTPUT
See also Page Read
AI08922
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
Unit
45
55
60
Min
0
0
0
ns
Min
0
0
0
ns
tAVLL
Address Valid to Latch Enable Low
tEHLX
Chip Enable High to Latch Enable Transition
tEHQX
Chip Enable High to Output Transition
G = VIL
Min
0
0
0
ns
tEHQZ
Chip Enable High to Output Hi-Z
G = VIL
Max
20
20
20
ns
tELLL
Chip Enable Low to Latch Enable Low
Min
0
0
0
ns
tGHQX
Output Enable High to Output Transition
E = VIL
Min
0
0
0
ns
tGHQZ
Output Enable High to Output Hi-Z
E = VIL
Max
15
15
15
ns
tGLQV
Output Enable Low to Output Valid
E = VIL
Max
15
25
25
ns
tGLQX
Output Enable Low to Output Transition
E = VIL
Min
0
0
0
ns
tLHAX
Latch Enable High to Address Transition
E = VIL
Min
5
5
5
ns
tLHLL
Latch Enable High to Latch Enable Low
Min
10
10
10
ns
tLLLH
Latch Enable Low to Latch Enable High
E = VIL
Min
10
10
10
ns
tLLQV
Latch Enable Low to Output Valid
E = VIL, G = VIL
Max
45
55
60
ns
tLLQX
Latch Enable Low to Output Transition
E = VIL, G = VIL
Min
0
0
0
ns
34/60
E = VIL
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 10. Asynchronous Page Read AC Waveforms
A0-A1
A0 and/or A1
tAVQV1
tAXQX
OUTPUT + 1
OUTPUT
DQ0-DQ31
AI03646
Table 18. Asynchronous Page Read AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
Unit
45
55
60
tAVQV1
Address Valid to Output Valid
E = VIL, G = VIL
Max
25
25
25
ns
tAXQX
Address Transition to Output Transition
E = VIL, G = VIL
Min
6
6
6
ns
Note: For other timings see Table 16., Asynchronous Bus Read AC Characteristics..
35/60
36/60
RP
VPEN
DQ0-DQ31
W
G
E=L
A0-A19
tAVLL
tWHEH
INPUT
tDVWH
tWHDX
tWHWL
tWHAX
tWLWH
Write Cycle
tELWL
tAVWH
VALID
INPUT
RP = VHH
Write Cycle
tPHWH
tVPHWH
VALID
tWHQV
tWHGL
VALID
Read Status Register
RP = VDD
tQVPL
tQVVPL
VALID SR
AI08923b
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 11. Asynchronous Write AC Waveform
RP
VPEN
DQ0-DQ31
W
G
E
L
A0-A19
tAVLL
tLLLH
tWHDX
Write Cycle
tWLWH
tELWL
tAVWH
tLHAX
INPUT
tLLWH
tELLL
tAVLH
VALID
tDVWH
tVPHWH
tWHWL
tWHEH
tWHAX
VALID
Write Cycle
RP = VHH
INPUT
tWHQV
tWHGL
VALID
Read Status Register
AI08924b
RP = VDD
tQVPL
tQVVPL
VALID SR
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 12. Asynchronous Latch Controlled Write AC Waveform
37/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
Unit
45
55
60
Min
0
0
0
ns
tAVLL
Address Valid to Latch Enable Low
tAVWH
Address Valid to Write Enable High
E = VIL
Min
25
25
25
ns
tDVWH
Data Input Valid to Write Enable High
E = VIL
Min
25
25
25
ns
tELLL
Chip Enable Low to Latch Enable Low
Min
0
0
0
ns
tELWL
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tLHAX
Latch Enable High to Address Transition
Min
5
5
5
ns
tLLLH
Latch Enable Low to Latch Enable High
Min
10
10
10
ns
tLLWH
latch Enable Low to Write Enable High
Min
25
25
25
ns
tQVVPL
Output Valid to VPEN Low
Min
0
0
0
ns
tVPHWH
VPEN High to Write Enable High
Min
0
0
0
ns
tWHAX
Write Enable High to Address Transition
E = VIL
Min
0
0
0
ns
tWHDX
Write Enable High to Input Transition
E = VIL
Min
0
0
0
ns
tWHEH
Write Enable High to Chip Enable High
Min
0
0
0
ns
tWHGL
Write Enable High to Output Enable Low
Min
150
150
150
ns
tWHQV
Write Enable High to Output Valid
Min
175
175
175
ns
tWHWL
Write Enable High to Write Enable Low
Min
20
20
20
ns
tWLWH
Write Enable Low to Write Enable High
Min
25
25
25
ns
tQVPL
Output Valid to Reset/Power-down Low
Min
0
0
0
ns
38/60
E = VIL
E = VIL
DQ0-DQ31
G
E
L
A0-A19
K
VALID
tELLL
tAVLL
1
Note: n depends on Burst X-Latency.
tLLKH
tKHLL
0
tKHLX
tKHAX
Setup
tAVQV
tKHQV
tGLQV
n
OUTPUT
n+1
n+2
AI08925b
tGHQX
tGHQZ
tEHQX
tEHQZ
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 13. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)
39/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 20. Synchronous Burst Read AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
tAVLL
Address Valid to Latch Enable Low
tBHKH
Unit
45
55
60
E = VIL
Min
0
0
0
ns
Burst Address Advance High to Valid Clock
Edge
E = VIL, G = VIL,
L = VIH
Min
8
8
8
ns
tBLKH
Burst Address Advance Low to Valid Clock
Edge
E = VIL, G = VIL,
L = VIH
Min
8
8
8
ns
tELLL
Chip Enable Low to Latch Enable low
Min
0
0
0
ns
tGLQV
Output Enable Low to Output Valid
E = VIL, L = VIH
Min
10
10
10
ns
tKHAX
Valid Clock Edge to Address Transition
E = VIL
Min
5
5
5
ns
tKHLL
Valid Clock Edge to Latch Enable Low
E = VIL
Min
0
0
0
ns
tKHLX
Valid Clock Edge to Latch Enable Transition
E = VIL
Min
0
0
0
ns
tKHQX
Valid Clock Edge to Output Transition
E = VIL, G = VIL,
L = VIH
Min
0
0
0
ns
tLLKH
Latch Enable Low to Valid Clock Edge
E = VIL
Min
6
6
6
ns
tRLKH
Valid Data Ready Low to Valid Clock Edge
E = VIL, G = VIL,
L = VIH
Min
6
6
6
ns
tKHQV
Valid Clock Edge to Output Valid
E = VIL, G = VIL,
L = VIH
Max
8
8
8
ns
Note: 1. Data output should be read on the valid clock edge.
2. For other timings see Table 16., Asynchronous Bus Read AC Characteristics..
Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)
n
n+1
n+2
n+3
n+4
n+5
K
tKHQV
Q0
DQ0-DQ31
Q1
Q2
Q3
Q4
Q5
tKHQX
SETUP
Burst Read
Q0 to Q3
Note: n depends on Burst X-Latency
AI04408c
Note: For set up signals and timings see Synchronous Burst Read.
40/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 15. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
Output (1)
V
V
V
V
V
tRLKH
R
(2)
AI03649b
Note: Valid Data Ready = Valid Low during valid clock edge
1. V= Valid output.
2. The internal timing of R follows DQ.
Figure 16. Synchronous Burst Read - Burst Address Advance
K
A0-A19
VALID
L
DQ0-DQ31
Q0
Q1
Q2
tGLQV
G
tBLKH
tBHKH
B
AI03650
41/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 17. Reset, Power-Down and Power-up AC Waveform
W, E, G
tPHWL
tPHEL
tPHGL
tPLRH
R
tPHWL
tPHEL
tPHGL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI03849b
Table 21. Reset, Power-Down and Power-up AC Characteristics
Symbol
tPHEL
tPHQV (1)
Parameter
Reset/Power-down High to Chip Enable Low
Max
50
Reset/Power-down High to Output Valid
Unit
ns
130
ns
tPHWL
Reset/Power-down High to Write Enable Low
50
ns
tPHGL
Reset/Power-down High to Output Enable Low
50
ns
tPLPH
Reset/Power-down Low to Reset/Power-down High
100
ns
tPLRH
Reset/Power-down Low to Valid Data Ready High
2
tVDHPH
Supply Voltages High to Reset/Power-down High
10
Note: 1. This time is tPHEL + tAVQV or tPHEL + tELQV.
42/60
Min
30
µs
µs
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PACKAGE MECHANICAL
Figure 18. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z05
Note: Drawing is not to scale.
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.700
A1
0.400
0.350
0.450
A2
1.100
b
0.500
–
–
D
10.000
–
D1
7.000
–
Max
0.0669
0.0157
0.0138
0.0177
0.0197
–
–
–
0.3937
–
–
–
0.2756
–
–
0.0433
ddd
0.150
0.0059
E
12.000
–
–
0.4724
–
–
E1
9.000
–
–
0.3543
–
–
e
1.000
–
–
0.0394
–
–
FD
1.500
–
–
0.0591
–
–
FE
1.500
–
–
0.0591
–
–
SD
0.500
–
–
0.0197
–
–
SE
0.500
–
–
0.0197
–
–
43/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
Ne
A2
N
1
e
D2 D1 D
Nd
b
E2
A
E1
CP
L1
E
c
A1
QFP-B
α
L
Note: Drawing is not to scale.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data
Symbol
millimeters
Typ
Min
A
Typ
Min
0.250
2.800
Max
0.1339
0.0098
2.550
3.050
b
0.300
0.450
0.0118
0.0177
c
0.130
0.230
0.0051
0.0091
0.1102
0.1004
0.1201
D
23.200
22.950
23.450
0.9134
0.9035
0.9232
D1
20.000
19.900
20.100
0.7874
0.7835
0.7913
D2
18.400
–
–
0.7244
–
–
e
0.800
–
–
0.0315
–
–
E
17.200
16.950
17.450
0.6772
0.6673
0.6870
E1
14.000
13.900
14.100
0.5512
0.5472
0.5551
E2
12.000
–
–
0.4724
–
–
L
0.800
0.650
0.950
0.0315
0.0256
0.0374
L1
1.600
–
–
0.0630
–
–
0°
7°
0°
7°
α
44/60
Max
3.400
A1
A2
inches
N
80
80
Nd
24
24
Ne
16
16
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PART NUMBERING
Table 24. Ordering Information Scheme
Example:
M58BW032B
T
45
T
3
T
Device Type
M58
Architecture
B = Burst Mode
Operating Voltage
W = VDD = 3.0V to 3.6V; VDDQ = VDDQIN =1.6 to VDD
Device Function
032B = 32 Mbit (x32), Boot Block, Burst Tuning Protection
032D = 32 Mbit (x32), Boot Block, Burst no Tuning Protection
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45ns
55 = 55ns
60 = 60ns
Package
T = PQFP80
ZA = LBGA80: 1.0mm pitch
Temperature Range
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
45/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
APPENDIX A. FLOW CHARTS
Figure 20. Program Flowchart and Pseudo Code
Start
Program Command:
– write 40h, Address AAh
– write Address & Data
(memory enters read status
state after the Program command)
Write 40h
Write Address
& Data
Read Status
Register
b7 = 1
do:
– read status register
(E or G must be toggled)
NO
while b7 = 1
YES
b3 = 0
NO
VPEN Invalid
Error (1)
NO
Program
Error (1)
NO
Program to Protect
Block Error
If b3 = 1, VPEN invalid error:
– error handler
YES
b4 = 0
If b4 = 1, Program error:
– error handler
YES
b1 = 0
If b1 = 1, Program to Protected Block Error:
– error handler
YES
End
AI03850d
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
46/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
– read status register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b2 = 1
NO
Program Complete
If b2 = 0, Program completed
YES
Read Memory Array Command:
– write FFh
– one or more data reads
from other blocks
Write FFh
Read data from
another block
Write D0h
Write FFh
Program Continues
Read Data
Program Erase Resume Command:
– write D0h
to resume programming
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
AI00612b
47/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 22. Block Erase Flowchart and Pseudo Code
Start
Erase Command:
– write 20h, Address 55h
– write Block Address
(A11-A19) & D0h
(memory enters read status
state after the Erase command)
Write 20h
Write Block Address
& D0h
NO
Read Status
Register
Suspend
b7 = 1
YES
NO
Suspend
Loop
do:
– read status register
(E or G must be toggled)
if Erase command given execute
suspend erase loop
while b7 = 1
YES
b3 = 0
NO
VPEN Invalid
Error (1)
YES
Command
Sequence Error
NO
Erase
Error (1)
NO
Erase to Protected
Block Error
If b3 = 1, VPEN invalid error:
– error handler
YES
b4 and b5
=1
If b4, b5 = 1, Command Sequence error:
– error handler
NO
b5 = 0
If b5 = 1, Erase error:
– error handler
YES
b1 = 0
If b1 = 1, Erase to Protected Block Error:
– error handler
YES
End
AI08623c
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
48/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
– read status register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b6 = 1
NO
Erase Complete
If b6 = 0, Erase completed
YES
Read Memory Array command:
– write FFh
– one or more data reads
from other blocks
Write FFh
Read data from
another block
or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command:
– write D0h to resume the Erase
operation
– if the Erase operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
AI00615b
49/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 24. Unlock Device and Change Tuning Protection Code Flowchart
Reset
Device locked
by tuning code
Add: don't care
Data: FFh
Add: don't care
Data: FFh
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 78h
1st: Write Cycle
Add: 00000h
Data: First 32 bit
2nd: Write Cycle
(old code,
factory setup = FFFFh)
b7 = 1
Issue
Read
command
Add: 00001h
Data: Second 32 bit
3rd: Write Cycle
4th: Write Cycle
(old code,
factory setup = FFFFh)
YES
NO
6th: Write Cycle
Add: 00000h
Data: First 32 bit
7th: Write Cycle
(new code)
YES
b7 = 1
DEVICE LOCKED
Add: AAh
Data: 48h
b7 = 1
YES
Add: don't care
Data: 78h
Issue Read command
5th: Write Cycle
Add: AAh
Data: 48h
8th: Write Cycle
Add: 00001h
Data: Second 32 bit
9th: Write Cycle
(new code)
b7 = 1
YES
Read Status
Register
Reset
b0 = 1
Device locked
by new code
YES
DEVICE UNLOCKED
AI04501b
50/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 25. Unlock Device and Program a Tuning Protected Block Flowchart
Reset
Device locked
by tuning code
Add: don't care
Data: FFh
Add: don't care
Data: FFh
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 78h
1st: Write Cycle
Add: 00000h
Data: First 32 bit
2nd: Write Cycle
(First part
of the tuning code)
Add: 00001h
Data: Second 32 bit
6th: Write Cycle
Add: location to prog. 7th: Write Cycle
Data: data to prog.
YES
YES
Add: don't care
Data: 78h
Add: AAh
Data: 40h
b7 = 1
b7 = 1
Issue
Read
command
Issue Read command
5th: Write Cycle
3rd: Write Cycle
4th: Write Cycle
(Second part
of the tuning code)
Status Register
check
Location
programmed
b7 = 1
YES
Read Status
Register
NO
DEVICE LOCKED
b0 = 1
YES
DEVICE UNLOCKED
AI04502b
51/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 26. Unlock Device and Erase a Tuning Protected Block Flowchart
Reset
Device locked
by tuning code
Add: don't care
Data: FFh
Add: don't care
Data: FFh
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 78h
1st: Write Cycle
Add: 00000h
Data: First 32 bit
2nd: Write Cycle
(First part
of the tuning code)
Add: 00001h
Data: Second 32 bit
6th: Write Cycle
Add: block to erase
Data: D0h
7th: Write Cycle
YES
YES
Add: don't care
Data: 78h
Add: 55h
Data: 20h
b7 = 1
b7 = 1
Issue
Read
command
Issue Read command
5th: Write Cycle
3rd: Write Cycle
4th: Write Cycle
(Second part
of the tuning code)
Status Register
check
Block
Erased
b7 = 1
YES
Read Status
Register
NO
DEVICE LOCKED
b0 = 1
YES
DEVICE UNLOCKED
AI04503b
52/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 27. Power-up Sequence to Burst the Flash
Power-up
or Reset
Asynchronous Read
Write 60h command
BCR bit 15 = '1'
Set Burst Configuration Register Command:
– write 60h
– write 03h
and BCR on A15-A0
Write 03h with A15-A0
BCR inputs
Synchronous Read
BCR bit 15 = '0'
BCR bit 14-bit 0 = '1'
AI03834
53/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 28. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE
90h
READ
ARRAY
NO
YES
READ ELEC.
SIGNATURE
98h
NO
D
YES
READ CFI
70h
NO
YES
READ
STATUS
20h
NO
YES
ERASE
SET-UP
40h
NO
YES
ERASE
COMMAND
ERROR
NO
D0h
PROGRAM
SET-UP
50h
YES
A
YES
C
NO
E
CLEAR
STATUS
D
READ
STATUS
B
AI03835
54/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 29. Command Interface and Program Erase Controller Flowchart (b)
E
48h
NO
YES
TP
PROGRAM
SET_UP
78h
NO
YES
F
TP
UNLOCK
SET_UP
60h
NO
YES
FFh
G
SET BCR
SET_UP
03h
NO
YES
NO
YES
D
AI03836
55/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 30. Command Interface and Program Erase Controller Flowchart (c)
A
B
ERASE
YES
READY
NO
NO
B0h
READ
STATUS
YES
ERASE
SUSPEND
YES
READY
NO
NO
ERASE
SUSPENDED
READ
STATUS
YES
READ
STATUS
YES
70h
NO
40h
YES
PROGRAM
SET_UP
NO
READ
ARRAY
NO
D0h
C
YES
READ
STATUS
AI03837
56/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 31. Command Interface and Program Erase Controller Flowchart (d)
C
B
PROGRAM
YES
READY
NO
B0h
NO
READ
STATUS
YES
PROGRAM
SUSPEND
YES
READY
NO
NO
PROGRAM
SUSPENDED
READ
STATUS
YES
READ
STATUS
YES
70h
NO
READ
ARRAY
NO
D0h
YES
READ
STATUS
AI03838
57/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 32. Command Interface and Program Erase Controller Flowchart (e)
F
B
TP
PROGRAM
YES
READY
NO
READ
STATUS
NO
READ
STATUS
G
B
TP
UNLOCK
YES
READY
AI03839
58/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
REVISION HISTORY
Table 25. Document Revision History
Date
Version
Revision Details
20-Oct-2003
1.0
First Issue.
21-Oct-2003
1.1
Figure 7, AC Measurement Load Circuit modified. IDDB test condition updated in
Table 5, DC Characteristics.
20-Nov-2003
1.2
Bit M3 no longer reserved, described in Burst Configuration Register section. Minor
text changes. Program and Erase Suspend Latency Times added to Table Table
10., Program, Erase Times and Program Erase Endurance Cycles.
27-Apr-2004
2.0
A19 added in Figure 4.PQFP Connections (Top view through package).
Table 6.Burst Configuration Register, Note 1 updated.
30-July-2004
3.0
DQ8-DQ15 and R signal names updated in Table 1., Signal Names.
Description of Valid Data Ready (R).signal updated.
Burst Length Bit (M2-M0).paragraph updated in Burst Configuration Register section.
X-Latency of 8 clock cycles added in Table 6., Burst Configuration Register
COMMAND INTERFACE section: Erase All Main Blocks command added, Read
Electronic Signature Command, Read Status Register Command, Write to Buffer
and Program Command, Set Block Protection Configuration Register Command and
Clear Block Protection Configuration Register Command. updated.
Erase All Main Blocks command added, Write to Buffer and Program, Set Burst
Configuration Register, Set and Clear Block Protection commands updated in Table
8., Commands.
Standby Status removed from Table 9., Read Electronic Signature.
Definition of bit 4 updated in STATUS REGISTER section.
tQVKH removed from Figure 13., Synchronous Burst Read (Data Valid from ’n’
Clock Rising Edge).
05-Nov-2004
4.0
Datasheet status changed to Preliminary Data.
59/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
60/60