M58MR064C M58MR064D 64 Mbit (4Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory ■ SUPPLY VOLTAGE – VDD = VDDQ = 1.65V to 2.0V for Program, Erase and Read ■ – VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA ■ SYNCHRONOUS / ASYNCHRONOUS READ FBGA – Burst mode Read: 54MHz TFBGA48 (ZC) 10 x 4 ball array – Page mode Read (4 Words Page) – Random Access: 100ns ■ PROGRAMMING TIME – 10µs by Word typical – Two or four words programming option ■ MEMORY BLOCKS – Dual Bank Memory Array: 16/48 Mbit Figure 1. Logic Diagram – Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS – Read within one Bank while Program or Erase within the other VDD VDDQ VPP – No delay between Read and Write operations ■ 6 PROTECTION/SECURITY – All Blocks protected at Power-up A16-A21 – Any combination of Blocks can be protected W – 64 bit unique device identifier E – 64 bit user programmable OTP cells – One parameter block permanently lockable ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK ■ ELECTRONIC SIGNATURE 16 G ADQ0-ADQ15 WAIT M58MR064C M58MR064D RP BINV WP L K – Manufacturer Code: 20h – Top Device Code, M58MR064C: 88DCh – Bottom Device Code, M58MR064D: 88DDh VSS AI90087 March 2002 1/52 M58MR064C, M58MR064D Figure 2. TFBGA Connections (Top view through package) 1 A 2 3 4 5 6 7 8 9 10 11 12 DU DU C WAIT A21 VSS K VDD W VPP A19 A17 NC D VDDQ A16 A20 L BINV RP WP A18 E VSS E VSS ADQ7 ADQ6 ADQ13 ADQ12 ADQ3 ADQ2 ADQ9 ADQ8 G F ADQ15 ADQ14 VSS ADQ5 ADQ4 ADQ11 ADQ10 VDDQ ADQ1 ADQ0 DU G 14 DU DU B H 13 DU DU DU AI90088 DESCRIPTION The M58MR064 is a 64 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-byWord basis using a 1.65V to 2.0V VDD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports synchronous burst read and asynchronous read from all the blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at each clock cycle for frequencies up to 54MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up. Blocks can be unprotected to make changes in the application and then re-protected. A parameter block "Security block" can be permanently protected against programming and erasing 2/52 in order to increase the data security. An optional 12V VPP power supply is provided to speed up the program phase at costumer production. An internal command interface (C.I.) decodes the instructions to access/modify the memory content. The program/erase controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Two status registers indicate the state of each bank. Instructions for Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Write Read Configuration Register, Program, Block Erase, Bank Erase, Program Suspend, Program Resume, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, Protection Program, CFI Query, are written to the memory through a Command Interface (C.I.) using standard micro-processor write timings. The memory is offered in TFBGA48, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to ’1’). M58MR064C, M58MR064D Table 1. Signal Names A16-A21 Address Inputs ADQ0-ADQ15 Data Input/Outputs or Address Inputs, Command Inputs E Chip Enable G Output Enable W Write Enable RP Reset/Power-down WP Write Protect K Burst Clock L Latch Enable WAIT Wait Data in Burst Mode BINV Bus Invert VDD Supply Voltage VDDQ Supply Voltage for Input/Output Buffers VPP Optional Supply Voltage for Fast Program & Erase VSS Ground DU Don’t Use as Internally Connected NC Not Connected Internally Organization The M58MR064 is organized as 4Mb by 16 bits. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A21 are the MSB addresses. Chip Enable E, Output Enable G and Write Enable W inputs provide memory control. The clock K input synchronizes the memory to the microprocessor during burst read. Reset RP is used to reset all the memory circuitry and to set the chip in power-down mode if a proper setting of the Read Configuration Register enables this function. WAIT output indicates to the microprocessor the status of the memory during the burst mode operations. Memory Blocks The device features asymmetrically blocked architecture. M58MR064 has an array of 135 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. Only one bank at the time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The memory features an erase suspend allowing reading or programming in another block. Once suspended the erase can be resumed. Program can be suspended to read data in another block and then resumed. The Bank Size and sectorization are summarized in Table 3. Parameter Blocks are located at the top of the memory address space for the M58MR064C, and at the bottom for the M58MR064D. The memory maps are shown in Figure 3. Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature (2) –40 to 85 °C TBIAS Temperature Under Bias –40 to 125 °C TSTG Storage Temperature –55 to 155 °C VIO (3) Input or Output Voltage –0.5 to VDDQ+0.5 V Supply Voltage –0.5 to 2.7 V Program Voltage –0.5 to 13 V TA VDD, VDDQ VPP Parameter Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. 3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. 3/52 M58MR064C, M58MR064D The architecture includes a 128 bits Protection register that is divided into two 64-bits segments. In the first one is written a unique device number, while the second one is programmable by the user. The user programmable segment can be permanently protected programming the bit 1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected by the user programming the bit 2 of the Protection Lock Register. Block protection against Program or Erase provides additional data security. All blocks are protected and unlocked at Power-up. Instructions are provided to protect or un-protect any block in the application. A second register locks the protection status while WP is low (see Block Locking description). Table 3. Bank Size and Sectorization Bank Size Parameter Blocks Main Blocks Bank A 16 Mbit 8 blocks of 4 KWord 31 blocks of 32 KWord Bank B 48 Mbit - 96 blocks of 32 KWord Figure 3. Memory Map Top Boot Block Address lines A21-A0 000000h 007FFFh Bottom Boot Block Address lines A21-A0 000000h 512 Kbit or 32 KWord 000FFFh 64 Kbit or 4 KWord Total of 96 Main Blocks Bank B 2F8000h 2FFFFFh 300000h 307FFFh Total of 8 Parameter Blocks 007000h 512 Kbit or 32 KWord Bank A 512 Kbit or 32 KWord 007FFFh 008000h 00FFFFh 64 Kbit or 4 KWord 512 Kbit or 32 KWord Total of 31 Main Blocks 3F0000h Bank A 3F7FFFh 3F8000h 3F8FFFh 0F8000h 512 Kbit or 32 KWord 0FFFFFh 100000h 64 Kbit or 4 KWord 107FFFh Total of 8 Parameter Blocks 3FF000h 3FFFFFh Total of 31 Main Blocks 64 Kbit or 4 KWord 512 Kbit or 32 KWord 512 Kbit or 32 KWord Total of 96 Main Blocks Bank B 3F8000h 3FFFFFh 512 Kbit or 32 KWord AI90089 4/52 M58MR064C, M58MR064D SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0ADQ15). When Chip Enable E is at VIL and Output Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memory array, data to be programmed in the memory array or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. In synchronous operations the address is also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. Both input data and commands are latched on the rising edge of Write Enable W. When Chip Enable E and Output Enable G are at VIL the address/data bus outputs data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection status the Read Configuration Register status, the protection register or the Status Register. The address/data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Address Inputs (A16-A21). The five MSB addresses of the memory array are latched on the rising edge of Latch Enable L. In synchronous operation these inputs are also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at VIL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is at VIH the outputs are High impedance. Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power-down Input (RP). The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Read Configuration Register status. Reset/Power-down of the memory is achieved by pulling RP to VIL for at least tPLPH. When the reset pulse is given, the memory will recover from Power-down (when enabled) in a minimum of tPHEL, tPHLL or tPHWL (see Table 31 and Figure 15) after the rising edge of RP. Exit from Reset/Power-down changes the contents of the Read Configuration Register bits 14 and 15, setting the memory in asynchronous page mode read and power save function disabled. All blocks are protected and unlocked after a Reset/Power-down. Latch Enable (L). L latches the address bits ADQ0-ADQ15 and A16-A21 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at VIH. Clock (K). The clock input synchronizes the memory to the micro controller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration settings) when L is at VIL. K is don't care during asynchronous page mode read and in write operations. Wait (WAIT). WAIT is an output signal used during burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cycle in advance. Bus Invert (BINV). BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previous data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at VOH to inform the receiving system that data must be inverted before any further processing. By doing so, the actual transitions on the data bus will be less than 8. In a similar way, when a command is given, BINV may be driven by the system at VIH to inform the memory that the data input must be inverted. Like the other input/output pins, BINV is high impedance when the chip is deselected, output enable G is at VIH or RP is at VIL; when used as an input, BINV must follow the same set-up and hold timings of the data inputs. VDD and VDDQ Supply Voltage (1.65V to 2.0V). VDD is the main power supply for all operations (Read, Program and Erase). VDDQ is the supply voltage for Input and Output. 5/52 M58MR064C, M58MR064D VPP Program Supply Voltage (12V). VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin; if VPP is kept in a low voltage range (0 to 2V) VPP is seen as a control input, and the current absorption is limited to 5µA (0.2µA typical). In this case with VPP = VIL we obtain an absolute protection against program or erase; with VPP = VPP1 these functions are enabled (see Table 26). VPP value is only sampled during program or erase write cycles; a change in its value after the 6/52 operation has been started does not have any effect and program or erase are carried on regularly. If VPP is used in the 11.4V to 12.6V range (VPPH) then the pin acts as a power supply (see Table 26). This supply voltage must remain stable as long as program or erase are running. In read mode the current sunk is less then 0.5mA, while during program and erase operations the current may increase up to 10mA. VSS Ground. VSS is the reference for all the voltage measurements. M58MR064C, M58MR064D DEVICE OPERATIONS The following operations can be performed using the appropriate bus cycles: Address Latch, Read Array (Random, and Page Modes), Write command, Output Disable, Standby, reset/Powerdown and Block Locking. See Table 4. Address Latch. In asynchronous operation, the address is latched on the rising edge of L input. In burst mode the address is latched either on the rising edge of L or on the first rising/falling edge of K (depending on configuration settings) when L is low. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register, the CFI, the Block Protection Status, the Read Configuration Register status and the Protection Register. Read operation of the Memory Array may be performed in asynchronous page mode or synchronous burst mode. In asynchronous page mode data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by ADQ0 and ADQ1 address inputs. According to the device configuration the following Read operations: Electronic Signature - Status Register - CFI - Block Protection Status - Read Configuration Register Status - Protection Register must be accessed as asynchronous read or as single synchronous read (see Figure 4). Table 4. User Bus Operations (1) Operation E G W L RP WP ADQ15-ADQ0 Address Latch VIL VIH VIH VIL (rising edge) VIH VIH Address Input Write VIL VIH VIL VIH VIH VIH Data Input Output Disable VIL VIH VIH VIH VIH VIH Hi-Z Standby VIH X X X VIH X Hi-Z X X X X VIL X Hi-Z VIL X X X VIH VIL X Reset / Power-down Block Locking Note: 1. X = Don't care. Table 5. Read Electronic Signature (AS and Read CFI instructions) (1) E G W ADQ1 (3) ADQ0 (3) Other Address (2) ADQ15-0 VIL VIL VIH VIL VIL EA (2) 0020h M58MR064C VIL VIL VIH VIL VIH EA (2) 88DCh M58MR064D VIL VIL VIH VIL VIH EA (2) 88DDh Code Device Manufacturer Code Device Code Note: 1. Addresses are latched on the rising edge of L input. 2. EA means Electronic Signature Address (see Read Electronic Signature) 3. Value during address latch. Table 6. Read Block Protection (AS and Read CFI instructions) (1) E G W ADQ1 (3) ADQ0 (3) Other Address ADQ15-0 Protected and unlocked VIL VIL VIH VIH VIL BA (4) 0001 Unprotected and unlocked VIL VIL VIH VIH VIL BA (4) 0000 Protected and locked VIL VIL VIH VIH VIL BA (4) 0003 Unprotected and locked (2) VIL VIL VIH VIH VIL BA (4) 0002 Block Status Note: 1. 2. 3. 4. Addresses are latched on the rising edge of L input. A locked block can be unprotected only with WP at VIH. Value during address latch. BA means Block Address. First cycle command address should indicate the bank of the block address. 7/52 M58MR064C, M58MR064D Table 7. Read Protection Register (RSIG and RCFI Instruction) (1) Word E G W A21-17 ADQ15-8 ADQ7-0 ADQ15-8 ADQ7-3 ADQ2 ADQ1 ADQ0 Lock VIL VIL VIH X (2) X (2) 80h 00h 00000B Security prot.data OTP prot.data 0 Unique ID 0 VIL VIL VIH X (2) X (2) 81h ID data ID data ID data ID data ID data Unique ID 1 VIL VIL VIH X (2) X (2) 82h ID data ID data ID data ID data ID data Unique ID 2 VIL VIL VIH X (2) X (2) 83h ID data ID data ID data ID data ID data Unique ID 3 VIL VIL VIH X (2) X (2) 84h ID data ID data ID data ID data ID data OTP 0 VIL VIL VIH X (2) X (2) 85h OTP data OTP data OTP data OTP data OTP data OTP 1 VIL VIL VIH X (2) X (2) 86h OTP data OTP data OTP data OTP data OTP data OTP 2 VIL VIL VIH X (2) X (2) 87h OTP data OTP data OTP data OTP data OTP data OTP 3 VIL VIL VIH X (2) X (2) 88h OTP data OTP data OTP data OTP data OTP data Note: 1. Addresses are latched on the rising edge of L input. 2. X = Don't care. Table 8. Dual Bank Operations (1, 2, 3) Commands allowed in the other bank Status of one bank Read Array Read Status Read ID/CFI Program Erase/ Erase Resume Program Suspend Erase Suspend Protect Unprotect Yes Yes Yes Yes Yes Yes Yes Yes – – – – – – – – Programming Yes Yes Yes – – – – Yes Erasing Yes Yes Yes – – – – Yes Program Suspended Yes Yes Yes – – – – Yes Erase Suspended Yes Yes Yes Yes – Yes – Yes Idle Reading Note: 1. For detailed description of command see Table 33 and 34. 2. There is a status register for each bank; status register indicates bank state, not P/E.C. status. 3. Command must be written to an address within the block targeted by that command. 8/52 M58MR064C, M58MR064D Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions) K L A21-A16 VALID ADDRESS CONF. CODE 2 ADQ15-ADQ0 VALID ADDRESS VALID DATA NOT VALID NOT VALID NOT VALID VALID DATA NOT VALID NOT VALID CONFIGURATION CODE 3 ADQ15-ADQ0 VALID ADDRESS CONFIGURATION CODE 4 ADQ15-ADQ0 VALID ADDRESS VALID DATA NOT VALID AI90090 Both Chip Enable E and Output Enable G must be at VIL in order to read the output of the memory. Read array is the default state of the device when exiting power down or after power up. Burst Read. The device also supports a burst read. In this mode a burst sequence is started at the first clock edge (rising or falling according to configuration settings) after the falling edge of L. After a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. The burst sequence may be configured for linear or interleaved order and for a length of 4, 8 words or for continuous burst mode. Wrap and no-wrap modes are also supported. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. See the Write Read Configuration Register (CR) Instruction for more details on all the possible settings for the synchronous burst read (see Table 14). It is possible to perform burst read across bank boundary (all banks in read array mode). Write. Write operations are used to give Instruction Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at VIL with Output Enable G at VIH. Addresses are latched on the rising edge of L. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Noise pulses of less than 5ns typical on E, W and G signals do not start a write cycle. Write operations are asynchronous and clock is ignored during write. Dual Bank Operations. The Dual Bank allows to run different operations simultaneously in the two banks. It is possible to read array data from one bank while the other is programming, erasing or reading any data (CFI, status register or electronic signature). Read and write cycles can be initiated for simultaneous operations in different banks without any delay. Only one bank at a time is allowed to be in program or erase mode, while the other must be in one of the read modes (see Table 8). Commands must be written to an address within the block targeted by that command. Output Disable. The data outputs are high impedance when the Output Enable G is at VIH with Write Enable W at VIH. Standby. The memory is in standby when Chip Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. The automatic standby feature is not available when the device is configured for synchronous burst mode. 9/52 M58MR064C, M58MR064D Table 9. Identifier Codes Code Manufacturer Code Address (h) Data (h) Bank Address + 00 0020 Top Bank Address + 01 88DC Bottom Bank Address + 01 88DD Device Code Protected and Unlocked 0001 Unprotected and Unlocked Block Protection 0000 Bank Address + 02 Protected and Locked 0003 Unprotected and Locked 0002 Die Revision Code Bank Address + 03 DRC (1) Read Configuration Register Bank Address + 05 CR (1) Lock Protection Register Bank Address + 80 LPR (1) Protection Register Bank Address + 81 Bank Address + 88 PR (1) Note: 1. DRC means Die Revision Code. CR means Read Configuration Register. LPR means Lock Protection Register. PR means Unique Device Number and User Programmable OTP. Reset/Power-down. The memory is in Powerdown when the Read Configuration Register is set for Power-down and RP is at VIL. The power consumption is reduced to the Power-down level, and Outputs are in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs. The memory is in reset when the Read Configuration Register is set for Reset and RP is at VIL. The power consumption is the same of the standby and the outputs are in high impedance. After a Reset/Power down the device defaults to read array mode, the status register is set to 80h and the read configuration register defaults to asynchronous read. 10/52 Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to VIL. The following summarizes the locking operation. All blocks are protected on power-up. They can then be unprotected or protected with the Unprotect and Protect commands. The Lock command protects a block and prevents it from being unlocked when WP = 0. When WP = 1, Lock is overridden. Lock is cleared only when the device is reset or powered-down (see Protect instruction). M58MR064C, M58MR064D INSTRUCTIONS AND COMMANDS Eighteen instructions are available (see Tables 10 and 11) to perform Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Block Erase, Bank Erase, Program, Tetra Word Program, Double Word Program, Clear Status Register, Program/Erase Suspend, Program/ Erase Resume, Block Protect, Block Unprotect, Block Lock, Protection Register Program, Read Configuration Register and Lock Protection Program. Status Register output may be read at any time, during programming or erase, to monitor the progress of the operation. An internal Command Interface (C.I.) decodes the instructions while an internal Program/Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Register whose bits indicate operation and exit status of the internal algorithms. The Command Interface is reset to Read Array when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequence must be followed exactly. Any invalid combination of commands will reset the device to Read Array. Read (RD) The Read instruction consists of one write cycle (refer to Device Operations section) and places the addressed bank in Read Array mode. When a device reset occurs, the memory is in Read Array as default. A read array command will be ignored while a bank is programming or erasing. However in the other bank a read array command will be accepted. Read Status Register (RSR) A bank's Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register Instruction (70h) to read the Status Register content of the addressed bank. The status of the other bank is not affected by the command. The Read Status Register instruction may be issued at any time, also when a Program/Erase operation is ongoing. The following Read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. Read Electronic Signature (RSIG) The Read Electronic Signature instruction consists of one write cycle (refer to Device Operations section) giving the command 90h to an address Table 10. Commands Hex Code Command 00h Invalid Reset 01h Protect Confirm 03h Write Read Configuration Register Confirm 10h Alternative Program Set-up 20h Block Erase Set-up 2Fh Lock Confirm 30h Double Word Program Set-up 40h Program Set-up 50h Clear Status Register 55h Tetra Word Program Set-up 60h Protect Set-up and Write Read Configuration Register 70h Read Status Register 80h Bank Erase Set-up 90h Read Electronic Signature 98h CFI Query B0h Program/Erase Suspend C0h Protection Program and Lock Protection Program D0h Program/Erase Resume, Erase Confirm or Unprotect Confirm FFh Read Array within the bank A. A subsequent read in the address of bank A will output the Manufacturer Code, the Device Code, the protection Status of Blocks of bank A, the Die Revision Code, the Protection Register, or the Read Configuration Register (see Table 9). If the first write cycle of Read Electronic Signature instruction is issued to an address within the bank B, a subsequent read in an address of bank B will output the protection Status of Blocks of bank B. The status of the other bank is not affected by the command (see Table 8). See Tables 5, 6, 7 and 8 for the valid address. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M58MR064C and M58MR064D. 11/52 M58MR064C, M58MR064D Table 11. Instructions Operation Write BKA FFh Read (1) Read Address Data 1+ Write BKA 70h Read (1) BKA Status Register Read Electronic Signature 1+ Write EA 90h Read (1) EA ED Read CFI 1+ Write CA 98h Read (1) CA CD 1 Write BKA 50h Operation Read Memory Array 1+ RSR Read Status Register RSIG RCFI READ Clear Status CLRS (5) Register PROGRAM/ERASE PROTECT CONFIGURATION (1,2) Data (3) EE Block Erase 2 Write BA 20h Write BA D0h BE Bank Erase 2 Write BKA 80h Write BKA D0h PG Program 2 Write WA 40h or 10h Write WA WD Double Word Program 3 Write WA1 30h Write WA1 WD1 Write WA2 WD2 Write WA1 WD1 Write WA2 WD2 Write WA3 WD3 Write WA4 WD4 DPG TPG Tetra Word Program 5 Write WA1 55h PES Program Erase Suspend 1 Write BKA B0h PER Program Erase Resume 1 Write BKA D0h BP Block Protect 2 Write BA 60h Write BA 01h BU Block Unprotect 2 Write BA 60h Write BA D0h BL Block Lock 2 Write BA 60h Write BA 2Fh PRP Protection Register Program 2 Write PA C0h Write PA PD LPRP Lock Protection Register Program 2 Write LPA C0h Write LPA LPD Write Read Configuration Register 2 Write RCA 60h Write RCA 03h CR 12/52 Address Data (3) Cyc. RD Address (1,2) Instruction M58MR064C, M58MR064D Note: 1. First cycle command address should be the same as the operation's target address. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one command cycle. 2. BKA means Address within the bank; BA means Block Address; EA means Electronic Signature Address; CA means Common Flash Interface Address; WA means Word Address; PA means Protection Register Address (see Table 7); LPA means Lock Protection Register Address (see Table 7); RCA means Read Configuration Register Address. 3. PD means Protection Data; CD means Common Flash Interface Data; ED means Electronic Signature Data; WD means Data to be programmed at the address location WA; LPD means Lock protection Register Data 4. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0. 5. Read cycle after e CLSR instruction will output the memory array. CFI Query (RCFI) The CFI Query Mode is associated to bank A. The address of the first write cycle must be within the bank A. The status of the other bank is not affected by the command (see Table 8). Writing 98h the device enters the Common Flash Interface Query mode. Next read operations in the bank A will read the CFI data. Write a read instruction to return to Read mode (refer to the Common Flash Interface section). Clear Status Register (CLSR) The Clear Status Register uses a single write operation, which resets bits b1, b3, b4 e b5 of the status register. The Clear Status Register is executed writing the command 50h independently of the applied VPP voltage. After executing this command the device returns to read array mode. The Clear Status Register command clears only the status register of the addressed bank. Block Erase (EE) Block erasure sets all the bits within the selected block to '1'. One block at a time can be erased. It is not necessary to pre-program the block as the P/E.C. will do it automatically before erasing. This instruction use two writes cycles. The first command written is the Block Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased should be given to the memory during the two cycles command. If the second command given is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. After writing the command, the device outputs status register data when any address within the bank is read. At the end of the operation the bank will remain in read status register until a read array command is written. Status Register bit b7 is '0' while the erasure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if there has been an Erase Failure. Status register bit b1 returns '1' if the user is attempting to erase a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Erase aborts if RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated (see Table 12). A Clear Status Register instruction must be issued to reset b1, b3, b4 and b5 of the Status Register. During the execution of the erase by the P/E.C., the bank with the block in erase accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. See figure 19 for Erase Flowchart and Pseudo Code. Bank Erase (BE) Bank erase sets all the bits within the selected bank to ’1’. It is not necessary to pre-program the block as the P/E.C. will do it automatically before erasing. This instruction uses two writes cycles. The first command written is the Bank Erase set-up command 80h. The second command is the Erase Confirm command D0h. An address within the bank to be erased should be given to the memory during the two cycles command. See the Block Erase command section for status register bit details. 13/52 M58MR064C, M58MR064D Table 12. Status Register Bits Mnemonic P/ECS ESS ES PS VPPS PSS BPS Bit 7 6 5 4 3 2 1 Name P/ECS Status Logic Level 1 Ready 0 Busy Erase Suspend Status 1 Suspended 0 In Progress or Completed Erase Status 1 Erase Error 0 Erase Success 1 Program Error 0 Program Success 1 VPP Invalid, Abort 0 VPP OK 1 Suspended 0 In Progress or Completed Program Status VPP Status Program Suspend Status Block Protection Status 1 0 0 Definition Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success. On an Erase Suspend instruction P/ECS and ESS bits are set to ’1’. ESS bit remains ’1’ until an Erase Resume instruction is given. ES bit is set to ’1’ if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. PS bit set to ’1’ if the P/E.C. has failed to program a word. VPPS bit is set if the VPP voltage is below VPPLK when a Program or Erase instruction is executed. VPP is sampled only at the beginning of the erase/program operation. On a program Suspend instruction P/ECS and PSS bits are set to ’1’. PSS remains ’1’ until a Program Resume Instruction is given. Program/Erase on protected BPS bit is set to ’1’ if a Program or Erase Block, Abort operation has been attempted on a protected No operation to block. protected blocks Reserved Note: Logic level ’1’ is VIH and ’0’ is VIL. Program (PG) The Program instruction programs the array on a word-by-word basis. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure (see 14/52 Table 12). Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Any attempt to write a ’1’ to an already programmed bit will result in a program fail (status register bit b4 set) if VPP = VPPH and will be ignored if VPP = VPP1. Programming aborts if RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. See Figure 16 for Program Flowchart and Pseudo Code. M58MR064C, M58MR064D Figure 5. Security Block Memory Map 88h User Programmable OTP 85h 84h Parameter Block # 0 Unique device number 81h 80h Protection Register Lock 2 1 0 AI90091 Table 13. Protection States (1) Current State (2) (WP, DQ1, DQ0) Program/Erase Allowed 100 Next State After Event (3) Protect Unprotect Lock WP transition Yes 101 100 111 000 101 No 101 100 111 001 110 Yes 111 110 111 011 111 No 111 110 111 011 000 Yes 001 000 011 100 001 No 001 000 011 101 011 No 011 011 011 111 or 110 (4) Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect in and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = VIH and A0 = VIL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value. 4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. 15/52 M58MR064C, M58MR064D Double Word Program (DPG) This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH but result could be uncertain. These instruction uses three write cycles. The first command written is the Double Word Program Set-Up command 30h. A second write operation latches the Address and the Data of the first word to be written, the third write operation latches the Address and the Data of the second word to be written and starts the P/E.C. (see Table 11). Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Any attempt to write a ’1’ to an already programmed bit will result in a program fail (status register bit b4 set). (See Table 12). Programming aborts if RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Double Word Program Flowchart and Pseudo code. Tetra Word Program (TPG) This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH but result could be uncertain. These instruction uses five write cycles. The first command written is the Tetra Word Program Set-Up command 55h. A second write operation latches the Address and the Data of the first word to be written, the third write operation 16/52 latches the Address and the Data of the second word to be written, the fourth write operation latches the Address and the Data of the third word to be written, the fifth write operation latches the Address and the Data of the fourth word to be written and starts the P/E.C. (see Table 11). Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Any attempt to write a ’1’ to an already programmed bit will result in a program fail (status register bit b4 set). (See Table 12). Programming aborts if RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Tetra Word Program Flowchart and Pseudo code. Erase Suspend/Resume (PES/PER) The Erase Suspend freezes, after a certain latency period (within 25us), the erase operation and allows read in another block within the targeted bank or program in the other block. This instruction uses one write cycle B0h and the address should be within the bank with the block in erase (see Table 11). The device continues to output status register data after the erase suspend is issued. The status register bit b7 and bit b6 are set to ’1’ then the erase operation has been suspended. Bit b6 is set to '0' in case the erase is completed or in progress (see Table 12). The valid commands while erase is suspended are: Program/Erase Resume, Program, Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Block Protect, Block Unprotect and Block Lock. The user can protect the Block being erased issuing the Block Protect or Block Lock commands. During a block erase suspend, the device goes into standby mode by taking E to VIH, which reduces active current draw. Erase is aborted if RP turns to VIL. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by issuing the command D0h using an address within the suspended bank. The status register bit b6 and bit b7 are cleared when erase resumes and read M58MR064C, M58MR064D operations output the status register after the erase is resumed. Block erase cannot resume until program operations initiated during block erase suspend have completed. It is also possible to nest suspends as follows: suspend erase in the first partition, start programming in the second or in the same partition, suspend programming and then read from the second or the same partition. The suggested flowchart for erase suspend/resume features of the memory is shown from Figure 20. Program Suspend/Resume (PES/PER) Program suspend is accepted only during the Program instruction execution. When a Program Suspend command is written to the C.I., the P/E.C. freezes the Program operation. Program Resume (PER) continues the Program operation. Program Suspend (PES) consists of writing the command B0h and the address should be within the bank with the word in programming (see Table 11). The Status Register bit b2 is set to '1' (within 5µs) when the program has been suspended. Bit b2 is set to '0' in case the program is completed or in progress (see Table 12). The valid commands while program is suspended are: Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature, CFI Query. During program suspend mode, the device goes in standby mode by taking E to VIH. This reduces active current consumption. Program is aborted if RP turns to VIL. If a Program Suspend instruction was previously executed, the Program operation may be resumed by issuing the command D0h using an address within the suspended bank (see Table 11). The status register bit b2 and bit b7 are cleared when program resumes and read operations output the status register after the erase is resumed (see Table 12). The suggested flowchart for program suspend/resume features of the memory is shown from Figure 18. Block Protect (BP) The BP instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Protect command 01h, written to an address within the block to be protected (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands (see Table 12). To read the status register write the RSR command. Block Unprotect (BU) The instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Unprotect command D0h, written to an address within the block to be protected (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands (see Table 12). To read the status register write the RSR command. Block Lock (BL) The instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Lock command 2Fh, written to an address within the block to be protected (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command (see Table 12). 17/52 M58MR064C, M58MR064D BLOCK PROTECTION The M58MR064C/M58MR064D provide a flexible protection of all the memory providing the protection, un-protection and locking of any blocks. All blocks are protected at power-up. Each block of the array has two levels of protection against programming or erasing operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: – when WP is at VIH, the Lock status is overridden and all blocks can be protected or unprotected; – when WP is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status; – the lock status is cleared for all blocks at power up. The protection and lock status can be monitored for each block using the Read Electronic Signature (RSIG) instruction. Protected blocks will output a '1' on DQ0 and locked blocks will output a '1' in DQ1 (see Table 13). PROTECTION REGISTER PROGRAM (PRP) and LOCK PROTECTION REGISTER PROGRAM (LPRP) The M58MR064C/M58MR064D features a 128-bit protection register and a security Block in order to increase the protection of a system design. The Protection Register is divided in two 64-bit segments. The first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be programmed by the user. When shipped the user programmable segment is read at '1'. It can be only programmed at '0'. The user programmable segment can be protected writing the bit 1 of the Protection Lock register (80h). The bit 1 protects also the bit 2 of the Protection Lock Register. The M58MR064C/M58MR064D feature a security Block. The security Block is located at 3FF0003FFFFF (M58MR064C) or at 000000-000FFF (M58MR064D) of the device. This block can be permanently protected by the user programming the bit 2 of the Protection Lock Register (see Figure 5). The protection Register and the Protection Lock Register can be read using the RSIG and RCFI instructions. A subsequent read in the address starting from 80h to 88h, the user will retrieve respectively the Protection Lock register, the unique device number segment and the OTP user programmable register segment (see Table 23). 18/52 WRITE READ CONFIGURATION REGISTER (CR). This instruction uses two Coded Cycles, the first write cycle is the write Read Configuration Register set-up 60h, the second write cycle is write Read Configuration Register confirm 03h both to Read Configuration Register address (see Table 11). This instruction writes the contents of address bits ADQ15-ADQ0 to bits CR15-CR0 of the Read Configuration Register (A21-A16 are don't care). At Power-up the Read Configuration Register is set to asynchronous Read mode, Power-down disabled and bus invert (power save function) disabled. A description of the effects of each configuration bit is given in Table 14. Read mode (CR15). The device supports an asynchronous page mode and a synchronous burst mode. In asynchronous page mode, the default at power-up, data is internally read and stored in a buffer of 4 words selected by ADQ0 and ADQ1 address inputs. In synchronous burst mode, the device latches the starting address and then outputs a sequence of data that depends on the Read Configuration Register settings (see Figures 10, 11 and 12). Synchronous burst mode is supported in both parameter and main blocks; it is also possible to perform burst mode read across the banks. Bus Invert configuration (CR14). This register bit is used to enable the BINV pin functionality. BINV functionality depends upon configuration bits CR14 and CR15 (see Table 14 for configuration bits definition) as shown in Table 15. As output pin BINV is active only when enabled (CR14 = 1) in Read Array burst mode (CR15 = 0). As input pin BINV is active only when enabled (CR14 = 1). BINV is ignored when ADQ0-ADQ15 lines are used as address inputs (addresses must not be inverted). X-Latency (CR13-CR11). These configuration bits define the number of clock cycles elapsing from L going low to valid data available in burst mode (see Figure 6). The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: – (n + 2) tK ≥ tACC + tQVK_CPU + tAVK_CPU – tK > tKQV + tQVK_CPU where "n" is the chosen X-Latency configuration code, tK is the clock period, tAVK_CPU is the address setup time guaranteed by the system CPU, and tQVK_CPU is the data setup time required by the system CPU. M58MR064C, M58MR064D Table 14. Read Configuration Register (AS and Read CFI instructions) (1) Configuration Register Function Read mode 0 = Synchronous Burst mode read 1 = Asynchronous Page mode read (default) CR15 Bus Invert configuration (power save) 0 = disabled (default) 1 = enabled X-Latency 010 = 2 clock latency 011 = 3 clock latency 100 = 4 clock latency 101 = 5 clock latency 111 = reserved Other configurations reserved Power-down configuration 0 = power-down disabled (default) 1 = power-down enabled Reserved CR14 CR13-CR11 CR10 CR9 Wait configuration 0 = WAIT is active during wait state 1 = WAIT is active one data cycle before wait state (default) Burst order configuration 0 = Interleaved 1 = Linear (default) Clock configuration 0 = Address latched and data output on the falling clock edge 1 = Address latched and data output on the rising clock edge (default) CR8 CR7 CR6 CR5-CR4 Reserved Burst Wrap 0 = burst wrap within burst length set by CR2-CR0 1 = Don’t wrap accesses within burst length set by CR2-CR0 (default) CR3 Burst length 001 = 4 word burst length 010 = 8 word burst length 111 = Continuous burst mode (requires CR7 = 1) CR2-CR0 Note: 1. The RCR can be read via the RSIG command (90h). Bank A Address + 05h contains the RCR data. See Table 9. 2. All the bits in the RCR are set to default on device power-up or reset. Table 15. BINV Configuration Bits BINV CR15 CR14 IN OUT 0 0 X 0 0 1 Active Active 1 0 X 0 1 1 Active 0 19/52 M58MR064C, M58MR064D Power-down configuration (CR10). The RP pin may be configured to give very low power consumption when driven low (power-down state). In power-down the ICC supply current is reduced to a typical figure of ICC2; if this function is disabled (default at power-up) the RP pin causes only a reset of the device and the supply current is the stand-by value. The recovery time after a RP pulse is significantly longer when power-down is enabled (see Table 31). Wait configuration (CR8). In burst mode WAIT indicates whether the data on the output bus are valid or a wait state must be inserted. The configuration bit determines if WAIT will be asserted one clock cycle before the wait state or during the wait state (see Figure 7). WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. Burst order configuration (CR7) and Burst Wrap configuration (CR3). See Table 16 for burst order and length. Clock configuration (CR6). In burst mode determines if address is latched and data is output on the rising or falling edge of the clock. Burst length (CR2-CR0). In burst mode determines the number of words output by the memory. It is possible to have 4 words, 8 words or a continuous burst mode, in which all the words are read sequentially. In continuous burst mode the burst sequence can cross the end of each of the two banks (all banks in read array mode). In continuous burst mode or in 4, 8 words no-wrap it may happen that the memory will stop the data output flow for a few clock cycles; this event is signaled by WAIT going low until the output flow is resumed. The initial address determines if the output delay will occur as well as its duration. If the starting address is aligned to a four words boundary no wait states will be needed. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence is crossing the first 64 word boundary. WAIT will be asserted only once during a continuous burst access. See also Table 16. Figure 6. X-Latency Configuration Sequence K L A21-A16 VALID ADDRESS CONF. CODE 2 ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA VALID DATA VALID DATA CONFIGURATION CODE 3 ADQ15-ADQ0 VALID DATA VALID DATA VALID DATA VALID ADDRESS CONFIGURATION CODE 4 ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA AI90092 20/52 M58MR064C, M58MR064D Figure 7. Wait Configuration Sequence K L A21-A16 VALID ADDRESS ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' WAIT CR8 = '1' AI90093 21/52 Starting Mode Address 4 Words 8 Words Continuous Burst Linear Interleaved Linear Interleaved 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... Wrap ... 7 ... 60 60-61-62-63-64-65-66... 61 61-62-63-WAIT-64-65-66... 62 62-63-WAIT-WAIT-64-65-66... 63 63-WAIT-WAIT-WAIT-64-65-66... No-wrap Linear Interleaved Linear Interleaved 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7... 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5-6-7-8... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9... 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13... 60 60-61-62-63 60-61-62-63-64-65-66-67 60-61-62-63-64-65-66... 61 61-62-63-WAIT-64 61-62-63-WAIT-64-65-66-67-68 61-62-63-WAIT-64-65-66... 62 62-63-WAIT-WAIT-64-65 62-63-WAIT-WAIT-64-65-66-67-68-69 62-63-WAIT-WAIT-64-65-66... 63 63-WAIT-WAIT-WAIT-64-65-66 63-WAIT-WAIT-WAIT-64-65-66-67-68-69-70 63-WAIT-WAIT-WAIT-64-65-66... ... 7 ... M58MR064C, M58MR064D 22/52 Table 16. Burst Order and Length Configuration M58MR064C, M58MR064D POWER CONSUMPTION Power-down The memory provides Reset/Power-down control input RP. The Power-down function can be activated only if the relevant Read Configuration Register bit is set to '1'. In this case, when the RP signal is pulled at VSS the supply current drops to typically ICC2 (see Table 26), the memory is deselected and the outputs are in high impedance. If RP is pulled to VSS during a Program or Erase operation, this operation is aborted and the memory content is no longer valid (see Reset/Power-down input description). Power-up The memory Command Interface is reset on Power-up to Read Array. Either E or W must be tied to VIH during Power-up to allow maximum security and the possibility to write a command on the first rising edge of W. At Power-up the device is configured as: – Page mode: (CR15 = 1) – Power-down disabled: (CR10 = 0) – BINV disabled: (CR14 = 0). All blocks are protected and unlocked. VDD, VDDQ and VPP are independent power supplies and can be biased in any order. Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VDD rails decoupled with a 0.1µF capacitor close to the VDD, VDDQ and VSS pins. The PCB trace widths should be sufficient to carry the required VDD program and erase currents. 23/52 M58MR064C, M58MR064D COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardized data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Tables 17, 18, 19, 20, 21, 22 and 23 show the address used to retrieve each data. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode (see Table 11). Refer to the CFI Query instruction to understand how the M58MR064 enters the CFI Query mode. Table 17. Query Structure Overview Offset Sub-section Name Description 00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout P Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate Algorithm (optional) Security Code Area Lock Protection Register Unique device Number and User Programmable OTP 80h Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs. Table 18. CFI Query Identification String Offset Sub-section Name 00h 0020h Manufacturer Code 01h 88DCh 88DDh Device Code 02h reserved 03h (1) DRC 04h-0Fh reserved 10h 0051h 11h 0052h 12h 0059h 13h 0003h 14h 0000h 15h offset = P = 0039h 16h 0000h 17h 0000h 18h 0000h 19h value = A = 0000h 1Ah 0000h Description ST Top Bottom Reserved Die Revision Code Reserved "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 20) p = 39h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) NA Address for Alternate Algorithm extended Query table (0000h means none exists) NA Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’. 1. DRC means Die Revision Code. 24/52 Value M58MR064C, M58MR064D Table 19. CFI Query System Interface Information Offset Data Description Value 1Bh 0017h VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 1.7V 1Ch 0020h VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 2V 1Dh 0017h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 1.7V 1Eh 00C0h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 12V 1Fh 0004h Typical timeout per single byte/word program = 2n µs 16µs 20h 0004h Typical timeout for tetra word program = 2n µs 16µs 21h 000Ah Typical timeout per individual block erase = 2n ms 1s 22h 0000h Typical timeout for full chip erase = 2n ms NA 23h 0004h Maximum timeout for word program = 2n times typical 256µs 24h 0004h Maximum timeout for tetra word = 2n times typical 256µs 25h 0004h Maximum timeout per individual block erase = 2n times typical 16s 26h 0000h Maximum timeout for chip erase = 2n times typical NA 25/52 M58MR064C, M58MR064D Table 20. Device Geometry Definition Data 27h 0017h Device Size = 2n in number of bytes 28h 29h 0001h 0000h Flash Device Interface Code description x16 Async. 2Ah 2Bh 0003h 0000h Maximum number of bytes in multi-byte program or page = 2n 8 Byte 2Ch 0003h Number of Erase Block Regions within the device bit 7 to 0 = x = number of Erase Block Regions It specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. 3 96 M58MR064D M58MR064C Offset Word Mode 26/52 Description Value 8 MByte 2Dh 2Eh 005Fh 0000h Region 1 Information (main block - Bank B) Number of identical-size erase block = 005Fh+1 2Fh 30h 0000h 0001h Region 1 Information (main block - Bank B) Block size in Region 1 = 0100h * 256 byte 31h 32h 001Eh 0000h Region 2 Information (main block - Bank A) Number of identical-size erase block = 001Eh+1 33h 34h 0000h 0001h Region 2 Information (main block - Bank A) Block size in Region 2 = 0100h * 256 byte 35h 36h 0007h 0000h Region 3 Information (parameter block - Bank A) Number of identical-size erase block = 0007h+1 8 37h 38h 0020h 0000h Region 3 Information (parameter block - Bank A) Block size in Region 3 = 0020h * 256 byte 8 KByte 2Dh 2Eh 0007h 0000h Region 1 Information (parameter block - Bank A) Number of identical-size erase block = 0007h+1 8 2Fh 30h 0020h 0000h Region 1 Information (parameter block - Bank A) Block size in Region 1 = 0020h * 256 byte 8 KByte 31h 32h 001Eh 0000h Region 2 Information (main block - Bank A) Number of identical-size erase block = 001Eh+1 31 33h 34h 0000h 0001h Region 2 Information (main block - Bank A) Block size in Region 2 = 0001h * 256 byte 35h 36h 005Fh 0000h Region 3 Information (parameter block - Bank B) Number of identical-size erase block = 005Fh+1 96 37h 38h 0000h 0001h Region 3 Information (parameter block - Bank B) Block size in Region 3 = 0001h * 256 byte 64 KByte 64 KByte 31 64 KByte 64 KByte M58MR064C, M58MR064D Table 21. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 39h 0050h 0052h Description Value "P" Primary Algorithm extended Query table unique ASCII string “PRI” 0049h "R" "I" (P+3)h = 3Ch 0031h Major version number, ASCII "1" (P+4)h = 3Dh 0030h Minor version number, ASCII "0" (P+5)h = 3Eh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. 0003h (P+7)h 0000h (P+8)h 0000h (P+9)h = 42h 0001h bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 (P+A)h = 43h 0003h (P+B)h 0000h Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are ‘0’ Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Protect/Unprotect bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are ‘0’ (P+C)h = 45h 0018h VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 (P+D)h = 46h 00C0h (P+E)h = 47h (P+F)h (P+10)h (P+11)h (P+12)h 0000h 1.8V HEX value in volts BCD value in 100 mV VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 Yes Yes 12V HEX value in volts BCD value in 100 mV Reserved 27/52 M58MR064C, M58MR064D Table 22. Burst Read Information Offset Data (P+13)h = 4Ch 0003h Description Value Page-mode read capability bits 0-7 8 Byte ’n’ such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. (P+14)h = 4Dh 0003h Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 3 (P+15)h = 4Eh 0001h Synchronous mode read capability configuration 1 4 bit 3-7 bit 0-2 Reserved ’n’ such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. (P+16)h = 4Fh 0002h Synchronous mode read capability configuration 2 8 (P+17)h = 50h 0007h Synchronous mode read capability configuration 3 Cont. (P+18)h = 51h 0036h Max operating clock frequency (MHz) (P+19)h = 52h 0001h Supported handshaking signal (WAIT pin) bit 0 bit 1 during synchronous read during asynchronous read 54 MHz (1 = Yes, 0 = No) (1 = Yes, 0 = No) Yes No Table 23. Security Code Area 28/52 Offset Data 80h 0000-0000-0000-0XX0 81h XXXX 82h XXXX 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX Description Lock Protection Register 64 bits: unique device number 64 bits: User Programmable OTP M58MR064C, M58MR064D Table 24. AC Measurement Conditions Input Rise and Fall Times Figure 9. AC Testing Load Circuit ≤ 4ns VDDQ / 2 0 to VDDQ Input Pulse Voltages Input and Output Timing Ref. Voltages 1N914 VDDQ/2 3.3kΩ Figure 8. Testing Input/Output Waveforms DEVICE UNDER TEST VDDQ OUT CL = 30pF VDDQ/2 0V CL includes JIG capacitance AI90094 AI90095 Table 25. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. 29/52 M58MR064C, M58MR064D Table 26. DC Characteristics (TA = –40 to 85°C; VDD = VDDQ = 1.65V to 2.0V) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC1 Typ Max Unit 0V ≤ VIN ≤ VDDQ ±1 µA 0V ≤ VOUT ≤ VDDQ ±5 µA E = VIL, G = VIH, f = 6MHz 10 20 mA Supply Current (Synchronous Read Mode Continuous Burst) E = VIL, G = VIH, f = 40MHz 20 30 mA RP = VSS ± 0.2V 2 10 µA E = VDD ± 0.2V 15 50 µA Word Program, Block Erase in progress 10 20 mA Program/Erase in progress in one Bank, Asynchronous Read in the other Bank 20 40 mA Program/Erase in progress in one Bank, Synchronous Read in the other Bank 30 50 mA VPP = 12V ± 0.6V 5 10 mA VPP ≤ VCC 0.2 5 µA VPP = 12V ± 0.6V 100 400 µA Supply Current (Power-down) ICC3 Supply Current (Standby) ICC5 (1) Min Supply Current (Asynchronous Read Mode) ICC2 ICC4 (1) Test Condition Supply Current (Program or Erase) Supply Current (Dual Bank) IPP1 VPP Supply Current (Program or Erase) IPP2 VPP Supply Current (Standby or Read) VIL Input Low Voltage –0.5 0.4 V VIH Input High Voltage VDDQ –0.4 VDDQ + 0.4 V VOL Output Low Voltage 0.1 V VOH Output High Voltage CMOS VPP1 IOL = 100µA IOH = –100µA VDDQ –0.1 VPP Supply Voltage Program, Erase VDDQ –0.4 VDDQ + 0.4 V VPPH VPP Supply Voltage Double/Tetra Word Program 11.4 12.6 V VPPLK Program or Erase Lockout 1 V Note: 1. Sampled only, not 100% tested. 2. VPP may be connected to 12V power supply for a total of less than 100 hrs. 30/52 V M58MR064C, M58MR064D Table 27. Asynchronous Read AC Characteristics (TA = –40 to 85°C; VDD = VDDQ = 1.65V to 2.0V) M58MR064 Symbol Alt Parameter Test Condition 100 Min 120 Max Min Unit Max tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL 100 120 ns tAVLH tAVAVDH Address valid to Latch Enable High G = VIH 10 10 ns tAVQV tACC Address Valid to Output Valid (Random) E = VIL, G = VIL 100 120 ns tAVQV1 tPAGE Address Valid to Output Valid (Page) E = VIL, G = VIL 45 45 ns tEHQX tOH Chip Enable High to Output Transition G = VIL tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL tELLH tELAVDH Chip Enable Low to Latch Enable High E = VIL, G = VIH tELQV (2) tCE Chip Enable Low to Output Valid G = VIL tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL 0 0 ns tGHQX tOH Output Enable High to Output Transition E = VIL 0 0 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 20 20 ns tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 25 35 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL 0 0 ns tLHAX tAVDHAX Latch Enable High to Address Transition E = VIL, G = VIH 10 10 ns Latch Enable High to Output Enable Low E = VIL 10 10 ns E = VIL, G = VIH 10 10 ns tLHGL tLLLH tAVDLAVDH tLLQV tAVDLQV tLLQV1 Latch Enable Pulse Width 0 0 20 10 ns 20 10 100 ns ns 120 ns Latch Enable Low to Output Valid (Random) E = VIL 100 120 ns Latch Enable Low to Output Valid (Page) E = VIL 45 45 ns Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 31/52 32/52 Note: Write Enable (W) = High. G E L A16-A21 ADQ0-ADQ15 tLHGL tELLH tLLLH tAVLH tELQX tELQV tGLQV tGLQX tLHAX tLLQV VALID ADDRESS tAVQV VALID ADDRESS tAVAV VALID DATA tGHQZ tGHQX tEHQX tEHQZ AI90096 VALID ADDRESS VALID ADDRESS M58MR064C, M58MR064D Figure 10. Asynchronous Read AC Waveforms G E L A16-A21 ADQ0-ADQ15 tAVLH tELQV tLLQV VALID ADDRESS tLHGL tGLQV tLHAX VALID DATA tGHQZ tLLQV1 tAVQV1 VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID DATA VALID DATA VALID ADDRESS AI90097 VALID DATA M58MR064C, M58MR064D Figure 11. Page Read AC Waveforms 33/52 M58MR064C, M58MR064D Table 28. Synchronous Burst Read AC Characteristics (TA = –40 to 85°C; VDD = VDDQ = 1.65V to 2.0V) M58MR064 Symbol Alt Parameter Test Condition 100 Min 120 Max Min Unit Max tAVK tAVCLKH Address Valid to Clock 7 7 ns tELK tCELCLKH Chip Enable Low to Clock 7 7 ns tK tCLK Clock Period 18 25 ns tKAX tCLKHAX 10 10 ns tKHKL tCLKHCLKL Clock High 5 5 ns tKLKH tCLKLCLKH Clock Low 5 5 ns tKQV tCLKHQV Clock to Data Valid Clock to BINV Valid Clock to WAIT Valid tKQX tCLKHQX Clock to Output Transition Clock to BINV Transition Clock to WAIT Transition tLLK tAVDLCLKH Latch Enable Low to Clock 34/52 Clock to Address Transition E = VIL, G = VIH E = VIL, G = VIL E = VIL 14 18 ns 4 4 ns 7 7 ns tELK tKAX tAVK tLLK tGLQX note 1 tKQV VALID VALID tK VALID note 2 tKQX tKQX tKQX tKQV tKQV note 3 VALID tGHQZ tGHQX tEHQZ tEHQX VALID VALID VALID DATA Note: 1. The number of clock cycles to be inserted depends upon the x-latency set in the read configuration register. 2. WAIT signal can be configured to be active during wait state or one cycle below wait state. 3. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information). WAIT BINV G E K L tLLLH VALID ADDRESS A16-A21 tAVLH VALID ADDRESS ADQ0-ADQ15 AI90098 M58MR064C, M58MR064D Figure 12. Synchronous Burst Read 35/52 M58MR064C, M58MR064D Table 29. Write AC Characteristics, Write Enable Controlled (TA = –40 to 85 °C; VDD = VDDQ = 1.65V to 2.0V) M58MR064 Symbol Alt Parameter 100 Min tAVAV tWC 120 Max Min Unit Max Address Valid to Next Address Valid 100 120 ns Address Valid to Latch Enable High 10 10 ns Input Valid to Write Enable High 40 40 ns Chip Enable Low to Latch Enable High 10 10 ns Chip Enable Low to Write Enable Low 0 0 ns tGHLL Output Enable High to Latch Enable Low 20 20 ns tGHWL Output Enable High to Write Enable Low 20 20 ns tLHAX Latch Enable High to Address Transition 10 10 ns tLHWH Latch Enable High to Write Enable High 10 10 ns tLLLH Latch Enable Pulse Width 10 10 ns VDD High to Chip Enable Low 50 50 µs VPP High to Write Enable High 200 200 ns tAVLH tDVWH tDS tELLH tELWL tVDHEL tCS tVCS tVPPHWH tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns Write Enable High to Latch Enable Low 0 0 ns Write Enable High to VPP Low 200 200 ns Write Enable High to Write Enable Low 30 30 ns Write Enable High to Write Protect Valid 200 200 ns Write Enable Low to Write Enable High 50 50 ns Write Protect Valid to Write Enable High 200 200 ns tWHLL tWHVPPL tWHWL tWPH tWHWPV tWLWH tWPVWH 36/52 tWP VDD VPP WP G E W L BINV tVDHEL tGHLL tGHWL tELLH tLLLH tELWL ADDRESS VALID A16-A21 tAVLH ADDRESS VALID ADQ0-ADQ15 tLHAX tLHWH VPP1 VPPH tAVAV tVPPHWH tWPVWH tWLWH tWHWPV tWHGL tWHLL tWHDX tWHVPPL VALID VALID tDVWH DATA VALID AI90099 M58MR064C, M58MR064D Figure 13. Write AC Waveforms, W Controlled 37/52 M58MR064C, M58MR064D Table 30. Write AC Characteristics, Chip Enable Controlled (TA = –40 to 85 °C; VDD = VDDQ = 1.65V to 2.0V) M58MR064 Symbol Alt Parameter 100 Min tAVAV tWC tAVLH 120 Max Min Unit Max Address Valid to Next Address Valid 100 120 ns Address Valid to Latch Enable High 10 10 ns tDVEH tDS Input Valid to Chip Enable High 40 40 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 60 60 ns tELLH Chip Enable Low to Latch Enable High 10 10 ns tGHLL Output Enable High to Latch Enable Low 20 20 ns tLHAX Latch Enable High to Address Transition 10 10 ns tLHEH Latch Enable High to Chip Enable High 10 10 ns tLLLH Latch Enable Pulse Width 10 10 ns VDD High to Chip Enable Low 50 50 µs tVPPHEH VPP High to Chip Enable High 200 200 ns tEHVPPL Chip Enable High to VPP Low 200 200 ns tEHWPV Chip Enable High to Write Protect Valid 200 200 ns 0 0 ns 200 200 ns tVDHEL tWLEL tWPVEH 38/52 tVCS tWS Chip Enable Low to Chip Enable Low Write Protect Valid to Chip Enable High VDD VPP WP G E W L BINV tVDHEL tWLEL tGHLL tELLH tLLLH ADDRESS VALID A16-A21 tAVLH ADDRESS VALID ADQ0-ADQ15 tELEH tLHAX VPP1 VPPH tLHEH tVPPHEH tWPVEH tDVEH tEHWPV tEHEL tEHWH tEHVPPL VALID VALID tEHDX DATA VALID AI90100 M58MR064C, M58MR064D Figure 14. Write AC Waveforms, E Controlled 39/52 M58MR064C, M58MR064D Figure 15. Reset and Power-up AC Waveforms L, W, E, G tPHWL tPHEL tPHGL tPHWL tPHEL tPHGL RP tPLPH tVDHPH VDD, VDDQ Power-up AI90101 Table 31. Reset and Power-up AC Characteristics Symbol tPLPH (1,2) tPHEL tPHLL tPHWL tVDHPH (3) Parameter Test Condition Min Unit 100 ns During Program and Erase 50 µs Other Conditions 30 ns 50 µs RP Pulse Width Reset High to Device Enabled Supply Valid to Reset High Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset. Table 32. Program, Erase Times and Program, Erase Endurance Cycles (TA = –40 to 85°C; VDD = VDDQ = 1.65V to 2.0V, VPP = VDD unless otherwise specified) Max (1) Typ Typical after 100k W/E Cycles Unit Parameter Block (4 K-Word) Erase (Preprogrammed) 2.5 0.5 1 sec Main Block (32 K-Word) Erase (Preprogrammed) 10 1 3 sec Parameter Min Bank Erase (Preprogrammed, Bank A) 4 sec Bank Erase (Preprogrammed, Bank B) 15 sec 40 sec 20 sec Chip Program (2) Chip Program (DPG, VPP = 12V) (2) Word Program (3) 200 10 10 µs Double Word Program 200 10 10 µs Tetra Word Program 200 10 10 µs Program/Erase Cycles (per Block) 100,000 cycles Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or erase should perform significantly better. 2. Excludes the time needed to execute the sequence for program instruction. 3. Same timing value if VPP = 12V. 40/52 M58MR064C, M58MR064D Figure 16. Program Flowchart and Pseudo Code (1) Start Write 40h or 10h Command Program instruction: – write 40h or 10h command – write Address & Data (memory enters read status state after the Program instruction) Write Address & Data do: – read status register (E or G must be toggled) if PES instruction given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If b4 = 1, Program error: – error handler NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 If b1 = 1, Program to protected block error: – error handler YES End AI90102 Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a program sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 41/52 M58MR064C, M58MR064D Figure 17. Double Word Program and Tetra Word Program Flowchart and Pseudo code (1) Start Write 55h Command DPG instruction: – write 30h command – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) (memory enters read status state after the Program instruction) Write Address 1 & Data 1 Write Address 2 & Data 2 TPG instruction: – write 55h command – write Address 1 & Data 1 (4) – write Address 2 & Data 2 (4) – write Address 3 & Data 3 (4) – write Address 4 & Data 4 (4) (memory enters read status state after the Program instruction) Write Address 3 & Data 3 Write Address 4 & Data 4 do: – read status register (E or G must be toggled) if PES instruction given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If b4 = 1, Program error: – error handler NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 If b1 = 1, Program to protected block error: – error handler YES End AI90103 Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a program sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 3. Address 1 and address 2 must be consecutive addresses differing only for address bit A0. 4. Address, address 2, address 3 and address 4 must be consecutive addresses differing only for address bit A1-A0. 42/52 M58MR064C, M58MR064D Figure 18. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command PES instruction: – write B0h command do: – read status register (E or G must be toggled) Write 70h Command Read Status Register b7 = 1 NO while b7 = 1 YES b2 = 1 NO Program Complete If b2 = 0 Program completed YES Write a read Command Read data from another address Write D0h Command Write FFh Command Program Continues Read Data PER instruction: – write D0h command to resume the program – if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI90104 43/52 M58MR064C, M58MR064D Figure 19. Block Erase Flowchart and Pseudo Code Start Write 20h Command EE instruction: – write 20h command – write Block Address (A12-A21) & command D0h (memory enters read status state after the EE instruction) Write Block Address & D0h Command Read Status Register Suspend b7 = 1 do: – read status register (E or G must be toggled) if PES instruction given execute suspend erase loop NO NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error (1) If b3 = 1, VPP invalid error: – error handler YES b4, b5 = 0 If b4, b5 = 1, Command sequence error: – error handler YES b5 = 0 NO Erase Error (1) If b5 = 1, Erase error: – error handler YES b1 = 0 NO Erase to Protected Block Error (1) If b1 = 1, Erase to protected block error: – error handler YES End AI90105 44/52 M58MR064C, M58MR064D Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command PES instruction: – write B0h command do: – read status register (E or G must be toggled) Write 70h Command Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO Erase Complete If b6 = 0, Erase completed YES Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Command Write FFh Command Erase Continues Read Data PER instruction: – write D0h command to resume erasure – if the erase operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI90106 45/52 M58MR064C, M58MR064D Table 33. Command Interface States - Lock table Current State of the Current Partition Current State of the Other Partition Any State Mode Read State Array CFI Electronic Signature Command Input to the Current Partition (and Next State of the Current Partition) Others Erase Read Confirm P/ Read Memory E Resume Status Array BU Register (FFH) Confirm (70h) (D0h) Clear Read Status Read CFI elect. Register (98h) sign. (90h) (50h) SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Read CFI Status Setup Protect Any State Unprotect Lock RCR Error ProtectUnprotectLockBlock Block Block Block Block Block Block ProtectProtectBlock ProtectProtectProtectProtectUnprotect- Unprotect- Protect- Unprotect- Unprotect- Unprotect- UnprotectLockError LockError Unprotect- LockError LockError LockError LockError Write RCR Write RCR LockBlock Write RCR Write RCR Write RCR Write RCR Error Error Error Error Error Error SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Set RCR Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Any State ProgramMultiple Program Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Read Elect. Sign. Program Suspend Read Array, CFI, Elect. Sign., Status SEE MODIFY TABLE PS Read Array Program (Busy) PS Read Status Register PS Read Array PS Read Elect. Sign. PS Read CFI Setup Erase Error Erase Error Erase (Busy) Erase Error Erase Error Erase Error Erase Error Idle Error Any State Block-Bank Erase Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Setup Busy Idle Program Suspend 46/52 Read Array, CFI, Erase Elect. Suspend Sign., Status SEE MADIFY TABLE ES Read Array Erase (Busy) ES Read Array Erase (Busy) ES Read Array ES Read Status Register ES Read Array Read Elect. Sign. ES Read Elect. Sign. Block Write RCR Lock Confirm Confirm (03h) (2Fh) Read Array Read Array Read Array Block Block ProtectProtectUnprotect- UnprotectLockBlock LockBlock Set RCR Block ProtectUnprotectRead CFI Read Array Read Array Read Array LockSetup Write RCR Setup Block ProtectUnprotectRead CFI Read Array Read Array Read Array LockSetup Write RCR Setup Protection Register Erase Suspend Block Protect Confirm (01h) Block ProtectUnprotectRead CFI Read Array Read Array Read Array LockSetup Write RCR Setup Any State Setup Idle Block ProtectUnprotectLock setup write RCR setup (60h) Block ProtectUnprotectLockSetup Write RCR Setup Block ProtectUnprotectLockError Write RCR Error PS Read Array PS Read Array PS Read Array PS Read Array Erase Erase Erase Erase Error Error Error Error Block ProtectUnprotectRead CFI Read Array Read Array Read Array LockSetup Write RCR Setup Block ProtectES Read Unprotect- ES Read CFI LockSetup Array Write RCR Setup ES Read Array ES Read Array M58MR064C, M58MR064D Table 34. Command Interface States - Modify table Current State of the Other Partition Current State of the Current Partition Mode State Read Array, CFI, Electronic Signature, Status Register Setup Busy Idle Erase Suspend Program Suspend Setup Busy Command Input to the Current Partition (and Next State of the Current Partition) Others SEE LOCK TABLE Idle Erase Suspend Program Suspend Setup Idle Erase Suspend Idle ProgramMultiple Program Program Suspend Read Array Read Array Program setup Block Erase Setup Done SEE LOCK TABLE Program Suspend Block-Bank Erase Erase Suspend Program-Erase Suspend (B0h) Read Array OTP Setup (C0h) Multiple Program Setup (30h/55h) Bank Erase Setup (80h) Read Array Read Array Read Array OTP Setup Multiple Program Setup Read Array Read Array Read Array Read Array Read Array Read Array Program setup Block Erase Setup OTP Setup Multiple Program Setup Read Array Read Array Read Array Read Array Read Array Read Array Bank Erase Setup Read Array Read Array Bank Erase Setup Read Array Protection Protection Protection Protection Protection Protection Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Read Array Program Setup Read Array Read Array Block Erase Setup Read Array Read Array OTP Setup Multiple Program Setup Read Array Read Array Read Array Read Array Read Array Bank Erase Setup Read Array Program (Busy) Program (Busy) Program (Busy) PS Read Status Program (Busy) Program (Busy) Program (Busy) Register Read Array Read Array Program Setup Block Erase Setup Read Array Setup Busy Idle Block Erase Setup (20h) Read Array Error, ProtectProtect Idle SEE LOCK UnprotectUnprotect-Lock/ TABLE LockBlock, Set RCR Erase Suspend RCR Program Suspend Setup Idle Protection Register (Busy) Setup Busy Busy Protection Idle Register SEE LOCK Done TABLE Erase Suspend Program Suspend Any State Setup Program (Busy) Idle Busy Setup Busy Program Setup (10h/40h) Read Array Read Array Read Array Read Array OTP Setup Multiple Program Setup Read Array Read Array Read Array Bank Erase Setup Read Array Read Array, CFI, Elect. Sign., Status Register SEE LOCK TABLE Setup SEE LOCK TABLE Erase Error Erase Error Erase Error Erase Error Erase Error Erase Error Busy Erase (Busy) Erase (Busy) Erase (Busy) ES Read Status Register Erase (Busy) Erase (Busy) Erase (Busy) Read Array, CFI, Elect. Sign., Status Register SEE LOCK TABLE PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array ES Read Array ES Read Array Program Setup ES Read Array ES Read Array ES Read Array Multiple ES Read Array Program Setup ES Read Array ES Read Array 47/52 M58MR064C, M58MR064D Table 35. Ordering Information Scheme Example: M58MR064C 100 ZC 6 T Device Type M58 Architecture M = Multiplexed Address/Data, Dual Bank, Burst Mode Operating Voltage R = 1.8V Device Function 064C = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot 064D = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot Speed 100 = 100 ns 120 = 120 ns Package ZC = TFBGA48: 0.5 mm pitch Temperature Range 6 = –40 to 85°C Option T = Tape & Reel packing Devices are shipped from the factory with the memory content bits erased to ’1’. Table 36. Daisy Chain Ordering Scheme Example: M58MR064 -ZC T Device Type M58MR064 Daisy Chain -ZC = TFBGA48: 0.5 mm pitch Option T = Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 48/52 M58MR064C, M58MR064D Table 37. Document Revision History Date Version Revision Details April 2001 -01 First Issue 07-Mar-2002 -02 Document Status changed to Datasheet, CFI information clarified: Table 18,data modified at Offset 13h. Table 19, data modified at Offsets 23h and 24h. Table 22, Offset addresses modified. 49/52 M58MR064C, M58MR064D Table 38. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data Symbol A A1 A2 b D D1 D2 D3 ddd E E1 E2 E3 e FD FD1 FD2 FE FE1 FE2 SD SE millimeters Min 0.950 0.200 Typ 0.790 0.300 10.530 4.500 6.500 8.500 0.250 10.480 – – – 6.290 1.500 3.500 5.500 0.500 3.015 2.015 1.015 2.395 1.395 0.395 0.250 0.250 6.240 – – – – – – – – – – – – Max 1.200 0.300 inches Min 0.0374 0.0079 Typ 0.350 10.580 – – – 0.080 6.340 – – – – – – – – – – – – 0.0311 0.0118 0.4146 0.1772 0.2559 0.3346 0.0098 0.4126 – – – 0.2476 0.0591 0.1378 0.2165 0.0197 0.1187 0.0793 0.0400 0.0943 0.0549 0.0156 0.0098 0.0098 0.2457 – – – – – – – – – – – – Figure 21. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline D D3 D2 D1 FE FE1 FE2 SD E1 e E2 E3 E SE BALL "A1" FD2 FD1 b DUMMY BALLS FD ddd A A1 A2 BGA-Z17 Drawing is not to scale. 50/52 Max 0.0472 0.0118 0.0138 0.4165 – – – 0.0031 0.2496 – – – – – – – – – – – – M58MR064C, M58MR064D Figure 22. TFBGA48 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H AI90107 Figure 23. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B START POINT C D E F G END POINT H AI90108 51/52 M58MR064C, M58MR064D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 52/52