MACH 5 CPLD Family Fifth Generation MACH Architecture FEATURES ◆ High logic densities and I/Os for increased logic integration ◆ ◆ ◆ ◆ ◆ ◆ ◆ — 128 to 512 macrocell densities — 68 to 256 I/Os Wide selection of density and I/O combinations to support most application needs — 6 macrocell density options — 7 I/O options — Up to 4 I/O options per macrocell density — Up to 5 density & I/O options for each package Performance features to fit system needs — 5.5 ns tPD Commercial, 7.5 ns tPD Industrial — 182 MHz fCNT — Four programmable power/speed settings per block Flexible architecture facilitates logic design — Multiple levels of switch matrices allow for performance-based routing — 100% routability and pin-out retention — Synchronous and asynchronous clocking, including dual-edge clocking — Asynchronous product- or sum-term set or reset — 16 to 64 output enables — Functions of up to 32 product terms Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — IEEE 1149.1 compliant for boundary scan testing — 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port — PCI compliant (-5/-6/-7/-10/-12 speed grades) — Safe for mixed supply voltage system design — Bus-Friendly™ Inputs & I/Os — Individual output slew rate control — Hot socketing — Programmable security bit Advanced E2CMOS process provides high performance, cost effective solutions Supported by ispDesignEXPERT™ software for rapid logic development — Supports HDL design methodologies with results optimized for MACH 5 devices — Flexibility to adapt to user requirements — Software partnerships that ensure customer success Lattice and Third-party hardware programming support — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# 20446 Amendment/0 Rev: I Issue Date: September 2000 Table 1. MACH 5 Device Features 1 Feature Supply Voltage (V) M5-128/1 M5LV-128 M5-192/1 M5-256/1 M5LV-256 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 Macrocells 128 128 192 256 256 320 320 384 384 512 512 Maximum User I/O Pins 120 120 120 160 160 192 192 160 192 256 256 6.52 6.52 6.52 6.52 6.52 tPD (ns) 5.5 5.5 5.5 5.5 5.5 6.52 tSS (ns) 3.0 3.0 3.0 3.0 3.0 3.02 3.02 3.02 3.02 3.02 3.02 tCOS (ns) 4.5 4.5 4.5 4.5 4.5 5.02 5.02 5.02 5.02 5.02 5.02 1672 1672 1672 1672 1672 fCNT (MHz) 182 182 182 182 182 1672 Typical Static Power (mA) 35 35 45 55 55 70 70 75 75 100 100 IEEE 1149.1 Boundary Scan Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PCI-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note: 1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices. 2. Preliminary specifications for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now. GENERAL DESCRIPTION The MACH® 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation. Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification. 2 MACH 5 Family Table 2. MACH 5 Speed Grades Speed Grade1 Device -5 -6 M5-1282 -7 -10 -12 -15 -20 C C, I C, I C, I I I M5-128/1 C C, I C, I C, I C, I M5LV-128 C C,I C, I C, I I M5-192/1 C C, I C, I C, I C, I I C C, I C, I C, I I I M5-2562 M5-256/1 C C, I C, I C, I C, I M5LV-256 C C, I C, I C, I I M5-320 C C, I C, I C, I C, I I M5LV-320 C C, I C, I C, I C, I I M5-384 3 C C, I3 C, I C, I C, I I M5LV-384 C3 C, I3 C, I C, I C, I I M5-512 C3 C, I3 C, I C, I C, I I M5LV-512 C3 C, I3 C, I C, I C, I I Note: 1. C = Commercial grade, I = Industrial grade 2. /1 version recommended for new designs 3. Preliminary specificatons With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512 macrocells to support full system logic integration. Extensive routing resources ensure pinout retention as well as high utilization. It is ideal for PAL® block device integration and a wide range of other applications including high-speed computing, low-power applications, communications, and embedded control. At each macrocell density point, Lattice offers several I/O and package options to meet a wide range of design needs (Table 3). Table 3. MACH 5 Package and I/O Options 1 M5-128/1 M5LV-128 Supply Voltage M5-192/1 M5-256/1 M5LV-256 5 3.3 5 5 3.3 100-pin TQFP 68 68, 74 68 68 68*, 74 100-pin PQFP 68 68* 68* 68* 68 144-pin TQFP 104 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 5 3.3 5 3.3 5 3.3 104 144-pin PQFP 104 104* 104* 104* 104* 160-pin PQFP 120 120 120 120 120 120* 120 120* 120 120* 120 160 160 160 160 160 160 160 160 240-pin PQFP 184* 184* 184* 184* 184* 184* 256-ball BGA 192 192* 192* 192* 192* 192* 256 256 208-pin PQFP 352-ball BGA Note: 1. The I/O options indicated with a “*” are obsolete, please contact factory for more information. MACH 5 Family 3 Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test Access Port (TAP) interface. FUNCTIONAL DESCRIPTION The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the segments together. The only logic difference between any two MACH 5 devices is the number of segments. Therefore, once a designer is familiar with one device, consistent performance can be expected across the entire family. All devices have four clock pins available which can also be used as logic inputs. CLK Block: 16 MCs Block Interconnect Segment: 4 Blocks 4 Segment Interconnect 20446G-001 Figure 1. MACH 5 Block Diagram The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an independent PAL device, it has superior control and logic generation capabilities. ◆ I/O cells ◆ Product-term array and Logic Allocator ◆ Macrocells ◆ Register control generator ◆ Output enable generator I/O Cells The I/Os associated with each PAL block have a path directly back to that PAL block called local feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide connections between any two signals in a device. The block feeder assigns block interconnect lines and local feedback lines to the PAL block inputs. 4 MACH 5 Family 2 OE Generator Control Generator 32 Input Register Path I/Os 16 Macrocells 32 Local Feedback Block Interconnect Product-term Array Logic Alocator 32 Block Feeder 2 Interconnect Feeder 20446G-002 Figure 2. PAL Block Structure Product-Term Array and Logic Allocator The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluster is a sumof-products function with either 3 of 4 product terms. Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If only three product terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation and/or polarity control. The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the MACH 5 device allows for the implementation of large equations (up to 32 product terms) with only one pass through the logic array. Table 4. Product Term Steering Options for PT Clusters and Macrocells Macrocell Available Clusters Macrocell Available Clusters M0 C0, C1, C2, C3, C4 M8 C5, C6, C7, C8, C9, C10, C11, C12 M1 C0, C1, C2, C3, C4, C5 M9 C6, C7, C8, C9, C10, C11, C12, C13 M2 C0, C1, C2, C3, C4, C5, C6 M10 C7, C8, C9, C10, C11, C12, C13, C14 M3 C0, C1, C2, C3, C4, C5, C6, C7 M11 C8, C9, C10, C11, C12, C13, C14, C15 M4 C0, C1, C2, C3, C4, C5, C6, C7 M12 C8, C9, C10, C11, C12, C13, C14, C15 M5 C1, C2, C3, C4, C5, C6, C7, C8 M13 C9, C10, C11, C12, C13, C14, C15 M6 C2, C3, C4, C5, C6, C7, C8, C9 M14 C10, C11, C12, C13, C14, C15 M7 C3, C4, C5, C6, C7, C8, C9, C10 M15 C11, C12, C13, C14, C15 MACH 5 Family 5 Macrocells The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be configured as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell. Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In order to use this option, these macrocells must be accessed via the I/O pins associated with macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be used as “buried” macrocells to drive device logic via the matrix. Control Bus Macrocell Logic Allocator 5-8 Clusters/ MC D Prog. Polarity Q Mode Selection 20446G-003 Figure 3. Macrocell Diagram Control Generator The control generator provides four configurable clock lines and three configurable set/reset lines to each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can be independently selected by any flip-flop within a block. The clock lines can be configured to provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks, and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks and one sum-term clock, are available per PAL block. Positive or negative edge clocking is available as well as advanced clocking features such as complementary and biphase clocking. Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful in applications such as fast data paths. A biphase clock line clocks flip-flops on both the positive and negative edges of the clock. The configuration options for the four clock lines per PAL block are as follows: Clock Line 0 Options ◆ Global clock (0, 1, 2, or 3) with positive or negative edge clock enable ◆ Product-term clock (A*B*C) ◆ Sum-term clock (A+B+C) 6 MACH 5 Family Clock Line 1 Options ◆ Global clock (0, 1, 2, or 3) with positive edge clock enable ◆ Global clock (0, 1, 2, or 3) with negative edge clock enable ◆ Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase) Clock Line 2 Options ◆ Global clock (0, 1, 2, or 3) with clock enable Clock Line 3 Options ◆ Complement of clock line 2 (same clock enable) ◆ Product-term clock (if clock line 2 does not use clock enable PT (0:3) PINCLK (0:3) MUX 4TO1 0 1 2 3 IN (0) IN (1) IN (2) OUT IN (3) U1 F1 F0 MUX 2TO1 MUX 2TO1 CLKIN Clock Enable PT0 N (0) /CLK OUT N (1) F0 CLK0 F0 PT (0:2) SET0/RST0 PT0 MUX 4TO1 0 1 2 3 IN (0) IN (1) IN (2) OUT IN (3) U2 F1 F0 /CLK MUX 2TO1 CLK1 CLK PT1 PT1 OUT OUT /PT1(ST) CLKEN1 BIPHASE CLKEN2 PT2 PT1 SET1/RST1 F0 MUX 2TO1 PT2 MUX 4TO1 0 1 2 3 PT2 OUT IN (0) IN (1) IN (2) OUT IN (3) U3 F1 F0 CLK2 SET2/RST2/LE /PT2 CLKIN Clock Enable F0 Block Sets/Reset 0–2, LE MUX 2TO1 PT3 MUX 2TO1 /CLK2 PTCLK F0 CLK3 Block Clocks 0–3 20446G-004 Figure 4. Clock Generator 20446G-005 Figure 5. Set/Reset Generator The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all. All three lines can be configured for product term set/reset and two of the three lines can be configured as sum term set/reset and one of the lines can be configured as product-term or sumterm latch enable. While the set/reset signals are generated in the control generator, whether that signal sets or resets a flip-flop is determined within the individual macrocell. The same signal can set one flip-flop and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells configured as latches. MACH 5 Family 7 OE Generator There is one output enable (OE) generator per PAL block that generates two product-term driven output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can choose to be permanently enabled, permanently disabled, or choose one of the two product term output enables per PAL block (Figure 6). Output Enable Generator VCC Internal Feedback External Feedback 20446G-006 Figure 6. Output Enable Generator and I/O Cell 8 MACH 5 Family MACH 5 TIMING MODEL The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing model is shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters. (External Feedback) (Internal Feedback) COMB/DFF/ LATCH IN INPUT REG/ INPUT LATCH tSIR (S/A) tHIR (S/A) tSIL tHIL tSRR tCES tCEH CE tBLK tSEG tCO (S/A) i Q tPDILi tGOAi tSRi tPL1 tPL2 tPL3 tPT tS (S/A) tH (S/A) tSAL tHAL tSRR tCES tCEH CE tPDi tCO (S/A) i Q tPDLi tGOAi tSRi SR tSLW OUT tBUF tEA tER SR PIN CLK 20446G-014 Figure 7. MACH 5 Timing Model MACH 5 Family 9 MULTIPLE I/O AND DENSITY OPTIONS The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers to choose a device close to their logic density and I/O requirements, thus minimizing costs. For the same package type, every density has the same pin-out. With proper design considerations, a design can be moved to a higher or lower density part as required. IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan Test Access Port as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. MACH 5 devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO software takes the JEDEC file output produced by design implementation software, along with information about the Boundary Scan chain, and creates a set of vectors that are used to drive the Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equipment can then be used to program MACH 5 devices during the testing of a circuit board. PCI COMPLIANT MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. MACH 5 devices provide the speed, drive, density, output enables and I/Os for the most complex PCI designs. 10 MACH 5 Family SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1 Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the 3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixedvoltage design capability. Note: 1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”. BUS-FRIENDLY INPUTS AND I/OS All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is a good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. In large designs, there may be several different speed requirements for different portions of the design. Table 5. Power Levels High Speed/High Power 100% Power Medium High Speed/Medium High Power 67% Power Medium Low Speed/Medium Low Power 40% Power Low Speed/Low Power 20% Power PROGRAMMABLE SLEW RATE Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee MACH 5 Family 11 initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. 12 MACH 5 Family MACH 5 PAL BLOCK 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 Output Enable Output Enable M0 Macro cell I/O Cell I/O M1 Macro cell I/O Cell I/O M2 Macro cell I/O Cell I/O M3 Macro cell I/O Cell I/O M4 Macro cell I/O Cell I/O I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O Macro cell I/O Cell I/O 0 C0 C1 C2 Macro cell M5 C4 C5 C6 Switch Matrix C7 C8 C9 C10 C11 Logic Allocator C3 M6 M7 M8 M9 C12 C13 M10 C14 C15 63 Macro cell M11 M12 M13 M14 M15 7 16 16 Control Generator 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 4 32 20446G-015 CLK MACH 5 Family 13 BLOCK DIAGRAM — M5(LV)-128/XXX SEGMENT 0 Block A/Macrocells 0-15 Block D/Macrocells 0-15 16 16 16 16 I/O Cells I/O Cells 2 PT OE 2 PT OE 2 16 Macrocells 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 32 2 Control Generator Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 32 7 PT 16 Macrocells 32 7 PT 32 I0, 1 Block Interconnect 2 32 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 64 PT 32 Macrocells Macrocells 2 2 PT OE I/O Cells Control 7 Generator 16 2 PT OE I/O Cells 16 16 16 16 Block C/Macrocells 0-15 Block B/Macrocells 0-15 CLK0 CLK1 CLK2 CLK3 7 PT 64 PT 32 Control 7 Generator 16 2 64 x 73 AND Logic Array and Logic Allocator S E G M E NT I NT E R C O N N E CT 4 Block D/Macrocells 0-15 Block A/Macrocells 0-15 16 16 16 16 I/O Cells I/O Cells 2 PT OE 2 PT OE 2 16 Macrocells 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 32 2 Control Generator Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 32 7 PT 16 Macrocells 7 PT 32 32 I2, 3 Block Interconnect 2 32 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 64 PT 32 Macrocells 2 16 64 x 73 AND Logic Array and Logic Allocator Macrocells 2 2 PT OE I/O Cells 16 Control 7 Generator 2 PT OE I/O Cells 16 16 16 16 Block B/Macrocells 0-15 Block C/Macrocells 0-15 SEGMENT 1 14 7 PT 64 PT 32 Control 7 Generator MACH 5 Family 20446G-007 CLK0 CLK1 CLK2 CLK3 4 I0 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 2 2 16 16 I/O Cells 16 Macrocells 64 PT I1 7 PT 7 PT MACH 5 Family 2 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 32 16 2 2 2 64 PT 16 I/O Cells 16 Macrocells SEGMENT 1 16 I/O Cells 16 Macrocells 64 PT 2 PT OE Control 7 Generator 7 PT 7 PT 7 PT 7 PT 32 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 2 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells 2 PT OE Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 16 I/O Cells Block B/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 I2, I3 32 16 Block A/Macrocells 0-15 S E G M E NT I NT E R C O N N E CT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 0 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 BLOCK DIAGRAM — M5-192/XXX 20446G-008 15 16 CLK0 CLK1 CLK2 CLK3 I0 4 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 I1 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT MACH 5 Family 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT I3 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 1 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 32 I2 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 2 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 3 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 S E G M E NT I NT E R C O N N E CT Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 0 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 BLOCK DIAGRAM — M5(LV)-256/XXX 20446G-009 MACH 5 Family I1 CLK0 CLK1 CLK2 CLK3 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 7 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 1 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 32 2 2 16 7 16 I/O Cells 16 Macrocells 64 PT I2 7 PT 7 PT 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 2 16 7 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 2 2 16 7 16 I/O Cells 16 Macrocells 64 PT 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 2 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 16 I/O Cells I3 2 PT OE 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 3 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 S E G M E NT I NT E R C O N N E CT Block D/Macrocells 0-15 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 4 Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 0 Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 2 16 I/O Cells Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 4 I0 32 16 Block A/Macrocells 0-15 BLOCK DIAGRAM — M5(LV)-320/XXX 20446G-010 17 18 CLK0 CLK1 CLK2 CLK3 I0 4 2 2 7 16 I/O Cells 16 Macrocells 64 PT I1 7 PT 7 PT MACH 5 Family 2 64 PT 16 I/O Cells 16 Macrocells 7 16 I/O Cells 16 Macrocells 64 PT 2 PT OE I3 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 1 2 PT OE 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 7 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 64 PT 16 I/O Cells 16 Macrocells 7 16 I/O Cells 16 Macrocells 64 PT 32 16 2 2 7 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE I2 2 64 PT 16 I/O Cells 16 Macrocells 7 16 I/O Cells 16 Macrocells 64 PT 32 16 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 2 SEGMENT 3 2 PT OE Control 7 Generator 7 PT 7 PT 2 PT OE Block D/Macrocells 0-15 Block Interconnect 2 PT OE 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 16 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 4 Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 SEGMENT 2 2 PT OE Control 7 Generator 7 PT 7 PT 2 PT OE 32 32 16 16 Block A/Macrocells 0-15 S E G M E NT I NT E R C O N N E CT Block Interconnect 2 PT OE 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 16 Block D/Macrocells 0-15 SEGMENT 5 Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 7 PT 7 PT 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells 2 PT OE Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 16 Block D/Macrocells 0-15 SEGMENT 0 Control Generator 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 16 Block A/Macrocells 0-15 BLOCK DIAGRAM — M5(LV)-384/XXX 20446G-011 CLK0 CLK1 CLK2 CLK3 I0 4 2 2 16 16 I/O Cells 16 Macrocells 64 PT I1 7 PT 7 PT MACH 5 Family 2 64 PT 16 I/O Cells 16 Macrocells 16 I/O Cells 16 Macrocells 64 PT 2 PT OE 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 1 2 PT OE 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 64 PT 16 I/O Cells 16 Macrocells 16 I/O Cells 16 Macrocells 64 PT 32 16 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 7 PT Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells 2 PT OE S E G M E NT Block C/Macrocells 0-15 16 32 2 SEGMENT 2 2 PT OE Control 7 Generator 7 PT 7 PT 2 PT OE Block D/Macrocells 0-15 Block Interconnect 2 PT OE 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 16 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 7 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 7 PT 7 PT 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells 2 PT OE Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 16 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 0 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 BLOCK DIAGRAM — M5(LV)-512/XXX Continued 20446G-012 19 20 2 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT MACH 5 Family 2 64 PT 16 I/O Cells 16 Macrocells 16 I/O Cells 16 Macrocells 64 PT 2 PT OE 32 16 2 16 I/O Cells 16 Macrocells 64 PT SEGMENT 3 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator I3 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block C/Macrocells 0-15 16 32 2 I/O Cells 16 Block D/Macrocells 0-15 Block Interconnect 2 PT OE Control 7 Generator 7 PT 7 PT 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells 2 PT OE Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 16 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 I NT E R C O N N E CT 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 6 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 2 2 16 16 I/O Cells 16 Macrocells 64 PT I2 7 PT 7 PT 2 64 PT 16 I/O Cells 16 Macrocells 16 I/O Cells 16 Macrocells 64 PT 32 16 2 16 16 I/O Cells 16 Macrocells 64 PT 7 PT 7 PT 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block C/Macrocells 0-15 16 32 2 SEGMENT 4 2 PT OE Control 7 Generator 7 PT 7 PT 2 PT OE Block D/Macrocells 0-15 Block Interconnect 2 PT OE 7 PT 7 PT Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Control Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 2 16 I/O Cells Block C/Macrocells 0-15 16 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells Block B/Macrocells 0-15 16 32 32 2 I/O Cells 16 Block A/Macrocells 0-15 16 32 Block Interconnect 2 PT OE Control 7 Generator 64 x 73 AND Logic Array and Logic Allocator 32 32 2 PT OE 16 Block D/Macrocells 0-15 SEGMENT 5 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells I/O Cells Block B/Macrocells 0-15 16 32 32 16 Block A/Macrocells 0-15 BLOCK DIAGRAM — M5(LV)-512/XXX Continued 20446G-013 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M5 Commercial (C) Devices Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C Device Junction Temperature (Note 1) . . . . . . . . . . . +130°C or +150°C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (-40°C to +85°C) . . . . . . . . . . 200 mA Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 5-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Typ Max Unit Output HIGH Voltage (For M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384, M5-512 Devices) IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL Output HIGH Voltage (For M5-128, M5-192, M5-256 Devices) IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOH = -2.5 mA, VCC = 5.25 V, VIN = VIH or VIL 3.6 V VOL Output LOW Voltage (Note 2) IOL = +16 mA, VCC = Min, VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 3) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 3) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25, VCC = Max (Note 4) 10 µA IIL Input LOW Leakage Current VIN = 0, VCC = Max (Note 4) -10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25, VCC = Max, VIN = VIH or VIL (Note 4) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 4) -10 µA ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 5) -180 mA VOH 2.4 IOH = 0 mA, VCC = Max, VIN = VIH or VIL V 3.3 V 2.4 V 2.0 -30 V Note: 1. 150° for M5-128, M5-192 and M5-256 devices. 130° for M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384 and M5-512 devices. 2. Total IOL between ground pins should not exceed 64 mA. 3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 4. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH. 5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. MACH 5 Family 21 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M5LV Commercial (C) Devices Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Device Junction Temperature . . . . . . . . . . . . . +130°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Industrial (I) Devices Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C Latchup Current (-40°C to +85°C) . . . . . . . . . . 200 mA Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 3.3-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Max Unit VCC = Min IOH = -100 µA VCC -0.2 V VIN = VIH or VIL IOH = 3.2 mA 2.4 V Output LOW Voltage VCC = Min VIN = VIH or VIL IOL = 100 µA VIH Input HIGH Voltage VOUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) 2.0 VIL Input LOW Voltage VOUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) -0.3 IIH Input HIGH Leakage Current IIL IOZH VOH Output HIGH Voltage VOL 0.2 V 0.5 V 5.5 V 0.8 V VIN = 3.6, VCC = Max (Note 3) 10 µA Input LOW Leakage Current VIN = 0, VCC = Max (Note 3) -10 µA Off-State Output Leakage Current HIGH VOUT = 3.6, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 3) -10 µA ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 4) -160 mA IOL = 16 mA (Note 1) -15 Notes: 1. Total IOL between ground pins should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH. 4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second. 22 MACH 5 Family M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 -5 Min -6 Max Min -7 Max Min -10 Max Min -12 Max Min -15 Max Min -20 Max Min Max Unit Combinatorial Delay: tPDi Internal combinatorial propagation delay 3.5 4.5 5.5 8.0 10.0 13.0 18.0 ns tPD Combinatorial propagation delay 5.5 6.5 7.5 10.0 12.0 15.0 20.0 ns Registered Delays: tSS Synchronous clock setup time 3.0 3.0 4.0 5.0 6.0 8.0 10.0 ns tSA Asynchronous clock setup time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHA Asynchronous clock hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns tCOSi Synchronous clock to internal output 2.5 3.0 4.0 5.0 6.0 8.0 10.0 ns tCOS Synchronous clock to output 4.5 5.0 6.0 7.0 8.0 10.0 12.0 ns tCOAi Asynchronous clock to internal output 6.0 6.0 8.0 10.0 13.0 15.0 18.0 ns tCOA Asynchronous clock to output 8.0 8.0 10.0 12.0 15.0 17.0 20.0 ns Latched Delays: tSAL Latch setup time 3.0 4.0 4.0 tHAL Latch hold time 3.0 tPDLi Transparent latch internal 6.0 7.0 7.0 8.0 9.0 10.0 10.0 ns tPDL Propagation delay through transparent latch 8.0 9.0 9.0 10.0 11.0 12.0 12.0 ns tGOAi Gate to internal output 7.0 8.0 8.0 9.0 10.0 11.0 12.0 ns tGOA Gate to output 9.0 10.0 10.0 11.0 12.0 13.0 14.0 ns 3.0 5.0 4.0 6.0 5.0 7.0 6.0 8.0 7.0 ns 8.0 ns Input Register Delays: tSIRS Input register setup time using a synchronous clock 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns tSIRA Input register setup time using an asynchronous clock 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHIRS Input register hold time using a synchronous clock 3.0 3.0 3.0 4.0 4.0 4.0 4.0 ns tHIRA Input register hold time using an asynchronous clock 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns Input Latch Delays: tSIL Input latch setup time 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns tHIL Input latch hold time 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns tPDILi Transparent input latch 5.0 5.0 5.5 6.0 6.0 6.0 6.0 ns Output Delays: tBUF Output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns tSLW Slow slew rate delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns tEA Output enable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns tER Output disable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns MACH 5 Family 23 M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 Min -6 Max Min -7 Max Min -10 Max Min -12 Max Min -15 Max Min -20 Max Min Max Unit Power Delays: tPL1 Power level 1 delay (Note 2) 4.0 (5.0) 4.0 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) ns tPL2 Power level 2 delay (Note 2) 6.0 (9.0) 6.0 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) ns tPL3 Power level 3 delay (Note 2) 9.0 9.0 (17.5) 9.0 9.0 9.0 9.0 9.0 (17.5) (17.5) (17.5) (17.5) (17.5) ns Additional Cluster Delay: tPT Product term cluster delay 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns Interconnect Delays: tBLK Block interconnect delay 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns tSEG Segment interconnect delay 4.5 4.5 5.0 6.0 6.0 6.0 6.0 ns Reset and Preset Delays: tSRi Asynchronous reset or preset to internal register output 6.0 8.0 8.0 10.0 12.0 14.0 16.0 ns tSR Asynchronous reset or preset to register output 8.0 10.0 10.0 12.0 14.0 16.0 18.0 ns tSRR Reset and set register recovery time 5.5 7.5 7.5 8.0 9.0 10.0 11.0 ns tSRW Asynchronous reset or preset width 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns Clock Enable Delays: tCES Clock enable setup time 4.0 5.0 5.0 6.0 7.0 7.0 8.0 ns tCEH Clock enable hold time 3.0 4.0 4.0 5.0 6.0 6.0 7.0 ns tWLS Global clock width low (Note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns tWHS Global clock width high (Note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns Width: tWLA Product term clock width low 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns tWHA Product term clock width high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns tGWA Gate width low (for low transparent) or high (for high transparent) 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns tWIR Input register clock width low or high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns 24 MACH 5 Family M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 Min -6 Max Min -7 Max Min -10 Max Min Max -12 Min Max -15 Min Max -20 Min Max Unit Frequency: fMAX fMAXA fMAXI External feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) 133 125 100 83.3 71.4 55.6 45.5 MHz Internal feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS +tCOSi) 182 167 125 100 83.3 62.5 50.0 MHz No feedback PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tHS) 200 167 167 125 100 83.3 83.3 MHz External feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA) 91 91 71.4 58.8 47.6 41.7 35.7 MHz Internal feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA +tCOAi) 111 111 83.3 66.7 52.6 45.5 38.5 MHz No feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tHA) 167 125 125 100 83.3 71.4 62.5 MHz Maximum input register frequency 1/(tSIRS+tHIRS) or 1/(2 x tWICW) 167 125 125 100 83.3 71.4 62.5 MHz Notes: 1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site. 2. Numbers in parentheses are for M5-128, M5-192, M5-256. 3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2). MACH 5 Family 25 CAPACITANCE1 Parameter Description Parameter Symbol Test conditions Typ Unit CIN I/CLK pin VIN =2.0 V 3.3 V or 5 V, 25º C, 1 MHz 12 pF CI/O I/O pin VOUT =2.0 V 3.3 V or 5 V, 25º C, 1 MHz 10 pF 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where these parameters may be affected. ICC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book CD-ROM or Lattice web site. ICC CURVES AT HIGH /LOW POWER MODES VCC = 5 V or 3.3 V, TA = 25º C M5(LV)-512 high power 700 600 M5(LV)-384 high power 500 ICC (mA) M5(LV)-320 high power M5-256/1 and M5LV-25 high power 400 300 M5-192/1 high power M5-128/1 and M5LV-128 high power M5(LV)-512 low power M5(LV)-384 low power M5(LV)-320 low power M5-256/1 and M5LV-256 low power M5-192/1 low power 200 100 M5-128/1 and M5LV-128 low power Frequency (MHz) Figure 8. ICC Curves at High/Low Power Modes 26 MACH 5 Family 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 20446G-048 VCC = 5 V, TA = 25º C 700 M5-256 high power 600 M5-192 high power 400 M5-128 high power 300 200 M5-256 low power M5-192 low power M5-128 low power 100 Frequency (MHz) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 ICC (mA) 500 20446G-049 Figure 9. ICC Curves at High/Low Power Modes MACH 5 Family 27 100-PIN PQFP CONNECTION DIAGRAM Top View 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 M5-128 M5LV-128* M5-192* M5-256* M5LV-256 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND GND TDO I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I3/CLK3 GND GND VCC VCC I2/CLK2 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 TMS GND GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 2A12 2B13 2B12 2B11 2B8 2B7 2B4 2B3 2B2 0D14 0C13 0C12 0C11 0C8 0C7 0C4 0C3 0C2 2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12 2C2 2C3 2C4 2C7 2C8 2C11 2C12 2C13 2D12 1C2 1C3 1C4 1C7 1C8 1C11 1C12 1C13 1D14 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 M5-128 M5LV-128* 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 M5-192* 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 M5-256* M5LV-256 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 GND GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 VCC VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK GND GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 VCC GND GND VCC I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 M5-256* M5LV-256 0A13 0A12 0A11 0A8 0A7 0A4 0A3 0A2 M5-192* 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 M5-128 M5LV-128* 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 100-Pin PQFP (68 I/O) M5-256* M5LV-256 M5-192* M5-128 M5LV-128* *Package obsolete, contact factory. 20446G-016 Pin Designations CLK GND I I/O NC 28 = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 100-PIN TQFP CONNECTION DIAGRAM – 68 I/O Top View 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 M5-192 M5-256 M5LV-256* 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND GND NC I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 VCC GND GND VCC NC I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 M5-256 M5LV-256* M5-128 M5LV-128 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 M5-192 0A13 0A12 0A11 0A8 0A7 0A4 0A3 0A2 M5-128 M5LV-128 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 100-Pin TQFP (68 I/O) 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND TDO I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I3/CLK3 GND VCC I2/CLK2 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 TMS 3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 2A12 2B13 2B12 2B11 2B8 2B7 2B4 2B3 2B2 0D14 0C13 0C12 0C11 0C8 0C7 0C4 0C3 0C2 2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12 2C2 2C3 2C4 2C7 2C8 2C11 2C12 2C13 2D12 1C2 1C3 1C4 1C7 1C8 1C11 1C12 1C13 1D14 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 M5-128 M5LV-128 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 M5-192 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 M5-256 M5LV-256* 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 GND GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 NC VCC GND GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 GND GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 M5-256 M5LV-256* M5-192 M5-128 M5LV-128 *Package obsolete, contact factory. 20446G-017 Pin Designations CLK GND I I/O NC = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 29 100-PIN TQFP CONNECTION DIAGRAM – 74 I/O Top View 0D1 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 3D12 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 M5LV-128 M5LV-256 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 GND M5LV-256 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A4 0A3 0A2 M5LV-128 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D11 0D12 100-Pin TQFP (74 I/O) 0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND TDO I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I3/CLK3 GND VCC I2/CLK2 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 TMS 3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 0D14 0C13 0C12 0C11 0C8 0C7 0C4 0C3 0C2 2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12 1C2 1C3 1C4 1C7 1C8 1C11 1C12 1C13 1D14 M5LV-256 M5LV-128 GND 1A13 1A7 I/O18 1A12 1A6 I/O19 1A11 1A5 I/O20 1A10 1A4 I/O21 1A8 1A3 I/O22 1A7 1A2 I/O23 1A4 1A1 I/O24 1A3 1A0 I/O25 1A2 1D11 I/O26 1A1 1D12 1/O27 VCC GND GND VCC 1D2 2D12 I/O28 1D3 2A0 I/O29 1D4 2A1 I/O30 1D7 2A2 I/O31 1D8 2A3 I/O32 1D10 2A4 I/O33 1D11 2A5 I/O34 1D12 2A6 I/O35 1D13 2A7 1/O36 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2 M5LV-256 M5LV-128 20446G-018 Pin Designations CLK GND I I/O NC 30 = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 144-PIN PQFP CONNECTION DIAGRAM Top View 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D10 0D11 0D12 0D13 0D8 0D11 0D12 0D13 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A10 2A11 3D12 3D11 3D8 3D7 3D4 3D3 M5-128 M5LV-128* M5-192* M5-192* M5-256* M5LV-256* 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND VCC I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 GND I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 VCC GND GND VCC I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 GND I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 VCC GND M5-256* M5LV-256* M5-128 M5LV-128* 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A5 0A4 0A3 0A2 0A1 0A0 0A3 0A2 0D2 0D3 0D4 0D7 0D3 0D4 0D7 0D8 0D11 0D12 0A13 0A12 0A11 A10 0A8 0A7 0A6 0A11 0A10 0A8 0A7 0A6 0A5 0A4 0A7 0A6 0A5 0A4 0A3 0A2 0A1 144-Pin PQFP 0A12 0A13 0A14 0B13 0B12 0A8 0A9 0A10 0A11 0A12 0B8 0B7 0B6 0B5 0B11 0B8 0B5 0B4 0B13 0B12 0B11 0B8 0B4 0B3 0B2 0B1 0B3 0B2 0B1 0B0 0B5 0B4 0B3 0B2 1B1 1B2 1B3 1B4 1B0 1B1 1B2 1B3 1B2 1B3 1B4 1B5 1B5 1B6 1B7 1B8 1B4 1B5 1B8 1B11 1B8 1B11 1B12 1B13 1B10 1B11 1B12 1B13 1A14 1B12 1B13 1A14 1A13 1A12 1A12 1A11 1A10 1A9 1A8 TDI I/O0 I/O1 I/O2 I/O3 I/O4 GND I/O5 I/O6 I/O7 I/O8 GND I/O9 I/O10 I/O11 I/O12 I0/CLK0 VCC GND I1/CLK1 I/O13 I/O14 I/O15 I/O16 GND I/O17 I/O18 I/O19 I/O20 GND I/O21 I/O22 I/O23 I/O24 I/O25 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TDO I/O77 I/O76 I/O75 I/O74 I/O73 GND I/O72 I/O71 I/O70 I/O69 GND I/O68 I/O67 I/O66 I/O65 I3/CLK3 GND VCC I2/CLK2 I/O64 I/O63 I/O62 I/O61 GND I/O60 I/O59 I/O58 I/O57 GND I/O56 I/O55 I/O54 I/O53 I/O52 TMS 3A8 3A9 3A10 3A11 3A12 2A12 2A13 2A14 2B13 2B12 0D14 0C13 0C12 0C11 0C10 3B13 3B12 3B11 3B8 2B11 2B8 2B5 2B4 0C8 0C7 0C6 0C5 3B5 3B4 3B3 3B2 2B3 2B2 2B1 2B0 0C4 0C3 0C2 0C1 2B2 2B3 2B4 2B5 2C0 2C1 2C2 2C3 1C1 1C2 1C3 1C4 2B8 2B11 2B12 2B13 2C4 2C5 2C8 2C11 1C5 1C6 1C7 1C8 2A12 2A11 2A10 2A9 2A8 2C12 2C13 2D14 2D13 2D12 1C10 1C11 1C12 1C13 1D14 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1D3 1D4 1D7 1D8 1D11 1D12 2D12 2D11 2D8 2D7 2D4 2D3 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A3 1A2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D10 2D11 1A5 1A4 1A3 1A2 1A1 1A0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D10 1D11 1D12 1D13 M5-192* M5-128 M5LV-128* 1A11 1A10 1A8 1A7 1A6 1A5 1A4 M5-256* M5LV-256* 1A13 1A12 1A11 1A10 1A8 1A7 1A6 GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 GND I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 VCC GND GND VCC I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 GND I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 0A14 0B13 0B12 0B11 0B10 M5-256* M5LV-256* M5-192* M5-128 M5LV-128* *Package obsolete, contact factory. 20446G-019 Pin Designations CLK GND I I/O NC = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 31 144-PIN TQFP CONNECTION DIAGRAM Top View 0D6 0D7 0D8 0D10 0D11 0D12 0D13 0D0 0D1 0D2 0D3 0D4 0D5 3D12 3D11 3D8 3D7 3D4 3D3 M5LV-256 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A5 0A4 0A3 0A2 0A1 0A0 0D3 0D4 0D7 0D8 0D11 0D12 M5LV-128 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND VCC I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 GND I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 VCC GND GND VCC I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 GND I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 VCC GND M5LV-256 0A13 0A12 0A11 A10 0A8 0A7 0A6 M5LV-128 0A7 0A6 0A5 0A4 0A3 0A2 0A1 144-Pin TQFP 0A8 0A9 0A10 0A11 0A12 0B8 0B7 0B6 0B5 0B13 0B12 0B11 0B8 0B4 0B3 0B2 0B1 0B5 0B4 0B3 0B2 1B1 1B2 1B3 1B4 1B2 1B3 1B4 1B5 1B5 1B6 1B7 1B8 1B8 1B11 1B12 1B13 1B10 1B11 1B12 1B13 1A14 1A12 1A11 1A10 1A9 1A8 TDI I/O0 I/O1 I/O2 I/O3 I/O4 GND I/O5 I/O6 I/O7 I/O8 GND I/O9 I/O10 I/O11 I/O12 I0/CLK0 VCC GND I1/CLK1 I/O13 I/O14 I/O15 I/O16 GND I/O17 I/O18 I/O19 I/O20 GND I/O21 I/O22 I/O23 I/O24 I/O25 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TDO I/O77 I/O76 I/O75 I/O74 I/O73 GND I/O72 I/O71 I/O70 I/O69 GND I/O68 I/O67 I/O66 I/O65 I3/CLK3 GND VCC I2/CLK2 I/O64 I/O63 I/O62 I/O61 GND I/O60 I/O59 I/O58 I/O57 GND I/O56 I/O55 I/O54 I/O53 I/O52 TMS 3A8 3A9 3A10 3A11 3A12 0D14 0C13 0C12 0C11 0C10 3B13 3B12 3B11 3B8 0C8 0C7 0C6 0C5 3B5 3B4 3B3 3B2 0C4 0C3 0C2 0C1 2B2 2B3 2B4 2B5 1C1 1C2 1C3 1C4 2B8 2B11 2B12 2B13 1C5 1C6 1C7 1C8 2A12 2A11 2A10 2A9 2A8 1C10 1C11 1C12 1C13 1D14 1D3 1D4 1D7 1D8 1D11 1D12 2D12 2D11 2D8 2D7 2D4 2D3 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A5 1A4 1A3 1A2 1A1 1A0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D10 1D11 1D12 1D13 M5LV-128 1A7 1A6 1A5 1A4 1A3 1A2 1A1 M5LV-256 1A13 1A12 1A11 1A10 1A8 1A7 1A6 GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 GND I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 VCC GND GND VCC I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 GND I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 0A14 0B13 0B12 0B11 0B10 M5LV-256 M5LV-128 20446G-020 Pin Designations CLK GND I I/O NC 32 = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 160-PIN PQFP CONNECTION DIAGRAM Top View 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0D10 0D11 0D12 0D13 0D8 0D11 0D12 0D13 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 3D12 3D11 3D8 3D7 3D4 3D3 M5-192 M5-192 M5-256 M5LV-256 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND VCC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND VCC I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 VCC GND GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 VCC GND I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 VCC GND M5-256 M5LV-256 M5-128 M5LV-128 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A5 0A4 0A3 0A2 0A1 0A0 0A3 0A2 0D2 0D3 0D4 0D7 0D3 0D4 0D7 0D8 0D11 0D12 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A6 0A11 0A10 0A9 0A8 0A7 0A6 0A5 0A4 M5-128 M5LV-128 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 160-Pin PQFP (128, 192, 256 Macrocells) 0A12 0A13 0A14 0A15 0B15 0B14 0B13 0B12 0A8 0A9 0A10 0A11 0A12 0A13 0A14 0A15 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 0B11 0B8 0B5 0B4 0B3 0B2 0B1 0B0 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B0 1B1 1B2 1B3 1B4 1B5 1B8 1B11 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1B9 1B10 1B11 1B12 1B13 1B14 1A15 1A14 1B12 1B13 1B14 1B15 1A15 1A14 1A13 1A12 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 TDO I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I3/CLK3 GND VCC I2/CLK2 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 GND I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 TMS 3A8 3A9 3A10 3A11 3A12 3A13 3A14 3A15 2A12 2A13 2A14 2A15 2B15 2B14 2B13 2B12 0D14 0D15 0C14 0C13 0C12 0C11 0C10 0C9 3B13 3B12 3B11 3B8 3B5 3B4 3B3 3B2 2B11 2B8 2B5 2B4 2B3 2B2 2B1 2B0 0C8 0C7 0C6 0C5 0C4 0C3 0C2 0C1 2B2 2B3 2B4 2B5 2B8 2B11 2B12 2B13 2C0 2C1 2C2 2C3 2C4 2C5 2C8 2C11 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2C12 2C13 2C14 2C15 2D15 2D14 2D13 2D12 1C9 1C10 1C11 1C12 1C13 1C14 1D15 1D14 1D3 1D4 1D7 1D8 1D11 1D12 2D12 2D11 2D8 2D7 2D4 2D3 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1A3 1A2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10 2D11 1A5 1A4 1A3 1A2 1A1 1A0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 M5-128 M5LV-128 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 M5-192 1A11 1A10 1A9 1A8 1A7 1A6 1A5 1A4 M5-256 M5LV-256 1A13 1A12 1A11 1A10 1A9 1A8 1A7 1A6 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 VCC GND GND VCC I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 VCC GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 0A14 0A15 0B14 0B13 0B12 0B11 0B10 0B9 M5-256 M5LV-256 M5-192 M5-128 M5LV-128 20446G-021 Pin Designations CLK GND I I/O NC = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 33 160-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM Top View 4A12 4A11 4A8 4A7 4A4 4A3 4B3 4B4 4B7 4B8 4B11 4B12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 5A12 5A11 5A8 5A7 5A4 5A3 5B3 5B4 5B7 5B8 5B11 5B12 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2 7B3 7B4 7B7 7B8 7B11 7B12 6B12 6B11 6B8 6B7 6B4 6B3 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 M5-320* M5LV-320 M5-384* M5LV-384 M5-512* M5LV-512 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND VCC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND VCC I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 VCC GND GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 VCC GND I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 VCC GND M5-512* M5LV-512 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 M5-384* M5LV-384 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 M5-320* M5LV-320 7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 160-Pin PQFP (320, 384, 512 Macrocells) 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 TDO I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I3/CLK3 GND VCC I2/CLK2 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 GND I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 TMS 5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13 4A2 4A3 4A4 4A7 4A8 4A11 4A12 4A13 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 5D13 5D12 5D11 5D8 5D7 5D4 5D3 5D2 4D13 4D12 4D11 4D8 4D7 4D4 4D3 4D2 3D13 3D12 3D11 3D8 3D7 3D4 3D3 3D2 4D2 4D3 4D4 4D7 4D8 4D11 4D12 4D13 3D2 3D3 3D4 3D7 3D8 3D11 3D12 3D13 2D2 2D3 2D4 2D7 2D8 2D11 2D12 2D13 4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2 3A13 3A12 3A11 3A8 3A7 3A4 3A3 3A2 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2B3 2B4 2B7 2B8 2B11 2B12 3B12 3B11 3B8 3B7 3B4 3B3 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 2A12 2A11 2A8 2A7 2A4 2A3 2B3 2B4 2B7 2B8 2B11 2B12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 1B3 1B4 1B7 1B8 1B11 1B12 2B12 2B11 2B8 2B7 2B4 2B3 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 M5-320* M5LV-320 2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2 M5-384* M5LV-384 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 M5-512* M5LV-512 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 VCC GND GND VCC I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 VCC GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 M5-512* M5LV-512 M5-384* M5LV-384 M5-320* M5LV-320 *Package obsolete, contact factory. 20446G-022 Pin Designations CLK GND I I/O NC 34 = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 7 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-7) 208-PIN PQFP CONNECTION DIAGRAM Top View 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D13 3D12 3D11 3D10 0D10 0D11 0D12 0D13 M5-256 M5LV-256 0A8 0A9 0A10 0A11 0A12 0A13 0A14 0A15 0B13 0B12 0B11 0B10 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12 1B13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 TDO I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 VCC GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I3/CLK3 GND VCC I2/CLK2 I/O99 I/O98 I/O97 I/O96 GND I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 TMS 3A8 3A9 3A10 3A11 2A12 3A13 3A14 3A15 3B13 3B12 3B11 3B10 3B9 3B8 3B7 3B6 3B5 3B4 3B3 3B2 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 2B13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D13 2D12 2D11 2D10 1D10 1D11 1D12 1D13 M5-256 M5LV-256 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 VCC GND GND VCC I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I0/CLK0 VCC GND I1/CLK1 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 TCK 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O159 I/O158 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 GND VCC I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 GND I/O143 I/O142 I/O141 I/O140 VCC GND GND VCC I/O139 I/O138 I/O137 I/O136 GND I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 I/O129 I/O128 VCC GND I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 M5-256 M5LV-256 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 208-Pin PQFP (192, 256 Macrocells) M5-256 M5LV-256 20446G-023 Pin Designations CLK GND I I/O NC = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 35 208-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM Top View 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 4B8 4B9 4B10 4B11 4B12 4B13 4B14 4B15 5B8 5B9 5B10 5B11 5B12 5B13 5B14 5B15 6B7 6B6 6B5 6B4 6B3 6B2 6B1 6B0 4B2 4B3 4B4 4B7 5B2 5B3 5B4 5B7 6B13 6B12 6B11 6B8 4A7 4A4 4A3 4A2 5A7 5A4 5A3 5A2 7B8 7B11 7B12 7B13 4A15 4A14 4A13 4A12 4A11 4A10 4A9 4A8 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2 0D7 0D4 0D3 0D2 0D7 0D4 0D3 0D2 1D2 1D3 1D4 1D7 1D2 1D3 1D4 1D7 1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I0/CLK0 VCC GND I1/CLK1 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 TDO I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 VCC GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I3/CLK3 GND VCC I2/CLK2 I/O99 I/O98 I/O97 I/O96 GND I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 TMS 5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13 4A2 4A3 4A4 4A7 4A8 4A11 4A12 4A13 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 5D15 5D14 5D13 5D12 5D11 5D10 5D9 5D8 4D15 4D14 4D13 4D12 4D11 4D10 4D9 4D8 3D15 3D14 3D13 3D12 3D11 3D10 3D9 3D8 5D7 5D4 5D3 5D2 4D7 4D4 4D3 4D2 3D7 3D4 3D3 3D2 4D2 4D3 4D4 4D7 3D2 3D3 3D4 3D7 2D2 2D3 2D4 2D7 4D8 4D9 4D10 4D11 4D12 4D13 4D14 4D15 3D8 3D9 3D10 3D11 3D12 3D13 3D14 3D15 2D8 2D9 2D10 2D11 2D12 2D13 2D14 2D15 4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2 3A13 3A12 3A11 3A8 3A7 3A4 3A3 3A2 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B11 2B12 2B13 3B13 3B12 3B11 3B8 3B7 3B6 3B5 3B4 3B3 3B2 3B1 3B0 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2A7 2A4 2A3 2A2 2B2 2B3 2B4 2B7 2B8 2B9 2B10 2B11 2B12 2B13 2B14 2B15 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B11 1B12 1B13 2B13 2B12 2B11 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 2B0 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 M5-320 M5LV-320 2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2 M5-384 M5LV-384 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 M5-512 M5LV-512 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 VCC GND GND VCC I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O159 I/O158 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 GND VCC I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 GND I/O143 I/O142 I/O141 I/O140 VCC GND GND VCC I/O139 I/O138 I/O137 I/O136 GND I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 I/O129 I/O128 VCC GND I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND M5-512 M5LV-512 5A15 5A14 5A13 5A12 5A11 5A10 5A9 5A8 7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 M5-384 M5LV-384 7B0 7B1 7B2 7B3 7B4 7B5 7B6 7B7 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 208-Pin PQFP (320, 384, 512 Macrocells) M5-320 M5LV-320 M5-512 M5LV-512 M5-384 M5LV-384 M5-320 M5LV-320 20446G-024 Pin Designations CLK GND I I/O NC 36 = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 7 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-7) 240-PIN PQFP CONNECTION DIAGRAM Top View 4A15 4A14 4A13 4A12 4A11 4A10 4A9 4A8 4B2 4B3 4B4 4B5 4B6 4B7 4B8 4B9 4B10 4B11 4B12 4B13 4B14 4B15 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 5A15 5A14 5A13 5A12 5A11 5A10 5A9 5A8 5A7 5A6 5A5 5A4 5A3 5A2 5B2 5B3 5B4 5B5 5B6 5B7 5B8 5B9 5B10 5B11 5B12 5B13 5B14 5B15 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2 7B0 7B1 7B2 7B3 7B4 7B5 7B6 7B7 7B8 7B9 7B10 7B11 7B12 7B13 6B13 6B12 6B11 6B10 9B9 6B8 6B7 6B6 6B5 6B4 6B3 6B2 6B1 6B0 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 M5-320* M5LV-320* M5-384* M5LV-384* M5-512* M5LV-512* 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I0/CLK0 VCC GND I1/CLK1 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 TDO I/O139 I/O138 I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 VCC GND I/O131 I/O130 I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 GND I/O123 I/O122 I/O121 I/O120 I/O119 I/O118 I/O117 I/O116 I3/CLK3 GND VCC I2/CLK2 I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 GND I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 GND VCC I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 TMS 5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13 4A2 4A3 4A4 4A7 4A8 4A11 4A12 4A13 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 5D15 5D14 5D13 5D12 5D11 5D10 5D9 5D8 4D15 4D14 4D13 4D12 4D11 4D10 4D9 4D8 3D15 3D14 3D13 3D12 3D11 3D10 3D9 3D8 5D7 5D6 5D5 5D4 5D3 5D2 5D1 5D0 4D7 4D6 4D5 4D4 4D3 4D2 4D1 4D0 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 4D0 4D1 4D2 4D3 4D4 4D5 4D6 4D7 3D0 3D1 3D2 3D3 3D4 3D5 3D6 3D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 4D8 4D9 4D10 4D11 4D12 4D13 4D14 4D15 3D8 3D9 3D10 3D11 3D12 3D13 3D14 3D15 2D8 2D9 2D10 2D11 2D12 2D13 2D14 2D15 4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2 3A13 3A12 3A11 3A8 3A7 3A4 3A3 3A2 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 M5-512* M5LV-512* M5-384* M5LV-384* M5-320* M5LV-320* 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 3B7 3B6 3B5 3B4 3B3 3B2 3B1 3B0 2B8 2B9 2B10 2B11 2B12 2B13 2B14 2B15 2B7 2B6 2B5 2B4 2B3 2B2 2B1 2B0 3B13 3B12 3B11 3B10 3B9 3B8 2B2 2B3 2B4 2B5 2B6 2B7 2B13 2B12 2B11 2B10 2B9 2B8 2B8 2B9 2B10 2B11 2B12 2B13 2A7 2A6 2A5 2A4 2A3 2A2 1B8 1B9 1B10 1B11 1B12 1B13 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 M5-320* M5LV-320* 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 M5-384* M5LV-384* 2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2 M5-512* M5LV-512* 1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 VCC GND GND GND GND VCC I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 GND I/O76 I/O77 I/O78 I/O79 I/O80 I/O81 I/O82 I/O83 VCC GND I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 I/O91 VCC GND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 155 184 183 182 181 GND VCC I/O183 I/O182 I/O181 I/O180 I/O179 I/O178 I/O177 I/O176 GND VCC I/O175 I/O174 I/O173 I/O172 I/O171 I/O170 I/O169 I/O168 GND I/O167 I/O166 I/O165 I/O164 I/O163 I/O162 VCC GND GND GND GND VCC I/O161 I/O160 I/O159 I/O158 I/O157 I/O156 GND I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 VCC GND I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 VCC GND M5-512* M5LV-512* 4A7 4A6 4A5 4A4 4A3 4A2 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 M5-384* M5LV-384* 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 240-Pin PQFP M5-320* M5LV-320* *Package obsolete, contact factory. 20446G-025 Pin Designations CLK GND I I/O NC = = = = = Clock Ground Input Input/Output No Connect VCC TDI TCK TMS TDO = = = = = Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out MACH 5 Family 7 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-7) 37 38 13 12 8 7 6 5 4 3 1 GND I/O18 I/O33 I/O48 I/O5 I/O6 I/O7 GND I/O23 I/O40 I/O54 I/O8 I/O9 I/O10 I/O26 GND I/O27 I/O43 I/O56 I/O62 I/O69 I/O74 I/O82 I/O89 I/O95 I/O101 I/O107 I/O114 I/O120 I/O127 I/O132 I/O146 I/O163 I/O179 GND 19 GND GND I/O21 I/O38 I/O53 GND I/O4 GND 20 H J K L M N P R T U V W Y I/O36 I/O51 I/O35 I/O50 *Package obsolete, contact factory. MACH 5 Family VCC I/O80 I/O87 I/O93 I/O99 I/O105 I/O112 VCC I/O125 VCC 18 I2/CLK2 I3/CLK3 GND L I/O186 K J H N R VCC I/O162 I/O177 I/O190 U TMS I/O161 I/O176 I/O189 T I/O144 I/O160 I/O175 GND VCC I/O159 I/O174 I/O188 P I/O143 I/O158 I/O173 GND I/O142 I/O157 I/O172 I/O187 M I/O141 I/O156 I/O140 I/O155 I/O139 I/O154 I/O171 I/O185 I/O138 I/O153 I/O170 GND VCC I/O152 I/O169 I/O184 G F 17 16 15 14 13 12 11 GND 10 GND 9 8 7 6 5 4 3 2 1 GND I/O115 I/O121 GND I/O133 I/O147 GND I/O180 GND Y W I/O55 I/O61 I/O68 I/O73 I/O81 I/O88 I/O94 I/O100 I/O106 I/O113 I/O119 I/O126 I/O131 I/O145 VCC I/O178 I/O191 V I/O67 GND I/O57 I/O63 GND I/O75 I/O83 GND VCC VCC Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out VCC TCK VCC Pin Designations I/O25 I/O42 I/O24 I/O41 I/O22 I/O39 I/O20 I/O37 I/O52 I1/CLK1 IO/CLK0 = = = = = = = = = = I/O19 I/O34 I/O49 VCC CLK GND I I/O NC VCC TDI TCK TMS TDO I/O17 I/O32 I/O137 I/O151 I/O168 GND TDO I/O150 I/O167 I/O183 E VCC I/O149 I/O166 I/O182 D I/O3 I/O79 I/O86 I/O92 I/O98 I/O104 I/O111 VCC I/O124 VCC G VCC GND I/O16 I/O31 I/O47 TDI I/O66 F I/O15 I/O30 VCC I/O2 VCC E I/O14 I/O29 I/O46 I/O60 I/O65 I/O72 I/O78 I/O85 I/O91 I/O97 I/O103 I/O110 I/O118 I/O123 I/O130 I/O136 VCC I/O165 I/O181 C I/O1 VCC GND 2 D I/O13 GND I/O108 I/O116 GND I/O128 I/O134 GND 9 I/O0 GND 10 C GND 11 B 14 GND I/O12 I/O28 I/O45 I/O59 I/O64 I/O71 I/O77 I/O84 I/O90 I/O96 I/O102 I/O109 I/O117 I/O122 I/O129 I/O135 I/O148 I/O164 GND 15 B 16 A 17 GND 18 GND I/O11 GND I/O44 I/O58 GND I/O70 I/O76 GND 19 A 20 256-BALL BGA CONNECTION DIAGRAM — M5-320, M5LV-320*, M5-384*, M5LV-384*, M5-512*, M5LV-512* Bottom View (I/O Pin-outs) 256-Ball BGA 20446G-026 0D13 0A11 0D10 0A13 GND 0D12 0A12 0D2 GND 1D2 1D3 GND 1D7 1D12 1A15 1A10 1D15 1A12 19 GND GND 1D13 1A14 1A11 GND 0D7 1A13 GND GND 20 D E F G H J K L M *Package obsolete, contact factory. MACH 5 Family N P R T U V W Y 18 GND 1A3 17 1A0 1A2 16 1B1 1B0 1A5 15 GND 1B4 1A1 14 1B7 1B5 1B2 VCC Segment (0-4) 1A6 1A4 PAL Block (A-D) VCC VCC 13 4B2 4B1 4B7 4B5 1B13 2B13 2B8 12 11 GND 10 GND 4B12 4B9 2B9 2B6 2B3 9 8 GND 2B11 1B12 1B15 2B15 2B12 1B10 1B14 2B14 2B10 1B8 1B11 GND 1B9 1B6 1B3 Macrocell (0-15) VCC TCK VCC 4A2 4A7 4A12 15 1A8 1D14 VCC 4A1 4A5 4A9 5 4 VCC 3B7 4B13 3B12 7 2B7 2B5 2B2 VCC 3 6 GND 2B4 2A1 2A4 5 2B1 2B0 2A5 VCC 2D14 2D9 2D5 2D8 2D4 2D3 I2/CLK2 2D7 GND 2D2 GND 3D2 3D3 GND 3D7 4 2A0 2A2 2A6 VCC TMS 3 GND 2A3 VCC 2A8 2 2A7 2A9 1 GND GND 2A12 2D15 2A13 2D13 2A10 2A15 2D10 2A11 2A14 2D12 GND VCC 2D11 2D6 2D0 3D0 3D1 2D1 3D4 3D5 3D6 I3/CLK3 3D8 3D11 3D10 3D9 3D14 3A13 3D12 3D15 VCC TDO 3A8 3A11 GND GND 1 3A12 3D13 GND 3A4 VCC VCC 3A3 3B2 GND 2 3A7 3A2 3B3 VCC 3B8 3B4 4B10 4B11 4B15 3B11 Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out 1A7 1D6 1D1 0D1 0D6 1D10 1D11 1D5 1D0 0D0 0D5 0B7 0B12 4A13 4B6 Pin Designations 1A9 1D9 1D8 1D4 I1/CLK1 IO/CLK0 0D3 VCC 0B4 4B3 6 GND 4B14 3B13 GND D 0D11 VCC 0A7 TDI VCC 0B3 4B0 4B8 4A0 4B4 4A3 GND 4A6 GND GND 7 GND 8 4A4 9 13 10 11 12 4 = = = = = = = = = = 0D9 0D14 0A4 0A2 VCC 4A8 14 CLK GND I I/O NC VCC TDI TCK TMS TDO 0D4 0D8 0A8 15 0B11 4A15 4A11 4A10 0D15 0B8 C 0A3 GND 16 GND 0B13 4A14 GND 17 B 0B2 18 GND 19 A 20 Y W V U T R P N M L K J H G F E D C B A 256-BALL BGA CONNECTION DIAGRAM — M5-320, M5LV-320* Bottom View (Macrocell Association) 256-Ball BGA 20446G-029 39 40 0D13 0A11 0D10 0A13 GND 0D12 0A12 GND 0D2 GND 1D2 1D3 GND 1D7 1D12 1A13 19 0D7 GND 1D13 1A12 GND 0D15 1D15 1A11 GND GND 20 D E F G H J K L M N *Package obsolete, contact factory. MACH 5 Family P R T U V W Y 1B2 18 17 16 15 14 2A8 1B11 2A15 2A11 2A10 1B12 2A13 GND 1B13 2A14 GND 1B8 1B4 VCC Segment (0-5) 1B3 1B7 13 2A4 2A6 2A9 2A12 PAL Block (A-D) VCC VCC Macrocell (0-15) VCC TCK 1A7 VCC 5B2 5A2 5A7 12 GND 2A3 2A5 2A7 15 1A2 1A4 1D14 5B1 5A1 5A5 5B7 5B5 5B3 5B12 5B9 5B6 5B4 8 11 GND 2A0 2A1 2A2 10 GND 2B0 2B1 2B2 9 GND 2B3 2B5 2B7 8 2B4 2B6 2B9 2B12 5 4 3 3B7 3B4 VCC 3B3 VCC 7 2B8 6 5 4 3D8 3D4 3D3 I2/CLK2 3D7 GND 3D2 GND 4D2 4D3 GND 4D7 3B8 VCC 3A2 3A4 3 2 3B2 3A3 3A8 1 GND GND 3D15 3A11 3D13 3A13 3D10 3A12 3D12 GND 3D14 3D9 3D5 GND 2B14 3B13 GND 2B10 2B11 2B15 3B11 2B13 3B12 VCC TMS 3A7 VCC 3D11 3D6 3D0 4D0 4D1 3D1 4D4 4D5 4D6 I3/CLK3 4D8 4D11 4D10 4D9 4D14 VCC 4A13 4D12 4D15 4A11 GND GND 1 4A12 4D13 GND 4A4 TDO 4A8 4A3 4B2 GND 2 4A7 4A2 VCC VCC 4B7 VCC 4B3 4B4 5B13 4B12 VCC 4B8 GND 5B14 4B13 GND 6 5B10 5B11 5B15 4B11 5B8 7 Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out 1A3 1D6 1D1 1D10 1D11 1D5 1D0 0D1 0D6 0D11 VCC 0A7 TDI VCC 5B0 5A0 5A3 GND 9 Pin Designations 1A8 1D9 1D8 1D4 I1/CLK1 0D0 0D5 5A12 VCC VCC 0B7 5A9 0B4 0B12 5A13 0B3 5A6 0B11 5A15 5A11 5A10 GND GND GND 10 11 12 D 0D9 0D14 0A4 0A2 VCC 5A4 13 5A8 14 5 IO/CLK0 15 = = = = = = = = = = 0D3 16 CLK GND I I/O NC VCC TDI TCK TMS TDO 0D4 0D8 0A8 0B8 C 0A3 GND 17 GND 0B13 5A14 GND B 0B2 18 GND 19 A 20 Y W V U T R P N M L K J H G F E D C B A 256-BALL BGA CONNECTION DIAGRAM — M5-384*, M5LV-384* Bottom View (Macrocell Association) 256-Ball BGA 20446G-028 0D13 0A11 0D10 0A13 GND 0D12 0A12 GND 0D2 GND 1D2 1D3 GND 1D7 1D12 1A13 1D15 1A11 GND 2A13 19 0D7 GND 1D13 1A12 GND 0D15 GND 20 D E F G H J K L M N MACH 5 Family P R T U V W Y 18 GND 2A7 17 2A2 2A4 16 2B1 2B0 2A12 2A11 Segment (0-5) 15 GND 2B4 2A3 2A8 14 2B7 2B5 2B2 VCC PAL Block (A-D) VCC VCC Macrocell (0-15) VCC TCK 1A7 VCC 7B3 6B3 7B8 6B8 6B6 7B10 7B14 6B14 6B10 7B13 6B13 6B9 13 2B13 3B13 3B8 12 11 GND 10 GND 3B9 3B6 3B3 9 8 GND 3B11 2B12 2B15 3B15 3B12 2B10 2B14 3B14 3B10 2B8 2B11 GND 2B9 2B6 2B3 15 1A2 1A4 1D14 VCC 7A8 7B6 8 GND 6B11 9 7B12 7B15 6B15 6B12 GND 10 6A11 6A12 VCC 6A3 6A8 6B2 VCC 7 3B7 3B5 3B2 VCC 6 GND 3B4 3A3 3A8 5 3B1 3B0 5D15 5A11 VCC TMS 4A7 VCC 4D11 4D6 4 3A2 3A4 4D8 4D4 4D3 I2/CLK2 I3/CLK3 5D4 5D8 4D7 GND 4D2 GND 5D2 5D3 GND 5D7 4A3 4A8 GND 4D15 4A11 4D13 4A13 4D10 3 2 1 GND 3A13 GND 3A7 VCC 4A2 4A4 4A12 4D12 GND 4D14 4D9 4D5 4D0 5D0 5D1 4D1 5D5 5D6 5D11 5D10 5D9 5D14 VCC 5A13 5D12 5A8 5A3 5A12 5D13 GND 5A4 TDO GND 1 6A13 GND GND 2 5A7 5A2 VCC 6A7 GND 3 VCC 6A4 3A11 3A12 VCC 6B0 6B4 6B5 6A2 6B1 GND 6B7 4 5 6 7 Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out 1A3 1D6 1D1 0D1 1D10 1D11 1D5 1D0 0D0 0D6 7B2 7A3 7B9 GND 11 Pin Designations 1A8 1D9 1D8 1D4 I1/CLK1 IO/CLK0 0D5 7B5 7B4 12 7B11 GND 13 D 0D3 VCC 7B7 14 GND 15 5 0D11 VCC 0A7 TDI VCC 7A12 7A11 7B0 7B1 16 = = = = = = = = = = 0D9 0D14 0A4 0A2 VCC 7A4 7A2 17 CLK GND I I/O NC VCC TDI TCK TMS TDO 0D4 0D8 0A8 7A7 C 0A3 GND B 18 GND 7A13 GND 19 A 20 Y W V U T R P N M L K J H G F E D C B A 256-BALL BGA CONNECTION DIAGRAM — M5-512*, M5LV-512* Bottom View (Macrocell Association) 256-Ball BGA 20446G-027 *Package obsolete, contact factory. 41 42 I/O1 I/O2 GND I/O3 I/O4 G H J K L I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 I/O33 I/O32 TDI NC NC 24 MACH 5 Family NC 25 GND I/O8 I/O9 GND I/O10 NC GND NC NC NC 26 U V W Y A B C D E AF NC NC 24 GND GND NC 23 NC I/O67 NC I/O75 I/O76 I/O69 I/O70 22 GND I/O72 I/O71 VCC 21 NC I/O79 I/O78 I/O77 I/O74 I/O68 20446G-030 TCK I/O66 I/O65 I/O64 VCC I/O63 VCC I/O62 I/O61 I/O73 GND 20 GND I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 20 17 14 13 12 11 10 9 19 8 7 3 2 I/O104 I/O109 I/O117 VCC I/O131 I/O137 I/O145 VCC I/O110 I/O118 I/O124 VCC VCC I/O138 I/O146 I/O152 VCC VCC I/O166 I/O172 I/O179 I/O185 I/O159 I/O165 I/O171 I/O178 E I/O220 I/O240 I/O254 VCC NC I/O223 I/O243 I/O255 I/O201 I/O222 I/O242 I/O200 I/O221 I/O241 GND VCC 18 17 16 15 14 13 12 11 10 9 8 NC 7 6 5 4 I/O175 I/O182 GND I/O204 I/O99 I/O106 I/O112 I/O120 I/O126 I/O133 I/O140 I/O148 I/O154 I/O161 I/O168 I/O174 I/O181 I/O187 I/O203 3 NC NC 2 GND GND 1 NC NC AF AE AD AC AB AA Y W I/O199 I/O219 I/O239 I/O253 U I/O198 I/O217 I/O237 I/O252 V T I/O197 I/O216 I/O236 I/O251 I/O218 I/O238 GND R I/O196 I/O215 I/O235 I/O250 VCC P I2CLK2 I/O234 N GND VCC I/O195 I/O214 I/O233 I3/CLK3 M L I/O193 I/O212 I/O231 I/O248 I/O194 I/O213 I/O232 I/O249 K I/O211 I/O230 GND J I/O192 I/O210 I/O229 I/O247 VCC H I/O209 I/O228 I/O246 G I/O191 I/O208 I/O227 GND VCC F I/O190 I/O207 I/O226 I/O245 NC I/O189 I/O206 I/O225 C D NC B A TDO I/O205 I/O224 GND NC NC NC 1 I/O98 I/O105 I/O111 I/O119 I/O125 I/O132 I/O139 I/O147 I/O153 I/O160 I/O167 I/O173 I/O180 I/O186 I/O202 TMS I/O244 GND I/O97 VCC NC NC NC 4 I/O96 I/O103 I/O108 I/O116 I/O123 I/O130 I/O136 I/O144 I/O151 I/O158 I/O164 I/O170 I/O177 I/O184 GND 5 NC NC 6 I/O95 I/O102 I/O107 I/O115 I/O122 I/O129 I/O135 I/O143 I/O150 I/O157 I/O163 I/O169 I/O176 I/O183 I/O188 GND I/O114 GND I/O128 I/O134 I/O142 GND I/O156 I/O162 GND 15 NC NC 16 GND GND I/O101 18 I/O94 I/O100 GND I/O113 I/O121 I/O127 GND I/O141 I/O149 I/O155 GND I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 I/O87 19 Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O60 21 22 Pin Designations I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O7 T I/O23 I/O6 R I/O41 VCC I/O59 I/O58 I/O57 VCC I/O56 VCC I/O55 I/O54 VCC I/O53 I/O52 I/O51 23 = = = = = = = = = = I/O21 I0/CLK0 I1/CLK1 I/O22 GND F I/O13 P NC E I/O12 GND I/O0 D I/O11 N GND C GND I/O5 NC B GND 25 CLK GND I I/O NC VCC TDI TCK TMS TDO M NC A 26 352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 352-Ball BGA MACH 5 Family 1D11 1D15 GND 1A12 NC GND NC NC NC V W Y AA AB AC D AE AF 25 NC NC 24 GND GND NC 23 NC 2A14 NC 20446G-031 NC 22 GND 2A12 2A13 21 NC 2A9 2A10 20 GND 2A6 2A8 2A11 7A8 19 2A1 2A4 2A5 2A7 7A4 7A1 VCC 7B2 7B3 18 2B1 2A0 2A2 2A3 PAL Block (A-D) VCC 2A15 7A12 7A15 7A3 7B0 GND 7B4 7B5 7B6 7B7 17 17 GND 2B2 2B0 VCC Macrocell (0-15) TCK 1A0 1A3 1A6 VCC 1A11 VCC 1D12 1D7 1D2 VCC 0D3 0D8 0D12 VCC 0A11 VCC 0A4 0A0 7A7 7A11 7A2 7B1 18 GND 7B15 6B15 VCC 7B14 7B13 7B12 7B11 NC 7B10 7B8 7B9 14 15 16 16 2B6 2B5 2B4 2B3 15 1A1 1A4 1A7 1A8 1A10 1A13 1D14 1D9 1D5 1D1 I0/CLK0 0D4 0D7 0D11 0D14 0A14 0A10 0A7 0A5 VCC 7A6 7A9 7A0 19 6B11 6B12 6B13 6B14 13 6B7 6B8 6B9 6B10 12 6B3 6B4 6B5 6B6 11 VCC 6B0 6B2 GND 10 GND 6A6 6A8 6A11 6A1 6A4 6A5 6A7 6B1 6A0 6A2 6A3 15 2B10 2B9 2B8 2B7 14 2B14 2B13 2B12 2B11 13 GND 3B15 2B15 VCC 12 3B14 3B13 3B12 3B11 11 3B10 3B9 3B8 3B7 10 3B6 3B5 3B4 3B3 9 GND 3B2 3B1 VCC 8 NC 3B0 3A1 3A2 7 3A0 3A3 3A4 3A6 7 8 9 Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out 1A2 1A5 1A9 1A14 1A15 1D13 1D10 1D8 1D4 1D0 0D0 0D2 0D6 0D10 0D13 0A15 0A12 0A9 0A8 0A2 7A14 7A5 GND 20 Pin Designations 26 GND U 0D5 L 1D6 0D9 K T GND J 1D3 0D15 H R 0A13 G I1/CLK1 GND F P NC E 0A3 TDI 7A13 21 22 D GND 0A6 D 0A1 NC 7A10 23 7 N GND C GND NC 24 = = = = = = = = = = 0D1 NC B GND 25 CLK GND I I/O NC VCC TDI TCK TMS TDO M NC A 26 6 3A5 3A7 3A8 3A10 6A15 6A10 6A9 NC 6 5 GND 3A9 3A11 3A14 VCC 6A13 6A12 GND 5 4D7 4D11 4D14 4A14 4A10 4D8 4D12 VCC 4A11 VCC 4 3A12 3A13 3A15 VCC 4A0 3 NC NC TMS 4A2 4A5 4A7 4D4 4D3 4A4 I2/CLK2 5D1 5D2 VCC 5D5 5D9 5D7 5D12 2 GND GND 4A1 4A3 4A8 4A9 4A12 4A15 4D13 4D10 4D6 4D2 4D0 5D0 5D4 5D8 5D10 5A15 5D14 5A10 VCC 5A14 VCC 5A8 5A6 5A9 5D13 5A7 5A3 5A5 5A13 5A4 5A0 5A2 NC NC NC 2 5A11 5A1 NC GND GND 3 TDO NC 6A14 NC 4 1 NC NC GND 4A6 NC GND 4A13 4D15 GND 4D9 4D5 4D1 GND I3/CLK3 5D3 5D6 GND 5D11 5D15 GND 5A12 NC GND NC NC NC 1 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 352-Ball BGA Segment (0-7) 43 5V M5 ORDERING INFORMATION1,2 Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. . M5- 512 /256 -7 A PROGRAMMING DESIGNATOR Blank = Initial Algorithm /1 = First Revision FAMILY TYPE M5= MACH 5 (5-V VCC) OPERATING CONDITIONS C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) MACROCELL DENSITY 128 = 128 Macrocells 192 = 192 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 /74 /104 /120 /160 /192 /256 = = = = = = = C PACKAGE TYPE Y = Plastic Quad Flat Pack (PQFP) V = Thin Quad Flat Pack (TQFP) A = Ball Grid Array (BGA) H = Plastic Quad Flat Pack (PQFP) with exposed heat sink 68 I/Os in 100-pin PQFP or TQFP 74 I/Os in 100-pin TQFP 104 I/Os in 144-pin PQFP or TQFP 120 I/Os in 160-pin PQFP 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA 256 I/Os in 352-ball BGA SPEED -5 = 5.5 ns tPD -6 = 6.5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD Note: 1. See below for valid device/package combinations. 2. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs. . Valid Combinations Valid Combinations M5-128/68 YC, VC, YI, VI M5-320/120 HC*, HI* M5-128/104 YC, YI M5-320/160 HC, YC**, HI, YI** M5-128/120 YC, YI M5-320/184 HC*, HI* M5-192/68 Commercial: YC*, VC, YI*, VI M5-320/192 AC, AI M5-192/104 -5, -7, -10, -12, -15 YC*, YI* M5-384/120 Commercial: HC*, HI* M5-192/120 Industrial: YC, YI M5-384/160 -6, -7, -10, -12, -15 HC, YC**, HI, YI** M5-256/68 -7, -10, -12, -15, -20 YC*, VC, YI*, VI M5-384/184 M5-256/104 YC*, YI* M5-384/192 Industrial: AC*, AI* M5-256/120 YC, YI M5-512/120 -7, -10, -12, -15, -20 HC*, HI* M5-256/160 YC, YI M5-512/160 HC, YC**, HI, YI** M5-512/184 HC*, HI* M5-512/192 AC*, AI* M5-512/256 AC, AI *Package obsolete, contact factory. ** Contact Factory for availability. Device Marking Actual device marking differs from the ordering part number (OPN). All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5-512/256-7AC-10AI. 44 HC*, HI* Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales of fice to confir m availability of specific valid combinations and to check on newly released combinations. MACH 5 Family 3.3V M5LV ORDERING INFORMATION1 Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. M5LV- 512 /256 -7 A FAMILY TYPE M5LV- = MACH 5 Low Voltage (3.3-V VCC) OPERATING CONDITIONS C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) PACKAGE TYPE Y = Plastic Quad Flat Pack (PQFP) V = Thin Quad Flat Pack (TQFP) A = Ball Grid Array (BGA) H = Plastic Quad Flat Pack (PQFP) with exposed heat sink MACROCELL DENSITY 128 = 128 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 /74 /104 /120 /160 /192 /256 = = = = = = = C SPEED -5 = 5.5 ns tPD -6 = 6.5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD 68 I/Os in 100-pin PQFP or TQFP 74 I/Os in 100-pin TQFP 104 I/Os in 144-pin PQFP or TQFP 120 I/Os in 160-pin PQFP 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA 256 I/Os in 352-ball BGA Note: 1. See below for valid device/package combinations. Valid Combinations Valid Combinations M5LV-128/68 YC*, VC, YI*, VI M5LV-320/120 HC, YC**, HI, YI** M5LV-128/74 VC, VI M5LV-320/160 HC, YC**, HI, YI** HC*, HI* M5LV-128/104 Commercial: YC*, VC, YI*, VI M5LV-320/184 M5LV-128/120 -5, -7, -10, -12 YC, YI M5LV-320/192 AC*, AI* YC, VC*, YI, VI* M5LV-384/120 Commercial: M5LV-256/74 Industrial: VC, VI M5LV-384/160 -6, -7, -10, -12, -15 M5LV-256/104 -7, -10, -12, -15 YC*, VC, YI*, VI M5LV-384/184 M5LV-256/120 YC, YI M5LV-384/192 M5LV-256/160 YC, YI M5LV-512/120 M5LV-256/68 *Package obsolete, contact factory. ** Contact Factory for availability. Device Marking Actual device marking differs from the ordering part number (OPN). All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5LV-512/256-7AC-10AI. Industrial: -10, -12, -15, -20 HC, YC**, HI, YI** HC, YC**, HI, YI** HC*, HI* AC*, AI* HC, YC**, HI, YI** M5LV-512/160 HC, YC**, HI, YI** M5LV-512/184 HC*, HI* M5LV-512/192 AC*, AI* M5LV-512/256 AC, AI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales of fice to confir m availability of specific valid combinations and to check on newly released combinations. MACH 5 Family 45 46 MACH 5 Family, 3.3-V Ind MACH 5 Family, 3.3-V Ind 47