RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION The M5M5V208AKV is low voltage 2-Mbit static RAMs organized as 262,144-words by 8-bit, fabricated by high-performance 0.25µm CMOS technology. The M5M5V208AKV is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. The M5M5V208AKV is packaged in 32-pin 8mm x 13.4mm sTSOP packages which is a high reliability and high density surface mount device. FEATURES Type name M5M5V208AKV-55HI Access time (max) 55ns Power supply current Active (max) 35mA (10MHz) M5M5V208AKV-70HI 70ns 7mA (1MHz) stand-by (max) 30µA PIN CONFIGURATION (TOP VIEW) A11 A9 A8 A13 W 1 32 2 31 3 30 4 29 DQ8 5 28 DQ7 S2 A15 VCC A17 A16 A14 A12 A7 A6 6 27 7 26 DQ6 DQ5 DQ4 GND A5 A4 8 M5M5V208AKV 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 OE A10 S1 DQ3 DQ2 DQ1 A0 A1 A2 A3 (Vcc= 3.6V) 0.3µA (Vcc= 3.0V TYPICAL) Outline 32P3K-B(KV) • Single 2.7 ~3.6V power supply • No clock, No refresh • Directly TTL compatible : All inputs and outputs • Easy memory expansion and power down by S1,S2 • Data hold on +2V power supply • Three-state outputs : OR - tie capability • OE prevents data contention in the I/O bus • Common data I/O • Package 2 M5M5V208AKV ············· 32pin 8 X 13.4 mm Rev ision-A0.5 sTSOP 1 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M5V208AKV series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a highimpedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing ORtie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. FUNCTION TABLE S1 X H L S2 L X H L L H H W X X L H H OE Mode DQ X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H ICC Stand-by Stand-by Active Active Active Note 1: "H" and "L" in this table mean VIH and VIL, respectively. 2: "X" in this table should be "H" or "L". BLOCK DIAGRAM 21 DQ1 A2 18 22 DQ2 A3 17 A4 16 A5 15 A6 14 A7 13 262144 WORDS X 8 BITS ( 1024 ROWS X256 COLUMNS X 8 BLOCKS ) 23 DQ3 25 DQ4 26 DQ5 DATA INPUTS/ OUTPUTS 27 DQ6 A12 12 28 DQ7 A14 11 29 DQ8 A16 10 A17 9 ADDRESS INPUTS A15 7 A13 4 CLOCK GENERATOR A8 3 A9 2 A11 1 5 WRITE W CONTROL INPUT A1 19 30 S1 A0 20 6 A10 31 Rev ision-A0.5 S2 CHIP SELECT INPUTS OUTPUT 32 OE ENABLE INPUT 8 VCC 24 GND (0V) 2 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Vcc VI Supply voltage Input voltage VO Pd Topr Tstg Output voltage Power dissipation Operating temperature Storage temperature Ratings Conditions With respect to GND Unit - 0.5*~4.6 - 0.5*~Vcc + 0.3 0~Vcc V V 700 - 40~85 - 65~150 mW °C °C Ta=25°C V * -3.0V in case of AC ( Pulse width ≤ 30ns ) DC ELECTRICAL CHARACTERISTICS (Ta= -40~85°C, Vcc=2.7~3.6V, unless otherwise noted) Symbol Parameter Limits Test conditions VIH High-level input voltage VIL VOH1 Low-level input voltage High-level output voltage 1 Min Typ 2.0 -0.3* 2.4 IOH= - 0.5mA Max Vcc + 0.3 0.6 V V V Vcc - 0.5 VOH2 High-level output voltage 2 VOL Low-level output voltage IOL= 2mA 0.4 II Input current VI =0~Vcc ±1 V µA IO Output current in off-state S1=VIH or S2=VIL or OE=VIH VI/O =0~VCC ±1 µA Active supply current (CMOS-level input) S1 ≤ 0.2V,S2 ≥ Vcc-0.2V other inputs ≤ 0.2V or ≥ Vcc-0.2V, Output-open 10MHz ICC1 28 30 1MHz 5 7 Active supply current (TTL-level input) S1=VIL,S2=VIH, other inputs=VIH or VIL, Output-open 10MHz 33 35 1MHz 5 7 ~25°C 0.3 2 Stand-by current 1) S2 ≤ 0.2V, other inputs=0 ~ VCC 2) S1 ≥ VCC - 0.2V, S2 ≥ VCC - 0.2V other inputs=0 ~ VCC ICC2 ICC3 ICC4 IOH= - 0.05mA Unit V ~40°C 5 ~70°C 10 ~85°C 30 1) S1=VIH, other inputs=VIL or VIH 2) S2=VIL, other inputs=VIL or VIH Stand-by current 0.33 mA mA µA mA * -3.0V in case of AC ( Pulse width ≤ 30ns ) CAPACITANCE (Ta=- 40~85°C, unless otherwise noted) Parameter Symbol CI CO Input capacitance Output capacitance Test conditions VI =GND, VI =25mVrms, f=1MHz VO =GND,VO =25mVrms, f=1MHz Min Limits Typ Max 8 10 Unit pF pF Note 3: Direction for current flowing into an IC is positive (no mark). 4: T ypical value is Vcc = 3V, Ta = 25 °C Rev ision-A0.5 3 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Ta=- 40~85°C, unless otherwise noted ) (1) MEASUREMENT CONDITIONS VCC ................................. Input pulse level ............. Input rise and fall time..... Reference level............... Output loads................... 2.7~3.6V VIH=2.2V,VIL=0.4V 5ns VOH=VOL=1.5V Fig.1, C L=30pF C L=5pF (for ten,tdis) Transition is measured ± 500mV from steady state voltage. (for ten,tdis) 1TTL DQ CL including scope and JIG Fig.1 Output load (2) READ CYCLE Limits Symbol tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time -55HI Max Min 55 Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address -70HI Max Min 70 55 70 55 55 30 20 20 20 70 70 35 25 25 25 10 10 10 5 10 5 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low Rev ision-A0.5 Limits -70HI -55HI Min Max Min Max 55 70 45 0 50 50 50 25 0 0 55 0 65 65 65 30 0 0 20 20 5 5 25 25 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 4 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle tCR A0~ 17 ta(A) tv (A) ta (S1) S1 (Note 5) tdis (S1) S2 (Note 5) ta (S2) (Note 5) tdis (S2) ta (OE) (Note 5) ten (OE) OE (Note 5) tdis (OE) (Note 5) ten (S1) ten (S2) DQ1~ 8 DATA VALID W = "H" level Write cycle (W control mode) tCW A0~ 17 tsu (S1) S1 (Note 5) (Note 5) S2 tsu (S2) (Note 5) (Note 5) tsu (A-WH) OE tsu (A) tw (W) trec (W) W tdis (W) ten(OE) ten (W) tdis (OE) DQ1~ 8 DATA IN STABLE tsu (D) Rev ision-A0.5 th (D) 5 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM Write cycle ( S1 control mode) tCW A0~ 17 tsu (A) tsu (S1) trec (W) S1 S2 (Note 5) (Note 5) (Note 7) W (Note 6) (Note 5) (Note 5) tsu (D) th (D) DATA IN STABLE DQ1~ 8 Write cycle (S 2 control mode) tCW A0~ 17 S1 (Note 5) (Note 5) tsu (A) tsu (S2) trec (W) S2 (Note 7) W (Note 6) (Note 5) (Note 5) tsu (D) DQ1~ 8 th (D) DATA IN STABLE Note 5: Hatching indicates the state is "don't care". 6: Writing is executed while S 2 high overlaps S 1 and W low. 7: When the falling edge of W is simultaneously or prior to the falling edge of S 1 or rising edge of S 2 , the outputs are maintained in the high impedance state. 8: Don't apply inverted phase signal externally when DQ pin is output mode. Rev ision-A0.5 6 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta= -40~85°C, unless otherwise noted) Symbol Parameter VCC (PD) VI (S1) Power down supply voltage Chip select input S1 VI (S2) Chip select input S2 ICC (PD) Test conditions Min 2.0 2.0 Limits Typ Max V V 0.2 VCC = 3.0V 1) S2 ≤ 0.2V, other inputs = 0~Vcc 2) S1 ≥ VCC-0.2V, S2 ≥ VCC-0.2V, other inputs = 0~Vcc Power down supply current ~25°C Unit 0.3 V 1 ~40°C 3 ~70°C 8 ~85°C 24 µA (2) TIMING REQUIREMENTS (Ta=-40~85°C, unless otherwise noted ) Symbol tsu (PD) trec (PD) Parameter Test conditions Power down set up time Power down recovery time Min 0 5 Limits Typ Max Unit ns ms (3) POWER DOWN CHARACTERISTICS S1 control mode VCC t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V S1 S1 ≥ VCC - 0.2V Note 9: On the power down mode by controlling S 1 ,the input level of S 2 must be S 2 ≥ Vcc - 0.2V or S 2 ≤ 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state. S2 control mode VCC S2 t su (PD) 2.7V 2.7V t rec (PD) 0.2V 0.2V S2 ≤ 0.2V Rev ision-A0.5 7 RENESAS LSIs M5M5V208AKV 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! · Renesas T echnology Corporation puts the m axim um effort int o m a k ing sem iconductor products better and more reliable, but there is always the possibility that trouble m ay occur with them . T r o u b le with sem iconductors m ay lead to personal injury, fire or property dam age.Rem ember to give due consideration to safety when m aking your circuit designs, with appropriate m easures such as (i) placem ent of substit u t ive, auxiliary circuits, (ii) use of nonflam m able m aterial or (iii) prevention against any m alfunction or mishap. Notes regarding these materials · T hese m aterials are intended as a reference to assist our custom ers in the selection of the Renesas T echnology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas T echnology Corporation or a third party. · Renesas T echnology Corporation assum es no responsibility for any dam age, or infringem ent of any third-party's rights, originat ing in the use of any product data, diagrams, charts, program s , a lgorit h m s , or circuit application exam ples contained in these m aterials . · A ll inf o r m a t ion contained in these m aterials , including product data, diagrams, charts, programs and algorithms represents inform ation on products at the tim e of publication of these m aterials, and are subject to change by Renesas T echnology Corporation without notice due to product im provem ents or other reasons. It is therefore recomm ended that custom ers contact Renesas T echnology Corporation or an authorized Renesas T echnology Corporation product distributor for the latest product inform ation before purchasing a product listed herein. T he inform ation described here m ay contain technical inaccuracies or typographical errors. Renesas T echnology Corporation assum es no responsibility for any dam age, liability, or other loss rising from t hese inaccuracies or errors. P lease also pay attention to inform ation published by Renesas T echnology Corporation by various m eans, including the Renesas T echnology Corporation S e m iconductor home page (http://www.renesas.com ). · When using any or all of the information contained in these m aterials , including product data, diagrams, charts, programs, and algorithm s , p lease be sure to evaluate all inform ation as a total system before m aking a final decision on the applicability of the inform ation and products. Renesas T echnology Corporation assum es no responsibility for any dam age, liability or other loss resulting from the inform ation contained herein. · Renesas T echnology Corporation sem iconductors are not designed or m anufactured for use in a device or system t hat is used under circumstances in which hum an life is potentially at stake. Please contact Renesas T echnology Corporation or an authorized Renesas T echnology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, m edical, aerospace, nuclear, or undersea repeater use. · T he prior written approval of Renesas T echnology Corporation is necessary to reprint or reproduce in whole or in part these m aterials . · If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from t he Japanese governm ent and cannot be im ported into a country other than the approved destinat ion. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destinat ion is prohibited. · P lease contact Renesas T echnology Corporation for further details on these m aterials or the products contained therein. REJ03C0104 © 2003 Renesas Technology Corp. New publication, effective Aug 2003. Specifications subject to change without notice Rev ision-A0.5 8