STMicroelectronics M69KB128AA70DW8 128 mbit (8mb x16) 1.8v supply, burst psram Datasheet

M69KB128AA
128 Mbit (8Mb x16) 1.8V Supply, Burst PSRAM
PRELIMINARY DATA
Features summary
■
SUPPLY VOLTAGE
– VCC = 1.7 to 1.95V core supply voltage
– VCCQ = 1.7 to 1.95V for I/O buffers
■
USER-SELECTABLE OPERATING MODES
– Asynchronous Modes: Random Read, and
Write, Page Read
– Synchronous Modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
■
ASYNCHRONOUS RANDOM READ
– Access Times: 70ns, 85ns
■
ASYNCHRONOUS PAGE READ
– Page Size: 4, 8 or 16 Words
– Subsequent Read Within Page: 20ns
■
BURST READ
– Fixed Length (4, 8, 16 or 32 Words) or
Continuous
– Maximum Clock Frequency: 66, 80,
104MHz
– Output delay: 7ns at 104MHz
■
LOW POWER CONSUMPTION
– Active Current: < 25mA
– Standby Current: 200µA
– Deep Power-Down Current: 10µA
■
LOW POWER FEATURES
– Partial Array Self Refresh (PASR)
– Deep Power-Down (DPD) Mode
■
OPERATING TEMPERATURE
– –30°C to +85°C
Wafer
M69KB128AA IS ONLY AVAILABLE AS PART OF A MULTIPLE MEMORY PRODUCT
January 2006
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev2
1/68
www.st.com
1
M69KB128AA
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Data Inputs/Outputs (DQ8-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Upper Byte Enable (UB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Lower Byte Enable (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9
Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10
Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.14
VCCQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.15
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.16
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
2/68
4.1
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standard asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
Asynchronous Read and Write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Asynchronous Page Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Configuration Registers Asynchronous Read and Write . . . . . . . . . . . . . . . . 16
M69KB128AA
6
7
Synchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
NOR-Flash Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Synchronous Burst Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3.2
Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3.3
Row Boundary crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
Synchronous Burst Read Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
Synchronous Burst Write Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6
Synchronous Burst Read and Write Suspend . . . . . . . . . . . . . . . . . . . . . . . 21
Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
Programming the Registers by the CR controlled method . . . . . . . . . . . . . . 27
7.1.1
Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.2
Program Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2
Programming and Reading the Registers by the software method . . . . . . . . 28
7.3
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4
7.5
7.3.1
Operating Mode Bit (BCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.2
Latency Type (BCR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.3
Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.4
WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.5
WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.6
Driver Strength Bits (BCR5-BCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3.7
Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3.8
Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4.1
Page Mode Operation Bit (RCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4.2
Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4.3
Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3/68
M69KB128AA
11
4/68
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M69KB128AA
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standard Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Frequency versus Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Asynchronous Write Operations (NOR-Flash Synchronous mode) . . . . . . . . . . . . . . . . . . 22
Synchronous Read Operations (NOR-Flash Synchronous mode) . . . . . . . . . . . . . . . . . . . 23
Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Device ID Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clock Related AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synchronous Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power-Up and Deep Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5/68
M69KB128AA
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
6/68
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Latency Configuration (Variable Latency mode, no Refresh collision) . . . . . . . . . . . . . . . . 25
Latency Configuration (Fixed Latency mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Switching from Asynchronous to Synchronous Write operation . . . . . . . . . . . . . . . . . . . . . 26
Refresh Collision during Synchronous Read Operation in Variable Latency mode . . . . . . 26
Set Configuration Register (Software Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Configuration Register (Software Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WAIT Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WAIT Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC Input Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Asynchronous Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Latch Enable Controlled, Asynchronous Random Read AC Waveforms . . . . . . . . . . . . . 44
Asynchronous Page Read AC Waveforms (4 Words) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CR Controlled Configuration Register Read Followed by Read, Asynchronous Mode . . . 45
Chip Enable Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . 47
Upper/Lower Byte Enable Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . 48
Write Enable Controlled, Asynchronous Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . 49
L Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CR Controlled Configuration Register Program, Asynchronous Mode . . . . . . . . . . . . . . . . 51
Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4-Word Synchronous Burst Read AC Waveforms (Variable Latency Mode) . . . . . . . . . . . 54
Synchronous Burst Read Suspend and Resume AC Waveforms . . . . . . . . . . . . . . . . . . . 55
Synchronous Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap) . . . 56
Burst Read Interrupted by Burst Read or Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . 57
CR Controlled Configuration Register Read Followed by Read, Synchronous Mode . . . . 58
4-Word Synchronous Burst Write AC Waveforms (Variable Latency Mode) . . . . . . . . . . . 60
Synchronous Burst Write Showing End-of-Row Condition AC Waveforms (No Wrap) . . . 61
Synchronous Burst Write Followed by Read AC Waveforms (4 Words) . . . . . . . . . . . . . . 62
Burst Write Interrupted by Burst Write or Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 63
CR Controlled Configuration Register Program, Synchronous Mode. . . . . . . . . . . . . . . . . 64
Power-Up AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Deep Power-Down Entry and Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
M69KB128AA
1
1 Summary description
Summary description
The M69KB128AA is a 128 Mbit (134,217,728 bit) PSRAM, organized as 8,388,608 Words by
16 bits. It uses a high-speed CMOS DRAM technology implemented using a one transistor-percell topology that achieves bigger array sizes. It provides a high-density solution for low-power
handheld applications.
The M69KB128AA is supplied by a 1.7 to 1.95V supply voltage range.
The PSRAM interface supports various operating modes: Asynchronous Random Read and
Write, Asynchronous Page Read and Synchronous mode that increases read/write speed.
In Asynchronous Random Read mode, the M69KB128AA is compatible with low power
SRAMs. In Asynchronous Page mode the device has much shorter access times within the
page that make it is compatible with the industry standard PSRAMs.
Two types of Synchronous modes are available:
●
Flash-NOR: the device operates in Synchronous mode for read operations and
Asynchronous mode for write operations.
●
Full Synchronous: the device supports Synchronous transfers for both read and write
operations.
The M69KB128AA features three configuration registers:
●
Two user-programmable registers used to define the device operation: the Bus
Configuration Register (BCR) and the Refresh Configuration Register (RCR).
●
A read-only Device ID Register (DIDR) containing device identification.
The Bus Configuration Register (BCR) indicates how the device interacts with the system
memory bus. The Refresh Configuration Register (RCR) is used to control how the memory
array refresh is performed. At Power-Up, these registers are automatically loaded with default
settings and can be updated any time during normal operation.
PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh
mechanism that requires no additional support from the system memory microcontroller.
To minimize the value of the Standby current during self-refresh operations, the M69KB128AA
includes two system-accessible mechanisms configured via the Refresh Configuration Register
(RCR):
●
The Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM
array that contains essential data.
●
The Deep Power-Down (DPD) mode completely halts the refresh operation. It is used
when no essential data is being held in the device.
7/68
M69KB128AA
1 Summary description
Figure 1.
Logic Diagram
VCC
VCCQ
23
16
A0-A22
DQ0-DQ15
W
WAIT
E
CR
G
M69KB128AA
UB
LB
K
L
VSS
Table 1.
8/68
VSSQ
Signal Names
A0-A22
Address Inputs
DQ0-DQ15
Data Inputs/Outputs
E
Chip Enable Input
CR
Configuration Register Enable Input
G
Output Enable Input
W
Write Enable Input
UB
Upper Byte Enable Input
LB
Lower Byte Enable Input
K
Clock Input
L
Latch Enable Input
WAIT
Wait Output
VCC
Core Supply Voltage
VCCQ
Input/Output Buffers Supply Voltage
VSS
Ground
VSSQ
Input/Output Buffers Ground
AI11294
M69KB128AA
Figure 2.
A22-A0
1 Summary description
Block Diagram
Address Decoder
Column Decoder
E
W
Bus Configuration
Register (BCR)
CR
DQ0-DQ15
K
Synchronous/
Asynchronous
Logic
Row
Decoder
8,192K x 16
Memory Array
I/O
Buffers
WAIT
E
W
G
L
Control
Logic
CR
LB
UB
AI09965b
1. This functional block diagram illustrates simplified device operation.
9/68
2 Signal descriptions
2
M69KB128AA
Signal descriptions
The signals are summarized in Figure 1: Logic Diagram, and Table 1: Signal Names.
2.1
Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during read and write
operations.
2.2
Data Inputs/Outputs (DQ8-DQ15)
The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected
address during a write or read operation, when Upper Byte Enable (UB) is driven Low. When
disabled, the Data Inputs/Outputs are high impedance.
2.3
Data Inputs/Outputs (DQ0-DQ7)
The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected
address during a write or read operation, when Lower Byte Enable (LB) is driven Low. When
disabled, the Data Inputs/Outputs are high impedance.
2.4
Chip Enable (E)
Chip Enable, E, activates the device when driven Low (asserted). When deasserted (VIH), the
device is disabled and goes automatically in low-power Standby mode or Deep Power-Down
mode, according to the RCR settings.
2.5
Output Enable (G)
When held Low, VIL, the Output Enable, G, enables the Bus Read operations of the memory.
2.6
Write Enable (W)
Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
2.7
Upper Byte Enable (UB)
The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a write or read operation.
10/68
M69KB128AA
2.8
2 Signal descriptions
Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7)
to or from the lower part of the selected address during a write or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active mode
as long as E remains Low.
2.9
Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus
frequency during Synchronous Burst Read and Write operations. The Clock input signal
increments the device internal address counter.
The addresses are latched on the rising edge of the Clock K, when L is Low during
Synchronous Bus operations.
Latency counts are defined from the first Clock rising edge after L falling edge to the first data
input latched or the first data output valid.
The Clock input is required during all synchronous operations and must be kept Low during
asynchronous operations.
2.10
Configuration Register Enable (CR)
When this signal is driven High, VIH, bus read or write operations access either the value of the
Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to
the value of A19.
2.11
Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the Latch
Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising edge.
2.12
Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and
Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause
data corruption.
Once a read or write operation has been initiated, the WAIT signal goes active to indicate that
the M69KB128AA device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when a Read or Write operation is launched while
an on-chip refresh is in progress (see Figure 6: Refresh Collision during Synchronous Read
Operation in Variable Latency mode).
Typically, the WAIT pin of the M69KB128AA can be connected to a shared WAIT signal used by
the processor to coordinate transactions with multiple memories on the synchronous bus.
See Section 3: Power-up for details on the WAIT signal operation.
11/68
2 Signal descriptions
2.13
M69KB128AA
VCC Supply Voltage
The VCC Supply Voltage is the core supply voltage.
2.14
VCCQ Supply Voltage
VCCQ provides the power supply for the I/O pins. This allows all Outputs to be powered
independently from the core power supply, VCC.
2.15
VSS Ground
The VSS Ground is the reference for all voltage measurements.
2.16
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VCCQ. VSSQ must be
connected to VSS.
12/68
M69KB128AA
3
3 Power-up
Power-up
To guarantee correct operation, a specific Power-Up sequence must be followed to initialize the
M69KB128AA. Power must be applied simultaneously to VCC and VCCQ. Once VCC and VCCQ
have reached a stable level (see Figure 35: Deep Power-Down Entry and Exit AC Waveforms
and Figure 34: Power-Up AC Waveforms), the device will require tVCHEL to complete its selfinitialization process. During the initialization period, the E signal must remain High. Once
initialization has completed, the device is ready for normal operation.
Initialization will load the Bus Configuration Register (BCR) and the Refresh Configuration
Register (RCR) with their default settings (see Table 9: Bus Configuration Register Definition,
and Table 11: Refresh Configuration Register Definition).
4
Low-power modes
4.1
Standby
When the device is in Standby, the current consumption is reduced to the level necessary to
perform the memory array refresh operation. The device will enter Standby when a read or
write operation is completed, depending on the operating mode (Asynchronous, NOR-Flash
Synchronous or Full Synchronous).
For details on how to enter Standby, refer to Table 3: Standard Asynchronous Operating
Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous mode) and Table 6:
Synchronous Read Operations (NOR-Flash Synchronous mode).
4.2
Deep Power-Down
Deep Power-Down (DPD) is used by the system memory microcontroller to disable the PSRAM
device when its storage capabilities are not needed. All refresh operations are then disabled.
For the device to enter Deep Power-Down, bit 4 of the RCR must be set to ‘0’ and Chip Enable,
E, must go High, VIH. When the Deep Power-Down is enabled, the data stored in the device
may be corrupted and BCR, RCR and DIDR content are saved.
To exit Deep Power-Down, the Chip Enable signal, E, must be held Low, VIL, for a minimum
time of tEHEL(DP). Bit 4 of the RCR will be automatically set to ‘1’. Once the Deep Power-Down
is exited, the device will be available for normal operations after tVCHEL (time to perform an
initialization sequence) During this delay, the current consumption will be higher than the
specified Standby levels, but considerably lower than the active current. The content of the
registers will be restored after Deep Power-Down.
For details on how to enter Deep Power-Down, refer to Table 3: Standard Asynchronous
Operating Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous mode)
and Table 6: Synchronous Read Operations (NOR-Flash Synchronous mode).
13/68
4 Low-power modes
4.3
M69KB128AA
Partial Array Self Refresh
The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM array.
This mechanism enables the device to reduce the Standby current by refreshing only the part of
the memory array that contains essential data. Different refresh options can be defined by
setting the RCR0 to RCR2 bits of the RCR:
●
Full array
●
One eighth of the array
●
One half of the array
●
One quarter of the array
●
None of the array.
These memory areas can be located either at the top or bottom of the memory array.
The WAIT signal is used for arbitration when a read/write operation is launched while an onchip refresh is in progress. If locations are addressed while they are undergoing refresh, the
WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see
Figure 6: Refresh Collision during Synchronous Read Operation in Variable Latency mode).
When the refresh operation is completed, the read or write operation will be allowed to continue
normally.
14/68
M69KB128AA
5
5 Standard asynchronous operating modes
Standard asynchronous operating modes
The M69KB128AA supports Asynchronous Read and Write modes (Random Read, Page
Read, Asynchronous Write).
The device is put in Asynchronous mode by setting bit 15 (BCR15) of the BCR to ‘1’. The Page
mode is controlled by the Refresh Configuration Register (bit RCR7).
During asynchronous operations, the WAIT signal should be ignored and the Clock input signal
K should be held Low, VIL.
Refer to Table 3: Standard Asynchronous Operating Modes for a detailed description of
asynchronous operating modes.
5.1
Asynchronous Read and Write modes
At Power-Up, the device defaults to Asynchronous Random Read mode (bit BCR15 set to ‘1’).
This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations are
initiated by bringing E and G Low, VIL, while keeping W High, VIH. Valid data will be gated
through the output buffers after the specific access time tELQV has elapsed.
Write operations occur when E and W are Low. During Asynchronous Random Write
operations, the G signal is ‘don't care’ and W will override G. The data to be written is latched
on the rising edge of E, W, LB or UB (whichever occurs first). The write operation is terminated
by de-asserting E, W, LB or UB.
The L input can either be used to latch the address or kept Low, VIL, during the entire read/write
operation.
See Figure 14 and Figure 15, and Table 17 for details on Asynchronous Read AC waveforms
and characteristics and Figure 18, Figure 19, Figure 20, and Figure 19 for details of
Asynchronous Write AC waveforms and characteristics.
5.2
Asynchronous Page Read mode
Asynchronous Page Read mode is enabled by setting RCR7 to ‘1’. The Latch Enable, L, and
the Chip enable E must be held Low, VIL during Asynchronous Page Read operations.
A Page of data is internally read. A memory page may consist of 4, 8 or 16 Words. During a 4Word page access, all the address bits except A0 to A1 should be fixed. During a 8-Word and
16-Word page access, all address bits are fixed except A0 to A2 and A0 to A3, respectively
(see Table 2: Page Mode Characteristics).
The first read operation within the Page has the normal access time (tAVQV), subsequent reads
within the same Page have much shorter access times (tAVQV1). If the Page changes then the
normal, longer timings apply again.
The Page mode is not available for write operations.
See Figure 16 and Table 17 for details of the Asynchronous Page Read timing requirements.
15/68
M69KB128AA
5 Standard asynchronous operating modes
Table 2.
5.3
Page Mode Characteristics
Page Size
Page Read Address
Page Read Start Address
Page Read Direction
4 Words
A0-A1
Don’t Care
Don’t Care
8 Words
A0-A2
Don’t Care
Don’t Care
16 Words
A0-A3
Don’t Care
Don’t Care
Configuration Registers Asynchronous Read and Write
Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR)
can be performed using the CR controlled method in standard Asynchronous mode.
16/68
M69KB128AA
Table 3.
5 Standard asynchronous operating modes
Standard Asynchronous Operating Modes
Asynchronous
Modes(1)
E
Valid
Output
Valid
Output
Valid
VIL
Valid
Output
Valid
High-Z
VIH
VIL
Valid
High-Z
Output
Valid
VIL
VIL
VIL
Valid
Input
Valid
Input
Valid
X
VIH
VIL
VIL
Valid
Input
Valid
Invalid
X
VIL
VIH
VIL
Valid
Invalid
Input
Valid
LB
Word Read
VIL
VIL
VIL
VIL
Lower Byte
Read
VIH VIL VIH
VIL
Upper Byte
Read
VIL
VIL
Word Write
X
VIL
Active
(ICC)
VIL
VIL
Read
Configuration
Register
(CR Controlled
Method)
VIH VIL
Deep
Power-Down(4)
Standby
VIL
WAIT CR A19 A18
LowZ
00(RCR)
10(BCR)
X1(DIDR)
VIL
A0-A17
A20-A22
X
BCR/
RCR/DIDR
Content
BCR/
RCR
Data
High-Z
(2)
VIH
Program
Configuration
Register (CR
Controlled)(3)
No Operation
W
DQ8DQ15
UB
Upper Byte
Write
L
DQ0DQ7
G
Lower Byte
Write
Power
VIH
X
X
00(RCR)
10(BCR)
X
(2)
Active
(ICC)
Deep
PowerDown
(ICCPD)
Standby
(IPASR)
X
VIH
X
X
X
X
X
X
X
X
VIL
X
X
X
X
X
X
X
X
High-Z
VIL
X
X
X
High-Z
HighZ
VIH
X
X
X
X
1. The Clock signal, K, must remain Low in asynchronous operating mode.
2. A18 and A19 are used to select the BCR, RCR or DIDR registers.
3. BCR and RCR only.
4. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
‘0’, and E has to be maintained High, VIH, during Deep Power-Down mode.
17/68
6 Synchronous operating modes
6
M69KB128AA
Synchronous operating modes
The synchronous modes allow high-speed read and write operations synchronized with the
clock. Refresh cycles are indicated to the host system by asserting the WAIT signal that, in
turn, stalls the microcontroller.
The M69KB128AA supports two types of synchronous modes:
●
NOR-Flash:- this mode greatly simplifies the interfacing with traditional burst-mode Flash
memory microcontrollers.
●
Full Synchronous: both read and write are performed in Synchronous mode.
All the options related to the synchronous modes can be configured through the Bus
Configuration Register, BCR. In particular, the device is put in Synchronous mode, either NORFlash or Full Synchronous, by setting bit BCR15 of the Bus Configuration Register to ‘0’.
The device will automatically detect whether the NOR-Flash or the Full Synchronous mode is
being used by monitoring the Clock, K, and the Latch Enable, L, signals. If a rising edge of the
Clock K is detected while L is held Low, VIL (active), the device operates in Full Synchronous
mode.
6.1
NOR-Flash Synchronous mode
In this mode, the device operates in synchronous mode for read operations, and in
asynchronous mode for write operations.
Asynchronous write operations are performed at Word level, with LB and UB Low. The data is
latched on E, W, LB, UB, whichever occurs first. RCR and BCR registers can be programmed in
NOR-Flash Asynchronous Write mode, using the CR controlled method (see Section 7.1:
Programming the Registers by the CR controlled method). A Program Configuration Register
operation can only be issued if the device is in idle state and no burst operations are in
progress. NOR-Flash Asynchronous Write operations are described in Table 5: Asynchronous
Write Operations (NOR-Flash Synchronous mode).
Synchronous read operations are also performed at Word level. They are controlled by the
state of E, L, G, W, LB and UB signals when a rising edge of the clock signal, K, occurs. The
initial Burst Read access latches the Burst start address. The number of Words to be output is
controlled by bits 0 to 2 of the BCR. The first data will be output after a number of clock cycles,
also called Latency. NOR-Flash Synchronous Burst Read operations are described in Table 6:
Synchronous Read Operations (NOR-Flash Synchronous mode).
When a Burst Write operation is initiated or when switching from NOR-Flash mode to Full
Synchronous mode, the delay from E Low to Clock High, tELKH, should not exceed 20ns.
However, when it is not possible to meet these specifications, special care must be taken to
keep addresses stable after driving the Write Enable signal, W, Low.
Write operations are considered as Asynchronous operations until the device detects a valid
clock edge and hence the address setup time of tAVWL must be satisfied (see Figure 5:
Switching from Asynchronous to Synchronous Write operation).
18/68
M69KB128AA
6.2
6 Synchronous operating modes
Full Synchronous mode
In Full Synchronous mode, the device performs read and write operations synchronously.
Synchronous Read and Write operations are performed at Word level.
The initial Burst Read and Write access latches the Burst start address. The number of Words
to be output or input during Synchronous Read and Write operations is controlled by bits 0 to 2
of the BCR.
During Burst Read and Write operations, the first data will be output after a number of clock
cycles defined by the Latency value.
Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR)
can be performed using the CR controlled method in Full Synchronous mode.
Full Synchronous operations are described in Table 7: Full Synchronous mode.
6.3
Synchronous Burst Read and Write
During Synchronous Burst Read or Write operations, addresses are latched on the rising edge
of the Clock K when L is Low and data are latched on the rising edge of K. The Write Enable,
W, signal indicates whether the operation is going to be a read (W=VIH) or a write (W=VIL).
The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and will
be deasserted to indicate when data are to be transferred to (or from) the memory array.
The Burst Length is the number of Words to be output or input during a Synchronous Burst
Read or Write operation. It can be configured as 4, 8, 16 or 32 Words or continuous through bit
BCR0 to BCR2 or the Burst Configuration Register. The Latency defines the number of clock
cycles between the beginning of a Burst Read operation and the first data output (counting from
the first Clock edge where L was detected Low) or between the beginning of a Burst Write
operation and the first data input. The Latency can be set through bits BCR13 to BCR11 of the
Bus Configuration Register (see Table 4: Operating Frequency versus Latency).
The latency can also be configured to fixed or variable by programming bit BCR14. By default,
the Latency Type is set to variable.
Synchronous Read operations are performed in both fixed and variable latency mode while
Synchronous Write operations are only performed with fixed latency.
See Figure 24, Note 1, and Figure 30, Note 31, for details on Synchronous Read and Write AC
waveforms, respectively.
19/68
6 Synchronous operating modes
6.3.1
M69KB128AA
Variable Latency
In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is
maintained only if there is no conflict with a refresh operation.
The Latency set in the BCR is applicable only for an initial burst read access, when no refresh
request is pending. For a given latency value, the Variable Latency mode allows higher
operating frequencies than the Fixed Latency mode (see Table 4: Operating Frequency versus
Latency and Figure 3: Latency Configuration (Variable Latency mode, no Refresh collision)).
Burst Write operations are always performed at fixed latency, even if BCR14 is configured to
Variable Latency (see Section 6.3.2: Fixed Latency).
Monitoring of the WAIT signal is recommended for reliable operation in this mode.
See Figure 24. and Figure 31 for details on Synchronous Burst Read and Write AC waveforms
in Variable Latency mode.
6.3.2
Fixed Latency
The latency programmed in the BCR is the real latency. The number of clock cycles is
calculated by taking into account the time necessary for a refresh operation and the time
necessary for an initial Burst access. This limits the operating frequency for a given latency
value (see Table 4: Operating Frequency versus Latency and Figure 4: Latency Configuration
(Fixed Latency mode)).
It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the
WAIT signal.
6.3.3
Row Boundary crossing
The M69KB128AA features 128-Word rows. Row boundary crossings between adjacent rows
may occur during Burst Read and Write operations. Row boundary crossings are not handled
automatically by the PSRAM.
The microcontroller must stop the Burst operation at the row boundary and restart it at the
beginning of the next row. Burst operations must be stopped by driving the Chip Enable signal,
E, High, after the WAIT signal falling edge. E must transition:
●
Before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0
●
Before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1.
Refer to Figure 26 and Figure 30 for details on how to manage row boundary crossings during
burst operations.
20/68
M69KB128AA
6.4
6 Synchronous operating modes
Synchronous Burst Read Interrupt
Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the
following means:
●
Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If
necessary, refresh cycles will be added during the new Burst operation to schedule any
outstanding refresh. If Variable Latency mode is set, additional wait cycles will be added if
a refresh operation is scheduled during the Synchronous Burst Read Interrupt. WAIT
monitoring is mandatory for proper system operation.
●
Starting a new Synchronous Burst Read operation without toggling E.
An ongoing Burst Read operation can be interrupted only after the first valid data is output.
When a new Burst access starts, I/O signals immediately become high impedance.
6.5
Synchronous Burst Write Interrupt
Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the
following means:
●
Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended),
●
Starting a new Synchronous Burst Write without toggling E. Considering that Burst Writes
are always performed in Fixed Latency mode, refresh is never scheduled. A maximum
Chip Enable, E, low time (tELEH) must be respected for proper device operation.
An ongoing Burst Write can be interrupted only after the first data is input. When a new Burst
access starts, I/O signals immediately become high impedance.
See Figure 27: Burst Read Interrupted by Burst Read or Write AC Waveforms and Figure 32:
Burst Write Interrupted by Burst Write or Read AC Waveforms for details on Burst Read and
Burst Write interrupt AC waveforms, respectively.
6.6
Synchronous Burst Read and Write Suspend
Synchronous Burst Read and Write operations can be suspended by halting the Clock K
holding it either High or Low. The status of the I/O signals will depend on the status of Output
enable input, G. The device internal address counter is suspended and data outputs become
high impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to
suspend the first data output at the beginning of a Synchronous Burst Read.
See Figure 25 for details on the Synchronous Burst Read and Write Suspend mechanisms.
During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the WAIT
output will be asserted. Bit BCR8 of the Bus Configuration Register is used to configure when
the transition of the WAIT output signal between the asserted and the deasserted state occurs
with respect to valid data available on the data bus.
21/68
M69KB128AA
6 Synchronous operating modes
Table 4.
Operating Frequency versus Latency
Latency
Configured
Latency
Latency
Mode
Fixed
Latency
BCR14 = 1
Table 5.
Normal
If
Refresh
Collision
104 MHz
80 MHz
66 MHz
2 (3 clock cycles)
3
5
66
52
40
3 (4 clock cycles)
(default)
4
7
104
80
66
All Others
-
-
-
-
-
(Clock Cycles)
Variable
Latency
BCR14 = 0
(Default)
2 (3 clock cycles)
3
33
33
20
3 (4 clock cycles)
(default)
4
52
52
33
4 (5 clock cycles)
5
66
66
40
5 (6 clock cycles)
6
75
75
52
6 (7 clock cycles)
7
104
80
66
All Others
-
-
-
-
Asynchronous Write Operations (NOR-Flash Synchronous mode)
Asynchronous
Power
Operations
K
Word Write
Program
Configuration
Register (CR
Controlled)(1)
No Operation
Active (ICC)
Active (ICC)
VIL
L
E
W
G
UB,
LB
VIL
VIL
VIL
X
VIL
VIL
VIL
VIL
VIH
X
LowVIH
Z
VIH
X
X
X
X
VIL
X
X
VIH
X
X
X
VIL
X
High-Z
X
X
High-Z
Standby
Standby
(IPASR)
X
Deep
Power-Down
Deep
Power-Down
(ICCPD)
X
1. BCR and RCR only.
22/68
Max Input Clock Frequency (MHz)
(Clock Cycles)
WAIT CR A19 A18 A0-A22 DQ0-DQ15
VIL
Valid
00(RCR)
10(BCR)
Input Valid
RCR/
BCR
Data
High-Z
HighZ
VIH
X
X
X
M69KB128AA
Table 6.
6 Synchronous operating modes
Synchronous Read Operations (NOR-Flash Synchronous mode)
Synchronous
Operations(1)
CR
A19
A18
A0A22(2)
DQ15DQ0
VIL
VIL
Valid
Valid
Valid
Output
Valid
VIL(3)
VIL
K
E
L
W
G
LB,
UB
Initial Burst
Read
=
VIL
VIL
VIH
X
Subsequent
Burst Read
=
VIL
VIH
X
X
Read
Configuration
Register
(CR Controlled
Method)
No Operation
Power
WAIT
Output
Valid
X
Active (ICC)
Low-Z
VIL
VIH
VIL
VIL
VIH
VIL
X
X
X
X
VIL
X
X
VIL VIH
X
X
X
X
VIL
X
High-Z
X
X
High-Z
Active (ICC) VIL
Standby
(IPASR)
Deep
Power-Down
Deep
PowerDown
(ICCPD)
RCR/
BCR/
DIDR
Content
VIL
=
Standby
00(RCR)
10(BCR)
X1(DIDR)
X
HighZ
VIL VIH
X
X
X
X
1. Burst Read Interrupt, Suspend and Terminate are described in dedicated paragraph of the Section 6: Synchronous
operating modes.
2. Except A18 and A19.
3. The above table shows the device behavior if both LB and UB are asserted, VIL. If either LB or UB is High, VIH, only one
Byte will be input or output, according to the status of W.
23/68
M69KB128AA
6 Synchronous operating modes
Table 7.
Full Synchronous mode
Synchronous
Mode(1)
CR
A19
A18
A0A22(2)
DQ15DQ0
VIL
VIL
Valid
Valid
Valid
X
VIL
VIL(3)
VIL
X
VIL
VIH
X
VIL
Valid
Valid
Valid
Input
Valid
VIH
X
VIH
VIL(2)
X
X
X
X
Input
Valid
VIL
VIL
VIH
X
RCR/
BCR
Data
X
X
RCR/
BCR/
DIDR
Content
K
E
L
W
G
LB,
UB
Initial Burst
Read
=
VIL
VIL
VIH
X
Subsequent
Burst Read
=
VIL
VIH
X
Initial Burst
Write
=
VIL
VIL
Subsequent
Burst Write
=
VIL
=
VIL
Program
Configuration
Register
(CR
Controlled)
Power
Active
(ICC)
Read
Configuration
Register
(CR
Controlled
Method)
No Operation
Standby
Deep
Power-Down
WAIT
Low-Z
Output
Valid
X
VIH
00(RCR)
10(BCR)
VIL
VIH
VIL
VIL
VIH
00(RCR)
10(BCR)
X1(DIDR)
VIL VIL
X
X
X
X
VIL
X
X
Standby
VIL VIH
(IPASR)
X
X
X
X
VIL
X
High-Z
X
X
High-Z
=
Active
(ICC)
Deep
PowerDown
(ICCPD)
VIL
High-Z
VIL VIH
X
X
X
X
1. Burst Read Interrupt, Suspend, Terminate and Burst Write Interrupt, Suspend and Terminate are described in dedicated
paragraph of the Section 6: Synchronous operating modes.
2. Except A18 and A19.
3. The above table shows the device behavior if both LB and UB are asserted, VIL. If either LB or UB is High, VIH, only one
Byte will be input or output, according to the status of W.
24/68
M69KB128AA
Figure 3.
6 Synchronous operating modes
Latency Configuration (Variable Latency mode, no Refresh collision)
K
0
1
2
3
4
5
6
7
Address
Valid
Addr.
ADV
Latency = 3 Clock Cycles
DQ0-DQ15
Hi Z
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Latency = 4 Clock Cycles
DQ0-DQ15
Hi Z
AI11280
Figure 4.
Latency Configuration (Fixed Latency mode)
N-1
Cycle
N
Cycle
K
tAVQV
Address
Valid
Addr.
tLLQV
ADV
tELQV
E
tKHQV2
DQ0-DQ15
OUT
Hi Z
Q1
Q2
Q3
Q4
Q5
AI11281b
1. See Table 21: Synchronous Burst Read AC Characteristics for details on the synchronous read AC Characteristics shown
in the above waveforms.
25/68
M69KB128AA
6 Synchronous operating modes
Figure 5.
Switching from Asynchronous to Synchronous Write operation
K
VALID
Addr.
tAVWL
L
tELKH
E
W
AI10203
Figure 6.
Refresh Collision during Synchronous Read Operation in Variable Latency mode
K
A0-A22
Address
Valid
L
E
G
W
LB/UB
WAIT
Hi Z
Hi Z
Q0
DQ0-DQ15
Q1
Q2
Q3
Additional WAIT states inserted
to allow Refresh completion
AI11275b
1. Additional Wait states are inserted to allow Refresh completion.
The latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT must be active Low, VIL, (BCR10 = 0) and asserted
during delay (BCR8= 0).
26/68
M69KB128AA
7
7 Configuration registers
Configuration registers
The M69KB128AA features three registers:
●
The Bus Configuration Register (BCR)
●
The Refresh Configuration Register (RCR)
●
The Device ID Register (DIDR).
BCR and RCR are user-programmable registers that define the device operating mode. They
are automatically loaded with default settings during Power-Up, and selected by address bits
A18 and A19 (see Table 8: Register Selection).
DIDR is a read-only register that contains information about the device identification. It is
selected by setting address bit A18 to ‘1’ with A19 ‘don’t care’ (see Table 8: Register Selection).
The configuration registers (only BCR and RCR) can be programmed and read using two
methods:
●
The CR Controlled Method (or Hardware Method)
●
The Software Method.
7.1
Programming the Registers by the CR controlled method
7.1.1
Read Configuration Register
The content of a register is read by issuing a read operation with Configuration Register Enable
signal, CR, High, VIH. Address bits A18 and A19 select the register to be read (see Table 8:
Register Selection). The value contained in the register is then available on data bits DQ0 to
DQ15.
The BCR, RCR and DIDR can be read either in normal asynchronous or synchronous mode.
The CR pin has to be driven high prior to any access.
See Table 6 and Table 7 for a detailed description of Configuration register Read by the CR
Controlled methods and Figure 17 and Figure 28, CR Controlled Configuration Register Read
waveforms in asynchronous and synchronous mode.
7.1.2
Program Configuration Register
BCR and RCR registers can be programmed by issuing a bus write operation, in asynchronous
or synchronous mode (NOR-Flash or Full Synchronous), with Configuration Register Enable
signal, CR, High, VIH. Address bits A18 and A19 allow to select between BCR and RCR (see
Table 8: Register Selection).
In synchronous mode, the values placed on address lines A0 to A15 are latched on the rising
edge of L, E, or W, whichever occurs first.
In asynchronous mode, a register is programmed by toggling L signal.
LB and UB are ‘don’t care’. The CR pin has to be driven high prior to any access.
Refer to Table 5 and Table 7 for a detailed description of Configuration Register Program by the
CR Controlled method and to Figure 22 and Figure 33, showing CR controlled Configuration
Register Program waveforms in asynchronous and synchronous mode.
27/68
M69KB128AA
7 Configuration registers
Table 8.
7.2
Register Selection
Register
Read or Write Operation
A18
A19
RCR
Read/Write
0
0
BCR
Read/Write
0
1
DIDR
Read-Only
1
X
Programming and Reading the Registers by the software
method
All registers (BCR, RCR, DIDR) can be read by issuing a Read Configuration Register
sequence (see Figure 8: Read Configuration Register (Software Method).
BCR and RCR can be programmed by issuing a Set Configuration Register sequence (see
Figure 7: Set Configuration Register (Software Method).
The timings will be identical to those described in Table 17: Asynchronous Read AC
Characteristics. The Configuration Register Enable input, CR, is ‘don’t care’.
Read Configuration Register and Set Configuration Register sequences both require 4 read or
write cycles. These cycles will be executed in asynchronous mode, whatever the device
operating mode:
1.
2 bus read and one bus write cycles to a unique address location, 7FFFFFh, indicate that
the next operation will read or write to a configuration register. The data written during the
third cycle must be ‘0000h’ to access the RCR, ‘0001h’ to access the BCR and ‘0002h’ to
access the DIDR during the next cycle.
2.
The fourth cycle reads from or writes to the configuration register.
The timings for programming and reading the registers by the software method are identical to
the asynchronous write and read timings.
28/68
M69KB128AA
Figure 7.
7 Configuration registers
Set Configuration Register (Software Method)
Addr.
7FFFFFh
7FFFFFh
7FFFFFh
tEHEL2
tEHEL2
tEHEL2
7FFFFFh
E
G
W
LB, UB
DQ0-DQ15
Configuration
Register Data
(2)
AI09469f
1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to ‘0001h’ and ‘0000’ respectively.
3. The highest order address location is not modified during this operation.
4. The control signal E must be toggled as shown in the above figure.
Figure 8.
Read Configuration Register (Software Method)
Addr.
7FFFFFh
7FFFFFh
7FFFFFh
tEHEL2
tEHEL2
tEHEL2
7FFFFFh
E
G
W
LB, UB
DQ0-DQ15
(1)
Configuration
Register Data
AI09470f
1. To read the BCR, RCR or DIDR on last bus read cycle, DQ0-DQ15 must be set to ‘0001h’, ‘0000’ and ‘0002’ respectively.
2. The highest order address location is not modified during this operation.
3. The control signal E must be toggled as shown in the above figure.
29/68
7 Configuration registers
7.3
M69KB128AA
Bus Configuration Register
The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system
memory bus. All the device operating modes are configured through the BCR, except the Page
mode which is configured through the RCR.
Refer to Table 9 for the description of the Bus Configuration Register Bits.
7.3.1
Operating Mode Bit (BCR15)
The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default
setting) to be selected. Selecting the Synchronous mode will allow the device to operate either
in NOR Flash mode or in full Synchronous Burst mode.
The device will automatically detect that the NOR Flash mode is being used by monitoring a
rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device
operates in full Synchronous mode.
7.3.2
Latency Type (BCR14)
The Latency Type bit is used to configure the latency type. When the Latency Type bit is set to
‘0’, the device operates in variable latency mode (only available for Synchronous Read mode).
When it is ‘1’, the fixed latency mode is selected and the latency is defined by the values of bits
BCR13 to BCR11.
Refer to Table 3 and Table 4 for examples of fixed and variable latency configuration.
7.3.3
Latency Counter Bits (BCR13-BCR11)
The Latency Counter bits are used to set the number of clock cycles between the beginning of
a read or write operation and the first data output or input.
The Latency Counter bits can only assume the values shown in Table 9: Bus Configuration
Register Definition (see also Figure 3 and Figure 4).
7.3.4
WAIT Polarity Bit (BCR10)
The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a
consequence, it also determines whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state (see Figure 10: WAIT Polarity).
By default, the WAIT output signal is active High.
7.3.5
WAIT Configuration Bit (BCR8)
The system memory microcontroller uses the WAIT signal to control data transfer during
Synchronous Burst Read and Write operations.
The WAIT Configuration bit is used to determine when the transition of the WAIT output signal
between the asserted and the deasserted state occurs with respect to valid data available on
the data bus. When the Wait Configuration bit is set to ‘0’, data is valid or invalid on the first
Clock rising edge immediately after the WAIT signal transition to the deasserted or asserted
state. When the Wait Configuration bit is set to ‘1’ (default settings), the WAIT signal transition
occurs one clock cycle prior to the data bus going valid or invalid.
See Figure 9: WAIT Configuration Example for an example of WAIT configuration.
30/68
M69KB128AA
7.3.6
7 Configuration registers
Driver Strength Bits (BCR5-BCR4)
The Driver Strength bits allow to set the output drive strength to adjust to different data bus
loading. Normal driver strength (full drive) and reduced driver strength (half drive and a quarter
drive) are available.
By default, outputs are configured at ‘half drive” strength.
7.3.7
Burst Wrap Bit (BCR3)
Burst Read operations can be confined inside the 4, 8, 16 or 32 Word boundary (wrap) or
allowed to step across the boundary (no wrap). The Burst Wrap bit is used to select between
‘wrap’ and ‘no wrap’. If the Burst Wrap bit is set to ‘1’ (no wrap), the device outputs data
sequentially regardless of burst boundaries. When Continuous Burst operation is selected, the
internal address switches to 000000h if the read address passes the last address. By default,
Burst wrap is disabled (see also Table 10: Burst Type Definition).
7.3.8
Burst Length Bits (BCR2-BCR0)
The Burst Length bits set the number of Words to be output or input during a Synchronous
Burst Read or Write operation. They can be set for 4 Words, 8 Words, 16 Words, 32 Words or
Continuous Burst (default settings), where all the Words are output or input sequentially
regardless of address boundaries (see also Table 10: Burst Type Definition).
31/68
M69KB128AA
7 Configuration registers
Table 9.
Bus Configuration Register Definition
Address
Bits
Bus
Configuration
Register Bits
Name
A15
BCR15
Operating Mode
Bit
A14
A13-A11
BCR14
BCR13BCR11
Value
Description
0
Synchronous Mode (NOR Flash or Full
Synchronous Mode)
1
Asynchronous Mode (Default)
0
Variable Latency (Default)
1
Fixed Latency
010
3 Clock Cycles
011
4 Clock Cycles (Default)
Latency Type
Latency Counter 100
Bits
101
5 Clock Cycles
110
7 Clock Cycles
6 Clock Cycles
Other Configurations Reserved(1)
A10
A9
A8
A7-A6
A5-A4
A3
A2-A0
BCR10
-
BCR8
Wait
Configuration Bit
BCR5-BCR4
BCR3
BCR2-BCR0
WAIT Active Low
1
WAIT Active High (default).See Figure 10:
WAIT Polarity.
WAIT Polarity Bit
-
-
0
-
Driver Strength
Bits
Must be set to ‘0’ Reserved(1)
0
WAIT Asserted During Delay (see Figure 9:
WAIT Configuration Example).
1
WAIT Asserted One Clock Cycle Before Delay
(Default)
Must be set to ‘0’ Reserved(1)
00
Full Drive
01
1/2 Drive (Default)
10
1/4 Drive
11
Reserved(1)
0
Wrap
1
No Wrap (Default)
001
4 Words
010
8 Words
011
16 Words
100
32 Words
111
Continuous Burst (default)
Burst Wrap Bit
Burst Length Bit
Other Configurations Reserved(1)
1. Programming the BCR with reserved value will force the device to use the default register settings.
32/68
M69KB128AA
Table 10.
7 Configuration registers
Burst Type Definition
Wrap (BCR3=’0’)
Mode
4 Words
Start
Add
8 Words
16 Words
32 Words
(Sequential)
(Sequential)
(Sequential)
Continuous Burst
BCR2-BCR0=111b
BCR2BCR0=001b
BCR2-BCR0=010b
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-...-14-15
0-1-2-3-...-30-31
0-1-2-3-..-511-.
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-...-14-15-0
1-2-3-...-30-31-0
1-2-3-4-...-510-511-
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-...-15-0-1
2-3-4-...-31-0-1
2-3-4-5-6-...-511-
3
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-...-15-0-1-2
3-4-5-...-31-0-1-2
3-4-5-...-511-
4
4-5-6-7-0-1-2-3
4-5-...-15-0-1-2-3
4-5-6-...-31-0-1-2-3
4-5-...-511-
5
5-6-7-0-1-2-3-4
5-6-7-...-15-0-1-...-4
5-6-7-..-31-0-1-..-4
5-6-7-...-511-
6
6-7-0-1-2-3-4-5
6-7-8-...-15-0-1-...-5 6-7-8-...-31-0-1-...-5
6-7-8-...-511-
7
7-0-1-2-3-4-5-6
7-8-9-...15-0-1-...-6 7-8-9-...-31-0-1-...-6
7-8-9-...-511-
...
...
...
...
14
14-15-0-1-2-...-13
14-15-...-31-0-...-13
14-...511-
15
15-0-1-2-...-14
15-0-1-...-31-0-...14
15-...511-
...
...
...
30
30-31-0-...-28-29
30-...-511-
31
31-0-1-...-29-30
31-...-511-
...
...
BCR2-BCR0=011b BCR2-BCR0=100b
...
...
No Wrap (BCR3=’1’)
(Sequential)
...
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-...-14-15
0-1-2-3-...-30-31
0-1-2-3-..-511-.
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-..-15-16
1-2-3-4-...-32
1-2-3-4-...-512-
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-...-17
2-3-4-...-33
2-3-4-5-...-513-
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-...-18
3-4-5-...-34
3-4-5-...-514-
4
4-5-6-7-8-9-10-11
4-5-6-...-19
4-5-6-...-35
4-5-6-...-515-
5
5-6-7-8-9-10-11-12
5-6-7-...-20
5-6-7-...-36
5-6-7-...-516-
6
6-7-8-9-10-11-12-13
6-7-8-...-21
6-7-8-...-37
6-7-8-...-517-
7
7-8-9-10-11-12-13-14
7-8-9-...-22
7-8-9-...-38
7-8-9-...-518-
...
...
...
14
14-15-...-29
14-15-16-...-46
14-...-525-
15
15-16-17-...-30
15-16-17-...-47
15-...-526-
...
...
...
30
30-31-0-...-28-62
30-...-541-
31
31-0-1-...-29-63
31-...-542-
33/68
M69KB128AA
7 Configuration registers
Figure 9.
WAIT Configuration Example
K
WAIT
DQ0-DQ15
BCR8='0', BCR10='1'
Data Valid During Current Cycle
Hi-Z
DQ0-DQ15
BCR8='1', BCR10='1'
Data Valid During Next Cycle
Hi-Z
Data[0] Data[1]
Data[0]
AI06795b
Figure 10. WAIT Polarity
BCR8='0'
BCR10='0'
BCR8='0'
BCR10='1'
K
WAIT
DQ0-DQ15
Hi-Z
Data[0] Data[1]
WAIT
DQ0-DQ15
Hi-Z
Data[0] Data[1]
AI09963
34/68
M69KB128AA
7.4
7 Configuration registers
Refresh Configuration Register
The role of the Refresh Configuration Register (RCR) is:
●
to define how the self refresh of the PSRAM array is performed,
●
to select the Deep Power-Down mode,
●
to enable Page Read operations.
Refer to Table 11 for the description of the Refresh Configuration Register Bits.
7.4.1
Page Mode Operation Bit (RCR7)
The Page Mode operation bit determines whether the Asynchronous Page Read mode is
enabled. At power-up, the RCR7 bit is set to ‘0’, and the Asynchronous Page Read mode is
disabled.
7.4.2
Deep Power-Down Bit (RCR4)
The Deep Power-Down bit enables or disables all refresh-related operations. The Deep PowerDown mode is enabled when the RCR4 bit is set to ‘0’, and remains enabled until this bit is set
to ‘1’. At power-up, the Deep Power-Down mode is disabled.
See the Section 4.2: Deep Power-Down for more details.
7.4.3
Partial Array Refresh Bits (RCR2-RCR0)
The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the total
PSRAM array. The refresh options can be full array, one half, one quarter, one eighth or none of
the array. These memory areas can be located either at the top or bottom of the memory array.
By default, the full memory array is refreshed.
35/68
M69KB128AA
7 Configuration registers
Table 11.
Refresh Configuration Register Definition
Address
Bits
Refresh
Configuration
Register Bits
Name
A15-A8
-
-
A7
RCR7
Page Mode
Operation Bit
A6-A5
-
-
A4
RCR4
Deep PowerDown Bit
A3
A2-A0
36/68
-
RCR2-RCR0
-
Partial Array
Refresh Bits
Value
Description
Must be set to ‘0’ Reserved
0
Page Read Mode Disabled (Default)
1
Page Read Mode Enabled
Must be set to ‘0’ Reserved
0
Deep Power-Down Enabled
1
Deep Power-Down Disabled (Default)
Must be set to ‘0’ Reserved
000
Full Array Refresh (Default)
001
Refresh of the Bottom Half of the Array
010
Refresh of the Bottom Quarter of the Array
011
Refresh of the Bottom Eighth of the Array
100
None of the Array
101
Refresh of the Top Half of the Array
110
Refresh of the Top Quarter of the Array
111
Refresh of the Top Eighth of the Array
M69KB128AA
7.5
7 Configuration registers
Device ID Register
The Device ID Register (DIDR) is a read-only register that contains the Manufacturer code. It is
preprogrammed by STMicroelectronics and cannot be modified by the user.
Refer to Table 12 for the description of the Bus Configuration Register Bits.
Table 12.
Device ID Register Definition
Address
Bits
Device ID
Register Bits
Name
A15
DIDR15
Row Size
A14-A11
DIDR14-DIDR11
Value
Description
0
128 Words
0000
A
0001
B
0010
C
0011
D
1111
P
Design Version
Other Configurations Reserved
A10-A8
DIDR10-DIDR8
000
16 Mbits
001
256 Mbits
010
64 Mbits
011
128 Mbits
100
32 Mbits
Device Density
Other Configurations Reserved
A7-A5
DIDR7-DIDR5
001
1.0
010
1.5
011
2.0
PSRAM Generation
Other Configurations Reserved
A4-A0
DIDR4-DIDR0
00001
Cypress
00010
Infineon
00011
Micron
00100
Renesas
01111
STMicroelectronics
Device ID
Other Configurations Reserved
37/68
M69KB128AA
8 Maximum Rating
8
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause
permanent damage to the device. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
Table 13.
Absolute Maximum Ratings
Symbol
Min
Max
Unit
Ambient Operating Temperature
–30
+85
°C
TSTG
Storage Temperature
–55
150
°C
VCC
Core Supply Voltage
–0.2
2.45
V
Input/Output Buffer Supply Voltage
–0.2
2.45
V
Input or Output Voltage
–0.2
2.45
V
TA
VCCQ
VIO
38/68
Parameter
M69KB128AA
9
9 DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 14: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 14.
Operating and AC Measurement Conditions
M69KB128AA
Parameter(1)
Unit
Min
Max
VCC Supply Voltage
1.7
1.95
V
VCCQ Input/Output Buffer Supply Voltage
1.7
1.95
V
Load Capacitance (CL)
30
pF
Output Circuit Protection Resistance (R)
50
Ω
Input Pulse Voltages(2)
VCC
0
Input and Output Timing Ref. Voltages(2)
VCC/2
Input Rise Time tr and Fall Time tf(2)(3)
V
V
1
V/ns
1. All voltages are referenced to VSS.
2. VCC=VCCQ
3. Referenced to VSS.
Figure 11. AC Measurement I/O Waveform
I/O Timing Reference Voltage
VCCQ
VCCQ/2
VSSQ
AI09484c
1. Logic states ‘1’ and ‘0’ correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings begin at
VCCQ/2 and output timings end at VCCQ/2.
Figure 12. AC Input Transitions
VCCTyp
VSS
90%
90%
10%
tr
10%
tf
ai10122
39/68
M69KB128AA
9 DC and AC parameters
Figure 13. AC Measurement Load Circuit
VCCQ/2
R
DEVICE
UNDER
TEST
OUT
CL
AI11289
Table 15.
Capacitance
Symbol
Parameter
CIN
Input Capacitance
CIO
Data Input/Output Capacitance
40/68
Test Condition
Min
Max
Unit
TA = 25°C, f = 1MHz,
VIN = 0V
2
6
pF
3.5
6
pF
M69KB128AA
Table 16.
Symbol
9 DC and AC parameters
DC Characteristics
Parameter
Refreshed
Array
Test Conditions
Min.
0.8VCCQ
VOH(1)
Output High Voltage
IOH = –0.2mA
VOL(1)
Output Low Voltage
IOL = 0.2mA
VIH(2)
Input High Voltage
VIL(3)
Input Low Voltage
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1(4)
Asynchronous Read/Write
Random at tRC min
ICC2(4)
Asynchronous Page Read
ICC3(4)
Burst, Initial Read/Write
Access
ICC4R(4) Continuous Burst Read
ICC4W(4)
Continuous Burst Write
Typ.
1/2 Array
Partial Array
Refresh Standby 1/4 Array
Current
1/8 Array
0.2VCCQ
V
VCCQ–0.4
VCCQ +
0.2
V
–0.2
0.4
V
VIN = 0 to VCCQ
1
µA
G = VIH or E = VIH
1
µA
VIN = 0V or VCCQ,
70ns
25
mA
IOUT = 0mA, E = VIL
85ns
22
mA
VIN = 0V or VCCQ
70ns
15
mA
IOUT = 0mA, E = VIL
85ns
12
mA
104MHz
35
mA
80MHz
30
mA
66MHz
25
mA
104MHz
30
mA
80MHz
25
mA
66MHz
20
mA
104MHz
35
mA
80MHz
30
mA
66MHz
25
mA
200
µA
170
µA
155
µA
150
µA
140
µA
200
µA
10
µA
VIN = 0V or VCCQ
IOUT = 0mA, E = VIL
VIN = 0V or VCCQ
IOUT = 0mA, E = VIL
VIN = 0V or VCCQ
IOUT = 0mA, E = VIL
VIN = 0V or VCCQ
E = VCCQ
None
ISB(5)
Standby Current
ICCPD
Deep-Power Down Current
Unit
V
Full Array
IPASR(4)
Max.
VIN = 0V or VCCQ, E = VCCQ
VIN = 0V or VCCQ,
VCC, VCCQ = 1.95V; TA= +85°C
3
1. BCR5-BCR4 = 01 (default settings).
2. Input signals may overshoot to VCCQ+ 1.0V for periods of less than 2ns during transitions.
3. Output signals may undershoot to VSS – 1.0V for periods of less than 2ns during transitions.
4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current
required to drive output capacitance expected for the actual system.
5. ISB maximum value is measured at +85°C with PAR set to Full Array. In order to achieve low standby current, all inputs
must be driven either to VCCQ or VSSQ. ISB might be slightly higher for up to 500ms after Power-up, or when entering
Standby mode.
41/68
M69KB128AA
9 DC and AC parameters
Table 17.
Asynchronous Read AC Characteristics
M69KB128AA
Unit
Symbol
Alt.
Parameter(1)
70ns
Min
tAVQV
85ns
Max
Min
Max
tAA
Address Valid to Output Valid
tAVS
Address Valid to L High
Configuration Register High to L High
tBLQV
tBA
Upper/Lower Byte Enable Low to Output Valid
70
85
ns
tBHQZ(2)
tBHZ
Upper/Lower Byte Enable High to Output Hi-Z
8
8
ns
tBLQX(3)
tBLZ
Upper/Lower Byte Enable Low to Output
Transition
10
tELTV
tCEW
Chip Enable Low to WAIT Valid
1
tELQV
tCO
Chip Enable Low to Output Valid
tELLH
tCVS
Chip Enable Low to L High
7
7
ns
tEHEL
tCPH
Chip Enable High between Subsequent
Asynchronous Operations
5
5
ns
tEHQZ(2)
tHZ
Output Enable High to Output Hi-Z
Chip Enable High to Output Hi-Z
tELQX(3)
tLZ
Chip Enable Low to Output Transition
tGLQV
tOE
Output Enable Low to Output Valid
20
20
ns
tGHQZ(2)
tOHZ
Output Enable Low to Output Hi-Z
8
8
ns
tGLQX(3)
tOLZ
Output Enable Low to Output Transition
3
3
ns
tAVAX
tRC
Read Cycle Time
70
85
ns
tLLLH
tVP
Latch Enable Low Pulse Width
5
7
ns
tLHLL
tVPH
Latch Enable High Pulse Width
10
10
ns
tLLQV
tAADV
Latch Enable Low to Output Valid
tAVH
Latch Enable High to Address Transition
Latch Enable High to Configuration Register
Low
tAVLH
tRHLH
tLHAX
tLHRL
70
5
85
5
ns
10
7.5
1
70
8
10
ns
7.5
ns
85
ns
8
10
70
2
ns
ns
85
2
ns
ns
ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
3. The Low-Z timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
42/68
M69KB128AA
Table 18.
9 DC and AC parameters
Asynchronous Page Read AC Characteristics
M69KB128AA
Symbol
Parameter(1)
Alt.
70ns
Min
85ns
Max
Min
Unit
Max
tAVQV1
tAPA
Page Access Time
20
25
ns
tAVAV
tPC
Page Cycle Time
20
25
ns
tELEH
tCEM
Maximum Chip Enable Pulse Width
tAVQX
tOH
Data Hold from Address Change
4
5
4
5
µs
ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
Figure 14. Asynchronous Random Read AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tAVQV
L
tEHEL
tEHQZ
E
tELQV
tBHQZ
LB/UB
tBLQV
tGHQZ
G
tGLQV
W
DQ0-DQ15
Hi-Z
tGLQX
tBLQX
VALID
OUTPUT
Hi-Z
tELQX
tELTV
WAIT
Hi-Z
Hi-Z
AI11276c
43/68
M69KB128AA
9 DC and AC parameters
Figure 15. Latch Enable Controlled, Asynchronous Random Read AC Waveforms
Addr.
VALID
ADDRESS
tAVQV
tAVLH
tLHAX
L
tLHLL
tEHQZ
tLLQV
tEHEL
tLLLH
E
tELQV
tELLH
G
tGHQZ
tGLQV
tGLQX
LB/UB
tBLQV
tBHQZ
Hi-Z
tBLQX
DQ0-DQ15
Hi-Z
VALID
OUTPUT
tELQX
AI09474f
Figure 16. Asynchronous Page Read AC Waveforms (4 Words)
tAVAX
VALID ADDRESS
A2-A22
Page Address
A0-A1
X
tLHLL
Y
Z
A
tAVAV
tAVAV
tAVAV
L
tELEH
E
tELQV
tBHQZ,
tEHQZ,
tGHQZ
tGLQV, tBLQV
G, LB,UB
tAVQV
DQ0-DQ15
Hi-Z
tAVQV1
DQN+X
DQN+Y
DQN+Z
DQN+A
tAVQX
AI09478e
1. Any address can be used as starting address.
44/68
M69KB128AA
9 DC and AC parameters
Figure 17. CR Controlled Configuration Register Read Followed by Read, Asynchronous Mode
Addr.
(Except A18-A19)
ADDRESS
tRHLH
ADDRESS
A18-19
Select Configuration Register
tLHRL
tAVQV
CR
tLHLL
L
tLLLH
tEHEL
tLLQV
Initiate Configuration Register Access
E
tEHQZ
tELQV
G
W
tGLQX
LB/UB
tELQX
DQ0-DQ15
Configuration Register
Data Valid
Data Valid
AI09471c
1. A18-A19 must be set to ‘00b’ to select RCR, ‘01b’ to select the BCR and ‘1Xb’ to select the DIDR.
45/68
M69KB128AA
9 DC and AC parameters
Table 19.
Asynchronous Write AC Characteristics
M69KB128AA
Symbol
Parameter(1)
Alt.
70ns
Min
85ns
Max
Min
Unit
Max
tAVBL, tAVEL,
tAVWL, tLLWL
tAS
Address Set-up to Beginning of Write Operation
0
0
ns
tAVLH, tRHLH
tAVS
Address Valid to Latch Enable High
Configuration Register High to Latch Enable High
5
5
ns
tAVWH,
tAVEH, tAVBH
tAW
Address Set-up to End of Write Operation
70
85
ns
tAVAX
tWC
Write Cycle Time
70
85
ns
tBW
Upper/Lower Byte Enable Low to End of Write Operation
70
85
ns
tBLBH, tBLEH
tBLWH
tELTV
tCEW Chip Enable Low to WAIT Valid
tEHEL
tCPH
Chip Enable High between Subsequent Asynchronous
Operations
5
5
ns
tELLH
tCVS
Chip Enable Low to L High
7
7
ns
tCW
Chip Enable Low to End of Write Operation
70
85
ns
tDH
Input Hold from Write
0
0
ns
tDW
Input Valid to Write Setup Time
20
20
ns
tHZ
Chip Enable High to WAIT Hi-Z
LB/UB High to WAIT Hi-Z
Write Enable High to WAIT Hi-Z
tLHAX, tLHRL
tAVH
Latch Enable High to Address Transition or
Latch Enable High to Configuration Register Low
2
2
ns
tLLLH
tVP
Latch Enable Low Pulse Width
5
7
ns
tLHLL
tVPH
Latch Enable High Pulse Width
10
10
ns
tLLWH
tVS
Latch Enable Low to Write Enable High
70
85
ns
tWHQZ
tWHZ
Beginning of Asynchronous Write to Data Output Hi-Z
tWLBH,
tWLEH,
tWP
Write Pulse Width
1
7.5
1
7.5
ns
tELWH
tELEH
tELBH
tEHDX,
tWHDX,
tBHDX
tELWH,
tDVBH, tDVEH
tDVWH
tEHTZ,
tBHTZ(2)
tWLWH(3)
46/68
8
8
10
45
10
55
ns
ns
ns
M69KB128AA
9 DC and AC parameters
M69KB128AA
Symbol
Parameter(1)
Alt.
70ns
Min
tWHWL
Max
85ns
Min
Unit
Max
tWPH Write Enable Pulse Width High
10
10
ns
tWR
0
0
ns
tWHAX,
tEHAX, tBHAX
Write Recovery Time
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. The Low-Z timings measure a 100mV
transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
3. W Low time must be limited to tEHEL.
Figure 18. Chip Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tAVEH
tEHAX
L
tAVEL,
tAVBL
tEHEL
tELEH
E
tBLEH
LB/UB
G
tWHWL
tWLEH
W
Hi-Z
tELTV
WAIT
tEHDX
tDVEH
DQ0-DQ15
Hi-Z
VALID INPUT
tEHTZ
Hi-Z
AI11284b
1. Data Inputs are Hi-Z if E is High, VIH.
47/68
M69KB128AA
9 DC and AC parameters
Figure 19. Upper/Lower Byte Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tAVBH
tBHAX
L
tELBH
E
tBLBH
LB/UB
G
tWHWL
tWLBH
W
tDVBH
Hi-Z
DQ0-DQ15
IN
VALID INPUT
tELQX
DQ0-DQ15
OUT
Hi-Z
tWLQZ
DON'T CARE
tELTV
WAIT
tBHDX
Hi-Z
tBHTZ
Hi-Z
AI11285b
1. Data Inputs are Hi-Z if E is High, VIH.
48/68
M69KB128AA
9 DC and AC parameters
Figure 20. Write Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tWHAX
tAVWH
L
tELWH
E
tBLWH
LB/UB
G
tWLWH
tWHWL
W
tAVWL
DQ0-DQ15
Hi-Z
tDVWH
tWHDX
VALID INPUT
tELTV
WAIT
Hi-Z
Hi-Z
AI11282b
1. Data Inputs are Hi-Z if E is High, VIH.
49/68
M69KB128AA
9 DC and AC parameters
Figure 21. L Controlled, Asynchronous Write AC Waveforms
Addr.
VALID ADDRESS
tAVLH
tLHAX
tLLWH
tLHLL
tLLLH
L
tAVWH
tELWH
E
tBLWH
LB/UB
G
tWLWH
tWHWL
W
tLLWL
DQ0-DQ15
tDVWH
Hi-Z
tEHDX
VALID INPUT
tELTV
WAIT
1. Data Inputs are Hi-Z if E is High, VIH.
50/68
Hi-Z
Hi-Z
AI11283c
M69KB128AA
9 DC and AC parameters
Figure 22. CR Controlled Configuration Register Program, Asynchronous Mode
OPCODE(3)
Addr.
(Except A18-A19)
tAVLH
A18-A19
tLHAX
00(RCR), 01 (BCR)
L
tLHLL
tLLLH
E
Access to Configuration Register
G
W
tWLWH
A0-A15 Latched
into Register
CR
tRHLH
tLHRL
LB, UB
AI09467f
1. Only the content of the Bus Configuration Register (BCR) and Refresh Configuration Register (RCR) can be modified.
2. Data Inputs/Outputs are not used.
3. The Opcode is the value to be written the configuration register.
4. W must go High after L goes High
5. CR is latched on the rising edge of L. There is no setup requirement of CR with respect to E.
51/68
M69KB128AA
9 DC and AC parameters
Table 20.
Clock Related AC Timings
M69KB128AA
Symbol
Alt.
Parameter
104MHz
Min
fCLk
fCLk
Clock frequency
tKHKH
tCLK
Clock Period
tKHKL
Clock Rise Time
Clock Fall Time
tR
tF
tKHKL
80MHz
Max
Min
66MHz
Max
104
Min
Max
80
9.62
Unit
66
12.5
15
1.6
MHz
ns
1.8
2.0
ns
tKP
Clock High to Clock Low
Clock Low to Clock High
3
tKHDZ
tKHZ
Clock High to Output Hi-Z
3
8
3
8
3
8
ns
tKHDX
tKLZ
Clock High to Output Transition
2
5
2
5
2
5
ns
tKLKH
Table 21.
4
5
ns
Synchronous Burst Read AC Characteristics
M69KB128AA
Symbol
Alt.
Parameter(1)
104MHz
Min
tAVQV
tAA
tLLQV
Max
80MHz
Min
Max
66MHz
Min
Unit
Max
Address Valid to Output Valid (Fixed Latency)
70
70
85
ns
tAADV
Latch Enable Low to Output Valid (Fixed
Latency)
70
70
85
ns
tKHQV1
tABA
Burst to Read Access Time (Variable
Latency)
35
46
55
ns
tKHQV2
tACLK Clock High to Output Delay
7
9
11
ns
tGLQV
tBOE
20
20
20
ns
Delay From Output Enable Low to Output
Valid in Burst mode
tEHEL(2)
Chip Enable High between Subsequent
tCBPH Operations in Full-Synchronous or NORFlash mode.
tELEH(2)
tCEM
Chip Enable Pulse Width
tCEW
Chip Enable Low to WAIT Valid
Latch Enable Low to WAIT Valid
tELQV
tCO
Chip Enable Low to Output Valid
tELKH
tCSP
Chip Enable Low to Clock High
tELTV
tLLTV
52/68
5
6
4
1
7.5
4
1
70
3
8
7.5
1
70
4
5
ns
4
µs
7.5
ns
85
ns
ns
M69KB128AA
9 DC and AC parameters
M69KB128AA
Symbol
Alt.
Parameter(1)
104MHz
Min
Max
80MHz
Min
Max
66MHz
Min
Unit
Max
tKHAX
tKHBH
tKHWL
tKHEH
tHD
Hold Time From Active Clock Edge
tHZ
Chip Enable High to Output Hi-Z or WAIT HiZ
2
2
2
ns
tKHLH
tKHQX
tEHQZ
tEHTZ(3)
tKHTX
tKHTV
tKHTL Clock High to WAIT Valid
8
8
8
ns
7
9
11
ns
5
ns
tKHQX1
tKLZ
Clock High to Output Transition
2
tKHQX2
tKOH
Output Hold from Clock High
2
tGHQZ(3)
tOHZ
Output Enable High to Output Hi-Z
tGLQX(4)
tOLZ
Output Enable Low to Output Transition
3
3
3
ns
tSP
Set-up Time to Active Clock Edge
3
3
3
ns
5
2
5
2
8
2
2
8
ns
8
ns
tAVKH
tRHKH
tQVKH
tLLKH
tBLKH
tWHKH
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge
of K; or if E is High for longer than 15ns.
3. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
4. The Low-Z timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
53/68
M69KB128AA
9 DC and AC parameters
Figure 23. Clock input AC Waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
Figure 24. 4-Word Synchronous Burst Read AC Waveforms (Variable Latency Mode)
tKHKH
tKHKL
K
tAVKH tKHAX
VALID
ADDRESS
Addr.
tKHLH
tLLKH
tLHLL
L
tELEH
tELKH
tKHQV1
tEHEL
tKHEH
E
tGLQV
tEHQZ
G
tWHKH
tGHQZ
tGLQX
tKHWL
W
tBLKH
tKHBH
LB/UB
tELTV
WAIT
tKHTX
Hi-Z
Hi-Z
tKHQV2
D0-D15
Hi-Z
READ Burst Identified
(W = High)
tKHQX2
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
AI11286d
1. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted
during delay (BCR8=0).
54/68
M69KB128AA
9 DC and AC parameters
Figure 25. Synchronous Burst Read Suspend and Resume AC Waveforms
tKHKL
K
tAVKH
tKHAX
Valid
Address
Addr.
Valid
Address
tAVLH
L
tLLKH
tEHQZ
tKHLH
tELKH
tEHEL
E
tGHQZ
tGLQX
tGHQZ
tGLQV
G
tWHKH
tKHWL
tGLQV
DON'T CARE
W
DON'T CARE
tBLKH
DON'T CARE
LB/UB
tKHTX
WAIT
D0-D15
Hi-Z
Hi-Z
Hi-Z
Valid
Output
tKHQV1
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
tKHQX2
AI11287d
1. The latency Type (BCR14) can be set to fixed or variable during Burst Read Suspend operations.The Latency is set to 3
clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. During Burst Read Suspend operations, the Clock signal must be stable (High or Low).
3. G can be held Low, VIL, during Burst Suspend operations. If so, data output remain valid.
55/68
M69KB128AA
9 DC and AC parameters
Figure 26. Synchronous Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap)
tKLKH, tKHKL
K
tKHKH
tF
Addr.
DON'T CARE
High
L
LB/UB
Low
E
Low
G
Low
Note 2
W
DON'T CARE
tKHTV
tEHTZ
tEHTZ
High-Z
WAIT
DQ0-DQ15
VALID
OUTPUT
VALID
OUTPUT
End of Row
AI11574
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to
1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
56/68
M69KB128AA
9 DC and AC parameters
VALID
INPUT
VALID
INPUT
D0-D15
2nd Write
Cycle
Hi-Z
LB/UB
2nd Read
Cycle
G
2nd Read
Cycle
WAIT
Hi-Z
W
D0-D15
2nd Read Cycle
tGLQV
tKHQV2
VALID
OUTPUT
LB/UB
2nd Write
Cycle
G
2nd Write
Cycle
Hi-Z
High
tDVKH
VALID
INPUT
VALID
INPUT
tKHDX
tKHQV2
VALID
OUTPUT
tKHQX2
tKHQX2
tGHQZ
Note 4
Hi-Z
tKHTV
tKHWL
tKHWL
E
L
tLLKH
Addr.
tAVKH
K
tWHKH
VALID
ADDRESS
tELKH
tKHLH
tKHAX
tKHKH
tAVKH
tLLKH
tWHKH
tLLTV
VALID
ADDRESS
tELEH(3)
tKHLH
tKHAX
tGLQV
VALID
OUTPUT
Burst Read Interrupted by New Burst Read or Write (2)
VALID
OUTPUT
tKHEH
tGHQZ
VALID
OUTPUT
Hi-Z
AI11292b
Figure 27. Burst Read Interrupted by Burst Read or Write AC Waveforms
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101).
WAIT is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable latency
and no refresh collision.
2. The Burst Read is interrupted during the first allowable clock cycle, i.e. after the first data is received by the microcontroller.
3. E can remain Low, VIL, between burst operations, but it must not remain Low for longer than tELEH.
4. If the latency is variable, WAIT is asserted tKHTV after L is clocked Low. If the latency is fixed, WAIT is asserted tLLTV after L
falling edge.
57/68
M69KB128AA
9 DC and AC parameters
Figure 28. CR Controlled Configuration Register Read Followed by Read, Synchronous Mode
K
Addr.
(except A18-A19)
ADDRESS
tAVKH
tKHAX
ADDRESS
A18-A19
tRHKH
tKHRL
tLLKH
tKHLH
tELKH
tKHQV1
CR
tLLKH
L
tEHEL
E
tEHQZ
G
tGLQV
High
tGLQV
tGHQZ
W
tBLKH
High-Z tBLKH
UB, LB
tELTV
WAIT
tGLQX
DQ0-DQ15
tKHQV2
CR VALID
DATA VALID
tKHQX2
ai10132f
1. A18-A19 must be set to ‘00b’ to select RCR, ‘01b’ to select BCR and ‘1Xb’ to select the DIDR.
58/68
M69KB128AA
Table 22.
9 DC and AC parameters
Synchronous Burst Write AC Characteristics
M69KB128AA
Symbol
Alt.
Parameter(1)
104MHz
Min
tAVWL
tLLWL(2)
Max
80MHz
Min
Max
66MHz
Min
Unit
Max
tAS
Address Set-up to Beginning of Write
Operation
0
0
0
ns
tSP
Set-up Time to Active Clock Edge
3
3
3
ns
5
6
8
ns
tAVKH
tDVKH
tWLKH
tLLKH
tBLKH
tWHKH
tWHWL
tEHEL(3)
Chip Enable High between Subsequent
tCBPH Operations in Full-Synchronous or
NOR-Flash mode.
tELEH(3)
tCEM
Maximum Chip Enable Low Pulse
tCEW
Chip Enable Low to WAIT Valid
1
tCSP
Chip Enable Low to Clock High
3
4
5
ns
tHD
Hold Time From Active Clock Edge
2
2
2
ns
tKADV
Last Clock Rising Edge to Latch Enable
Low (Fixed Latency)
4
6
6
ns
tHZ
Chip Enable High to Input Hi-Z or WAIT
Hi-Z
8
8
8
ns
tKHTL
Clock High to WAIT Valid or Low
7
9
11
ns
tAVH
Latch Enable High to Address Transition
(Fixed Latency)
tELTV
tLLTV
tELKH
4
7.5
4
1
7.5
1
4
µs
7.5
ns
tKHAX
tKHRL
tKHLH
tKHDX
tKHEH
tKHBH
tKHWH
tKHLL
tEHDZ
tEHTZ(4)
tKHTV
tKHTX
tLHAX
2
2
2
ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. tAVWL and tLLWL, are required if tELKH> 20ns.
3. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge
of K; or if E is High for longer than 15ns.
4. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
59/68
M69KB128AA
9 DC and AC parameters
Figure 29. 4-Word Synchronous Burst Write AC Waveforms (Variable Latency Mode)
tKHKH
K
VALID
ADDRESS
Addr.
tAVKH
tKHAX
tAVWL
tLLWL
tKHLL
L
tKHLH
tLLKH
tKHBH
tBLKH
LB/UB
tELEH
tELKH
tEHEL
E
tKHEH
High
G
tWLKH
tKHWH
W
tKHTX
tEHTZ
tELTV
WAIT
Hi-Z
Note 2
Hi-Z
tKHDX
tDVKH
D0-D15
Hi-Z
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
WRITE Burst Identified
(W = Low)
ai11288
1. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and asserted
during delay (BCR8=0).
2. The WAIT signal must remain asserted for LC clock cycles (LC Latency code), whatever the Latency mode (fixed or
variable).
3. tAVLL and tLLWL, are required if tELKH> 20ns.
60/68
M69KB128AA
9 DC and AC parameters
Figure 30. Synchronous Burst Write Showing End-of-Row Condition AC Waveforms (No Wrap)
tKLKH
K
tKHKH
Addr.
tF
DON'T CARE
L
LB/UB
Note 2
E
High
G
DON'T CARE
W
tKHTV
tEHTZ
tEHTZ
High-Z
WAIT
tDVKH
DQ0-DQ15
tKHDX
VALID
INPUT D[n]
VALID
INPUT D[n+1]
End of Row
(A6-A0 = 7Fh)
ai11575
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to
1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
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9 DC and AC parameters
DO3
DIN3
tDVKH
DIN0
tKHTX
tKHWH
DQ0DQ15
WAIT
UB, LB
W
G
E
tWLKH
tELKH
L
tLLKH
tAVKH
Addr.
K
tKHAX
tKHLH
tKHKH
DIN1 DIN2
tKHDX
(2)
tELKH
tWHKH
tEHEL
tKHKL
tKHEH
tKHLL
tAVKH
tKLKH
tKHAX
tKHLH
tKHWL
tGLQX
DO0
tKHTX
DO1
DO2
tKHEH
tKHQX2
ai11291b
tGHQZ
Figure 31. Synchronous Burst Write Followed by Read AC Waveforms (4 Words)
1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT
signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than tELEH.
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9 DC and AC parameters
VALID
OUTPUT
VALID
OUTPUT
tKHQX
VALID
OUTPUT
VALID
OUTPUT
tKHBH
VALID
INPUT
VALID
INPUT
tKHQV2
tGLQV
D0-D15
Hi-Z
2nd Read
Cycle
LB/UB
2nd Read
Cycle
VALID
INPUT
G
2nd Read
Cycle
tKHDX
tGLKH
tKHTV
tKHWL
Hi-Z
D0-D15
2nd WriteCycle
LB/UB
2nd Write
Cycle
G
2nd Write
Cycle
WAIT
Hi-Z
W
High
tKHWH
E
L
tLLKH
Addr.
tAVKH
K
tWHKH
VALID
ADDRESS
tELKH
tKHLH
tKHAX
tKHKH
tDVKH
tAVKH
tLLKH
tWHKH
VALID
ADDRESS
tELEH(3)
tKHLH
tKHAX
tDVKH
VALID
INPUT
tKHDX
Burst Write Interrupted by New Burst Write or Read (2)
tKHEH
tGHQZ
VALID
INPUT
Hi-Z
AI11293b
Figure 32. Burst Write Interrupted by Burst Write or Read AC Waveforms
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101).
WAIT is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable latency
and no refresh collision.
2. The Burst Write is interrupted during the first allowable clock cycle, i.e. after the first Word written to the memory.
3. E, can remain Low, VIL, between burst operations, but it must not remain Low for longer than tELEH.
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9 DC and AC parameters
Figure 33. CR Controlled Configuration Register Program, Synchronous Mode
K
Addr.(3)
Opcode
tAVKH
tKHAX
00 (RCR)
01 (BCR)
A18-A19(4)
tRHKH
tKHRL
tLLKH
tKHLH
CR(5)
L
tELEH
E
G
tWLKH
tKHWH
W
UB, LB
DQ0-DQ15(2)
tELTV
WAIT
Hi-Z
AI10131d
1. Only the Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. Data Inputs/Outputs are not used.
3. The Opcode is the value to be written in the Configuration Register.
4. A19 gives the Configuration Register address.
5. CR initiates the Configuration Register Access.
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Table 23.
9 DC and AC parameters
Power-Up and Deep Power-Down AC Characteristics
M69KB128AA
Symbol
Alt.
Parameter
Unit
Min
Max
tPU
tPU
Initialization delay after Power-Up or Deep Power-Down Exit
150
µs
tEHEL(DP)
tDPD
Deep Power-Down Entry to Deep Power-Down Exit
10
µs
tELEH(DP)
tDPDX
Chip Enable Low to Deep Power-Down Exit
10
µs
Figure 34. Power-Up AC Waveforms
E
tPU
VCC, VCCQ
1.7V
Device Ready
for Normal Operation
Device Initialization
AI09465d
1. Power must be applied to VCC prior to or at the same time as VCCQ.
Figure 35. Deep Power-Down Entry and Exit AC Waveforms
E
tEHEL(DP)
Deep Power-Down
Entry (RCR4= 0)
Deep Power-Down
Mode
tELEH (DP)
tPU
Deep Power-Down Device Initialization
Device Ready
Exit
for Normal Operation
AI11306
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M69KB128AA
10 Part Numbering
10
Part Numbering
Table 24.
Ordering Information Scheme
Example:
M69KB128AA
70 A W 8
Device Type
M69 = PSRAM
Mode
K = Bare Die
Operating Voltage
B = VCC = 1.7 to 1.95V, Burst, Address/Data bus standard x16
Array Organization
128 = 128 Mbit (8Mb x16)
Option 1
A = 1 Chip Enable
Silicon Revision
A = Revision A
Speed Class
70 = 70ns
85 = 85ns
Maximum Clock Frequency
A = 66MHz max clock frequency in burst Read mode
C = 80MHz max clock frequency in burst Read mode
D = 104MHz max clock frequency in burst Read mode
Package
W = Unsawn Wafer
Operating Temperature
8 = –30 to 85 °C
The notation used for the device number is as shown in Table 24. Not all combinations are
necessarily available. For a list of available options (speed, package, etc.) or for further
information on any aspect of this device, please contact your nearest STMicroelectronics Sales
Office.
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M69KB128AA
11
11 Revision history
Revision history
Table 25.
Document Revision History
Date
Revision
Changes
29-Nov-2005
1
First Issue
20-Jan-2006
2
Section Wafer and die specifications removed.
Figure 7: Set Configuration Register (Software Method) and Figure 8:
Read Configuration Register (Software Method) updated.
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M69KB128AA
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