STMicroelectronics M95320-WMN3T 64/32/16/8 kbit serial spi bus eeprom with high speed clock Datasheet

M95640
M95320
64Kbit and 32Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■ Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
■
Figure 1. Packages
Single Supply Voltage:
– 4.5 to 5.5V for M95xxx
– 2.5 to 5.5V for M95xxx-W
– 1.8 to 5.5V for M95xxx-R
■
10MHz, 5MHz or 2MHz clock rate (depending
on ordering options)
■
5ms or 10ms Write Time (depending on
ordering options)
■
Status Register
■
Hardware Protection of the Status Register
■
BYTE and PAGE WRITE (up to 32 Bytes)
■
Self-Timed Programming Cycle
■
Adjustable Size Read-Only EEPROM Area
■
Enhanced ESD Protection
■
More than 100,000 or 1 million Erase/Write
Cycles (depending on ordering options)
■
More than 40 Year Data Retention
8
1
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP14 (DL)
169 mil width
November 2003
1/39
M95640, M95320
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. DIP and SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. TSSOP14 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Stand-by Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/39
M95640, M95320
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write Enable (WREN) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Byte Write (WRITE) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating Conditions (M95xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Operating Conditions (M95xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Operating Conditions (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 16. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. DC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. DC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. DC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. DC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. AC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/39
M95640, M95320
Table 19. AC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. AC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. AC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. AC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 33
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 33
Figure 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . 34
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
34
Figure 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 35
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 35
Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . 36
Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter 37
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/39
M95640, M95320
SUMMARY DESCRIPTION
These electrically erasable programmable memory (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320).
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is taken Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 3. DIP and SO Connections
M95xxx
S
Q
W
VSS
8
7
6
5
1
2
3
4
VCC
HOLD
C
D
AI01790D
Figure 2. Logic Diagram
VCC
D
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
Figure 4. TSSOP14 Connections
Q
C
S
M95xxx
M95xxx
S
Q
NC
NC
NC
W
VSS
W
HOLD
VSS
AI01789C
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
HOLD
NC
NC
NC
C
D
AI02346C
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
Table 1. Signal Names
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply Voltage
VSS
Ground
5/39
M95640, M95320
SIGNAL DESCRIPTION
During all operations, V CC must be held stable and
within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held
High or Low (according to voltages of VIH, VOH, VIL
or VOL, as specified in Tables 13 to 17). These signals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives instructions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
6/39
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Standby mode. Driving Chip Select (S) Low enables the
device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write operations.
M95640, M95320
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register instructions) have been clocked into the device.
Figure 5 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 5. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
C Q D
C Q D
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
7/39
M95640, M95320
Figure 6. SPI Modes Supported
CPOL
CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
8/39
M95640, M95320
OPERATING FEATURES
Power-up
When the power supply is turned on, V CC rises
from VSS to VCC.
During this time, the Chip Select (S) must be allowed to follow the V CC voltage. It must not be allowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Powerup, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first operation.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value, all operations are disabled and the device will not respond
to any command.
A stable and valid VCC must be applied before applying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V CC.
Active Power and Stand-by Power Modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode. The device
consumes ICC, as specified in Tables 13 to 17.
When Chip Select (S) is High, the device is disabled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Stand-by
Power mode, and the device consumption drops
to ICC1.
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect
of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
7).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 7 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) being Low.
Figure 7. Hold Condition Activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
9/39
M95640, M95320
Status Register
Figure 8 shows the position of the Status Register
in the control logic of the device. The Status Register contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 2. Status Register Format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Data Protection and Protocol Control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
■
Write and Write Status Register instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
■
All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction
completion
– Write (WRITE) instruction completion
■
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
■
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sentence:
– The ‘last bit of the instruction’ can be the eighth
bit of the instruction code, or the eighth bit of a
data byte, depending on the instruction (except
for Read Status Register (RDSR) and Read
(READ) instructions).
– The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Table 3. Write-Protected Block Size
Status Register Bits
Array Addresses Protected
Protected Block
BP1
BP0
0
0
0
10/39
M95640
M95320
none
none
none
1
Upper quarter
1800h - 1FFFh
0C00h - 0FFFh
1
0
Upper half
1000h - 1FFFh
0800h - 0FFFh
1
1
Whole memory
0000h - 1FFFh
0000h - 0FFFh
M95640, M95320
MEMORY ORGANIZATION
The memory is organized as shown in Figure 8.
Figure 8. Block Diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Size of the
Read only
EEPROM
area
Y Decoder
Status
Register
1 Page
X Decoder
AI01272C
11/39
M95640, M95320
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 4.
If an invalid instruction is sent (one not contained
in Table 4), the device automatically deselects itself.
Table 4. Instruction Set
Instruc
tion
Description
Instruction
Format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Figure 9. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
12/39
As shown in Figure 9, to send this instruction to the
device, Chip Select (S) is driven Low, and the bits
of the instruction byte are shifted in, on Serial Data
Input (D). The device then enters a wait state. It
waits for a the device to be deselected, by Chip
Select (S) being driven High.
M95640, M95320
Figure 10. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 10, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
– Power-up
– WRDI instruction execution
– WRSR instruction completion
– WRITE instruction completion.
13/39
M95640, M95320
Figure 11. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
MSB
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register continuously, as shown in Figure 11.
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register instruction is accepted.
14/39
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Register (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protected mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for execution.
M95640, M95320
Figure 12. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the selftimed Write Status Register cycle (whose duration
is tW) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2.
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction.
15/39
M95640, M95320
Table 5. Protection Modes
W
Signal
SRWD
Bit
1
0
0
0
1
0
Mode
Memory Content
Protected Area1
Unprotected Area1
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Write Protected
Ready to accept Write
instructions
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1
and BP0 bits cannot be
changed
Write Protected
Ready to accept Write
instructions
1
1
Write Protection of the
Status Register
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.
The protection features of the device are summarized in Table 3.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
– If Write Protect (W) is driven High, it is possible
to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
– If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
(Attempts to write to the Status Register are rejected, and are not accepted for execution). As
a consequence, all the data bytes in the memory area that are software protected (SPM) by the
16/39
Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
– by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
– or by driving Write Protect (W) Low after setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
Table 6. Address Range Bits
Device
M95640
M95320
Address Bits
A12-A0
A11-A0
Note: 1. b15 to b13 are Don’t Care on the M95640.
b15 to b12 are Don’t Care on the M95320.
M95640, M95320
Figure 13. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
Q
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Read from Memory Array (READ)
As shown in Figure 13, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The address is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incremented, and the byte of data at the new address is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
17/39
M95640, M95320
Figure 14. Byte Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Write to Memory Array (WRITE)
As shown in Figure 14, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data.
In the case of Figure 14, this occurs after the
eighth bit of the data byte has been latched in, indicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period tWC (as specified in Tables 18 to 22), at the end of which the Write in
Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 15, the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
18/39
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the internal address counter rolls over to the beginning of
the page, and the previous data there are overwritten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
– if the Write Enable Latch (WEL) bit has not been
set to 1 (by executing a Write Enable instruction
just before)
– if a Write cycle is already in progress
– if the device has not been deselected, by Chip
Select (S) being driven High, at a byte boundary
(after the eighth bit, b0, of the last data byte that
has been latched in)
– if the addressed page is in the region protected
by the Block Protect (BP1 and BP0) bits.
M95640, M95320
Figure 15. Page Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
19/39
M95640, M95320
POWER-UP AND DELIVERY STATE
Power-up State
After Power-up, the device is in the following state:
– Stand-by mode
– deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started).
– not in the Hold Condition
– the Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
20/39
the SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down
(they are non-volatile bits).
INITIAL DELIVERY STATE
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
M95640, M95320
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
TLEAD
Parameter
Storage Temperature
Lead Temperature during Soldering
1
Min.
Max.
Unit
–65
150
°C
260 2
260 3
260 3
°C
PDIP
SO
TSSOP
VO
Output Voltage
–0.45
VCC+0.6
V
VI
Input Voltage
–0.45
6.5
V
VCC
Supply Voltage
–0.3
6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 4
–4000
4000
V
Note: 1.
2.
3.
4.
ECOPACK ®
Compliant with the
7191395 specifiication for lead-free soldering processes
No longer than 10 seconds
Not exceeding 250°C for more than 30 seconds, and peaking at 260°C
JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
21/39
M95640, M95320
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 8. Operating Conditions (M95xxx)
Symbol
VCC
Parameter
Min.
Max.
Unit
Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (range 6)
–40
85
°C
Ambient Operating Temperature (range 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
2.5
5.5
V
Ambient Operating Temperature (range 6)
–40
85
°C
Ambient Operating Temperature (range 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
1.8
5.5
V
Ambient Operating Temperature
–40
85
°C
TA
Table 9. Operating Conditions (M95xxx-W)
Symbol
VCC
Parameter
TA
Table 10. Operating Conditions (M95xxx-R)
Parameter1
Symbol
VCC
TA
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 11. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Load Capacitance
100
Input Rise and Fall Times
Unit
pF
50
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input and Output Timing Reference Voltages
0.3VCC to 0.7VCC
V
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 16. AC Measurement I/O Waveform
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
AI00825B
22/39
Max.
M95640, M95320
Table 12. Capacitance
Symbol
COUT
CIN
Parameter
Test Condition
Max.
Unit
VOUT = 0V
8
pF
Input Capacitance (D)
VIN = 0V
8
pF
Input Capacitance (other pins)
VIN = 0V
6
pF
Output Capacitance (Q)
Min.
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 5 MHz.
Table 13. DC Characteristics (M95xxx, temperature range 6)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
ICC1
Supply Current
Supply Current
(Stand-by)
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5MHz,
VCC = 5 V, Q = open, Current Product 2
4
mA
C = 0.1VCC/0.9VCC at 10MHz,
VCC = 5 V, Q = open, New Product 3
5
mA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Current Product 2
10
µA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, New Product 3
2
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL1
Output Low Voltage
IOL = 2 mA, VCC = 5 V
0.4
V
VOH1
Output High Voltage
IOH = –2 mA, VCC = 5 V
0.8 VCC
V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Current product: identified by Process Identification letter S.
3. New product: identified by Process Identification letter V.
23/39
M95640, M95320
Table 14. DC Characteristics (M95xxx, temperature range 3)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
ICC1
Supply Current
Supply Current
(Stand-by)
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 5 V, Q = open, Current Product 2
2
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open, New Product 3
4
mA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Current Product 2
20
µA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, New Product 3
5
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL1
Output Low Voltage
IOL = 2 mA, VCC = 5 V
0.4
V
VOH1
Output High Voltage
IOH = –2 mA, VCC = 5 V
0.8 VCC
V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Current product: identified by Process Identification letter S.
3. New product: identified by Process Identification letter B.
Table 15. DC Characteristics (M95xxx-W, temperature range 6)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
ICC1
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 2.5 V, Q = open, Current Product 1
2
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open, New Product 2
3
mA
S = VCC , VCC = 2.5 V,
VIN = VSS or VCC, Current Product 1
2
µA
S = VCC , VCC = 2.5 V
VIN = VSS or VCC, New Product 2
1
µA
Supply Current
Supply Current
(Stand-by)
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL
Output Low Voltage
IOL = 1.5 mA, VCC = 2.5 V
0.4
V
VOH
Output High Voltage
IOH = –0.4 mA, VCC = 2.5 V
Note: 1. Current product: identified by Process Identification letter S.
2. New product: identified by Process Identification letter V.
24/39
0.8 VCC
V
M95640, M95320
Table 16. DC Characteristics (M95xxx-W, temperature range 3)
Symbol
Parameter
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
Test Condition
Min.
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
3
mA
ICC1
Supply Current
(Stand-by)
S = VCC , VCC = 2.5 V, VIN = VSS or VCC
2
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL
Output Low Voltage
IOL = 1.5 mA, VCC = 2.5 V
0.4
V
VOH
Output High Voltage
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
V
Note: New product: identified by Process Identification letter B.
Table 17. DC Characteristics (M95xxx-R)
Symbol
Parameter
Test Condition1
Min.2
Max.2
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 1.8 V, Q = open
1
mA
ICC1
Supply Current
(Stand-by)
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
1
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL
Output Low Voltage
IOL = 0.15 mA, VCC = 1.8 V
0.3
V
VOH
Output High Voltage
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
V
Note: 1. This product is under qualification. For more infomation, please contact your nearest ST sales office.
2. Preliminary data.
25/39
M95640, M95320
Table 18. AC Characteristics (M95xxx, temperature range 6)
Test conditions specified in Table 11 and Table 8
Max.3
Min.4
Max.4
Unit
D.C.
5
D.C.
10
MHz
Alt.
fC
fSCK
Clock Frequency
tSLCH
tCSS1
S Active Setup Time
90
15
ns
tSHCH
tCSS2
S Not Active Setup Time
90
15
ns
tSHSL
tCS
S Deselect Time
100
40
ns
tCHSH
tCSH
S Active Hold Time
90
25
ns
S Not Active Hold Time
90
15
ns
tCHSL
Parameter
Min.3
Symbol
tCH 1
tCLH
Clock High Time
90
40
ns
tCL 1
tCLL
Clock Low Time
90
40
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
20
15
ns
tCHDX
tDH
Data In Hold Time
30
15
ns
tHHCH
Clock Low Hold Time after HOLD not Active
70
15
ns
tHLCH
Clock Low Hold Time after HOLD Active
40
20
ns
tCHHL
Clock High Set-up Time before HOLD Active
60
30
ns
tCHHH
Clock High Set-up Time before HOLD not
Active
60
30
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
50
20
ns
tQHQL 2
tFO
Output Fall Time
50
20
ns
tHHQX 2
tLZ
HOLD High to Output Low-Z
50
25
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
100
25
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
26/39
Output Disable Time
Clock Low to Output Valid
tCH + tCL ≥ 1 / fC.
Value guaranteed by characterization, not 100% tested in production.
Current product: identified by Process Identification letter S.
New product: identified by Process Identification letter V.
100
25
ns
60
25
ns
0
0
ns
M95640, M95320
Table 19. AC Characteristics (M95xxx, temperature range 3)
Test conditions specified in Table 11 and Table 8
Min.3
Max.3
Min.4
Max.4
Unit
Clock Frequency
D.C.
2
D.C.
5
MHz
tCSS1
S Active Setup Time
200
90
ns
tSHCH
tCSS2
S Not Active Setup Time
200
90
ns
tSHSL
tCS
S Deselect Time
200
100
ns
tCHSH
tCSH
S Active Hold Time
200
90
ns
S Not Active Hold Time
200
90
ns
Symbol
Alt.
fC
fSCK
tSLCH
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
90
ns
tCL 1
tCLL
Clock Low Time
200
90
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
40
20
ns
tCHDX
tDH
Data In Hold Time
50
30
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
40
ns
tCHHL
Clock High Set-up Time before HOLD Active
120
70
ns
tCHHH
Clock High Set-up Time before HOLD not
Active
120
70
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
50
ns
tQHQL 2
tFO
Output Fall Time
100
50
ns
tHHQX 2
tLZ
HOLD High to Output Low-Z
100
50
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
100
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
Output Disable Time
250
100
ns
Clock Low to Output Valid
150
60
ns
0
0
ns
tCH + tCL ≥ 1 / fC.
Value guaranteed by characterization, not 100% tested in production.
Current product: identified by Process Identification letter S.
New product: identified by Process Identification letter B.
27/39
M95640, M95320
Table 20. AC Characteristics (M95xxx-W, temperature range 6)
Test conditions specified in Table 11 and Table 9
Min.3
Max.3
Min.4
Max.4
Unit
Clock Frequency
D.C.
2
D.C.
5
MHz
tCSS1
S Active Setup Time
200
90
ns
tSHCH
tCSS2
S Not Active Setup Time
200
90
ns
tSHSL
tCS
S Deselect Time
200
100
ns
tCHSH
tCSH
S Active Hold Time
200
90
ns
S Not Active Hold Time
200
90
ns
Symbol
Alt.
fC
fSCK
tSLCH
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
90
ns
tCL 1
tCLL
Clock Low Time
200
90
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
40
20
ns
tCHDX
tDH
Data In Hold Time
50
30
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
40
ns
tCHHL
Clock High Set-up Time before HOLD Active
120
60
ns
tCHHH
Clock High Set-up Time before HOLD not
Active
120
60
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
50
ns
tQHQL 2
tFO
Output Fall Time
100
50
ns
tHHQX 2
tLZ
HOLD High to Output Low-Z
100
50
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
100
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
28/39
Output Disable Time
250
100
ns
Clock Low to Output Valid
150
60
ns
tCH + tCL ≥ 1 / fC.
Value guaranteed by characterization, not 100% tested in production.
Current product: identified by Process Identification letter S.
New product: identified by Process Identification letter V.
0
0
ns
M95640, M95320
Table 21. AC Characteristics (M95xxx-W, temperature range 3)
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
fC
fSCK
Clock Frequency
tSLCH
tCSS1
S Active Setup Time
90
ns
tSHCH
tCSS2
S Not Active Setup Time
90
ns
tSHSL
tCS
S Deselect Time
100
ns
tCHSH
tCSH
S Active Hold Time
90
ns
S Not Active Hold Time
90
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
tCH 1
tCLH
Clock High Time
90
ns
tCL 1
tCLL
Clock Low Time
90
ns
tCLCH 2
tRC
Clock Rise Time
1
µs
tCHCL 2
tFC
Clock Fall Time
1
µs
tDVCH
tDSU
Data In Setup Time
20
ns
tCHDX
tDH
Data In Hold Time
30
ns
tHHCH
Clock Low Hold Time after HOLD not Active
70
ns
tHLCH
Clock Low Hold Time after HOLD Active
40
ns
tCHHL
Clock High Set-up Time before HOLD Active
60
ns
tCHHH
Clock High Set-up Time before HOLD not Active
60
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
50
ns
tQHQL 2
tFO
Output Fall Time
50
ns
tHHQX 2
tLZ
HOLD High to Output Low-Z
50
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
100
ns
tW
tWC
Write Time
5
ms
Output Disable Time
100
ns
Clock Low to Output Valid
60
ns
0
ns
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. New product: identified by Process Identification letter B.
29/39
M95640, M95320
Table 22. AC Characteristics (M95xxx-R)
Test conditions specified in Table 11 and Table 10
Min.3
Max.3
Unit
Clock Frequency
D.C.
2
MHz
tCSS1
S Active Setup Time
200
ns
tSHCH
tCSS2
S Not Active Setup Time
200
ns
tSHSL
tCS
S Deselect Time
200
ns
tCHSH
tCSH
S Active Hold Time
200
ns
S Not Active Hold Time
200
ns
Symbol
Alt.
fC
fSCK
tSLCH
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
ns
tCL 1
tCLL
Clock Low Time
200
ns
tCLCH 2
tRC
Clock Rise Time
1
µs
tCHCL 2
tFC
Clock Fall Time
1
µs
tDVCH
tDSU
Data In Setup Time
40
ns
tCHDX
tDH
Data In Hold Time
50
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
ns
tCHHL
Clock High Set-up Time before HOLD Active
120
ns
tCHHH
Clock High Set-up Time before HOLD not Active
120
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
ns
tQHQL 2
tFO
Output Fall Time
100
ns
tHHQX 2
tLZ
HOLD High to Output Low-Z
100
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
ns
tW
tWC
Write Time
10
ms
Output Disable Time
250
ns
Clock Low to Output Valid
150
ns
0
ns
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data: this product is under qualification. For more infomation, please contact your nearest ST sales office.
30/39
M95640, M95320
Figure 17. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
D
Q
tCLCH
LSB IN
MSB IN
High Impedance
AI01447C
Figure 18. Hold Timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
Q
D
HOLD
AI02032
31/39
M95640, M95320
Figure 19. Output Timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
AI01449D
32/39
M95640, M95320
PACKAGE MECHANICAL
Figure 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
Notes: 1. Drawing is not to scale.
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
A
Max.
Typ.
Min.
5.33
A1
Max.
0.210
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
–
–
0.100
–
–
eA
7.62
–
–
0.300
–
–
eB
L
10.92
3.30
2.92
3.81
0.430
0.130
0.115
0.150
33/39
M95640, M95320
Figure 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
Max.
A
1.35
A1
Min.
Max.
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
CP
34/39
1.27
Typ.
0.050
8
0.10
0.004
M95640, M95320
Figure 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
1
E
4
α
L
A1
A
A2
L1
CP
b
e
TSSOP8AM
Notes: 1. Drawing is not to scale.
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
Max.
Min.
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
0.0394
0°
8°
35/39
M95640, M95320
Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline
D
14
8
c
E1
1
E
7
α
A1
A
L
A2
L1
CP
b
e
TSSOP14-M
Notes: 1. Drawing is not to scale.
Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
Min.
1.200
A1
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
5.000
4.900
5.100
0.1969
0.1929
0.2008
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.500
0.750
0.0236
0.0197
0.0295
L1
1.000
0°
8°
α
36/39
Max.
0.0394
0°
8°
M95640, M95320
PART NUMBERING
Table 27. Ordering Information Scheme
Example:
M95320
–
W MN
6
T
P
Device Type
M95 = SPI serial access EEPROM
Device Function1
640 = 64 Kbit (8192 x 8)
320 = 32 Kbit (4096 x 8)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
DL = TSSOP14 (169 mil width)
Temperature Range
6 = –40 to 85 °C
3 = –40 to 125 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Pb-free plating
G = Green pack
Note: 1. Devices bearing the process identification letter “B” or “V” in the package marking (on the top side of the package, on the right side),
guarantee more than 1 million Erase/Write cycle endurance (see Table 28, below). For more information about these devices, and
their device identification, please contact your nearest ST sales office, and ask for the Product Change Notice.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter
Markings on Current Products1
Markings on New Products1
95640 6 (or 95640W6)
xxxxS
95640 6 (or 95640W6)
xxxxV
95640 3
xxxxS
95640 3 (or 95640W3)
xxxxB
Note: 1. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0053 (PCEE0053) and MPG/
EE/0054 (PCEE0054).
37/39
M95640, M95320
REVISION HISTORY
Table 29. Document Revision History
Date
Rev.
Description of Revision
13-Jul-2000
1.2
Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp 1,11,15. New clause
on p7. Addition of TSSOP8 package on pp 1, 2, Ordering Info, Mechanical Data
16-Mar-2001
1.3
Test condition added ILI and ILO, and specification of tDLDH and tDHDL removed.
tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.
“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated.
19-Jul-2001
1.4
M95160 and M95080 devices removed to their own data sheet
06-Dec-2001
1.5
Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
18-Dec-2001
2.0
Document reformatted using the new template. No parameters changed.
08-Feb-2002
2.1
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40 to 85°C, range.
Endurance set to 100K write/erase cycles
18-Dec-2002
2.2
10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write cycles distinguished
on front page, and in the DC and AC Characteristics tables
26-Mar-2003
2.3
Process indentification letter corrected in footnote to AC Characteristics table for temp. range 3
26-Jun-2003
2.4
-S voltage range upgraded by removing it and inserting -R voltage range in its place
15-Oct-2003
3.0
Table of contents, and Pb-free options added. VIL(min) improved to -0.45V.
21-Nov-2003
3.1
VI(min) and VO(min) corrected (improved) to -0.45V.
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M95640, M95320
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