Lattice MACH111SP-7JC High-performance ee cmos programmable logic Datasheet

MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
High-performance electrically-erasable CMOS PLD families
32 to 128 macrocells
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
SpeedLocking™ – guaranteed fixed timing up to 16 product terms
Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD
Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
Safe for mixed supply voltage system designs
Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
Programmable power-down mode results in power savings of up to 75%
Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO ®) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication# 14051
Amendment/0
Rev: K
Issue Date: November 1998
Table 1. MACH 1 and 2 Family Device Features 1
Feature
MACH111 (SP)
MACH131 (SP)
MACH211 (SP)
MACH221 (SP)
MACH231 (SP)
32
64
64
96
128
Macrocells
Maximum user I/O pins
32
64
32
48
64
tP D (ns)
5.0
5.5
7.5 (6.0)
7.5
6.0 (10)
tS (ns)
3.5
3.0
5.5 (5)
5.5
5 (6.5)
tCO (ns)
3.5
4
4.5 (4)
5
4 (6.5)
fCNT (MHz)
182
182
133 (166)
133
166 (100)
Note:
1. Values in parentheses ( ) are for the SP version.
GENERAL DESCRIPTION
The MACH® 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex
Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,
telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns
tPD and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for
users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
Table 2. MACH 1 and 2 Family Speed Grades1
-7
-10
-12
-14
-15
-18
MACH111
Device
C (Note 2)
-5
-6
C, I
C, I
C, I
I
C
I
MACH111SP
C (Note 2)
C, I
C, I
C, I
I
C
I
MACH131
C (Note 3)
C, I
C, I
C, I
I
C
I
MACH131SP
C (Note 3)
C, I
C, I
C, I
I
C
I
C
C, I
C, I
I
C
I
C
C, I
C, I
I
C
I
C
C, I
C, I
I
C
I
C
C, I
C, I
I
C
I
C
C
C, I
I
C
I
C
C, I
I
C
I
MACH211
MACH211SP
C
MACH221
MACH221SP
MACH231
MACH231SP
C
Notes:
1. C = Commercial, I = Industrial
2. -5 speed grade for MACH111 (SP) = 5.0 ns tPD
3. -5 speed grade for MACH131(SP) = 5.5 ns tPD
The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that
includes JTAG-compatible in-system programming (ISP). These devices offer five different densityI/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic
Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is
PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed
timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power
savings.
2
MACH 1 & 2 Families
Table 3. MACH 1 and 2 Family Package and I/O Options
Device
44-pin PLCC
44-pin TQFP
MACH111
X
X
MACH111SP
X
X
68-pin PLCC
84-pin PLCC
MACH131
100-pin PQFP
X
X
X
MACH131SP
MACH211
X
X
MACH211SP
X
X
MACH221
100-pin TQFP
X
MACH221SP
X
MACH231
X
MACH231SP
X
X
Note:
1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and
not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call
your local Lattice/Vantis sales office or visit our Web site at www.vantis.com for more information.
Lattice/Vantis offers software design support for MACH devices in both the MACHXL® and
DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis
implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD
devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL
compliant VHDL and SDF simulation netlists for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
MACH 1 & 2 Families
3
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL® blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
Clock/Input Pins
Output
Macrocells
I/O Cells
I/O Pins
Array and
Allocator
I/O Pins
Buried
Macrocells
PAL Block
Switch Matrix
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
PAL Block
(note 1)
I/O Pins
PAL Block
PAL Block
I/O Pins
14051K-002
Dedicated Input
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
PAL Blocks
Macrocells per Block
I/Os per Block
Product Terms per Block
MACH111(SP)
Device
2
16
16
70
MACH131(SP)
4
16
16
70
MACH211(SP)
4
16
8
68
MACH221(SP)
8
12
6
52
MACH231(SP)
8
16
8
68
Figure 1. Overall Architecture of MACH 1 & 2 Devices
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed fixed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
4
MACH 1 & 2 Families
Each PAL block consists of the following elements:
◆
Product-term array
◆
Logic Allocator
◆
Macrocells
◆
I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the flip-flops within a single PAL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efficient logic implementation.
Because the number of product terms available for a given function is not fixed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Table 4. PAL Block Inputs
Device
Number of Inputs to PAL Block
Device
Number of Inputs to PAL Block
MACH111
26
MACH211SP
26
MACH111SP
26
MACH221
26
MACH131
26
MACH221SP
26
MACH131SP
26
MACH231
32
MACH211
26
MACH231SP
32
Logic Allocator
The logic allocator (Figure 2) is a block within which different product terms are allocated to the
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it fits functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
MACH 1 & 2 Families
5
To
n-2
To
n-1
From
n-1
*
To Macrocell
n
n
n
Product Term
Cluster
*
To
n+1 From From
n+1 n+2
14051K-003
Logic
Allocator
*MACH 2 only
Figure 2. Product Term Clusters and the Logic Allocator
Table 5. Logic Allocation for MACH111(SP)
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M0
C0, C1
M8
C8, C9
M1
C0, C1, C2
M9
C8, C9, C10
M2
C1, C2, C3
M10
C9, C10, C11
M3
C2, C3, C4
M11
C10, C11, C12
M4
C3, C4, C5
M12
C11, C12, C13
M5
C4, C5, C6
M13
C12, C13, C14
M6
C5, C6, C7
M14
C13, C14, C15
M7
C6, C7
M15
C14, C15
Table 6. Logic Allocation for MACH131(SP)
6
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M0
C0, C1
M8
C7, C8, C9
M1
C0, C1, C2
M9
C8, C9, C10
M2
C1, C2, C3
M10
C9, C10, C11
M3
C2, C3, C4
M11
C10, C11, C12
M4
C3, C4, C5
M12
C11, C12, C13
M5
C4, C5, C6
M13
C12, C13, C14
M6
C5, C6, C7
M14
C13, C14, C15
M7
C6, C7, C8
M15
C14, C15
MACH 1 & 2 Families
Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)
Macrocell
Output
Macrocell
Buried
Available Clusters
Output
C0, C1, C2
C0, C1, C2, C3
M8
M1
C1, C2, C3, C4
C2, C3, C4, C5
M10
M3
C3, C4, C5, C6
C4, C5, C6, C7
M12
M5
C5, C6, C7, C8
C6, C7, C8, C9
M14
M7
M0
M2
M4
M6
Buried
Available Clusters
M9
C7, C8, C9, C10
C8, C9, C10, C11
M11
C9, C10, C11, C12
C10, C11, C12, C13
M13
C11, C12, C13, C14
C12, C13, C14, C15
M15
C13, C14, C15
C14, C15
Table 8. Logic Allocation for MACH221(SP)
Macrocell
Output
Macrocell
Buried
Available Clusters
Output
C0, C1, C2
C0, C1, C2, C3
M6
M1
C1, C2, C3, C4
C2, C3, C4, C5
M8
M3
C3, C4, C5, C6
C4, C5, C6, C7
M10
M5
M0
M2
M4
Buried
Available Clusters
M7
C5, C6, C7, C8
C6, C7, C8, C9
M9
C7, C8, C9, C10
C8, C9, C10, C11
M11
C9, C10, C11
C10, C11
Macrocell
There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The
buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively
doubles the number of macrocells available without increasing the pin count.
Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series,
a transparent-low latch configuration is provided. If the register is used, it can be configured as
a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 9.
Programmable polarity (for output macrocells) and the T-type flip-flop both give the software a
way to minimize the number of product terms needed. These choices can be made automatically
by the software when it fits the design into the device.
Table 9. Register/Latch Operation
Configuration
D-Register
T-Register
Latch
D/T
CLK/LE
Q+
X
0,1,↓
Q
0
↑
0
1
↑
1
X
0,1,↓
Q
0
↑
Q
1
↑
Q
X
1
Q
0
0
0
1
0
1
MACH 1 & 2 Families
7
The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,
and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell.
This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as
inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4.
The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried
macrocell is provided only as an internal feedback signal which feeds the switch matrix. This
allows the designer to generate additional logic without requiring additional pins. The buried
macrocell can also be used to register or latch inputs. The input register is a D-type flip-flop; the
input latch is a transparent-low D-type latch. Once configured as a registered or latched input, the
buried macrocell cannot generate logic from the product-term array. The basic buried macrocell
configurations are shown in Figure 6.
PAL-Block
Asynchronous
Preset
1
AP
D/T/L1 Q
Sum of Products
from Logic
Allocator
1
0
0
To I/O
Cell
CLK0
AR
CLKn
PAL-Block
Asynchronous
Reset
To
Switch
Matrix
14051K-004
Note:
1. Latch option available on MACH 2 devices only.
Figure 3. Output Macrocell
8
MACH 1 & 2 Families
From
Logic
Allocator
To
I/O
Cell
n
From
Logic
Allocator
To Switch
Matrix
To Switch
Matrix
b. Combinatorial, active low
a. Combinatorial, active high
From
Logic
Allocator
CLK0
n
D APQ
From
Logic
Allocator
CLK0
To
I/O
Cell
AR
CLKn
n
To Switch
Matrix
d. D-type register, active low
c. D-type register, active high
n
T AP Q
CLK0
To
I/O
Cell
AR
CLKn
From
Logic
Allocator
To
I/O
Cell
T AP Q
AR
CLKn
To Switch
Matrix
f. T-type register, active low
e. T-type register, active high
CLKn
n
CLK0
To Switch
Matrix
From
Logic
Allocator
CLK0
To
I/O
Cell
D APQ
AR
CLKn
To Switch
Matrix
From
Logic
Allocator
To
I/O
Cell
n
n
L APQ
G
AR
To Switch
Matrix
To
I/O
Cell
From
Logic
Allocator
n
CLK0
CLKn
To Switch
Matrix
L APQ
To
I/O
Cell
G AR
h. Latch, active low (MACH 2 only)
g. Latch, active high (MACH 2 only)
14051K-005
Figure 4. Output Macrocell Configurations
MACH 1 & 2 Families
9
PAL-Block
Asynchronous
Preset
From I/O Pin
1
1
0
Sum of Products
From Logic
IC Allocator
CLK0
CLKn
PAL-Block
Asynchronous
Reset
AP
D/T/L Q
0
AR
To
Switch
Matrix
14051K-030
Figure 5. Buried Macrocell (MACH 2 only)
From
Logic
Allocator
From Logic
Allocator
n
n
D
AP
Q
CLKÂ0
AR
CLÂKn
To Switch
Matrix
To Switch
Matrix
a. Combinatorial
From Logic
Allocator
n
b. D-type register
T
CLK0
CLKn
AP
From I/O
Cell
Q
D
AR
AP
Q
CLK0
AR
CLKn
To Switch
Matrix
To Switch
Matrix
c. T-type register
From
Logic
Allocator
CLK0
n
d. Input register
L
AP
From I/O
Cell
Q
L
G
CLKn
AR
CLK0
CLKn
G
AP
Q
AR
To Switch
Matrix
To Switch
Matrix
e. Latch
f. Input latch
Figure 6. Buried Macrocell Configurations (MACH 2 only)
10
MACH 1 & 2 Families
14051K-006
The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
Table 10. Macrocell Clocks
Device
Number of Clocks Available
MACH111
Device
Number of Clocks Available
MACH211SP
4
2
MACH111SP
2
MACH221
4
MACH131
4
MACH221SP
4
MACH131SP
4
MACH231
4
MACH211
4
MACH231SP
4
All flip-flops have asynchronous reset and preset. This is controlled by the common product terms
that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops
is illustrated in Table 11.
Table 11. Asynchronous Reset/Preset Operation
Configuration
Register
Latch
AR
AP
CLK/LE
Q+
0
0
X
See Table 9
0
1
X
1
1
0
X
0
1
1
X
0
0
0
X
See Table 9
0
1
0
Illegal
0
1
1
1
1
0
0
Illegal
1
0
1
0
1
1
0
Illegal
1
1
1
0
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
MACH 1 & 2 Families
11
Output Enable
Product Terms
(Common to bank of
I/O Cells)
0 1
1 1
VCC
1 0
0 0
From Output
Macrocell
To Switch
Matrix
To Buried
Macrocell
(MACH 2 only)
14051K-007
Figure 7. I/O Cell
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch
matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
MACH 1 & 2 SpeedLocking
• Patented Architecture
• Path Independent
• Logic/Routing Independent
• Guaranteed Fixed Timing
• Up to 16 Product Terms per Output
Non-MACH
• Variable
• Path Dependent
• Logic/Routing Dependent Delays
• Unpredictable
• 4-5 Product Terms before Delays
SpeedLocking
11
10
tPD (ns) 9
8
7
6
5
Shared Expander Delay
10.4 ns
Non-MACH
8.8 ns
Parallel Expander Delay
6.6 ns
5.8 ns
5 ns
5 PT
10 PT
7.4 ns
MACH 1 & 2
15 PT
Product Terms
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
12
MACH 1 & 2 Families
14051K-001
JTAG IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.
All MACHxxxSP devices provide in-system programming (ISP) capability through their JTAG ports.
This capability has been implemented in a manner that insures that the JTAG port remains
compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through
which ISP is achieved, customers benefit from a standard, well-defined interface.
MACHxxxSP devices can be programmed across the commercial temperature and voltage range.
These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based
Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes
the JEDEC file output produced by Vantis’ design implementation software, along with information
about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/
VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC.
Alternatively, Lattice/VantisPRO software can output files in formats understood by common
automated test equipment. This equipment can then be used to program MACHxxxSP devices
during the testing of a circuit board. For more information about in-system programming, refer to
the separate document entitled MACH ISP Manual.
BUS-FRIENDLY INPUTS AND I/Os
The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input.
This double inversion weakly holds the input at its last driven logic state. For the circuit diagram,
please refer to the Input/Output Equivalent Schematics (page 393) in the General Information
Section of the Vantis 1999 Data Book.
PCI COMPLIANT
The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local
Bus Specification published by the PCI Special Interest Group. The MACH 1 & 2 families’
predictable timing ensures compliance with the PCI AC specifications independent of the design.
POWER-DOWN MODE
The MACH 1 & 2 families feature a programmable low-power mode in which individual signal
paths can be programmed for low power. These low-power speed paths will be slower than the
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while
the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If
all of the signals in a PAL block are in low-power mode, then the total power is reduced even
further.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system
designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V,
while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-touse mixed-voltage design compatibility. For more information, refer to the Technical Note entitled
Mixed Supply Design with MACH 1 & 2 SP Devices.
POWER-UP RESET
All flip-flops power-up to a logic LOW for predictable system initialization. The actual values of
the outputs of the MACH devices will depend on the configuration of the macrocell. To guarantee
MACH 1 & 2 Families
13
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset
delay time has elapsed.
SECURITY BIT
A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. Programming and
verification are also defeated by the security bit. The bit can only be reset by erasing the entire
device.
14
MACH 1 & 2 Families
MACH111(SP) AND MACH131(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
43
47
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
M0
Output
Macro
Cell
M1
Output
Macro
Cell
M2
Output
Macro
Cell
M3
Output
Macro
Cell
M4
Output
Macro
Cell
M5
Output
Macro
Cell
0
C0
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
C1
C2
C3
C5
C6
Switch
Matrix
C7
C8
Logic Allocator
C4
C9
Output
Macro
Cell
M6
Output
Macro
Cell
M7
Output
Macro
Cell
M8
C10
C11
Output
Macro
Cell
M9
C12
C13
Output
Macro
Cell
M10
C14
C15
63
Output
Macro
Cell
M11
Output
Macro
Cell
M12
Output
Macro
Cell
M13
Output
Macro
Cell
M14
CLK
M15
Output
Macro
Cell
for MACH111SP
2
for MACH111, MACH131, MACH131SP
4
Output Enable
Output Enable
0
4
8
12
16
20
24
28
32
36
40
43
47
51
16
16
14051K-013
MACH 1 & 2 Families
15
MACH211(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
43
47
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output
Macro
Cell
M0
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
Buried
Macro
Cell
M1
Output
Macro
Cell
M2
Buried
Macro
Cell
M3
0
C0
I/O
Cell
Output
Macro
Cell
M4
C1
C2
Buried
Macro
Cell
M5
C3
C5
C6
Switch
Matrix
C7
C8
Logic Allocator
C4
Output
Macro
Cell
M6
Buried
Macro
Cell
M7
Output
Macro
Cell
M8
C9
C10
C11
Buried
Macro
Cell
M9
C12
C13
Output
Macro
Cell
M10
C14
C15
63
Buried
Macro
Cell
M11
Output
Macro
Cell
M12
Buried
Macro
Cell
M13
Output
Macro
Cell
M15
Buried
Macro
Cell
CLK
M14
0
4
8
12
16
20
24
28
32
36
40
43
47
for MACH211SP
2
for MACH211
4
51
16
8
16
14051K-015
MACH 1 & 2 Families
MACH221(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
43
47
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output
Macro
Cell
M0
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
Buried
Macro
Cell
M1
Output
Macro
Cell
M2
0
I/O
Cell
C0
C1
Buried
Macro
Cell
M3
C2
C3
M4
C5
C6
C7
C8
Logic Allocator
C4
Switch
Matrix
Output
Macro
Cell
Buried
Macro
Cell
M5
Output
Macro
Cell
M6
C9
C10
Buried
Macro
Cell
M7
C11
47
4
8
12
16
20
24
28
32
36
40
43
47
Output
Macro
Cell
M9
Buried
Macro
Cell
M10
Output
Macro
Cell
M11
Buried
Macro
Cell
51
CLK
0
M8
4
12
6
14051K-016
MACH 1 & 2 Families
17
MACH231(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
43
47
51
55
59
63
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output
Macro
Cell
M0
Output
Macro
Cell
M2
C0
C4
C5
C6
C7
C8
Output
Macro
Cell
M8
Output
Macro
Cell
M10
Output
Macro
Cell
M12
C15
63
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
Buried
Macro
Cell
M11
C13
C14
I/O
Buried
Macro
Cell
M9
C11
C12
I/O
Cell
Buried
Macro
Cell
M7
C9
C10
I/O
Output
Macro
Cell
M6
Logic Allocator
Switch
Matrix
I/O
Cell
Buried
Macro
Cell
M5
C3
I/O
Output
Macro
Cell
M4
C2
I/O
Cell
Buried
Macro
Cell
M3
C1
I/O
Buried
Macro
Cell
M1
0
I/O
Cell
Buried
Macro
Cell
M13
Output
Macro
Cell
M15
Buried
Macro
Cell
CLK
M14
4
0
4
8
12
16
20
24
28
32
36
40
43
47
51
55
59
63
16
8
14051K-017
18
MACH 1 & 2 Families
BLOCK DIAGRAM (MACH111, MACH111SP)
MACH111
Block A
CLK0 /I1
CLK1 /I2
CLK2/I4
CLK3 /I5
I/O0 – I/O15
CLK0 /I0
CLK1 /I1
MACH111SP
16
16
I/O Cells
16
16
4
4 MACH111
2 MACH111SP
Macrocells
OE
52 x 70
AND Logic Array
and
Logic Allocator
26
Switch Matrix
26
52 x 70
AND Logic Array
and
Logic Allocator
OE
4
Macrocells
16
16
2 MACH111 Only
I/O Cells
16
16
I/O16 – I/O31
Block B
MACH 1 & 2 Families
I0
I3
MACH111
14051K-008
19
BLOCK DIAGRAM (MACH131, MACH131SP)
Block A
Block B
I/O0 – I/O15
I/O16 – I/O31
16
16
I/O Cells
16
4
I2, I5
I/O Cells
4
16
16
4
Macrocells
16
4
Macrocells
OE
OE
52 x 70
AND Logic Array
and
Logic Allocator
52 x 70
AND Logic Array
and
Logic Allocator
26
2
26
Switch Matrix
26
26
52 x 70
AND Logic Array
and
Logic Allocator
52 x 70
AND Logic Array
and
Logic Allocator
OE
4
OE
4
Macrocells
16
16
I/O Cells
4
Macrocells
4
16
16
I/O Cells
16
20
4
16
I/O48 – I/O63
I/O32 – I/O47
Block D
Block C
MACH 1 & 2 Families
CLK0/I0, CLK1/I1
CLK2/I3, CLK3/I4
14051K-009
BLOCK DIAGRAM (MACH211, MACH211SP)
Block A
Block B
I/O0–I/O7
MACH211 only
I/O8–I/O15
8
I/O Cells
I/O Cells
8
Macrocells
MACH211
CLK0 /I0
CLK1 /I1
MACH211SP
8
8
8
CLK0 /I1
CLK1 /I2
CLK2/I4
CLK3 /I5
Macrocells
2 MACH211SP
4 MACH211
8
8
8
Macrocells
Macrocells
2
2
OE
52 x 68
AND Logic
Array
and
OE
52 x 68
AND Logic
Amrray
and
26
26
Switch Matrix
26
26
52 x 68
AND Logic Array
and
Logic Allocator
OE
2
Macrocells
8
8
Macrocells
8
I/O Cells
52 x 68
AND Logic Array
and
Logic Allocator
OE
2
Macrocells
8
8
Macrocells
8
2 MACH211 only
I/O Cells
8
8
I/O24–I/O31
I/O16–I/O23
Block D
Block C
I0
I3
MACH211
14051K-010
MACH 1 & 2 Families
21
22
MACH 1 & 2 Families
Macrocells
I/O42 – I/O47
I/O Cells
6
6
Macrocells
Block H
2
I/O36 – I/O41
I/O Cells
6
Macrocells
6
6
Macrocells
Block G
2
O
26
26
6
6
Macrocells
O
6
2
O
52 x 52
AND Logic Array
and Logic Allocator
Macrocells
6
6
52 x 52
AND Logic Array
and Logic Allocator
26
26
6
6
I/O Cells
I/O6 – I/O11
Block B
52 x 52
AND Logic Array
and Logic Allocator
Macrocells
6
2
6
6
O
52 x 52
AND Logic Array
and Logic Allocator
Macrocells
6
I/O Cells
I/O0 – I/O5
Block A
I/O30 – I/O35
I/O Cells
6
Block F
6
6
Macrocells
6
I/O24 – I/O29
I/O Cells
6
Macrocells
2
6
6
6
Block E
Macrocells
O
2
O
26
26
52 x 52
AND Logic Array
and Logic Allocator
26
26
2
6
Macrocells
6
6
O
52 x 52
AND Logic Array
and Logic Allocator
Macrocells
6
I/O Cells
I/O18 – I/O23
Block D
52 x 52
AND Logic Array
and Logic Allocator
Macrocells
Switch Matrix
2
6
Macrocells
6
6
O
52 x 52
AND Logic Array
and Logic Allocator
Macrocells
6
I/O Cells
I/O12 – I/O17
Block C
CLK0/I0, CLK1/I1
CLK2/I4, CLK3/I5
4
4
4
4
I2–I3,
I6–I7
BLOCK DIAGRAM (MACH221, MACH221SP)
14051K-011
MACH 1 & 2 Families
OE
32
32
8
8
Macrocells
OE
OE
8
8
Macrocells
OE
I/O48 – I/O55 (Block G)
I/O Cells
8
Macrocells
2
8
8
Macrocells
64 x 68
AND Logic Array
and Logic Allocator
32
2
I/O56 – /O63 (Block
I/O Cells
2
8
8
64 x 68
AND Logic Array
and Logic Allocator
Macrocells
8
I/O Cells
I/O8 – I/O15 (Block B)
32
8
8
Macrocells
64 x 68
AND Logic Array
and Logic Allocator
Macrocells
8
2
8
8
64 x 68
AND Logic Array
and Logic Allocator
Macrocells
8
I/O Cells
I/O0 – I/O7 (Block A)
OE
32
32
Macrocells
I/O40 – I/O47 (Block F)
I/O Cells
2
8
8
Macrocells
OE
64 x 68
AND Logic Array
and Logic Allocator
Switch Matrix
8
2
8
8
Macrocells
8
8
64 x 68
AND Logic Array
and Logic Allocator
Macrocells
8
I/O Cells
I/O16 – I/O23 (Block C)
OE
32
32
8
8
Macrocells
OE
I/O32 – I/O39 (Block E)
I/O Cells
2
64 x 68
AND Logic Array
and Logic Allocator
Macrocells
8
2
8
8
Macrocells
8
8
64 x 68
AND Logic Array
and Logic Allocator
Macrocells
8
I/O Cells
I/O24 – I/O31 (Block D)
CLK0/I0, CLK1/I1
CLK2/I3, CLK3/I4
4
4
2
4
I2, I5
BLOCK DIAGRAM (MACH231, MACH231SP)
14051K-012
23
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C
Device Junction Temperature . . . . . . . . . . . . . +150°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V
DC Output or I/O Pin Voltage . . -0.5 V to VCC +0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
Operating ranges define those limits between which the functionality of the device is guaranteed.
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Description
IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL
Min
Typ
Max
Unit
2.4
V
VOH
Output HIGH Voltage
IOH = –300 µA, VCC = Max, VIN = VIH or VIL (Note 1)
3.5
V
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min, VIN = VIH or VIL (Note 2)
0.5
V
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs
(Note 3)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all Inputs
(Note 3)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, V VCC = Max (Note 4)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 4)
–10
µA
IOZH
Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 4)
10
µA
IOZL
Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIH or VIL (Note 4)
–10
µA
ISC
Output Short-Circuit Current
–130 (Note 6),
–160
mA
VOUT = 0.5 V VCC = Max (Note 5)
2.0
–30
V
Notes:
1. This applies to MACH111SP, MACH131SP, and die code “B” or later for MACH211(SP) and MACH231(SP). This does not apply
to MACH111, MACH131, MACH221(SP), and die code “A” for MACH211(SP) and MACH231(SP).
2. Total IOL for one PAL block should not exceed 64 mA.
3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.
4. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
6. For commercial temperature range only.
24
MACH 1 & 2 Families
MACH111 AND MACH111SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
-5
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
tS
Setup Time from Input, I/O, or Feedback D-type
to Clock
T-type
tH
Register Data Hold Time
tCO
Clock to Output
tWL
tWH
fMAX
5
1/(tS + tCO)
Maximum
Frequency Internal Feedback (fCNT)
-10
7.5
-12
-14
-15
-18
10
12
14
15
18
ns
3.5
5.5
6.5
7
8.5
10
12
ns
4
6.5
7.5
8
10
11
13.5
ns
0
0
0
0
0
0
0
ns
3.5
Clock Width
External
Feedback
-7
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
5
6
8
10
10
12
ns
LOW
2.5
3
5
6
6
6
7.5
ns
HIGH
2.5
3
5
6
6
6
7.5
ns
D-type
143
95
80
66.7
54
50
42
MHz
T-type
133
87
74
62.5
50
47.6
39
MHz
D-type
182
133
100
76.9
69
66.6
53
MHz
T-type
167
125
91
71.4
57
55.5
44
MHz
200
167
100
83.3
83.3
83.3
66.7
MHz
No Feedback 1/(tWL + tWH)
tAR
Asynchronous Reset to Registered Output
7.5
9.5
tARW
Asynchronous Reset Width (Note 2)
4.5
5
7.5
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 2)
4.5
5
7.5
8
10
10
12
ns
tAP
Asynchronous Preset to Registered Output
tAPW
Asynchronous Preset Width (Note 2)
4.5
tAPR
Asynchronous Preset Recovery Time (Note 2)
4.5
tEA
Input, I/O, or Feedback to Output Enable
7.5
9.5
10
12
14.5
15
18
ns
tER
Input, I/O, or Feedback to Output Disable
7.5
9.5
10
12
14.5
15
18
ns
tLP
tPD Increase for Powered-down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
7
7
7
7
7
7
7
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
3
3
3
3
3
3
3
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
7.5
11
9.5
5
11
7.5
5
16
16
12
7.5
19.5
19.5
14.5
8
20
20
15
10
24
24
18
10
ns
ns
ns
12
ns
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH 1 & 2 Families
25
MACH131 AND MACH131SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
-5
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
tS
Setup Time from Input, I/O, or Feedback
tH
Hold Time
tCO
Clock to Output
tWL
tWH
fMAX
Maximum
Frequency
1/(tS + tCO)
Internal Feedback (fCNT)
No
Feedback
5.5
-10
7.5
-12
-14
-15
-18
10
12
14
15
18
ns
D-type
3.0
5.5
6.5
7
8.5
10
12
ns
T-type
3.5
6.5
7.5
8
10
11
13.5
ns
0
0
0
0
0
0
0
ns
4
Clock Width
External
Feedback
-7
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
5
6
8
10
10
12
ns
LOW
2.5
3
4
6
6
6
7.5
ns
HIGH
2.5
3
4
6
6
6
7.5
ns
D-type
143
95
80
66.7
54
50
42
MHz
T-type
133
87
74
62.5
50
47.6
39
MHz
D-type
182
133
100
76.9
69
66.6
53
MHz
T-type
167
125
91
71.4
57
55.5
44
MHz
200
167
125
83.3
83.3
83.3
66.7
MHz
1/(tWL + tWH)
tAR
Asynchronous Reset to Registered Output
8.5
9.5
tARW
Asynchronous Reset Width (Note 2)
4.5
5
7.5
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 2)
4.5
5
7.5
8
10
10
12
ns
tAP
Asynchronous Preset to Registered Output
tAPW
Asynchronous Preset Width (Note 2)
4.5
5
7.5
12
14.5
15
18
ns
tAPR
Asynchronous Preset Recovery Time (Note 2)
4.5
5
7.5
8
10
10
12
ns
tEA
Input, I/O, or Feedback to Output Enable
7.5
9.5
10
12
14.5
15
18
ns
tER
Input, I/O, or Feedback to Output Disable
7.5
9.5
10
12
14.5
15
18
ns
tLP
tPD Increase for Powered-Down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
tLPS
tS Increase for Powered-Down Macrocell (Note 3)
7
7
7
7
7
7
7
ns
tLPCO
tCO Increase for Powered-Down Macrocell (Note 3)
3
3
3
3
3
3
3
ns
tLPEA
tEA Increase for Powered-Down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
8.5
11
9.5
16
11
19.5
16
20
19.5
24
20
24
ns
ns
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book..
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered down, this parameter must be added to its respective high-speed parameter.
26
MACH 1 & 2 Families
MACH211 AND MACH211SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
-6
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial
Output
tS
Setup Time from Input, I/O, or Feedback D-type
to Clock
T-type
tH
Register Data Hold Time
tCO
Clock to Output
tWL
tWH
fMAX
Maximum
Frequency
Min
6
1/(tS + tCO)
Internal Feedback (fCNT)
-10
Max
Min
-12
Max
7.5
-14
-15
-18
Min Max Min Max Min Max Min
10
12
14
15
Max Unit
18
ns
5
5.5
6.5
7
8.5
10
12
ns
5.5
6.5
7.5
8
10
11
13.5
ns
0
0
0
0
0
0
0
ns
4
Clock Width
External
Feedback
-7
Min Max
1
4.5
6
8
10
10
12
ns
LOW
2.5
3
5
6
6
6
7.5
ns
HIGH
2.5
3
5
6
6
6
7.5
ns
D-type
111
100
80
66.7
54
50
42
MHz
T-type
105
91
74
62.5
50
47.6
39
MHz
D-type
166
133
100
83.3
69
66.6
55.6
MHz
T-type
150
125
91
76.9
62.5
62.5
51.3
MHz
200
167
100
83.3
83.3
83.3
66.7
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
No Feedback 1/(tWL + tWH)
5
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
0
0
0
0
0
0
0
ns
tGO
Gate to Output
7
7
7.5
7
8
(note 4)
(note 5)
13
10
11
11
(note 6)
ns
13.5
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
tSIR
Input Register Setup Time
1.5
2
2
2
2
2
2.5
ns
tHIR
Input Register Hold Time
1.5
2
2
2
2.5
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register
Setup
D-type
8
9
10
12
14.5
15
18
ns
T-type
9
10
11
13
16
16
19.5
ns
Input Register
Clock Width
LOW
2.5
3
5
6
6
6
7.5
ns
HIGH
2.5
3
5
6
6
6
7.5
ns
200
167
100
83.3
83.3
83.3
66.7
MHz
2.5
3
5
6
6
6
7.5
ns
20
9
9.5
12
14
17
17
(note 6)
ns
20.5
20
tWICL
tWICH
10
11
13
15
18
18
(note 6)
ns
22
fMAXIR
Maximum Input Register
Frequency
tSIL
Input Latch Setup Time
1.5
2
2
2
2
2
2.5
ns
tHIL
Input Latch Hold Time
1.5
2
2
2
2.5
2.5
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
12
12
14
17
20
20
24
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
13
14
16
19
22
22
26.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
7.5
8.5
9
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
9
10
11
13
16
16
19.5
ns
tWIGL
Input Latch Gate Width LOW
2.5
3
5
6
6
6
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
1/(tWICL + tWICH)
12
12.5
MACH 1 & 2 Families
14
16
19
19
23
ns
27
MACH211 AND MACH211SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
-6
Parameter Description
-7
Min Max
Min
-10
Max
Min
-12
Max
1
-14
-15
-18
Min Max Min Max Min Max Min
Max Unit
tAR
Asynchronous Reset to Registered or Latched
Output
tARW
Asynchronous Reset Width (Note 2)
4
5
10
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 2)
4
5
10
10
10
10
12
ns
tAP
Asynchronous Preset to Registered or Latched
Output
tAPW
Asynchronous Preset Width (Note 2)
4
5
10
12
14.5
15
18
ns
tAPR
Asynchronous Preset Recovery Time (Note 2)
4
5
10
10
10
10
12
ns
tEA
Input, I/O, or Feedback to Output Enable
tER
tLP
9
9.5
9
15
9.5
16
15
10
19.5
16
20
19.5
12
14
24
20
15
24
18
ns
ns
9
9.5
ns
Input, I/O, or Feedback to Output Disable
9
9.5
10
12
14
15
18
ns
tPD Increase for Powered-down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
0
0
0
0
0
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
10
10
10
10
10
10
10
ns
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
4. MACH211 tGO = 7 ns. MACH211SP tGO = 7.5 ns.
5. MACH211, commercial tGO = 7 ns.
6. The faster -18 tGO, tPDL, tICO, apply to MACH211 only, not MACH211SP.
28
MACH 1 & 2 Families
MACH221 and MACH221SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
-7
Parameter
Symbol
Parameter Description
Min
tPD
Input, I/O, or Feedback to Combinatorial Output
ts
Setup Time from Input, I/O, or Feedback to
Clock
tH
Register Data Hold Time
tCO
Clock to Output
tWL
tWH
Clock Width
Maximum
Frequency
Max
Min
7.5
1/(tS + tCO)
Internal Feedback (fCNT)
-12
Max
Min
10
D-type
5.5
6.5
T-type
6.5
0
-14
Max
Min
12
-15
Max
Min
14
-18
Max
Min
15
Max
Unit
18
ns
7
8.5
10
12
7.5
8
10
11
13.5
ns
0
0
0
0
0
ns
5
External
Feedback
fMAX
-10
1
6
8
10
10
ns
12
ns
LOW
3
5
6
6
6
7.5
ns
HIGH
3
5
6
6
6
7.5
ns
D-type
95
80
66.7
54
50
42
MHz
T-type
87
74
62.5
50
47.6
39
MHz
D-type
133
100
83.3
69
66.6
55.6
MHz
T-type
125
91
76.9
62.5
62.5
51.3
MHz
167
100
83.3
83.3
83.3
66.7
MHz
5.5
6.5
7
8.5
10
12
ns
0
0
0
0
0
0
ns
No Feedback 1/(tWL + tWH)
tSL
Setup Time from Input, I/O, or Feedback to Gate
tHL
Latch Data Hold Time
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
tSIR
Input Register Setup Time
2
tHIR
Input Register Hold Time
2
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
tWICL
Input Register
tWICH
Clock Width
HIGH
fMAXIR
Maximum Input Register
Frequency
tSIL
tHIL
tIGO
Input Latch Gate to Combinatorial Output
12
14
17
20
20
24
ns
tIGOL
Input Latch Gate to Output Through Transparent Output
Latch
14
16
19
22
22
26.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7.5
8.5
9
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
10
11
13
16
16
19.5
ns
tWIGL
Input Latch Gate Width LOW
3
5
6
6
6
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
11.5
14
16
19
19
23
ns
tAR
Asynchronous Reset to Registered or Latched Output
9.5
15
16
19.5
20
24
ns
tARW
Asynchronous Reset Width (Note 3)
5
10
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
5
8
10
10
10
12
ns
tAP
Asynchronous Preset to Registered or Latched Output
7
7
3
10
(note 2)
5
9.5
6
12
2
6
14
2
2
11
11
6
17
2
2
13
11
7.5
17
2
2.5
15
13.5
ns
20.5
2.5
2.5
18
ns
ns
3.5
18
ns
ns
22
ns
D-type
9
10
12
14.5
15
18
T-type
10
11
13
16
16
19.5
ns
LOW
3
5
6
6
6
7.5
ns
3
5
6
6
6
7.5
ns
167
100
83.3
83.3
83.3
66.7
MHz
Input Latch Setup Time
2
2
2
2
2
2.5
ns
Input Latch Hold Time
2
2
2
2.5
2.5
3.5
ns
1/(tWICL + tWICH)
9.5
15
MACH 1 & 2 Families
16
19.5
20
ns
24
ns
29
MACH221 and MACH221SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
-7
Parameter Description
Min
-10
Max
Min
-12
Max
Min
1
-14
Max
Min
-15
Max
Min
-18
Max
Min
Max
Unit
tAPW
Asynchronous Preset Width (Note 3)
5
tAPR
Asynchronous Preset Recovery Time (Note 3)
5
tEA
Input, I/O, or Feedback to Output Enable
9.5
12
12
14
15
18
ns
tER
Input, I/O, or Feedback to Output Disable
9.5
12
12
14
15
18
ns
tLP
tPD Increase for Powered-down Macrocell (Note 4)
10
10
10
10
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 4)
10
10
10
10
10
10
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 4)
0
0
0
0
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 4)
10
10
10
10
10
10
ns
10
12
8
14.5
10
15
10
18
10
ns
12
ns
Notes:
1. See “Switching Test Circuits” in the General Information section of the Vantis 1999 Data Book.
2. MACH221 tGO = 7 ns. MACH221SP tGO = 8 ns.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
4. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
30
MACH 1 & 2 Families
MACH231 AND MACH231SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
-6
Parameter
Symbol
Parameter Description
Min
-7
Max
Min
-10
Max
Min
-12
Max
Min
1
-14
Max
Min
-15
Max
Min
-18
Max
Min
Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
Setup Time from Input, I/O, or Feedback D-type
to Clock
T-type
5
5.5
6.5
7
8.5
10
12
ns
tS
6
6.5
7.5
8
10
11
13.5
ns
tH
Register Data Hold Time
0
0
0
0
0
0
0
ns
tCO
Clock to Output
tWL
7.5
4
10
5
12
6.5
14
8
15
10
18
10
12
ns
ns
LOW
2.5
3
4
6
6
6
7.5
ns
HIGH
2.5
3
4
6
6
6
7.5
ns
D-type
111
95
77
66.7
54
50
42
MHz
T-type
100
87
72
62.5
50
47.6
39
MHz
D-type
166
133
100
83.3
69
66.6
55.6
MHz
T-type
150
125
91
76.9
62.5
62.5
51.3
MHz
200
167
125
83.3
83.3
83.3
66.7
MHz
Clock Width
tWH
External
Feedback
fMAX
6
Maximum
Frequency
1/(tS + tCO)
Internal Feedback (fCNT)
No
Feedback
1/(tWL + tWH)
tSL
Setup Time from Input, I/O, or Feedback to Gate
5
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
0
0
0
0
0
0
0
ns
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
tSIR
Input Register Setup Time
1.5
2
2
2
2
2
2.5
ns
tHIR
Input Register Hold Time
1.5
2
2.5
2.5
2.5
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
Input Register Clock to output Register
Setup
D-type
8
9
11
12
14.5
15
18
ns
tICS
T-type
9
10
12
13
16
16
19.5
ns
Input Register
Clock Width
LOW
2.5
3
4
6
6
6
7.5
ns
HIGH
2.5
3
4
6
6
6
7.5
ns
tWICL
tWICH
5
2
6
3
9
7.5
4
9.5
10
8.5
6
14
11
11
6
14.5
15.5
11
6
17
16
13.5
7.5
17
18
ns
20.5
18
ns
22
ns
ns
fMAXIR
Maximum Input Register Frequency
200
167
125
83.3
83.3
83.3
66.7
MHz
tSIL
Input Latch Setup Time
1.5
2
2
2.5
2.5
2.5
2.5
ns
tHIL
Input Latch Hold Time
1.5
2
2.5
3
3
3
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
11
12
17
17
20
20
24
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
13
14
18
19.5
22
22
26.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
7.5
10
10.5
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
9
10
11
13.5
16
16
19.5
ns
MACH 1 & 2 Families
31
MACH231 AND MACH231SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
-6
Parameter Description
Min
-7
Max
Min
-10
Max
Min
-12
Max
Min
1
-14
Max
Min
-15
Max
Min
-18
Max
Min
Max Unit
tWIGL
Input Latch Gate Width LOW
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
11
12.5
16
17
19
19
23
ns
tAR
Asynchronous Reset to Registered or Latched
Output
9
9.5
13
16
19.5
20
24
ns
tARW
Asynchronous Reset Width (Note 2)
4
5
10
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time
(Note 2)
4
5
7.5
8
10
10
12
ns
tAP
Asynchronous Preset to Registered or Latched
Output
tAPW
Asynchronous Preset Width (Note 2)
4
5
10
12
14.5
15
18
ns
tAPR
Asynchronous Preset Recovery Time (Note 2)
4
5
7.5
8
10
10
12
ns
tEA
Input, I/O, or Feedback to Output Enable
9
9.5
10
12
15
15
18
ns
tER
Input, I/O, or Feedback to Output Disable
9
9.5
10
12
15
15
18
ns
tLP
tPD Increase for Powered-down Macrocell (Note 3)
9
10
10
10
10
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
6
7
7
7
7
7
7
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
0
0
0
0
0
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
9
10
10
10
10
10
10
ns
2
3
9
4
6
9.5
13
6
16
6
19.5
7.5
ns
20
24
ns
Notes:
1. See “Switching Test Circuit” in the General Information section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
CAPACITANCE 1
Parameter Symbol
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN = 2.0V
COUT
Output Capacitance
VOUT = 2.0V
VCC = 5.0V,
TA = 25°C
f = 1 MHz
Typ
Unit
6
pF
8
pF
Note:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
these parameters may be affected.
32
MACH 1 & 2 Families
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency.
The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type
register.
TA = 25°C, VCC =5V
MACH111(SP)
MACH131(SP)
150
ICC (mA)
100
Low Power
75
ICC (mA)
High Speed
125
50
25
0
0
10
20
30
40
50
60
70
80
90
250
225
200
175
150
High Speed
Low Power
125
100
75
50
25
0
100 110 120 130 140 150
0
10
20
30
MACH211(SP)
High Speed
Low Power
100
ICC (mA)
ICC (mA)
125
75
50
25
0
20
30
40
50
60
70
80
70
90
275
250
225
200
175
150
125
100
75
50
25
0
80
90
100 110 120 130 140 150
High Speed
Low Power
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
Frequency (MHz)
MACH231
MACH231SP
400
350
400
300
High Speed
350
High Speed
300
250
250
200
200
Low Power
ICC (mA)
ICC (mA)
60
MACH 221(SP)
150
10
50
Frequency (MHz)
Frequency (MHz)
0
40
150
150
100
100
50
0
0
0
10
20
30
40
50
60
70
80
Low Power
0
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
MACH 1 & 2 Families
33
Table 12. ICC
Device
Parameter Symbol
Parameter
Description
Test Description
MACH111(SP)
MACH211(SP)
Supply Current (Static)
MACH131(SP)
MACH231SP
MACH111(SP)
MACH211(SP)
70
75
135
ICC
45
Supply Current (Active)
MACH231SP
VCC = 5V,
TA = 25°C,
f = 1 MHz
75
80
100
MACH231
34
VCC = 5V,
TA = 25°C,
f = 0 MHz
80
MACH221(SP)
MACH131(SP)
Unit
40
MACH221(SP)
MACH231
Typ
150
MACH 1 & 2 Families
mA
44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
3 2
I/O28
I/O29
I/O30
I/O31
VCC
GND
5 4
I/O0
6
I/O1
I/O3
I/O2
I/O4
44-Pin PLCC
1 44 43 42 41 40
7
39
I/O27
I/O6
8
38
I/O26
I/O7
9
37
I/O25
(TDI) I0
10
36
I/O24
(CLK 0/I0) CLK0/I1
11
35
CLK3/I5 (TDO)
GND
12
34
GND
(TCK) CLK1/I2
13
33
CLK2/I4 (CLK 1/I1)
I/O8
14
32
I3 (TMS)
I/O9
15
31
I/O23
I/O10
16
30
I/O22
I/O11
17
29
I/O21
I/O5
Block A
Block B
I/O20
I/O19
I/O18
I/O17
GND
I/O16
VCC
I/O15
I/O14
I/O13
I/O12
18 19 20 21 22 23 24 25 26 27 28
14051K-018
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Clock or Input
Ground
Input
Input/Output
Supply Voltage
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
MACH 1 & 2 Families
35
44-PIN TQFP CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44
43
42
41
40
39
38
37
36
35
34
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
44-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
Block B
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
12
13
14
15
16
17
18
19
20
21
22
Block A
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
14051K-019
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Clock or Input
Ground
Input
Input/Output
Supply Voltage
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
36
MACH 1 & 2 Families
84-PIN PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15)
Top View
84-Pin PLCC
Block D
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
VCC
I5
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
Block A
GND
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
GND
VCC
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I2
VCC
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I0
VCC
GND
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
72
14
15
71
70
16
69
17
68
18
67
19
66
20
65
21
64
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Block C
Block B
14051K-020
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
MACH 1 & 2 Families
37
100-PIN PQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)
Top View
100-Pin PQFP
Block D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
Block A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
GND
TDO
N/C
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
IO/CLK0
VCC
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
N/C
TCK
GND
GND
Block B
Block C
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
38
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
MACH 1 & 2 Families
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
14051K-021
100-PIN TQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)
Top View
100-Pin TQFP
Block D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
GND
NC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
NC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GND
Block A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
TDO
NC
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
NC
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
GND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TDI
I/5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
TCK
Block B
Block C
14051K-022
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
MACH 1 & 2 Families
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
39
44-PIN PLCC CONNECTION DIAGRAM (MACH211-7/10/12/15 AND
MACH211SP-6/7/10/12/15)
Top View
44-Pin PLCC
3 2
I/O28
I/O29
I/O30
I/O31
VCC
GND
5 4
I/O0
6
I/O1
I/O2
I/O3
Block D
I/O4
Block A
1 44 43 42 41 40
I/O5
7
39
I/O27
I/O6
8
38
I/O26
I/O7
9
37
I/O25
(TDI) I0
10
36
I/O24
(CLK 0/I0) CLK0/I1
11
35
CLK3/I5 (TDO)
GND
12
34
GND
(TCK) CLK1/I2
13
33
CLK2/I4 (CLK 1/I1)
I/O8
14
32
I3 (TMS)
I/O9
15
31
I/O23
I/O10
16
30
I/O22
I/O11
17
29
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
VCC
GND
I/O15
I/O14
I/O13
I/O12
18 19 20 21 22 23 24 25 26 27 28
Block B
Block C
14051K-023
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
Note:
1. Pin designators in parentheses ( ) apply to the MACH211SP
40
MACH 1 & 2 Families
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
44-PIN TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND
MACH211SP-6/7/10/12/15)
Top View
44-Pin TQFP
Block D
44
43
42
41
40
39
38
37
36
35
34
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
Block A
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
12
13
14
15
16
17
18
19
20
21
22
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
Block B
Block C
14051K-024
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
Note:
1. Pin designators in parentheses ( ) apply to the MACH211SP
MACH 1 & 2 Families
41
68-PIN PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15)
Top View
68-Pin PLCC
Block H
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
I7
GND
VCC
I6
CLK3/I5
CLK2/I4
I/O35
I/O34
I/O33
I/O32
I/O31
GND
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
VCC
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
GND
I/O30
Block C
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block F
I/O7
I/O8
I/O9
I/O10
I/O11
CLK0/I0
CLK1/I1
I2
VCC
GND
I3
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
Block G
Block B
I/O6
GND
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
GND
Block A
Block D
Block E
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
42
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
MACH 1 & 2 Families
14051K-025
100-PIN PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15)
Top View
100-Pin PQFP
Block H
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
GND
TDO
N/C
I6
I/O41
N/C
I/O40
I/O39
I/O38
I/O37
I/O36
I5/CLK3
GND
GND
VCC
VCC
I4/CLK2
I/O35
I/O34
I/O33
I/O32
I/O31
N/C
I/O30
N/C
I3
TMS
GND
GND
Block G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Block F
GND
GND
TDI
I7
N/C
I/O6
N/C
I/O7
I/O8
I/O9
I/O10
I/O11
IO/CLK0
VCC
VCC
GND
GND
I1/CLK1
I/O12
I/O13
I/O14
I/O15
I/O16
N/C
I/O17
I2
N/C
TCK
GND
GND
N/C
I/O18
N/C
I/O19
I/O20
I/O21
I/O22
I/O23
VCC
GND
GND
VCC
I/O24
I/O25
I/O26
I/O27
I/O28
N/C
I/O29
N/C
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Block C
Block B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
N/C
I/O5
N/C
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
I/O47
I/O46
I/O45
I/O44
I/O43
N/C
I/O42
N/C
Block A
14051K-026
Block E
Block D
PIN DESIGNATIONS
I/CLK
GND
I
I/O
VCC
=
=
=
=
=
Input or Clock
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
MACH 1 & 2 Families
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
43
84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15)
Top View
84-Pin PLCC
Block H
GND
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
GND
VCC
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
Block G
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
74
13
73
72
14
71
15
70
16
17
69
68
18
67
19
66
20
21
65
64
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Block F
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I0
VCC
GND
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I2
VCC
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
Block C
Block B
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
VCC
I5
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
Block A
Block D
Block E
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
44
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
MACH 1 & 2 Families
14051K-027
100-PIN PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
100-Pin PQFP
Block H
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
GND
TDO
N/C
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
Block G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Block F
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
IO/CLK0
VCC
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
N/C
TCK
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Block C
Block B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
Block A
Block D
Block E
14051K-028
PIN DESIGNATIONS
I/CLK
GND
I
I/O
VCC
=
=
=
=
=
Input or Clock
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
MACH 1 & 2 Families
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
45
100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
100-Pin TQFP
Block H
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
TDO
NC
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
Block G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Block F
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
TCK
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
NC
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
GND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Block C
Block B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
GND
NC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
NC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GND
Block A
Block D
Block E
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
46
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
TDI
TCK
TMS
TDO
=
=
=
=
MACH 1 & 2 Families
Test
Test
Test
Test
Data In
Clock
Mode Select
Data Out
14051K-029
ORDERING INFORMATION
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is
formed by a combination of:
MACH
131
SP
-5
Y
C
FAMILY TYPE
MACH = Macro Array CMOS High-Density
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/1
= First Revision
MACROCELL DENSITY
111
= 32 Macrocells, 32 I/Os
131
= 64 Macrocells, 64 I/Os
211
= 64 Macrocells, 32 I/Os
221
= 96 Macrocells, 48 I/Os
231
= 128 Macrocells, 64 I/Os
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
I
= Industrial (-40°C to +85°C)
PACKAGE TYPE
J
= Plastic Leaded Chip Carrier
(PLCC)
V = Thin Quad Flat Pack (TQFP)
Y = Plastic Quad Flat Pack (PQFP)
PRODUCT DESIGNATION
SP
= JTAG-compatible, In-system Programmable
SPEED
-5 = 5.0 or 5.5 ns tPD
-6 = 6.0 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-14 = 14 ns tPD
-15 = 15 ns tPD
-18 = 18 ns tPD
Valid Combinations – Commercial
Valid Combinations – Industrial
MACH111
-5, -7, -10, -12, -15
JC, VC
MACH111
-7, -10, -12, -14, -18
JI
MACH111SP
-5, -7, -10, -12, -15
JC, VC
MACH111SP
-7, -10, -12, -14, -18
JI
MACH131
-5, -7, -10, -12, -15
JC/1
MACH131
-7, -10, -12, -14, -18
JI/1
MACH131SP
-5, -7, -10, -12, -15
VC, YC
MACH131SP
-7, -10, -12, -14, -18
YI
-7, -10, -12, -15
JC, VC
MACH211
-10, -12, -14, -18
JI
-6, -7, -10, -12, -15
JC, VC
MACH211SP
-10, -12, -14, -18
JI
MACH221
-7, -10, -12, -15
JC
MACH221
-10, -12, -14, -18
JI
MACH221SP
-7, -10, -12, -15
YC
MACH221SP
-10, -12, -14, -18
YI
-6, -7
JC
MACH231
-12, -14, -18
JI/1
-10, -12, -15
JC/1
MACH231SP
-12, -14, -18
YI
-10, -12, -15
VC, YC
MACH211
MACH211SP
MACH231
MACH231SP
Valid Combinations
The Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local Lattice/
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
Note:
1. All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e.
MACH131SP-5YC-7YI
MACH 1 & 2 Families
47
48
MACH 1 & 2 Families