19-5106; Rev 0; 12/09 KIT ATION EVALU E L B A AVAIL 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs 4 6 MAX11049ETN+ 56 TQFN-EP* 8 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. DB4 DB3 DB0 CH1 RD DVDD 51 20 DVDD CS WR 52 19 SHDN CONVST CS 53 18 CONVST SHDN RD 54 RDC DB14 56 DGND 17 EOC *EP + 16 DB0 15 DB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB2 DB15 55 DB3 EOC DB4 EXT REF 21 DGND DGND 50 DB8 REFIO REF BUF 22 RDC WR DB9 BANDGAP REFERENCE 23 AGNDS MAX11047 MAX11048 MAX11049 DB10 INT REF AVDD 24 AVDD AGNDS 48 DB11 INTERFACE AND CONTROL AGND 25 AGND AVDD 47 DB12 AGND MAX11047 MAX11048 MAX11049 CH2 26 CH0 AGND 46 DB13 AGNDS AGNDS 27 AGNDS CH7 45 RDC 49 CONFIGURATION REGISTERS CH3 28 RDC AGNDS 44 DB5 16-BIT ADC 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RDC 43 DB6 S/H 16-BIT ADC DB7 CLAMP S/H RDC TOP VIEW REFIO Pin Configuration DVDD CLAMP BIDIRECTIONAL DRIVERS CH7 56 TQFN-EP* 56 TQFN-EP* DB15 8 x 16-BIT REGISTERS CH0 DVDD MAX11047ETN+ DGND AVDD CHANNELS MAX11048ETN+ CH4 Functional Diagram PIN-PACKAGE AGNDS Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis PART CH5 Automatic Test Equipment Power-Factor Monitoring and Correction Ordering Information AGND Applications AVDD The MAX11047/MAX11048/MAX11049 operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11047/MAX11048/MAX11049 are available in a 56-pin TQFN package and operate over the extended -40°C to +85°C temperature range. 4-/6-/8-Channel 16-Bit ADC Single Analog and Digital Supply High-Impedance Inputs Up to 1GΩ On-Chip T/H Circuit for Each Channel Fast 3µs Conversion Time High Throughput: 250ksps for All 8 Channels 16-Bit, High-Speed, Parallel Interface Internal Clocked Conversions 10ns Aperture Delay 100ps Channel-to-Channel T/H Matching Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of 0 to 5V o External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of +3.7V to +5.2V o 56-Pin TQFN Package (8mm x 8mm) o Evaluation Kit Available CH6 The MAX11047/MAX11048/MAX11049 16-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The MAX11047/MAX11048/MAX11049 accept a 0 to +5V input. All inputs are overrange protected with internal ±20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, 16-bit, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. Features o o o o o o o o o o o TQFN ____________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX11047/MAX11048/MAX11049 General Description MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0–CH7 to AGND ...............................................-2.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (AVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (DVDD + 0.3V) and +6V DB0–DB15 to AGND ....................................-0.3V to the lower of (DVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derated 36mW/°C above +70°C) ........2222mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -2 ±0.6 +2 LSB > -1 ±0.6 < +1.3 LSB STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity N INL 16 (Note 2) Integral Nonlinearity INL (Note 3) Differential Nonlinearity DNL (Note 2) Differential Nonlinearity DNL (Note 3) No Missing Codes Bits ±0.8 LSB ±0.7 LSB 16 Bits ±0.002 Offset Error Offset Temperature Coefficient ±0.01 ±2.4 %FSR μV/°C Channel Offset Matching ±0.01 %FSR Gain Error ±0.03 %FSR Positive Full-Scale Error ±0.02 %FSR Positive Full-Scale Error Matching Channel Gain-Error Matching Between all channels Gain Temperature Coefficient ±0.02 %FSR ±0.03 %FSR ±0.8 ppm/°C DYNAMIC PERFORMANCE (Note 4) Signal-to-Noise Ratio SNR fIN = 10kHz, full-scale input 91 92.3 dB Signal-to-Noise and Distortion Ratio SINAD fIN = 10kHz, full-scale input 90.5 92 dB Spurious-Free Dynamic Range SFDR fIN = 10kHz, full-scale input 95 Total Harmonic Distortion THD fIN = 10kHz, full-scale input -105 -95 dB fIN = 60Hz, full scale and ground on adjacent channel (Note 5) -126 -100 dB 0 1.22 x VREFIO V -1 +1 μA Channel-to-Channel Crosstalk 106 dB ANALOG INPUTS (CH0–CH7) Input Voltage Range Input Leakage Current 2 (Note 6) _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Input Capacitance TYP MAX UNITS +20 mA 250 ksps 15 Input-Clamp Protection Current Each input simultaneously -20 pF TRACK AND HOLD Throughput Rate Per channel, 8 channels in 4μs Acquisition Time tACQ 1 -3dB point Full-Power Bandwidth μs 4 -0.1dB point MHz > 0.2 Aperture Delay 10 ns Aperture-Delay Matching 100 ps Aperture Jitter 50 psRMS INTERNAL REFERENCE REFIO Voltage VREF 4.073 REFIO Temperature Coefficient 4.096 4.119 ±5 V ppm/°C EXTERNAL REFERENCE Input Current REF Voltage Input Range VREF -10 +10 μA 3.00 4.25 V REF Input Capacitance 15 pF DIGITAL INPUTS (DB0–DB15, RD, WR, CS, CONVST) Input-Voltage High VIH VDVDD = 2.7V to 5.25V Input-Voltage Low VIL VDVDD = 2.7V to 5.25V Input Capacitance CIN Input Current IIN VIN = 0 or VDVDD Output-Voltage High VOH ISOURCE = 1.2mA Output-Voltage Low VOL 2 V 0.8 10 V pF ±10 μA DIGITAL OUTPUTS (DB0–DB15, EOC) VDVDD 0.4 V ISINK = 1mA 0.4 V Three-State Leakage Current DB0–DB15, VRD ≥ VIH or VCS ≥ VIH 10 μA Three-State Output Capacitance DB0–DB15, VRD ≥ VIH or VCS ≥ VIH 15 pF POWER SUPPLIES (MAX11047) Analog Supply Voltage AVDD 4.75 5.25 V Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current IAVDD Digital Supply Current IDVDD Shutdown Current Shutdown Current 32 mA VDVDD = 3.3V (Note 7) 5.7 mA For DVDD 10 μA For AVDD Power-Supply Rejection Ratio PSRR VAVDD = 4.9V to 5.1V (Note 8) 12 ±0.5 μA LSB _______________________________________________________________________________________ 3 MAX11047/MAX11048/MAX11049 ELECTRICAL CHARACTERISTICS (continued) MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V POWER SUPPLIES (MAX11048) Analog Supply Voltage AVDD 4.75 5.25 Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current IAVDD 36 mA Digital Supply Current IDVDD VDVDD = 3.3V (Note 7) 6.5 mA Shutdown Current For DVDD 10 μA Shutdown Current For AVDD 12 Power-Supply Rejection Ratio PSRR ±0.5 VAVDD = 4.9V to 5.1V (Note 8) μA LSB POWER SUPPLIES (MAX11049) Analog Supply Voltage AVDD 4.75 5.25 Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current IAVDD 40 mA Digital Supply Current IDVDD VDVDD = 3.3V (Note 7) 7.3 mA Shutdown Current For DVDD 10 μA Shutdown Current For AVDD 12 Power-Supply Rejection Ratio PSRR VAVDD = 4.9V to 5.1V (Note 8) CONVST Rise to EOC Fall tCON Conversion time (Note 9) Acquisition Time tACQ ±0.5 V μA LSB TIMING CHARACTERISTICS (Note 7) 3 1 μs μs CS Rise to CONVST Rise tQ CONVST Rise to EOC Rise t0 EOC Fall to CONVST Fall t1 CONVST mode B0 = 0 only (Note 10) 0 ns CONVST Low Time t2 CONVST mode B0 = 1 only 20 ns ns Sample quiet time (Note 9) 500 ns 65 140 ns CS Fall to WR Fall t3 0 WR Low Time t4 20 ns CS Rise to WR Rise t5 0 ns Input Data Setup Time t6 10 ns Input Data Hold Time t7 0 ns CS Fall to RD Fall t8 0 ns RD Low Time t9 30 ns RD Rise to CS Rise t10 0 ns RD High Time t11 10 ns RD Fall to Data Valid t12 RD Rise to Data Hold Time t13 4 35 (Note 10) 5 _______________________________________________________________________________________ ns ns 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) Note 1: See the Definitions section at the end of the data sheet. Note 2: Guaranteed at 5V ≤ VAVDD ≤ 5.25V for+25°C ≤ TA ≤ +85°C. See the Input Range and Protection section and Typical Operating Characteristics. Note 3: TA = -40°C. Note 4: Dynamic performance is guaranteed at AVDD = 5.0V to 5.25V. See the Input Range and Protection section and the Typical Operating Characteristics. Note 5: Tested with alternating channels modulated at full scale and ground. Note 6: See the Input Range and Protection section. Note 7: CLOAD= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 8: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage. Note 9: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 10: Guaranteed by design. Typical Operating Characteristics (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) DIFFERENTIAL NONLINEARITY (DNL) vs. CODE 0.2 0.2 DNL (LSB) 0.4 0.4 0 -0.4 -0.6 MAX DNL 0 -1.5 65536 57344 49152 40960 24576 32768 MIN INL 4.75 4.85 5.05 5.15 5.25 VAVDD (V) TA = +25°C fSAMPLE = 250ksps 35 33 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V 31 29 -0.5 MIN INL 4.95 MAX11049 STATIC MAX11049 CONVERTING MAX11048 STATIC MAX11048 CONVERTING MAX11047 CONVERTING 27 MIN DNL MAX11047 toc05 37 IAVDD (mA) 0.5 VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX11047 toc04 1.0 MAX11047 toc03 MIN DNL -0.5 OUTPUT CODE (DECIMAL) MAX INL -1.0 MAX DNL 0 -1.0 INL AND DNL vs. TEMPERATURE 1.5 0.5 -0.8 -1.0 65536 57344 32768 24576 8192 -0.2 OUTPUT CODE (DECIMAL) INL AND DNL (LSB) 0 16384 -0.8 -1.0 49152 -0.6 40960 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -0.4 MAX INL 1.0 0 16384 -0.2 1.5 INL AND DNL (LSB) 0.6 8192 0.6 VAVDD = 5.0V, VDVDD = 3.3V, fSAMPLE = 250ksps TA = +25°C, VRDC = 4.096V 0.8 0 0.8 INL (LSB) 1.0 MAX11047 toc01 1.0 INL AND DNL vs. ANALOG SUPPLY VOLTAGE MAX11047 toc02 INTEGRAL NONLINEARITY (INL) vs. CODE MAX11047 STATIC 25 -1.5 -40 -15 10 35 TEMPERATURE (°C) 60 85 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) _______________________________________________________________________________________ 5 MAX11047/MAX11048/MAX11049 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX11047 CONVERTING 2 10 60 MAX11047/MAX11048/ MAX11049 STATIC 0 2.75 85 VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF 1.2 3.25 3.75 4.25 4.75 5.25 -40 -15 10 35 60 VDVDD (V) TEMPERATURE (°C) ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE 4 3 2 VAVDD = 5.0V VDVDD = 3.3V IDVDD 5 10 4 35 60 VRDC 4.09505 2 4.09500 IDVDD VREFIO 4.09495 0 85 TA = +25°C 4.09515 4.09510 3 1 0 -15 IAVDD TA = +25°C 85 4.09520 MAX11047 toc9a IAVDD 2.75 3.25 3.75 4.25 4.75 5.25 4.09490 4.75 4.85 4.95 5.05 5.15 5.25 TEMPERATURE (°C) AVDD OR VDVDD (V) VAVDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE VAVDD = 5.0V 4.108 4.104 0.010 0.006 ERRORS (%FS) UPPER TYPICAL LIMIT TA = +25°C 4.100 4.096 4.092 OFFSET ERROR MATCHING 0.002 -0.002 VAVDD = 5.0V VREFIO = 4.096V 0.006 OFFSET ERROR MATCHING 0.002 -0.002 OFFSET ERROR OFFSET ERROR LOWER TYPICAL LIMIT 4.088 0.010 ERRORS (%FS) 4.112 MAX11047 toc11 -40 MAX11047/MAX11048/ MAX11049 STATIC MAX11047 CONVERTING TEMPERATURE (°C) 5 1 2.4 0 35 MAX11048 CONVERTING MAX11047 CONVERTING 3.6 MAX11047 toc13 -15 SHUTDOWN CURRENT (µA) -40 MAX11048 CONVERTING MAX11047 toc10 4 MAX11047 STATIC 23 4.8 6 MAX11048 STATIC MAX11049 CONVERTING 6.0 VREF (V) 27 SHUTDOWN CURRENT (µA) IDVDD (mA) MAX11048 CONVERTING MAX11047 toc09 IAVDD (mA) 8 MAX11049 STATIC 31 MAX11047 toc08 TA = +25°C fSAMPLE = 250ksps CDBxx = 15pF 10 7.2 IDVDD (mA) MAX11049 CONVERTING MAX11049 CONVERTING MAX11047 toc12 35 12 MAX11047 toc06 VAVDD = 5.0V fSAMPLE = 250ksps DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX11047 toc07 ANALOG SUPPLY CURRENT vs. TEMPERATURE VREFIO (V) MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs -0.006 -0.006 4.084 4.080 -0.010 -40 -15 10 35 TEMPERATURE (°C) 6 60 85 4.75 4.85 4.95 5.05 VAVDD (V) 5.15 5.25 -0.010 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE ERRORS (%FS) 0.002 -0.002 GAIN-ERROR MATCHING GAIN ERROR 0.002 GAIN-ERROR MATCHING -0.002 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V -20 -40 MAX11047 toc16 VAVDD = 5.0V 0.006 ERRORS (%FS) GAIN ERROR FFT PLOT 0 MAGNITUDE (dB) TA = +25°C 0.006 0.010 MAX11047 toc14 0.010 MAX11047 toc15 GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE -60 -80 -100 -0.006 -0.006 4.85 4.95 5.05 5.15 5.25 60 85 0 25 50 75 100 TWO-TONE IMD PLOT TOTAL HARMONIC DISTORTION vs. TEMPERATURE SNR SNR AND SINAD (dB) 92.5 9.2 10.0 10.8 -106.0 91.5 VAVDD = 5.0V fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 91.0 90.0 12.4 11.6 -40 FREQUENCY (kHz) -15 10 SINAD -106.5 -107.0 -107.5 35 60 -108.0 85 -40 -15 60 85 THD vs. ANALOG SUPPLY VOLTAGE MAX11047 toc21 SNR 92.5 35 -105.0 MAX11047 toc20 93.0 10 TEMPERATURE (°C) TEMPERATURE (°C) SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE -105.5 -106.0 91.5 THD (dB) 92.0 SINAD 91.0 4.75 4.85 4.95 -106.5 -107.0 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 90.5 90.0 VAVDD = 5.0V fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -105.5 92.0 90.5 8.4 -105.0 125 MAX11047 toc19 MAX11047 toc17 93.0 -120 7.6 35 SIGNAL-TO-NOISE RATIO (SNR) AND SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. TEMPERATURE -100 -140 10 FREQUENCY (kHz) -80 SNR AND SINAD (dB) MAGNITUDE (dB) -60 -15 TEMPERATURE (°C) fIN1 = 9834Hz fIN2 = 10384Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS -40 -140 -40 VAVDD (V) 0 -20 -0.010 THD (dB) 4.75 MAX11047 toc18 -0.010 -120 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -107.5 -108.0 5.05 VAVDD (V) 5.15 5.25 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) _______________________________________________________________________________________ 7 MAX11047/MAX11048/MAX11049 Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. FREQUENCY -95 THD (dB) 92 91 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 89 0.1 -95 -110 -120 1.0 100.0 10.0 0.1 1.0 10.0 100.0 FREQUENCY (kHz) FREQUENCY (kHz) CROSSTALK vs. FREQUENCY OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO 2.5V -115 24,000 VCHX = 2.500270V VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C 20,000 16,000 12,000 -120 8000 32774 32773 FREQUENCY (kHz) 32772 0 100.0 10.0 32771 1.0 32770 0.1 32769 4000 32768 -125 MAX11047 toc23 -115 NUMBER OF OCCURENCES -105 -105 -110 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT GND -100 -100 MAX11047 toc25 90 88 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -90 MAX11047 toc24 SINAD (dB) 93 CROSSTALK (dB) THD vs. INPUT FREQUENCY -85 MAX11047 toc22 94 OUTPUT CODE (DECIMAL) CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE CONVERSION TIME vs. TEMPERATURE 2.99 CONVERSION TIME (µs) 2.98 2.97 2.96 2.95 2.94 2.93 MAX11047 toc27 2.99 2.98 2.97 2.96 2.95 2.94 2.93 2.92 2.92 4.75 4.85 4.95 5.05 VAVDD (V) 8 3.00 MAX11047 toc26 3.00 CONVERSION TIME (µs) MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs 5.15 5.25 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs PIN NAME 1 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 FUNCTION 2 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 3 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 4 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 5 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 6 DB8 7, 21, 50 DGND Digital Ground 16-Bit Parallel Data Bus Digital Output Bit 8 8, 20, 51 DVDD Digital Supply. Bypass to DGND with a 0.1μF capacitor at each DVDD input. 9 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 10 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 11 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 12 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 13 DB3 16-Bit Parallel Data Bus Digital I/O Bit 3 14 DB2 16-Bit Parallel Data Bus Digital I/O Bit 2 15 DB1 16-Bit Parallel Data Bus Digital I/O Bit 1 16 DB0 16-Bit Parallel Data Bus Digital I/O Bit 0 17 EOC Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. 18 CONVST 19 SHDN 22, 28, 35, 43, 49 RDC 23, 27, 33, 38, 44, 48 AGNDS 24, 30, 41, 47 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1μF capacitor at each AVDD input. 25, 31, 40, 46 AGND Analog Ground. Connect all AGND inputs together. 26 CH0 Channel 0 Analog Input for the MAX11049 29 CH1 Channel 1 Analog Input for the MAX11049. Channel 0 for the MAX11048. 32 CH2 Channel 2 Analog Input for MAX11049. Channel 1 for the MAX11048, Channel 0 for the MAX11047. 34 CH3 Channel 3 Analog Input for MAX11049. Channel 2 for the MAX11048, Channel 1 for the MAX11047. 36 REFIO External Reference Input/Internal Reference Output. Place a 0.1μF capacitor from REFIO to AGND. 37 CH4 Channel 4 Analog Input for the MAX11049. Channel 3 for the MAX11048, Channel 2 for the MAX11047. 39 CH5 Channel 5 Analog Input for the MAX11049. Channel 4 for the MAX11048, Channel 3 for the MAX11047. Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode is zero. Active-High Shutdown Input. Drive the SHDN high to place the device into a low-current state. In shutdown mode, the contents of the configuration register are not lost. Reference Buffer Decoupling. Bypass to AGND with at least a 22μF capacitor each at pins 22, 28, 43, and 49. Connect all RDC outputs together and bypass with 80μF total capacitance. See the Layout, Grounding, and Bypassing section. Signal Ground. Connect all AGND and AGNDS inputs together. _______________________________________________________________________________________ 9 MAX11047/MAX11048/MAX11049 Pin Description MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN NAME 42 CH6 Channel 6 Analog Input for MAX11049. Channel 5 for MAX11048. 45 CH7 Channel 7 Analog Input for MAX11049 52 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 53 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 54 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 55 DB15 56 DB14 — EP FUNCTION 16-Bit Parallel Data Bus Digital Out Bit 15 16-Bit Parallel Data Bus Digital Out Bit 14 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. Detailed Description The MAX11047/MAX11048/MAX11049 are fast, lowpower ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the MAX11047/MAX11048/MAX11049 ideal for motor control and power monitoring. The MAX11047/ MAX11048/MAX11049 are available with a 0 to 5V input range that features ±20mA overrange, fault-tolerant inputs. The MAX11047/MAX11048/MAX11049 operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The MAX11047/MAX11048/MAX11049 perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3μs following the end of a sample. The data bus is bidirectional and allows for easy programming of the configuration register. The MAX11047/MAX11048/MAX11049 feature a reference buffer, which is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with a 0.1μF capacitor to ground when using the internal reference. Analog Inputs Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by 10 using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For MAX11047/MAX11048/ MAX11049, the input is unipolar in the range of: 0 to + VREFIO x 5.0 4.096 In external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in a full-scale input range of 3.662V to 5.188V, respectively. All analog inputs are fault-protected up to ±20mA. The MAX11047/MAX11048/MAX11049 include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below -300mV. The clamp circuit remains high impedance while the input signal is within the range of 0V to +VAVDD and draws little to no current. However, when the input signal exceeds the range of 0V to +VAVDD, the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of 0V to +VAVDD. To make use of the input clamps, connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the MAX11047/MAX11048/MAX11049 does not exceed ±20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Applications Information VFAULT _ MAX − 7V Digital Interface 20mA where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280Ω. While the input voltage is within the range of -300mV to +(VAVDD + 300mV), no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. INPUT SIGNAL The bidirectional, parallel, digital interface, DB0–DB3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0–DB3, together with the output-only DB4–DB15, also output the 16-bit conversion result. All bits are high impedance when RD = 1 or CS = 1. PIN VOLTAGE AVDD DVDD DB15 CLAMP S/H 16-BIT ADC 8 x 16-BIT REGISTERS CH0 SOURCE CH7 CLAMP S/H BIDIRECTIONAL DRIVERS RS DB4 DB3 DB0 16-BIT ADC CONFIGURATION REGISTERS AGNDs MAX11047 MAX11048 MAX11049 WR RD CS INTERFACE AND CONTROL AGND CONVST SHDN EOC INT REF BANDGAP REFERENCE RDC REF BUF DGND EXT REF REFIO Figure 1. Required Setup for Clamp Circuit 25 15 15 ICLAMP (mA) AT SOURCE -5 0 -5 -10 -15 -15 -20 -20 -30 -20 -10 0 10 20 30 40 SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) Figure 2. Input Clamp Characteristics AT SOURCE 5 -10 -25 AT CH_ INPUT 10 5 0 RS = 1170I VAVDD = 5.0V 20 AT CH_ INPUT 10 ICLAMP (mA) 25 RS = 1170I VAVDD = 5.0V 20 -25 -4 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) Figure 3. Input Clamp Characteristics (Zoom In) ______________________________________________________________________________________ 11 MAX11047/MAX11048/MAX11049 RS = MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs DB3 (Int/Ext Reference) DB3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10kΩ resistor, bypass with 0.1μF capacitor to AGND. 1 = external reference, drive REFIO with a high quality reference. DB2 (Output Data Format) DB2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two’s complement. DB1 (Reserved) Set to 0 for normal operation. 0 = normal operation. 1 = reserved; do not use. DB0 (CONVST Mode) DB0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on DB3–DB0 of the bus and then raise WR once to save changes. Starting a Conversion CONVST initiates conversions. The MAX11047/ MAX11048/MAX11049 provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. In default mode (DB0 = 0), drive CONVST low to place the MAX11047/MAX11048/MAX11049 into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1μs (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the MAX11047/MAX11048/MAX11049 begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. 12 Table 1. Configuration Register DB3 DB2 DB1 DB0 Int/Ext Reference Output Data Format Reserved CONVST Mode In the second mode (DB0 = 1), the MAX11047/ MAX11048/MAX11049 enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. Drive CONVST low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the MAX11047/ MAX11048/MAX11049. Reading Conversion Results The CS and RD are active-low, digital inputs that control the readout through the 16-bit, parallel, 20MHz data bus (D0–D15). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel’s result. When CS and RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout. Reference Internal Reference The MAX11047/MAX11048/MAX11049 feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1μF capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10kΩ. Drive only high-impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10μV in the bandwidth of up to 50kHz. Reference Buffer The MAX11047/MAX11048/MAX11049 have a built- in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference modes. The internal reference buffer output feeds five RDC outputs. Connect all RDC outputs together. The reference buffer is externally compensated and requires at least 10μF on the RDC node for stability. For best performance, provide a total of at least 80μF on the RDC outputs. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Layout, Grounding, and Bypassing For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND, AGND, and AGNDS pins on the MAX11047/MAX11048/MAX11049 to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. To achieve the highest performance, connect all the RDC outputs to a local RDC plane on the PCB. Bypass the RDC outputs with a total of at least 80μF of capacitance. For example, if two capacitors are used, place two 47μF, 10V X5R capacitors in 1210 case size as close as possible to pins 22 and 49. Alternatively, if four capacitors are used, place four 22μF, 10V X5R capacitors in 1210 case size as close as possible to pins 22, 28, 43, and 49. Ensure that each capacitor is connected directly into the GND plane with an independent via. In cases where Y5U or Z5U ceramics are used, select higher voltage rating capacitors to compensate for the high-voltage coefficient of these ceramic capacitors, thus ensuring that at least 80μF of capacitance is on the RDC plane when the plane is driven to 4.096V by the internal reference buffer. For example, at 4.096V, a 22μF X5R ceramic capacitor with a 10V rating diminishes to only 20μF, whereas the same capacitor in Y5U ceramic at 4.096V decreases to about 13μF. However, a 22μF Y5U ceramic capacitor with a 25V rating capacitor is approximately 20μF at 4.096V. Bypass AVDD and DVDD to the ground plane with 0.1μF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10μF decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the MAX11047/ MAX11048/MAX11049 and the DVDD power plane from the digital interface side of the device. For sampling periods near minimum (1μs) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the MAX11047/MAX11048/MAX11049. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. CS (USER SUPPLIED) t5 t3 CS (USER SUPPLIED) t4 WR (USER SUPPLIED) t10 t9 t8 t11 RD (USER SUPPLIED) t7 t13 t12 t6 D0–D15 D0–D15 (USER SUPPLIED) Sn Sn + 1 CONFIGURATION REGISTER Figure 4. Programming Configuration-Register Timing Requirements Figure 5. Readout Timing Requirements ______________________________________________________________________________________ 13 MAX11047/MAX11048/MAX11049 Transfer Functions Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values. MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs SAMPLE tCON tACQ CONVST t1 EOC tO tQ CS RD D0–D15 S0 S1 S6 S7 Figure 6. Conversion Timing Diagram (DB0 = 0) SAMPLE tCON tACQ CONVST t2 EOC tO tQ CS RD D0–D15 S0 S1 S6 S7 Figure 7. Conversion Timing Diagram (DB0 = 1) 14 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs LSB = FS 65536 FFFF FULL-SCALE TRANSITION OUTPUT CODE (hex) OUTPUT CODE (hex) FS 65536 0001 0000 FFFF 8001 8000 7FFF FFFE 7FFE 8001 0001 8000 0000 FS/2 +FS 0 FS/2 VIN x 65536 - 32768, 5 VRDC x 4.096 FS = +FS INPUT VOLTAGE (LSB) INPUT VOLTAGE (LSB) CODE = FULL-SCALE TRANSITION FFFE 7FFE 0 LSB = 5 x VRDC 4.096 Figure 8. Two’s Complement Transfer Function Typical Application Circuits Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worstcase value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function for an SAR ADC. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. CODE = 5 x VRDC VIN x 65536 , FS = 4.096 5 4.096 VRDC x Figure 9. Offset-Binary Transfer Function Offset Error For the MAX11047/MAX11048/MAX11049, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x8000 to 0x8001 for two’s complement encoding. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (5/4.096) x VREF/65,536 above GND. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transition and the ideal analog input of 0.5 x (5/4.096) x VREF/65,536 above GND, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (5/4.096) x V REF x (65,534/65,536). For the MAX11047/MAX11048/MAX11049, top code transition is 0x7FFE to 0x7FFF in two’s complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two’s complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11047/MAX11048/MAX11049, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (5/4.096) x VREF x (65,534/65,536) from this measurement. ______________________________________________________________________________________ 15 MAX11047/MAX11048/MAX11049 7FFF MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs VOLTAGE TRANSFORMER PHASE 1 OPT 2.5V ADC OPT CURRENT TRANSFORMER ADC 2.5V VN NEUTRAL ADC IN ADC LOAD 1 MAX11049 LOAD 2 LOAD 3 I3 V3 I2 ADC ADC PHASE 2 V2 ADC ADC PHASE 3 Figure 10. Power-Grid Protection 16 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 DSP-BASED DIGITAL PROCESSING ENGINE MAX11048 16-BIT ADC IGBT CURRENT DRIVERS 16-BIT ADC 16-BIT ADC 16-BIT ADC 16-BIT ADC IPHASE1 IPHASE3 IPHASE2 3-PHASE ELECTRIC MOTOR POSITION ENCODER Figure 11. DSP Motor Control ______________________________________________________________________________________ 17 MAX11047/MAX11048/MAX11049 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: ⎡ ⎤ Signal RMS SINAD(dB) = 10 × log ⎢ ⎥ ⎣ (Noise + Distortion) RMS ⎦ Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = SINAD − 1. 76 6. 02 Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is expressed as: Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channel-to-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency. Chip Information PROCESS: BiCMOS ⎡ V2 2 + V3 2 + V4 2 + V 5 2 THD = 20 × log ⎢ V1 ⎢ ⎣ ⎤ ⎥ ⎥ ⎦ where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 56 TQFN-EP T5688+2 21-0135 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.