19-4100; Rev 0; 4/08 1% Accurate, Low-Voltage, Quad Window Voltage Detector Features The MAX16063 is a 1% accurate, adjustable, quad window voltage detector in a small thin QFN package. This device is designed to provide a higher level of system reliability by monitoring multiple supply voltages and providing a fault signal when any of the voltages exceed their overvoltage thresholds or fall below their undervoltage thresholds. o Monitor Four Undervoltage/Overvoltage Conditions o 1% Accuracy Over Temperature o User-Adjustable Voltage Thresholds (Down to 0.4V) o Open-Drain Outputs with Internal Pullups Reduce the Number of External Components o Manual Reset Input o Margin Enable Input o Fixed or Adjustable RESET Timeout o Guaranteed to Remain Asserted Down to VCC = 1V o Fully Specified from -40°C to +125°C o Small, 4mm x 4mm Thin QFN Package The MAX16063 offers user-adjustable voltage thresholds that allow voltages to be monitored down to 0.4V. This allows the upper and lower trip thresholds of each window detector to be set externally with the use of three external resistors. Each monitored threshold has an independent opendrain output for signaling a fault condition. The outputs can be wire-ORed together to provide a single fault output. The open-drain outputs are internally pulled up with a 30µA current, but can be externally driven to other voltage levels for interfacing to other logic levels. Features include a margin input to disable the outputs during margin testing or any other time after power-up operations. Also featured is a reset output that deasserts after a reset timeout period after all voltages are within their threshold specifications. The reset timeout is internally set to 140ms (min), but can be externally adjusted to other reset timeouts using an external capacitor. In addition, the MAX16063 offers a manual reset input. This device is offered in a 4mm x 4mm thin QFN package and is fully specified from -40°C to +125°C. Ordering Information PART MAX16063TG+ TEMP RANGE PIN-PACKAGE -40°C to +125°C 24 TQFN-EP* +Denotes a lead-free package. *EP = Exposed pad. For tape-and-reel, add a “T” after the “+.” Tape-and-reel are offered in 2.5k increments. Typical Operating Circuit 3.5V 2.5V 1.8V 1.5V SRT VCC MARGIN UVIN1 RESET UVOUT1 Networking/Telecommunications Equipment OVIN1 OVOUT1 UVIN2 UVOUT2 Multivoltage ASICs Servers Automotive VCC µC GND Applications Storage Equipment RESET MAX16063 OVIN2 OVOUT2 UVIN3 UVOUT3 OVIN3 OVOUT3 UVIN4 UVOUT4 OVIN4 OVOUT4 GND MR Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX16063 General Description MAX16063 1% Accurate, Low-Voltage, Quad Window Voltage Detector ABSOLUTE MAXIMUM RATINGS VCC, OVOUT_, UVOUT_, RESET, UVIN_, OVIN_ to GND .........................................-0.3V to +6V MARGIN, MR, SRT to GND ........................-0.3V to (VCC + 0.3V) Input/Output Current (RESET, MARGIN, SRT, MR, UVOUT_, OVOUT_) .......±20mA Continuous Power Dissipation (TA = +70°C) 24-Pin Thin QFN (derate 16.9mW/°C above +70°C) ....1666mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER Operating Voltage Range Supply Current (Note 3) UVLO (Undervoltage Lockout) UVLO Hysteresis SYMBOL VCC ICC VUVLO CONDITIONS (Note 2) MIN TYP 1.0 MAX UNITS 5.5 V VCC = 3.3V, outputs deasserted 45 65 VCC = 5V, outputs deasserted 50 70 1.80 1.98 VCC rising 1.62 VUVLO_HYS 65 µA V mV UVIN_/OVIN_ Adjustable Threshold (UVIN_ Falling/OVIN_ Rising) UVIN_/OVIN_ Hysteresis UVIN_/OVIN_ Input Current VTH VTH_HYS 0.390 UVIN_ falling/OVIN_ rising (percentage of the threshold) IIB 0.394 0.398 0.5 -100 V % VTH +100 nA RESET Reset Timeout tRP SRT Ramp Current ISRT SRT = VCC 140 200 280 CSRT = 1500pF (Note 4) 2.43 3.09 3.92 CSRT = 100pF 0.206 CSRT = open VSRT = 0V SRT Threshold SRT Hysteresis UVIN_/OVIN_ to Reset Delay 2 tRD UVIN_ falling/OVIN_ rising ms 0.05 460 600 740 nA 1.173 1.235 1.293 V 100 mV 20 µs _______________________________________________________________________________________ 1% Accurate, Low-Voltage, Quad Window Voltage Detector (VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER RESET Output-Voltage Low RESET Output-Voltage High SYMBOL VOL VOH MR Input-Voltage Low VIL MR Input-Voltage High VIH CONDITIONS MIN TYP MAX VCC = 3.3V, ISINK = 10mA, RESET asserted 0.3 VCC = 2.5V, ISINK = 6mA, RESET asserted 0.3 VCC = 1.2V, ISINK = 50µA, RESET asserted 0.3 VCC ≥ 2.0V, ISOURCE = 6µA, RESET deasserted 0.8 x VCC V 0.7 x VCC V 1 µs MR Glitch Rejection 100 MR to RESET Delay 200 MR Pullup Resistance V V 0.3 x VCC MR Minimum Pulse Width UNITS 12 20 ns ns 28 kΩ OUTPUTS (UVOUT_/OVOUT_) UVOUT_, OVOUT_ OutputVoltage Low VOL UVOUT_, OVOUT_ OutputVoltage High VOH UVIN_/OVIN_ to UVOUT_/ OVOUT_ Propagation Delay tD VCC = 3.3V, ISINK = 2mA 0.3 VCC = 2.5V, ISINK = 1.2mA 0.3 VCC ≥ 2.0V, ISOURCE = 6µA 0.8 x VCC (VTH - 100mV) to (VTH + 100mV) V V 20 µs DIGITAL LOGIC MARGIN Input-Voltage Low VIL MARGIN Input-Voltage High VIH MARGIN Pullup Resistance MARGIN Delay Time 0.3 x VCC 0.7 x VCC Pulled up to VCC tMD Rising or falling (Note 5) 12 V V 20 50 28 kΩ µs Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX. The outputs are guaranteed to remain asserted down to VCC = 1V. Measured with MR and MARGIN unconnected. The minimum and maximum specifications for this parameter are guaranteed by using the worse case of the SRT current and SRT threshold specifications. Note 5: Amount of time required for logic to lock/unlock outputs from margin testing. Note 1: Note 2: Note 3: Note 4: _______________________________________________________________________________________ 3 MAX16063 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 50 45 40 35 VCC = 5V 0.425 50 45 VCC = 3.3V 40 VCC = 2.5V 0.400 0.375 35 30 0.350 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) UVIN_/OVIN_ THRESHOLD vs. TEMPERATURE OUTPUT VOLTAGE vs. SINK CURRENT MAXIMUM TRANSIENT DURATION vs. INPUT OVERDRIVE 0.43 100 0.42 VOUT_ (mV) 75 0.41 0.40 0.39 50 0.38 25 0.37 0.36 600 OUTPUT GOES LOW ABOVE THIS LINE 500 5.5 MAX16063 toc06 0.44 MAXIMUM TRANSIENT DURATION (µs) MAX16063 toc04 0.45 MAX16063 toc05 1.5 400 300 200 100 UVOUT_ / OVOUT_ LOW 0.35 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 4 MAX16063 toc03 55 0.450 MAX16063 toc02 60 MARGIN AND MR UNCONNECTED INPUT THRESHOLD SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 65 MAX16063 toc01 MARGIN AND MR UNCONNECTED 55 UVIN_/OVIN_ THRESHOLD vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 60 INPUT THRESHOLD MAX16063 1% Accurate, Low-Voltage, Quad Window Voltage Detector 0 1 2 3 4 5 SINK CURRENT (mA) 6 7 8 1 10 100 INPUT OVERDRIVE (mV) _______________________________________________________________________________________ 1000 1% Accurate, Low-Voltage, Quad Window Voltage Detector RESET TIMEOUT PERIOD vs. TEMPERATURE MAX16063 toc07 197 RESET TIMEOUT PERIOD (ms) RESET TIMEOUT DELAY MAX16063 toc08 198 UVIN1 1V/div 196 195 UVOUT1 2V/div 194 193 RESET 2V/div 192 191 SRT = VCC 190 -40 -25 -10 5 20 35 50 65 80 95 110 125 40ms/div TEMPERATURE (°C) UVIN_ TO UVOUT_ DELAY TIME MARGIN ENABLE FUNCTION MAX16063 toc09 MAX16063 toc10 MARGIN 2V/div UVIN1 2V/div UVOUT_ 2V/div UVOUT1 2V/div RESET 2V/div UVIN_ BELOW RESPECTIVE THRESHOLDS 4µs/div 100µs/div _______________________________________________________________________________________ 5 MAX16063 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) 1% Accurate, Low-Voltage, Quad Window Voltage Detector MAX16063 Pin Description PIN 6 NAME FUNCTION 1 UVIN3 Undervoltage Threshold Input 3. When the voltage on UVIN3 falls below its threshold, UVOUT3 asserts low. 2 OVIN3 Overvoltage Threshold Input 3. When the voltage on OVIN3 rises above its threshold, OVOUT3 asserts low. 3 UVIN4 Undervoltage Threshold Input 4. When the voltage on UVIN4 falls below its threshold, UVOUT4 asserts low. 4 OVIN4 5 N.C. Overvoltage Threshold Input 4. When the voltage on OVIN4 rises above its threshold, OVOUT4 asserts low. No Connection. Not internally connected. 6 GND Ground 7, 24 VCC Unmonitored Power to the Device 8 UVOUT3 Active-Low Undervoltage Output 3. When the voltage at UVIN3 falls below its threshold, UVOUT3 asserts low and stays asserted until the voltage at UVIN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC. 9 OVOUT3 Active-Low Overvoltage Output 3. When the voltage at OVIN3 rises above its threshold, OVOUT3 asserts low and stays asserted until the voltage at OVIN3 falls below its threshold. The open-drain output has a 30µA internal pullup to VCC. 10 UVOUT4 Active-Low Undervoltage Output 4. When the voltage at UVIN4 falls below its threshold, UVOUT4 asserts low and stays asserted until the voltage at UVIN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC. 11 OVOUT4 Active-Low Overvoltage Output 4. When the voltage at OVIN4 rises above its threshold, OVOUT4 asserts low and stays asserted until the voltage at OVIN4 falls below its threshold. The open-drain output has a 30µA internal pullup to VCC. 12 MR Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20kΩ resistor. 13 SRT Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC. 14 MARGIN Active-Low Margin Enable Input. Pull MARGIN low to deassert all outputs (go into high state) regardless of the voltage at any monitored input. _______________________________________________________________________________________ 1% Accurate, Low-Voltage, Quad Window Voltage Detector PIN NAME 15 OVOUT2 Active-Low Overvoltage Output 2. When the voltage at OVIN2 rises above its threshold, OVOUT2 asserts low and stays asserted until the voltage at OVIN2 falls below its threshold. The open-drain output has a 30µA internal pullup to VCC. 16 UVOUT2 Active-Low Undervoltage Output 2. When the voltage at UVIN2 falls below its threshold, UVOUT2 asserts low and stays asserted until the voltage at UVIN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC. 17 OVOUT1 Active-Low Overvoltage Output 1. When the voltage at OVIN1 rises above its threshold, OVOUT1 asserts low and stays asserted until the voltage at OVIN1 falls below its threshold. The open-drain output has a 30µA internal pullup to VCC. 18 UVOUT1 Active-Low Undervoltage Output 1. When the voltage at UVIN1 falls below its threshold, UVOUT1 asserts low and stays asserted until the voltage at UVIN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC. 19 RESET Active-Low Reset Output. RESET asserts low when the voltage on any of the UVIN_ inputs falls below their respective thresholds, the voltage on any of the OVIN_ inputs goes above its respective threshold, or MR is asserted. RESET remains asserted for at least the minimum reset timeout after all monitored UVIN_ inputs exceed their respective thresholds, all OVIN_ inputs fall below their respective thresholds, and MR is deasserted. This open-drain output has a 30µA internal pullup. 20 UVIN1 Undervoltage Threshold Input 1. When the voltage on UVIN1 falls below its threshold, UVOUT1 asserts low. 21 OVIN1 Overvoltage Threshold Input 1. When the voltage on OVIN1 rises above its threshold, OVOUT1 asserts low. 22 UVIN2 Undervoltage Threshold Input 2. When the voltages on UVIN2 falls below its threshold, UVOUT2 asserts low. 23 OVIN2 Overvoltage Threshold Input 2. When the voltage on OVIN2 rises above its threshold, OVOUT2 asserts low. EP Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the only electrical connection to GND. — FUNCTION _______________________________________________________________________________________ 7 MAX16063 Pin Description (continued) MAX16063 1% Accurate, Low-Voltage, Quad Window Voltage Detector MR SRT VCC VCC TIMING RESET CIRCUIT RESET UVIN1 UVOUT1 OVIN1 OVOUT1 UVIN2 UVOUT2 OUTPUT DRIVER OVOUT2 OVIN2 UVIN3 UVOUT3 OVOUT3 OVIN3 UVIN4 UVOUT4 OVOUT4 VCC OVIN4 VCC UNDERVOLTAGE LOCKOUT VCC MAX16063 REFERENCE MARGIN Figure 1. Functional Diagram 8 _______________________________________________________________________________________ 1% Accurate, Low-Voltage, Quad Window Voltage Detector The MAX16063 is an adjustable quad window voltage detector in a small thin QFN package. This device is designed to provide a higher level of system reliability by monitoring multiple supply voltages and providing a fault signal when any of the voltages exceeds its overvoltage threshold or falls below its undervoltage threshold. This device offers user-adjustable thresholds that allow voltages to be monitored down to 0.4V. It allows the upper and lower trip thresholds of each window detector to be set externally with the use of three external resistors. Each monitored threshold has an independent opendrain output for signaling a fault condition. The outputs can be wire-ORed together to provide a single fault output. The open-drain outputs are internally pulled up with a 30µA current, but can be externally driven to other voltage levels for interfacing to other logic levels. The MAX16063 features a margin input to disable the outputs during margin testing or any other time after power-up operations and a reset output that deasserts after a reset timeout period after all voltages are within their threshold specification. The reset timeout is internally set to 140ms (min), but can be externally adjusted to other reset timeouts using an external capacitor. In addition, a manual reset input is offered. Applications Information Voltage Monitoring The MAX16063 features undervoltage and overvoltage comparators for window detection (see Figure 2). UVOUT_/OVOUT_ deassert high when the monitored voltage is within the “selected window.” When the monitored voltage falls below the lower limit of the window (VTRIPLOW), UVOUT_ asserts low; or if the monitored voltage exceeds the upper limit (VTRIPHIGH), OVOUT_ asserts low. The application in Figure 2 shows the MAX16063 enabling the DC-DC converter when the monitored voltage is in the selected window. MAX16063 Detailed Description +5V R1 VCC UVIN_ OVOUT_ R2 IN UVOUT_ EN OUT DC-DC REGULATOR MAX16063 GND OVIN_ R3 Figure 2. MAX16063 Monitor Circuit The resistor values R1, R2, and R3 can be calculated as shown: ⎛R ⎞ VTRIPLOW = VTH ⎜ TOTAL ⎟ 2 3 R + R ⎝ ⎠ ⎛R ⎞ VTRIPHIGH = VTH ⎜ TOTAL ⎟ ⎝ R3 ⎠ where RTOTAL = R1 + R2 + R3. Use the following steps to determine the values for R1, R2, and R3: 1) Choose a value for RTOTAL, the sum of R1, R2, and R3. Because the MAX16063 has very low input bias current (2nA typ), R TOTAL can be up to 2MΩ. Large-value resistors help minimize power consumption. Lower-value resistors can be used to maintain overall accuracy. _______________________________________________________________________________________ 9 1% Accurate, Low-Voltage, Quad Window Voltage Detector MAX16063 Use the following formulas to calculate the error: ⎛ R1 R3 ⎞ IIB ⎜ R1 + ⎝ R2 + R3 ⎟⎠ EUV (%) = x 100 VTRIPLOW I (R2 + (2 x R1)) x 100 EOV (%) = IB VTRIPHIGH where EUV and EOV are the undervoltage and overvoltage error (in %), respectively. 2) Calculate R3 based on RTOTAL and the desired upper trip point: powered directly from the system voltage supply. Select R1 and R2 to set the trip voltage. When the supply voltage remains below the selected threshold, a low logic level on UVOUT_ turns on the p-channel MOSFET. In the case of an overvoltage event, UVOUT_ goes high turning off the MOSFET, and shuts down the power to the load. Figure 4 shows a similar application using a fuse and a silicon-controlled rectifier (SCR). An overvoltage event turns on the SCR and shorts the supply to ground. The surge of current through the short circuit blows the fuse and terminates the current to the load. Select R3 so that the gate of the SCR is properly biased when UVOUT_ goes high. Unused Inputs R3 = Any unused UVIN_ inputs must be connected to VCC, and any unused OVIN_ inputs must be connected to GND. VTH x R TOTAL VTRIPHIGH UVOUT_ / OVOUT_ Outputs 3) Calculate R2 based on R TOTAL , R3, and the desired lower trip point: R2 = VTH x R TOTAL − R3 VTRIPLOW 4) Calculate R1 based on RTOTAL, R3, and R2: R1 = R TOTAL − R2 − R 3 Overvoltage Shutdown The MAX16063 is ideal for overvoltage-shutdown applications. Figure 3 shows a typical circuit for this application using a pass p-channel MOSFET. The MAX16063 is UVOUT_ and OVOUT_ outputs assert low when UVIN_ and OVIN_, respectively, drop below or exceed their specified thresholds. The undervoltage/overvoltage outputs are open-drain with a (30µA) internal pullup to VCC. For many applications, no external pullup resistor is required to interface with other logic devices. An external pullup resistor to any voltage up to 5.5V overdrives the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to VCC (Figure 5). When choosing the external pullup resistor, the resistance value should be large enough to ensure that the output can sink the necessary current during a logic-low condition and small enough to be able to overdrive the internal pullup current and meet output high specifications (V OH ). Resistor values of 50kΩ to 200kΩ can generally be used. VSUPPLY FUSE VSUPPLY R1 VCC VCC R2 LOAD LOAD UVIN_ MAX16063 R3* R3 R1 MAX16063 SCR UVIN_ UVOUT_ GND UVOUT_ R2 GND *OPTIONAL. VALUES OF 10kΩ AND ABOVE ARE RECOMMENDED. Figure 3. Overvoltage Shutdown Circuit (with External Pass MOSFET) 10 Figure 4. Overvoltage Shutdown Circuit (with SCR Fuse) ______________________________________________________________________________________ 1% Accurate, Low-Voltage, Quad Window Voltage Detector Reset Timeout Capacitor The reset timeout period can be adjusted to accommodate a variety of microprocessor (µP) applications. Adjust the reset timeout period (tRP) by connecting a capacitor (CSRT) between SRT and GND. Calculate the reset timeout capacitor as follows: tRP (s) CSRT (F) = ⎛ VTH _ SRT ⎞ ⎜ I ⎟ ⎝ SRT ⎠ Connect SRT to VCC for a factory-programmed reset timeout of 140ms (min). Manual Reset Input (MR) Many µP-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on MR asserts RESET low. RESET remains asserted while MR is low, and during the reset timeout period (140ms min) after MR returns high. The MR input has an internal 20kΩ pullup resistor to VCC, so it can be left open if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1µF capacitor from MR to GND provides additional noise immunity. UVIN_ VTH_ VCC = 3.3V VTH_ + VTH_HYS 5V RESET 100kΩ VCC 90% 10% VCC tRD UVOUT_ RESET tRP UVOUT_ 90% 10% tD tD MAX16063 GND GND VTH_ OVIN_ VTH_ - VTH_HYS OVOUT_ 90% 10% tD Figure 5. Interfacing to a Different Logic Supply Voltage tD Figure 6. Output Timing Diagram ______________________________________________________________________________________ 11 MAX16063 RESET Output RESET asserts low when the voltage on any of the UVIN_ inputs falls below its respective threshold, the voltage on any of the OVIN_ inputs goes above its respective threshold, or MR is asserted. RESET remains asserted for the reset timeout period after all monitored UVIN_ inputs exceed their respective thresholds, all OVIN_ inputs fall below their respective thresholds, and MR is deasserted (see Figure 6). This open-drain output has a 30µA internal pullup. MAX16063 1% Accurate, Low-Voltage, Quad Window Voltage Detector Margin Output Disable (MARGIN) MARGIN allows system-level testing while power supplies are adjusted from their nominal voltages. Drive MARGIN low to deassert all outputs (UVOUT_, OVOUT_, and RESET) regardless of the voltage at any monitored input. The state of each output does not change while MARGIN = GND. While MARGIN is low, the IC continues to monitor all voltages. When MARGIN is deasserted, the outputs go to their monitored states after a short propagation delay. The MARGIN input is internally pulled up to VCC. Leave unconnected or connect to VCC if unused. Undervoltage Lockout (UVLO) The MAX16063 features a VCC undervoltage lockout (UVLO) that preserves a reset status even if VCC falls as low as 1V. The undervoltage lockout circuitry monitors the voltage at VCC. If VCC falls below the UVLO falling threshold (typically 1.735V), RESET is asserted and all 12 detector outputs are asserted low. This eliminates an incorrect RESET or detector output state as VCC drops below the normal V CC operational voltage range of 1.98V to 5.5V. During power-up as VCC rises above 1V, RESET is asserted and all detector outputs are asserted low until VCC exceeds the UVLO threshold. As VCC exceeds the UVLO threshold, all inputs are monitored and the correct output state appears at all the outputs. This also ensures that RESET and all detector outputs are in the correct state once VCC reaches the normal VCC operational range. Power-Supply Bypassing In noisy applications, bypass VCC to ground with a 0.1µF capacitor as close to the device as possible. In addition, the additional capacitor improves transient immunity. For fast-rising V CC transients, additional capacitance may be required. ______________________________________________________________________________________ 1% Accurate, Low-Voltage, Quad Window Voltage Detector OVOUT1 UVOUT2 OVOUT2 MARGIN SRT TOP VIEW UVOUT1 PROCESS: BiCMOS 18 17 16 15 14 13 Package Information For the latest package outline information, go to www.maxim-ic.com/packages. RESET 19 12 MR UVIN1 20 11 OVOUT4 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 UVOUT4 24 TQFN T2444-4 21-0139 9 OVOUT3 8 UVOUT3 7 VCC OVIN1 21 MAX16063 UVIN2 22 OVIN2 23 + 1 2 3 4 5 6 UVIN3 OVIN3 UVIN4 OVIN4 N.C. GND VCC 24 THIN QFN (4mm x 4mm) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX16063 Chip Information Pin Configuration