19-5875; Rev 0; 5/11 EVALUATION KIT AVAILABLE MAX2769B Universal GPS Receiver General Description Features The MAX2769B is a next-generation Global Navigation Satellite System (GNSS) receiver covering GPS, GLONASS, Galileo, and Compass navigation satellite systems on a single chip. This single-conversion GNSS receiver is designed to provide high performance for industrial and automotive applications. S AEC-Q100 Automotive Qualified Designed on Maxim’s advanced, low-power SiGe BiCMOS process technology, the MAX2769B offers the highest performance and integration at a low cost. Incorporated on the chip is the complete receiver chain, including a dual-input LNA and mixer, followed by the image-rejected filter, PGA, VCO, fractional-N frequency synthesizer, crystal oscillator, and a multibit ADC. The total cascaded noise figure of this receiver is as low as 1.4dB. S Fractional-N Synthesizer with Integrated VCO Supports Wide Range of Reference Frequencies S No External IF SAW or Discrete Filters Required S Programmable IF Frequency S Dual-Input Uncommitted LNA for Separate Passive and Active Antenna Inputs S 1.4dB Cascade Noise Figure S Integrated Crystal Oscillator S Integrated Active Antenna Sensor S 2.7V to 3.3V Supply Voltage S Small, 28-Pin, RoHS-Compliant, Thin QFN LeadFree Package (5mm x 5mm) Ordering Information appears at end of data sheet. CLKOUT XTAL 19 18 17 16 15 PLL MAX2769B IDLE 24 Location-Enabled Mobile Handsets Telematics (Asset Tracking, Inventory Management) PGM 26 LNA2 VCO LNA1 27 3-WIRE INTERFACE LNA2 25 0 PNDs (Personal Navigation Devices) Marine/Avionics Navigation LNA1 Software GPS 1 2 3 4 5 6 7 ANTBIAS VCC_RF MIXIN LD SHDN + LNAOUT For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX2769B.related. N.C. 28 ANTFLAG Laptops and Netbooks 14 VCCD 13 VCC_CP 12 CPOUT 11 VCC_VCO 10 CS 9 SCLK 8 SDATA FILTER 90 Automotive Navigation Systems Q1 VCC_IF 23 Q0 Applications 20 ADC N.C. 22 21 ADC The MAX2769B is packaged in a 5mm x 5mm, 28-pin thin QFN package with an exposed paddle. VCC_ADC Block Diagram I0 The MAX2769B is the most flexible receiver on the market. The integrated delta-sigma fractional-N frequency synthesizer allows programming of the IF frequency within a ±30Hz (fXTAL = 32MHz) accuracy while operating with any reference or crystal frequencies that are available in the host system. The ADC outputs CMOS logic levels with 1 or 2 quantized bits for both I and Q channels, or up to 3 quantized bits for the I channel. I and Q analog outputs are also available. S 40pF Output Clock Drive Capability I1 The MAX2769B completely eliminates the need for external IF filters by implementing on-chip monolithic filters and requires only a few external components to form a complete low-cost GPS RF receiver solution. S GPS/GLONASS/Galileo/Compass Systems ����������������������������������������������������������������� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX2769B Universal GPS Receiver ABSOLUTE MAXIMUM RATINGS VCC_ to Ground.....................................................-0.3V to +4.2V Other Pins Except LNA_, MIXIN, XTAL, and LNAOUT to Ground............................. -0.3V to +(Operating VCC_ + 0.3V) Maximum RF Input Power.............................................. +15dBm Continuous Power Dissipation (TA = +70NC) TQFN (derates 27mW/NC above +70NC)....................2500mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 2.7 2.85 3.3 V Default mode, LNA1 is active (Note 2) 18 27 31 Default mode, LNA2 is active (Note 2) 15 25 30.5 Supply Voltage Supply Current mA 5 Idle ModeK, IDLE = low, SHDN = high Shutdown mode, SHDN = low 200 FA Voltage Drop at ANTBIAS from VCC_RF Sourcing 20mA at ANTBIAS 0.2 V Short-Circuit Protection Current at ANTBIAS ANTBIAS is shorted to ground 57 mA Active Antenna Detection Current To assert logic-high at ANTFLAG 1.1 mA DIGITAL INPUT AND OUTPUT Digital Input Logic-High Measure at the SHDN pin Digital Input Logic-Low Measure at the SHDN pin 1.5 V 0.4 V Idle Mode is a trademark of Maxim Integrated Products, Inc. ����������������������������������������������������������������� Maxim Integrated Products 2 *The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet. MAX2769B Universal GPS Receiver AC ELECTRICAL CHARACTERISTICS* (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS CASCADED RF PERFORMANCE RF Frequency L1 band 1575.42 LNA1 input active, default mode (Note 3) Noise Figure Out-of-Band 3rd-Order Input Intercept Point MHz 1.4 LNA2 input active, default mode (Note 3) 2.7 Measured at the mixer input 10.3 -7 dBm In-Band Mixer Input Referred 1dB Measured at the mixer input Compression Point -85 dBm Mixer Input Return Loss 10 dB Image Rejection 25 dB Spurs at LNA1 Input Maximum Voltage Gain Measured at the mixer input (Note 4) dB LO leakage -101 Reference harmonics leakage -103 Measured from the mixer to the baseband analog output Variable Gain Range 91 96 55 59 dBm 103 dB dB FILTER RESPONSE FBW = 00 Passband Center Frequency Passband 3dB Bandwidth Lowpass 3dB Bandwidth Stopband Attenuation 4 FBW = 10 4 FBW = 01 9.27 FBW = 00 2.5 FBW = 10 4.2 FBW = 01 9.66 FBW = 11 9 3rd-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 5th-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 30 40 49.5 MHz MHz MHz dB LNA LNA1 INPUT Power Gain 19 Noise Figure dB 0.83 dB -1.1 dBm Output Return Loss 10 dB Intput Return Loss 8 dB Input IP3 (Note 5) ����������������������������������������������������������������� Maxim Integrated Products 3 *The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet. MAX2769B Universal GPS Receiver AC ELECTRICAL CHARACTERISTICS* (continued) (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS LNA2 INPUT Power Gain 13 Noise Figure dB 1.14 dB 1 dBm Output Return Loss 19 dB Input Return Loss 11 dB Input IP3 (Note 5) FREQUENCY SYNTHESIZER LO Frequency Range 0.2V < VTUNE < (VCC_ - 0.3V) 1550 LO Tuning Gain 1610 57 MHz MHz/V Reference Input Frequency 8 44 MHz Main Divider Ratio 36 32,767 — 1023 — Reference Divider Ratio Charge-Pump Current 1 ICP = 0 0.5 ICP = 1 1 mA TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER Frequency Range 8 Output Logic-Level High (VOH) With respect to ground, IOH = 10FA (DC-coupled) Output Logic-Level Low (VOL) With respect to ground, IOL = 10FA (DC-coupled) Capacitive Slew Current 32 2 V 0.8 Load = 10kW + 40pF, fCLKOUT = 32MHz Output Load Reference Input Level Sine wave 0.5 Clock Output Multiply/Divide Range /4, /2, /1 (x2, max input frequency of 16MHz) ÷4 MHz V 11 mA 10||40 kI||pF VP-P x2 — ADC ADC Differential Nonlinearity AGC enabled, 3-bit output Q0.1 LSB ADC Integral Nonlinearity AGC enabled, 3-bit output Q0.1 LSB Note 1: MAX2769B is production tested at TA = +25NC and +85NC. All min/max specifications are guaranteed by design and characterization from -40NC to +85NC, unless otherwise noted. Default register settings are not production tested or guaranteed. User must program the registers upon power-up. Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically disabled and LNA2 becomes active. PLL is in an integer-N mode with fCOMP = fTCXO/16 = 1.023MHz and ICP = 0.5mA. The complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz. Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only. Note 3: The LNA output connects to the mixer input without a SAW filter between them. Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm/ tone. Passive pole at the mixer output is programmed to be 13MHz. Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm per tone. ����������������������������������������������������������������� Maxim Integrated Products 4 *The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet. MAX2769B Universal GPS Receiver Typical Operating Characteristics (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) CASCADED GAIN AND NOISE FIGURE vs. TEMPERATURE TA = +85°C AGC GAIN 1.0 105 NOISE FIGURE 100 0.5 95 40 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 10 35 60 85 0 -10 |S12| -20 -30 -40 -50 90 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 LNA1 GAIN AND NOISE FIGURE vs. LNA1 BIAS DIGITAL CODE LNA1 GAIN AND NOISE FIGURE vs. TEMPERATURE LNA1 INPUT 1dB COMPRESSION POINT vs. LNA1 BIAS DIGITAL CODE GAIN 15 0.8 NOISE FIGURE 0.4 10 0.2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LNA BIAS DIGITAL CODE (DECIMAL) 19.6 19.4 19.2 1.0 19.0 0.8 18.8 0.6 18.6 18.4 0.4 5 0 LNA BIAS = 1000 1.2 20 1.0 MAX2769B toc05 1.4 25 NOISE FIGURE GAIN 18.2 0.2 18.0 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 17.8 LNA1 GAIN (dB) MAX2769B toc04 LNA1 INPUT 1dB COMPRESSION POINT (dBm) FREQUENCY (GHz) 1.2 0.6 -15 10 TEMPERATURE (°C) LNA1 GAIN (dB) NOISE FIGURE (dB) 1.4 -40 20 PGA GAIN CODE (DECIMAL FORMAT) 1.6 NOISE FIGURE (dB) 110 |S21| 5.0 MAX2769B toc06 60 1.5 LNA1 |S21| AND |S12| (dB) 80 30 CASCADED GAIN TA = +25°C 40 120 115 NOISE FIGURE (dB) 100 TA = -40°C MAX2769B toc02 2.0 MAX2769B toc01 CASCADED RECEIVER GAIN (dB) 120 LNA1 |S21| AND |S12| vs. FREQUENCY MAX2769B toc03 CASCADED RECEIVER GAIN vs. PGA GAIN CODE 2.5 0 -2.5 -5.0 -7.5 -10.0 -12.5 -15.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LNA BIAS DIGITAL CODE (DECIMAL) ����������������������������������������������������������������� Maxim Integrated Products 5 MAX2769B Universal GPS Receiver Typical Operating Characteristics (continued) (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) -20 -30 13.2 1.4 1.2 13.0 1.0 12.8 0.8 NOISE FIGURE 0.6 12.6 GAIN 0.4 -40 12.4 0.2 -50 0 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 -40 -15 FREQUENCY (GHz) 10 35 85 60 -10 -20 -30 LNA2 -40 -50 12.2 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 TEMPERATURE (°C) FREQUENCY (GHz) MIXER INPUT REFERRED IP1dB vs. OFFSET FREQUENCY LNA OUTPUT RETURN LOSS vs. FREQUENCY -5 LNA1 -10 -15 LNA2 0 MIXER INPUT REFERRED IP1dB (dB) MAX2769B toc10 0 PGA GAIN = 32dB -10 -20 -30 PGA GAIN = 51dB -40 -50 -60 -70 -80 PRF = -100dBm -90 -20 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 FREQUENCY (GHz) MAX2769B toc09 LNA1 13.4 1.6 MAX2769B toc11 |S12| 0 13.6 LNA2 GAIN (dB) 0 -10 1.8 NOISE FIGURE (dB) 10 LNA OUTPUT RETURN LOSS (dB) LNA2 |S21| AND |S12| (dB) 20 LNA BIAS = 10 LNA INPUT RETURN LOSS (dB) |S21| MAX2769B toc08 2.0 MAX2769B toc07 30 LNA INPUT RETURN LOSS vs. FREQUENCY LNA2 GAIN AND NOISE FIGURE vs. TEMPERATURE LNA2 |S21| AND |S12| vs. FREQUENCY 0 50 100 150 200 250 300 OFFSET FREQUENCY (MHz) ����������������������������������������������������������������� Maxim Integrated Products 6 MAX2769B Universal GPS Receiver Typical Operating Characteristics (continued) (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) MIXER INPUT REFERRED NOISE FIGURE vs. PGA GAIN 1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY MAX2769B toc12a -10 -15 -20 825 850 875 900 950 1800 1850 925 JAMMER FREQUENCY (MHz) 0 -10 -20 -30 -40 2000 2050 10 8 5 15 25 35 45 55 65 PGA GAIN (dB) FBW = 00b -10 -20 -30 -40 -50 -50 12 6 2100 0 MAGNITUDE (dB) MAGNITUDE (dB) 10 MAX2769B toc14 FBW = 00b 1950 14 MIXER INPUT REFERRED GAIN vs. PGA GAIN CODE 5TH-ORDER POLYPHASE FILTER MAGNITUDE RESPONSE vs. BASEBAND FREQUENCY 3RD-ORDER POLYPHASE FILTER MAGNITUDE RESPONSE vs. BASEBAND FREQUENCY 10 1900 MAX2769B toc15 800 100 MIXER INPUT REFERRED GAIN (dB) JAMMER POWER (dBm) -5 MAX2769B toc13 MIXER INPUT REFERRED NOISE FIGURE (dB) 16 80 TA = -40°C MAX2769B toc16 0 MAX2769B toc12b TA = +25°C 60 TA = +85°C 40 -60 -60 -70 1 2 3 4 5 6 7 8 BASEBAND FREQUENCY (MHz) 9 10 20 1 2 3 4 5 6 7 8 BASEBAND FREQUENCY (MHz) 9 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 PGA GAIN CODE (DECIMAL FORMAT) ����������������������������������������������������������������� Maxim Integrated Products 7 MAX2769B Universal GPS Receiver Typical Operating Characteristics (continued) (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) -20 -30 -40 -50 -10 -20 -30 -40 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) 5TH-ORDER POLYPHASE FILTER vs. BASEBAND FREQUENCY (FBW = 10) -10 -20 -30 -40 -50 4 6 8 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) -40 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) FREQUENCY (MHz) 2-BIT ADC TRANSFER CURVE 3-BIT ADC TRANSFER CURVE 2.5 2.0 1.5 1.0 0.5 7 6 5 4 3 2 1 0 -60 -30 10 12 14 16 18 20 3.0 CODE (DECIMAL VALUE) 0 2 3.5 MAX2769B toc20 10 -20 -60 0 CODE (DECIMAL VALUE) 2 -10 -50 -60 0 MAX2769B toc19 0 -50 -60 FREQUENCY RESPONSE (dB) MAX2769B toc18 0 10 MAX2769B toc22 -10 3RD-ORDER POLYPHASE FILTER vs. BASEBAND FREQUENCY (FBW = 10) MAX2769B toc21 FREQUENCY RESPONSE (dB) 0 10 FREQUENCY RESPONSE (dB) MAX2769B toc17 10 5TH-ORDER POLYPHASE FILTER vs. BASEBAND FREQUENCY (FBW = 01) FREQUENCY RESPONSE (dB) 3RD-ORDER POLYPHASE FILTER vs. BASEBAND FREQUENCY (FBW = 01) 0 -0.5 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL VOLTAGE (V) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL VOLTAGE (V) ����������������������������������������������������������������� Maxim Integrated Products 8 MAX2769B Universal GPS Receiver Typical Operating Characteristics (continued) (MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) CRYSTAL OSCILLATOR FREQUENCY vs. DIGITAL TUNING CODE DIGITAL OUTPUT DIFFERENTIAL LOGIC MAX2769B toc24 16,368.10 CLK 2V/div CLK 1V/div SIGN DATA 2V/div SIGN+ 1V/div MAGNITUDE DATA 2V/div SIGN1V/div CRYSTAL OSCILLATOR FREQUENCY (kHz) MAX2769B toc23 16,368.05 MAX2769B toc25 DIGITAL OUTPUT CMOS LOGIC TA = +25°C 16,368.00 TA = -40°C 16,367.95 TA = +85°C 16,367.90 16,367.85 20ns/div 0 40ns/div 4 8 12 16 20 24 28 32 CRYSTAL OSCILLATOR FREQUENCY VARIATION vs. TEMPERATURE 6 4 2 0 -2 -4 -6 -8 MAX2769B toc27 8 CLOCK OUTPUT DRIVER WITH 40pF LOAD MAX2769B toc28 2.0 TEMPERATURE SENSOR VOLTAGE (V) 10 TEMPERATURE SENSOR VOLTAGE vs. TEMPERATURE MAX2769B toc26 CRYSTAL OSCILLATOR FREQUENCY VARIATION (ppm) DIGITAL TUNING CODE (DECIMAL) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -10 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 20ns/div TEMPERATURE (°C) ����������������������������������������������������������������� Maxim Integrated Products 9 MAX2769B Universal GPS Receiver 21 20 BASEBAND CLOCK 19 18 17 C11 C10 XTAL CLKOUT Q1 C7 Q0 I0 I1 TOP VIEW VCC_ADC BASEBAND OUTPUT REFERENCE INPUT Typical Application Circuit 16 14 N.C. ADC PLL VCO 90 26 27 + 2 LNAOUT ANTFLAG 1 C5 CPOUT 3 4 C2 VCC_VCO C4 LNA1 28 VCC_CP 5 6 C3 10 CS 9 SCLK 8 SDATA SERIAL INPUT 7 SHDN LNA1 LNA2 11 3-WIRE INTERFACE C0 VCCD C1 FILTER 25 LD PGM 12 0 LNA2 24 MIXIN C9 13 MAX2769B VCC_RF IDLE 23 ANTBIAS VCC_IF ADC N.C. 22 C8 C6 15 C13 ACTIVE ANTENNA BIAS C12 Table 1. Component List DESIGNATION QUANTITY C0, C9 2 0.47nF AC-coupling capacitors DESCRIPTION C1 1 27pF PLL loop filter capacitor C2 1 0.47nF PLL loop filter capacitor C3–C8 6 0.1FF supply voltage bypass capacitor C10, C11 2 10nF AC-coupling capacitor C12 1 0.47nF AC-coupling capacitor C13 1 0.1nF supply voltage bypass capacitor R1 1 20kI PLL loop filter resistor ���������������������������������������������������������������� Maxim Integrated Products 10 MAX2769B Universal GPS Receiver I1 I0 VCC_ADC Q0 Q1 CLKOUT XTAL Pin Configuration 21 20 19 18 17 16 15 TOP VIEW N.C. 22 14 VCCD VCC_IF 23 13 VCC_CP IDLE 24 12 CPOUT 11 VCC_VCO 10 CS LNA2 25 MAX2769B PGM 26 LNA1 27 EP ANTFLAG LNAOUT ANTBIAS 4 5 6 7 SHDN 3 LD 2 MIXIN 1 VCC_RF + N.C. 28 9 SCLK 8 SDATA TQFN Pin Description PIN NAME FUNCTION 1 ANTFLAG Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the ANTBIAS pin. 2 LNAOUT LNA Output. The LNA output is internally matched to 50I. 3 ANTBIAS Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna. 4 VCC_RF 5 MIXIN 6 LD 7 8 SHDN SDATA 9 SCLK RF Section Supply Voltage. Bypass to ground with 100nF and 100pF capacitors in parallel as close as possible to the pin. Mixer Input. The mixer input is internally matched to 50I. Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked. Operation Control Logic Input. A logic-low shuts off the entire device. Data Digital Input of 3-Wire Serial Interface Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising edge of the SCLK. ���������������������������������������������������������������� Maxim Integrated Products 11 MAX2769B Universal GPS Receiver Pin Description (continued) PIN NAME FUNCTION Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high when the loading action is completed. 10 CS 11 VCC_VCO 12 CPOUT Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and C (see the Typical Application Circuit). 13 VCC_CP PLL Charge-Pump Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin. 14 VCCD Digital Circuitry Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin. 15 XTAL XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used. 16 CLKOUT 17 Q1 18 Q0 19 VCC_ADC 20 I0 21 I1 VCO Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin. Reference Clock Output Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or analog differential voltage output. ADC Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin. I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or analog differential voltage output. 22 N.C. 23 VCC_IF No Connection. Leave this pin unconnected. 24 IDLE Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active, and all other blocks are off. 25 LNA2 LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50I. 26 PGM Logic Input. Connect to ground to use the serial interface. A logic-high allows programming to 8 hard-coded by device states connecting SDATA, CS, and SCLK to supply or ground according to Table 3. 27 LNA1 LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50I (see the Typical Application Circuit). 28 N.C. No connection. Leave this pin open. — EP IF Section Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin. Exposed Pad. Ultra-low-inductance connection to ground. Place several vias to the PCB ground plane. ���������������������������������������������������������������� Maxim Integrated Products 12 MAX2769B Universal GPS Receiver Detailed Description Integrated Active Antenna Sensor The MAX2769B includes a low-dropout switch to bias an external active antenna. To activate the antenna switch output, set ANTEN in the Configuration 1 register to logic 1. This closes the switch that connects the antenna bias pin to VCC_RF to achieve a low 200mV dropout for a 20mA load current. A logic-low in ANTEN disables the antenna bias. The active antenna circuit also features short-circuit protection to prevent the output from being shorted to ground. 16 BASEBAND CLOCK CLKOUT 10nF MAX2769B 15 XTAL 23pF Low-Noise Amplifier (LNA) The MAX2769B integrates two low-noise amplifiers. LNA1 is typically used with a passive antenna. This LNA requires an AC-coupling capacitor. In the default mode, the bias current is set to 4mA, the typical noise figure and IIP3 are approximately 0.8dB and -1.1dBm, respectively. LNA2 is typically used with an active antenna. The LNA2 is internally matched to 50. and requires a DC-blocking capacitor. Bits LNAMODE in the Configuration 1 register control the modes of the two LNAs. See Table 6 and Table 7 for the LNA mode settings. Mixer The MAX2769B includes a quadrature mixer to output low-IF or zero IF I and Q signals. The quadrature mixer is internally matched to 50I and requires a low-side LO injection. The output of the LNA and the input of the mixer are brought off-chip to facilitate the use of a SAW filter. Programmable Gain Amplifier (PGA) The MAX2769B integrates a baseband programmable gain amplifier that provides 59dB of gain control range. The PGA gain can be programmed through the serial interface by setting bits GAININ in the Configuration 3 register. Set bits 12 and 11 (AGCMODE) in the Configuration 2 register to 10 to control the gain of the PGA directly from the 3-wire interface. Automatic Gain Control (AGC) The MAX2769B provides a control loop that automatically programs PGA gain to provide the ADC with an input power that optimally fills the converter and establishes a desired magnitude bit density at its output. An algorithm Figure 1. Schematic of the Crystal Oscillator in the MAX2679B EV Kit operates by counting the number of magnitude bits over 512 ADC clock cycles and comparing the magnitude bit count to the reference value provided through a control word (GAINREF). The desired magnitude bit density is expressed as a value of GAINREF in a decimal format divided by the counter length of 512. For example, to achieve the magnitude bit density of 33%, which is optimal for a 2-bit converter, program the GAINREF to 170, so that 170/512 = 33%. Baseband Filter The baseband filter of the receiver can be programmed to be a lowpass filter or a complex bandpass filter. The lowpass filter can be configured as a 3rd-order Butterworth filter for a reduced group delay by setting bit F3OR5 in the Configuration 1 register to be 1 or a 5th-order Butterworth filter for a steeper out-of-band rejection by setting the same bit to be 0. The two-sided 3dB corner bandwidth can be selected to be 2.5MHz, 4.2MHz, 9.66MHz, or by programming bits FBW in the Configuration 1 register. When the complex filter is enabled by changing bit FCENX in the Configuration 1 register to 1, the lowpass filter becomes a bandpass filter and the center frequency can be programmed by bits FCEN and FCENMSB in the Configuration 1 register. ���������������������������������������������������������������� Maxim Integrated Products 13 MAX2769B Universal GPS Receiver Table 2. Output Data Format SIGN/MAGNITUDE UNSIGNED BINARY TWO’S COMPLEMENT BINARY INTEGER VALUE 1b 2b 3b 1b 2b 3b 1b 2b 3b 7 0 01 011 1 11 111 0 01 011 5 0 01 010 1 11 110 0 01 010 3 0 00 001 1 10 101 0 00 001 1 0 00 000 1 10 110 0 00 000 -1 1 10 100 0 01 011 1 11 111 -3 1 10 101 0 01 010 1 11 110 -5 1 11 110 0 00 001 1 10 101 -7 1 11 111 0 00 000 1 10 100 Synthesizer The MAX2769B integrates a 20-bit sigma-delta fractionalN synthesizer allowing the device to tune to a required VCO frequency with an accuracy of approximately Q30Hz. The synthesizer includes a 10-bit reference divider with a divisor range programmable from 1 to 1023, a 15-bit integer portion main divider with a divisor range programmable from 36 to 32767, and also a 20-bit fractional portion main divider. The reference divider is programmable by bits RDIV in the PLL integer division ratio register (see Table 11), and can accommodate reference frequencies from 8MHz to 32MHz. The reference divider needs to be set so the comparison frequency falls between 0.05MHz to 32MHz. The PLL loop filter is the only external block of the synthesizer. A typical PLL filter is a classic C-R-C network at the charge-pump output. The charge-pump output sink and source current is 0.5mA by default, and the LO tuning gain is 57MHz/V. As an example, see the Typical Application Circuit for the recommended loopfilter component values for fCOMP = 1.023MHz and loop bandwidth = 50kHz. The desired integer and fractional divider ratios can be calculated by dividing the LO frequency (fLO) by fCOMP. fCOMP can be calculated by dividing the TCXO frequency (fTCXO) by the reference division ratio (RDIV). For example, let the TCXO frequency be 20MHz, RDIV be 1, and the nominal LO frequency be 1575.42MHz. The following method can be used when calculating divider ratios supporting various reference and comparison frequencies: f 20MHz Comparison Frequency = TCXO = = 20MHz RDIV 1 f 1575.42MHz LO Frequency Divider = LO = = 78.771 fCOMP 20MHz Integer Divider = 78(d) = 000 000 0100 1110 (binary) Fractional Divider = 0.771 x 220 = 808452 (decimal) = 1100 0101 0110 0000 0100 In the fractional mode, the synthesizer should not be operated with integer division ratios greater than 251. Crystal Oscillator The MAX2769B includes an on-chip crystal oscillator. A parallel mode crystal is required when the crystal oscillator is being used. It is recommended that an AC-coupling capacitor be used in series with the crystal and the XTAL pin to optimize the desired load capacitance and to center the crystal-oscillator frequency. Take the parasitic loss of interconnect traces on the PCB into account when optimizing the load capacitance. For example, the MAX2769B EV kit utilizes a 16.368MHz crystal that is designed for a 12pF load capacitance. A series capacitor of 23pF is used to center the crystal oscillator frequency, see Figure 1. In addition, the 5-bit serial-interface word, XTALCAP in the PLL Configuration register, can be used to vary the crystal-oscillator frequency electronically. The range of the electronic adjustment depends on how much the chosen crystal frequency can be pulled by the varying capacitor. The frequency of the crystal oscillator used on the MAX2769B EV kit has a range of approximately 200Hz. The MAX2769B provides a reference clock output. The frequency of the clock can be adjusted to crystal-oscillator frequency, a quarter of the oscillator frequency, a half of the oscillator frequency (fXTAL P 16MHz), or twice the oscillator frequency, by programming bits REFDIV in the PLL Configuration register. ���������������������������������������������������������������� Maxim Integrated Products 14 MAX2769B Universal GPS Receiver ADC data mapping. The variable T = 1 designates the location of the magnitude threshold for the 2-bit case. The MAX2769B features an on-chip ADC to digitize the downconverted GPS signal. The maximum sampling rate of the ADC is approximately 50Msps. The sampled output is provided in a 2-bit format (1-bit magnitude and 1-bit sign) by default and also can be configured as a 1-bit or 2-bit in both I and Q channels, or 1-bit, 2-bit, or 3-bit in the I channel only. The ADC supports the digital outputs in three different formats: the unsigned binary, the sign and magnitude, or the two’s complement format by setting bits FORMAT in Configuration register 2. MSB bits are output at I1 or Q1 pins and LSB bits are output at I0 or Q0 pins, for I or Q channel, respectively. In the case of 3-bit, output data format is selected in the I channel only, the MSB is output at I1, the second bit is at I0, and the LSB is at Q1. ADC Fractional Clock Divider A 12-bit fractional clock divider is located in the clock path prior to the ADC and can be used to generate the ADC clock that is a fraction of the reference input clock. In a fractional divider mode, the instantaneous division ratio alternates between integer division ratios to achieve the required fraction. For example, if the fractional output clock is 4.5 times slower than the input clock, an average division ratio of 4.5 is achieved through an equal series of alternating divide-by-4 and divide-by-5 periods. The fractional division ratio is given by: fOUT/fIN = LCOUNT/(4096 - MCOUNT + LCOUNT) where LCOUNT and MCOUNT are the 12-bit counter values programmed through the serial interface. Figure 2 illustrates the ADC quantization levels for 2-bit and 3-bit cases and also describes the sign/magnitude 011 01 010 001 00 000 -7 -6 -5 -4 -2 -3 -1 100 101 10 1 2 3 4 5 6 7 T=1 110 11 111 Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases ���������������������������������������������������������������� Maxim Integrated Products 15 MAX2769B Universal GPS Receiver DSP Interface data, and so on. In this case, the serial clock must be at least twice as fast as the ADC clock. If a 4-bit serialization of bit0, bit1, bit2, and bit3 is chosen, the serial clock must be at least four times faster than the ADC clock. GPS data is output from the ADC as the four logic signals (bit0, bit1, bit2, and bit3) that represent sign/magnitude, unsigned binary, or two’s complement binary data in the I (bit0 and bit1) and Q (bit2 and bit3) channels. The resolution of the ADC can be set up to 3 bits per channel. For example, the 2-bit I and Q data in sign/magnitude format is mapped as follows: bit0 = ISIGN, bit1 = IMAG, bit2 = QSIGN, and bit3 = QMAG. The data can be serialized in 16-bit segments of bit0, followed by bit1, bit2, and bit3. The number of bits to be serialized is controlled by the bits STRMBITS in the Configuration 3 register. This selects between bit0; bit0 and bit1; bit0 and bit2; and bit0, bit1, bit2, and bit3 cases. If only bit0 is serialized, the data stream consists of bit0 data only. If a serialization of bit0 and bit1 (or bit2) is selected, the stream data pattern consists of 16 bits of bit0 data followed by 16 bits of bit1 (or bit2) data, which, in turn, is followed by 16 bits of bit0 The ADC data is loaded in parallel into four holding registers that correspond to four ADC outputs. Holding registers are 16 bits long and are clocked by the ADC clock. At the end of the 16-bit ADC cycle, the data is transferred into four shift registers and shifted serially to the output during the next 16-bit ADC cycle. Shift registers are clocked by a serial clock that must be chosen fast enough so that all data is shifted out before the next set of data is loaded from the ADC. An all-zero pattern follows the data after all valid ADC data are streamed to the output. A DATASYNC signal is used to signal the beginning of each valid 16-bit data slice. In addition, there is a TIME_SYNC signal that is output every 128 to 16,384 cycles of the ADC clock. STRM_EN PIN 21 I OUTPUT DRIVER ADC Q REFDIV<1:0> DATA_SYNC TIME_SYNC STRM_EN L_CNT<11:0> M_CNT<11:0> CLK_IN THROUGH /2 /4 x2 DATA_OUT CLK_SER STRM_EN STRM_START STRM_STOP STRM_COUNT<2:0> DIEID<1:0> STRM_BITS<1:0> FRM_COUNT<27:0> STAMP_EN DAT_SYNCEN TIME_SYNCEN STRM_RST CLK_ADC CLK_SER CONTROL SIGNALS FROM 3-WIRE INTERFACE REF/XTAL PIN 15 PIN 17 PIN 18 BIT 0 BIT 1 BIT 2 BIT 3 ADCCLK_SEL PIN 20 CLK_OUT FRCLK_SEL SERCLK_SEL Figure 3. DSP Interface Top-Level Connectivity and Control Signals ���������������������������������������������������������������� Maxim Integrated Products 16 MAX2769B Universal GPS Receiver Preconfigured Device States When a serial interface is not available, the device can be used in preconfigured states that don’t require programming through the serial interface. Connecting the PGM pin to logic-high and SCLK, SDATA, and CS pins to either logic-high or low sets the device in one of the preconfigured states according to Table 3. Power-On Reset (POR) The MAX2769B incorporates power-on reset circuitry to ensure that register settings are loaded upon power-up. To ensure proper operation, the rising edge of PGM must occur no sooner than when VCC_ reaches 90% of its final nominal value; see Figure 4 for details. Serial Interface, Address, and Bit Assignments A serial interface is used to program the MAX2769B for configuring the different operating modes. The serial interface is controlled by three signals: SCLK (serial clock), CS (chip select), and SDATA (serial data). The control of the PLL, AGC, test, and block selection is performed through the serial-interface bus from the baseband controller. A 32-bit word, with the MSB (D27) being sent first, is clocked into a serial shift register when the chip-select signal is asserted low. The timing of the interface signals is shown in Figure 5 and Table 4 along with typical values for setup and hold time requirements. Table 3. Preconfigured Device States REFERENCE FREQUENCY (MHz) REFERENCE DIVISION RATIO MAIN DIVISION RATIO I AND Q OR I ONLY NUMBER OF IQ BITS I AND Q LOGIC LEVEL IF CENTER FREQUENCY (MHz) IF FILTER BW (MHz) IF FILTER ORDER SCLK DATA CS 3-WIRE CONTROL PINS DEVICE STATE DEVICE ELECTRICAL CHARACTERISTICS 0 16.368 16 1536 I 1 Differential 4.092 2.5 5th 0 0 0 1 16.368 16 1536 I 1 Differential 4.092 2.5 3rd 0 0 1 2 16.368 16 1536 I 2 CMOS 4.092 2.5 5th 0 1 0 3 32.736 32 1536 I 2 CMOS 4.092 2.5 5th 0 1 1 4 19.2 96 7857 I 2 CMOS 4.092 2.5 5th 1 0 0 5 27.456 26 1488 I 3 CMOS 4.092 4.2 5th 1 0 1 6 16.368 16 1536 I 3 CMOS 4.092 4.2 5th 1 1 0 7 27.456 26 1508 I 3 CMOS 9.27075 9.66 5th 1 1 1 VCC_ 100% 90% 0% TIME (s) PGM PGM = 0 PGM RISING EDGE ANYTIME AFTER VCC_ HAS REACHED 90% OF ITS NOMINAL VALUE. TIME (s) Figure 4. VCC_ Power-On Reset ���������������������������������������������������������������� Maxim Integrated Products 17 MAX2769B Universal GPS Receiver CS tCSH tCSS tCSW SCLK tDH tDS tCH tCL DATA MSB SDATA DATA LSB ADDR MSB ADDR LSB Figure 5. 3-Wire Timing Diagram Table 4. Serial-Interface Timing Requirements SYMBOL tCSS PARAMETER TYP VALUE UNITS Falling edge of CS to rising edge of the first SCLK time. Data to serial-clock setup time. 10 ns tDS 10 ns tDH Data to clock hold time. 10 ns tCH Serial clock pulse-width high. 25 ns tCL Clock pulse-width low. 25 ns tCSH Last SCLK rising edge to rising edge of CS. 10 ns tCSW CS high pulse width. 1 clock Table 5. Default Register Settings Overview REGISTER NAME ADDRESS (A3:A0) CONF1 0000 Configures RX and IF sections, bias settings for individual blocks. CONF2 0001 Configures AGC and output sections. CONF3 0010 Configures support and test functions for IF filter and AGC. PLLCONF 0011 PLL, VCO, and CLK settings. DIV 0100 PLL main and reference division ratios, other controls. FDIV 0101 PLL fractional division ratio, other controls. STRM 0110 DSP interface number of frames to stream. DATA CLK 0111 Fractional clock-divider values. TEST1 1000 Reserved for test mode. TEST2 1001 Reserved for test mode. ���������������������������������������������������������������� Maxim Integrated Products 18 MAX2769B Universal GPS Receiver Table 6. Default Register Settings REGISTER ADDRESS NAME (A3:A0) POWER-ON RESET, PGM = 0 (hex) 0 1 2 3 4 PRECONFIGURED DEVICE STATE, PGM = 1 (hex) 5 6 7 CONF1 0000 A2919A3 A2919A3 A2919A3 A2919A7 A2919A3 A2919A3 A293573 A293573 A29B26B CONF2 0001 055028C 055121C 055028C 055121C 055028C 055028C 855030C 855030C 855030C CONF3 0010 EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC PLLCONF 0011 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 DIV 0100 0C00080 0C00080 0C00080 0C00080 0C00100 3D62300 0BA00D0 0C00080 0BC80D0 FDIV 0101 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070 STRM 0110 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000 CLK 0111 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 TEST1 1000 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 TEST2 1001 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 7CC0403 8000070 Detailed Register Definitions Table 7. Configuration 1 (Address: 0000) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) CHIPEN 27 1 Chip enable. Set 1 to enable the device and 0 to disable the entire device except the serial bus. Idle enable. Set 1 to put the chip in the idle mode and 0 for operating mode. DESCRIPTION IDLE 26 0 RESERVED 25:22 1000 — RESERVED 21:20 10 — RESERVED 19:18 10 — RESERVED 17:16 01 MIXPOLE 15 0 — Mixer pole selection. Set 1 to program the passive filter pole at mixer output at 36MHz, or set 0 to program the pole at 13MHz. LNAMODE 14:13 00 LNA mode selection, D14:D13 = 00: LNA selection gated by the antenna bias circuit, 01: LNA2 is active; 10: LNA1 is active; 11: both LNA1 and LNA2 are off. MIXEN 12 1 Mixer enable. Set 1 to enable the mixer and 0 to shut down the mixer. ANTEN 11 1 Antenna bias enable. Set 1 to enable the antenna bias and 0 to shut down the antenna bias. FCEN 10:5 001101 FBW 4:3 00 IF filter center bandwidth selection. D4:D3 = 00: 2.5MHz; 10: 4.2MHz; 01: 9.66MHz; 11: Reserved. F3OR5 2 0 Filter order selection. Set 0 to select the 5th-order Butterworth filter. Set 1 to select the 3rdorder Butterworth filter. FCENX 1 1 Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 0 to select lowpass filter mode. FGAIN 0 1 IF filter gain setting. Set 0 to reduce the filter gain by 6dB. IF center frequency programming. Default for fCENTER = 3.092MHz, BW = 2.5MHz. The MSB of FCEN is located in Register Test Mode 2 (Table 16). 001101 = 3.092MHz, 001011 = 4.092MHz, 010011 = 10.0MHz ���������������������������������������������������������������� Maxim Integrated Products 19 MAX2769B Universal GPS Receiver Table 8. Configuration 2 (Address: 0001) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) IQEN 27 0 GAINREF 26:15 170d RESERVED 14:13 00 Reserved. AGCMODE 12:11 00 AGC mode control. Set D12:D11 = 00: independent I and Q; 01: reserved; 10: gain is set directly from the serial interface by GAININ; 11: reserved. FORMAT 10:9 01 Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X: two’s complement binary. BITS 8:6 010 Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: reserved; 010: 2 bits; 011: reserved, 100: 3 bits. DRVCFG 5:4 00 Output driver configuration. Set D5:D4 = 00: CMOS logic, 01: reserved; 1X: analog outputs. RESERVED 3 1 — RESERVED 2 0 — DIEID 1:0 00 Identifies a version of the IC. DESCRIPTION I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I channel only. AGC gain reference value expressed by the number of MSB counts (magnitude bit density). 10101010 = 234 magnitude bit density reference, 1010100 = 84 magnitude bit density reference, 100111010 = 314 magnitude bit density reference. Table 9. Configuration 3 (Address: 0010) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) DESCRIPTION GAININ 27:22 111010 PGA gain value programming from the serial interface in steps of dB per LSB. 000000 = PGA gain set to 0dB, 101011 = 42dB, 101100 = 43dB, 101110 = 45dB, 111010 = 57dB, 111111 = 62dB. RESERVED 21 1 — HILOADEN RESERVED 20 0 Set 1 to enable the output driver to drive high loads. RESERVED 19 1 — 18 1 — 17 1 — 16 1 — FHIPEN 15 1 Highpass coupling enable. Set 1 to enable the highpass coupling between the filter and PGA, or 0 to disable the coupling. RESERVED 14 1 — RESERVED 13 1 — RESERVED 12 0 — STRMEN 11 0 DSP interface for serial streaming of data enable. This bit configures the IC such that the DSP interface is inserted in the signal path. Set 1 to enable the interface or 0 to disable the interface. RESERVED RESERVED ���������������������������������������������������������������� Maxim Integrated Products 20 MAX2769B Universal GPS Receiver Table 9. Configuration 3 (Address: 0010) (continued) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) DESCRIPTION STRMSTART 10 0 The positive edge of this command enables data streaming to the output. It also enables clock, data sync, and frame sync outputs. STRMSTOP 9 0 The positive edge of this command disables data streaming to the output. It also disables clock, data sync, and frame sync outputs. RESERVED 8:6 111 — STRMBITS 5:4 01 Number of bits streamed. D5:D4 = 00: reserved; 01: 1 MSB, 1 LSB; 10: reserved, Q MSB; 11: 1 MSB, 1 LSB, Q MSB, Q LSB. STAMPEN 3 1 The signal enables the insertion of the frame number at the beginning of each frame. If disabled, only the ADC data is streamed to the output. TIMESYNCEN 2 1 This signal enables the output of the time sync pulses at all times when streaming is enabled by the STRMEN command. Otherwise, the time sync pulses are available only when data streaming is active at the output, for example, in the time intervals bound by the STRMSTART and STRMSTOP commands. DATSYNCEN 1 0 This control signal enables the sync pulses at the DATASYNC output. Each pulse is coincident with the beginning of the 16-bit data word that corresponds to a given output bit. STRMRST 0 0 This command resets all the counters irrespective of the timing within the stream cycle. Table 10. PLL Configuration (Address: 0011) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) RESERVED 27 1 — RESERVED 26 0 — DESCRIPTION RESERVED 25 0 — REFOUTEN 24 1 Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer. RESERVED 23 1 — REFDIV 22:21 11 Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2; 01: clock frequency = XTAL frequency/4; 10: clock frequency = XTAL frequency/2; 11: clock frequency = XTAL. IXTAL 20:19 01 Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: reserved; 01: buffer normal current; 10: reserved; 11: oscillator high current. RESERVED 18:14 10000 — LDMUX 13:10 0000 PLL lock-detect enable. ���������������������������������������������������������������� Maxim Integrated Products 21 MAX2769B Universal GPS Receiver Table 10. PLL Configuration (Address: 0011) (continued) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) DESCRIPTION ICP 9 0 Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA. PFDEN 8 0 Set 0 for normal operation or 1 to disable the PLL phase frequency detector. RESERVED 7 0 — RESERVED 6:4 000 — INT_PLL 3 1 PLL mode control. Set 1 to enable the integer-N PLL or 0 to enable the fractional-N PLL. PWRSAV 2 0 PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable. RESERVED 1 0 — RESERVED 0 0 — Table 11. PLL Integer Division Ratio (Address 0100) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) NDIV 27:13 1536d RDIV 12:3 16d PLL reference division ratio. RESERVED 2:0 000 — DESCRIPTION PLL integer division ratio. Table 12. PLL Division Ratio (Address 0101) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) FDIV 27:8 80000h RESERVED 7:0 DESCRIPTION PLL fractional divider ratio. 01110000 — Table 13. Reserved (Address 0110) DATA BIT LOCATION RESERVED 27:0 DEFAULT VALUE (PGM = 0) DESCRIPTION 8000000h — ���������������������������������������������������������������� Maxim Integrated Products 22 MAX2769B Universal GPS Receiver Table 14. Clock Fractional Division Ratio (Address 0111) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) L_CNT 27:16 256d Sets the value for the L counter. 000100000000 = 256 fractional clock divider, 100000000000 = 2048 fractional clock divider. M_CNT 15:4 1563d Sets the value for the M counter. 011000011011 = 1563 fractional clock divider, 100000000 = 2048 fractional clock divider. FCLKIN 3 0 Fractional clock divider. Set 1 to select the ADC clock to come from the fractional clock divider, or 0 to bypass the ADC clock from the fractional clock divider. ADCCLK 2 0 ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come from the reference divider/multiplier. RESERVED 1 1 — MODE 0 0 DSP interface mode selection. DESCRIPTION Table 15. Test Mode 1 (Address 1000) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) RESERVED 27:0 1E0F401 DESCRIPTION — Table 16. Test Mode 2 (Address 1001) DATA BIT LOCATION DEFAULT VALUE (PGM = 0) RESERVED 27:1 28C0402 FCENMSB 0 0 DESCRIPTION — When combined with FCEN, this bit represents the MSB of a 7-bit FCEN word. Applications Information The LNA and mixer inputs require careful consideration in matching to 50I lines. Proper supply bypassing, grounding, and layout are required for reliable performance from any RF circuit. Layout Issues The MAX2769B EV kit can be used as a starting point for layout. For best performance, take into consideration grounding and routing of RF, baseband, and powersupply PCB proper line. Make connections from vias to the ground plane as short as possible. On the highimpedance ports, keep traces short to minimize shunt capacitance. EV kit Gerber files can be requested at www.maxim-ic.com. Power-Supply Layout To minimize coupling between different sections of the IC, a star power-supply routing configuration with a large decoupling capacitor at a central VCC_ node is recommended. The VCC_ traces branch out from this node, each going to a separate VCC_ node in the circuit. Place a bypass capacitor as close as possible to each supply pin This arrangement provides local decoupling at each VCC_ pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Do not share the capacitor ground vias with any other branch. Refer to Maxim’s Wireless and RF Application Notes for more information. ���������������������������������������������������������������� Maxim Integrated Products 23 MAX2769B Universal GPS Receiver Chip Information Package Information Ordering Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PROCESS: SiGe BiCMOS PART TEMP RANGE PIN-PACKAGE MAX2769ETI/V+ -40NC to +85NC 28 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. /V denotes an automotive qualified part. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 TQFN-EP T2855+3 21-0140 90-0023 ���������������������������������������������������������������� Maxim Integrated Products 24 MAX2769B Universal GPS Receiver Revision History REVISION NUMBER REVISION DATE 0 5/11 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products 25 Maxim is a registered trademark of Maxim Integrated Products, Inc.