19-2646; Rev 1; 6/04 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP Features The MAX4747–MAX4750 low-voltage, quad single-pole single-throw (SPST)/dual single-pole/double-throw (SPDT) analog switches operate from a single +2V to +11V supply and handle rail-to-rail analog signals. These switches exhibit low leakage current (0.1nA) and consume less than 0.5nW (typ) of quiescent power, making them ideal for battery-powered applications. When powered from a +3V supply, these switches feature 50Ω (max) on-resistance (RON), with 3.5Ω (max) matching between channels and 9Ω (max) flatness over the specified signal range. The MAX4747 has four normally open (NO) switches, the MAX4748 has four normally closed (NC) switches, and the MAX4749 has two NO and two NC switches. The MAX4750 has two SPDT switches. These switches are available in 14-pin TSSOP, 16-pin thin QFN (4mm x 4mm), and 16-bump chip-scale packages (UCSP™). This tiny chip-scale package occupies a 2mm ✕ 2mm area and significantly reduces the required PC board area. ♦ 2mm ✕ 2mm UCSP ♦ Guaranteed On-Resistance (RON) 25Ω (max) at +5V 50Ω (max) at +3V ♦ On-Resistance Matching 3Ω (max) at +5V 3.5Ω (max) at +3V ♦ Guaranteed <0.1nA Leakage Current at TA = +25°C ♦ Single-Supply Operation from +2.0V to +11V ♦ TTL/CMOS-Logic Compatible ♦ -84dB Crosstalk (1MHz) ♦ -72dB Off-Isolation (1MHz) ♦ Low Power Consumption: 0.5nW (typ) ♦ Rail-to-Rail Signal Handling Applications Battery-Powered Systems Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems Cell Phones Communications Circuits Glucose Meters PDAs Ordering Information MAX4747EUD TEMP RANGE -40°C to +85°C MAX4747ETE -40°C to +85°C PIN-/BUMPPACKAGE 14 TSSOP 16 Thin QFN MAX4747EBE-T -40°C to +85°C 16 UCSP-16 PART TOP MARK — 4747 — Ordering Information continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc. Pin Configurations/Truth Tables V+ N.C. IN1 TOP VIEW (BUMPS SIDE DOWN) NO1 TOP VIEW 16 15 14 13 MAX4747 COM1 1 12 IN4 NO2 2 11 NO4 4 IN3 5 6 7 8 N.C. IN2 MAX4747ETE NO3 3 GND COM2 THIN QFN 10 COM4 9 COM3 NO1 1 14 V+ COM1 2 13 IN1 NO2 3 12 IN4 COM2 4 10 COM4 IN3 6 9 COM3 8 NO3 GND 7 2 3 4 COM1 NO2 COM2 IN2 NO1 V+ A IN3 B 11 NO4 IN2 5 1 IN1 GND NO3 COM4 COM3 C IN4 NO4 D TSSOP UCSP INPUT LOW SWITCH STATE OFF HIGH ON Pin Configurations/Truth Tables continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX4747–MAX4750 General Description MAX4747–MAX4750 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND) V+ ...........................................................................-0.3V to +12V IN_, COM_, NO_, NC_ (Note 1)....................-0.3V to (V+ + 0.3V) Continuous Current (any pin) ...........................................±10mA Peak Current (any pin, pulsed at 1ms, 10% duty cycle) ...±20mA Continuous Power Dissipation (TA = +70°C) 14-Pin TSSOP (derate 6.3mW/°C above +70°C) .........500mW 16-Bump UCSP (derate 8.3mW/°C above +70°C) ......659mW 16-Pin Thin QFN (derate 16.9mW/°C above +70°C) .....1349mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Bump Temperature (soldering) Infrared (15s) ...............................................................+220°C Vapor Phase (60s) .......................................................+215°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Signals on IN_, NO_, NC_, or COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—Single +3V Supply (V+ = +3V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS V+ V ANALOG SWITCH Analog Signal Range VCOM_, VNO_, VNC_ 0 +25°C On-Resistance On-Resistance Matching Between Channels (Notes 5, 6) RON V+ = +2.7V, ICOM_ = 5mA, VNO_ or VNC_ = +1.5V ∆RON V+ = +2.7V, ICOM_ = 5mA, VNO_ or VNC_ = +1.5V 17 TMIN to TMAX 50 60 +25°C 0.2 TMIN to TMAX 3.5 4.5 +25°C 2.7 RFLAT(ON) V+ = +2.7V, ICOM_ = 5mA, VNO_ or VNC_ = +1V, +1.5V, +2V -0.1 +0.1 INO_(OFF), INC_(OFF) V+ = +3.6V, VCOM_ = +0.3V, +3V, VNO_ or VNC_ = +3V, +0.3V +25°C NO_ or NC_ Off-Leakage Current (Note 8) TMIN to TMAX -2 +2 V+ = +3.6V, ICOM_(OFF) VCOM_ = +0.3V, +3V, VNO_ or VNC_ = +3V, +0.3V +25°C -0.1 +0.1 COM_ Off-Leakage Current (Note 8) TMIN to TMAX -2 +2 +25°C -0.2 +0.2 TMIN to TMAX -4 +4 COM_ On-Leakage Current (Note 8) 2 ICOM_(ON) V+ = +3.6V, VCOM_ = +0.3V, +3.0V, VNO_ or VNC_ = +0.3V, +3V, or floating Ω 9 On-Resistance Flatness (Note 7) TMIN to TMAX Ω 11 Ω nA nA nA _______________________________________________________________________________________ 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP (V+ = +3V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX 57 150 UNITS DYNAMIC +25°C tON VNO_ or VNC_ = +1.5V, RL = 300Ω, CL = 35pF, Figure 2 tOFF VNO_ or VNC_ = +1.5V, RL = 300Ω, CL = 35pF, Figure 2 tBBM VNO_ or VNC_ = +1.5V, RL = 300Ω, CL = 35pF, Figure 3 Q VGEN = 0V, RGEN = 0, CL = 1.0nF, Figure 4 +25°C 7 pC On-Channel -3dB Bandwidth BW Signal = 0dBm, 50Ω in and out +25°C 250 MHz Off-Isolation (Note 9) VISO f = 1MHz, VNO_ = 1VRMS, RL = 50Ω, CL = 5pF, Figure 5 +25°C -72 dB Crosstalk (Note 10) VCT f = 1MHz, VNO_ = 1VRMS, RL = 50Ω, CL = 5pF, Figure 6 +25°C 84 dB Turn-On Time TMIN to TMAX 170 +25°C Turn-Off Time Break-Before-Make (MAX4749/MAX4750 Only) (Note 8) Charge Injection NO_ or NC_ Off-Capacitance 24 TMIN to TMAX COFF TMIN to TMAX 60 70 +25°C ns ns 33 ns 1 f = 1MHz, Figure 7 +25°C 20 pF COM_ Off-Capacitance CCOM_(OFF) f = 1MHz, Figure 7 +25°C 20 pF COM_ On-Capacitance CCOM_(ON) f = 1MHz, Figure 7 +25°C 40 pF LOGIC INPUT Input Logic High VIH Input Logic Low VIL Input Leakage Current IIN 1.4 VIN_ = 0V or V+ -1 V +0.005 0.8 V +1 µA 11 V 1 µA POWER SUPPLY Power-Supply Range Positive Supply Current V+ I+ 2 V+ = +5.5V, VIN_ = 0V or V+, all switches on or off 0.0001 _______________________________________________________________________________________ 3 MAX4747–MAX4750 ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued) MAX4747–MAX4750 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP ELECTRICAL CHARACTERISTICS—Single +5V Supply (V+ = +5V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS V+ V ANALOG SWITCH Analog Signal Range On-Resistance VCOM_, VNO_, VNC_ RON 0 V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +3.0V +25°C 8.2 TMIN to TMAX 25 30 +25°C 0.1 3 On-Resistance Matching Between Channels (Notes 5, 6) ∆RON On-Resistance Flatness (Notes 7) RFLAT(ON) V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +1V, +2V, +3V -0.1 +0.1 INO_(OFF), INC_(OFF) V+ = +5.5V, VCOM_ = +1V, +4.5V, VNO_ or VNC_ = +4.5V, +1V +25°C NO_ or NC_ Off-Leakage Current (Note 8) TMIN to TMAX -2 +2 V+ = +5.5V, ICOM_(OFF) VCOM_ = +1V, +4.5V, VNO_ or VNC_ = +4.5V, +1V +25°C -0.1 +0.1 COM_ Off-Leakage Current (Note 8) TMIN to TMAX -2 +2 V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +3.0V TMIN to TMAX 4 +25°C COM_ On-Leakage Current (Note 8) ICOM_(ON) 2.2 TMIN to TMAX Ω Ω 5 7 V+ = +5.5V, VCOM_ = +1V, +4.5V, VNO_ or VNC_ = +1V, +4.5V, or floating +25°C -0.2 +0.2 TMIN to TMAX -4 +4 Ω nA nA nA DYNAMIC +25°C 36 85 Turn-On Time tON VNO_ or VNC_ = +3.0V, RL = 300Ω, CL = 35pF, Figure 2 TMIN to TMAX Turn-Off Time tOFF VNO_ or VNC_ = +3.0V, RL = 300Ω, CL = 35pF, Figure 2 TMIN to TMAX Break-Before-Make (MAX4749/MAX4750 Only) (Note 8) tBBM VNO_ or VNC_ = +3.0V, RL = 300Ω, CL = 35pF, Figure 3 TMIN to TMAX Q VGEN = 0V, RGEN = 0, CL = 1.0nF, Figure 4 +25°C 9 pC Charge Injection 95 +25°C 19 45 55 +25°C ns ns 14 ns 1 On-Channel -3dB Bandwidth BW Signal = 0dBm, 50Ω in and out +25°C 250 MHz Off-Isolation (Note 9) VISO f = 1MHz, VNO_= 1VRMS, RL = 50Ω, CL = 5pF, Figure 5 +25°C -72 dB 4 _______________________________________________________________________________________ 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP (V+ = +5V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS f = 1MHz, VNO_ = 1VRMS, RL = 50Ω, CL = 5pF, Figure 6 +25°C -84 dB f = 1MHz, Figure 7 +25°C 20 pF COM_ Off-Capacitance CCOM_(OFF) f = 1MHz, Figure 7 +25°C 20 pF COM_ On-Capacitance CCOM_(ON) f = 1MHz, Figure 7 +25°C 40 pF Crosstalk (Note 10) VCT NO_ or NC_ Off-Capacitance COFF LOGIC INPUT Input Logic High VIH Input Logic Low VIL Input Leakage Current IIN 2 VIN_ = 0V or V+ V -1 +0.005 0.8 V +1 µA 11 V 1 µA POWER SUPPLY Power-Supply Range V+ Positive Supply Current I+ 2 V+ = +5.5V, VIN_ = 0V or V+, all switches on or off 0.0001 The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 4: UCSP parts are 100% tested at +25°C only, and are guaranteed by design over temperature. TSSOP and Thin QFN parts are 100% tested at +85°C and guaranteed by design over temperature. Note 5: ∆RON = RON(MAX) - RON(MIN). Note 6: UCSP and Thin QFN on-resistance matching between channels is guaranteed by design. Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. Note 8: Guaranteed by design. Note 9: Off-isolation = 20 log10 (VNO_/VCOM_), VNO_ = output, VCOM_ = input to off switch. Note 10: Between any two switches. Note 3: Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) V+ = 5V TA = +85°C 12 V+ = 3V 25 RON (Ω) 8 TA = +25°C TA = +85°C 20 TA = +25°C 30 RON (Ω) RON (Ω) V+ = 2V 30 MAX4747–50-toc02 MAX4747–50-toc01 40 ON-RESISTANCE vs. VCOM ON-RESISTANCE vs. VCOM 16 MAX4747–50-toc03 ON-RESISTANCE vs. VCOM 50 15 20 V+ = 3V 10 10 TA = -40°C 4 V+ = 5V TA = -40°C 5 V+ = 11V 0 0 0 0 2 4 6 VCOM (V) 8 10 12 0 1 2 3 VCOM (V) 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VCOM (V) _______________________________________________________________________________________ 5 MAX4747–MAX4750 ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE TA = -40°C 10 0 1.0 1.5 2.0 2.5 -15 VCOM (V) 10 35 60 -40 85 IN LOGIC THRESHOLD vs. SUPPLY VOLTAGE FREQUENCY RESPONSE 2.5 2.0 1.5 1.0 MAX4747–50-toc08 -20 LOSS -30 -40 -50 -60 OFFISOLATION -70 60 50 PHASE CROSSTALK -110 0.01 0 2 4 6 8 10 12 0.1 1 TURN-ON/OFF TIME vs. TEMPERATURE 100 V+ = 3V 0 1000 0 30 4 6 8 10 12 VCOM (V) TOTAL HARMONIC DISTORTION vs. FREQUENCY VNO = V+/2 100 tON 80 2 1 SOURCE AND LOAD = 600Ω VCOM = 2VP-P V+ = 3V 0.1 THD (%) tON, V+ = 5V 40 20 10 120 TURN-ON/OFF TIME (ns) MAX4747–50-toc10 70 tON, V+ = 3V V+ = 5V TURN-ON/OFF TIME vs. SUPPLY VOLTAGE 80 50 30 FREQUENCY (MHz) SUPPLY VOLTAGE (V) 60 40 10 -100 0.5 V+ = 11V 20 -80 -90 85 CHARGE INJECTION vs. VCOM -10 GAIN (dB)/PHASE (DEGREES) 3.0 MAX4747–50-toc07 VNO_ = V+ 3.5 60 35 10 TEMPERATURE (°C) 0 0 -15 TEMPERATURE (°C) 4.0 MAX4747–50-toc06 0.01 -40 CHARGE (pC) 0.5 OFF 0.1 0.1 0 LOGIC THRESHOLD (V) ON 1 1 5 60 tOFF V+ = 5V 0.01 40 tOFF, V+ = 3V tOFF, V+ = 5V 20 10 0 0.001 0 -40 -15 10 35 TEMPERATURE (°C) 6 10 MAX4747–50-toc09 10 100 V+ = 5V, VCOM = 4.5V, NO_ or NC_ = FLOATING MAX4747-50 toc12 15 100 MAX4747–50-toc11 RON (Ω) 20 V+ = 3V, 5V 1000 SUPPLY CURRENT (pA) 25 MAX4747–50-toc05 V+ = 2.5V TA = +25°C TA = +85°C LEAKAGE vs. TEMPERATURE 10,000 MAX4747–50-toc04 30 LEAKAGE CURRENT (pA) ON-RESISTANCE vs. VCOM TURN-ON/OFF TIME (ns) MAX4747–MAX4750 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP 60 85 0 2 4 6 8 SUPPLY VOLTAGE (V) 10 12 0.01 0.1 1 FREQUENCY (kHz) _______________________________________________________________________________________ 10 100 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP PIN NAME FUNCTION MAX4747 MAX4748 MAX4749 MAX4750 1, 3, 8, 11 — — — — 1, 3, 8, 11 — — NC1–NC4 Analog-Switch Normally Closed Terminals — — 1, 8 — NO1, NO3 Analog-Switch Normally Open Terminals — — — 1, 8 NO1, NO2 Analog-Switch Normally Open Terminals — — — 4, 11 NC1, NC2 Analog-Switch Normally Closed Terminals — — 3, 11 — NC2, NC4 Analog-Switch Normally Closed Terminals 2, 4, 9, 10 2, 4, 9, 10 2, 4, 9, 10 — COM1–COM4 NO1–NO4 Analog-Switch Normally Open Terminals Analog-Switch Common Terminal — — — 2, 9 COM1, COM2 13, 5, 6, 12 13, 5, 6, 12 13, 5, 6, 12 — IN1–IN4 Logic-Control Digital Input Analog-Switch Common Terminal — — — 13, 6 IN1, IN2 Logic-Control Digital Input 7 7 7 7 GND 14 14 14 14 V+ — — — 3, 5, 10, 12 N.C. Ground. Connect to digital ground. Positive Analog and Digital Supply Voltage Input. Internally connected to substrate. No Connection. Not internally connected. Pin Description—UCSP PIN MAX4747 MAX4748 MAX4749 MAX4750 NAME FUNCTION B1, A2, C4, D2 — — — NO1–NO4 Analog-Switch Normally Open Terminals — B1, A2, C4, D2 — — NC1–NC4 Analog-Switch Normally Closed Terminals — — B1, C4 — NO1, NO3 Analog-Switch Normally Open Terminals — — — B1, C4 NO1, NO2 Analog-Switch Normally Open Terminals — — — A3, D2 NC1, NC2 Analog-Switch Normally Closed Terminals Analog-Switch Normally Closed Terminals — — A2, D2 — NC2, NC4 A1, A3, D4, D3 A1, A3, D4, D3 A1, A3, D4, D3 — COM1–COM4 Analog-Switch Common Terminal — — — A1, D4 COM1, COM2 Analog-Switch Common Terminal C1, A4, B4, D1 C1, A4, B4, D1 C1, A4, B4, D1 — IN1–IN4 — — — C1, B4 IN1, IN2 C3 C3 C3 C3 GND B2 B2 B2 B2 V+ — — — A2, A4, D1, D3 N.C. Logic-Control Digital Input Logic-Control Digital Input Ground. Connect to digital ground. Positive Analog and Digital Supply Voltage Input. Internally connected to substrate. No Connection. Not internally connected. _______________________________________________________________________________________ 7 MAX4747–MAX4750 Pin Description—TSSOP 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747–MAX4750 Pin Description—Thin QFN PIN 8 NAME FUNCTION MAX4747 MAX4748 MAX4749 MAX4750 1, 3 1, 3 1, 3 4, 12 COM1, COM2 2 — — 3 NO2 4, 13 4, 13 4, 13 2, 10 IN2, IN1 5, 12 5, 12 5, 12 — IN3, IN4 6 6 6 6 GND Ground. Connect to digital ground. 7 — 7 — NO3 Analog-Switch Normally Open Terminal 8, 14 8, 14 8, 14 1, 5, 8, 9, 13, 14 N.C. No Connection. Not internally connected. 9, 10 9, 10 9, 10 — COM3, COM4 11 — — — NO4 15 15 15 15 V+ 16 — 16 11 NO1 Analog-Switch Normally Open Terminal — 2 2 7 NC2 Analog-Switch Normally Closed Terminal — 7 — — NC3 Analog-Switch Normally Closed Terminal — 11 11 — NC4 Analog-Switch Normally Closed Terminal — 16 — 16 NC1 EP EP EP EP — Analog-Switch Normally Closed Terminal Exposed Pad. Connect exposed paddle to V+. Analog-Switch Common Terminals Analog-Switch Normally Open Terminal Logic-Control Digital Inputs Logic-Control Digital Inputs Analog-Switch Common Terminals Analog-Switch Normally Open Terminal Positive Supply-Voltage Input _______________________________________________________________________________________ 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP Test Circuits/Timing Diagrams Operating Considerations for High-Voltage Supply The MAX4747–MAX4750 operate to +11V with some precautions. The absolute maximum rating for V+ is +12V (referenced to GND). When operating near this region, bypass V+ with a minimum 0.1µF capacitor to ground as close to the IC as possible. V+ D1 EXTERNAL BLOCKING DIODE MAX4747– MAX4750 V+ * * NO_ COM_ Logic Levels The MAX4747–MAX4750 are TTL compatible when powered from a single +3V supply. When powered from other supply voltages, the logic inputs should be driven rail-to-rail. For example, with a +11V supply, IN_ should be driven low to 0V and high to 11V. With a +3.3V supply, IN_ should be driven low to 0V and high to 3.3V. Driving IN_ rail-to-rail minimizes power consumption. Analog Signal Levels Analog signals that range over the entire supply voltage (GND to V+) pass with very little change in RON (see the Typical Operating Characteristics). The bidirectional switches allow NO_, NC_, and COM_ connections to be used as either inputs or outputs. Power-Supply Sequencing and Overvoltage Protection CAUTION: Do not exceed the absolute maximum ratings. Stresses beyond the listed ratings can cause permanent damage to the devices. Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+ before applying analog signals, especially if the analog signal is not current limited. If this sequencing is not possible, and if the analog inputs are not current limited to <20mA, add small-signal diode D1 as shown in Figure 1. If the analog signal can dip below GND, add D2. Adding protection diodes reduces the analog signal range to a diode drop (about 0.7V) below V+ (for D1), and to a diode drop above ground (for D2). Leakage is unaffected by adding the diodes. On-resistance increases slightly at low supply voltages. Maximum supply voltage (V+) must not exceed +11V. * * GND EXTERNAL BLOCKING DIODE D2 GND *INTERNAL PROTECTION DIODES Figure 1. Overvoltage Protection Using External Blocking Diodes Adding protection diodes causes the logic thresholds to be shifted relative to the power-supply rails. The most significant shift occurs when using low supply voltages (+5V or less). With a +5V supply, TTL compatibility is not guaranteed when protection diodes are added. Driving IN_ and IN_ all the way to the supply rails (i.e., to a diode drop higher than the V+ pin, or to a diode drop lower than the GND pin) is always acceptable. Protection diodes D1 and D2 also protect against some overvoltage situations. Using the circuit in Figure 1, no damage results if the supply voltage is below the absolute maximum rating (+12V) and if a fault voltage up to the absolute maximum rating (V+ + 0.3V) is applied to an analog signal terminal. UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PC board techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP—A Wafer-Level Chip-Scale Package on Maxim’s web site at www.maxim-ic.com/ucsp. _______________________________________________________________________________________ 9 MAX4747–MAX4750 Applications Information MAX4747–MAX4750 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP Test Circuits/Timing Diagrams (continued) MAX4747– MAX4750 V+ V+ COM_ NO_ OR NC_ VN_ LOGIC INPUT 50% VIL VOUT CL 35pF RL 300Ω tOFF IN_ VOUT SWITCH OUTPUT GND LOGIC INPUT tr < 5ns tf < 5ns VIH 0.9 x VOUT 0.9 x VOUT 0 tON CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL VOUT = VN_ ( R + R ) L LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. ON Figure 2. Switching Time V+ MAX4749 V+ NO_ VN_ VOUT1 COM_ VOUT2 COM_ NC_ RL2 300Ω IN_ IN_ LOGIC INPUT LOGIC INPUT RL1 300Ω tr < 5ns tf < 5ns VIH 50% VIL CL1 35pF SWITCH OUTPUT 1 (VOUT1) CL2 35pF 0.9 x V0UT1 0 SWITCH OUTPUT 2 (VOUT2) GND 0.9 x VOUT2 0 tBBM tBBM CL INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 3. Break-Before-Make Interval V+ MAX4747– MAX4750 ∆VOUT V+ RGEN V GEN NC_ OR NO_ GND VOUT COM CL 1nF VOUT IN OFF ON OFF IN_ VILTO VIH IN OFF ON OFF Q = (∆V OUT )(C L ) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 4. Charge Injection 10 ______________________________________________________________________________________ 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP 10nF SIGNAL GENERATOR 0dBm 10nF V+ MAX4747– MAX4750 V+ COM_ IN_ VIL OR VIH NC_ OR NO_ ANALYZER SIGNAL GENERATOR 0dBm V+ MAX4747– MAX4750 V+ COM_ NO_/NC_ IN_ IN_ 0 OR 2.4V RL COM_ NO_/NC_ ANALYZER GND 50Ω 0 OR 2.4V N.C. GND RL 10nF VDUAL SUPPLIES USED TO ACCOMMODATE GROUND-REFERENCED INSTRUMENTS. Figure 5. Off-Isolation/On-Channel Bandwidth 10nF VDUAL SUPPLIES USED TO ACCOMMODATE GROUND-REFERENCED INSTRUMENTS. Figure 6. Crosstalk Ordering Information (continued) 10nF MAX4747– MAX4750 V+ COM_ CAPACITANCE METER f = 1MHz IN_ NC_ OR NO_ GND TEMP RANGE PART V+ VIL OR VIH PIN-/BUMPPACKAGE TOP MARK MAX4748EUD -40°C to +85°C 14 TSSOP — MAX4748ETE -40°C to +85°C 16 Thin QFN — MAX4748EBE-T -40°C to +85°C 16 UCSP-16 4748 MAX4749EUD -40°C to +85°C 14 TSSOP MAX4749ETE -40°C to +85°C 16 Thin QFN — MAX4749EBE-T -40°C to +85°C 16 UCSP-16 4749 MAX4750EUD -40°C to +85°C 14 TSSOP MAX4750ETE -40°C to +85°C 16 Thin QFN — MAX4750EBE-T -40°C to +85°C 16 UCSP-16 4750 — — Figure 7. Channel Off-/On-Capacitance Chip Information TRANSISTOR COUNT: 130 PROCESS: CMOS ______________________________________________________________________________________ 11 MAX4747–MAX4750 Test Circuits/Timing Diagrams (continued) 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP MAX4747–MAX4750 Pin Configurations/Truth Tables (continued) V+ N.C. IN1 TOP VIEW (BUMPS SIDE DOWN) NC1 TOP VIEW 16 15 14 13 MAX4748 COM1 1 12 IN4 NC2 2 11 NO4 4 IN3 5 6 7 8 N.C. IN2 MAX4748ETE NC3 3 GND COM2 10 COM4 9 COM3 NC1 1 14 V+ COM1 2 13 IN1 NC2 3 12 IN4 COM2 4 10 COM4 IN3 6 9 COM3 GND 7 8 NC3 NO1 V+ N.C. IN1 14 13 12 IN4 NC2 2 11 NC4 6 7 8 N.C. IN3 5 NO3 4 GND IN2 MAX4749ETE 10 COM4 9 COM3 SWITCH STATE LOW HIGH ON OFF 14 V+ COM1 2 13 IN1 NC2 3 12 IN4 COM2 4 NC1 V+ N.C. N.C. 16 15 14 13 V+ IN3 IN1 GND NC3 COM4 COM3 C IN4 NC4 D 1 2 3 4 COM1 NC2 COM2 IN2 NO1 V+ A 10 COM4 IN3 6 9 COM3 8 NO3 IN3 B IN1 GND NO3 COM4 COM3 C IN4 NC4 D INPUT NO1, NO3 NC2, NC4 LOW HIGH OFF ON ON OFF UCSP MAX4750 12 COM1 IN2 2 11 NO1 MAX4750ETE 10 IN1 9 N.C. NO1 1 14 V+ COM1 2 13 IN1 N.C. 3 12 N.C. NC1 4 11 NC2 N.C. 5 10 N.C. 7 8 GND NC2 N.C. N.C. 6 THIN QFN 8 NO2 GND 7 1 2 3 4 COM1 N.C. NC1 N.C. NO1 V+ A IN2 B IN1 GND NO2 N.C. COM2 C 9 COM2 IN2 6 5 12 NC1 B TOP VIEW (BUMPS SIDE DOWN) 1 4 IN2 TSSOP N.C. COM2 COM2 11 NC4 IN2 5 TOP VIEW 3 NC2 UCSP NO1 1 GND 7 THIN QFN NO2 COM1 A MAX4749 1 3 4 TOP VIEW (BUMPS SIDE DOWN) COM1 COM2 3 TSSOP INPUT TOP VIEW 15 2 11 NC4 IN2 5 THIN QFN 16 1 N.C. NC2 D TSSOP UCSP INPUT NO1, NO2 NC1, NC2 LOW HIGH OFF ON ON OFF ______________________________________________________________________________________ 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP TSSOP4.40mm.EPS ______________________________________________________________________________________ 13 MAX4747–MAX4750 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX4747–MAX4750 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 14 C 2 2 ______________________________________________________________________________________ 50Ω Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP 16L,UCSP.EPS PACKAGE OUTLINE, 4x4 UCSP 21-0101 H 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX4747–MAX4750 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)