19-2586; Rev 2; 2/11 KIT ATION EVALU E L B A AVAIL Smallest TEC Power Drivers for Optical Modules Features The MAX8520/MAX8521 are designed to drive thermoelectric coolers (TECs) in space-constrained optical modules. Both devices deliver ±1.5A output current and control the TEC current to eliminate harmful current surges. On-chip FETs minimize external components and high switching frequency reduces the size of external components. o Circuit Footprint 0.31in2 The MAX8520/MAX8521 operate from a single supply and bias the TEC between the outputs of two synchronous buck regulators. This operation allows for temperature control without “dead zones” or other nonlinearities at low current. This arrangement ensures that the control system does not hunt when the set-point is very close to the natural operating point, requiring a small amount of heating or cooling. An analog control signal precisely sets the TEC current. Both devices feature accurate, individually-adjustable heating current limit and cooling current limit along with maximum TEC voltage limit to improve the reliability of optical modules. An analog output signal monitors the TEC current. A unique ripple cancellation scheme helps reduce noise. The MAX8520 is available in a 5mm x 5mm TQFN package and its switching frequency is adjustable up to 1MHz through an external resistor. The MAX8521 is also available in a 5mm x 5mm TQFN as well as space-saving 3mm x 3mm UCSP™ and 36-bump WLP (3mm x 3mm) packages, with a pin-selectable switching frequency of 500kHz or 1MHz. o Direct Current Control Prevents TEC Current Surges Applications SFF/SFP Modules o Low Profile Design o On-Chip Power MOSFETs o High-Efficiency Switch-Mode Design o Ripple Cancellation for Low Noise o 5% Accurate Adjustable Heating/Cooling Current Limits o 2% Accurate TEC Voltage Limit o No Dead Zone or Hunting at Low Output Current o ITEC Monitors TEC Current o 1% Accurate Voltage Reference o Switching Frequency up to 1MHz o Synchronization (MAX8521) Ordering Information PART TEMP RANGE PIN-PACKAGE MAX8520ETP+ -40°C to +85°C 20 TQFN-EP* 5mm x 5mm MAX8521EBX MAX8521ETP+ -40°C to +85°C 6 x 6 UCSP 3mm x 3mm -40°C to +85°C 20 TQFN-EP* 5mm x 5mm MAX8521EWX+ -40°C to +85°C 36 WLP** 3mm x 3mm +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Four center bumps depopulated. Fiber Optic Laser Modules Typical Operating Circuit Fiber Optic Network Equipment ATE Biotech Lab Equipment INPUT 3V TO 5.5V VDD PVDD_ LX1 FREQ PGND1 SHDN CS ON OFF TEC CURRENT MONITOR CURRENTCONTROL SIGNAL ITEC MAX8521 CTLI COMP OS1 OS2 LX2 TEC OUTPUT ITEC = ± 1.5A REF GND PGND2 Pin Configurations appear at end of data sheet ANALOG /DIGITAL TEMPERATURE CONTROL UCSP is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8520/MAX8521 General Description MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V SHDN, MAXV, MAXIP, MAXIN, CTLI to GND .........................................................-0.3V to +6V COMP, FREQ, OS1, OS2, CS, REF, ITEC to GND...........................................-0.3V to (VDD + 0.3V) PVDD1, PVDD2 to GND .............................-0.3V to (VDD + 0.3V) PVDD1, PVDD2 to VDD ..........................................-0.3V to +0.3V PGND1, PGND2 to GND .......................................-0.3V to +0.3V COMP, REF, ITEC short to GND....................................Indefinite LX Current (Note 1) ........................................±2.25A LX Current Continuous Power Dissipation (TA = +70°C) 6 x 6 UCSP (derate 22mW/°C above +70°C) ...............1.75W 20-Pin 5mm x 5mm x 0.9mm TQFN (derate 20.8mW/°C above +70°C) (Note 2)...................................................1.67W 36-Bump WLP (derate 22mW/°C above +70°C)............1.75W Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) Lead(Pb)-Free (TQFN, WLP)........................................+260°C Containing Lead (UCSP)............................................. +240°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: LX has internal clamp diodes to PGND and PVDD. Applications that forward bias these diodes should take care not to exceed the IC’s package power dissipation limits. Note 2: Solders underside metal slug to PCB ground plane. PACKAGE THERMAL CHARACTERISTICS (Note 3) 20 TQFN Junction-to-Ambient Thermal Resistance (θJA)...............30°C/W Junction-to-Case Thermal Resistance (θJC)......................2°C/W 6x6 UCSP Junction-to-Ambient Thermal Resistance (θJA)................65.5°C/W Junction-to-Case Thermal Resistance (θJC).......................0°C/W 36 WLP Junction-to-Ambient Thermal Resistance (θJA)..................38°C/W Junction-to-Case Thermal Resistance (θJC)......................4°C/W Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDD = VPVDD1 = VPVDD2 = V SHDN = 5V, 1MHz mode (Note 4). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = 0°C to +85°C, unless otherwise noted. Typical values at TA = +25°C.) PARAMETER Input Supply Range SYMBOL CONDITIONS VDD Reference Load Regulation MAX UNITS 5.5 V ±1.5 VREF ∆VREF VDD = 3V to 5.5V, IREF = 150µA VDD = 3V nFET On-Resistance RDS(ON-N) pFET On-Resistance RDS(ON-P) nFET Leakage ILEAK(N) pFET Leakage ILEAK(P) 1.485 VDD = 3V to 5V, IREF = 10µA to 1mA VDD = 5V MAXIP/MAXIN Threshold Accuracy 2 TYP 3.0 Maximum TEC Current Reference Voltage MIN A 1.500 1.515 V 1.2 5.0 mV 160 VMAXI_ = VREF 140 150 VMAXI_ = VREF/3 40 50 60 VMAXI_ = VREF 143 150 155 VMAXI_ = VREF/3 45 50 55 VDD = 5V, I = 0.2A 0.09 0.14 VDD = 3V, I = 0.2A 0.11 0.16 VDD = 5V, I = 0.2A 0.14 0.23 VDD = 3V, I = 0.2A 0.17 0.30 VLX = VDD = 5V, TA = +25°C 0.03 4.00 VLX = VDD = 5V TA = +85°C 0.3 VLX = 0V, TA = +25°C 0.03 VLX = 0V, TA = +85°C 0.3 _______________________________________________________________________________________ 4.00 mV Ω Ω µA µA Smallest TEC Power Drivers for Optical Modules (VDD = VPVDD1 = VPVDD2 = V SHDN = 5V, 1MHz mode (Note 4). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = 0°C to +85°C, unless otherwise noted. Typical values at TA = +25°C.) PARAMETER No-Load Supply Current Shutdown Supply Current Thermal Shutdown SYMBOL CONDITIONS MIN 500kHz mode 11 14 1MHz mode 16 21 LOAD) VCOMP = VREF = 1.500V, VDD = 3.3V 500kHz mode 8 11 1MHz mode 11 14 IDD-SD SHDN = GND, VDD = 5V, (Note 5) 2 3 IDD(NO VUVLO Internal Oscillator Switching Frequency MAX VCOMP = VREF = 1.500V, VDD = 5V TSHUTDOWN Hysteresis = 15°C UVLO Threshold TYP fSW-INT UNITS mA mA °C +165 VDD rising 2.50 2.65 2.80 VDD falling 2.40 2.55 2.70 MAX8521, FREQ = VDD, VDD = 3V to 5V 0.8 1.0 1.2 MAX8521, FREQ = GND, VDD = 3V to 5V 0.4 0.5 0.6 MAX8520, REXT = 60kΩ, VDD = 5V 0.8 1.0 1.2 MAX8520, REXT = 60kΩ, VDD = 3V 0.76 0.93 1.10 V MHz MAX8520, REXT = 150kΩ, VDD = 5V 0.4 0.5 0.6 MAX8520, REXT = 150kΩ, VDD = 3V 0.36 0.46 0.56 External Sync Frequency Range 25% < duty cycle < 75% (MAX8521 only) 0.7 1.2 MHz LX_ Duty Cycle (Note 6) 0 100 % -100 +100 µA -5 +5 µA VDD x 0.25 V OS1, OS2, CS Input Current IOS1, IOS2, ICS SHDN, FREQ Input Current ISHDN, IFREQ 0V or VDD 0V or VDD, FREQ applicable for the MAX8521 only SHDN, FREQ Input Low Voltage VIL VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only SHDN, FREQ Input High Voltage VIH VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only VDD x 0.75 VMAXV = VREF x 0.67, VOS1 to VOS2 = ±4V, VDD = 5V -2 +2 % VMAXV = VREF x 0.33, VOS1 to VOS2 = ±2V, VDD = 3V -3 +3 % VMAXV = VMAXI_ = 0.1V or 1.5V -0.1 +0.1 µA MAXV Threshold Accuracy MAXV, MAXI_ Input Bias Current IMAXV-BIAS, IMAXI_-BIAS V CTLI Gain ACTLI VCTLI = 0.5V to 2.5V (Note 7) 9.5 10.0 10.5 V/V CTLI Input Resistance RCTLI 1MΩ terminated at REF 0.5 1.0 2.0 MΩ 50 100 160 µS +10 % Error-Amp Transconductance VITEC Accuracy gm VOS1 to VCS = ±100mV VOS1 = VDD/2 -10 _______________________________________________________________________________________ 3 MAX8520/MAX8521 ELECTRICAL CHARACTERISTICS (continued) MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules ELECTRICAL CHARACTERISTICS (VDD = VPVDD1 = VPVDD2 = VSHDN = 5V, 1MHz mode (Note 4). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = -40°C to +85°C, unless otherwise noted.) (Note 8) PARAMETER Input Supply Range SYMBOL CONDITIONS VDD Reference Load Regulation VREF ∆VREF VDD = 3V to 5.5V, IREF = 150µA VDD = 3V nFET On-Resistance RDS(ON-N) pFET On-Resistance RDS(ON-P) IDD(NO LOAD) Shutdown Supply Current IDD-SD UVLO Threshold VUVLO Internal Oscillator Switching Frequency 3.0 5.5 fSW-INT 1.480 VDD = 3V to 5V, IREF = 10µA to 1mA VDD = 5V MAXIP/MAXIN Threshold Accuracy No Load Supply Current MAX ±1.5 Maximum TEC Current Reference Voltage MIN 1.515 V 5 mV VMAXI_ = VREF 140 160 VMAXI_ = VREF/3 40 60 VMAXI_ = VREF 143 155 VMAXI_ = VREF/3 45 55 0.14 VDD = 3V, I = 0.2A 0.16 VDD = 5V, I = 0.2A 0.23 VDD = 3V, I = 0.2A 0.30 500kHz mode 1MHz mode 14 21 500kHz mode 1MHz mode SHDN = GND, VDD = 5V (Note 5) 11 14 3 VCOMP = VREF = 1.500V, VDD = 3.3V V A VDD = 5V, I = 0.2A VCOMP = VREF = 1.500V, VDD = 5V UNITS VDD Rising 2.50 2.80 VDD Falling 2.40 2.70 MAX8521, FREQ = VDD, VDD = 3V to 5V 0.8 1.2 MAX8521, FREQ = GND, VDD = 3V to 5V 0.4 0.6 MAX8520, REXT = 60kΩ, VDD = 5V 0.8 1.2 MAX8520, REXT = 60kΩ, VDD = 3V 0.76 1.10 mV Ω Ω mA mA V MHz MAX8520, REXT = 150kΩ, VDD = 5V 0.4 0.6 MAX8520, REXT = 150kΩ, VDD = 3V 0.36 0.56 External Sync Frequency Range 25% < duty cycle < 75% (MAX8521 only) 0.7 1.2 MHz LX_ Duty Cycle Note 6 0 100 % -100 +100 µA -5 +5 µA VDD x 0.25 V OS1, OS2, CS Input Current SHDN, FREQ Input Current IOS1, IOS2, 0V or VDD ICS ISHDN, IFREQ 0V or VDD, FREQ applicable for the MAX8521 only SHDN, FREQ Input Low Voltage VIL VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only SHDN, FREQ Input High Voltage VIH VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only 4 VDD x 0.75 _______________________________________________________________________________________ V Smallest TEC Power Drivers for Optical Modules (VDD = VPVDD1 = VPVDD2 = VSHDN = 5V, 1MHz mode (Note 4). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = -40°C to +85°C, unless otherwise noted.) (Note 8) PARAMETER SYMBOL MAXV Threshold Accuracy IMAXVBIAS, MAXV, MAXI_ Input Bias Current MIN MAX UNITS VMAXV = VREF x 0.67, VOS1 to VOS2 = ±4V, VDD = 5V CONDITIONS -2 +2 % VMAXV = VREF x 0.33, VOS1 to VOS2 = ±2V, VDD = 3V -3 +3 % VMAXV = VMAXI_ = 0.1V or 1.5V -0.1 +0.1 µA 10.5 V/V IMAXI_-BIAS CTLI Gain ACTLI VCTLI = 0.5V to 2.5V (Note 7) 9.5 CTLI Input Resistance RCTLI 1MΩ terminated at REF 0.5 2.0 MΩ 50 160 µS -10 +10 % Error-Amp Transconductance gm VOS1 to VCS = ±100mV VOS1 = VDD/2 VITEC Accuracy Note 4: Enter 1MHz mode by connecting a 60kΩ resistor from FREQ to ground for the MAX8520, and connecting FREQ to VDD for the MAX8521. Note 5: Includes power FET leakage. Note 6: Duty-cycle specification is guaranteed by design and not production tested. Note 7: CTLI Gain is defined as: ACTLI = ∆VCTLI ∆( VOS1 − VCS ) Note 8: Specifications to -40°C are guaranteed by design and not production tested. Typical Operating Characteristics (VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted.) EFFICIENCY vs. TEC CURRENT VDD = 3.3V, RTEC = 1.3Ω EFFICIENCY vs. TEC CURRENT VDD = 5V, RTEC = 2Ω 70 80 60 50 40 60 20 20 10 10 0 0 0.4 0.6 0.8 1 TEC CURENT (A) 1.2 1.4 1.6 VOS2 20mV/div AC-COUPLED FREQ = 1MHz 40 30 0.2 C2 = C7 = 1µF 50 30 0 FREQ = 500kHz 70 EFFICIENCY (%) EFFICIENCY (%) FREQ = 1MHz MAX8520/21 toc03 MAX8520/21 toc02 FREQ = 500kHz 80 90 MAX8520/21 toc01 90 COMMON-MODE OUTPUT VOLTAGE RIPPLE VOS1 20mV/div AC-COUPLED ITEC = 1A 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 400ns/div TEC CURRENT (A) _______________________________________________________________________________________ 5 MAX8520/MAX8521 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted.) DIFFERENTIAL OUTPUT VOLTAGE RIPPLE TEC CURRENT RIPPLE VDD RIPPLE MAX8520/21 toc06 MAX8520/21 toc05 MAX8520/21 toc04 C2 = C7 = 1µF 1.5A VOS2 - VOS1 1mV/div AC-COUPLED VDD 20mV/div AC-COUPLED ITEC = 1A ITEC = 1A 10mA/div AC-COUPLED 0A 400ns/div 400ns/div 400ns/div ZERO-CROSSING TEC CURRENT MAX8520/21 toc07 VITEC vs. TEC CURRENT MAX8520/21 toc08 VCTLI 1V/div 3.0 2.5 VCTLI I00mV/div 0V MAX8520/21 toc09 TEC CURRENT vs. CTLI VOLTAGE 2.0 VITEC (V) 1.5V 1.5 0A 1.0 0A ITEC 1A/div 0.5 ITEC 100mA/div 0 20ms/div -2.0 -1.5 -1.0 -0.5 1ms/div 0 0.5 1.0 TEC CURRENT (A) SWITCHING FREQUENCY vs. TEMPERATURE ITEC vs. AMBIENT TEMPERATURE 0.500 0.490 0.480 0.470 FREQ = 1MHz VCTLI = 2V RTEC = 1Ω 0.460 FREQ = 1MHz 1000 VCTLI = 1.5V RTEC = 1Ω 900 800 700 600 FREQ = 500KHz 500 0.450 400 -40 -20 0 +20 +40 +60 AMBIENT TEMPERATURE (°C) 6 MAX8520/21 toc11 0.510 1100 SWITCHING FREQUENCY (kHz) MAX8520/21 toc10 0.520 TEC CURRENT (A) MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules +80 -40 -20 0 +20 +40 +60 TEMPERATURE (°C) _______________________________________________________________________________________ +80 1.5 2.0 Smallest TEC Power Drivers for Optical Modules 600 FREQ = 500kHz 400 800 VDD = 5V 700 0 400 4.0 4.5 5.0 MAX8520/21 toc14 REF SOURCING 150µA 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 60 5.5 80 100 120 140 3.0 160 3.5 4.0 4.5 5.0 5.5 VDD (V) REXT (kΩ) VDD (V) REFERENCE VOLTAGE CHANGE vs. TEMPERATURE REFERENCE VOLTAGE CHANGE vs. LOAD CURRENT STARTUP AND SHUTDOWN WAVEFORMS 3 2 1 0 -1 -2 -3 MAX8520/21 toc17 MAX8520/21 toc16 REF SOURCING 150µA 0 REFERENCE VOLTAGE CHANGE (mV) MAX8520/21 toc15 5 4 VDD = 3.3V 600 500 3.5 MAX8520/21 toc13 900 200 3.0 REFERENCE VOLTAGE CHANGE (mV) 1000 0.6 REFERENCE VOLTAGE CHANGE (mV) 800 1100 SWITCHING FREQUENCY (kHz) MAX8520/21 toc12 SWITCHING FREQUENCY CHANGE (kHz) FREQ = 1MHz 1000 REFERENCE VOLTAGE CHANGE vs. VDD SWITCHING FREQUENCY vs. REXT SWITCHING FREQUENCY CHANGE vs. VDD 1200 -2 VSHDN 5V/div 0V -4 IDD 200mA/div 0mA -6 -8 ITEC 500mA/div 0mA -10 -4 -12 -5 -40 -20 0 +20 +40 +60 0 +80 0.2 0.4 0.6 0.8 1.0 200µs/div LOAD CURRENT (mA) TEMPERATURE (°C) CTLI STEP RESPONSE VDD STEP RESPONSE MAX8520/21 toc18 MAX8520/21 toc19 VCTLI 1V/div VDD 2V/div 1.5V 0V 1A ITEC 10mA/div 0A ITEC 1A/div 1ms MAX8520/MAX8521 Typical Operating Characteristics (continued) (VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted.) 10ms/div _______________________________________________________________________________________ 7 MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules Typical Operating Characteristics (continued) (VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted.) THERMAL STABILITY, COOLING MODE THERMAL STABILITY, ROOM TEMPERATURE MAX8520/21 toc20 THERMAL STABILITY, HEATING MODE MAX8520/21 toc21 TEMPERATURE 0.001°C/div TTEC = +25°C TA = +45°C MAX8520/21 toc22 TEMPERATURE 0.001°C/div TTEC = +25°C TA = +25°C 4s/div TEMPERATURE 0.001°C/div TTEC = +25°C TA = +5°C 4s/div 4s/div Pin Description PIN 8 NAME FUNCTION TQFN UCSP/WLP 1 E1, E2 LX1 2 D1, D2, D3 PGND1 3 C1 SHDN Shutdown Control Input. Pull SHDN low to turn off PWM control and ITEC output. 4 C2 COMP Current-Control Loop Compensation. See the Compensation Capacitor section. 5 B1 ITEC Inductor Connection. LX1 is high-impedance in shutdown. Power Ground 1. Internal synchronous-rectifier ground connection. Connect all PGND pins together at power ground plane. TEC Current-Monitor Output. The ITEC output voltage is a function of the voltage across the TEC current-sense resistor. VITEC = VREF + 8 (VOS - VCS). Keep capacitance on ITEC < 150pF. 6 A1 MAXIN Maximum Negative TEC Current. Connect MAXIN to REF to set default negative current limit to - 150mV/RSENSE. To lower this current limit, connect MAXIN to a resistor-divider network from REF to GND. The current limit will then be equal to -(VMAXIN/VREF) x (150mV/RSENSE). 7 A2 MAXIP Maximum Positive TEC Current. Connect MAXIP to REF to set default positive current limit to 150mV/RSENSE. To lower this current limit, connect MAXIP to a resistor-divider network from REF to GND. The current limit will then be equal to (VMAXIP/VREF) x (150mV/RSENSE). 8 A3 MAXV Maximum Bipolar TEC Voltage. Connect MAXV to REF to set default maximum TEC voltage to VDD. To lower this limit, connect MAXV to a resistor-divider network from REF to GND. The maximum TEC voltage is equal to 4 x VMAXV or VDD, whichever is lower. 9 A4 REF 1.50V Reference Output. Bypass REF to GND with a 0.1µF ceramic capacitor. _______________________________________________________________________________________ Smallest TEC Power Drivers for Optical Modules PIN TQFN NAME UCSP/WLP FUNCTION TEC Current-Control Input. Sets TEC current. Center point is 1.50V (no TEC current). The current is given by: ITEC = (VOS1 - VCS) / RSENSE = (VCTLI - 1.50) / (10 x RSENSE). When (VCTLI - VREF) > 0V then VOS2 > VOS1 > VCS. 10 A5 CTLI 11 A6 GND Analog Ground. Star connect to PGND at underside exposed pad for TQFN package. 12 B6 VDD Analog Supply Voltage Input. Bypass VDD to GND with a 1µF ceramic capacitor. For MAX8520: Analog FREQ Set Pin (see the Switching Frequency section). For MAX8521: Digital FREQ Selection Pin. Connect to VDD for 1MHz operation, connect to GND for 500kHz operation. The PWM oscillator can synchronize to FREQ by switching at FREQ between 700kHz and 1.2MHz. 13 C5 FREQ 14 D6, D5, D4 PGND2 15 E5, E6 LX2 16 F5, F6 PVDD2 17 F4 CS 18 C6 OS2 Output Sense 2. OS2 senses one side of the differential TEC voltage. OS2 is a sense point, not a power output. OS2 discharges to ground in shutdown. 19 F3 OS1 Output Sense 1. OS1 senses one side of the differential TEC voltage. OS1 is a sense point, not a power output. OS1 discharges to ground in shutdown. 20 F1, F2 PVDD1 Power Input 1. Connect all PVDD inputs together at the VDD power plane. B2, B5, C3, C4 GND2 Ground. Additional ground pads aid in heat dissipation. Short to either GND or PGND plane. B3, B4 E3, E4 N.C. — EP — Power Ground 2. Internal synchronous rectifier ground connection. Connect all PGND pins together at the power ground plane. Inductor Connection. LX2 is high-impedance in shutdown. Power Input 2. Connect all PVDD inputs together at the VDD power plane. Current-Sense Input. The current through the TEC is monitored between CS and OS1. The maximum TEC current is given by 150mV/RSENSE and is bipolar. No Connect. Connect N.C. pads to GND2 to aid in heat dissipation. Exposed Paddle (TQFN Only). Internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. _______________________________________________________________________________________ 9 MAX8520/MAX8521 Pin Description (continued) MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules Detailed Description The MAX8520/MAX8521 TEC drivers consist of two switching buck regulators that operate together to directly control the TEC current. This configuration creates a differential voltage across the TEC, allowing bidirectional TEC current for controlled cooling and heating. Controlled cooling and heating allow accurate TEC temperature control to within 0.01°C. The voltage at CTLI directly sets the TEC current. An external thermalcontrol loop is typically used to drive CTLI. Figures 1 and 2 show examples of the thermal-control-loop circuit. Ripple Cancellation Switching regulators like those used in the MAX8520/ MAX8521 inherently create ripple voltage on the output. The dual regulators in the MAX8520/MAX8521 switch in-phase and provide complementary in-phase duty cycles so ripple waveforms at the TEC are greatly reduced. This feature suppresses ripple currents and electrical noise at the TEC to prevent interference with the laser diode. Switching Frequency For the MAX8521, FREQ sets the switching frequency of the internal oscillator. With FREQ = GND, the oscillator frequency is set to 500kHz. The oscillator frequency is 1MHz when FREQ = VDD. For the MAX8520, connect a resistor (REXT in Figure 2) from FREQ to GND. Choose REXT = 60kΩ for 1MHz operation, and REXT = 150kΩ for 500KHz operation. For any intermediary frequency between 500kHz and 1MHz, use the following equation to find the value of REXT value needed for VDD = 5V: ⎛ 1 1⎞ REXT = 90 × ⎜ − ⎟ ⎝ fs 3 ⎠ where REXT is the resistance given in kΩ, and fs is the desired frequency given in MHz. Note that for VDD < 5V, the frequency is reduced slightly, to the extent of about 7% when VDD reaches 3V. This should be taken into consideration when selecting the value for REXT at known supply voltage. Voltage and Current-Limit Setting Both the MAX8520 and MAX8521 provide control of the maximum differential TEC voltage. Applying a voltage to MAXV limits the maximum voltage across the TEC. The voltage at MAXIP and MAXIN sets the maximum positive and negative current through the TEC. These current limits can be independently controlled. 10 Table 1. TEC Connection for Figure 1 TEC Connection Thermistor Heating Mode PTC Cooling Mode NTC Table 2. TEC Connection for Figure 2 TEC Connection Thermistor Heating Mode NTC Cooling Mode PTC Current Monitor Output ITEC provides a voltage output proportional to the TEC current (ITEC). See the Functional Diagram for more detail: VITEC = 1.5V +(8 (VOS1-VCS)) Reference Output The MAX8520/MAX8521 include an on-chip voltage reference. The 1.50V reference is accurate to 1% over temperature. Bypass REF with 0.1µF to GND. REF can be used to bias an external thermistor for temperature sensing as shown in Figures 1 and 2. Thermal and Fault-Current Protection The MAX8520/MAX8521 provide fault-current protection in either FETs by turning off both high-side and low-side FETs when the peak current exceeds 3A in either FETs. In addition, thermal-overload protection limits the total power dissipation in the chip. When the device’s die junction temperature exceeds +165°C, an on-chip thermal sensor shuts down the device. The thermal sensor turns the device on again after the junction temperature cools down by +15°C. Design Procedures Duty-Cycle Range Selection By design, the MAX8520/MAX8521 are capable of operating from 0% to 100% duty cycle, allowing both LX outputs to enter dropout. However, as the LX pulse width narrows, accurate duty-cycle control becomes difficult. This can result in a low-frequency noise appearing at the TEC output (typically in the 20kHz to 50kHz range). While this noise is typically filtered out by the low thermal-loop bandwidth, for best result, operate the PWM with a pulse width greater than 200ns. For 500kHz application, the recommended duty-cycle range is from 10% to 90%. For 1MHz application, it is from 20% to 80%. ______________________________________________________________________________________ Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521 VDD L1 4.7µF LX1 VDD C1 1µF REF C2 1µF CS RSENSE 0.09Ω PVDD1 R2 OS1 C3 1µF RTHER PGND1 C5 10µF U1 PVDD2 MAX8521 C4 1µF OS2 PGND2 L2 4.7µF REF LX2 C6 0.1µF COMP C8 0.1µF C7 1µF VDD MAXIP FREQ MAXIN 49.9kΩ ITEC ON MAXV 100kΩ SHDN CTLI OFF GND 0.022µF 10kΩ 243kΩ 1µF 10µF U3A U2 MAX4475 MAX4477 510kΩ TO REF VDD DAC INPUTS 10kΩ 100kΩ U4 MAX5144 U3B MAX4477 Figure 1. MAX8521 Typical Application Circuit ______________________________________________________________________________________ 11 MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules VDD L1 4.7µF LX1 VDD C1 1µF REF C2 1µF CS RSENSE 0.09Ω PVDD1 R2 OS1 C3 1µF RTHER PGND1 C5 10µF U1 PVDD2 C4 1µF MAX8520 OS2 PGND2 L2 4.7µF REF LX2 C6 0.1µF COMP C7 1µF C8 0.1µF MAXIP FREQ MAXIN 49.9kΩ REXT 60kΩ ITEC MAXV 100kΩ ON SHDN CTLI OFF GND 0.022µF 1kΩ 243kΩ 10µF 10µF U2 50kΩ MAX4238 0.01µF DAC INPUTS VDD REF U4 MAX5144 Figure 2. Typical Application Circuit for the MAX8520 with Reduced Op-Amp Count Configuration 12 ______________________________________________________________________________________ Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521 3/4 VDD 1/4 VDD LX2 -1.2 REF COMP PWM 4X 1.2X gm CTLI RSENSE CCOMP 1 LX1 R R +1.2 0.5X CS 10X OS1 Figure 3. Functional Diagram of the Current-Control Loop Inductor Selection The MAX8520/MAX8521 dual buck converters operate in-phase and in complementary mode to drive the TEC differentially in a current-mode control scheme. At zero TEC current, the differential voltage is zero, hence the outputs with respect to GND are equal to half of VDD. As the TEC current demand increases, one output will go up and the other will go down from the initial point of 0.5VDD by an amount equal to 0.5 VTEC (VTEC = ITEC RTEC). Therefore, the operating duty cycle of each buck converter depends on the operating ITEC and RTEC. Since inductor current calculation for heating and cooling are identical, but reverse in polarity, the calculation only needs to be carried out for either one. For a given inductor, and input voltage, the maximum inductor ripple current happens when the duty cycle is at 50%. Therefore, the inductor should be calculated at 50% duty cycle to find the maximum ripple current. The maximum desired ripple current of a typical standard buck converter is in the range of 20% to 40% of the maximum load. The higher the value of the inductor, the lower the ripple current. However, the size will be physically larger. For the TEC driver the thermal loop is inherently slow, so the inductor can be larger for lower ripple current for better noise and EMI performance. Picking an inductor to yield ripple current of 10% to 20% of the maximum TEC current is a good starting point. Calculate the inductor value as follows: L= (0.25 × VDD ) LIR × ITEC(MAX) × fs where LIR is the selected inductor ripple-current ratio, ITEC(MAX) is the maximum TEC current, and fs is the switching frequency As an example, for VDD = 3.3V, LIR = 12%, and fs = 1MHz, L = 4.58µH Even though each inductor ripple current is at its maximum at 50% duty cycle (zero TEC current), the ripple cancels differentially because each is equal and inphase. Output Filter Capacitor Selection Common-Mode Filter Capacitors The common-mode filter capacitors (C2 and C7 of Figure 1) are used as filter capacitors to ground for each output. The output ripple voltage depends on the capacitance, the ESR of these capacitors, and the inductor ripple current. Ceramic capacitors are recommended for their low ESR and impedance at high frequency. ______________________________________________________________________________________ 13 MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules The output common-mode ripple voltage can be calculated as follows: VRIPPLEpk-pk = LIR x ITEC(MAX) (ESR + 1/8 x C x fs) A 1µF ceramic capacitor with ESR of 10 mΩ with LIR = 12% and ITEC(MAX) = 1.5A will result in VRIPPLE(P-P) of 24.3mV. For size-constraint application, the capacitor can be made smaller at the expense of higher ripple voltage. However, the capacitance must be high enough so that the LC resonant frequency is less than 1/5 the switching frequency: f= 1 2π LC where f is the resonant frequency of the output filter. Differential Mode Filter Capacitor The differential-mode filter capacitor (C5 in Figure 1) is used to bypass differential ripple current through the TEC as the result of unequal duty cycle of each output. This happens when the TEC current is not at zero. As TEC current increases from zero, both outputs move away from the 50% duty-cycle point complementarily. The common-mode ripple decreases, but the differential ripple does not cancel perfectly, and there will be a resulting differential ripple. The maximum value happens when one output is at 75% duty cycle and the other is at 25% duty cycle. At this operating point, the differential ripple is equal to 1/2 of the maximum common-mode ripple. The TEC ripple current determines the TEC performance, because the maximum temperature differential that can be created between the terminals of the TEC depends on the ratio of ripple current and DC current. The lower the ripple current, the closer to the ideal maximum. The differential-mode capacitor provides a lowimpedance path for the ripple current to flow, so that the TEC ripple current is greatly reduced. The TEC ripple current then can be calculated as follows: ITEC(RIPPLE) = (0.5 x LIR x ITEC(MAX)) x (ZC5)/(RTEC + RSENSE + ZC5) where ZC5 is the impedance of C5 at twice the switching frequency, RTEC is the TEC equivalent resistance, and RSENSE is the current-sense resistor. Decoupling Capacitor Selection Decouple each power supply input (V DD , PVDD1, PVDD2) with a 1µF ceramic capacitor close to the supply pins. In applications with long distances between the source supply and the MAX8520/MAX8521, addi14 tional bypassing may be needed to stabilize the input supply. In such cases, a low-ESR electrolytic or ceramic capacitor of 100µF or more at VDD is sufficient. Compensation Capacitor A compensation capacitor is needed to ensure currentcontrol-loop stability (see Figure 3). Select the capacitor so that the unity-gain bandwidth of the current-control loop is less than or equal to 10% the resonant frequency of the output filter: ⎛g ⎞ ⎛ ⎞ 24 × RSENSE CCOMP ≥ ⎜ m ⎟ × ⎜ ⎟ ⎝ fBW ⎠ ⎝ 2π(RSENSE × RTEC ) ⎠ where: fBW = Unity-gain bandwidth frequency, less than or equal to 10% the output filter resonant frequency gm = Loop transconductance, typically 100µA/V CCOMP = Value of the compensation capacitor RTEC = TEC series resistance, use the minimum resistance value RSENSE = Sense resistor Setting Voltage and Current Limits Certain TEC parameters must be considered to guarantee a robust design. These include maximum positive current, maximum negative current, and the maximum voltage allowed across the TEC. These limits should be used to set the MAXIP, MAXIN, and MAXV voltages. Setting Max Positive and Negative TEC Current MAXIP and MAXIN set the maximum positive and negative TEC currents, respectively. The default current limit is ±150mV/RSENSE when MAXIP and MAXIN are connected to REF. To set maximum limits other than the defaults, connect a resistor-divider from REF to GND to set VMAXI_. Use resistors in the 10kΩ to 100kΩ range. VMAXI_ is related to ITEC by the following equations: VMAXIP = 10(ITECP(MAX) RSENSE) VMAXIN = 10(ITECN(MAX) RSENSE) where ITECP(MAX) is the maximum positive TEC current and ITECN(MAX) is the negative maximum TEC current. Positive TEC current occurs when CS is less than OS1: ITEC x RSENSE = OS1 - CS when ITEC > 0A. ITEC RSENSE = CS - OS1 when ITEC < 0A. ______________________________________________________________________________________ Smallest TEC Power Drivers for Optical Modules Setting Max TEC Voltage Apply a voltage to the MAXV pin to control the maximum differential TEC voltage. VMAXV can vary from 0V to V REF . The voltage across the TEC is four times VMAXV and can be positive or negative: |VOS1 - VOS2| = 4 x VMAXV or VDD, whichever is lower Set VMAXV with a resistor-divider between REF and GND using resistors from 10kΩ to 100kΩ. VMAXV can vary from 0V to VREF. Control Inputs/Outputs Output Current Control The voltage at CTLI directly sets the TEC current. CTLI is typically driven from the output of a temperature control loop. The transfer function relating current through the TEC (ITEC) and VCTLI is given by: ITEC = (VCTLI - VREF)/(10 RSENSE) where VREF is 1.50V and: ITEC = (VOS1 - VCS)/RSENSE CTLI is centered around REF (1.50V). ITEC is zero when CTLI = 1.50V. When VCTLI > 1.50V the current flow is from OS2 to OS1. The voltages on the pins relate as follows: VOS2 > VOS1 > VCS The opposite applies when VCTLI < 1.50V current flows from OS1 to OS2: VOS2 < VOS1 < VCS Shutdown Control The MAX8520/MAX8521 can be placed in a power-saving shutdown mode by driving SHDN low. When the MAX8520/MAX8521 are shut down, the TEC is off (OS1 and OS2 decay to GND) and supply current is reduced to 2mA (typ). ITEC Output ITEC is a status output that provides a voltage proportional to the actual TEC current. VITEC = VREF when TEC current is zero. The transfer function for the ITEC output is: VITEC = 1.50V + 8 (VOS1 – VCS) Use ITEC to monitor the cooling or heating current through the TEC. For stability keep the load capacitance on ITEC to less than 150pF. Applications Information The MAX8520/MAX8521 typically drive a thermo-electric cooler inside a thermal-control loop. TEC drive polarity and power are regulated based on temperature information read from a thermistor or other temperaturemeasuring device to maintain a stable control temperature. Temperature stability of +0.01°C can be achieved with carefully selected external components. There are numerous ways to implement the thermal loop. Figures 1 and 2 show designs that employ precision op amps, along with a DAC or potentiometer to set the control temperature. The loop can also be implemented digitally, using a precision A/D to read the thermistor or other temperature sensor, a microcontroller to implement the control algorithm, and a DAC (or filtered-PWM signal) to send the appropriate signal to the MAX8520/MAX8521 CTLI input. Regardless of the form taken by the thermalcontrol circuitry, all designs are similar in that they read temperature, compare it to a set-point signal, and then send an error-correcting signal to the MAX8520/ MAX8521 that moves the temperature in the appropriate direction. PCB Layout and Routing High switching frequencies and large peak currents make PCB layout a very important part of design. Good design minimizes excessive EMI and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Follow these guidelines for good PCB layout: 1) Place decoupling capacitors as close to the IC pins as possible. 2) Keep a separate power ground plane, which is connected to PGND1 and PGND2. PVDD1, PVDD2, PGND1 and PGND2 are noisy points. Connect decoupling capacitors from PVDD_ to PGND_ as direct as possible. Output capacitors C2, C7 returns are connected to PGND plane. 3) Connect a decoupling capacitor from VDD to GND. Connect GND to a signal ground plane (separate from the power ground plane above). Other VDD decoupling capacitors (such as the input capacitor) need to be connected to the PGND plane. 4) Connect GND and PGND_ pins together at a single point, as close as possible to the chip. 5) Keep the power loop, which consists of input capacitors, output inductors and capacitors, as compact and small as possible. ______________________________________________________________________________________ 15 MAX8520/MAX8521 Take care not to exceed the positive or negative current limit on the TEC. Refer to the manufacturer’s data sheet for these limits. 6) To ensure high DC-loop gain and minimum loop error, keep the board layout adjacent to the negative input pin of the integrator (U2 in Figure1) clean and free of moisture. Any contamination or leakage current into this node can act to lower the DC gain of the integrator which can degrade the accuracy of the thermal loop. If space is available, it can also be helpful to surround the negative input node of the integrator with a grounded guard ring. Refer to the MAX8520/MAX8521 evaluation kit for a PCB layout example. Chip Information PROCESS: BiCMOS TOP VIEW BUMPS ON BOTTOM 16 PVDD2 17 CS 18 OS2 + 19 OS1 TOP VIEW 20 PVDD1 Pin Configurations LX1 1 15 LX2 PGND1 2 14 PGND2 SHDN 3 13 FREQ COMP 4 12 VDD ITEC 5 11 GND MAX8520/ MAX8521 6 7 8 9 10 MAXIP MAXV REF CTLI EP MAXIM MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules F6 F5 PVDD2 PVDD2 E6 LX2 F4 CS F3 OS1 F2 F1 PVDD1 PVDD1 E5 LX2 E2 LX1 E1 LX1 D6 D5 D4 D3 D2 D1 PGND2 PGND2 PGND2 PGND1 PGND1 PGND1 C6 OS2 C5 FREQ B6 VDD B5 GND2 A6 GND A5 CTLI C4 GND2 C3 GND2 C2 C1 COMP SHDN B2 GND2 A4 REF A3 MAXV B1 ITEC A2 A1 MAXIP MAXIN + TQFN MAX8521 CONNECT EP TO GND UCSP/WLP Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 16 LAND PATTERN NO. PACKAGE TYPE PACKAGE CODE OUTLINE NO. 20 TQFN-EP T2055+4 21-0140 90-0009 6 x 6 UCSP B36-2 21-0082 Refer to Application Note 1891 36 WLP W363A3+2 21-0024 Refer to Application Note 1891 ______________________________________________________________________________________ Smallest TEC Power Drivers for Optical Modules ON OFF SHDN REF FREQ (MAX8521) REF 3V TO 5.5V VDD PVDD1 MAXV MAX VTEC = VMAXV × 4 OR VDD LX1 MAXIP MAXIN MAX ITEC = (VMAXIP/VREF) × (0.15V/RSENSE) PWM CONTROL AND GATE CONTROL MAX ITEC = (VMAXIN/VREF) × (0.15V/RSENSE) PGND1 CS RSENSE OS1 CS OS2 ITEC OS1 PVDD2 VDD REF CTLI LX2 COMP GND FREQ (MAX8520) MAX8521/ MAX8520 PGND2 ______________________________________________________________________________________ 17 MAX8520/MAX8521 Functional Diagram MAX8520/MAX8521 Smallest TEC Power Drivers for Optical Modules Revision History REVISION NUMBER REVISION DATE 0 10/02 Initial release 1 12/08 Added WLP package to Ordering Information, updated Electrical Characteristics, Absolute Maximum Ratings, Pin Description, and Package Information. 2 2/11 Update Absolute Maximum Ratings, add WLP to Pin Description, update style DESCRIPTION PAGES CHANGED — 1–5, 8, 9, 15–18 1–5, 8, 9, 11, 14–18 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.