19-2390; Rev 0; 4/02 Lowest Jitter Quad PECL-to-ECL Differential Translators The MAX9424–MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications. These devices feature an ultra-low 0.24ps(RMS) random jitter and channel-tochannel skew is less than 90ps in asynchronous mode. The four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. The parts differ from one another by their input and output termination options. The input options are an open input or an internal differential 100Ω termination. The output options are an open-emitter output or a series 50Ω termination. See Ordering Information. The MAX9424–MAX9427 operate from a positive voltage supply of +2.375V to +5.5V, and a negative supply voltage of -2.375V to -5.5V and operate across the extended temperature range of -40°C to +85°C. They are offered in 32-pin 5mm x 5mm TQFP and space-saving 5mm x 5mm QFN packages. Applications Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Base Station ATE Features ♦ 0.24ps RMS Added Random Jitter ♦ 10ps Channel-to-Channel Skew in Synchronous Mode ♦ Guaranteed 500mV Differential Output at 3GHz Clock Frequency ♦ 420ps Propagation Delay in Asynchronous Mode ♦ Functionally Compatible with SK4426 (MAX9424) SK4430 (MAX9425) SK4436 (MAX9426) SK4440 (MAX9427) ♦ Integrated 50Ω Outputs (MAX9425/MAX9427) ♦ Integrated 100Ω Inputs (MAX9426/MAX9427) ♦ Synchronous/Asynchronous Operation Ordering Information INPUT OUTPUT (IN_, (OUT_, OUT_) IN_) MAX9424EHJ -40°C to +85°C 32 TQFP Open Open MAX9424EGJ* -40°C to +85°C 32 QFN Open Open MAX9425EHJ -40°C to +85°C 32 TQFP Open 50Ω MAX9425EGJ* -40°C to +85°C 32 QFN Open 50Ω MAX9426EHJ -40°C to +85°C 32 TQFP 100Ω Open MAX9426EGJ* -40°C to +85°C 32 QFN 100Ω Open MAX9427EHJ -40°C to +85°C 32 TQFP 100Ω 50Ω MAX9427EGJ* -40°C to +85°C 32 QFN 100Ω 50Ω *Future product—contact factory for availability. TEMP RANGE PART PINPACKAGE Pin Configurations OUT0 OUT0 VEE IN1 IN1 27 26 25 25 28 26 VGG IN1 27 29 IN1 28 IN0 VEE 29 30 OUT0 30 IN0 OUT0 31 31 VGG 32 32 IN0 TOP VIEW IN0 TOP VIEW * * VCC 1 24 VGG VCC 24 VGG SEL 2 23 OUT1 SEL 2 23 OUT1 SEL 3 22 OUT1 SEL 3 22 OUT1 CLK 4 21 VEE CLK 4 21 VEE CLK 5 20 VEE EN 6 19 OUT2 EN 7 18 OUT2 VCC 8 17 VGG VEE IN2 IN2 16 OUT3 IN2 OUT3 TQFP (5mm x 5mm) 15 16 IN2 15 14 14 VEE 13 13 12 OUT3 11 VGG IN3 10 IN3 * 9 12 17 VGG 8 OUT3 18 OUT2 11 VCC 19 OUT2 VGG 7 9 6 EN 10 EN 20 VEE IN3 5 MAX9424 MAX9425 MAX9426 MAX9427 IN3 CLK MAX9424 MAX9425 MAX9426 MAX9427 1 * QFN NOTE: CORNER PINS ARE CONNECTED TO VGG. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9424–MAX9427 General Description MAX9424–MAX9427 Lowest Jitter Quad PECL-to-ECL Differential Translators ABSOLUTE MAXIMUM RATINGS VCC to VGG ............................................................-0.3V to +6.0V VGG to VEE.............................................................-0.3V to +6.0V Input Pins to VGG ........................................-0.3V to (VCC + 0.3V) Differential Input Voltage ..............................|VCC - VGG| or 3.0V, whichever is less Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70°C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/°C above +70°C) .................................761mW 32-Pin 5mm x 5mm QFN (derate 21.3mW/°C above +70°C) ...................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin 5mm x 5mm TQFP ........................................+105°C/W 32-Pin 5mm x 5mm QFN............................................+47°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 32-Pin 5mm x 5mm TQFP ..........................................+73°C/W Junction-to-Case Thermal Resistance 32-Pin 5mm x 5mm TQFP ..........................................+25°C/W 32-Pin 5mm x 5mm QFN..............................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (all input pins) ...............................±500V Human Body Model (all output pins) ...............................±2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VGG = 2.375V to 5.5V, VGG - VEE = 2.375V to 5.5V, MAX9424/MAX9426 outputs terminated with 50Ω to VGG - 2.0V, MAX9425/MAX9427 not externally terminated, TA = -40°C to +85°C. Typical values are at VCC - VGG = 3.3V, VGG - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC V INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage VIHD Figure 1 VGG + 1.4 Differential Input Low Voltage VILD Figure 1 VGG Differential Input Voltage VID Figure 1 Input Current Differential Input Resistance (IN_, IN_) IIH, IIL RIN MAX9424/ MAX9425 MAX9426/ MAX9427 VCC 0.2 VCC VGG VCC - VGG < 3.0V 0.2 VCC - VGG ≥ 3.0V 0.2 3.0 -10 25 -10 25 EN, EN, SEL, SEL, IN_, IN_, CLK or CLK = VIHD or VILD EN, EN, SEL, SEL, CLK, or CLK = VIHD or VILD MAX9426/MAX9427 V V µA 86 100 114 Ω OUTPUTS (OUT_, OUT_) Differential Output Voltage VOH - VOL Figure 1 600 635 VGG 1.25 50 VGG 1.05 60 Ω 8 10 mA mA Output Common-Mode Voltage VOCM Figure 1 Output Impedance ROUT MAX9425/MAX9427 VGG 1.50 40 Internal Current Source ISINK MAX9425/MAX9427 6 mV V POWER SUPPLY Positive Supply Current Negative Supply Current 2 ICC IEE (Note 4) 16 27 MAX9424/MAX9426 (Note 4) 100 130 MAX9425/MAX9427 (Note 4) 172 230 _______________________________________________________________________________________ mA Lowest Jitter Quad PECL-to-ECL Differential Translators (VCC - VGG = 2.375V to 5.5V, VGG - VEE = 2.375V to 5.5V, outputs terminated with 50Ω to VGG - 2.0V, EN = VIHD, EN = VILD, fCLK ≤ 3.0GHz, fIN ≤ 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VGG + 1.4V to VCC, VILD = VGG to VCC - 0.2V, VIHD - VILD = 0.2V to smallest of |VCC - VGG| or 3.0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC - VGG = 3.3V, VGG - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25°C, unless otherwise noted.) (Notes 1 and 5) PARAMETER SYMBOL IN_ to OUT_ Differential Propagation Delay CLK to OUT_ Differential Propagation Delay tPLH1 tPHL1 tPLH2 tPHL2 OUT_ to OUT_ Skew tSKD1 OUT_ to OUT_ Skew tSKD2 Maximum Clock Frequency fCLK(MAX) Maximum Data Frequency fIN(MAX) Added Random Jitter tRJ MIN TYP MAX UNITS Figure 3, SEL = high, asynchronous operation CONDITIONS 300 420 570 ps Figure 4, SEL = low, synchronous operation 460 580 730 ps 38 90 ps 10 70 ps SEL = high, asynchronous operation (Note 6) SEL = low, synchronous operation (Note 6) MAX9424/MAX9426, VOH - VOL ≥ 500mV, SEL = low MAX9425/MAX9427, VOH - VOL ≥ 300mV, SEL = low MAX9424/MAX9426, VOH - VOL ≥ 400mV, SEL = high MAX9425/MAX9427, VOH - VOL ≥ 250mV, SEL = high SEL = low, fCLK = 3.0GHz clock, fIN = 1.5GHz (Note 7) 3.0 GHz 2.0 GHz SEL = high, fIN = 2.0GHz (Note 7) Added Deterministic Jitter tDJ SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps 223 - 1 PRBS pattern (Note 7) SEL = high, IN_ = 2.0Gbps 223 - 1 PRBS pattern (Note 7) 0.24 0.8 0.3 0.8 27 80 20 80 ps(RMS) ps(P-P) IN_ to CLK Setup Time tS Figure 4 80 ps CLK to IN_ Hold Time tH Figure 4 80 ps Output Rise Time tR Figure 3 89 120 ps Output Fall Time tF Figure 3 87 120 ps 0.2 1 ps/°C Propagation Delay Temperature Coefficient ∆tPD/∆T Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All outputs open, all inputs biased differential high or low except VCC, VGG, and VEE. Note 5: Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Device jitter added to the input signal. _______________________________________________________________________________________ 3 MAX9424–MAX9427 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (MAX9424: VCC - VGG = 3.3V, VGG - VEE = 3.3V, outputs terminated with 50Ω to VGG - 2.0V, enabled, fCLK = 3.0GHz, fIN = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25°C, unless otherwise noted.) OUTPUT AMPLITUDE (VOH - VOL) vs. IN_ FREQUENCY 50 ICC SEL = HIGH 550 500 450 400 350 0 -40 -15 10 35 0.5 1.0 1.5 2.0 IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE RISE TIME 88 86 3.0 2.5 -40 -15 400 tPLH1 390 380 MAX9424–MAX9427 toc05 410 630 CLK-TO-OUT PROPAGATION DELAY (ps) tPHL1 10 620 610 tPLH2, tPHL2 600 590 580 570 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 35 TEMPERATURE (°C) CLK-TO-OUT PROPAGATION DELAY vs. TEMPERATURE MAX9424–MAX9427 toc04 420 IN-TO-OUT PROPAGATION DELAY (ps) FALL TIME 90 IN_ FREQUENCY (GHz) TEMPERATURE (°C) 4 92 84 0 85 60 MAX9424–MAX9427 toc03 INPUTS BIASED DIFFERENTIALLY HIGH OR LOW, OUTPUTS OPEN 94 MAX9424–MAX9427 toc02 600 OUTPUT AMPLITUDE (mV) IEE 75 25 650 MAX9424–MAX9427 toc01 100 OUTPUT RISE/FALL TIME vs. TEMPERATURE OUTPUT RISE/FALL TIME (ps) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) MAX9424–MAX9427 Lowest Jitter Quad PECL-to-ECL Differential Translators -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Lowest Jitter Quad PECL-to-ECL Differential Translators PIN NAME FUNCTION Positive Supply Voltage. Bypass VCC to VGG with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = 1 and SEL = 0 enables all four channels to operate independently. Setting SEL = 0 and SEL = 1 enables all four channels to be synchronized to CLK. Inverting Differential Select Input 1, 8 VCC 2 SEL 3 SEL 4 CLK Noninverting Differential Clock Input 5 CLK 6 EN 7 EN Inverting Differential Clock Input Noninverting Differential Output Enable Input. Setting EN = 1 and EN = 0 enables all four outputs. Setting EN = 0 and EN = 1 disables all four outputs. Inverting Differential Output Enable Input 9 IN3 Noninverting Differential Input 3 10 11, 17, 24, 30 12 IN3 Inverting Differential Input 3 VGG Ground Reference OUT3 Inverting Differential Output 3 13 OUT3 14, 20, 21, 27 VEE 15 IN2 Noninverting Differential Output 3 Negative Supply Voltage. Bypass from VEE to VGG with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Input 2 16 IN2 Inverting Differential Input 2 18 OUT2 Inverting Differential Output 2 19 OUT2 Noninverting Differential Output 2 22 OUT1 Noninverting Differential Output 1 23 OUT1 Inverting Differential Output 1 25 IN1 Inverting Differential Input 1 26 IN1 Noninverting Differential Input 1 28 OUT0 Noninverting Differential Output 0 29 OUT0 Inverting Differential Output 0 31 IN0 Inverting Differential Input 0 32 IN0 Noninverting Differential Input 0 _______________________________________________________________________________________ 5 MAX9424–MAX9427 Pin Description Lowest Jitter Quad PECL-to-ECL Differential Translators MAX9424–MAX9427 Functional Diagram VCC VGG 11, 17, 24, 30 1, 8 VEE 14, 20, 21, 27 VCC 32 IN0 IN0 1 31 VGG VCC 28 D Q D Q 29 0 CK VCC OUT0 OUT0 VEE CK 26 IN1 IN1 1 25 VGG VCC 22 D Q D Q 23 0 CK OUT1 OUT1 VEE CK VCC 15 IN2 IN2 1 16 VGG VCC 19 D Q D Q 18 0 CK VCC OUT2 OUT2 VEE CK 9 IN3 IN3 1 10 VGG VCC 13 D Q D Q 12 0 CK VCC VEE CK 4 CLK CLK 5 2 SEL SEL MAX9424 MAX9425 MAX9426 MAX9427 3 6 EN EN 7 VGG 6 _______________________________________________________________________________________ OUT3 OUT3 Lowest Jitter Quad PECL-to-ECL Differential Translators VIHD (MAX) VID VGG VID = 0 VOH VILD (MAX) VOH - VOL VOCM VIHD (MIN) VID MAX9424–MAX9427 VCC VOL VID = 0 VGG VEE VILD (MIN) INPUT VOLTAGE DEFINITION (PECL) OUTPUT VOLTAGE DEFINITION (ECL) Figure 1. Input and Output Voltage Definitions IN_ IN_ 100kΩ IN_ IN_ MAX9424/MAX9425 MAX9426/MAX9427 VGG VGG 50Ω OUT_ 50Ω OUT_ OUT_ OUT_ 8mA 8mA VEE MAX9424/MAX9426 MAX9425/MAX9427 Figure 2. Input and Output Configurations Detailed Description The MAX9424–MAX9427 high-speed, low-skew PECL-toECL differential translators are designed for high-speed data and clock driver applications. These devices translate up to four PECL signals to ECL signals. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. A variety of input and output terminations are offered for maximum design flexibility. The MAX9424 has open inputs and open-emitter outputs. The MAX9425 has open inputs and 50Ω series outputs. The MAX9426 has 100Ω differential input impedance and open-emitter outputs. The MAX9427 has 100Ω differential input impedance and 50Ω series outputs. Supply Voltages These devices require a positive voltage supply (connect to VCC), a negative voltage supply (connect to VEE), and a ground reference (connect to VGG). VCC is independent of VEE and therefore the supply voltages do not need to be symmetrical. The PECL input voltages are referenced to VCC, and the ECL output voltages are referenced to VGG. Data Inputs and Outputs The input and output structures are shown in Figure 2. The open inputs of the MAX9424/MAX9425 require external termination, whereas the MAX9426/MAX9427 have integrated 100Ω differential input termination resistors between IN_ and IN_. _______________________________________________________________________________________ 7 MAX9424–MAX9427 Lowest Jitter Quad PECL-to-ECL Differential Translators IN_ VIHD - VILD IN_ tPLH1 tPHL1 OUT_ VOH - VOL OUT_ VOH - VOL 80% OUT_ - OUT_ VOH - VOL 20% DIFFERENTIAL OUTPUT WAVEFORM 80% 20% tR tF SEL = HIGH EN = HIGH Figure 3. IN to OUT Propagation Delay and Transition Timing Diagram CLK VIHD - VILD CLK tH tS tH IN_ VIHD - VILD IN_ tPLH2 tPHL2 OUT_ VIHD - VILD OUT_ SEL = LOW EN = HIGH Figure 4. CLK to OUT Propagation Delay Timing Diagram The MAX9425/MAX9427 have internal 50Ω series-output termination resistors and 8mA internal pulldown current sources, removing the need for external termination. The MAX9424/MAX9426 have open-emitter outputs, which require external termination (see the Output Termination section). Enable Setting EN = high and EN = low enables the device. Alternatively, setting EN = low and EN = high forces the outputs to a differential low; all changes on CLK, SEL, and IN_ are ignored. 8 Asynchronous Operation Setting SEL = high and SEL = low enables the four channels to operate independently. The clock signal is ignored in this mode. When asynchronous mode is selected, drive or bias the CLK and CLK inputs. Biasing the clock inputs properly is shown in Figure 5. This prevents the unused clock inputs from toggling, which eliminates unnecessary switching noise. _______________________________________________________________________________________ Lowest Jitter Quad PECL-to-ECL Differential Translators IN_ IN_ OUT_ OUT_ 100Ω 100Ω OUT_ IN_ OUT_ IN_ 1kΩ 1/4 MAX9424/MAX9425 VGG 1kΩ 1/4 MAX9426/MAX9427 VGG Figure 5. Input Bias Circuits for Unused Inputs Synchronous Operation Power-Supply Bypassing Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode where the buffered inputs are clocked out simultaneously on the rising edge of the differential clock input (CLK and CLK). To have the input signals clocked out on the falling edge, swap the clock lines. Typically, VGG is directly connected to ground. Bypass each VCC pin to VGG with high-frequency surface-mount ceramic 0.01µF capacitors. Place these capacitors as close to the device as possible. Use the same bypass capacitor configuration between each VEE pin and VGG. In high-frequency, high-noise environments, add a 0.1µF capacitor in parallel with each 0.01µF capacitor. Use multiple vias when connecting the bypass capacitors to VGG (ground). This reduces trace inductance, lowering power-supply bounce when drawing high transient currents. Differential Signal Input The maximum input signal magnitude for each of the devices is VCC - VGG or 3.0V, whichever is less. This includes IN_, IN_, CLK, CLK, SEL, SEL, EN and EN. Applications Information Input Bias Bias any unused inputs as shown in Figure 5. This avoids noise coupling that can cause toggling of the unused outputs. Output Termination Terminate the open-emitter outputs (MAX9424/ MAX9426) through 50Ω to VGG - 2V or use equivalent Thevenin terminations. Terminate both outputs of a differential pair and use identical termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT0 is used as a singleended output, terminate both OUT0 and OUT0. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device’s total thermal limits should be observed. Circuit Board Traces Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners, and using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces. Chip Information TRANSISTOR COUNT: 882 PROCESS: Bipolar _______________________________________________________________________________________ 9 MAX9424–MAX9427 VCC VCC MAX9424–MAX9427 Lowest Jitter Quad PECL-to-ECL Differential Translators Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 10 ______________________________________________________________________________________ Lowest Jitter Quad PECL-to-ECL Differential Translators 32L TQFP, 5x5x01.0.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9424–MAX9427 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)