FUJITSU SEMICONDUCTOR DATA SHEET DS05-50101-2E MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 8M (× 8) FLASH MEMORY & 2M (× 8) STATIC RAM MB84VA2000-10/MB84VA2001-10 ■ FEATURES • Power supply voltage of 2.7 to 3.6 V • High performance 100 ns maximum access time • Operating Temperature –20 to +85°C — FLASH MEMORY • Minimum 100,000 write/erase cycles • Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VA2000: Top sector MB84VA2001: Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to "MBM29LV800TA/BA" data sheet in detailed function — SRAM • Power dissipation Operating : 35 mA max. Standby : 50 µA max. • Power down features using CE1s and CE2s • Data retention supply voltage: 2.0 V to 3.6 V Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. MB84VA2000-10/MB84VA2001-10 ■ BLOCK DIAGRAM VCCf VSS A0 to A19 RY/BY A0 to A19 8 M bit Flash Memory RESET CEf DQ0 to DQ7 VCCs VSS A0 to A17 WE OE CE1s CE2s 2 2 M bit Static RAM MB84VA2000-10/MB84VA2001-10 ■ PIN ASSIGNMENTS (Top View) A B C D E F G H 6 CE1s VSS DQ1 A1 A2 A4 CE2s A9 5 A10 DQ5 DQ2 A0 A3 A7 RY/BY A15 4 OE DQ7 DQ4 DQ0 A6 A19 RESET A16 3 A11 A8 A5 N.C. DQ3 N.C. A13 N.C. 2 A14 A18 N.C. CEf N.C. VCCf DQ6 A12 1 WE VCCs A17 VSS N.C. N.C. N.C. N.C. Table 1 Pin Configuration Pin Function Input/ Output A0 to A17 Address Inputs (Common) I A18 to A19 Address Input (Flash) I DQ0 to DQ7 Data Inputs/Outputs (Common) I/O CEf Chip Enable (Flash) I CE1s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I RY/BY Ready/Busy Outputs (Flash) O RESET Hardware Reset Pin/Sector Protection Unlock (Flash) I N.C. No Internal Connection — VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power 3 MB84VA2000-10/MB84VA2001-10 ■ PRODUCT LINE UP Flash Memory Ordering Part No. VCC = 3.0 V +0.6 V –0.3 V SRAM MB84VA2000-10/MB84VA2001-10 Max. Address Access Time (ns) 100 100 Max. CE Access Time (ns) 100 100 Max. OE Access Time (ns) 40 50 ■ BUS OPERATIONS Table 2 User Bus Operations Operation (1), (3) Full Standby CEf CE2s H X X L X X H X X L H X X L H Output Disable X Read from Flash (2) L Write to Flash CE1s L OE WE DQ0 to DQ7 RESET X X HIGH-Z H H H HIGH-Z H L H DOUT H H L DIN H Read from SRAM H L H L H DOUT H Write to SRAM H L H X L DIN H H X Flash Hardware Reset X X X HIGH-Z L X L Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes: 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4 MB84VA2000-10/MB84VA2001-10 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY • One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. • Individual-sector, multiple-sector, or bulk-erase capability. FFFFFH FFFFFH 16K byte 64K byte F0000H FC000H 8K byte 64K byte E0000H FA000H 8K byte 64K byte D0000H F8000H 32K byte 64K byte C0000H F0000H 64K byte 64K byte B0000H E0000H 64K byte 64K byte A0000H D0000H 64K byte 64K byte 90000H C0000H 64K byte 64K byte 80000H B0000H 64K byte 64K byte 70000H A0000H 64K byte 64K byte 60000H 90000H 64K byte 64K byte 50000H 80000H 64K byte 64K byte 40000H 70000H 64K byte 64K byte 30000H 60000H 64K byte 64K byte 20000H 50000H 64K byte 64K byte 10000H 40000H 64K byte 32K byte 08000H 30000H 64K byte 8K byte 06000H 20000H 64K byte 8K byte 04000H 10000H 64K byte 16K byte 00000H 00000H MB84VA2000 Sector Architecture MB84VA2001 Sector Architecture 5 MB84VA2000-10/MB84VA2001-10 Table 3 Sector Address Tables (MB84VA2000) 6 Sector Address A19 A18 A17 A16 A15 A14 A13 Address Range SA0 0 0 0 0 X X X 00000H to 0FFFFH SA1 0 0 0 1 X X X 10000H to 1FFFFH SA2 0 0 1 0 X X X 20000H to 2FFFFH SA3 0 0 1 1 X X X 30000H to 3FFFFH SA4 0 1 0 0 X X X 40000H to 4FFFFH SA5 0 1 0 1 X X X 50000H to 5FFFFH SA6 0 1 1 0 X X X 60000H to 6FFFFH SA7 0 1 1 1 X X X 70000H to 7FFFFH SA8 1 0 0 0 X X X 80000H to 8FFFFH SA9 1 0 0 1 X X X 90000H to 9FFFFH SA10 1 0 1 0 X X X A0000H to AFFFFH SA11 1 0 1 1 X X X B0000H to BFFFFH SA12 1 1 0 0 X X X C0000H to CFFFFH SA13 1 1 0 1 X X X D0000H to DFFFFH SA14 1 1 1 0 X X X E0000H to EFFFFH SA15 1 1 1 1 0 X X F0000H to F7FFFH SA16 1 1 1 1 1 0 0 F8000H to F9FFFH SA17 1 1 1 1 1 0 1 FA000H to FBFFFH SA18 1 1 1 1 1 1 X FC000H to FFFFFH MB84VA2000-10/MB84VA2001-10 Table 4 Sector Address Tables (MB84VA2001) Sector Address A19 A18 A17 A16 A15 A14 A13 Address Range SA0 0 0 0 0 0 0 X 00000H to 03FFFH SA1 0 0 0 0 0 1 0 04000H to 05FFFH SA2 0 0 0 0 0 1 1 06000H to 07FFFH SA3 0 0 0 0 1 X X 08000H to 0FFFFH SA4 0 0 0 1 X X X 10000H to 1FFFFH SA5 0 0 1 0 X X X 20000H to 2FFFFH SA6 0 0 1 1 X X X 30000H to 3FFFFH SA7 0 1 0 0 X X X 40000H to 4FFFFH SA8 0 1 0 1 X X X 50000H to 5FFFFH SA9 0 1 1 0 X X X 60000H to 6FFFFH SA10 0 1 1 1 X X X 70000H to 7FFFFH SA11 1 0 0 0 X X X 80000H to 8FFFFH SA12 1 0 0 1 X X X 90000H to 9FFFFH SA13 1 0 1 0 X X X A0000H to AFFFFH SA14 1 0 1 1 X X X B0000H to BFFFFH SA15 1 1 0 0 X X X C0000H to CFFFFH SA16 1 1 0 1 X X X D0000H to DFFFFH SA17 1 1 1 0 X X X E0000H to EFFFFH SA18 1 1 1 1 X X X F0000H to FFFFFH 7 MB84VA2000-10/MB84VA2001-10 Table 5. 1 Flash Memory Autoselect Code Type A12 A6 A1 A0 Code (HEX) Manufacturer’s Code VIL VIL VIL VIL 04H MB84VA2000 VIL VIL VIL VIH DAH MB84VA2001 VIL VIL VIL VIH 5BH Device Code Table 5. 2 Expanded Autoselect Code Table Code DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04H 0 0 0 0 0 1 0 0 MB84VA2000 DAH 1 1 0 1 1 0 1 0 MB84VA2001 5BH 0 1 0 1 1 0 1 1 Type Manufacturer’s Code Device Code 8 MB84VA2000-10/MB84VA2001-10 Table 6 Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Flash Memory Command Definitions Second Bus Third Bus Write Cycle Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/Reset 1 XXXH F0H Read/Reset 3 555H Autoselect 3 Program — — — — — — — — — — AAH 2AAH 55H 555H F0H RA RD — — — — 555H AAH 2AAH 55H 555H 90H — — — — — — 4 555H AAH 2AAH 55H 555H A0H PA PD — — — — Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0H) Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”). Data (30H) Set to Fast Mode 3 555H AAH 2AAH 55H 555H 20H — — — — — — Fast Program (Note) 2 XXXH A0H PA PD — — — — — — — — Reset from Fast Mode (Note) 2 XXXH 90H XXXH F0H — — — — — — — — Extended Sector Protect 4 XXXH 60H SPA 60H SPA 40H SPA SD — — — — Address bits A11 to A20 = X = “H” or “L” for all address commands except for Program Address (PA) and Sector Address (SA). Bus operations are defined in Table 2. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. RA =Address of the memory location to be read. PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA =Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, and A13 will uniquely select any sector. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. Note:This command is valid while Fast Mode. 9 MB84VA2000-10/MB84VA2001-10 ■ ABSOLUTE MAXIMUM RATINGS Storage Temperature .................................................................................................. –55°C to +125°C Ambient Temperature with Power Applied .................................................................. –25°C to +85°C Voltage with Respect to Ground All pins (Note) .......................................................... –0.3 V to VCCf +0.5 V –0.3 V to VCCs +0.5 V VCCf/VCCs Supply (Note) .............................................................................................. –0.3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negativeovershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf +0.5 V or VCCs +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum rating conditions. Do not exceed these ratings. ■ RECOMMENDED OPERATING RANGES Commercial Devices Ambient Temperature (TA) .........................................................................–20°C to +85°C VCCf/VCCs Supply Voltages.........................................................................+2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 10 MB84VA2000-10/MB84VA2001-10 ■ DC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Unit ILI Input Leakage Current — –1.0 — +1.0 µA ILO Output Leakage Current — –1.0 — +1.0 µA — — 22 — — 12 — — 35 mA ttCYCLE =10 MHz — — 40 mA tCYCLE = 1 MHz — — 12 mA tCYCLE = 10 MHz — — 35 mA tCYCLE = 1 MHz — — 6 mA ICC1f Flash VCC Active Current VCCf = VCC Max., CEf = VIL tCYCLE = 10 MHz (Read) OE = VIH tCYCLE = 5 MHz ICC2f Flash VCC Active Current VCCf = VCC Max., CEf = VIL, OE = VIH (Program/Erase) ICC1s SRAM VCC Active Current VCCs = VCC Max., CE1s = VIL, CE2s = VIH ICC2s SRAM VCC Active Current CE1s = 0.2 V, CE2s = VCCs – 0.2 V, WE = VCCs – 0.2 V ISB1f Flash VCC Standby Current VCCf = VCC Max., CEf = VCCf ± 0.3 V RESET = VCCf ± 0.3 V — — 5 µA ISB2f Flash VCC Standby Current (RESET) VCCf = VCC Max., RESET = VSS ± 0.3 V — — 5 µA ISB1s SRAM VCC Standby Current CE1s = VIH or CE2s = VIL — — 2 mA ISB2s** SRAM VCC Standby Current mA VCCs = 3.0 V ±10% TA = 25°C — 1 2.5 µA TA = –20 to +85°C — — 55 µA VCCs = 3.3 V CE1s = VCC – 0.2 V or CE2s ±0.3 V = 0.2 V TA = 25°C — 1.5 3 µA TA = –20 to +85°C — — 60 µA TA = 25°C — 1 2 µA TA = –20 to +40°C — — 5 µA TA = –20 to +85°C — — 50 µA VCCs = 3.0 V VIL Input Low Level — –0.3 — 0.6 V VIH Input High Level — 2.2 — VCC+0.3* V VOL Output Low Voltage Level IOL = 2.1 mA, VCCf = VCCs = VCC Min. — — 0.4 V VOH Output High Voltage Level IOH = –500 µA, VCCf = VCCs = VCC Min. VCC – 0.5 — — V VLKO Flash Low VCC Lock-Out Voltage 2.3 — 2.5 V — * : VCC indicate lower of VCCf or VCCs ** :During standby mode with CE1s = VCCS – 0.2 V, CE2s should be CE2s < 0.2V or CE2s > VCCS – 0.2V 11 MB84VA2000-10/MB84VA2001-10 ■ AC CHARACTERISTICS • CE Timing Parameter Symbols JEDEC Standard — tCCR Description Test Setup CE Recover Time — Min. • Timing Diagram for alternating SRAM to Flash CEf tCCR tCCR tCCR tCCR CE1s CE2s 12 -10 Unit 0 ns MB84VA2000-10/MB84VA2001-10 • Read Only Operations Characteristics (Flash) Parameter Symbols Description JEDEC Standard tAVAV tRC Read Cycle Time tAVQV tACC tELQV -10 (Note) Test Setup Unit Min. Max. — 100 — ns Address to Output Delay CEf = VIL OE = VIL — 100 ns tCEf Chip Enable to Output Delay OE = VIL — 100 ns tGLQV tOE Output Enable to Output Delay — — 40 ns tEHQZ tDF Chip Enable to Output High-Z — — 30 ns tGHQZ tDF Output Enable to Output High-Z — — 30 ns tAXQX tOH Output Hold Time From Addresses, CEf or OE, Whichever Occurs First — 0 — ns — tREADY RESET Pin Low to Read Mode — — 20 µs Note: Test Conditions–Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 13 MB84VA2000-10/MB84VA2001-10 • Read Cycle (Flash) tRC Addresses Stable ADDRESSES tACC CEf tOE tDF OE tOEH WE tCE HIGH-Z DQ HIGH-Z Output Valid tRC ADDRESSES Addresses Stable tACC tRH RESET tOH DQ 14 HIGH-Z Output Valid MB84VA2000-10/MB84VA2001-10 • Erase/Program Operations (Flash) Parameter Symbols Description JEDEC Standard tAVAV tWC Write Cycle Time tAVWL tAS tAVEL -10 Unit Min. Typ. Max. 100 — — ns Address Setup Time (WE to Addr.) 0 — — ns tAS Address Setup Time (CEf to Addr.) 0 — — ns tWLAX tAH Address Hold Time (WE to Addr.) 50 — — ns tELAX tAH Address Hold Time (CEf to Addr.) 50 — — ns tDVWH tDS Data Setup Time 50 — — ns tWHDX tDH Data Hold Time 0 — — ns — tOES Output Enable Setup Time 0 — — ns — tOEH Output Enable Hold Time Read 0 — — ns Toggle and Data Polling 10 — — ns tGHEL tGHEL Read Recover Time Before Write (OE to CEf) 0 — — ns tGHWL tGHWL Read Recover Time Before Write (OE to WE) 0 — — ns tWLEL tWS WE Setup Time (CEf to WE) 0 — — ns tELWL tCS CEf Setup Time (WE to CEf) 0 — — ns tEHWH tWH WE Hold Time (CEf to WE) 0 — — ns tWHEH tCH CEf Hold Time (WE to CEf) 0 — — ns tWLWH tWP Write Pulse Width 50 — — ns tELEH tCP CEf Pulse Width 50 — — ns tWHWL tWPH Write Pulse Width High 30 — — ns tEHEL tCPH CEf Pulse Width High 30 — — ns tWHWH1 tWHWH1 Byte Programming Operation — 8 — µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) — 1 — sec — — 15 sec — tVCS VCCf Setup Time 50 — — µs — tVLHT Voltage Transition Time (Note 2) 4 — — µs — tVIDR Rise Time to VID (Note 2) 500 — — ns — tRB Recover Time from RY/BY 0 — — ns — tRP RESET Pulse Width 500 — — ns — tRH RESET Hold Time Before Read 200 — — ns — tEOE Delay Time from Embedded Output Enable — — 100 ns — tBUSY Program/Erase Valid to RY/BY Delay — — 90 ns Note : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. 15 MB84VA2000-10/MB84VA2001-10 • Write Cycle (WE control) (Flash) 3rd Bus Cycle Data Polling 555H ADDRESSES tWC PA tAS PA tRC tAH CEf tCH tCS tCO OE tGHWL tWP tFOE tWHWH1 tWPH WE tOH tDS tDH DQ 16 A0H PD DQ7 DOUT DOUT MB84VA2000-10/MB84VA2001-10 • Write Cycle (CEf control) (Flash) 3rd Bus Cycle ADDRESSES Data Polling PA 555H tWC tAS PA tAH WE tWS tWH OE tGHEL tCP tWHWH1 tCPH CEf tDS tDH DQ Notes: 1. 2. 3. 4. 5. A0H PD DQ7 DOUT PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. 17 MB84VA2000-10/MB84VA2001-10 • AC Waveforms Chip/Sector Erase Operations (Flash) 2AAH 555H ADDRESSES tWC tAS 555H 555H SA*1 2AAH tAH CEf tCS tCH OE tGHWL tWP tWPH WE tDS tDH AAH DQ 30H for Sector Erase 55H 80H AAH 55H tVCS VCC Note: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase. 18 10H/ 30H MB84VA2000-10/MB84VA2001-10 • AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tOD tFOE OE tOEH WE tCO * DQ7 DQ7 = Valid Data DQ7 Data In High-Z tWHWH1 or 2 DQ (DQ0 to DQ6) DQ0 to DQ6 = Invalid Data In DQ0 to DQ6 Valid Data High-Z tEOE *DQ7 = Valid Data (The device has completed the Embedded operation.) • AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) CEf tOEH WE tOES OE * DQ6 Data In DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling DQ0 to DQ7 Data Valid tEOE *DQ6 = Stops toggling. (The device has completed the Embedded operation.) 19 MB84VA2000-10/MB84VA2001-10 • RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY • RESET, RY/BY Timing Diagram (Flash) WE RESET tRP tRB RY/BY tREADY • Temporary Sector Unprotection (Flash) VCC tVIDR tVCS tVLHT VID 3V 3V RESET CE WE tVLHT Program or Erase Command Sequence RY/BY Unprotection period 20 tVLHT MB84VA2000-10/MB84VA2001-10 • Extended Sector Protection (Flash) VCC tVCS RESET tVLHT tVIDR Add SPAX SPAX SPAY A0 A1 A6 CE OE TIME-OUT WE Data 60H 60H 40H 01H 60H tOE SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 µs (min) 21 MB84VA2000-10/MB84VA2001-10 • Read Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit 100 — ns tRC Read Cycle Time tAA Address Access Time — 100 ns tCO1 Chip Enable (CE1s) Access Time — 100 ns tCO2 Chip Enable (CE2s) Access Time — 100 ns tOE Output Enable Access Time — 50 ns tCOE Chip Enable (CE1s Low and CE2s High) to Output Active 5 — ns tOEE Output Enable Low to Output Active 0 — ns tOD Chip Enable (CE1s High or CE2s Low) to Output High-Z — 40 ns tODO Output Enable High to Output High-Z — 40 ns tOH Output Data Hold Time 10 — ns • Read Cycle (Note 1) (SRAM) tRC ADDRESSES tAA tOH tCO1 CE1s tCOE tOD tCO2 CE2s tOD tOE OE tOEE tODO tCOE DQ Note: 1. WE remains HIGH for the read cycle. 22 VALID DATA OUT MB84VA2000-10/MB84VA2001-10 • Write Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit tWC Write Cycle Time 100 — ns tWP Write Pulse Width 60 — ns tCW Chip Enable to End of Write 80 — ns tAS Address Setup Time 0 — ns tWR Write Recovery Time 0 — ns tODW WE Low to Output High-Z — 40 ns tOEW WE High to Output Active 0 — ns tDS Data Setup Time 40 — ns tDH Data Hold Time 0 — ns • Write Cycle (Note 4) (WE control) (SRAM) tWC ADDRESSES tAS tWP tWR WE tCW CE1s CE2s DOUT tCW tODW tOEW Note 2 Note 3 tDS DIN Note 5 tDH VALID DATA IN Note 5 Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 23 MB84VA2000-10/MB84VA2001-10 • Write Cycle (Note 4) (CE1s control) (SRAM) tWC ADDRESSES tAS tWP tWR WE tCW CE1s CE2s tCW tCOE tODW DOUT tDS DIN Note 5 tDH VALID DATA IN Note 5 Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 24 MB84VA2000-10/MB84VA2001-10 • Write Cycle (Note 4) (CE2s Control) (SRAM) tWC ADDRESSES tAS tWP tWR WE tCW CE1s CE2s tCW tCOE tODW DOUT tDS DIN Note 5 tDH VALID DATA IN Note 5 Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 25 MB84VA2000-10/MB84VA2001-10 ■ ERASE AND PROGRAMMING PERFORMANCE (Flash) Limits Parameter Unit Comment Min. Typ. Max. Sector Erase Time — 1 15 sec Excludes programming time prior to erasure Byte Programming Time — 8 3,600 µs Excludes system-level overhead Chip Programming Time — 12 50 sec Excludes system-level overhead 100,000 — — cycles Erase/Program Cycle ■ DATA RETENTION CHARACTERISTICS (SRAM) Parameter Symbol Parameter Description Min. Typ. Max. Unit 2.0 — 3.6 V VDH = 3.0 V — — 50* µA VDH = 3.6 V — — 60 µA Chip Deselect to Data Retention Mode Time 0 — — ns Recovery Time 5 — — ms VDH Data Retention Supply Voltage IDDS2 Standby Current tCDR tR * : 5 µA (Max.) at TA = –20°C to +40°C • CE1s Controlled Data Retention Mode (Note 1) VCCs DATA RETENTION MODE 2.7 V See Note 2 See Note 2 VIH CE1s GND 26 VCCS –0.2 V tCDR tR MB84VA2000-10/MB84VA2001-10 • CE2s Controlled Data Retention Mode (Note 3) VCCs DATA RETENTION MODE 2.7 V CE2s VIH tCDR tR VIL 0.2 V GND Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to Vccs+0.3V. 2.When CE1s is operating at the VIH min. level (2.2 V), the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 3. In CE2s controlled data retention mode, input and input/output pins can be used between -0.3V to Vccs+0.3V. ■ PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN = 0 T.B.D T.B.D pF COUT Output Capacitance VOUT = 0 T.B.D T.B.D pF CIN2 Control Pin Capacitance VIN = 0 T.B.D T.B.D pF Note: Test conditions TA = 25°C, f = 1.0 MHz ■ HANDRING OF PACKAGE Please handle this package carefully since the sides of packages are right angle. ■ CAUTION 1. )The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2.) For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector useing "Extended sector protect" command. 27 MB84VA2000-10/MB84VA2001-10 ■ PACKAGE 48-pin plastic FBGA (BGA-48P-M06) ■ PACKAGE DIMENSIONS 48-pin plastic BGA (BGA-48P-M06) Note: The actual shape of coners may differ from the dimension. 11.00±0.15(.433±.006) 1.40±0.20 (.055±.008) 0.30±0.10 (.012±.004) 10.00±0.15 (.394±.006) 7.00±0.15(.276±.006) Ø0.40±0.10 (Ø.016±.004) 5.00±0.15 (.197±.006) 0.15(.006) 1st PIN INDEX C 28 1998 FUJITSU LIMITED MCM-M001-2-3 1.00±0.15 (.039±.006) INDEX Dimension in mm (inches). MB84VA2000-10/MB84VA2001-10 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. http://www.fmap.com.sg/ F9805 FUJITSU LIMITED Printed in Japan 29