Fujitsu MB89135A 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12510-9E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89130/130A Series
MB89131/P131/133A/P133A/135A/
MB89P135A/PV130A
■ DESCRIPTION
The MB89130/130A series has been developed as a general-purpose version of the F2MC*-8L family consisting
of proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such
as timers, a serial interface, an A/D converter, and external interrupts. The MB89130A series also include a
remote control transmitting output and wake-up interrupt function.
* : F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
•
•
•
•
•
•
•
•
•
F2MC-8L family CPU core
Low-voltage operation (when an A/D converter is not used)
Low current consumption (applicable to the dual-clock system)
Minimum execution time : 0.95 µs at 4.2 MHz
21-bit timebase timer
I/O ports : max. 36 ports
External interrupt 1 : 3 channels
External interrupt 2 (wake-up function) : 8 channels (only for the MB89130A series)
8-bit serial I/O : 1 channel
(Continued)
■ PACKAGE
48-pin plastic QFP
48-pin plastic SH-DIP
48-pin ceramic MQFP
(FPT-48P-M13)
(DIP-48P-M01)
(MQP-48C-P01)
MB89130/130A Series
(Continued)
• 8/16-bit timer/counter : 1 channel
• 8-bit A/D converter : 4 channels
• Remote control transmitting frequency generator (for the MB89130A series only)
• Low-power consumption modes (stop, sleep, and watch mode)
• QFP-48 package, SH-DIP-48 package
• CMOS technology
■ PRODUCT LINEUP
Part number
Item
MB89131
MB89133A
ROM size
4 K × 8 bits
(internal mask
ROM)
RAM size
128 × 8 bits
Ports
MB89P133A
Mass-produced products
(mask ROM products)
Classification
CPU functions
MB89135A
8 K × 8 bits
(internal mask
ROM)
16 K × 8 bits
(internal mask
ROM)
One-time PROM products
4 K × 8 bits
8 K × 8 bits
(internal PROM, (internal PROM,
to be
to be
programmed
programmed
with generalwith generalpurpose EPROM purpose EPROM
programmer)
programmer)
256 × 8 bits
The number of instructions :
Instruction bit length :
Instruction length :
Data bit length :
Minimum execution time :
Minimum interrupt processing time :
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.95 µs at 4.2 MHz
8.57 µs at 4.2 MHz
Output ports (N-ch open-drain
ports) :
Output ports (CMOS) :
I/O ports (CMOS) :
4 (All also serve as peripherals.)
Total :
128 × 8 bits
8
24 (8 ports also serve as peripherals. For
MB89130A, 16 ports also serve as.)
36
8/16-bit timer/
counter
8-bit timer/counter × 2 channels or a 16-bit event counter
8-bit serial I/O
8 bits
LSB/MSB first selectable
8-bit A/D converter
MB89P131
8-bit resolution × 4 channels
A/D conversion mode (minimum conversion time : 42 µs at 4.2 MHz)
Sense mode (minimum conversion time : 11.4 µs at 4.2 MHz)
Capable of continuous activation by an internal timer
Reference voltage input
3 independent channels (edge selection, interrupt vector, source flag)
Rising/falling both edges selectable
External interrupt 1
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in the stop
mode.)
(Continued)
2
MB89130/130A Series
Part number
Item
MB89131
MB89133A
MB89135A
MB89P133A
MB89P131
External interrupt 2
(wake-up function)

8 channels (only for level detection)

Remote control
transmitting generator

1 channel
(Pulse width and cycle selectable by program)

Standby mode
Sleep, stop, and clock mode
Process
Operating voltage*
CMOS
2.2 to 4.0 V (with the dual-clock option)
2.2 to 6.0 V (with the single-clock option)
2.7 V to 6.0 V
* : Varies with conditions such as the operating frequency. (See “■ ELECTRICAL CHARACTERISTICS”.)
(Continued)
3
MB89130/130A Series
(Continued)
Part number
MB89P135
MB89PV130A
One-time PROM products
Piggyback/evaluation product
ROM size
16 K × 8 bits
(internal PROM, to be programmed with
general-purpose EPROM programmer)
32 K × 8 bits
(external ROM)
RAM size
512 × 8 bits
1 K × 8 bits
Item
Classification
CPU functions
Ports
The number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Minimum interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, 16 bits
: 0.95 µs at 4.2 MHz
: 8.57 µs at 4.2 MHz
Output ports (N-ch open-drain ports)
Output ports (CMOS)
I/O ports (CMOS)
: 4 (All also serve as peripherals.)
:8
: 24 (8 ports also serve as peripherals. For
MB89130A, 16 ports also serve as
peripherals.)
: 36
Total
8/16-bit timer/
counter
8-bit timer/counter × 2 channels or a 16-bit event counter
8-bit serial I/O
8 bits
LSB/MSB first selectable
8-bit A/D converter
8-bit resolution × 4 channels
A/D conversion mode (minimum conversion time : 42 µs at 4.2 MHz)
Sense mode (minimum conversion time : 11.4 µs at 4.2 MHz)
Capable of continuous activation by an internal timer
Reference voltage input
External interrupt 1
3 independent channels (selectable edge, interrupt vector, source flag)
Rising/falling both edges selectable
Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in the
stop mode.)
External interrupt 2
(wake-up function)
8 channels (only for level detection)
Remote control
transmitting
frequency
generator
1 channel
(Pulse width and cycle selectable by program)
Standby mode
Sleep, stop, and clock mode
Process
Operating voltage
EPROM for use
4
CMOS
2.7 V to 6.0 V
2.7 V to 6.0 V

MBM27C256A-20TVM
MB89130/130A Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89131
MB89133A
MB89135A
MB89P133A
MB89P131
FPT-48P-M13
DIP-48P-M01
×
MQP-48C-P01
×
×
MB89P135A
MB89PV130A
Package
×
×
×
×
×
×
FPT-48P-M13
DIP-48P-M01
×
MQP-48C-P01
×
×
: Available, × : Not available
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that
will actually be used. Take particular care on the following points :
• The number of register banks available is different among the MB89131, MB89133A/135A and MB89P135A/
PV130A.
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• When operated at low speed, the product with an OTPROM will consume more current than the product with
a mask ROM.
However, the same is current consumption in sleep/stop modes. (For more information, see “■ ELECTRICAL
CHARACTERISTICS”.)
• In the case of the MB89PV130A, added is the current consumed by the EPROM which is connected to the
top socket.
3. Mask Options
Functions that can be selected as options and how to designate these options vary with product.
Before using options, check “■ MASK OPITONS”.
Take particular care on the following point :
• P40 to P43 must be set to no pull-up resistor when an A/D converter is used.
• For MB89P135A, pull-up resistor option cannot be set for P40 to P43.
• Each option is fixed on the MB89PV130A.
5
MB89130/130A Series
■ PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
P40/AN0
P41/AN1
P42/AN2
P43/AN3
AVR
AVSS
P30/SCK
P31/SO
P32/SI
P33/EC/SCO
P34/TO/INT0
P35/INT1
(TOP VIEW)
(FPT-48P-M13)
Note : Parenthesized function is available only for the MB89130A series.
6
P36/INT2
P37/BZ/(RCO)
P00/(INT20)
P01/(INT21)
P02/(INT22)
P03/(INT23)
P04/(INT24)
P05/(INT25)
P06/(INT26)
P07/(INT27)
P10
P11
MB89130/130A Series
(TOP VIEW)
VSS
P16
P15
P14
P13
P12
P11
P10
P07/(INT27)
P06/(INT26)
P05/(INT25)
P04/(INT24)
P03/(INT23)
P02/(INT22)
P01/(INT21)
P00/(INT20)
P37/BZ/(RCO)
P36/INT2
P35/INT1
P34/TO/INT0
P33/EC/SCO
P32/SI
P31/SO
P30/SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P17
P20
P21
P22
P23
P24
P25
P26
P27
X1A
X0A
VCC
X1
X0
MOD1
MOD0
RST
AVCC
P40/AN0
P41/AN1
P42/AN2
P43/AN3
AVR
AVSS
(DIP-48P-M01)
Note : Parenthesized function is available only for the MB89130A series.
7
MB89130/130A Series
70
59
68
57
56
55
54
53
77
78
79
80
49
50
51
52
69
70
71
72
73
74
75
61
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P36/INT2
P37/BZ/(RCO)
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10
P11
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
68
67
66
65
64
63
62
61
48
47
46
45
44
43
42
41
40
39
38
37
P40/AN0
P41/AN1
P42/AN2
P43/AN3
AVR
AVSS
P30/SCK
P31/SO
P32/SI
P33/EC/SCO
P34/TO/INT0
P35/INT1
(TOP VIEW)
(MQP-48C-P01)
• Pin assignment on package top
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
49
VPP
57
N.C.
65
O4
73
OE
50
A12
58
A2
66
O5
74
N.C.
51
A7
59
A1
67
O6
75
A11
52
A6
60
A0
68
O7
76
A9
53
A5
61
O1
69
O8
77
A8
54
A4
62
O2
70
CE
78
A13
55
A3
63
O3
71
A10
79
A14
56
N.C.
64
VSS
72
N.C.
80
VCC
N.C. : Internally connected. Do not use.
8
MB89130/130A Series
■ PIN DESCRIPTION
Pin no.
Pin name
SH-DIP*1
QFP*2
35
5
X0
36
6
X1
38
8
X0A
39
9
X1A
33
3
MOD0
34
4
MOD1
32
Circuit
type
Function
A
Main clock crystal oscillator pins (max. 4.2 MHz)
B
Subclock crystal oscillator pins (32.768 kHz)
C
Operation mode selecting pins
Connect directly to VSS.
D
Reset I/O pin
This pin is of N-ch open-drain output type with pull-up resistor, and a hysteresis input type. The internal circuit is
initialized by the input of “L”. “L” is output from this pin by
an internal reset source as a option.
2
RST
16 to 9
34 to 27
P00 (INT20)
to
P07 (INT27)
I
General-purpose I/O ports
On the MB89130A series, these ports also serve as an external interrupt input.
External interrupt inputs are of hysteresis input type.
8 to 2, 48
26 to 20, 18
P10 to P17
E
General-purpose I/O ports
47 to 40
17 to 10
P20 to P27
G
General-purpose output ports
24
42
P30/SCK
F
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O. This
port is of hysteresis input type.
23
41
P31/SO
F
General-purpose I/O port
Also serves as a 8-bit serial I/O data output. This port is of
hysteresis input type.
22
40
P32/SI
F
General-purpose I/O port
Also serves as a 8-bit serial I/O data input. This port is of
hysteresis input type.
F
General-purpose I/O port
Also serves as the external clock input for the 8-bit
timer/counter. This port is of hysteresis input type. The
system clock output is provided as an option.
21
39
P33/EC/SCO
20
38
P34/TO/INT0
F
General-purpose I/O port
Also serve as the overflow output for the 8-bit timer/
counter and an external interrupt input. This port is of hysteresis input type.
19,
18
37,
36
P35/INT1,
P36/INT2
F
General-purpose I/O ports
Also serves as an external interrupt input. These ports are
of hysteresis input type.
*1 : DIP-48P-M01
*2 : FPT-48P-M13
(Continued)
9
MB89130/130A Series
(Continued)
Pin no.
SH-DIP*1
QFP*2
Circuit
type
Function
17
35
P37/BZ/ (RCO)
F
General-purpose I/O port
Also serves as a buzzer output. This port is of hysteresis
input type. On the MB89130A series, this port also serves
as a remote control output.
30 to 27
48 to 45
P40/AN0 to
P43/AN3
H
N-ch open-drain output ports
Also serve as an analog input for the A/D converter.
37
7
VCC

Power supply pin
1
19
VSS

Power supply (GND) pin
31
1
AVCC

A/D converter power supply pin
Use this pin at the same voltage as VCC.
26
44
AVR

A/D converter reference voltage input pin
25
43
AVSS

A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1 : DIP-48P-M01
*2 : FPT-48P-M13
10
Pin name
MB89130/130A Series
• External EPROM pins (MB89PV130A only)
Pin no.
Pin name
I/O
Function
49
VPP
O
“H” level output pin
50
51
52
53
54
55
58
59
60
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
61
62
63
O1
O2
O3
I
Data input pins
64
VSS
O
Power supply (GND) pin
65
66
67
68
69
O4
O5
O6
O7
O8
I
Data input pins
70
CE
O
ROM chip enable pin
Outputs “H” during standby.
71
A10
O
Address output pin
73
OE
O
ROM output enable pin
Outputs “L” at all times.
75
76
77
78
79
A11
A9
A8
A13
A14
O
Address output pins
80
VCC
O
EPROM power supply pin
56
57
72
74
N.C.

Internally connected pins
Be sure to leave them open.
11
MB89130/130A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Crystal or ceramic oscillation type (main clock)
Circuit for the MB89P133A/P131/P135A/PV130A
External clock input selecting versions of MB89131/
133A/135A
Oscillation feedback resistor of approximately
1 MΩ/5 V
X1
X0
Standby control signal
A
• Crystal or ceramic oscillation type (main clock)
Crystal or ceramic oscillation selecting versions of
MB89131/133A/135A
Oscillation feedback resistor of approximately
1 MΩ/5 V
X1
X0
Standby control signal
• Crystal and ceramic oscillation type (subclock)
Circuit for the MB89131/133A/135A
Oscillation feedback resistor of approximately
4.5 MΩ/5 V
X1A
X0A
Standby control signal
B
• Crystal and ceramic oscillation type (subclock)
Circuit for the MB89P131/P133A/P135A/PV130A
Oscillation feedback resistor of approximately
4.5 MΩ/5 V
X1A
X0A
Standby control signal
C
• Output pull-up resistor (P-ch) of approximately
50 kΩ/5 V
• Hysteresis input
R
P-ch
D
N-ch
(Continued)
12
MB89130/130A Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• CMOS input
R
P-ch
E
N-ch
• Pull-up resistor optional
• CMOS output
• Hysteresis input
R
P-ch
F
N-ch
• Pull-up resistor optional
• CMOS output
P-ch
G
N-ch
R
• N-ch open-drain output
• Analog input
P-ch
H
N-ch
Analog input
• CMOS output
• CMOS input
• The interrupt input is a hysteresis input (available
only for the MB89130A series) .
P-ch
P-ch
I
• Pull-up resistor optional
N-ch
Interrupt input
Only for MB89130A series
• Pull-up resistor optional
13
MB89130/130A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the
voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC
is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz)
and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when
power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
7. Turning on the supply voltage (only for the MB89P135A)
Power on sharply up to the option enabling voltage (2 V) within 13 clock cycles after starting of oscillation.
14
MB89130/130A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P131
The MB89P131 is an OTPROM version of the MB89131.
1. Features
• 4-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address
0000H
Single chip
EPROM mode
(Corresponding addresses on the EPROM programmer)
I/O
0080H
00C0H
Not available
RAM
0140H
0000H
Not available
F000H
Not available
7000H
PROM
4 KB
FFFFH
EPROM
32 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P131 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer for the MBM27C256A.
(2) Load program data into the EPROM programmer at 7000H to 7FFFH (note that addresses F000H to FFFFH
while operating as a single chip correspond to 7000H to 7FFFH in EPROM mode) .
(3) Program with the EPROM programmer.
15
MB89130/130A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P133A
The MB89P133A is an OTPROM version of the MP89133A.
1. Features
• 8-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address
Single chip
0000H
EPROM mode
(Corresponding addresses on the EPROM programmer)
I/O
0080H
RAM
0180H
Not available
0000H
Not available
E000H
6000H
PROM
8 KB
FFFFH
EPROM
32 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P133A functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer for the MBM27C256A.
(2) Load program data into the EPROM programmer at 6000H to 7FFFH (note that addresses E000H to FFFFH
while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode) .
(3) Program with the EPROM programmer.
16
MB89130/130A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P135A
The MB89P135A is an OTPROM version of the MB89133A/135A.
1. Features
• 16-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address
Single chip
0000H
EPROM mode
(Corresponding addresses on the EPROM programmer)
I/O
0080H
RAM
0280H
Not available
8000H
0000H
Vacancy
(Read value FFH)
Not available
BFF0H
3FF0H
Option area
Not available
BFF6H
3FF6H
Vacancy
(Read value FFH)
Not available
C000H
4000H
PROM
16 KB
FFFFH
EPROM
16 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P135A functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer for the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH
while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode) .
(3) Load option data into the EPROM programmer at 3FF0H to 3FF6H.
(4) Program with the EPROM programmer.
17
MB89130/130A Series
4. Setting OTPROM Options (MB89P135A Only)
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map :
• OTPROM option bit map
AdBit 7
Bit 6
dress
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Clock
mode
selection
1 : Single
clock
0 : Dual
clock
Reset pin
output
1 : Yes
0 : No
Power-on
reset
1 : Yes
0 : No
00 : 22/FCH 10 : 216/FCH
01 : 212/FCH 11 : 218/FCH
P05
Pull-up
1 : Yes
0 : No
P04
Pull-up
1 : Yes
0 : No
P03
Pull-up
1 : Yes
0 : No
P02
Pull-up
1 : Yes
0 : No
P01
Pull-up
1 : Yes
0 : No
P00
Pull-up
1 : Yes
0 : No
P16
Pull-up
1 : No
0 : Yes
P15
Pull-up
1 : Yes
0 : No
P14
Pull-up
1 : Yes
0 : No
P13
Pull-up
1 : Yes
0 : No
P12
Pull-up
1 : Yes
0 : No
P11
Pull-up
1 : Yes
0 : No
P10
Pull-up
1 : Yes
0 : No
P37
Pull-up
1 : Yes
0 : No
P36
Pull-up
1 : Yes
0 : No
P35
Pull-up
1 : Yes
0 : No
P34
Pull-up
1 : Yes
0 : No
P33
Pull-up
1 : Yes
0 : No
P32
Pull-up
1 : Yes
0 : No
P31
Pull-up
1 : Yes
0 : No
P30
Pull-up
1 : Yes
0 : No
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Readable
and
writable
Vacancy
Vacancy
Vacancy
Readable
and
writable
Readable
and
writable
3FF1H
P07
Pull-up
1 : Yes
0 : No
P06
Pul-up
1 : Yes
0 : No
3FF2H
P17
Pull-up
1 : No
0 : Yes
3FF3H
3FF0H Readable
and
writable
3FF4H Readable
and
writable
Vacancy
3FF5H Readable
and
writable
Vacancy
3FF6H Readable
and
writable
Oscillation
stabilization time
Note : Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is selected.
18
Bit 0
MB89130/130A Series
■ HANDLING THE MB89P131/P133A/P135A
1. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150 °C, 48 h
Data verification
Assembly
2. Programming Yield
Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test.
For this reason, a programming yield of 100% cannot be assured at all times.
3. EPROM Programmer Socket Adapter
Part no.
Package
Compatible socket adapter
Sun Hayato Co., Ltd.
Recommended programmer manufacturer
and programmer name
Minato Electronics Inc.
1890A
MB89P131PF
MB89P133APFM
MB89P133AP
QFP-48
ROM-48QF2-28DP-8L
SH-DIP-48
ROM-48SD-28DP-8L2
Recommended


Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403
FAX (81) -3-5396-9106
Minato Electronics Inc. : TEL : USA (1) -916-348-6066
JAPAN (81) -45-591-5611
19
MB89130/130A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato
Co., Ltd.) listed below :
Package
Socket adapter part number
LCC-32 (Square)
ROM-32LC-28DP-S
Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403
FAX (81) -3-5396-9106
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM is diagrammed below.
Address
Single chip
Corresponding addresses on the EPROM programmer
0000 H
I/O
0080 H
RAM
0480 H
Not available
8000 H
0000 H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
4. Programming to the EPROM
(1)
(2)
(3)
20
Set the EPROM programmer for the MBM27C256A.
Load program data into the EPROM programmer at 0000H to 7FFFH.
Program with the EPROM programmer.
MB89130/130A Series
■ BLOCK DIAGRAM
X0A
X1A
Main clock oscillator
Timebase timer
Clock controller
Reset circuit
(WDT)
Subclock oscillator
(32.768 kHz)
8
RST
8-bit timer/counter
P34/TO/INT0
8-bit timer/counter
P33/EC/SCO
CMOS I/O port
Ports 0 and 1
8
P00/ (INT20)
to P07/ (INT27)
Internal bus
X0
X1
External interrupt 2*
(wake-up function)
P30/SCK
P32/SI
P31/SO
8-bit serial I/O
Port 3
P10 to P17
P35/INT1
8
P20 to P27
Port 2
External interrupt 1
P36/INT2
Remote control*
transmitting
frequency generator
CMOS output port
Buzzer output
P37/BZ/(RCO)
CMOS I/O port
F2MC-8L
CPU
N-ch open-drain output port
8-bit A/D converter
4
Port 4
RAM
4
P40/AN0
to P43/AN3
AVR
ROM
AVCC
AVSS
The other pins
MOD0, MOD1, VCC, VSS
* : Only for the MB89130A series.
Note : Parenthesized pin function is only for the MB89130A series.
21
MB89130/130A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89130/130A series offer a memory space of 64 Kbytes for storing all of I/O, data,
and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately
above the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is allocated from exactly the opposite end, that is, near the highest address. The tables of
interrupt reset vectors and vector call instructions are allocated from the highest address within the program
area. The memory space of the MB89130/130A series is structured as illustrated below.
• Memory Space
MB89P133A
MB89133A
MB89P131
MB89131
0000 H
0000 H
007F H
00C0 H
Vacancy
0000 H
I/O
I/O
I/O
0000 H
I/O
I/O
007F H
007F H
007F H
0080 H
0080 H
0080 H
0080 H
RAM
256 B
00FF H
0100 H
Register
013F H
0140 H
0000 H
MB89PV130A
007F H
RAM
128 B
0100 H
MB89P135A
MB89135A
RAM
256 B
00FF H
0100 H
Register
017F H
0180 H
RAM
512 B
00FF H
0100 H
Register
017F H
0180 H
RAM
1 KB
00FF H
0100 H
Register
01FF H
0200 H
Register
01FF H
0200 H
027F H
0280 H
Vacancy
Vacancy
Vacancy
Vacancy
047F H
0480 H
Vacancy
BFFF H
C000 H
EFFF H
F0 00 H
FFFF H
22
DFFF H
E000 H
ROM
4 KB
FFFF H
BFFF H
C000 H
FFFF H
External
ROM
32 KB
ROM
16 KB
ROM
16 KB
ROM
8 KB
7FFF H
8000 H
FFFF H
FFFF H
MB89130/130A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose
memory registers. The following registers are provided :
Program counter (PC) :
A 16-bit register for indicating the instruction storage positions.
Accumulator (A) :
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T) : A 16-bit register which is used for arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is
used.
Index register (IX) :
A 16-bit register for index modification
Extra pointer (EP) :
A 16-bit pointer for indicating a memory address
Stack pointer (SP) :
A 16-bit pointer for indicating a stack area
Program status (PS) :
A 16-bit register for storing a register pointer, a condition code
16 bits
Initial value
FFFDH
: Program counter
PC
A
: Accumulator
Indeterminate
T
: Temporary accumulator
Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
PS
: Program status
I-flag = 0, IL1, 0 = 11
The other bit values are Indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR) . (See the diagram below.)
• Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
23
MB89130/130A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and
bits for control of CPU operations at the time of an interrupt.
H-flag :
I-flag :
IL1, 0 :
N-flag :
Z-flag :
V-flag :
C-flag :
24
Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.
Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’.
Cleared to ‘0’ at the reset.
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level
is higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low
Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.
Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.
Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
‘0’ otherwise.
Set to the shift-out value in the case of a shift instruction.
MB89130/130A Series
The following general-purpose registers are provided :
General-purpose registers : An 8-bit resister for storing data
The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 8 banks can be used on the MB89131/P131 and a total of 16 banks can be used
on the MB89133A/P133A/135A and a total of 32 banks can be used on the MB89P135A/PV130A. The bank
currently in use is indicated by the register bank pointer (RP) .
• Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
8 banks (MB89131/P131)
16 banks (MB89133A/P133A/135A)
32 banks (MB89P135A/PV130A)
Memory area
25
MB89130/130A Series
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
Vacancy
06H
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Timebase timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
BZCR
Buzzer register
10H
Vacancy
11H
Vacancy
12H
(R/W)
SCGC
13H
Peripheral control clock register
Vacancy
14H
(R/W)
RCR1
Remote control transmitting control register 1*
15H
(R/W)
RCR2
Remote control transmitting control register 2*
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
Vacancy
1FH
Vacancy
(Continued)
26
MB89130/130A Series
(Continued)
Address
Read/write
Register name
Register description
20H
(R/W)
ADC1
A/D converter control register 1
21H
(R/W)
ADC2
A/D converter control register 2
22H
(R/W)
ADCD
A/D converter data register
23H
(R/W)
EIC1
External interrupt 1 control register 1
24H
(R/W)
EIC2
External interrupt 1 control register 2
25H
Vacancy
26H to 31H
Vacancy
32H
(R/W)
EIE2
External interrupt 2 enable register*
33H
(R/W)
EIF2
External interrupt 2 flag register*
34H to 7BH
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
* : Only for the MB89130A series
Note : Do not use vacancies.
27
MB89130/130A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Program voltage
Symbol
Value
Unit
Max.
VCC
AVCC
VSS − 0.3
VSS + 7.2
V
*
AVR
VSS − 0.3
VSS + 7.2
V
AVR must not exceed VCC + 0.3 V
VPP
VSS − 0.6 VSS + 13.0
V
Only for the MB89P131/P133A/
P135A
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
“L” level maximum output current
IOL

10
mA
“L” level average output current
IOLAV

4
mA
“L” level total maximum output current
ΣIOL

100
mA
“L” level total average output current
ΣIOLAV

20
mA
“H” level maximum output current
IOH

–10
mA
“H” level average output current
IOHAV

–2
mA
“H” level total maximum output current
ΣIOH

–30
mA
ΣIOHAV

–10
mA
Power consumption
PD

200
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
“H” level total average output current
Storage temperature
Remarks
Min.
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
* : Use AVCC and VCC set to the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
MB89130/130A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min.
Max.
2.2*
6.0*
V
Normal operation assurance range*
MB89131/133A/135A
2.7*
6.0*
V
Normal operation assurance range*
MB89P131/P133A/135A/PV130A
1.5
6.0
V
Retains the RAM state in the stop mode
AVR
2.0
AVCC
V
TA
−40
+85
°C
VCC
AVCC
* : These values vary with the operating frequencies and the analog assurance range. See Figure 1 and 2, and
“5. A/D Converter Electrical Characteristics.”
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
(MB89P131/P133A/P135A/PV130A, and single-clock MB89131/133/133A/135/135A)
Operating voltage (V)
6
5
Operation assurance range
4
3
2
1
1
2
3
4
Main clock oprating frequency (at an instruction cycle of 4/FCH) (MHz)
4.0
2.0
1.0
Minimum execution time (Instruction cycle) (µs)
Note : The shaded area is assured only for the MB89131/133/133A/135/135A.
29
MB89130/130A Series
Figure 2 Operating Voltage vs. Main Clock Operating Frequency
(Dual-clock MB89131/133/133A/135/135A)
Operating voltage (V)
6
5
4
Operation assurance range
3
2
1
1
2
3
4
Main clock oprating frequency (at an instruction cycle of 4/FCH) (MHz)
4.0
2.0
1.0
Minimum execution time (Instruction cycle) (µs)
Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
30
MB89130/130A Series
3. DC Characteristics
Parameter
“H” level
input voltage
“L” level
input voltage
Open-drain
output pin
applied
voltage
“H” level
output voltage
“L” level
output voltage
Input leakage
current
(Hi-z output
leakage current)
Pull-up
resistance
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin
Condition
Value
Min.
Typ.
Max.
0.7 VCC

VCC +
0.3
Unit
VIH
P00 to P07,
P10 to P17
VIHS
RST,
P30 to P37,
INT20 to
INT27
0.8 VCC

VCC +
3.0
V
VIL
P00 to P07,
P10 to P17
VSS −
0.3

0.3 VCC
V
VILS
RST,
P30 to P37
INT20 to
INT27
VSS −
0.3

0.2 VCC
V
VD
P40 to P43
VCC −
0.3

VCC +
0.3
V
VOH
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37
IOH = −2.0 mA
2.4


V
VOL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P43
IOL = 1.8 mA


0.4
V
VOL2
RST
IOL = 4.0 mA


0.6
V
P00 to P07,
P10 to P17,
P20 to P27,
0.0 V < VI < VCC
P30 to P37,
P40 to P43,
MOD0, MOD1


±5
µA
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P43,
RST
25
50
100
kΩ
ILI1
RPULL

VI = 0.0 V
Remarks
V
INT20 to INT27
are available
only for the
MB89130A series.
INT20 to INT27
are available
only for the
MB89130A series.
Without pull-up
resistor
(Continued)
31
MB89130/130A Series
(Continued)
Parameter
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin
Value
Remarks
Typ.
Max.

4
7
mA
MB89131/
133A/135A

6
10
mA
MB89P131/
P133A/P135A

2
5
mA

50
100
µA
MB89131/
133A/135A

1
3
mA
MB89P131/
P133A/P135A
FCL = 32.768 kHz
VCC = 3.0 V
Subclock sleep
mode

25
50
µA
ICCT
FCL = 32.768 kHz
VCC = 3.0 V
• Watch mode
• Main clock stop
mode in dualclock system


15
µA
ICCH
TA = +25 °C
• Subclock stop
mode
• Main clock stop
mode in singleclock system


1
µA
IA
AVCC
FCH = 4 MHz,
when A/D
conversion is operating

1
3
mA
IAH
AVCC
FCH = 4 MHz,
TA = +25 °C,
when A/D
conversion is not
operating


1
µA
CIN
Other than
AVCC, AVSS,
VCC, and VSS
f = 1 MHz

10

pF
FCH = 4.00 MHz
VCC = 5.0 V
tinst*2 = 1.0 µs
ICCS1
FCH = 4.00 MHz
VCC = 5.0 V
tinst*2 = 1.0 µs
Main clock sleep
mode
ICCL
FCL = 32.768 kHz
VCC = 3.0 V
Subclock mode
ICCLS
VCC (External
clock operation)
Power supply
current*1
*1 : The power supply current is measured at the external clock.
*2 : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”
32
Unit
Min.
ICC1
Input
capacitance
Condition
MB89130/130A Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
tZLZH

RST “L” pulse width
Value
Min.
Max.
48 tHCYL*

Unit
Remarks
ns
* : tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
tZLZH
0.8 VCC
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition

Value
Unit
Remarks
Min.
Max.

50
ms
Power-on reset function only
1

ms
Due to repeated operations
Note : Make sure that power supply rises within the oscillation stabilization time selected.
For example, when the main clock is operating at 3 MHz (FCH) and the oscillation stabilization time selecting
option has been set to 212/FCH, the oscillation stabilization time is 1.4 ms. Therefore, the maximum value of
power supply rising time is about 1.4 ms.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be
varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
VCC
0.2 V
0.2 V
0.2 V
33
MB89130/130A Series
(3) Clock Timing
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin
FCH
Value
Unit
Remarks
Min.
Typ.
Max.
X0, X1
1

4.2
MHz Main clock
FCL
X0A, X1A

32.768

kHz
tHCYL
X0, X1
238

1000
ns
Main clock
tLCYL
X0A, X1A

30.5

µs
Subclock
Input clock pulse width
PWH1
PWL1
X0
30


ns
External clock
Input clock rising/falling time
tCR1
tCF1
X0


24
ns
External clock
Input clock frequency
Clock cycle time
Subclock
• X0 and X1 Timing and Conditions of Applied Voltage
tHCYL
PWH1
PWL1
tCF1
X0
0.8 VCC
0.8 VCC
0.2 VCC
tCR1
0.8 VCC
0.2 VCC
• Main Clock Conditions
When a crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
FCH
C0
34
C1
Open
FCH
MB89130/130A Series
• X0A and X1A Timing and Conditions of Applied Voltage
tLCYL
0.8 VCC
0.8 VCC
X0A
• Subclock Conditions
When a crystal
or
ceramic resonator is used
X0A
When a single-clock option is used
X1A
X0A
X1A
Open
Rd
FCL
C0
C1
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
Symbol
Value
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH) tinst = 1.0 µs when operating at
FCH = 4 MHz
2/FCL
µs
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
tinst
35
MB89130/130A Series
(5) Recommended Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Family) for Main Clock Oscillation Circuit
X0
X1
R
∗1
C1∗
C2 ∗ 2
2
Frequency Dumping
FAR part number*1
(MHz)
resistor
(built-in capacitor type)
Temperature
Loading
characteristics of
FAR frequency
capacitors*2
(TA = −20 °C to +60 °C)
1000 Ω
±0.5%
±0.5%
510 Ω
±0.5%
±0.5%

±0.5%
±0.5%
1 kΩ
±0.5%
±0.5%
750 Ω
±0.5%
±0.5%

±0.5%
±0.5%

±0.5%
±0.5%

±0.5%
±0.5%
FAR-C4 B-04194- 00
4.194

Inquiry : FUJITSU MEDIA DEVICES LIMITED
±0.5%
±0.5%
FAR-C4CC-02000-L00
2.00
FAR-C4 C-02000- 20
FAR-C4 A-03000- 20
3.00
FAR-C4 A-04000- 01
FAR-C4 A-04000- 21
FAR-C4CB-04000-M00
FAR-C4 B-04000- 00
36
Initial deviation of
FAR frequency
(TA = +25 °C)
4.00
Built-in
MB89130/130A Series
• Sample Application of Ceramic Resonator for Main Clock Oscillation Circuit
X0
X1
R
∗
C1
• Mask ROM products
Resonator
manufacturer*
Kyocera Corporation
C2
Resonator
KBR-4.0MKS
Frequency (MHz)
C1 (pF)
C2 (pF)
R
4.00
33
33
Not required
Matsushita Electronic
EFOV4004B
Components Co,. Ltd.
4.00
CSBF1000J
1.00
100
6.8 kΩ
30
30
Not required
CST4.00MGW
Built-in
Built-in
Not required
CSA4.00MGU
30
30
Not required
Built-in
Built-in
Not required
100
100
Not required
CST4.00MGWU040
Built-in
Built-in
Not required
CSTCS4.00MG
Built-in
Built-in
Not required
CSTCS4.00MGWOC5
Built-in
Built-in
Not required
Built-in
Built-in
Not required
CST4.00MGWU
CSA4.00MGU040
TDK Corporation
1.5 kΩ
100
CSA4.00MG
Murata Mfg. Co., Ltd.
33 (Built-in) 33 (Built-in)
CCR4.0MC3
4.00
4.00
(Continued)
37
MB89130/130A Series
(Continued)
• One-time PROM products
Resonator
Resonator
manufacturer*
C1 (pF)
C2 (pF)
R
100
100
Not required
Built-in
Built-in
Not required
CSA4.00MG
30
30
Not required
CSA4.00MGU
30
30
Not required
Built-in
Built-in
Not required
100
100
Not required
CST4.00MGWU040
Built-in
Built-in
Not required
CSTCS4.00MG
Built-in
Built-in
Not required
CSA3.00MG040
CST3.00MGW040
Murata Mfg. Co., Ltd.
CST4.00MGWU
CSA4.00MGU040
Frequency (MHz)
3.00
4.00
Inquiry : Kyocera Corporation
• AVX Corporation
North American Sales Headquarters : TEL 1-803-448-9411
• AVX Limited
European Sales Headquarters : TEL 44-1252-770000
• AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters : TEL 852-363-3303
Matsushita Electronic Components Co., Ltd.
• North America
Panasonic Industrial Co. : TEL 1-201-348-7000
• Canada
Matsushita Electric of Canada Ltd. : TEL 905-238-2436
• Europe
Panasonic Industrial Europe (Continental) : TEL 49-40-8549-2048
Panasonic Industrial Europe (Nlederlassung Munchen) : TEL 49-89-4800-7150
• Asia
Panasonic Industry of Asia, Company : TEL 65-299-8400
Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc. : TEL 1-404-436-1300
• Murata Europe Management GmbH : TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd. : TEL 65-758-4233
TDK Corporation
• TDK Corporation of America
Chicago Regional Office : TEL 1-708-803-6100
• TDK Electronics Europe GmbH
Components Division : TEL 49-2102-9450
• TDK Singapore (PTE) Ltd. : TEL 65-273-5022
• TDK Hongkong Co., Ltd. : TEL 852-736-2238
• Korea Branch, TDK Corporation : TEL 82-2-554-6633
38
MB89130/130A Series
• Sample Application of Crystal Resonator for Subclock Oscillation Circuit
X0A
X1A
Rd
∗
C1
C2
• Mask ROM products
Resonator manufacturer*
SII
Inquiry :
Resonator
Frequency (kHz)
C1 (pF)
C2 (pF)
Rd (kΩ)
DS-VT-200
32.768
24
24
680
SII
• Seiko Instruments Inc. (Japan) : TEL 81-43-211-1219
• Seiko Instruments U.S.A. Inc. : TEL 310-517-7770
• Seiko Instruments GmbH : TEL 49-6102-297-122
(6) Serial I/O Timing
(VCC = +5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
Parameter
Condition
Internal shift
clock mode
SCK
SCK ↓ → SO time
tSLOV
Valid SI → SCK ↑
tIVSH
External shift
SCK, SO
clock mode
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Value
Unit
Min.
Max.
2 tinst*

µs
−200
200
ns
200

ns
200

ns
1 tinst*

µs
1 tinst*

µs
0
200
ns
200

ns
200

ns
Remarks
* : For information on tinst, see “ (4) Instruction Cycle.”
39
MB89130/130A Series
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
• External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
40
MB89130/130A Series
(7) Peripheral Input Timing
(VCC = +5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin
Condition
Peripheral input “H” level pulse width 1
tILIH1
Peripheral input “L” level pulse width 1
tIHIL1
EC,
INT0 to INT2

Value
Unit Remarks
Min.
Max.
2 tinst*

µs
2 tinst*

µs
* : For information on tinst, see “ (4) Instruction Cycle.”
tIHIL1
EC,
INT0 to INT2
tILIH1
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
41
MB89130/130A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FCH = 3 MHz, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin
Condition
Typ.
Max.


8
bit


±1.5
LSB


±1.0
LSB


±0.9
LSB
AVSS −
1.0 LSB
AVSS +
0.5 LSB
AVSS +
2.0 LSB
mV
AVR −
3.0 LSB
AVR −
1.5 LSB
AVR
mV


0.5
LSB

44 tinst*

µs

12 tinst*

µs


10
µA
0

AVR
V
2.0

AVCC
V
AVR = AVCC = 5.0 V,
when A/D conversion
is operating

100
300
µA
AVR = AVCC = 5.0 V,
when A/D conversion
is not operating


1
µA
Total error
Linearity error

Differential
linearity error
Zero transition
voltage
Full-scale transition
voltage
AVR = AVCC
VOT
—
VFST
Interchannel
disparity
A/D mode
conversion time

Sense mode
conversion time
Analog port input
current
IAIN
Analog input
voltage

Reference voltage

AN0
to
AN3
IR
AVR
Reference voltage
supply current
IRH
Unit
Min.
AVR = AVCC = 5.0 V
Resolution
Value

Remarks
1LSB =
AVR/256
* : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable by the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28 = 256.
• Linearity error (unit : LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit : LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
42
MB89130/130A Series
• Total error (unit : LSB)
The difference between theoretical and actual conversion values
Digital output
1111 1111
1111 1110
Theoretical conversion value
Actual conversion value
1 LSB =
(1 LSB × N + VOT)
AVR
256
Linearity error =
Differential linearity error =
Linearity error
Total error =
0000 0010
0000 0001
0000 0000
VOT
VNT V(N+1)T
VFST
VNT − (1 LSB × N + VOT)
1 LSB
V(N+1)T − VNT
1 LSB
−1
VNT − (1 LSB × N + 1 LSB)
1 LSB
Analog input
43
MB89130/130A Series
7.
Notes on Using A/D Converter
• lnput impedance of the analog input pins
The A/D converter used for the MB89130/130A series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ) .
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.
0.1 µF for the analog input pin.
• Analog Input Equivalent Circuit
Analog input pin
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
Sample hold circuit
.
C =. 28 pF
.
R =. 9 kΩ
Close for 8 instruction cycles after starting
A/D conversion.
Analog channel selector
• Error
The smaller the | AVR − AVSS |, the greater the error would become relatively.
44
Comparator
MB89130/130A Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
(2) “H” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
VOL (V)
VCC – VOH (V)
VCC = 2.2 V
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
TA = +25 °C
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
VIN (V)
5.0
4.5
TA = +25 °C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
VCC = 2.2 V
1.1
1.0 TA = +25 °C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.5 −1.0 −1.5 −2.0
0.0
VIN (V)
5.0
4.5
TA = +25 °C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1
2
0
4
5
6
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
−2.5
−3.0
IOH (mA)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
3
VCC = 2.5 V
7
VCC (V)
VIN vs. VCC
VIHS
VILS
3
4
5
6
7
VCC (V)
VIHS : Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS : Threshold when input voltage in hysteresis
characteristics is set to “L” level
(5) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25 °C
300
100
50
10
0
1
2
3
4
5
6
7
VCC (V)
45
MB89130/130A Series
(6) Power Supply Current (External Clock)
ICC1 vs. VCC
ICCS1 vs. VCC
ICC (mA)
5.0
4.5
4.0
Divide by 4(ICC1)
FCH = 4.0 MHz
TA = +25 °C
ICCS1 (mA)
3
2.5
3.5
FCH = 4.0 MHz
TA = +25 °C
Divide by 4(ICCS1)
Divide by 64
2
3.0
2.5
1.5
2.0
Divide by 64
1.5
1.0
1
0.5
0.5
0.0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VCC (V)
TA = +25 °C
180
140
35
120
30
100
25
80
20
60
15
40
10
20
5
2.5
3
3.5
4
4.5
3
3.5
4
4.5
5
5.5
6
6.5
VCC (V)
5
5.5
6
6.5
VCC (V)
TA = +25 °C
45
40
2
2.5
ICCLS (µA)
50
160
0
1.5
2
ICCLS vs. VCC
ICCL vs. VCC
ICCL (µA)
200
0.0
1.5
0
1.5
2
2.5
3
ICCT vs. VCC
3.5
4
4.5
5
5.5
6
6.5
VCC (V)
IR vs. AVR
ICCT (µA)
30
TA = +25 °C
25
IR (µA)
200
TA = +25 °C
180
160
140
20
120
15
100
80
10
60
40
5
20
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VCC (V)
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
AVR (V)
(Continued)
46
MB89130/130A Series
(Continued)
IA (mA)
5.0
4.5
4.0
ICCH vs. VCC
IA vs. AVCC
ICCH (µA)
2.0
FCH = 4 MHz
TA = +25 °C
1.8
1.6
3.5
1.4
3.0
1.2
2.5
1.0
2.0
0.8
1.5
0.6
1.0
0.4
0.5
0.2
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVCC (V)
TA = +25 °C
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V)
47
MB89130/130A Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1
Symbol
dir
off
ext
#vct
#d8
#d16
dir: b
rel
@
A
AH
AL
T
TH
TL
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
×
(×)
(( × ))
Instruction Symbols
Meaning
Direct address (8 bits)
Offset (8 bits)
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
48
MB89130/130A Series
Table 2
Mnemonic
Transfer Instructions (48 instructions)
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Note: During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
49
MB89130/130A Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
(Continued)
50
MB89130/130A Series
(Continued)
Mnemonic
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
~
#
Operation
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
51
L
52
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
9
A
B
C
D
E
F
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
R7
R6
R5
R4
R3
R2
R1
R0
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
rel
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
8
A
A
SETC
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
CMPW
CMP
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
7
F
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6
dir: 6,rel A,@IX +d @IX +d,A
IX,#d16
A,IX
E
6
D
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
C
5
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
A
A
DIVU
SETI
9
4
8
RORC
7
3
6
ROLC
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89130/130A Series
■ INSTRUCTION MAP
MB89130/130A Series
■ MASK OPTIONS
Part number
MB89131
MB89133A
MB89135A
MB89P131
MB89P133A
Specifying procedure
Specify when
ordering masking
Specify when
ordering masking
Specify when
ordering masking
Selectable by pin
(P40 to P43 must be
fixed to no pull-up
resistor option when
an A/D converter is
used.)
Selectable by pin
(P40 to P43 must be
fixed to no pull-up
resistor option when
an A/D converter is
used.)
No.
1
Pull-up resistors
•P00 to P07, P10 to P17,
•P30 to P37, P40 to P43
Selectable by pin
(P40 to P43 must be
fixed to no pull-up
resistor option when
an A/D converter is
used.)
2
Power-on reset
•Power-on reset provided
•No power-on reset
Selectable
Selectable
Selectable
3
Selection of oscillation stabilization
time
•The oscillation stabilization time initial value is selectable from 4 types
Selectable
given below.
0 : Oscillation stabilization 22/FCH
1 : Oscillation stabilization 212/FCH
2 : Oscillation stabilization 216/FCH
3 : Oscillation stabilization 218/FCH
Selectable
Selectable
4
Reset pin output
•Reset output enabled
•Reset output disabled
Selectable
Selectable
Selectable
5
Clock mode selection
•Single-clock mode
•Dual-clock mode
Selectable
Selectable
Selectable
6
Selection of oscillation circuit type
•Crystal or ceramic oscillation type Selectable
•External clock input type
Selectable
Not required*1
7
Peripheral control clock output function*2
•Not used
•Used
Not required*3
Not required*3
Selectable
*1 : Both external clock and oscillation resonator can be used on the OTPROM product.
*2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output.
*3 : The peripheral control clock output function can be used only by software.
53
MB89130/130A Series
No.
Part number
MB89P135A
MB89PV130A
Specifying procedure
Set with EPROM programmer
Setting not possible
1
Pull-up resistors
•P00 to P07, P10 to P17,
•P30 to P37, P40 to P43
Selectable by pin
All pins fixed to no pull-up resis(P40 to P43 must be fixed to no
tor option
pull-up resistor option.)
2
Power-on reset
•Power-on reset provided
•No power-on reset
Selectable
3
Selection of oscillation stabilization
wait time
•The oscillation stabilization time initial value is selectable from 4 types
given below.
Selectable
0 : Oscillation stabilization 22/FCH
1 : Oscillation stabilization 212/FCH
2 : Oscillation stabilization 216/FCH
3 : Oscillation stabilization 218/FCH
Oscillation stabilization 218/FCH
4
Reset pin output
•Reset output enabled
•Reset output disabled
Selectable
Reset output enabled
5
Selection of clock mode selection
•Single-clock mode
•Dual-clock mode
Selectable
Dual-clock mode
6
Selection of oscillation circuit type
•Crystal or ceramic oscillation type Not required*1
•External clock input type
Not required*1
7
Peripheral control clock output function*2
•Not used
•Used
Not required*3
Not required*3
Power-on reset provided
*1 : Both external clock and oscillation resonator can be used.
*2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output.
*3 : The peripheral control clock output function can be used only by software.
54
MB89130/130A Series
■ MB89P131/P133A STANDARD OPTIONS
No.
Product option
MB89P131-101
MB89P133A-201
1
Pull-up resistor
Not provided for any port
Not provided for any port
2
Power-on reset
Provided
Provided
3
Selection of oscillation stabiliza2 : Oscillation stabilization 216/FCH
tion time
2 : Oscillation stabilization 216/FCH
4
Reset pin output
Enabled
Disabled
5
Selection of clock mode
Dual-clock mode
Dual-clock mode
■ ORDERING INFORMATION
Part number
MB89131PFM
MB89133APFM
MB89135APFM
MB89P131PFM-101
MB89P133APFM-201
MB89P135APFM
Package
Remarks
48-pin Plastic QFP
(FPT-48P-M13)
MB89133AP
MB89P133AP-201
48-pin Plastic SH-DIP
(DIP-48P-M01)
MB89PV130ACF-ES
48-pin Ceramic MQFP
(MQP-48C-P01)
55
MB89130/130A Series
■ PACKAGE DIMENSION
48-pin Plastic QFP
(FPT-48P-M13)
13.10±0.40 SQ
(.516±.016)
10.00±0.20 SQ
(.394±.008)
36
2.35(.093)MAX
(Mounting height)
0(0)MIN
(STAND OFF)
25
37
Details of "A" part
24
0.15(.006)
8.80
(.346)
REF
INDEX
11.50±0.30
(.453±.012)
0.20(.008)
0.18(.007)MAX
0.53(.021)MAX
"A"
48
13
Details of "B" part
LEAD No.
1
0.80(.0315)TYP
12
0.30±0.10
(.012±.004)
0.16(.006)
M
0.15±0.05
(.006±.002)
0~10°
"B"
0.80±0.30
(.031±.012)
0.10(.004)
C
1994 FUJITSU LIMITED F48023S-1C-1
Dimensions in mm (inches)
(Continued)
56
MB89130/130A Series
48-pin Plastic SH-DIP
(DIP-48P-M01)
+0.20
43.69 –0.30
+.008
1.720 –.012
INDEX-1
13.80±0.25
(.543±.010)
INDEX-2
0.51(.020)MIN
5.25(.207)
MAX
0.25±0.05
(.010±.002)
3.00(.118)
MIN
+0.50
1.00 –0
+.020
.039 –0
0.45±0.10
(.018±.004)
15.24(.600)
TYP
15°MAX
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
40.894(1.610)REF
1994 FUJITSU LIMITED D48002S-3C-3
Dimensions in mm (inches)
(Continued)
57
MB89130/130A Series
(Continued)
48-pin Ceramic MQFP
(MQP-48C-P01)
17.20(.677)TYP
PIN No.1 INDEX
15.00±0.25
(.591±.010)
14.82±0.35
(.583±.014)
1.50(.059)TYP
8.80(.346)REF
1.00(.040)TYP
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
+0.13
10.92 –0.0
+.005
.430 –0
7.14(.281) 8.71(.343)
TYP
TYP
PAD No.1 INDEX
0.30(.012)TYP
+0.45
4.50(.177)TYP
1.10 –0.25
+.018
.043 –.010
0.40±0.08
(.016±.003)
0.60(.024)TYP
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches)
58
MB89130/130A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
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Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://www.fujitsu.co.jp/
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Tel: +1-408-922-9000
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FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
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FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0008
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
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applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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