Fujitsu MB89193AHP 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12512-7E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89190/190A Series
MB89191/193/195/P195/PV190
MB89191A/191AH/193A/193AH/195A/P195A/PV190A
■ OUTLINE
The MB89190/190A series microcontrollers contain various resources such as timers, serial interfaces, A/D
converters, external interrupts, and remote-control functions, as well as an F2MC*-8L CPU core for low-voltage
and high-speed operations. These single-chip microcontrollers are suitable for small devices such as remote
controllers with compact packages.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time: 0.95 µs at 4.2 MHz (VCC = 2.7 V)
• F2MC-8L family CPU core
• Two timers
8/16-bit timer/counter
20-bit timebase counter
• Serial interface
8-bit synchronous serial (Selectable transfer direction allows communication with various equipment.)
(Continued)
■ PACKAGE
28-pin Plastic SOP
28-pin Plastic DIP
28-pin Plastic SH-DIP
48-pin Ceramic MQFP
(FPT-28P-M17)
(DIP-28P-M05)
(DIP-28P-M03)
(MQP-48C-P01)
MB89190/190A Series
(Continued)
• External interrupts
Edge detection (Selectable edge): 3 channels
Low-level interrupt (Wake-up function): 8 channels
• A/D converter (MB89190A series only)
8-bit successive approximation type: 8 channels
• Built-in remote-control transmitting frequency generator
• Low-power consumption modes
Stop mode (Almost no current consumption occurs because oscillation stops.)
Sleep mode (The current consumption is reduced about 1/3 of that during normal operation because the CPU
stops.)
• Packages
SOP-28, SH-DIP-28, and DIP-28
■ PRODUCT LINEUP
Part number
Item
MB89191
MB89191A
MB89191AH
MB89193
MB89193A
MB89193AH
MB89195
MB89195A
Classification
Mask ROM products
ROM size
4 K × 8 bits
(internal mask
ROM)
RAM size
128 × 8 bits
16 K × 8 bits
(internal mask
ROM)
MB89PV190
MB89PV190A
One-time
product
For
development
and evaluation
16 K × 8 bits
32 K × 8 bits
(internal PROM, (external ROM)
to be
programmed
with generalpurpose
EPROM
programmer)
256 × 8 bits
CPU functions
The number of basic instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
Ports
Output port (N channel open drain): 4 (also serves as peripherals for MB89190A
series)or 6 (for MB89190 series)
I/O port (CMOS):
16 (also serves as peripherals)
Total:
20 or 22
Timer counter
2
8 K × 8 bits
(internal mask
ROM)
MB89P195
MB89P195A
136
8 bits
1 to 3 bytes
1, 8, and 16 bits
0.95 µs at 4.2 MHz
8.57 µs at 4.2 MHz
2 channels of 8-bit timer counter or one 16-bit event counter (operation clock: 1.9 µs, 30.4
µs, and 487.6 µs at 4.2 MHz, and external clock)
Serial I/O
8 bits
LSB/MSB first selectable
Transfer clock (external, 1.9 µs, 7.6 µs, 30.4 µs at 4.2 MHz)
A/D converter
(MB89190A series
only)
8 bits x 8 channels
A/D conversion mode (conversion time: 41.9 µs at 4.2 MHz)
Sense mode (conversion time: 11.9 µs at 4.2 MHz)
Capable of continuous activation by an internal timer.
Reference voltage input
(Continued)
MB89190/190A Series
(Continued)
Part number
Item
External interrupt 1
MB89191
MB89191A
MB89191AH
MB89193
MB89193A
MB89193AH
MB89195
MB89195A
MB89P195
MB89P195A
MB89PV190
MB89PV190A
3 independent channels (selectable edge, interrupt vector, and interrupt source flag)
Rising/falling/both edge selectable
Used for wake-up from stop/sleep mode. (Edge detection is also permitted in the stop
mode.)
External interrupt 2
(Wake-up function)
8 channels (low-level interrupt only)
Remote-control
transmitting
frequency generator
The pulse width and cycle are software-programmable.
Standby mode
Sleep mode and stop mode
Process
CMOS
Operating voltage*
2.2 V to 6.0 V
2.7 V to 6.0 V
EPROM for use
MBM27C256A20TVM
* : Varies with conditions such as operating frequencies (see “■ Electrical Characteristics.”) It differs from the
operating voltage of an A/D converter.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89191
MB89191A
MB89191AH
MB89193
MB89193A
MB89193AH
MB89195
MB89195A
Package
MB89P195
MB89P195A
×
DIP-28P-M05
×
DIP-28P-M03
: Available
×
×
FPT-28P-M17
MQP-48C-P01
MB89PV190
MB89PV190A
×
×
*
× : Not available
* : A socket (manufacturer: Sun Hayato Co., Ltd.) for pin pitch conversion is available.
48QF-28SOP-8L: (MQP-48C-P01) → for conversion to FPT-28P-M17
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
Note: For more information on each package, see “■ Package Dimensions.”
3
MB89190/190A Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback model, verify its difference from the model that will actually be used.
Take particular care on the following points:
• On the MB89191/191A, addresses 0140H to 0180H cannot be used for register banks.
• The stack area, etc., is set in the upper limit of the RAM.
2. Current Consumption
• In the case of MB89PV190/PV190A, added is the current consumed by the EPROM which is connected to
the top socket.
• When operated at low speed, the products with an OTPROM (EPROM) will consume more current than the
products with a mask ROM.
However, the same is current consumption in the sleep/stop mode. (For more information, see “■ Electrical
Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary with product.
Before using options, check “■ Mask Options.”
Take particular care on the following points:
• Pull-up resistor optional cannot be set for P00 to P03, and P40 to P45 on the MB89191A/193A/195A/P195A.
• The power-on reset option is fixed as “enabled” for MB89P195/P195A.
• Options are fixed on the MB89PV190/PV190A.
4. MB89191AH/MB89193AH
MB89191AH/193AH are “L” level heavy output current drive type of P30 to P32 and P40 to P43 of MB89191A/
193A.Characteristics other than “L” level output of P30 to P32 and P40 to P43 are the same as MB89191A/193A.
4
MB89190/190A Series
■ PIN ASSIGNMENT
TOP VIEW
P04/INT24
1
28
VCC
P05/INT25
2
27
P03/INT23/AN7
P06/INT26
3
26
P02/INT22/AN6
P07/INT27
4
25
P01/INT21/AN5
TEST
5
24
P00/INT20/AN4
RST
6
23
P45/AVR
X0
7
22
P44/AVSS
X1
8
21
P43/AN3
VSS
9
20
P42/AN2
P37/BZ/RCO
10
19
P41/AN1
P36/INT12
11
18
P40/AN0
P35/INT11
12
17
P30/SCK
P34/TO/INT10
13
16
P31/SO
P33/EC
14
15
P32/SI
FPT–28P–M17
DIP–28P–M03
DIP–28P–M05
5
MB89190/190A Series
P35/INT11
N. C.
N. C.
N. C.
N. C.
N. C.
VSS
N. C.
N. C.
N. C.
N. C.
N. C.
48
47
46
45
44
43
42
41
40
39
38
37
68
67
66
65
64
63
62
61
(Top view)
P34/TO/INT10
1
P33/EC
2
P32/SI
3
69
P31/SO
4
70
P30/SCK
5
71
Each pin inside the dashed line
is for MB89PV190/PV190A
units only.
36
N. C.
35
N. C.
60
34
P36/INT12
59
33
P37/BZ/RCO
58
32
X1
57
31
X0
56
30
RST
74
55
29
TEST
P43/AN3
9
75
54
28
P07/INT27
P44/AVSS
10
76
53
27
P06/INT26
P45/AVR
11
26
P05/INT25
P00/INT20/AN4
12
25
P04/INT24
13
14
15
16
17
18
19
20
21
22
23
24
P01/INT21/AN5
N. C.
N. C.
N. C.
N. C.
V CC
N. C.
N. C.
N. C.
N. C.
P02/INT22/AN6
P03/INT23/AN7
52
8
51
P42/AN2
50
73
49
7
80
P41/AN1
79
72
78
6
77
P40/AN0
(MQP-48C-P01)
• Pin assignment on the package top (MB89PV190/PV190A only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
49
VPP
57
N.C.
65
O4
73
OE
50
A12
58
A2
66
O5
74
N.C.
51
A7
59
A1
67
O6
75
A11
52
A6
60
A0
68
O7
76
A9
53
A5
61
O1
69
O8
77
A8
54
A4
62
O2
70
CE
78
A13
55
A3
63
O3
71
A10
79
A14
56
N.C.
64
VSS
72
N.C.
80
VCC
N.C.: Internally connected. Do not use.
6
MB89190/190A Series
■ PIN DESCRIPTION
Pin no.
Pin name
SOP*1, DIP*2
SH-DIP*3
MQFP*4
7
31
X0
8
32
X1
5
29
6
Circuit
type
Function
A
Clock oscillation pins
TEST
B
Test input pin
Connect directly to VSS.
30
RST
C
Reset I/O pin
This pin consists of an N-ch open-drain output with
a pull-up resistor and of hysteresis input. A low
level is output from this pin by internal source. The
internal circuit is initialized by the input of a low
level.
24 to 27
12
13,
23,
24
P00/INT20/
AN4 to P03/
INT23/AN7
G
General-purpose I/O ports
Also serve as external interrupt input pins. In the
MB89190A series, also serve as analog input pins.
External interrupt input is of hysteresis input type.
1 to 4
25 to 28
P04/INT24 to
P07/INT27
D
General-purpose I/O ports
Also serve as external interrupt input.
External interrupt input is of hysteresis input type.
17
5
P30/SCK
D
General-purpose I/O port
Also serves as clock I/O for the 8-bit serial I/O
interface.
The serial I/O clock input is of hysteresis input type
with a built-in noise filter.
16
4
P31/SO
E
General-purpose I/O port
Also serves as a serial I/O data output pin.
15
3
P32/SI
D
General-purpose I/O port
Also serves as a serial I/O data input pin.
The serial I/O data input is of hysteresis input type
with a built-in noise filter.
14
2
P33/EC
D
General-purpose I/O port
Also serves as an external clock input pin for the 8bit timer/counter.
External clock input of the 8-bit timer/counter is
hysteresis input type with a built-in noise filter.
13
1
P34/TO/
INT10
D
General-purpose I/O port
Also serves as the overflow output and external
interrupt input for the 8-bit timer/counter.
External interrupt input is of hysteresis input type
with a built-in noise filter.
*1:
*2:
*3:
*4:
FPT-28P-M17
DIP-28C-M05
DIP-28P-M03
MQP-48C-P01
(Continued)
7
MB89190/190A Series
(Continued)
Pin no.
MQFP*4
12
48
P35/INT11
11
34
P35/INT12
10
33
18 to 21
6 to 9
23
*1:
*2:
*3:
*4:
8
Pin name
SOP*1, DIP*2
SH-DIP*3
Circuit
type
Function
D
General-purpose I/O port
Also serve as external interrupt input pins.
External interrupt input is of hysteresis input type
with a built-in noise filter.
P37/BZ/RCO
E
General-purpose I/O port
Also serves as a buzzer output pin and remotecontrol output pin.
P40/AN0 to
P43/AN3
F
N-ch open-drain output ports
Also serve as analog input pins for the A/D
converter.
11
P45/AVR
F
In the MB89190A series, also serves as a
reference voltage input pin for the A/D converter.
In the MB89190 series, serves as an N-ch opendrain output port.
22
10
P44/AVSS
F
In the MB89190A series, also serves as a power
pin for the A/D converter, and should be applied the
same voltage as VSS to.
In the MB89190 series, also serves as an N-ch
open-drain output port.
28
18
VCC
—
Power supply pin
9
42
VSS
—
Power supply (GND) pin
FPT-28P-M17
DIP-28P-M05
DIP-28P-M03
MQP-48C-P01
MB89190/190A Series
• External EPROM pins (MB89PV190/PV190A)
Pin no.
Pin name
I/O
Function
49
VPP
O
“H” level output pin
79
78
50
75
71
76
77
51
52
53
54
55
58
59
60
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
61
62
63
65
66
67
68
69
O1
O2
O3
O4
O5
O6
O7
O8
I
Data input pins
70
CE
O
ROM chip enable pin
Outputs “H” during standby.
73
OE
O
ROM output enable pin
Outputs “L” at all times.
80
VCC
O
EPROM power pin
64
VSS
O
Power supply (GND) pin
9
MB89190/190A Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• Oscillation feedback registor of approximately
1 MΩ at 5 V
X1
X0
• When crystal and ceramic oscillators are selected
optionally
Standby control signal
X1
X0
• When CR oscillation is selected optionally
Standby control signal
B
C
• Output pull-up resistor (P-ch): Approx. 50 kΩ at 5 V
• Hysteresis input
R
P-ch
N-ch
D
• CMOS output
• CMOS input
• Hysteresis input (resource input)
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(Continued)
10
MB89190/190A Series
(Continued)
Type
Circuit
Remarks
E
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
F
• N-ch open-drain output
• Analog input
R
Pch
Nch
Analog input
G
• Pull-up resistor optional (MB89190 series only)
•
•
•
•
R
P-ch
CMOS output
CMOS input
Hysteresis input (resource input)
Analog input
P-ch
N-ch
Analog input
• Pull-up resistor optional (MB89190 series only)
11
MB89190/190A Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input or output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC to VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC=DAVC=VCC and AVSS=AVR=VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the
voltage could cause malfunctions within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
release from stop mode.
12
MB89190/190A Series
■ PROGRAMMING TO PROM ON THE MB89P195/P195A
The MB89P195/P195A can program data in the internal PROM using a dedicated conversion adaptor and
specified general-purpose EPROM programmer.
1. Memory Space
Address in normal operation mode
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000 H
I/O
0080 H
RAM
0180 H
8000 H
Not available
0000 H
Vacancy
(Read value FFH)
C000 H
4000 H
PROM
16 K
FFFF H
EPROM
16 K
7FFF H
• Programming procedure
(1) Load program data into the ROM programmer at addresses 4000H to 7FFFH. (Addresses 0C000H to 0FFFFH
in the operation mode correspond to 4000H to 7FFFH in ROM programmer. See the illustration above.)
(2) Set the data at addresses 0000H to 3FFFH of the programmer ROM in the ROM programmer, to FFH.
(3) Program in the successive-address write mode of the ROM programmer.
Note: Program must be started at the address 00000H.
For details, contact our Sales Division.
13
MB89190/190A Series
2. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcontroller program.
Program, verify
Aging
+150°C for 48 Hrs.
Data verification
Assembly
3. Programming Yield
Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming
yield of 100% cannot be assured at all times.
4. EPROM Programmer Socket Adapter
Recommended programmer manufacturer
and programmer name
Part no.
MB89P195
MB89P195A
MB89P195PF
MB89P195APF
Package
Compatible
socket
adapter
Sun Hayato
Co., Ltd.
Minato
Electronics Inc.
MODEL1890A
(ver.2.2)
+
OU-910
(ver.4.1)
UNISITE
(ver.5.0 or
later)
3900
(ver.2.8 or
later)
DIP-28
ROM-28DP28DP-8L
Recommended
Recommended
SOP-28
ROM-28SOP28DP-8L
Recommended
Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Minato Electronics Inc.: TEL: USA (1)-916-348-6066
JAPAN (81)-45-591-5611
Data I/O Co., Ltd.:TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
14
Data I/O Co., Ltd.
2900
(ver.3.8 or
later)
MB89190/190A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the EPROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) below.
Package
Adapter socket part number
LCC-32
ROM-32LC-28DP-YS
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
3. Memory Space
Address in normal operation mode
Address when writing to EPROM
(Corresponding addresses on the EPROM programmer)
0000 H
I/O
0080 H
RAM
0180 H
Not available
8000 H
0000 H
EPROM
32 K
PROM
32 K
FFFF H
7FFF H
4. Programming to the EPROM
(1) Set the EPROM programmer for MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
15
MB89190/190A Series
■ BLOCK DIAGRAM
X0
Oscillator
(Max. 4.2 MHz)
X1
Timebase timer
Internal bus
Clock control
Reset circuit
(WDT)
RST
4
Port 0
CMOS I/O port
8-bit timer/counter
P34/TO
/INT10
8-bit timer/counter
P33/EC
External interrupt
(Wake-up)
P04/INT24 to
P07/INT27
P00/INT20/AN4 to 4
P03/INT23/AN7
P30/SCK
P45*/AVR
P44*/AV SS
Port 4
(MB89190A only)
P40/AN0 to
P43/AN3
P32/SI
P31/SO
Port 3
8-bit A/D converter
8-bit
serial
P35/INT11
External interrupt
4
P36/INT12
N-ch open-drain output port
Remote-control
transmit frequency
generator
P37/BZ/RCO
Buzzer output
RAM
CMOS I/O port
F2MC-8L
CPU
ROM
The other pins
TEST, VCC, V SS
16
*: In the MB89190A series, P44 and P45 serve only as
AVR and AV ss pins, respectively, and cannot be used as ports.
The MB89190 has no built-in A/D converter.
MB89190/190A Series
■ CPU CORE
1. Memory Space
The microcontrollers of MB89190/190A series offer a 64 Kbytes of memory for storing all of I/O, data, and
program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above
the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is allocated from exactly the opposite end of I/O area, that is, the highest address. The tables
of interrupt reset vectors, and vector call instructions are allocated from the highest address within the program
area. The memory space of the MB89190/190A series is structured below:
Memory Space
MB89191/191A
0000 H
MB89193/193A
0000 H
I/O
0080 H
MB89195/195A
MB89P195/P195A
0000 H
I/O
0080 H
MB89PV190/PV190A
0000 H
I/O
0080 H
I/O
0080 H
Vacancy
00C0 H
0100 H
RAM
RAM
0100 H
Register
RAM
0100 H
Register
RAM
0100 H
Register
Register
0140 H
0180 H
0180 H
0180 H
Not available
Not available
Not available
Not available
8000 H
C000 H
External ROM
Program PROM
(Mask ROM)
E000 H
F000 H
Mask ROM
Mask ROM
FFFF H
FFFF H
FFFF H
FFFF H
17
MB89190/190A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers and general-purpose memory
registers. The following dedicated registers are provided:
Program counter (PC):
A 16-bit-long register for indicating the instruction storage positions
Accumulator (A):
A 16-bit-long temporary register for arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit-long register which is used for arithmetic operations with the accumulator.
When the instruction is an 8-bit data processing instruction, the lower byte is
used.
Index register (IX):
A 16-bit-long register for index modification
Extra pointer (EP) :
A 16-bit-long pointer for indicating a memory address
Stack pointer (SP) :
A 16-bit-long pointer for indicating a stack area
Program status (PS) :
A 16-bit-long register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
T
: Temporary accumulator Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
PS
: Program status
Indeterminate
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR) (see the diagram below).
Structure of the Program Status Register
15
PS
14
13
12
RP
10
9
8
Vacancy Vacancy Vacancy
RP
18
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
MB89190/190A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low
N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.
Z-flag:
Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag:
Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
‘0’ otherwise. Set to ‘1’ the shift-out value in the case of a shift instruction.
19
MB89190/190A Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit-long register for storing data
The general-purpose registers are of 8 bits and located in register banks of the memory. One bank contains
eight registers and up to a total of 16 banks can be used on the MB89190/190A (8 banks on MB89191/191A).
The bank currently in use is indicated by the register bank pointer. (RP)
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuraiton
This address = 0100 H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
16 banks
(8 banks for the MB89191/191A)
Memory area
20
MB89190/190A Series
■ I/O MAP
Address
Read/write
Register name
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
ENI0
Port 0 input enable register
03H to 07H
Register description
Vacancy
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog control register
0AH
(R/W)
TBTC
Time-base timer control register
0BH
0CH
Vacancy
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
BUZR
Buzzer register
10H to 13H
Vacancy
14H
(R/W)
RCR1
Remote-control transmit control register 1
15H
(R/W)
RCR2
Remote-control transmit control register 2
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
Vacancy
1FH
Vacancy
20H
(R/W)
ADC1
A/D converter control register 1
21H
(R/W)
ADC2
A/D converter control register 2
22H
(R/W)
ADCD
A/D converter data register
23H
(R/W)
EIC1
24H
(R/W)
EIC2
25H to 31H
External interrupt control register 1
External interrupt control register 2
Vacancy
32H
(R/W)
EIE2
External interrupt 2 enable register
33H
(R/W)
EIF2
External interrupt 2 flag register
7CH
(W)
ILR1
Interrupt level register 1
7DH
(W)
ILR2
Interrupt level register 2
7EH
(W)
ILR3
Interrupt level register 3
34H to 7BH
Vacancy
7FH
Vacancy
Note: Do not use vacancies.
21
MB89190/190A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
AVR
VSS – 0.3
VSS + 7.0
V
Must not exceed VCC + 0.3 V.
MB89190A series only
EPROM program voltage
VPP
VSS – 0.3
VSS + 13.0
V
MB89P195/P195A only
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
IOL1

10
mA
Except P33 and P34
(Except P30 toP34 and P40 to
P43 for MB89191AH/193AH)
IOL2

20
mA
P33, P34(P30 toP34 and P40 to
P43 for MB89191AH/193AH)
mA
Except P33 and P34
(Except P30 toP34 and P40 to
P43 for MB89191AH/193AH)
Average value (operating current
× operation rate)
Power supply voltage
“L” level maximum output
current
IOLAV1

4
“L” level average output current
IOLAV2

8
mA
P33 and P34(P30 toP34 and P40
to P43 for MB89191AH/193AH)
Average value (operating current
× operation rate)
“L” level total average output
current
ΣIOLAV

20
mA
Average value (operating current
× operation rate)
“L” level total maximum output
current
ΣIOL

100
mA
“H” level maximum output
current
IOH1

–10
mA
Except P33, P34, and P37
IOH2

–20
mA
P33, P34, P37
IOHAV1

–2
mA
Except P33, P34, and P37
Average value (operating current
× operation rate)
IOHAV2

–4
mA
Except P33, P34, and P37
Average value (operating current
× operation rate)
“H” level total average output
current
ΣIOHAV

–10
mA
Average value (operating current
× operation rate)
“H” level total maximum output
current
ΣIOH

–30
mA
Power consumption
PD

200
mW
Operating temperature
Ta
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“H” level average output
current
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
MB89190/190A Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Symbol
Parameter
Power supply voltage
VCC
Value
Unit
Remarks
6.0*
V
Normal operation assurance range*
MB89191/191A/193/193A/195/195A
2.7*
6.0*
V
Normal operation assurance range*
MB89P195/P195A/PV190/PV190A
1.5
6.0
V
Retains the RAM state in the stop
mode
Min.
Max.
2.2*
A/D converter reference input
voltage
AVR
0.0
VCC
V
Operating temperature
TA
–40
+85
°C
* : These values vary with the operation frequency and the assured analog operation range. See Figure 1 and “ 5.
A/D Converter Electrical Characteristics.”
Operating voltage (V)
6
Analog accuracy assured in the
Vcc = 3.5 V to 6.0 V range.
5
Operation assurance range
4
3
2
1
1
2
3
4
Main clock operation frequency (at an instruction cycle of 4/Fc) (MHz)
4.0
2.0
0.95 (µs)
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89191/191A/193/193A/195/195A.
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
23
MB89190/190A Series
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
3. DC Characteristics
Parameter
Symbol
VIH
P00 to P07,
P30 to P37,
TEST

0.7 VCC

VCC +
0.3
V
VIHS
RST,
INT10 to INT12,
EC, SCK, SI,
INT20 to INT27

0.8 VCC

VCC +
0.3
V
VIL
P00 to P03,
P33 to P36,
TEST

VSS −
0.3

0.3 VCC
V
VILS
RST,
INT10 to INT12,
EC, SCK, SI,
INT 20 to INT27

VSS −
0.3

0.2 VCC
V
VD
P40 to P44

VSS −
0.3

VSS +
0.3
V
VOH1
P00 to P07,
P30 to P32,
P35, P36
IOH = –2.0 mA
2.4


V
VOH2
P33, P34
IOH = –15 mA
2.4


V
VOH3
P37
IOH = –7.0 mA
2.4


V
VOL1
P00 to P07,
P40 to P45,
P30 to P32,
P35 to P37
“H” level
input voltage
“L” level
input voltage
Open-drain output
pin applied voltage
“H” level
output voltage
“L” level
output voltage
Pin
(VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
IOL = 1.8 mA


0.4
V
P00 to P07,
P35 to P37
VOL2
RST
MB89191AH/
193AH
IOL = 4.0 mA


0.4
V
P33, P34
IOL = 12 mA
VOL3


0.4
V
P30 to P34,
P40 to P43
Input leakage
current(Hi-z output
leakage current)
Except
MB89191AH/
193AH
Except
MB89191AH/
193AH
MB89191AH/
193AH
ILI1
P00 to P07,
P30 to P37,
TEST
0.0 V < VI < VCC


±5
µA
Without
pull-up
resistor
Open-drain output
leakage current (Off ILD1
state)
P40 to P45
0.0 V < VI < VCC


±1
µA
Without
pull-up
resistor
(Continued)
24
MB89190/190A Series
(Continued)
Parameter
Pull-up
resistance
Symbol
RPULL
Pin
P00 to P07,
P30 to P37,
P40 to P45,
RST
ICC
Power supply
voltage*
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Typ.
Max.
VI = 0.0 V
25
50
100
kΩ
—
5
10
MB89191/
191A/193/
mA 193A/195/
195A/PV190/
PV190A
—
7
12
mA
FC = 4.2 MHz
VCC
MB89P195/
P195A
ICCS
FC = 4.2 MHz
—
3
7
mA Sleep mode
ICCH
TA = +25 °C
—
—
1
µA
ICCA
FC = 4.2 MHz
During A/D
converter
operation
—
6
13
MB89191A/
mA 193A/195A/
PV190A
—
8
15
mA MB89P195A
—
10
—
pF
Input capacitance CIN
Except AVR,
f = 1 MHz
AVSS, VCC, and VSS
Stop mode
* : For the MB89PV190/PV190A, the current consumption of a connected EPROM and ICE is not included.
The mesurement condition of the power supply current are set as VCC = 5.0 V with an external clock.
25
MB89190/190A Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
Parameter
RST “L” pulse width
tZLZH
—
16 tXCYL
—
ns
Note: tXCYL is the oscillation period (1/FC) input to the X0 pin.
t ZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Min.
Max.
—
50
ms
1
—
ms
Remarks
Due to repeated operations
Note: Make sure that power supply rises within the oscillation stabilization time selected.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
t OFF
tR
2.0 V
VCC
26
0.2 V
0.2 V
0.2 V
MB89190/190A Series
(3) Clock Timings
Symbol
Parameter
Pin
Condition
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Max.
Clock frequency
FC
X0, X1
—
1
4.2
MHz
Clock cycle time
tXCYL
X0, X1
—
238
1000
ns
Input clock pulse
width
PWH
PWL
X0
—
20
—
ns
External clock
Input clock pulse
risilng/falling time
tCR
tCF
X0
—
—
10
ns
External clock
X0, X1 Timings and Conditions of Applied Voltage
t XCYL
PWH
PWL
t CF
t CR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal or ceramic resonator is used
X0
When an external clock is used
X1
X0
X1
Open
(4) Instruction Cycles
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Instruction cycle
(minimum execution time)
Symbol
tinst
Value (typical)
Unit
Remarks
4/FC
µs
tinst = 0.95 µs when operating at FC =
4.2 MHz
27
MB89190/190A Series
(5) Recommended Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Series)
X0
X1
R
C1*2
FAR*1
C2*2
*1: Fujitsu Acoustic Resonator
FAR part number
(built-in capacitor type)
FAR-C4SA-04000- 01M
Inquiry: FUJITSU LIMITED
28
Frequency Dumping
(MHz)
resistor
4.00
200 Ω
Initial deviation
of
FAR frequency
(TA = +25°C)
Temperature
characteristics of
FAR frequency
(TA = –20°C to
+60°C)
Loading
capacitors*2
±0.5%
±0.5%
Built-in
MB89190/190A Series
• Sample Application of Ceramic Resonator
X0
X1
R
C1
*
C2
• Mask ROM products
Resonator
manufacturer*
Murata Mfg. Co., Ltd.
TDK. Co., Ltd.
Resonator
CSA2.00MG040
CST2.00MG040
CSA4.00MG
CST4.00MGW
CSTCS4.00MG0C5
CCR4.0MC3
FCR4.0MC5
Frequency
(MHz)
2.00
4.00
4.00
C1 (pF)
C2 (pF)
R
100
Built-in
30
Built-in
Built-in
Built-in
Built-in
100
Built-in
30
Built-in
Built-in
Built-in
Built-in
Not required
Not required
Not required
Not required
Not required
Not required
Not required
C1 (pF)
C2 (pF)
R
30
Built-in
100
Built-in
30
Built-in
30
Built-in
100
Built-in
30
Built-in
1 kΩ
1 kΩ
Not required
Not required
Not required
Not required
• One-time products
Resonator
manufacturer*
Murata Mfg. Co., Ltd.
Inquiry:
Resonator
CSA3.20MGCA
CST3.20MGA
CSA3.20MGA040
CST3.20MGWA040
CSA3.58MGCA
CST3.58MGWHA
Frequency
(MHz)
3.20
3.58
Murata Mfg. Co., Ltd
• Murata Electronics North America. Inc.: TEL 1-404-436-1300
• Murata Europe Mnagement GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
TDK Corporation
• TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
• TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
• TDK Singapore (PTE) Ltd.: TEL 65-273-5022
• TDK Hongkong Co., Ltd.: TEL 852-736-2238
• Korea Branch, TDK Corporation: TEL 82-2-554-6633
29
MB89190/190A Series
(6) Serial I/O Timings
(VCC = 5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Condition
Internal clock
operation
SCK
External
clock
operation
Value
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycles.”
Internal Shift Clock Mode
t SCYC
SCK
2.4 V
0.8 V
0.8 V
t SLOV
2.4 V
SO
0.8 V
SI
t IVSH
t SHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Shift Clock Mode
t SLSH
SCK
SO
t SHSL
0.8 VCC
0.2 VCC
0.2 VCC
t SLOV
2.4 V
0.8 V
t
SI
30
IVSH
t
SHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Unit
Min.
0.8 VCC
Remarks
MB89190/190A Series
(7) Peripheral Input Timings
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Unit Remarks
Min.
Max.
Symbol
Parameter
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
EC, INT10 to INT12,
INT20 to INT27
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycles.”
Peripheral Input Timing Diagram
t IHIL
t ILIH
EC
INT10 to INT12
INT20 to INT27
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
(VCC = 5.0 V±10%, AVSS= VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Value
Pin
Min.
Typ.
Max.
Unit
Peripheral input “H” noise
limit width
tIHNC
EC, SI, SCK
INT10 to INT12
7
15
23
ns
Peripheral input “L” noise
limit width
tILNC
EC, SI, SCK
INT10 to INT12
7
15
23
ns
Remarks
Peripheral Input Timing Diagram
t ILNC
EC, SCK, S1
INT10 to INT12
t IHNC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
31
MB89190/190A Series
5. A/D Converter Electrical Characteristics (MB89190A Series Only)
(AVCC = VCC = 3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Resolution
Condition
—
Total error
—
Linearity error
Differential linearity
error
Zero transition
voltage
VOT
AVR = AVCC
—
Full-scale transition
voltage
VFST
Inter channel
disparity
A/D mode
conversion time
—
Sense mode
conversion time
Analog port input
current
Unit
Min.
Typ.
Max.
—
—
8
bit
—
—
±1.5
LSB
—
—
±1.0
LSB
—
—
±0.9
LSB
AVSS
+2.0
LSB
mV
AVR
mV
AVSS
–1.0
LSB
AVSS
+0.5
LSB
AVR
–3.0
LSB
AVR
–1.5
LSB
—
—
0.5
LSB
—
44 tinst*
—
µs
—
12 tinst*
—
µs
—
—
10
µA
0
—
AVR
V
0
—
VCC
V
—
100
300
µA
—
—
1
µA
Remarks
—
IAIN
Analog input voltage
AN0 to AN7
—
Reference voltage
IR
Reference voltage
supply current
Value
AVR
IRH
AVR = VCC =
5.0 V when A/
D conversion is
operating
* : For information on tinst, see “(4) Instruction Cycles” in “4. AC Characteristics.”
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable by the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28=256.
Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1110” ↔ “1111 1111”) from actual conversion characteristics.
Differential linearity error (unit: LSB)
The deviation of input voltage needed change the output code by 1 LSB from the theoretical value.
• Total error (unit: LSB)
The difference between theoretical and actual conversion values.
32
MB89190/190A Series
Digital output
1111
1111 •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0000
0000
0000
Theoretical conversion value
1111
1110
Actual conversion value
(1LSB × N + VOT)
1LSB =
AVR
256
Linearity error
VNT – (1LSB × N + VOT)
1LSB
=
Linearity error
Differential linearity error =
V( N + 1 ) T – VNT
–1
1LSB
=
Total error
VNT – (1LSB × N + 1LSB)
1LSB
0010
0001
0000
VOT
VNT
V( N + I )T
VFST
Analog input
7. Notes on Using A/D Converter
• Input impedance of analog input pins
The A/D converter used for the MB89190A series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.
0.1 µF for the analog input pin.
Analog input equivalent circuit
Sample hold
circuit,
.
C =. 33 pF
Analog input pin
Comparator
If the analog input impedance
is higher than 10 kΩ, it is
recommended to connect an
external capacitor of approx.
0.1 µF.
.
R =. 6 kΩ
Close for 8 instruction cycles
after starting A/D conversion.
Analog channel selector
• Error
The smaller the AVR-AVSS, the greater the error would become relatively.
33
MB89190/190A Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
VOL1 vs. IOL
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
VOL (V)
0.30
VOL (V)
0.6
VCC = 4.0 V
TA = +25°C
0.25
VCC = 5.0 V
VCC = 6.0 V
0.20
0.2
0.05
0.1
2
3
4
5
IOL (mA)
VOL3 vs. IOL
VOL (V)
1.2
VCC = 2.0 V
VCC = 2.5 V
TA = +25°C
1.0
0.8
VCC = 3.0 V
0.6
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.2
0.0
34
0.4
0.10
1
0
2
4
6
8
10 12
14 16
18 20
IOL (mA)
VCC = 5.0 V
VCC = 6.0 V
0.5
0.3
0
VCC = 4.0 V
TA = +25°C
0.15
0.00
VOL2 vs. IOL
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
0.0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
MB89190/190A Series
(2) “H” Level Output Voltage
VOH1 vs. IOH
VCC = 4.0 V
VCC = 2.5 V
VCC = 2.0 V
VCC = 3.0 V
VCC - VOH (V)
0.6
TA = +25°C
0.5
VOH2 vs. IOH
VCC = 5.0 V
VCC = 6.0 V
VCC - VOH (V)
VCC = 3.0 V
3.0
TA = +25°C
VCC = 2.5 V
2.5
0.4
2.0
0.3
1.5
0.2
1.0
0.1
0.5
0.0
0
–1
–2
–3
–4
–5
IOH (mA)
0.0
VCC = 2.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0
–4
–8
– 12
– 16
– 20
IOH (mA)
VOH3 vs. IOH
VCC - VOH (V)
VCC = 2.0 V
1.2
TA = + 25°C
VCC = 2.5 V
VCC = 3.0 V
1.0
0.8
VCC = 4.0 V
0.6
VCC = 5.0 V
VCC = 6.0 V
0.4
0.2
0.0
0
–2
–4
–6
–8
– 10
IOH (mA)
(3) “H” Level Input Voltage/“L” Level
Input Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level
Input Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
4.5
TA = +25°C
4.0
TA= +25°C
3.5
VIHS
3.0
4.0
2.5
3.5
VILS
2.0
3.0
1.5
2.5
1.0
2.0
0.5
1.5
0.0
1.0
0
0.5
0.0
VIN vs. VCC
VIN (V)
5.0
4.5
0
1
2
3
4
5
6
7
VCC (V)
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
35
MB89190/190A Series
(5) Power Supply Current (External Clock)
ICC vs. VCC
ICC (mA)
6
ICCS vs. VCC
ICCS (mA)
1.50
TA = +25°C
TA = +25°C
5
Fc = 4.2 MHz
1.25
Fc = 4.2 MHz
4
1.00
Fc = 3.0 MHz
3
Fc = 3.0 MHz
0.75
2
0.50
Fc = 1.0 MHz
1
Fc = 1.0 MHz
0.25
0
0.00
1
2
3
4
5
6
7
2
1
3
4
5
6
7
VCC (V)
5
6
7
AVR (V)
VCC (V)
ICCH vs. VCC
ICCH (µA)
2.0
IR vs. AVR
IR (µA)
150
TA = +25°C
1.8
TA = +25°C
1.6
125
1.4
100
1.2
1.0
75
0.8
50
0.6
0.4
25
0.2
0
0
1
2
3
4
5
6
7
1
2
3
VCC (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
100
10
36
1
2
3
4
5
6
VCC (V)
4
MB89190/190A Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
37
MB89190/190A Series
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
•
•
•
•
“–” indicates no change.
dH is the 8 upper bits of operation description data.
AL and AH must become the contents of AL and AH prior to the instruction executed.
00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
38
MB89190/190A Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
39
MB89190/190A Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
40
MB89190/190A Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
41
L
42
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
R0
R1
R2
R3
R4
R5
R6
R7
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
7
8
9
A
B
C
D
E
F
CMPW
A
A
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
rel
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6
dir: 6,rel A,@IX +d @IX +d,A
IX,#d16
A,IX
A
CMP
SETC
6
F
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
E
5
D
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
C
4
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
RORC
A
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
SETI
9
3
8
ROLC
7
2
A
6
DIVU
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
MULU
RETI
3
1
RET
2
SWAP
1
NOP
0
0
H
MB89190/190A Series
■ INSTRUCTION MAP
MB89190/190A Series
■ MASK OPTION LIST
Part number
No.
MB89191 MB89191A
MB89193 MB89193A
MB89195 MB89195A
when
Specifying procedure Specify
ordering masking
1
2
P00 to P07
Selectable by pin
Port pull-up P30 to P37
resistors
P00 to P03 Selectable Not
P40 to P45 by pin
available
Power-on reset
• Power-on reset provided
• No power-on reset
• 218/FC (approx. 62.4 ms)
• 216/FC (approx. 15.6 ms)
• 212/FC (approx. 0.98 ms)
• 22/FC (approx. 0 ms)
MB89P195A
–101*2
Specify when
ordering masking
None
Selectable by pin
None
–201*2
MB89PV190
MB89PV190A
Fixed
None
Not available
Selectable Not
None
by pin
available
Not available
Selectable
Provided
Provided
Provided
Selectable
Fixed to
216/FC
Selectable
Fixed to
216/FC
Provided Provided
Selection of oscillation
stabilization wait time
(at 4.2 MHz)*1
3
MB89P195
4
Reset pin output
• Reset output provided
• No reset output
Selectable
Provided
Selectable
5
Oscillation type of clock
1 Crystal and ceramic
oscillators
2 CR
Selectable
“1” only
Selectable
“1” only
Provided
Fixed to
216/FC
“1” only
*1: The oscillation stabilization time is generated by dividing the original clock oscillation. The time described
in this item should be used as a rough guideline since the oscillation cycle is unstable immediately after
oscillation starts. “FC” indicates the original oscillation frequency.
*2: –101 and –201 are provided respectively for the MB89P195 and MB89P195A OTP versions as the standard
products.
43
MB89190/190A Series
■ ORDERING INFORMATION
Part number
MB89191PF
MB89193PF
MB89195PF
MB89P195PF-101
MB89191APF
MB89191AHPF
MB89193APF
MB89193AHPF
MB89195APF
MB89P195APF-201
28-pin Plastic SOP
(FPT-28P-M17)
MB89191P-SH
MB89193P-SH
MB89195P-SH
MB89191AP-SH
MB89191AHP-SH
MB89193AP-SH
MB89193AHP-SH
MB89195AP-SH
28-pin Plastic SH-DIP
(DIP-28C-M03)
MB89191P
MB89193P
MB89195P
MB89P195P-101
MB89191AP
MB89191AHP
MB89193AP
MB89193AHP
MB89195AP
MB89P195AP-201
28-pin Plastic DIP
(DIP-28P-M05)
MB89PV190CF
MB89PV190ACF
44
Package
48-pin Ceramic MQFP
(MQP-48C-P01)
Remarks
MB89190/190A Series
■ PACKAGE DIMENSION
28-pin Plastic SOP
(FPT-28P-M17)
+0.25
17.75 –0.20
28
15
+.010
.699 –.008
Details of "B" part
Details of "A" part
0.15(.006)
0.35(.014)
11.80±0.30
(.465±.012)
INDEX
8.60±0.20
(.339±.008)
0.20(.008)
0.20(.008)
"A"
0.18(.007)
MAX
0.68(.027)
MAX
1
0.18(.007)
MAX
0.68(.027)
MAX
14
1.27(.050)
TYP
0.45±0.10
(.018±.004)
0.13(.005)
M
2.80(.110)MAX
(Mounting height)
0.15±0.05
(.006±.002)
"B"
0.10(.004)
16.51(.650)
REF
C
0.80±0.20
(.031±.008)
10.20±0.30
(.402±.012)
Dimensions in mm (inches)
1994 FUJITSU LIMITED F28048S-1C-1
28-pin Plastic DIP
(DIP-28P-M05)
0(0)MIN
(STAND OFF)
+0.20
35.73 –0.30
+.008
1.407 –.012
INDEX-1
13.80±0.25
(.543±.010)
INDEX-2
+0.50
+0.50
0.99 –0
.039
1.52 –0
+.020
–0
+.020
.060 –0
0.51(.020)MIN
4.96(.195)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
1.58(.062)
MAX
C
1994 FUJITSU LIMITED D28013S-3C-2
2.54(.100)
TYP
0.46±0.08
(.018±.003)
15.24(.600)
TYP
15°MAX
Dimensions in mm (inches)
45
MB89190/190A Series
28-pin Plastic SH-DIP
(DIP-28P-M03)
+0.20
26.00 –0.30
1.024
+.008
–.012
INDEX-1
9.10±0.25
(.358±.010)
INDEX-2
4.85(.191)MAX
0.51(.020)MIN
0.25±0.05
(.010±.002)
3.00(.118)MIN
0.45±0.10
(.018±.004)
+0.50
1.00 –0
23.114(.910)REF
1.778(.070)
MAX
C
15°MAX
10.16(.400)
TYP
+.020
.039 –0
1.778±0.18
(.070±.007)
Dimensions in mm (inches)
1994 FUJITSU LIMITED D28012S-3C-3
48-pin Ceramic MQFP
(MQP-48C-P01)
PIN No.1 INDEX
17.20(.677)TYP
15.00±0.25
(.591±.010)
14.82±0.35
(.583±.014)
1.50(.059)TYP
8.80(.346)REF
1.00(.040)TYP
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
+0.13
10.92 –0.0
+.005
.430 –0
7.14(.281) 8.71(.343)
TYP
TYP
PAD No.1 INDEX
0.30(.012)TYP
+0.45
4.50(.177)TYP
1.10 –0.25
+.018
.043 –.010
0.40±0.08
(.016±.003)
0.60(.024)TYP
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
46
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches)
MB89190/190A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9901
 FUJITSU LIMITED Printed in Japan
48
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.