FUJITSU SEMICONDUCTOR DATA SHEET DS07-12543-4E 8-bit Proprietary Microcontrollers CMOS F2MC-8L MB89580B/580BW Series MB89583B/585B/589B/P585B/P589B/ MB89583BW/585BW/P585BW ■ DESCRIPTION The MB89580B/BW series is a line of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, these microcontrollers contain a variety of peripheral functions, such as PLL clock control, timers, a serial interface, a PWM timer, and the USB function. In particular, these microcontrollers contain one USB function channel to support both full and low speeds. ■ FEATURES • Package type 64-pin LQFP package (0.5 mm and 0.65 mm pitch) • High-speed operations at low voltage Minimum execution time : 0.33 µs (Automatically generates a 12 MHz main clock and a 48 MHz USB interface synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.) • F2MC-8L CPU core Instruction set that is optimum to the controllers -Multiplication and division instructions -16-bit arithmetic operations -branch instructions by bit testing -bit manipulation instructions, etc. (Continued) ■ PACKAGES 64-pin plastic LQFP 64-pin plastic LQFP (FPT-64P-M03) (FPT-64P-M09) MB89580B/580BW series (Continued) • PLL clock control The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise characteristics. (6 MHz externally-supplied clock→12 MHz internal system clock) • Various timers 8-bit PWM timer (can be used as either 8-bit PWM timer × 2 channels or PPG timer × 1 channel) Internal 21-bit timebase timer • Internal USB transceiver circuit (Compatible with full and low speeds) • USB function Compliant to USB Protocol Revision 1.0 Support for both low and full speeds (selectable) Allows four endpoints to be specified at maximum. Types of transfer supported : control/interrupt/bulk/isochronous Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for function’s send and receive data.) • UART/serial interface Built-in UART/SIO function (selectable by switching) • External interrupt External interrupt (level detection × 8 channels) Eight inputs are independent of one another and can also be used for resetting from low-power consumption mode (the L-level detection feature available) . • Low power consumption (standby mode supported) Stop mode (There is almost no current consumption since oscillation stops.) Sleep mode (This mode stops the running CPU.) • A maximum of 53 general-purpose I/O ports General-purpose I/O ports (CMOS) : 34 General-purpose output ports (CMOS) : 8 General-purpose I/O ports (Nch open drain) : 3 General-purpose input ports (CMOS 3.3 V input-compatible) : 8 • Parallel ports Also serve as eight of the general-purpose I/O ports (CMOS) Interrupt function available Allows asynchronous read and write by external signals • Power supply Supply voltage : 3.0 V to 5.5 V 2 MB89580B/580BW series ■ PRODUCT LINEUP Part number MB89583B MB89585B MB89P585B MB89589B MB89P589B MB89583BW MB89585BW MB89P585BW Parameter ROM size 8 KB RAM size 512 B Package 16 KB 1 KB 18 KB 16 KB 512 B 1 KB LQFP-64 (FPT-64P-M09) LQFP-64 (FPT-64P-M03) Operation at USB reset 8 KB LQFP-64 (FPT-64P-M03) High impedance state Others OTP/EVA product MASK product MASK product Low-level output OTP/EVA product MASK product Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 0. 33 µs (6 MHz) : 3 µs (6 MHz) Generalpurpose ports General-purpose I/O ports General-purpose output ports General-purpose input ports (34 : CMOS, 3 : Nch open drain) (8 : CMOS) (8 : CMOS 3.3 V input) Parallel ports Shares eight (P40 through P47) of the above general-purpose I/O ports. Allows asynchronous read and write by external signals. An interrupt function is available to set data. CPU functions OTP/EVA product Can be set to full/low speed. Four endpoints at maximum Power supply mode : Can be set to own power supply/bus power supply mode. FIFO 8 bits × 8 built in Built-in DMAC (Can be set to DMA transfer to the internal RAM or to the external FIFO.) Periph- USB eral function functions PWM timer 8-bit PWM timer operation × 2 channels (can also be used as a PPG × 1 channel timer) UART SIO Allows switching between UART (clock-synchronous/asynchronous data transfer allowed) and SIO (simple serial transfer) . Timebase timer 21-bit timebase timer Clock output Allows output of two main clock divisions Standby mode Sleep mode and Stop mode ■ PACKAGES AND CORRESPONDING PRODUCTS Package MB89583B MB89585B MB89P585B FPT-64P-M03 FPT-64P-M09 : Available × × × MB89589B MB89P589B × × MB89583BW MB89585BW × × MB89P585BW × × : Not available 3 MB89580B/580BW series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTP product, verify its differences from the product that will actually be used. 2. Current Consumption When operated at low speeds, a product mounted with either one-time PROM or EPROM consumes more current than a product mounted with a mask ROM. However, in sleep/stop mode the current consumption is the same. For detailed information on each package, see “■ PACKAGE DIMENSIONS.” 3. Differences Between the MB89580B series and the MB89580BW Series MB89580B series : Remains in high impedance state until USB connection takes place. Before the USB connection, use one general-purpose port output to control pullup resistance connection of this port by software. MB89580BW : Outputs at low level until USB connection takes place. • Example MB89580B product connection 3.3 V MB89580B series Host PC General-purpose port 1.5 kΩ D+ RPVP pin D− RPVM pin • Example MB89580BW product connection 3.3 V Host PC MB89580BW series 1.5 kΩ D+ RPVP pin D− RPVM pin Note : Full speed is assumed in the above examples. 4 MB89580B/580BW series ■ PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P43/D3/DO3 P42/D2/DO2 P41/D1/DO1 P40/D0/DO0 P67/DI7 P66/DI6 P65/DI5 P64/DI4 P63/DI3 P62/DI2 P61/DI1 P60/DI0 RPVM RPVP C VCC (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P53/A0/FFX P54/CEX RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P20 DO4/P44/UCK/D4 DO5/P45/UO/D5 DO6/P46/UI/PWM1/D6 DO7/P47/PWM2/D7 P30/INT0/CLK P31/INT1 P32/INT2 P33/INT3 P34/INT4 P35/INT5 P36/INT6/WEX P37/INT7/RDX P50/OBF/IBFX/W VSS P51/R P52/EFX (FPT-64P-M03) (FPT-64P-M09) 5 MB89580B/580BW series ■ PIN DESCRIPTION Pin No. Pin name Circuit type Function 1 P44/UCK/D4/ DO4 E General-purpose CMOS I/O pin UART/S10 clock I/O This pin also serves as a parallel interface/external FIFO data output pin. 2 P45/UO/D5/ DO5 B General-purpose CMOS I/O pin UART/S10 serial data output This pin also serves as a parallel interface/external FIFO data output pin. 3 P46/UI/ PWM1/D6/ DO6 E General-purpose CMOS I/O pin UART/S10 serial data input PWM timer This pin also serves as a parallel interface/external FIFO data output pin. 4 P47/PWM2/ D7/DO7 B General-purpose CMOS I/O pin PWM timer This pin also serves as a parallel interface/external FIFO data output pin. 5 P30/INT0/ CLK E General-purpose CMOS I/O pin Clock output pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 6 P31/INT1 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 7 P32/INT2 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 8 P33/INT3 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 9 P34/INT4 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 10 P35/INT5 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 11 P36/INT6/ WEX E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) This pin also serves as the parallel interface write strobe input pin. 12 P37/INT7/ RDX E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) This pin also serves as the parallel interface read strobe input pin. 13 P50/OBF/ IBFX/W B General-purpose CMOS I/O pin Interrupt output to the parallel interface host. This pin also serves the OUT FIFO data strobe pin. (Continued) 6 MB89580B/580BW series Pin No. Pin name Circuit type 14 VSS Power supply pin (GND) 15 P51/R B General-purpose CMOS I/O pin. This pin also serves the IN FIFO data strobe pin. 16 P52/EFX K General-purpose Nch open drain I/O pin. This pin also serves as the IN FIFO data enable input pin. 17 P53/A0/FFX K General-purpose Nch open drain I/O pin. Parallel interface’s data select input This pin also serves as the OUT FIFO data enable input pin. 18 P54/CEX K General-purpose Nch open drain I/O pin. This pin also serves as the parallel interface device select input pin. 19 RST I Reset pin. (Reset on the negative logic low level.) 20 MOD0 F An operating mode designation pin. Connect directly to Vss. 21 MOD1 F An operating mode designation pin. Connect directly to Vss. 22 X0 23 X1 A Pins for the connection of crystal oscillatoion circuit (6 MHz) 24 VSS Power supply pin (GND) 25 P27 B General-purpose CMOS output pin 26 P26 B General-purpose CMOS output pin 27 P25 B General-purpose CMOS output pin 28 P24 B General-purpose CMOS output pin 29 P23 B General-purpose CMOS output pin 30 P22 B General-purpose CMOS output pin 31 P21 B General-purpose CMOS output pin 32 P20 B General-purpose CMOS output pin 33 P17 B General-purpose CMOS I/O pin 34 P16 B General-purpose CMOS I/O pin 35 P15 B General-purpose CMOS I/O pin 36 P14 B General-purpose CMOS I/O pin 37 P13 B General-purpose CMOS I/O pin 38 P12 B General-purpose CMOS I/O pin 39 P11 B General-purpose CMOS I/O pin 40 P10 B General-purpose CMOS I/O pin 41 P07 B General-purpose CMOS I/O pin 42 P06 B General-purpose CMOS I/O pin 43 P05 B General-purpose CMOS I/O pin 44 P04 B General-purpose CMOS I/O pin Function (Continued) 7 MB89580B/580BW series (Continued) 8 Pin No. Pin name Circuit type 45 P03 B General-purpose CMOS I/O pin 46 P02 B General-purpose CMOS I/O pin 47 P01 B General-purpose CMOS I/O pin 48 P00 B General-purpose CMOS I/O pin 49 VCC Power supply pin 50 C Connect an external capacitor of 0.1 µF. When using with 3.3 V power supply, connect this pin with the Vcc pin to set to 3.3 V input. 51 RPVP USBDRV USB route port + pin 52 RPVM USBDRV USB router port − pin 53 P60/DI0 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. (LSB) 54 P61/DI1 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. 55 P62/DI2 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. 56 P63/DI3 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. 57 P64/DI4 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. 58 P65/DI5 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. 59 P66/DI6 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. 60 P67/DI7 F General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. (MSB) 61 P40/D0/DO0 B General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. 62 P41/D1/DO1 B General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. 63 P42/D2/DO2 B General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. 64 P43/D3/DO3 B General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. Function MB89580B/580BW series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation feedback resistance : 1 MΩ approx. X1 A X0 Standby control signal • CMOS I/O R Pch Pullup control register Pch B Nch Input Standby control signal • CMOS I/O • Hysteresis input R Pch Pullup control register Pch E Nch Port input Standby control signal Resource input • CMOS input F Input • Hysteresis I/O • Pullup resistance R Pch I Nch Input (Continued) 9 MB89580B/580BW series (Continued) Type Circuit Remarks • USB I/O D+ input D– input D+ Differencial input D– Full D+ output Full D– output USBDRV Low D+ output Low D– output Direction Speed • Nch open drain I/O R Pch Pullup control register K Nch Standby control signal 10 Input MB89580B/580BW series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply to the analog power system is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the pins. These unused pins should be connected to a pullup or pulldown resistance of at least 2 kΩ between the pin and the power supply. Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled the same as unused input pins. 3. Power Supply Voltage Fluctuations Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 11 MB89580B/580BW series ■ ONE-TIME PROM AND EPROM MICROCONTROLLER PROGRAMMING SPECIFICATIONS PROM mode is available on the MB89P585B/BW microcontrollers. The use of a dedicated adapter allows you to program the devices with a general-purpose ROM programmer. However, keep in mind that electronic signature mode is not available. 1. ROM programmer adapter and its compatible programmers Compatible adapter Compatible programmers and models Sun Hayato Co, Ltd. Ando Denki K. K. FTP-64P-M03 ROM2-64LQF-32DP-8LA FTP-64P-M09 ROM2-64QF2-32DP-8LA2 AF9708 (Version 1.40 or higher) AF9709 (Version 1.40 or higher) AF9723 (Version 1.50 or higher) Package Inquiry: Sun Hayato Co., Ltd. Ando Denki K. K. : TEL. 81-3-3986-0403 : TEL. 81-3-3733-1160 2. Memory map in PROM mode (Corresponding addresses on the ROM programmer) Normal operating mode 0000H I/O 0080H RAM 0480H Not available C000H 0000H Program area (PROM) FFFFH Program area (PROM) 3FFFH 3. Programming the EPROM (Using the Ando Denki K.K. programmer) (1) Set the EPROM programmer type code to 17209. (2) Load program data on to the EPROM programmer at 0000H to 3FFFH. (3) Program C000H to FFFFH with the EPROM programmer. 12 MB89580B/580BW series ■ BLOCK DIAGRAM X0 X1 Main clock oscillator Reset output Clock control circuit Power on reset circuit (watchdog timer) RST PLL circuit 21-bit timebase timer UART RPVM USB DRV RPVP P37/INT7/RDX P30/INT0/CLK P00 to P07, P10 to P17 P31/INT1 to P35/INT5 Clock output External interrupt (level) P20 to P27 CMOS In Port P36/INT6/WEX P40/D0/DO0 to P43/D3/DO3 USB Function circuit DMA CMOS I/O Port P50/OBF/IBFX/W SIO P44/UCK/D4/DO4 P45/UO/D5/DO5 CMOS Out Port P51/R P46/UI/PWM1/D6/DO6 P47/PWM2/D7/DO7 CMOS I/O Port Internal bus 8-bit PWM timer P60/DI0 to P67/DI7 RAM 18 K / 1 K / 512 Byte F2MC - 8L CPU P53/FFX P54/CEX Nch I/O Port P52/EFX ROM 8 K / 16 KByte Other pins VSS VCC MOD0 MOD1 C 13 MB89580B/580BW series ■ CPU CORE 1. Memory Space The MB89580B/BW microcontrollers offer a memory space of 64 Kbytes consisting of the I/O, RAM and ROM areas. The memory space contains areas that are used for specific purposes, such as a general-purpose register and a vector table. • I/O area (addresses : 0000H through 007FH) This area is assigned with the control and data registers, for example, of peripheral functions to be built in. The I/O area is as accessible as the memory since the area is assigned to a part of the memory space. Direct addressing also allows the area to be accessed faster. • RAM area As an internal data area, a static RAM is built in. The internal RAM capacity varies with the product type. The area 80H to FFH can be accessed at high speed with direct addressing. The area 100H to 1FFH can be used a general-purpose register area. (The usable area is limited depending on the product.) When reset, RAM data becomes undefined. • ROM area As an internal program area, a ROM is built in. The internal ROM capacity varies with the product type. The area FFC0H to FFFFH should be used for a vector table, for example. • Memory map MB89585B MB89585BW MB89P585B MB89P585BW MB89583B MB89583BW 0000H 0000H 0000H I/O 0080H I/O 0200H 0280H I/O 0080H RAM 512 B 0100H Generalpurpose register MB89589B MB89P589B 0080H RAM 1 KB 0100H 0200H RAM 18 KB 0100H Generalpurpose register 0200H Generalpurpose register 0480H 4880H Not available Not available Not available E000H C000H ROM 8 KB C000H ROM* 16 KB FFC0H FFC0H FFC0H FFFFH FFFFH FFFFH Vector table (reset, interrupt and vector call instructions) 14 ROM* 16 KB * : The area is EPROM on the MB89P585B, MB89P585BW, and MB89P589B microcontrollers. MB89580B/580BW series 2. Registers The MB89580B/BW series has two types of registers; the registers dedicated to specific purposes in the CPU and the general-purpose registers. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit register to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register to store a register pointer or a condition code. 16 bits : Program counter PC Initial value FFFDH A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate RP CCR PS : Program status I-flag = 0, IL1, 0 = 11 Initial values for other bits are indeterminate. 15 MB89580B/580BW series The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition code register in the lower 8 bits (CCR) . (See the diagram below.) RP PS CCR bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 − − bit8 − bit7 H bit6 I bit5 IL1 bit4 IL0 bit3 N bit2 Z bit1 bit0 V C CCR initial value X011XXXXB H-Flag I-Flag IL 1,0 N-Flag Z-Flag V-Flag C-Flag X : Undefined The RP points to the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule shown next. Rule for Conversion of Actual Addresses in the General-purpose Register Area RP higher bits "0" Generated addresses "0" "0" "0" "0" "0" A15 A14 A13 A12 A11 A10 "0" A9 "1" A8 R4 R3 A7 R2 A6 A5 R1 A4 OP code in lower bits R0 A3 b2 A2 b1 A1 b0 A0 The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at the time of an interrupt. H flag I flag IL1, 0 16 : The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow from bit 4 to bit 3. The bit is cleared to “0” in other instances. The flag is for decimal adjustment instructions; do not use for other than additions and subtractions. : Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The flag is set to “0” when reset. : Indicates the level of the interrupt currently enabled. An interrupt is processed only if its level is higher than the value this bit indicates. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low Higher Lower = no interruption MB89580B/580BW series N flag Z flag V flag C flag : The flag is set to “1” when an arithmetic operation results in setting of the MSB to “1” or is cleared to “0” when the MSB is set to “1.” : The flag is set to “1” when an arithmetic operation results in “0” or is set to “0” in other instances. : The flag is set to “1” when an arithmetic operation results in two’s complement overflow or is cleared to “0” if no overflow occurs. : The flag is set to “1” when an arithmetic operation results in a carry from bit 7 or in a borrow to bit 7. The flag is cleared to “0” if neither of them occurs. In the case of a shift instruction, the flag is set to the shift-out value. The following general-purpose registers are provided: •General-purpose registers : 8-bit data storage registers The general-purpose registers are 8 bits in length and located in the register banks in the memory. One bank contains eight registers and the MB89580B/BW microcontrollers allow a total of 16 banks to be used at maximum. The bank currently in use is indicated by the register bank pointer (RP) . Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 17 MB89580B/580BW series ■ I/O MAP Address Register name Register description 00H PDR0 Port 0 data register 01H DDR0 Port 0 direction register 02H PDR1 Port 1 data register 03H DDR1 Port 1 direction register 04H PDR2 Port 2 data register 05H Vacancy 06H Vacancy Read/write Initial value R/W XXXXXXXX W 00000000 R/W XXXXXXXX W 00000000 R/W 00000000 07H SYCC System clock control register R/W XXX1 1X 0 0 08H STBC Standby control register R/W 0 0 0 1XXXX 09H WDTC Watchdog timer control register R/W 0 XXXXXXX 0AH TBTC Timebase timer control register R/W 0 0 XXX 0 0 0 0BH Vacancy 0CH PDR3 Port 3 data register R/W XXXXXXXX 0DH DDR3 Port 3 direction register R/W 00000000 0EH Vacancy 0FH Vacancy 10H PDR4 Port 4 data register R/W XXXXXXXX 11H DDR4 Port 4 direction register R/W 00000000 12H PDR5 Port 5 data register R/W XXX1 1 1XX 13H DDR5 Port 5 direction register R/W XXXXXX 0 0 14H PDR6 Port 6 data register R/W XXXXXXXX 15H PDCR Parallel port data control register R/W XXX0 0 0 0 0 16H to 20H Vacancy 21H PURR0 Port 0 pullup option setting register R/W 11111111 22H PURR1 Port 1 pullup option setting register R/W 11111111 23H PURR2 Port 2 pullup option setting register R/W 11111111 24H PURR3 Port 3 pullup option setting register R/W 11111111 25H PURR4 Port 4 pullup option setting register R/W 11111111 26H PURR5 Port 5 pullup option setting register R/W XXX 1 1 1 1 1 27H CTR1 PWM control register 1 R/W 00000000 28H CTR2 PWM control register 2 R/W 000X0000 29H CTR3 PWM control register 3 R/W X 0 0 0 XXXX 2AH CMR1 PWM compare register 1 W XXXXXXXX 2BH CMR2 PWM compare register 2 W XXXXXXXX (Continued) 18 MB89580B/580BW series Address Register name 2CH CKR 2DH SCS Register description Read/write Initial value Clock output control register R/W XXXXXXX 0 Serial clock switching register R/W XXXXXXX 0 2EH Vacancy 2FH SMC1 Serial mode control register 1 R/W 00000000 30H SMC2 Serial mode control register 2 R/W 00000000 31H SSD R 0 0 0 0 1 XXX 32H SIDR/SODR Serial input/serial output data register R/W XXXXXXXX 33H SRC Serial rate control register R/W XXXXXXXX Serial status and control register 34H to 3BH Vacancy 3CH EIE External interrupt control register R/W 00000000 3DH EIF External interrupt flag register R/W XXXXXXX 0 R/W XXXXXXX 0 3EH to 3FH 40H Vacancy DMDR USB power supply mode register 41H to 4EH Vacancy 4FH DBARH DMA base address register H R/W 0 0 0 0 0 0 XX 50H UMDR USB reset mode register R/W 1 0 0 0 XX 0 0 51H DBAR DMA base address register R/W XXXXXXXX 52H TDCR0 Transfer data count register 0 R/W X0000000 53H TDCR11 Transfer data count register 11 R/W 00000000 54H TDCR12 Transfer data count register 12 R/W XXXXXX 0 0 55H TDCR21 Transfer data count register 21 R/W 00000000 56H TDCR22 Transfer data count register 22 R/W XXXXXX 0 0 57H TDCR3 Transfer data count register 3 R/W X0000000 58H UCTR USB control register R/W 00000000 59H USTR1 USB status register 1 R/W 00000000 5AH USTR2 USB status register 2 R XXXXXX 0 0 5BH UMSKR USB interrupt mask register R/W 00000000 5CH UFRMR1 USB frame status register 1 R XXXXXXXX 5DH UFRMR2 USB frame status register 2 R XXXXXXXX 5EH EPER USB endpoint enable register R/W XXXX 0 0 0 1 5FH EPBR0 Endpoint 0 setup register R/W X0000000 60H EPBR11 Endpoint setup register 11 R/W 0X000000 61H EPBR12 Endpoint setup register 12 R/W 00000000 (Continued) 19 MB89580B/580BW series (Continued) Address Register name Register description Read/write Initial value 62H EPBR21 Endpoint setup register 21 R/W 0X000000 63H EPBR22 Endpoint setup register 22 R/W 00000000 64H EPBR31 Endpoint setup register 31 R/W XX 0 0 0 0 XX 65H EPBR32 Endpoint setup register 32 R/W X0000000 66H to 7BH Vacancy 7CH ILR1 Interrupt level setting register 1 W 11111111 7DH ILR2 Interrupt level setting register 2 W 11111111 7EH ILR3 level setting register 3 W 11111111 7FH Vacancy • Information about read/write R/W : Read/write enabled, R : Read only, W : Write only • Information about initial values 0 : The initial value of this bit is “0”. 1 : The initial bit of this bit is “1”. X : The initial value of this bit is undefined. Note : Vacancies are not for use. 20 MB89580B/580BW series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage Symbol VCC (VSS = 0 V) Value Unit Max VSS − 0.3 VSS + 6.0 V VSS − 0.3 VCC + 0.3 V Other than P60 to P67 VSS − 0.5 VSS + 4.0 V P60 to P67 Input voltage VI Output voltage VO VSS − 0.3 VCC + 0.3 V “L” level average output current IOLAV 4 mA “L” level total maximum output current ΣIOL 100 mA “L” level total average output current ΣIOLAV 40 mA IOH −15 mA “H” level average output current IOHAV −4 mA “H” level total maximum output current ΣIOH −50 mA “H” level total average output current ΣIOHAV −20 mA Power consumption PD 300 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C “H” level maximum output current Storage temperature Remarks Min Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 21 MB89580B/580BW series 2. Recommended Operating Conditions Parameter Symbol Power supply voltage (VSS = 0 V) Value Unit Remarks Min Typ Max VCC 3.0 5.5 V Operating temperature TA −40 +85 °C Smoothing capacitor CS 0.1 1.0 µF At Vcc = 5.0 V* Series resistance RS 16 Ω When the USB function is in use * : Use either a ceramic capacitor or a capacitor with similar frequency characteristics. The capacity of the smoothing capacitor for the Vcc pin should be greater than that of the Cs. When using with a supply voltage of 3.3 V, connect pin C with Vcc to input 3.3 V. • C, RPVP and RPVM Pin Connection Diagram RS RPVP RS RPVM C CS 22 MB89580B/580BW series 5.5 Operating voltage VCC (V) 5.0 4.0 3.0 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 12.5 10.0 11.0 12.0 13.0 CPU operating frequency (FCH MHz) (At instruction cycle 4/ FCH) 4.0 2.0 0.8 0.4 0.33 0.32 Minimum execution time (instruction cycle) (µs) However, FCH = clock frequency (Fc) × 2 Note: When USB is used, the clock frequency (FC) should be fixed at 6 MHz (CPU operating frequency (FCH) = 12 MHz). And main clock gear speed should be fixed at 4/FCH. Figure 1 Operating voltage - operating frequency WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 23 MB89580B/580BW series 3. DC Characteristics Parameter Symbol Pin name Condition VIH P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, MOD0, MOD1 VIHS “L” level output voltage Unit Typ Max 0.7 VCC VCC + 0.3 V RST, INT0 to INT7, UCK, UI 0.8 VCC VCC + 0.3 V VIH1 P60 to P67 VSS + 2.0 VSS + 3.6 V VIL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, MOD0, MOD1 VSS − 0.3 0.3 VCC V VILS RST, INT0 to INT7, UCK, UI VSS − 0.3 0.2 VCC V VIL1 P60 to P67 VSS − 0.5 VSS + 0.8 V VD1 P52 to P54 VSS − 0.3 VCC + 0.3 V VOH P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50, P51 IOH = −2.0 mA 4.0 V VOL P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50 to P54, RST IOL = 4.0 mA 0.4 V “L” level input voltage “H” level output voltage Value Min “H” level input voltage Open-drain output application voltage (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Remarks (Continued) 24 MB89580B/580BW series (Continued) Parameter Input leakage current (Hi-Z output leakage current) Open-drain output leakage current Pullup resistance (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name Value Min Typ Max Unit Remarks When no pullup resistance is specified ILI P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P60 to P67 0.0 < VI < VCC −5 +5 µA ILIOD P52 to P54 0.0 < VI < VSS + 5.5 +5 µA RPULL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, RST VI = 0.0 V 25 50 100 kΩ RST is excluded when pullup resistance available is specified. FCH = 12.0 MHz VCC = 5.0 V tinst = 0.333 µs 25 38 MB89P585B/BW, MB89585B/BW, mA MB89583B/BW MB89P589B, MB89589B ICCS1 FCH = 12.0 MHz VCC = 5.0 V tinst = 0.333 µs 20 30 mA Sleep mode ICCH TA = 25 °C 5 20 µA f = 1 MHz 10 pF ICC Power supply current Input capacitance Condition VCC CIN Other than Vcc and Vss Stop 25 MB89580B/580BW series 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Parameter RST “L” pulse width Symbol Condition tZLZH Value Min Max 48 tHCLY Unit Remarks ns Note : tHCYL is the internal main clock oscillating cycle (1/2 Fc) . tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset and Power On Time Parameter (VSS = 0 V, TA = −40 °C to +85 °C) Symbol Condition Power supply rising time tR Power supply cutoff time tOFF Value Unit Min Max 0.066 50 ms 4 ns Remarks Due to repeated operations Note : The power supply must be up within the selected oscillation stabilization time. When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the voltage. tR tOFF 3.5 V VCC 0.2 V 26 0.2 V 0.2 V MB89580B/580BW series (3) Clock Timing Parameter (VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition Clock frequency FC X0, X1 Clock cycle time tXCYL X0, X1 Internal main clock frequency FCH Internal clock cycle tHCYL Value Unit Min Typ Max 1 6 6.25 MHz 160 166.6 1000 ns 2 12 12.5 MHz 80 83.3 500 ns Remarks Twice the Fc tXCYL/2 Note: When USB is used, the clock frequency (FC) should be fixed at 6 MHz (CPU operating frequency (FCH) = 12 MHz). And main clock gear speed should be fixed at 4/FCH. • X0 and X1 Timing and Conditions tXCYL X0 0.2 VCC 0.2 VCC • Clock Conditions When a crystal resonator is used X0 X1 C1 C2 (4) Instruction Cycle Parameter Instruction cycle (Min execution time) (VSS = 0 V, TA = −40 °C to +85 °C) Symbol Value Unit Remarks tinst 4 / FCH, 8 / FCH, 16 / FCH, 64 / FCH µs When operating at FCH = 12 MHz tinst = 0.33 µs (4 / FCH) 27 MB89580B/580BW series (5) UART Serial I/O Timing Parameter (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC UCK UCK ↓ → UO tSLOV UCK, UO Valid UI → UCK↑ tIVSH UI, UCK UCK ↑ → valid UI hold time tSHIX UCK, UI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH UCK ↓ → UO time tSLOV UCK, UO Valid UI → UCK↑ tIVSH UI, UCK UCK ↑ → valid UI hold time tSHIX UCK, UI Value Condition Internal shift clock mode UCK External shift clock mode Max 2 tinst* µs −200 200 ns 200 ns 200 ns 1 tinst* µs 1 tinst* µs 0 200 ns 200 ns 200 ns * : For information about tinst, see “Instruction Cycle.” • Internal shift clock mode tSCYC UCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V 0.8 V UO tIVSH tSHIX 0.8 VCC 0.2 VCC UI 0.8 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL UCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV UO 2.4 V 0.8 V tIVSH UI 28 0.8 VCC 0.2 VCC Unit Min tSHIX 0.8 VCC 0.2 VCC Remarks MB89580B/580BW series (6) Peripheral Input Timing Parameter (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Pin name Value Condition Unit Min Max 2 tinst* µs 2 tinst* µs Remarks INT0 to INT7 * : For information about tinst, see “Instruction Cycle.” tIHIL1 INT0 to INT7 tILIH1 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 29 MB89580B/580BW series (7) Parallel Port Timing Parameter 30 (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition IBFX ↑ → WEX ↓ timing tIHWL IBFX WEX CEX ↓ → WEX ↓ delay tCLWL WEX ↑ → CEX ↑ delay Value Unit Min Max 1 / 2•tinst µs CEX WEX 0 ns tWHCH CEX WEX 0 ns WEX pulse width tWLWH WEX 40 ns Write data setup tDVWH D0 to D7 WEX 10 ns Write data hold tWHDX D0 to D7 WEX 10 ns Write address setup tAVWH A0 WEX 10 ns Write address hold tWHAX A0 WEX 10 ns OBF ↑ → RDX ↓ timing tOHRL OBF RDX 1 / 2•tinst µs CEX ↓ → RDX ↓ delay tCLRL CEX RDX 0 ns RDX ↑ → CEX ↑ delay tRHCH CEX RDX 0 ns RDX pulse width tRLRH RDX 40 ns Read data delay tRLDV D0 to D7 RDX 15 ns Read data hold tRHDX D0 to D7 RDX 0 ns Read address setup tAVRL A0 RDX 10 ns Read address hold tRHAX A0 RDX 10 ns Remarks MB89580B/580BW series • Write Timing IBFX tIHWL CEX tCLWL tWHCH WEX tWLWH D0 to D7 tDVWH tWHDX tAVWH tWHAX A0 • Read Timing OBF tOHRL CEX tCLRL tRHCH RDX tRLRH D0 to D7 tRLDV tRHDX A0 tAVRL tRHAX 31 MB89580B/580BW series (8) External FIFO Connection Timing Parameter 32 (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C, FC = 6 MHz) Symbol Pin name Condition Value Unit Remarks ns Resetting before PKEND is not allowed. Min Max 0 FIFO empty resetting timing tEFXH EFX Not including the initial resetting after reset FIFO empty timing tEFXL EFX, R 0 360 ns Read cycle time tRSCY 645 ns Read clock “H” pulse width tRHWD 145 ns Valid DI → R ↓ setup time tDISP 50 ns R ↓ → valid DI hold time tDIHD DI7 to DI0, R 0 ns FIFO full reset timing tFFXH FFX 0 ns FIFO full timing tFFXL FFX, W 0 360 ns Write recycle time tWSCY 645 ns Write clock “H” pulse width tWHWD 145 ns Valid DO → W ↑ setup time tDOSP 200 ns W ↓ → valid DO hold time tDOHD 40 ns R W DO7 to DO0, W Resetting before PKEND is not allowed. MB89580B/580BW series • Read Data from External FIFO tEFXH PKEND 0.7 VCC EFX (P52) 0.3 VCC tEFXL tRSYC 2.4 V 2.4 V R (P51) 0.8 V 0.8 V tRHWD tDISP tDIHD DI7 to DI0 2.0 V Valid 0.8 V Invalid Invalid Valid Invalid • Write Data to External FIFO PKEND tFFXH 0.7 VCC FFX (P53) 0.3 VCC tWSCY W (P50) tFFXL 2.4 V 2.4 V 0.8 V tWHWD 0.8 V tDOSP tDOHD 2.4 V 2.4 V 0.8 V 0.8 V DO7 to DO0 33 MB89580B/580BW series ■ ORDERING INFORMATION Part number 34 Package MB89589BPFM MB89P589BPFM 64-pin plastic LQFP (FPT-64P-M09) MB89583BPFV MB89585BPFV MB89P585BPFV MB89583BWPFV MB89585BWPFV MB89P585BWPFV 64-pin plastic LQFP (FPT-64P-M03) Remarks MB89580B/580BW series ■ PACKAGE DIMENSIONS 64-pin plastic LQFP (FPT-64P-M03) Note: Pins width and pins thickness include plating thickness. 12.00±0.20(.472±.008)SQ 10.00±0.10(.394±.004)SQ 48 0.145±0.055 (.006±.002) 33 49 32 Details of "A" part 0.08(.003) +0.20 1.50 –0.10 +.008 .059 –.004 INDEX 64 0°~8° 17 (Mounting height) 0.10±0.10 (.004±.004) (Stand off) "A" LEAD No. 1 16 0.50(.020) C 0.20±0.05 (.008±.002) 0.08(.003) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 2000 FUJITSU LIMITED F64009S-c-4-7 Dimensions in mm (inches) (Continued) 35 MB89580B/580BW series (Continued) 64-pin plastic LQFP (FPT-64P-M09) Note: Pins width and pins thickness include plating thickness. 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.0057±.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8° 64 17 1 0.65(.026) C "A" 16 0.32±0.05 (.013±.002) 0.13(.005) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) M 2001 FUJITSU LIMITED F64018S-c-2-4 Dimensions in mm (inches) 36 MB89580B/580BW series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0202 FUJITSU LIMITED Printed in Japan