FUJITSU SEMICONDUCTOR DATA SHEET DS07-12534-4E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89620R Series MB89623R/625R/P625/W625/626R/627R/P627/W627/T627R MB89PV620 ■ DESCRIPTION The MB89620R series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external interrupt. The MB89620R series is applicable to a wide range of applications from consumer products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • Various package options Three types of QFP packages (1 mm, 0.65 mm, or 0.5 mm lead pitch) SDIP packages • High-speed processing at low voltage Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Four types of timers 8-bit PWM timer (also usable as a reload timer) 8-bit pulse width count timer (Continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 20-bit timebase timer • Two serial interfaces Switchable transfer direction allows communication with various equipment. • 8-bit A/D converter Sense mode function enabling comparison at 5 µs Activation by an external input capable (Continued) MB89620R Series (Continued) • External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) • Bus interface functions Including hold and ready functions ■ PACKAGE 64-pin Plastic SH-DIP 64-pin Plastic LQFP (DIP-64P-M01) (FPT-64P-M03) 64-pin Ceramic SH-DIP (DIP-64C-A06) 2 64-pin Plastic QFP (FPT-64P-M06) 64-pin Ceramic MQFP (MQP-64C-P01) 64-pin Plastic QFP (FPT-64P-M09) 64-pin Ceramic MDIP (MDP-64C-P02) MB89620R Series ■ PRODUCT LINEUP Part number Parameter MB89P625 MB89P627 MB89PV620 MB89623R MB89625R MB89626R MB89627R MB89T627R MB89W625 MB89W627 Classificati on External ROM products Mass production products (mask ROM products) ROM size 8 K × 8 bits 16 K × 8 bits 24 K × 8 bits 32 K × 8 bits External (internal (internal (internal (internal ROM mask ROM) mask ROM) mask ROM) mask ROM) 1 K × 8 bits 1 K × 8 bits One-time PROM products/EPROM products 16 K × 8 bits (internal PROM, programmable with generalpurpose EPROM programmer) 512 × 8 bits Piggyback/ evaluation product for evaluation and development 32 K × 8 bits 32 K × 8 bits (internal (external PROM, programmable ROM) with generalpurpose EPROM programmer) RAM size 256 × 8 bits 512 × 8 bits 768 × 8 bits 1 K × 8 bits CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs /10 MHz 3.6 µs/10 MHz Ports Input ports: Output ports (N-ch open-drain): I/O ports (N-ch open-drain) Output ports (CMOS): I/O ports (CMOS): Total: 5 (4 ports also serve as peripherals.) 8 (All also serve as peripherals.) 8 (4 ports also serve as peripherals.) 8 (All also serve as bus control pins.) 24 (All also serve as bus pins or peripherals.) 53 1 K × 8 bits 8-bit PWM timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) 8-bit resolution PWM operation (conversion cycle: 102 µs to 839 ms) 8-bit pulse width count timer 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs) 8-bit pulse width measurement operation (Continuous measurement “H” pulse width/“L” pulse width/from ↑ to ↑/from ↓ to ↓ capable) 16-bit timer/ counter 16-bit timer operation (operating clock cycle: 0.4 µs) 16-bit event counter operation (Rising/falling/both edges selectable) 8-bit serial I/O 1, 8-bit serial I/O 2 8 bits LSB first/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) 8-bit A/D converter 8-bit resolution × 8 channels A/D conversion mode (conversion time: 18 µs) Sense mode (conversion time: 5 µs) Continuous activation by an external activation or an internal timer capable Reference voltage input (Continued) 3 MB89620R Series (Continued) Part number Parameter MB89P625 MB89P627 MB89PV620 MB89623R MB89625R MB89626R MB89627R MB89T627R MB89W625 MB89W627 External interrupt 4 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Standby modes Sleep mode, stop mode Process CMOS Operating voltage* 2.2 V to 6.0 V 2.7 V to 6.0 V EPROM for use MBM27C256 A-20TV MBM27C256 A-20CZ — *: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ PACKAGE AND CORRESPONDING PRODUCTS MB89623R MB89625R MB89626R MB89627R MB89T627R MB89P625 MB89W625 MB89W627 MB89PV620 × × ×* ×* FPT-64P-M06 × × FPT-64P-M09 ×* ×* Package MB89P627 DIP-64P-M01 ×* FPT-64P-M03 ×* DIP-64C-A06 × × × MQP-64C-P01 × × × × MDP-64C-P02 × × × × : Available × ×: Not available *: Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available. 64SD-64QF2-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M03 64SD-64SQF-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M09 Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Note: For more information about each package, see section “■ Package Dimensions.” 4 MB89620R Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89623R, the upper half of the register bank cannot be used. • On the MB89P627, the program area starts from address 8007H but on the MB89PV620 and MB89627R starts from 8000H. (On the MB89P627, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV620 and MB89627R, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P627.) • The stack area, etc., is set at the upper limit of the RAM. • The external area is used. 2. Current Consumption • In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section “■ Electrical Characteristics”.) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • A pull-up resistor cannot be set for P40 to P47 on the MB89P625, MB89W625, MB89P627, and MB89W627. • A pull-up resistor is not selectable for P50 to P57 when the A/D converter is used. • Options are fixed on the MB89PV620. 5 MB89620R Series 4. Differences between the MB89620 and MB89620R Series • Memory access area Memory access area of the following products is the same; both the MB89625 and MB89625R, and both the MB89627 and MB89627R. The access area of the MB89623 and MB89626 is different from that of the MB89623R and MB89626R respectively when using in external bus mode. See below. Memory area Address MB89623 MB89623R 0000H to 007FH I/O area I/O area 0080H to 017FH RAM area RAM area 0180H to 027FH 0280H to BFFFH Access prohibited External area External area C000H to DFFFH E000H to FFFFH Access prohibited ROM area ROM area Memory area Address MB89626 MB89626R 0000H to 007FH I/O area I/O area 0080H to 037FH RAM area RAM area 0380H to 047FH 0480H to 7FFFH Access prohibited External area External area 8000H to 9FFFH A000H to FFFFH Access prohibited ROM area ROM area • Other specifications Both the MB89620R and MB89620 series is the same. • Electrical specifications/electrical characteristics Electrical specifications of the MB89620R series are the same with that of the MB89620 series. ■ CORRESPONDENCE BETWEEN THE MB89620 AND MB89620R SERIES • The MB89620R series is the reduction version of the MB89620 series. • The MB89620 and MB89620R series consist of the following products: MB89620 series MB89623 MB89625 MB89626 MB896267 MB89623R MB89625R MB89626R MB896267R MB89W625 MB89W627 MB89T627R MB89P625 MB89620R series MB89620 series MB89620R series 6 MB89P627 MB89PV620 MB89620R Series ■ PIN ASSIGNMENT (Top view) P36/WTO P37/PTO P40 P41 P42 P43 P44/BZ P45/SCK2 P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 64 63 VCC 62 92 61 A14 91 60 A13 90 59 A8 89 58 A9 88 57 A11 87 56 OE 86 55 A10 85 54 CE 84 53 O8 83 52 O7 82 51 O6 81 50 O5 80 49 O4 79 48 47 46 45 44 Each pin inside the 43 dashed line is for the 42 41 MB89PV620 only. 40 39 38 37 36 35 34 33 VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30/ADST VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC P21/HAK P22/HRQ P23/RDY P24/CLK P25/WR P26/RD P27/ALE (DIP-64P-M01) (DIP-64C-A06) (MDP-64C-P02) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P45/SCK2 P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30/ADST VSS (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 (FPT-64P-M03) (FPT-64P-M09) 7 MB89620R Series 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 94 95 96 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Each pin inside the dashed line is for the MB89PV620 only. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/ADST VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK 20 21 22 23 24 25 26 27 28 29 30 31 32 P45/SCK2 P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 84 83 82 81 80 79 78 64 63 62 61 60 59 58 57 56 55 54 53 52 P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 (Top view) (FPT-64P-M06) (MQP-64C-P01) • Pin assignment on package top (MB89PV620 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 65 N.C. 73 A2 81 N.C. 89 OE 66 VPP 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 VSS 88 A10 96 VCC N.C.: Internally connected. Do not use. 8 MB89620R Series ■ PIN DESCRIPTION Pin no. Pin name SH-DIP*1 MDIP*2 QFP1*3 MQFP*4 LQFP*5 QFP2*6 30 23 22 X0 31 24 23 X1 28 21 20 MOD0 29 22 21 MOD1 27 20 19 RST 56 to 49 49 to 42 48 to 41 41 to 34 40 33 32 39 32 38 Circuit type Function A Crystal oscillator pins B Operating mode selection pins Connect directly to VCC or VSS. C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 48 to 41 P00/AD0 to P07/AD7 D General-purpose I/O ports When an external bus is used, these ports function as multiplex pins of lower address output and data I/O. 40 to 33 P10/A08 to P17/A15 D General-purpose I/O ports When an external bus is used, these ports function as upper address output. P20/BUFC F General-purpose output-only port When an external bus is used, this port can also be used as a buffer control output by setting the BCTR. 31 P21/HAK F General-purpose output-only port When an external bus is used, this port can also be used as a hold acknowledge output by setting the BCTR. 31 30 P22/HRQ D General-purpose output-only port When an external bus is used, this port can also be used as a hold request input by setting the BCTR. 37 30 29 P23/RDY D General-purpose output-only port When an external bus is used, this port functions as a ready input. 36 29 28 P24/CLK F General-purpose output-only port When an external bus is used, this port functions as a clock output. 35 28 27 P25/WR F General-purpose output-only port When an external bus is used, this port functions as a write signal output. 34 27 26 P26/RD F General-purpose output-only port When an external bus is used, this port functions as a read signal output. 33 26 25 P27/ALE F General-purpose output-only port When an external bus is used, this port functions as an address latch signal output. (Continued) *1: DIP-64P-M01, DIP-64C-A06 *4: MQP-64C-P01 *2: MDP-64C-P02 *5: FPT-64P-M03 *3: FPT-64P-M06 *6: FPT-64P-M09 9 MB89620R Series (Continued) Pin no. *1 Pin name Circuit type Function SH-DIP MDIP*2 QFP1*3 MQFP*4 LQFP*5 QFP2*6 58 51 50 P30/ADST E General-purpose I/O port Also serves as an A/D converter external activation. This port is a hysteresis input type. 59 52 51 P31/SCK1 E General-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O 1. This port is a hysteresis input type. 60 53 52 P32/SO1 E General-purpose I/O port Also serves as the data output for the 8-bit serial I/O 1. This port is a hysteresis input type. 61 54 53 P33/SI1 E General-purpose I/O port Also serves as the data input for the 8-bit serial I/O 1. This port is a hysteresis input type. 62 55 54 P34/EC E General-purpose I/O port Also serves as the external clock input for the 16-bit timer/counter. This port is a hysteresis input type. 63 56 55 P35/PWC E General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width count timer. This port is a hysteresis input type. 1 58 57 P36/WTO E General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width count timer. This port is a hysteresis input type. 2 59 58 P37/PTO E General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. This port is a hysteresis input type. 3 to 6 60 to 63 G N-ch open-drain I/O ports These ports are a hysteresis input type. 7 64 63 P44/BZ G N-ch open-drain I/O port Also serves as a buzzer output. This port is a hysteresis input type. 8 1 64 P45/SCK2 G N-ch open-drain I/O port Also serves as the clock I/O for the 8-bit serial I/O 2. This port is a hysteresis input type. 9 2 1 P46/SO2 G N-ch open-drain I/O port Also serves as the data output for the 8-bit serial I/O 2. This port is a hysteresis input type. 10 3 2 P47/SI2 G N-ch open-drain I/O port Also serves as the data input for the 8-bit serial I/O 2. This port is a hysteresis input type. 59 to 62 P40 to P43 (Continued) *1: DIP-64P-M01, DIP-64C-A06 *4: MQP-64C-P01 10 *2: MDP-64C-P02 *5: FPT-64P-M03 *3: FPT-64P-M06 *6: FPT-64P-M09 MB89620R Series (Continued) Pin no. SH-DIP*1 MDIP*2 QFP1*3 MQFP*4 LQFP*5 QFP2*6 Pin name Circuit type 11 to 18 4 to 11 3 to 10 P50/AN0 to P57/AN7 H N-ch open-drain output-only ports Also serve as the analog input for the A/D converter. 22 to 25 15 to 18 14 to 17 P60/INT0 to P63/INT3 I General-purpose input-only ports Also serve as an external interrupt input. These ports are a hysteresis input type. 26 19 18 P64 I General-purpose input-only port This port is a hysteresis input type. 64 57 56 VCC — Power supply pin 32, 57 25, 50 24, 49 VSS — Power supply (GND) pins 19 12 11 AVCC — A/D converter power supply pin 20 13 12 AVR — A/D converter reference voltage input pin 21 14 13 AVSS — A/D converter power supply (GND) pin Use this pin at the same voltage as VSS. *1: DIP-64P-M01, DIP-64C-A06 *4: MQP-64C-P01 Function *2: MDP-64C-P02 *5: FPT-64P-M03 *3: FPT-64P-M06 *6: FPT-64P-M09 11 MB89620R Series • External EPROM pins (MB89PV620 only) Pin no. MDIP *1 MQFP*2 I/O Function 65 66 VPP O “H” level output pin 66 67 68 69 70 71 72 73 74 67 68 69 70 71 72 73 74 75 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 75 76 77 77 78 79 O1 O2 O3 I Data input pins 78 80 VSS O Power supply (GND) pin 79 80 81 82 83 82 83 84 85 86 O4 O5 O6 O7 O8 I Data input pins 84 87 CE O ROM chip enable pin Outputs “H” during standby. 85 88 A10 O Address output pin 86 89 OE O ROM output enable pin Outputs “L” at all times. 87 88 89 91 92 93 A11 A9 A8 O Address output pins 90 94 A13 O 91 95 A14 O 92 96 VCC O EPROM power supply pin — 65 76 81 90 N.C. — Internally connected pins Be sure to leave them open. *1: MDP-64C-P02 *2: MQP-64C-P01 12 Pin name MB89620R Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X1 X0 Standby control signal B C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D • CMOS output • CMOS input R P-ch N-ch • Pull-up resistor optional (except P22 and P23) E • CMOS output • Hysteresis input R P-ch N-ch • Pull-up resistor optional F • CMOS output P-ch N-ch (Continued) 13 MB89620R Series (Continued) Type Circuit Remarks G • N-ch open-drain output • Hysteresis input R N-ch • Pull-up resistor optional (MB89623R, MB89625R, MB89626R, and MB89627R only) H • N-ch open-drain output • Analog input R N-ch Analog input I • Hysteresis input • Pull-up resistor optional R 14 • Pull-up resistor optional MB89620R Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 15 MB89620R Series ■ PROGRAMMING TO THE EPROM ON THE MB89P625 The MB89P625 is an OTPROM version of the MB89620R series. 1. Features • 16-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below. Single chip Address EPROM mode (Corresponding addresses on the EPROM programmer) 0000 H I/O 0080 H RAM 0280 H External area BFF0H 3FF0 H External area BFF6H Option area 3FF6H Vacancy (Read value: FF H) External area C000H 4000H PROM 16 KB FFFFH EPROM 16 KB 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P625 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see “4. Setting OTPROM Options.”) (3) Program to 3FF0H to 7FFFH with the EPROM programmer. 16 MB89620R Series 4. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map (MB89P625) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Vacancy Vacancy Vacancy Vacancy Vacancy Bit 2 Reset pin output 1: Yes 0: No Bit 1 Oscillation stabilization time 1: Crystal 0: Ceramic Bit 0 Power-on reset 1: Yes 0: No Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable 3FF1H P07 Pull-up 1: No 0: Yes P06 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes 3FF2H P17 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes 3FF3H P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes 3FF4H P57 Pull-up 1: No 0: Yes P56 Pull-up 1: No 0: Yes P55 Pull-up 1: No 0: Yes P54 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable P64 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes 3FF0H 3FF5H Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected. 17 MB89620R Series ■ PROGRAMMING TO THE EPROM ON THE MB89P627 The MB89P627 is an OTPROM version of the MB89620R series. 1. Features • 32-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below. Single chip Address EPROM mode (Corresponding addresses on the EPROM programmer) 0000H I/O 0080H RAM 0480H External area 8000H 0000H External area 8007HH Option area 0007H PROM 32 KB FFFFH EPROM 32 KB 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P627 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as a single chip assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “4. Setting OTPROM Options.”) (3) Program to 0000H to 7FFFH with the EPROM programmer. 18 MB89620R Series 4. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map (MB89P627) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Vacancy Vacancy Vacancy Vacancy Vacancy Bit 2 Reset pin output 1: Yes 0: No Bit 1 Oscillation stabilization time 1: Crystal 0: Ceramic Bit 0 Power-on reset 1: Yes 0: No Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable 0001H P07 Pull-up 1: No 0: Yes P06 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes 0002H P17 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes 0003H P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes 0004H P57 Pull-up 1: No 0: Yes P56 Pull-up 1: No 0: Yes P55 Pull-up 1: No 0: Yes P54 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable P64 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable 0000H 0005H 0006H Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected. 19 MB89620R Series ■ HANDLING THE MB89P625/P627 1. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 h Data verification Assembly 2. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 3. Erasure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 Ws/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000Å. Although erasure time will be much longer than with UV source at 2537Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. 20 MB89620R Series 4. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer Part number Package Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name UNISITE MB89P625P-SH SH-DIP-64 ROM-64SD-28DP-8L MB89P625PF QFP-64 ROM-64QF-28DP-8L MB89P625PFM QFP-64 ROM-64QF2-28DP-8L Advantest Corp. Data I/O Co., Ltd. 3900 Recommended Recommended Recommended — 2900 R4945A — Recommended Recommended Recommended *: It is required to connect a capacitor of approximately 0.1 µF between VPP and GND, and VCC and GND. Inquiry:Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Data I/O Co., Ltd.: TEL:USA/ASIA(1)-206-881-6444 EUROPE(49)-8-985-8580 Advantest Corp.:TEL:Except JAPAN (81)-3-3930-4111 21 MB89620R Series ■ PROGRAMMING TO THE EPROM PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV, MBM27C256A-20CZ 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 3. Memory Space Memory space in 32-Kbyte PROM is diagrammed below. Single chip Corresponding addresses on the EPROM programmer Address 0000H I/O 0080H RAM 0480H Not available 8000H 0000H Not available 8006H Not available 0006H PROM 32 KB FFFFH EPROM 32 KB 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0006H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 22 MB89620R Series ■ BLOCK DIAGRAM X0 X1 20-bit timebase timer Oscillator Clock controller 8-bit PWM timer P37/PTO 8-bit pulse width count timer P36/WTO 8 P10/A08 to P17/A15 8 P35/PWC Port 3 CMOS I/O port Ports 0 and 1 P00/AD0 to P07/AD7 Internal bus Reset circuit (WDT) RST P34/EC 16-bit timer/counter P33/SI1 P32/SO1 P31/SCK1 8-bit serial I/O 1 MOD0 MOD1 External bus interface P30/ADST Port 2 CMOS I/O port P47/SI2 P46/SO2 P45/SCK2 CMOS output port Port 4 8-bit serial I/O 2 Buzzer output P44/BZ 4 P40 to P43 N-ch open-drain I/O port N-ch open-drain output port 8 F2MC-8L CPU 8-bit A/D converter Port 5 RAM 8 ROM External interrupt The other pins VCC, VSS × 2 P50/AN0 to P57/AN7 AVR AVCC AVSS 4 4 Port 6 P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC P60/INT0 to P63/INT3 P64 Input port 23 MB89620R Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89620R series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89620R series is structured as illustrated below. • Memory Space 0000H MB89PV620 0000H I/O 0080H MB89623R 0080H 0080H 0000H I/O RAM 768 B RAM 1 KB 0100H 0100H Register MB89627R MB89P627 MB89T627R MB89W627 0080H 0080H 0100H Register Register MB89626R I/O RAM 512 B RAM 256 B 0100H 0000H I/O I/O RAM 1 KB 0100H 0000H MB89625R MB89P625 MB89W625 Register Register 0180H 0200H *3 0280H 0200H 0200H 0200H 0280H 0380H 0480H 0480H 8000H 8006H External area External area *2 8000H A000H External ROM 32 KB FFFFH External area External area *3 0480H 8000H 8006H C000H C000H *3 ROM* 1 8 KB FFFFH FFFFH External area *2 ROM 32 KB ROM 24 KB ROM*1 16 KB E000H FFFFH *3 FFFFH *1: The ROM area is an external area depending on the mode. *2: Since addresses 8000H to 8005H for the MB89P627 and MB89W627 comprise an option area, do not use this area for the MB89PV620 and MB89627R. *3: Access to this area is prohibited when using external bus mode. 24 MB89620R Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits FFFDH : Program counter PC A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the Program Status Register 15 PS 14 13 12 RP 11 10 9 8 Vacancy Vacancy Vacancy RP 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 25 MB89620R Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag:Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise. V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 26 MB89620R Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89620R. In the MB89623R, there are 16 banks in internal RAM. The remaining 16 banks can be extended externally by allocating an external RAM to addresses 0180H to 01FFH using an external circuit. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. • Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 27 MB89620R Series ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (R/W) BCTR External bus pin control register 06H Vacancy 07H Vacancy 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Timebase timer control register Vacancy 0BH 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H (R/W) PDR5 Port 5 data register 11H (R) PDR6 Port 6 data register 12H (R/W) CNTR PWM control register 13H (W) COMR PWM compare register 14H (R/W) PCR1 PWC pulse width control register 1 15H (R/W) PCR2 PWC pulse width control register 2 16H (R/W) RLBR PWC reload buffer register 17H Vacancy 18H (R/W) TMCR 16-bit timer control register 19H (R/W) TCHR 16-bit timer count register (H) 1AH (R/W) TCLR 16-bit timer count register (L) Vacancy 1BH 1CH (R/W) SMR1 Serial I/O 1 mode register 1DH (R/W) SDR1 Serial I/O 1 data register 1EH (R/W) SMR2 Serial I/O 2 mode register 1FH (R/W) SDR2 Serial I/O 2 data register (Continued) 28 MB89620R Series (Continued) Address Read/write Register name Register description 20H (R/W) ADC1 A/D converter control register 1 21H (R/W) ADC2 A/D converter control register 2 22H (R/W) ADCD A/D converter data register Vacancy 23H 24H (R/W) EIC1 External interrupt 1 control register 1 25H (R/W) EIC2 External interrupt 1 control register 2 26H to 7BH Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Vacancy Note: Do not use vacancies. 29 MB89620R Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Rating Min. Max. Unit Remarks Power supply voltage VCC AVCC VSS – 0.3 VSS + 7.0 V *1 A/D converter reference input voltage AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed AVCC + 0.3 V. VI VSS – 0.3 VCC + 0.3 V Except P40 to P47*2 VI2 VSS – 0.3 VSS + 7.0 V P40 to P47 VO VSS – 0.3 VCC + 0.3 V Except P40 to P47*2 VO2 VSS – 0.3 VSS + 7.0 V P40 to P47 “L” level maximum output current IOL 20 mA “L” level average output current IOLAV 4 mA “L” level total maximum output current ∑IOL 100 mA “L” level total average output current ∑IOLAV 40 mA “H” level maximum output current IOH –20 mA “H” level average output current IOHAV –4 mA “H” level total maximum output current ∑IOH –50 mA “H” level total average output current ∑IOHAV –20 mA Power consumption PD 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Input voltage Output voltage Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) *1: Use AVCC and VCC set to the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2: VI and VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 30 MB89620R Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Symbol Parameter A/D converter reference input voltage Operating temperature Unit 2.2* 6.0* V 2.7* 6.0* V 1.5 6.0 V AVR 0.0 AVCC V TA –40 +85 °C VCC AVCC Power supply voltage Value Min. Max. Remarks Normal operation assurance range* (MB89623R/625R/626R/627R) Normal operation assurance range* (MB89P625/W625/P627/T627R/W627/PV620) Retains the RAM state in stop mode *: These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” Figure 1 Operating Voltage vs. Clock Operating Frequency 6 Analog accuracy assured in the AVCC = VCC = 3.5 V to 6.0 V range 5 Operating voltage (V) Operation assurance range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Clock operating frequency (MHz) Note: The shaded area is assured only for the MB89623R/625R/626R/627R. Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 31 MB89620R Series 3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition Value Min. Typ. Max. Unit VIH P00 to P07, P10 to P17, P22, P23 0.7 VCC VCC + 0.3 V VIHS RST, MOD0, MOD1, P30 to P37, P60 to P64 0.8 VCC VCC + 0.3 V VIHS2 P40 to P47 0.8 VCC VCC + 0.3 V VIL P00 to P07, P10 to P17, P22, P23 VSS − 0.3 0.3 VCC V VILS RST, MOD0, MOD1, P30 to P37, P40 to P47, P60 to P64 VSS − 0.3 0.2 VCC V VD P50 to P57 VSS − 0.3 VCC + 0.3 V VD2 P40 to P47 VSS − 0.3 VSS + 6.0 V VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37 IOH = –2.0 mA 4.0 V VOL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57 0.4 V VOL2 RST 0.4 V Input leakage current ILI1 (Hi-z output leakage current) P00 to P07, P10 to P17, P20 to P27, 0.0 V < VI < P30 to P37, VCC P40 to P47, P60 to P64, MOD0, MOD1 ±5 µA Pull-up resistance P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64, RST 25 50 100 kΩ “H” level input voltage “L” level input voltage Open-drain output pin application voltage “H” level output voltage “L” level output voltage RPULL IOL = +4.0 mA VI = 0.0 V Remarks Without pull-up resistor (Continued) 32 MB89620R Series (Continued) (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition FC = 10 MHz Normal operating mode tinst*2 = 0.4 µs ICC VCC Power supply current*1 Min. — Typ. 9 Max. Unit 15 — 10 18 MB89P625/ W625 mA MB89P627/ W627 FC = 10 MHz Sleep mode tinst*2 = 0.4 µs — 3 4 mA ICCH Stop mode TA = +25°C — — 1 µA IA FC = 10 MHz, when starting A/D conversion — 1 3 mA FC = 10 MHz, TA = +25°C, when stopping A/D conversion — — 1 µA f = 1 MHz — 10 pF IAH CIN Other than AVCC, AVSS, VCC, and VSS Remarks MB89623R/ 625R/626R/ mA 627R/T627R/ PV620 ICCS AVCC Input capacitance Value *1: In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included. The power supply current is measured at the external clock. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 33 MB89620R Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 16 tXCYL — Unit Remarks ns Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 0.2 V 34 0.2 V 0.2 V MB89620R Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Clock frequency FC Clock cycle time Parameter Condition Value Unit Remarks Min. Max. X0, X1 1 10 MHz tXYCL X0, X1 100 1000 ns Input clock pulse width PWH PWL X0 20 — ns External clock Input clock rising/falling time tCR tCF X0 — 10 ns External clock — • X0 and X1 Timing and Conditions tXCYL PW PWL tCR 0.8 VCC tCF 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC • Clock Conditions When a crystal or ceramic resonator is used X0 When an external clock is used X1 X0 X1 Open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) Unit Remarks 4/FC µs tinst = 0.4 µs when operating at FC = 10 MHz 35 MB89620R Series (5) Clock Output Timing (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Symbol Parameter Cycle time Pin name Condition tCYC CLK CLK ↑ → CLK ↓ Value Remarks — ns tXCYL × 2 at 10 MHz oscillation 100 ns Approx. tCYC/2 at 10 MHz oscillation Max. 200 30 — tCHCL tCYC tCHC 2.4 V 2.4 V CLK 0.8 V 36 Unit Min. MB89620R Series (6) Bus Read Timing (VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Value Condition Min. Max. Unit Remarks Valid address → RD ↓ time tAVRL RD, A15 to A08, AD7 to AD0 1/4 tinst*– 64 ns — µs RD pulse width tRLRH RD 1/4 tinst*– 20 ns — µs Valid address → data read time tAVDV AD7 to AD0, A15 to A08 — 1/2 tinst* µs In the case of no wait RD ↓ → data read time tRLDV RD, AD7 to AD0 — 1/2 tinst*– 80 ns µs In the case of no wait RD ↑ → data hold time tRHDX AD7 to AD0, RD 0 — µs RD ↑ → ALE ↑ time tRHLH RD, ALE 1/4 tinst*– 40 ns — µs RD ↑ → address invalid time tRHAX RD, A15 to A08 1/4 tinst*– 40 ns — µs RD ↓ → CLK ↑ time tRLCH 1/4 tinst*– 40 ns — µs CLK ↓ → RD ↑ time tCLRH 0 — ns RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — µs A15 to A08, AD7 to AD0, BUFC 5 — µs — RD, CLK BUFC ↑ → valid address time tBHAV *: For information on tinst, see “(4) Instruction Cycle.” 2.4 V CLK 0.8 V tRHL ALE 0.8 V AD 2.4 V 0.7 VCC 0.3 VCC 0.8 V tAVD A 2.4 V 0.8 V 0.7 VCC 2.4 V 0.3 VCC 0.8 V tRHDX 2.4 V tCLRH tRLC 0.8 V tAVRL tRLDV 2.4 V 0.8 V tRHA tRLR RD 0.8 V tRLBL 2.4 V tBHAV 2.4 V BUFC 0.8 V 37 MB89620R Series (7) Bus Write Timing (VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition Value Min. Max. Valid address → ALE ↓ time tAVLL AD7 to AD0, ALE, A15 to A08 1/4 tinst*1– 64 ns — µs ALE ↓ time → address invalid time tLLAX AD7 to AD0, ALE, A15 to A08 5 — ns Valid address → WR ↓ time tAVWL WR, ALE 1/4 tinst*1– 60 ns WR pulse width tWLWH WR Write data → WR ↑ time tDVWH AD7 to AD0, WR — µs inst 1 — µs inst 1 1/2 t * – 60 ns — µs 1/4 tinst*1– 40 ns — ns 1/4 tinst*1– 40 ns 1/2 t * – 20 ns WR ↑ → address invalid time tWHAX WR, A15 to A08 WR ↑ → data hold time tWHDX AD7 to AD0, WR WR ↑ → ALE ↑ time tWHLH WR, ALE WR ↓ → CLK ↑ time tWLCH CLK ↓ → WR ↑ time tCLWH ALE pulse width tLHLL ALE ALE ↓ → CLK ↑ time tLLCH ALE,CLK — — µs inst 1 — µs inst 1 1/4 t * – 40 ns — µs 0 — ns — µs — µs 1/4 t * – 40 ns WR, CLK 1/4 tinst*1– 35 ns*2 inst 1 2 1/4 t * – 30 ns* *1: For information on tinst, see “(4) Instruction Cycle.” *2: These characteristics are also applicable to the bus read timing. 2.4 V CLK 0.8 V tLHLL ALE tLLC tWHL 2.4 V 0.8 V tAVL AD 0.8 V tLLAX 2.4 V 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V 0.8 V tDVW A 2.4 V 0.8 V tWHD 2.4 V tCLWH 0.8 V tWLC tAVW tWHA tWLW WR 2.4 V 0.8 V 38 Unit Remarks MB89620R Series (8) Ready Input Timing (VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Symbol Parameter RDY valid → CLK ↑ time tYVCH CLK ↑ → RDY invalid time tCHYX Pin name RDY, CLK Condition — Value Unit Remarks Min. Max. 60 — ns * 0 — ns * *: These characteristics are also applicable to the read cycle. 2.4 V CLK 2.4 V ALE AD Data Address A WR tYVCH tCHYX RDY tYVCH tCHYX Note: The bus cycle is also extended in the read cycle in the same manner. 39 MB89620R Series (9) Serial I/O Timing (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Value Unit Remarks Min. Max. 2 tinst* — µs –200 200 ns tSCYC SCK1, SCK2 SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ tIVSH SI1, SCK1 SI2, SCK2 1/2 tinst* — µs SCK1 ↑ → valid SI1 hold time SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1 SCK2, SI2 1/2 tinst* — µs Serial clock “H” pulse width tSHSL SCK1, SCK2 1 tinst* — µs Serial clock “L” pulse width tSLSH SCK1, SCK2 1 tinst* — µs SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 0 200 ns Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ tIVSH SI1, SCK1 SI2, SCK2 1/2 tinst* — µs SCK1 ↑ → valid SI1 hold time SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1 SCK2, SI2 1/2 tinst* — µs Serial clock cycle time *: For information on tinst, see “(4) Instruction Cycle.” 40 Condition Internal shift clock mode External shift clock mode MB89620R Series • Internal Shift Clock Mode tSCYC SCK1 SCK2 2.4 V 0.8 V 0.8 V tSLOV SO1 SO2 2.4 V 0.8 V tIVSH SI1 SI2 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External Shift Clock Mode tSLSH tSHSL SCK1 SCK2 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SO1 SO2 2.4 V 0.8 V tIVSH SI1 SI2 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 41 MB89620R Series (10) Peripheral Input Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Parameter Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Peripheral input “H” pulse width 2 tILIH2 Peripheral input “L” pulse width 2 tIHIL2 Peripheral input “H” pulse width 2 tILIH2 Peripheral input “L” pulse width 2 tIHIL2 Condition PWC, EC, INT0 to INT3 — A/D mode ADST Sense mode Value Max. 2 tinst* — µs 2 tinst* — µs 32 tinst* — µs 32 tinst* — µs 8 tinst* — µs 8 tinst* — µs *: For information on tinst, see “(4) Instruction Cycle.” tIHIL1 PWC EC INT0 to INT3 tILIH1 0.2 VCC 0.2 VCC tIHIL2 tILIH2 0.8 VCC ADST 0.2 VCC 42 0.8 VCC 0.8 VCC 0.2 VCC Unit Min. 0.8 VCC Remarks MB89620R Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Resolution Condition — Total error — Linearity error Differential linearity error Zero transition voltage VOT Full-scale transition voltage VFST AVR=AVCC Unit Remarks Min. Typ. Max. — — 8 bit — — ±1.5 LSB — — ±1.0 LSB — — ±0.9 LSB AVSS –1.0LSB AVSS +0.5LSB AVSS +2.0LSB mV AVR–3.0LSB AVR–1.5LSB AVR mV — — 0.5 LSB — 44 tinst* — µs — 12 tinst* — µs — — 10 µA — Interchannel disparity A/D mode conversion time — Sense mode conversion time Analog port input current Value — IAIN AN0 to AN7 Analog input voltage — 0.0 — AVR V Reference voltage — 0.0 — AVCC V AVR = 5.0 V, when starting A/D conversion — 100 µA AVR = 5.0 V, when stopping A/D conversion — — 1 µA IR AVR Reference voltage supply current IRH *: For information on tinst, see “(4) Instruction Cycle” in “4 AC Characteristics.” 6. A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values 43 MB89620R Series Digital Digitaloutput output 1111 1111 1111 1111 1111 1111 • • 1110 1110 •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• Theoretical Theoreticalconversion conversionvalue value Actual Actualconversion conversionvalue value (1 (1LSB LSB××NN++VVOT OT)) 11LSB LSB== AVR AVR 256 256 Linearity Linearityerror error== Linearity Linearityerror error VVNT NT –– (1 (1LSB LSB××NN++VVOT OT)) 11LSB LSB VV((NN++11))TT––VVNT NT Differential ––11 Differentiallinearity linearityerror error== 11LSB LSB Total Totalerror error== VVNT NT –– (1 (1LSB LSB××NN++11LSB) LSB) 11LSB LSB 0000 0000 0010 0010 0000 0000 0001 0001 0000 0000 0000 0000 VVOT OT VVNT NT V V(N (N++I)T I)T VVFST FST Analog Analoginput input 7. Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. • Analog Input Equivalent Circiut Sample hold circuit . C =. 33 pF Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. . R =. 6 kΩ Close for 8 instruction cycles after activating A/D conversion. Analog channel selector • Error The smaller the | AVR – AVSS |, the greater the error would become relatively. 44 MB89620R Series ■ EXAMPLE CHARACTERISTICS (2) “H” Level Output Voltage (1) “L” Level Output Voltage VOL vs. IOL VOL (V) VCC = 3.0 V VCC = 4.0 V TA = +25°C 0.5 VCC = 5.0 V 0.4 VCC = 6.0 V 0.3 VCC – VOH (V) 1.0 0.9 VCC – VOH vs. IOH TA = +25°C VCC = 2.5 V 0.8 0.7 0.6 VCC = 3.0 V 0.5 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.4 0.2 0.3 0.2 0.1 0.1 0 1 2 3 4 5 6 7 8 0.0 0.0 9 10 IOL (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) TA = +25°C 4.0 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 0.0 2 3 4 5 6 –2.0 –2.5 –3.0 IOH (mA) TA = +25°C 4.5 4.0 1 –1.5 VIN vs. VCC VIN (V) 5.0 4.5 0 –1.0 (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN vs. VCC VIN (V) 5.0 –0.5 7 VCC (V) VIHS VILS 0 1 2 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 45 MB89620R Series (5) Power Supply Current (External Clock) ICC vs. VCC ICC (mA) 16 ICCS vs. VCC ICCS (mA) 5 TA = +25°C TA = +25°C 14 FC = 10 MHz 4 12 10 FC = 10 MHz 8 FC = 8 MHz 6 FC = 8 MHz 3 2 FC = 4 MHz 4 FC = 4 MHz 1 2 FC = 1 MHz 0 1 3 2 4 5 6 7 VCC (V) IA vs. AVCC IA (mA) 5.0 1 FC = 10 MHz TA = +25°C 160 3.5 140 3.0 120 2.5 100 2.0 80 1.5 60 1.0 40 0.5 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVCC (V) (6) Pull-up Resistance RPULL vs. VCC RPULL (kΩ) 1000 TA = +25°C 100 10 1 2 3 4 5 4 5 6 VCC (V) 0 2.0 6 7 VCC (V) IR vs. AVR TA = +25°C 180 4.0 0 2.0 3 2 IR (µA) 200 4.5 46 FC = 1 MHz 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVR (V) MB89620R Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 47 MB89620R Series Table 2 Mnemonic Transfer Instructions (48 instructions) ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Note: During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 48 MB89620R Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A (Continued) 49 MB89620R Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ # Operation 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 50 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A SUBC A XCH A, T XOR A AND A OR A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 rel CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 A A SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CMPW CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 7 F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A A DIVU SETI 9 4 8 RORC 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89620R Series ■ INSTRUCTION MAP 51 MB89620R Series ■ MASK OPTIONS Part number MB89623R MB89625R MB89626R MB89627R Specifying procedure Specify when ordering masking No. 52 Selectable per pin. (P50 to P57 must be set to without a pull-up resistor when an A/D converter is used.) MB89P625 MB89W625 MB89P627 MB89W627 Set with EPROM programmer MB89PV620 MB89T627R Setting not possible Can be set per pin. (P40 to P47 are available only for without a pull-up resistor.) Fixed to without pull-up resistor 1 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64 2 Power-on reset selection With power-on reset Without power-on reset Selectable Setting possible Fixed to with power-on reset 3 Oscillation stabilization time selection Crystal oscillator: 218/FC(s) Ceramic oscillator: 214/FC(s) Selectable Setting possible Crystal oscillator (218/FC(s)) 4 Reset pin output With reset output Without reset output Selectable Setting possible With reset output MB89620R Series ■ ORDERING INFORMATION Part number MB89623RP-SH MB89625RP-SH MB89626RP-SH MB89627RP-SH MB89P625P-SH MB89P627-SH MB89T627RP-SH Package Remarks 64-pin Plastic SH-DIP (DIP-64P-M01) MB89623RPFV MB89625RPFV 64-pin Plastic LQFP (FPT-64P-M03) Lead pitch: 0.5 mm MB89623RPF MB89625RPF MB89626RPF MB89627RPF MB89P625PF MB89P627PF MB89T623RPF MB89T625RPF MB89T627RPF 64-pin Plastic QFP (FPT-64P-M06) Lead pitch: 1.0 mm MB89623RPFM MB89625RPFM MB89626RPFM MB89627RPFM MB89P625PFM MB89P627PFM MB89T627RPFM 64-pin Plastic QFP (FPT-64P-M09) Lead pitch: 0.65 mm MB89W625C-SH MB89W627C-SH 64-pin Ceramic SH-DIP (DIP-64C-A06) MB89PV620CF 64-pin Ceramic MQFP (MQP-64C-P01) MB89PV620C-SH 64-pin Ceramic MDIP (MDP-64C-P02) 53 MB89620R Series ■ PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) +0.22 58.00 –0.55 +.008 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 5.65(.222)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN +0.50 1.00 –0 +.020 .039 –0 0.45±0.10 (.018±.004) 0.51(.020)MIN 15°MAX 19.05(.750) TYP 1.778±0.18 (.070±.007) 1.778(.070) MAX C 1994 FUJITSU LIMITED D64001S-3C-4 55.118(2.170)REF Dimensions in mm(inches). (Continued) 54 MB89620R Series (Continued) 64-pin Plastic LQFP (FPT-64P-M03) 12.00±0.20(.472±.008)SQ 10.00±0.10(.394±.004)SQ 48 33 49 32 0.08(.003) Details of "A" part INDEX +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 64 17 "A" LEAD No. 1 0.50±0.08 (.020±.003) 0~8° 16 0.18 .007 +0.08 –0.03 +.003 –.001 0.08(.003) M 0.145±0.055 (.006±.002) 0.50±0.20 (.020±.008) 0.45/0.75 (.018/.030) C 1998 FUJITSU LIMITED F64009S-3C-6 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) Dimensions in mm (inches). (Continued) 55 MB89620R Series (Continued) 64-pin Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) 20.00±0.20(.787±.008) 51 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 33 52 32 14.00±0.20 (.551±.008) 18.70±0.40 (.736±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 64 20 "A" LEAD No. 19 1 1.00(.0394) TYP 0.40±0.10 (.016±.004) 0.15±0.05(.006±.002) 0.20(.008) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.30±0.40(.878±.016) C 2000 FUJITSU LIMITED F64013S-3C-3 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX 0 10° 1.20±0.20 (.047±.008) Dimensions in mm (inches). (Continued) 56 MB89620R Series (Continued) 64-pin Plastic QFP (FPT-64P-M09) 14.00±0.20(.551±.008)SQ 48 33 12.00±0.10(.472±.004)SQ +0.20 1.50 –0.10 +.008 .059 –.004 49 (Mounting height) 32 9.75 (.384) REF 13.00 (.512) NOM 1 PIN INDEX 64 LEAD No. 17 1 0.65(.0256)TYP Details of "A" part 16 0.30±0.10 (.012±.004) "A" 0.13(.005) M +0.05 0.127 –0.02 0.10±0.10 (STAND OFF) (.004±.004) +.002 .005 –.001 0.10(.004) 0 C 2000 FUJITSU LIMITED F64018S-1C-3 10° 0.50±0.20 (.020±.008) Dimensions in mm (inches). (Continued) 57 MB89620R Series (Continued) 64-pin Ceramic SH-DIP (DIP-64C-A06) 56.90±0.56 (2.240±.022) 8.89(.350) DIA TYP R1.27(.050) REF 18.75±0.25 (.738±.010) INDEX AREA 1.27±0.25 (.050±.010) 5.84(.230)MAX 0.25±0.05 (.010±.004) 3.40±0.36 (.134±.014) 1.45(.057) MAX C 1994 FUJITSU LIMITED D64006SC-1-2 1.778±0.180 (.070±.007) 0.90±0.10 (.0355±.0040) +0.13 0.46 –0.08 +.005 .018 –.003 19.05±0.25 (.750±.010) 0°~9° 55.118(2.170)REF Dimensions in mm (inches). (Continued) 58 MB89620R Series (Continued) 64-pin Ceramic MQFP (MQP-64C-P01) 18.70(.736)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.00(.472)TYP +0.40 1.20 –0.20 .047 1.00±0.25 (.039±.010) +.016 –.008 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 1.27±0.13 (.050±.005) 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 0.30(.012)TYP 7.62(.300)TYP 0.40±0.10 (.016±.004) 18.00(.709) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 9.48(.373)TYP 11.68(.460)TYP 0.50(.020)TYP C 1994 FUJITSU LIMITED M64004SC-1-3 10.82(.426) 0.15±0.05 MAX (.006±.002) Dimensions in mm (inches). (Continued) 59 MB89620R Series (Continued) 64-pin Ceramic MDIP (MDP-64C-P02) 0°~9° 56.90±0.64 (2.240±.025) 15.24(.600) TYP 18.75±0.30 (.738±.012) 2.54±0.25 (.100±.010) 33.02(1.300)REF INDEX AREA 0.25±0.05 (.010±.002) 1.27±0.25 (.050±.010) 10.16(.400)MAX 1.778±0.25 (.070±.010) C 60 19.05±0.30 (.750±.012) 1994 FUJITSU LIMITED M64002SC-1-4 +0.13 0.46 –0.08 +.005 .018 –.003 55.12(2.170)REF 0.90±0.13 (.035±.005) 3.43±0.38 (.135±.015) Dimensions in mm (inches). MB89620R Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0012 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.