FUJITSU SEMICONDUCTOR DATA SHEET DS07-12531-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89630R Series MB89635R/T635R/636R/637R/T637R MB89P637/W637/PV630 ■ OUTLINE The MB89630R series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, a UART, timers, a PWM timer, a serial interface, an A/D converter, an external interrupt, and a watch prescaler. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • High-speed operating capability at low voltage • Minimum execution time: 0.4 µ[email protected] V, 0.8 µ[email protected] V • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Five types of timers 8-bit PWM timer: 2 channels (Also usable as a reload timer) 8-bit pulse-width count timer (Continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 21-bit timebase timer • UART CLK-synchronous/CLK-asynchronous data transfer capable (6, 7, and 8 bits) • Serial interface Switchable transfer direction to allows communication with various equipment. • 10-bit A/D converter Start by an external input capable (Continued) MB89630R Series (Continued) • External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Subclock mode Watch mode • Bus interface function With hold and ready function ■ PACKAGE 2 64-pin Plastic SH-DIP 64-pin Plastic QFP 64-pin Plastic QFP (DIP-64P-M01) (FPT-64P-M06) (FPT-64P-M09) 64-pin Ceramic SH-DIP 64-pin Ceramic MQFP 64-pin Ceramic MDIP (DIP-64C-A06) (MQP-64C-P01) (MDP-64C-P02) MB89630R Series ■ PRODUCT LINEUP Part number Item MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630 Classification Mass-produced products (mask ROM products) External ROM products One-time PROM product Piggyback/ evaluation EPROM product (for product evaluation and development) ROM size 16 K × 8 bits 24 K × 8 bits 32 K × 8 bits 32 K × 8 bits (internal (internal (internal (Internal PROM, to be 32 K × 8 bits mask ROM) mask ROM) mask ROM) Fixed to external ROM programmed with (external general-purpose ROM) EPROM programmer) RAM size 512 × 8 bits 768 × 8 bits 1024 × 8 bits 512 × 8 bits 1024 × 8 bits 1 K × 8 bits CPU functions The number of instructionns: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 to 6.4 µs/10 MHz, 61 µ[email protected] kHz 3.6 to 57.6 µs/10 MHz, 562.5 µ[email protected] kHz Ports Input ports: Output ports (N-ch open-drain): I/O ports (N-ch open-drain): Output ports (CMOS): I/O ports (CMOS): Total: 5 (All also serve as peripherals.) 8 (All also serve as peripherals.) 4 (All also serve as peripherals.) 8 (All also serve as bus control.) 28 (27 ports also serve as bus pins and peripherals.) 53 Clock timer 21 bits × 1 (in main clock)/15 bits × 1 (at 32.768 kHz) 8-bit PWM timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 2 channels 7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 2 channels 8-bit pulse width count timer 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs) 8-bit pulse width measurement operation (capable of continuous measurement, and measurement of “H” pulse width/ “L” pulse width/ from ↑ to ↑/from ↓ to ↓) 16-bit timer/ counter 16-bit timer operation (operating clock cycle: 0.4 µs) 16-bit event counter operation (rising edge/falling edge/both edge selectable) 8-bit serial I/O UART 10-bit A/D converter 8 bits LSB first/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) Capable of switching two I/O systems by software Transfer data length (6, 7, and 8 bits) Transfer rate (300 to 62500 bps. at 10 MHz osciliation) 10-bit resolution × 8 channels A/D conversion mode (conversion time: 13.2 µs) Sense mode (conversion time: 7.2 µs) Capable of continuous activation by an external activation or an internal timer (Continued) 3 MB89630R Series (Continued) Part number MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630 Item External interrupt input 4 independent channels (edge selection, interrupt vector, source flag). Rising edge/falling edge selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Standby mode Sleep mode, stop mode, watch mode, and subclock mode Process CMOS Operating voltage* 2.2 V to 6.0 V 2.7 V to 6.0 V MBM27C256A-20CZ MBM27C256A-20TV EPROM for use * : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) In the case of the MB89PV630, the voltage varies with the restrictions of the EPROM for use. ■ PACKAGE AND CORRESPONDING PRODUCTS MB89635R MB89T635R Package MB89636R MB89637R MB89T637R MB89P637 MB89W637 MB89PV630 DIP-64P-M01 × × FPT-64P-M06 × × ×* ×* ×* FPT-64P-M09 DIP-64C-A06 × × × MQP-64C-P01 × × × × MDP-64C-P02 × × × × : Available × ×: Not available * : To convert pin pitches, an adapter socket (manufacturer: Sun Hayato Co., Ltd.) is available. 64SD-64QF2-8L: For conversion from (DIP-64P-M01, DIP-64C-A06, or MDP-64C-P02) to FPT-64P-M09 Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Note: For more information about each package, see section “■ Package Dimensions.” 4 MB89630R Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: On the MB89P637/W637, the program area starts from address 8007H but on the MB89PV630 and MB89637R starts from 8000H. • On the MB89P637/W637, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV630/MB89637R, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P637/W637. • The stack area, etc., is set at the upper limit of the RAM. • The external area is used. 2. Current Consumption • In the case of the MB89PV630, add the current consumed by the EPROM which connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • A pull-up resistor cannot be set for P50 to P53 on the MB89P637 and MB89W637. • Options are fixed on the MB89PV630, MB89T635R, and MB89T637R. 4. Differences between the MB89630 and MB89630R Series • Memory access area There are no difference between the access area of MB89635/MB89635R, and that of MB89637/MB89637R. The access area of MB89636 is different from that of the MB89636R when using in external bus mode. Memory area Address MB89636 MB89636R 0000H to 007FH I/O area I/O area 0080H to 037FH RAM area RAM area 0380H to 047FH 0480H to 7FFFH Access prohibited External area 8000H to 9FFFH A000H to FFFFH External area Access prohibited ROM area ROM area 5 MB89630R Series • Other specifications Both MB89630 series and MB89630R is the same. • Electrical specifications/electrical characteristics Electrical specifications of the MB89630R series are the same as that of the MB89630 series. Electrical characteristics of both the series are much the same. ■ CORRESPONDENCE BETWEEN THE MB89630 AND MB89630R SERIES • The MB89630R series is the reduction version of the MB89630 series. • The the MB89630 and MB89630R series consist of the following products: MB89630 series MB89635 MB89T635 MB89636 MB89637 MB89630R series MB89635R MB89T635R MB89636R MB89637R 6 MB89T637 MB89T637R MB89P637 MB89W637 MB89PV630 MB89630R Series ■ PIN ASSIGNMENT (Top view) P31/UO1 P30/UCK1 P43/PTO1 P42/UI2 P41/UO2 P40/UCK2 P53/PTO2 P52 P51/BZ P50/ADST P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVCC AVR AVSS P74/EC P73/INT3 P72/INT2 P71/INT1/X0A* P70/INT0/X1A* RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 64 63 62 92 61 91 60 90 59 89 58 88 57 87 56 86 55 85 54 84 53 83 52 82 51 81 50 80 49 79 48 47 46 45 44 Each pin inside 43 the dashed line is 42 for MB89PV630 only. 41 40 39 38 37 36 35 34 33 (DIP-64P-M01) (DIP-64C-A06) (MDP-64C-P02) VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4 VCC P32/UI1 P33/SCK1 P34/SO1 P35/SI1 P36/PWC P37/WTO VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC P21/HAK P22/HRQ P23/RDY P24/CLK P25/WR P26/RD P27/ALE *: When the dual-clock system is selected. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P52 P53/PTO2 P40/UCK2 P41/UO2 P42/UI2 P43/PTO1 P30/UCK1 P31/UO1 VCC P32/UI1 P33/SCK1 P34/SO1 P35/SI1 P36/PWC P37/WTO VSS (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P71/INT1/X0A* P70/INT0/X1A* RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC P51/BZ P50/ADST P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVCC AVR AVSS P74/EC P73/INT3 P72/INT2 (FPT-64P-M09) *: When the dual-clock system is selected. 7 MB89630R Series 64 63 62 61 60 59 58 57 56 55 54 53 52 P53/PTO2 P40/UCK2 P41/UO2 P42/UI2 P43/PTO1 P30/UCK1 P31/UO1 VCC P32/UI1 P33/SCK1 P34/SO1 P35/SI1 P36/PWC (Top view) 1 2 3 4 5 6 85 77 7 86 76 8 87 75 9 88 74 10 89 73 11 90 72 12 91 71 13 92 70 14 93 69 15 16 17 18 19 Each pin inside the dashed line is for MB89PV630 only. 94 95 96 65 66 67 68 84 83 82 81 80 79 78 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P37/WTO VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK 20 21 22 23 24 25 26 27 28 29 30 31 32 P52 P51/BZ P50/ADST P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVCC AVR AVSS P74/EC P73/INT3 P72/INT2 P71/INT1/X0A* P70/INT0/X1A* (FPT-64P-M06) (MQP-64C-P01) *: When the dual-clock system is selected. • Pin assignment on package top (MB89PV630 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 65 N.C. 73 A2 81 N.C. 89 OE 66 VPP 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 VSS 88 A10 96 VCC N.C.: Internally connected. Do not use. 8 MB89630R Series ■ PIN DESCRIPTION Pin no. Pin name SH-DIP*1 MDIP*2 QFP2*3 QFP1*4 MQFP*5 30 22 23 X0 31 23 24 X1 28 20 21 MOD0 29 21 22 MOD1 27 19 20 RST 56 to 49 48 to 41 48 to 41 40 to 33 40 32 33 39 31 38 Circuit type Function A Main clock crystal oscillator pins D Operating mode selection pins Connect directly to VCC or VSS. C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 49 to 42 P00/AD0 to P07/AD7 F General-purpose I/O ports When an external bus is used, these ports function as the multiplex pins of the lower address output and the data I/O. 41 to 34 P10/A08 to P17/A157 F General-purpose I/O ports When an external bus is used, these ports function as an upper address output. P20/BUFC H General-purpose output port When an external bus is used, this port can also be used as a buffer control output by setting the BCTR. 32 P21/HAK H General-purpose output port When an external bus is used, this port can also be used as a hold acknowledge by setting the BCTR. 30 31 P22/HRQ F General-purpose output port When an external bus is used, this port can also be used as a hold request input by setting the BCTR. 37 29 30 P23/RDY F General-purpose output port When an external bus is used, this port functions as a ready input. 36 28 29 P24/CLK H General-purpose output port When an external bus is used, this port functions as a clock output. 35 27 28 P25/WR H General-purpose output port When an external bus is used, this port functions as a write signal output. 34 26 27 P26/RD H General-purpose output port When an external bus is used, this port functions as a read signal output. *1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M09 *4: FPT-64P-M06 *5: MQP-M64C-P01 (Continued) 9 MB89630R Series (Continued) Pin no. *1 SH-DIP MDIP*2 QFP2*3 QFP1*4 MQFP*5 Circuit type Function 33 25 26 P27/ALE H General-purpose output port When an external bus is used, this port functions as an address latch signal output. 2 58 59 P30/UCK1 G General-purpose I/O port Also serves as the clock I/O 1 for the UART. This port is a hysteresis input type. 1 57 58 P31/UO1 F General-purpose I/O port Also serves as the data output 1 for the UART. 63 55 56 P32/UI1 G General-purpose I/O port Also serves as the data input 1 for the UART. This port is a hysteresis input type. 62 54 55 P33/SCK1 G General-purpose I/O port Also serves as the data input for the 8-bit serial I/O. This port is a hysteresis input type. 61 53 54 P34/SO1 F General-purpose I/O port Also serves as the data output for the 8-bit serial I/O. 60 52 53 P35/SI1 G General-purpose I/O port Also serves as the data input for the 8-bit serial I/O. This port is a hysteresis input type. 59 51 52 P36/PWC G General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width counter. This port is a hysteresis input type. 58 50 51 P37/WTO F General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width counter. 6 62 63 P40/UCK2 G General-purpose I/O port Also serves as the clock I/O 2 for the UART. This port is a hysteresis input type. 5 61 62 P41/UO2 F General-purpose I/O port Also serves as the data output 2 for the UART. 4 60 61 P42/UI2 G General-purpose I/O port Also serves as the data input 2 for the UART. This port is a hysteresis input type. 3 59 60 P43/PTO1 F General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. 10 2 3 P50/ADST K General-purpose I/O port Also serves as an A/D converter external activation. This port is a hysteresis input type. *1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M09 10 Pin name *4: FPT-64P-M06 *5: MQP-M64C-P01 (Continued) MB89630R Series (Continued) Pin no. Circuit type Function QFP2 9 1 2 P51/BZ J General-purpose I/O port Also serves as a buzzer output. 8 64 1 P52 J General-purpose I/O port 7 63 64 P53/PTO2 J General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. 11 to 18 3 to 10 4 to 11 P60/AN0 to P67/AN7 I N-ch open-drain output ports Also serve as an A/D converter analog input. 26, 25 18, 17 19, 18 P70/INT0/X1A, P71/INT1/X0A 24, 23 16, 15 17, 16 P72/INT2, P73/INT3 E Input-only ports Also serve as an external interrupt input. These ports are a hysteresis input type. 22 14 15 P74/EC E General-purpose input port Also serves as the external clock input for the 16-bit timer/counter. This port is a hysteresis input type. 64 56 57 VCC — Power supply pin 32, 57 24,49 25, 50 VSS — Power supply (GND) pin 19 11 12 AVCC — A/D converter power supply pin 20 12 13 AVR — A/D converter reference voltage input pin 21 13 14 AVSS — A/D converter power supply pin Use this pin at the same voltage as VSS. *3 QFP1*4 MQFP*5 Pin name SH-DIP*1 MDIP*2 *1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M09 B/E Input-only ports These ports are a hysteresis input type. Also serve as an external interrupt input (at singleclock operation). Subclock crystal oscillator pins (at dual-clock operation) *4: FPT-64P-M06 *5: MQP-M64C-P01 11 MB89630R Series • External EPROM pins (MB89PV630 only) Pin no. 12 Pin name I/O Function MDIP MQFP 65 66 VPP O “H” level output pin 66 67 68 69 70 71 72 73 74 67 68 69 70 71 72 73 74 75 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 75 76 77 77 78 79 O1 O2 O3 I Data input pins 78 80 VSS O Power supply (GND) pin 79 80 81 82 83 82 83 84 85 86 O4 O5 O6 O7 O8 I Data input pins 84 87 CE O ROM chip enable pin Outputs “H” during standby. 85 88 A10 O Address output pin 86 89 OE O ROM output enable pin Outputs “L” at all times. 87 88 89 91 92 93 A11 A9 A8 O Address output pins 90 94 A13 O 91 95 A14 O 92 96 VCC O EPROM power supply pin — 65 76 81 90 N.C. — Internally connected pins Be sure to leave them open. MB89630R Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks • Crystal or ceramic oscillation type (main clock) External clock input selection versions of MB89PV630, MB89P637, MB89W637, MB89635R, MB89T635R, MB89636R, MB89637R, and MB89T637R At an oscillation feedback resistor of approximately 1 MΩ@5.0 V X1 X0 Standby control signal B • Crystal or ceramic oscillation type (subclock) MB89PV630, MB89P637, MB89W637, MB89635R, MB89636R, and MB89637R with dual-clock system At an oscillation feedback resistor of approximately 4.5 MΩ@5.0 V X1A X0A Standby control signal C • At an output pull-up resistor (P-ch) of approximately 50 kΩ@5.0 V • Hysteresis input R P-ch N-ch D E • Hysteresis input R • Pull-up resistor optional (except P70 and P71) F • CMOS output • CMOS input R P-ch P-ch N-ch • Pull-up resistor optional (except P22 and P23) (Continued) 13 MB89630R Series (Continued) Type Circuit Remarks G • CMOS output • Hysteresis input R P-ch P-ch N-ch • Pull-up resistor optional H • CMOS output P-ch N-ch I • Analog input N-ch Analog input J • CMOS input R P-ch N-ch • Pull-up resistor optional K • Hysteresis input R P-ch N-ch • Pull-up resistor optional 14 MB89630R Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (option selection) and wake-up from stop mode. 15 MB89630R Series ■ PROGRAMMING TO THE EPROM ON THE MB89P637 The MB89P637 is an OTPROM version of the MB89630 series. 1. Features • 32-Kbytes PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode is illustrated below. EPROM mode (Corresponding addresses on the EPROM programmer) Normal operating mode 0000H I/O 0080H 0100H Register RAM 0200H 0480H External area 0000H 8000H Option setting area Option setting area 0007H 8007H Program area (EPROM) 32 KB PROM 32 KB FFFFH 7FFFH 3. Programming to the EPPROM In EPROM mode, the MB89P637 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. However, the electronic signature mode cannot be used. When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the EPROM can be programmed as follows: 16 MB89630R Series • Programming procedure (1) Set the EPROM programmer to the MBM27C256A-20CZ and MBM27C256A-20TV. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (Note that addresses 8000H to FFFFH in the operating mode assign to 0000H to 7FFFH in EPROM mode). (3) Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “8. OTPROM Option Bit Map.”) (4) Program with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. Erasure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. 17 MB89630R Series 7. EPROM Programmer Socket Adapter Part No. MB89P637-SH MB89P637PF Package SH-DIP-64 QFP-64 ROM-64SD-28DP-8L ROM-64QF-28DP-8L Compatible socket adapter Sun Hayato Co., Ltd. Inquiry: Sun Hayato Co., Ltd.: TEL : (81)-3-3986-0403 FAX : (81)-3-5396-9106 8. OTPROM Option Bit Map Address Bit 7 Bit 3 Reset pin output 1: Yes 0: No P07 P06 P05 P04 P03 Pull-up Pull-up Pull-up Pull-up Pull-up 1: No 1: No 1: No 1: No 1: No 0: Yes 0: Yes 0: Yes 0: Yes 0: Yes P17 P16 P15 P14 P13 Pull-up Pull-up Pull-up Pull-up Pull-up 1: No 1: No 1: No 1: No 1: No 0: Yes 0: Yes 0: Yes 0: Yes 0: Yes P37 P36 P35 P34 P33 Pull-up Pull-up Pull-up Pull-up Pull-up 1: No 1: No 1: No 1: No 1: No 0: Yes 0: Yes 0: Yes 0: Yes 0: Yes Vacancy Vacancy Vacancy Vacancy P43 Pull-up Readable Readable Readable Readable 1: No and writable and writable and writable and writable 0: Yes Vacancy Vacancy Vacancy P74 P73 Pull-up Pull-up Readable Readable Readable 1: No 1: No and writable and writable and writable 0: Yes 0: Yes Bit 2 Power-on reset 1: Yes 0: No P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P72 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy 0000H 0001H 0002H 0003H 0004H 0005H 0006H Bit 6 Vacancy Bit 5 Single/dualclock system Readable Readable Readable 1: Dual clock and writable and writable and writable 0: Single clock Vacancy Vacancy Vacancy Vacancy Bit 1 Bit 0 Oscillation stabilization (/FCH) 11:218/FCH 01:217/FCH 10:214/FCH 00:24/FCH P01 P00 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes P11 P10 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes P31 P30 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes P41 P40 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes Vacancy Vacancy Readable Readable and writable and writable Vacancy Reserved bit Readable Readable Readable Readable Readable Readable Readable Readable and writable and writable and writable and writable and writable and writable and writable and writable Note: Each bit is set to ‘1’ as the initialized value. 18 Bit 4 Vacancy MB89630R Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20CZ, MBM27C256A-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX : (81)-3-5396-9106 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below. Address Single chip Corresponding addresses on the EPROM programmer 0000H I/O 0080H RAM 0480H Not available 8000H 0000H Not available Not available 8007H 0007H PROM 32 KB FFFFH EPROM 32 KB 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 19 MB89630R Series ■ BLOCK DIAGRAM Main clock oscillator X0A X1A Subclock oscillator (32.768 kHz) 21-bit timebase timer Clock controller CMOS I/O port Reset circuit (Watchdog timer) 8-bit PWC timer Watch prescaler P10 /A08 to P1 7/A1 5 8 CMOS I/O port P35/SI1 P34/SO1 P33/SCK1 P32/UI1 P31/UO1 P 3 0 / U C K1 UART P 4 0 / U C K2 P41/UO2 P42/UI2 MOD0 MOD1 External bus interface UART baud rate generator CMOS I/O port Port 2 P 4 3 / P T O1 N-ch open-drain I/O port CMOS output port 8-bit PWM timer P 5 3 / P T O2 P52 Port 5 P27 /ALE P26 /RD P25 /WR P24 /CLK P23 /RDY P22 /HRQ P21 /HAK P20 /BUFC 8-bit serial I/O Port 4 8 Port0 and port1 P00 /AD0 to P07 /AD7 P 3 7 / WT O P 3 6 / P WC Port 3 RST Internal data bus X0 X1 Buzzer output P51/BZ RAM 3 10-bit A/D converter F 2 M C- 8L CPU N-ch open-drain output port 8 Port 6 8 P50/ADST A V CC, A V SS , AVR P60/AN0 to P67/AN7 RO M External interrupt Other pins VCC × 2, VSS × 2 20 16-bit timer/counter 4 Port 7 Input port P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74/EC MB89630R Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89630R series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89630R series is structured as illustrated below. • Memory space 0000H MB89PV630 0000H 0080H 0200H Register Register 0200H 0200H 0380H 0480H 0480H RAM 1024 KB 0100H 0100H 0280H External area 8000H 0080H RAM 768 B Register 0200H 0000H I/O 0080H 0100H Register MB89636R I/O RAM 512 B RAM 1 KB 0100H 0000H I/O I/O 0080H MB89635R MB89T635R *3 0480H External area External area External area *2 8000H 8000H 8007H MB89637R MB89T637R MB89P637 MB89W637 8007H *3 *2 A000H External ROM 32 KB C000H ROM* 24 KB ROM*1 16 KB FFFFH ROM*1 32 KB 1 FFFFH FFFFH FFFFH *1: The ROM area is an external area depending on the mode. The internal ROM cannot be used on the MB89T635R and MB89T637R. *2: Addresses 8000H to 8006H for the MB89P637 and MB89W637 comprise an option area, do not use this area for the MB89PV630 and MB89637R. *3: The access is forbidden in the external bus mode. 21 MB89630R Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating the instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A16-bit register for index modification Extra pointer (EP): A16-bit pointer for indicating a memory address Stack pointer (SP): A16-bit register for indicating a stack area Program status (PS): A16-bit register for storing a register pointer, a condition code Initial value 16 bits FFFDH : Program counter PC A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status I-flag = 0, IL1, IL0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the program status register 15 PS 14 13 12 RP 10 9 8 Vacancy Vacancy Vacancy RP 22 11 7 6 5 4 3 2 1 0 H I IL1, IL0 N Z V C CCR MB89630R Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for conversion of actual addresses of the general-purpose register area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, IL0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise. V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow doesnot occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 23 MB89630R Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89653A (RAM 512 × 8 bits). The bank currently in use is indicated by the register bank pointer (RP). • Register bank configuraiton This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 24 MB89630R Series ■ I/O MAP Address Read/write Register name 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (W) BCTR External bus pin control register 06H Register description Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC System clock control register 09H (R/W) WDTE Watchdog timer control register 0AH (R/W) TBCR Timebase timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) CHG3 Port 3 switching register 0DH (R/W) PDR3 Port 3 data register 0EH (W) DDR3 Port 3 data direction register 0FH (R/W) PDR4 Port 4 data register 10H (W) DDR4 Port 4 data direction register 11H (R/W) BUZR Buzzer register 12H (R/W) PDR5 Port 5 data register 13H (R/W) PDR6 Port 6 data register 14H (R) PDR7 Port 7 data register 15H (R/W) PCR1 PWC pulse width control register 1 16H (R/W) PCR2 PWC pulse width control register 2 17H (R/W) RLBR PWC reload buffer register 18H (R/W) TMCR 16-bit timer control register 19H (R/W) TCHR 16-bit timer count register (H) 1AH (R/W) TCLR 16-bit timer count register (L) Vacancy 1BH 1CH (R/W) SMR1 Serial mode register 1DH (R/W) SDR1 Serial data register 1EH Vacancy 1FH Vacancy (Continued) 25 MB89630R Series (Continued) Address Read/write Register name 20H (R/W) ADC1 A/D converter control register 1 21H (R/W) ADC2 A/D converter control register 2 22H (R/W) ADDH A/D converter data register (H) 23H (R/W) ADDL A/D converter data register (L) 24H (R/W) EIC1 External interrupt control register 1 25H (R/W) EIC2 External interrupt control register 2 26H Vacancy 27H Vacancy 28H (R/W) CNTR1 PWM timer control register 1 29H (R/W) CNTR2 PWM timer control register 2 2AH (R/W) CNTR3 PWM timer control register 3 2BH (W) COMR1 PWM timer compare register 1 2CH (W) COMR2 PWM timer compare register 2 2DH (R/W) SMC UART serial mode control register 2EH (R/W) SRC UART serial rate control register 2FH (R/W) SSD UART serial status/data register 30H (R) (W) SIDR SODR 31H to 7BH UART serial input data control register UART serial output data control register Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level settingregister 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Note: Do not use vacancies. 26 Register description Vacancy MB89630R Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V * AVCC VSS – 0.3 VSS + 7.0 V * AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed “AVCC + 0.3 V”. VI VSS – 0.3 VCC + 0.3 V Except P50 to P53 VI2 VSS – 0.3 VSS + 7.0 V P50 to P53 VO VSS – 0.3 VCC + 0.3 V Except P50 to P53 VO2 VSS – 0.3 VSS + 7.0 V P50 to P53 “L” level maximum output current IOL 20 mA “L” level average output current IOLAV 4 mA “L” level total maximum output current ∑IOL 100 mA “L” level total average output current ∑IOLAV 40 mA “H” level maximum output current IOH –20 mA “H” level average output current IOHAV –4 mA “H” level total maximum output current ∑IOH –50 mA “H” level total average output current ∑IOHAV –20 mA Power consumption PD 500 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage A/D converter reference input voltage Input voltage Output voltage Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 27 MB89630R Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Value Symbol Parameter Min. Max 2.2* 6.0* Unit Remarks V Normal operation assurance range* MB89635R/637R VCC 2.7* 6.0* V Normal operation assurance range* MB89PV630/P637/ W637/T635R/T637R AVCC 1.5 6.0 V Retains the RAM state in stop mode A/D converter reference input voltage AVR 3.0 AVCC V Operating temperature TA –40 +85 °C Power supply voltage * : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” Figure 1 Operating Voltage vs. Main Clock Operating Frequency 6 Operating voltage (V) 5 Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range Operation assurance range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 4.0 2.0 0.8 0.4 Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89635R/636R/637R. Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 28 MB89630R Series WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 29 MB89630R Series 3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Condition Value Unit Remarks Min. Typ. Max. VIH1 P00 to P07, P10 to P17, P22, P23, P31, P34, P37, P41, P43, P51 to P53 0.7 VCC VCC + 0.3 V P51 to P53 with pull-up resistor VIH2 P51 to P53 0.7 VCC VSS + 6.0 V Without pull-up resistor VIHS RST, MOD0, MOD1, P30, P32, P33, P35, P36, P40, P42,P50, P72 to P74 0.8 VCC VCC + 0.3 V P50 with pull-up resistor VIHS2 P50, P70, P71 0.8 VCC VSS + 6.0 V Without pull-up resistor VIL P00 to P07, P10 to P17, P22, P23, P31, P34, P37, P41, P43 VSS − 0.3 0.3 VCC V VILS P30, P32, P33, P35, P36, P40, P42, P50 to P53, P70 to P74, RST, MOD0, MOD1 VSS − 0.3 0.2 VCC V VD P50 to P53 VSS − 0.3 VSS + 6.0 V “H” level input voltage “L” level input voltage Open-drain output pin application voltage Pin name “H” level output VOH voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOH = –2.0 mA P40 to P43 4.0 V “L” level output voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOL = 4.0 mA P40 to P43, P50 to P53, P60 to P67, RST 0.4 V P00 to P07, P10 to P17, P20 to P23, P30 to P37, P40 to P43, P50 to P53, 0.0 V < VI < VCC P70 to P74, MOD0, MOD1 ±5 µA VOL Input leakage current ILI (Hi-z output leakage current) Without pull-up resistor (Continued) 30 MB89630R Series (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Pull-up resistance Pin name Symbol RPULL Condition Max. 25 50 100 kΩ — 12 20 mA — 1.0 2 mA MB89635R/T635R/ 636R/637R/T637R/ PV630 — 1.5 2.5 mA MB89P637/W637 FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs — 3 7 mA FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs — 0.5 1.5 mA — 50 100 µA MB89635R/T635R/ 636R/637R/T637R/ PV630 — 500 700 µA MB89P637/W637 — 25 50 µA — 3 15 µA — — 1 µA FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs ICC2 FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs Sleep mode FCL = 32.768 kHz, Power supply current*1 ICCL VCC Remarks Typ. ICC1 ICCS2 Unit Min. P00 to P07, P10 to P17, P30 to P37, P40 to P43, VI = 0.0 V P50 to P53, P72 to P74 ICCS1 Value VCC = 3.0 V Subclock mode With pull-up resistor FCL = 32.768 kHz, ICCLS VCC = 3.0 V Subclock sleep mode FCL = 32.768 kHz, ICCT ICCH VCC = 3.0 V • Watch mode • Main clock stop mode at dualclock system TA = +25°C • Subclock stop mode • Main clock stop mode at singleclock system (Continued) 31 MB89630R Series (Continued) (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Pin name Symbol IA Power supply current*1 AVCC IAH Input capacitance CIN Value Condition Other than AVCC, AVSS, VCC, and VSS Unit Min. Typ. Max. FCH = 10 MHz, when A/D conversion operates. — 6 — mA FCH = 10 MHz, TA = +25°C, when A/D conversion in a stop. — — 1 µA f = 1 MHz — 10 — pF Remarks *1: The power supply current is measured at the external clock. In the case of the MB89PV630, the current consumed by the connected EPROM and ICE is not counted. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter RST “L” pulse width Symbol Condition tZLZH — Value Min. Max. 48 tHCYL — tZLZH RST 0.2 VCC 32 0.2 VCC Unit ns Remarks MB89630R Series (2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Power supply rising time tR Power supply cut-off time tOFF Condition Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Min. interval time for the next power-on reset — Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tOFF tR 2.0 V 0.2 V 0.2 V VCC 0.2 V (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol Pin name FCH Condition Value Unit Remarks Min. Typ. Max. X0, X1 1 — 10 MHz FCL X0A, X1A — 32.768 — kHz tHCYL X0, X1 100 — 1000 ns tLCYL X0A, X1A — 30.5 — µs PWH PWL X0 20 — — ns External clock PWLH PWLL X0A — 15.2 — µs External clock tCR tCF X0 — — 10 ns External clock — 33 MB89630R Series • Main clock timing condition tHCYL PWH PWL tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC • Main clock configurations When a crystal or ceramic reasonator is used X0 When an external clock is used X1 X0 X1 Open • Subclock timing condition tLCYL PWLH tCR PWLL tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC • Subclock configurations When a crystal or ceramic reasonator is used X0A X1A When an external clock is used X0A X1A Open 34 MB89630R Series (4) Instruction Cycle Symbol Parameter Instruction cycle (minimum execution time) Value (typical) Unit Remarks 4/FCH, 8/FCH, 16/FCH, 64/FCH µs (4/FCH) tinst = 0.4 µs, operating at FCH = 10 MHz 2/FCL µs tinst = 61.036 µs, operating at FCL = 32.768 kHz tinst Note: Operating at 10 MHz, the cycle varies with the set execution time. (5) Clock Output Timing (VCC = 5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Clock time tCYC CLK CLK ↑ → CLK ↓ tCHCL CLK Condition — Value Unit Min. Max. 1/2 tinst* — µs 1/4 tinst* – 70 ns 1/4 tinst* µs Remarks * : For information on tinst, see “(4) Instruction Cycle.” tCYC tCHCL 2.4 V 2.4 V CLK 0.8 V 35 MB89630R Series (6) Bus Read Timing (VCC = 5.0 V±10%, 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Valid address → RD ↓ time tAVRL RD pulse width tRLRH Pin name Value Condition Unit Max. RD, A15 to A08, AD7 to AD0 1/4 tinst*– 64 ns — µs RD 1/2 tinst*– 20 ns — µs 1/2 tinst* 200 µs No wait 1/2 tinst*– 80 ns 120 µs No wait 0 — µs 1/4 tinst*– 40 ns — µs 1/4 tinst*– 40 ns — µs 1/4 tinst*– 40 ns — µs 0 — ns –5 — µs 5 — µs Valid address → data read tAVDV time AD7 to AD0, A15 to A08 RD ↓ → data read time tRLDV RD, AD7 to AD0 RD ↑ → data hold time tRHDX AD7 to AD0, RD RD ↑ → ALE ↑ time tRHLH RD, ALE RD ↑ → address loss time tRHAX RD, A15 to A08 RD ↓ → CLK ↑ time tRLCH CLK ↓ → RD ↑ time tCLRH RD ↓ → BUFC ↓ time tRLBL RD, BUFC BUFC ↑ → valid address time tBHAV A15 to A08, AD7 to AD0, BUFC — RD, CLK * : For information on tinst, see “(4) Instruction Cycle.” 2.4 V CLK 0.8 V tRHLH ALE 0.8 V 2.4 V 0.7 VCC 0.7 VCC 2.4 V 0.8 V 0.3 VCC 0.3 VCC 0.8 V AD tRHDX tAVDV A 2.4 V 2.4V tCLRH tRLCH 0.8 V 0.8V tAVRL 2.4 V 0.8 V tRHAX tRLDV tRLRH RD 2.4 V 0.8 V tRLBL tBHAV 2.4 V BUFC 36 Remarks Min. 0.8 V MB89630R Series (7) Bus Write Timing (VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Valid address → ALE ↓ time tAVLL Pin name ALE ↓ time → address loss time tLLAX AD7 to AD0, ALE A15 to A08 Valid address → WR ↓ time tAVWL WR, ALE WR pulse width tWLWH WR Write data → WR ↑ time tDVWH AD7 to AD0, WR WR ↑ → address loss time tWHAX WR, A15 to A08 WR ↑ → data hold time tWHDX AD7 to AD0, WR WR ↑ → ALE ↑ time tWHLH WR, ALE WR ↓ → CLK ↑ time tWLCH CLK ↓ → WR ↑ time tCLWH ALE pulse width tLHLL ALE ALE ↓ → CLK ↑ time tLLCH ALE,CLK Condition Value Max. 1/4 tinst*1 – 64 ns*2 — µs 5 — ns 1/4 tinst*1 – 60 ns*2 — µs 1 2 — µs 1 2 1/2 tinst* – 60 ns* — µs 1/4 tinst*1 – 40 ns*2 — µs 1/4 tinst*1 – 40 ns*2 1/2 tinst* – 20 ns* — — µs 1 2 — µs 1 2 — µs — ns — µs — µs 1/4 tinst* – 40 ns* 1/4 tinst* – 40 ns* WR, CLK Unit Remarks Min. 0 1/4 tinst*1 – 35 ns*2 1 2 1/4 tinst* – 30 ns* *1: For information on tinst, see “(4) Instruction Cycle.” *2: This characteristics are also applicable to the bus read timing. 2.4 V CLK 0.8 V tLHLL ALE tWHLH 2.4 V 0.8 V 0.8 V tAVLL AD tLLCH tLLAX 2.4 V 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V 0.8 V tDVWH A 2.4 V tWHDX 2.4 V tCLWH tWLCH 0.8 V 0.8 V tWHAX tAVWL tWLWH WR 2.4 V 0.8V 37 MB89630R Series (8) Ready Input Timing (VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Symbol Parameter RDY valid → CLK ↑ time tYVCH CLK ↑ → RDY loss time tCHYX Pin name Condition RDY, CLK — Value 60 — ns * 0 — ns * 2.4 V 2.4 V ALE AD Address Data A WR tYVCH tCHYX RDY tYVCH Note: The bus cycle is also extended in the read cycle in the same manner. 38 Remarks Max. * : This characteristics are also applicable to the read cycle. CLK Unit Min. tCHYX MB89630R Series (9) Serial I/O Timing (VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition Value Unit Remarks Min. Max. 2 tinst* — µs –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs Serial clock cycle time tSCYC SCK1, UCK1, UCK2 SCK1 ↓ → SO1 time UCK1 ↓ → UO1 time UCK2 ↓ → UO2 time tSLOV SCK1, SO1 UCK1, UO1 UCK2, UO2 Valid SI1 → SCK1 ↑ Valid UI1 → UCK1 ↑ Valid UI2 → UCK2 ↑ tIVSH SI1, SCK1 UI1, UCK1 UI2, UCK2 SCK1 ↑ → valid SI1 hold time UCK1 ↑ → valid UI1 hold time tSHIX UCK2 ↑ → valid UI2 hold time SCK1, SI1 UCK1, UI1 UCK2, UI2 Serial clock “H” pulse width tSHSL SCK1, UCK1, UCK2 1 tinst* — µs Serial clock “L” pulse width tSLSH SCK1, UCK1, UCK2 1 tinst* — µs SCK1 ↓ → SO1 time UCK1 ↓ → UO1 time UCK2 ↓ → UO2 time tSLOV SCK1, SO1 UCK1, UO1 UCK2, UO2 0 200 ns Valid SI1 → SCK1 ↑ Valid UI1 → UCK1 ↑ Valid UI2 → UCK2 ↑ tIVSH SI1, SCK1 UI1, UCK1 UI2, UCK2 1/2 tinst* — µs SCK1 ↓ → valid SI1 hold time UCK1 ↓ → valid UI1 hold time tSHIX UCK2 ↓ → valid UI2 hold time SCK1, SI1 UCK1, UI1 UCK2, UI2 1/2 tinst* — µs Internal shift clock mode External shift clock mode * : For information on tinst, see “(4) Instruction Cycle.” 39 MB89630R Series • Internal shift clock mode tSCYC SCK1 UCK1 UCK2 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO1 UO1 UO2 0.8 V tIVSH SI1 UI1 UI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH SCK1 UCK1 UCK2 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SO1 UO1 UO2 2.4 V 0.8 V tIVSH SI1 UI1 UI 40 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB89630R Series (10) Peripheral Input Timing (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Peripheral input “H” pulse width 2 tILIH2 Peripheral input “L” pulse width 2 tIHIL2 Peripheral input “H” pulse width 3 tILIH3 Peripheral input “L” pulse width 3 tIHIL3 Pin name PWC, INT0 to INT3,EC ADST ADST Value Unit Remarks Min. Max. 2 tinst* — µs 2 tinst* — µs 8 inst 2 t * — µs A/D mode 28 tinst* — µs A/D mode 28 tinst* — µs Sense mode 8 inst — µs Sense mode 2 t * * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 PWC, EC, INT0 to INT3 tILIH1 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tIHIL2 (tIHIL3) tILIH2 (tILIH3) ADST 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 41 MB89630R Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 3.5 V to 6.0 V, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Resolution Linearity error — Differential linearity error — Total error Zero transition voltage VOT Full-scale transition voltage VFST Analog port input current — IAIN Analog input voltage Reference voltage supply current 42 IR Typ. Max. — — 10 bit — — ±2.0 LSB — — ±1.5 LSB — — ±3.0 LSB Remarks At AVCC = VCC AN0 to AN7 AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV — AN0 to AN7 — Reference voltage Unit Min. AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV Interchannel disparity A/D mode conversion time Value — — — 4 LSB — 13.2 — µs — — 10 µA 0.0 — AVR V 0.0 — AVCC V — 200 At 10 MHz oscillation µA AVR = 5.0 V MB89630R Series 6. A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise Total error Theoretical I/O characteristics 3FF 3FF VFST 3FE 3FE 3FD 1.5 LSB Digital output Digital output 3FD 004 003 Actual conversion value {1 LSB × N + 0.5 LSB} 004 VNT 003 VOT 002 Actual conversion value 002 1 LSB Theoretical value 001 001 0.5 LSB AVR AVSS 1 LSB = VFST – VOT 1022 AVR AVSS Analog input Analog input (V) Digital output N total error = VNT – {1 LSB × N + 0.5 LSB} 1 LSB (Continued) 43 MB89630R Series (Continued) Zero transition error Full-scale transition error 004 Theoretical value Actual conversion value 3FF Actual conversion value Digital output Digital output 003 002 3FE VFST (Actual measurement) 3FD Actual conversion value 001 Actual conversion value 3FC VOT (Actual measurement) AVR AVSS Analog input Analog input Differential linearity error Linearity error 3FF Theoretical value Actual conversion value 3FE N+1 {1 LSB × N + VOT} Actual conversion value VNT VFST (Actual measurement) 004 Digital output Digital output 3FD V(N + 1)T N N–1 003 VNT Actual conversion value Actual conversion value 002 Theoretical value 001 N–2 VOT (Actual measurement) AVR AVSS Analog input Digital output N linearity error = 44 VNT – {1 LSB × N + VOT} 1 LSB AVR AVSS Analog input Digital output N differential linearity error = V(N + 1)T – VNT 1 LSB –1 MB89630R Series 7. Notes on Using A/D Converter • Input impedance of the analog input pins The output impedance of the external circuit for the analog input must satisfy the followingconditions. If the output impedance of the external circuit is too high, an analog voltage sampling time might beinsufficient (sampling time = 6 µs at 10MHz oscillation.) Therefore, it is recommended to keep the output impedance of the external circuit below 10 kΩ . • Analog input circuit model Analog input C0 Converter RON1 RON2 C1 RON1: RON2: C0: C1: Approx. 1.5 kΩ Approx. 1.5 kΩ Approx. 60 pF Approx. 4 pF Note: The values mentioned here should be used as a guideline. • Error The smaller the | AVR–AVss |, the greater the error would become relatively. 45 MB89630R Series ■ CHARACTERISTICS EXAMPLE (2) “H” Level Output Voltage (1) “L” Level Output Voltage VOL vs. IOL VOL (V) VCC = 3.0 V VCC = 4.0 V TA = +25°C 0.5 VCC = 5.0 V VCC - VOH vs. IOH VCC - VOH (V) 1.0 0.9 TA = +25°C VCC = 2.5 V 0.8 0.7 0.4 VCC = 6.0 V 0.3 0.6 VCC = 3.0 V 0.5 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.4 0.2 0.3 0.2 0.1 0.1 0 1 2 3 4 5 6 7 8 9 0.0 0.0 10 IOL (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) –0.5 –1.0 VIN vs. VCC –2.5 TA = +25°C VIHS 4.0 4.5 3.5 4.0 3.0 3.5 2.5 3.0 2.0 2.5 1.5 2.0 1.0 1.5 0.5 1.0 0.0 VILS 0 0.5 0.0 1 2 3 4 5 6 7 VCC (V) –3.0 IOH (mA) VIN vs. VCC 4.5 TA = +25°C 0 –2.0 (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN (V) 5.0 VIN (V) 5.0 –1.5 1 2 3 4 5 6 7 VCC (V) VIHS: Threshold as the input voltage in hysteresis characteristics is set to “H” level VILS: Threshold as the input voltage in hysteresis characteristics is set to “L” level 46 MB89630R Series (5) Power Supply Current (External Clock) ICC1 vs. VCC, ICC2 vs. VCC ICC (mA) 16 ICCS (mA) 5.0 FCH = 10MHz TA = +25°C 14 Divide by 4 (ICC1) 4.0 3.5 10 3.0 8 2.5 Divide by 4 (ICCS1) 2.0 6 Divide by 8 1.5 Divide by 16 1.0 Divide by 64 (ICC2) 6.0 6.5 VCC (V) 0.5 4 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ICCL vs. VCC ICCL (µA) 200 TA = +25°C 180 0 2.0 40 35 120 30 100 25 80 20 60 15 40 10 20 5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) Divide by 16 Divide by 64 (ICCS2) 2.5 3.0 3.5 4.0 4.5 5.0 0 2.0 5.5 6.0 6.5 VCC (V) ICCLS vs. VCC TA = +25°C 45 140 2.5 Divide by 8 ICCLS (µA) 50 160 0 2.0 FCH = 10MHz TA = +25°C 4.5 12 0 2.0 ICCS1 vs. VCC, ICCS2 vs. VCC 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) (Continued) 47 MB89630R Series (Continued) I CCT vs. V CC I CCT (µA) 20 TA = +25°C 18 1.6 14 1.4 12 1.2 10 1.0 8 0.8 6 0.6 4 0.4 2 0.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 TA = +25°C 1.8 16 0 2.0 I CCH vs. V CC I CCH (µA) 2.0 6.5 V CC (V) 0 2.0 2.5 3.0 3.5 4.0 (6) Pull-up Resistance R PULL vs. V CC R PULL (kΩ) 1000 TA = +25°C 100 10 1 48 2 3 4 5 6 V CC (V) 4.5 5.0 5.5 6.0 6.5 V CC (V) MB89630R Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 49 MB89630R Series Table 2 Mnemonic Transfer Instructions (48 instructions) ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Note: During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 50 MB89630R Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A (Continued) 51 MB89630R Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ # Operation 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 52 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A SUBC A XCH A, T XOR A AND A OR A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 rel CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 A A SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CMPW CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 7 F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A A DIVU SETI 9 4 8 RORC 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89630R Series ■ INSTRUCTION MAP 53 MB89630R Series ■ MASK OPTIONS Part number MB89635R MB89636R MB89637R MB89P637 MB89W637 MB89PV630 MB89T635R MB89T637R Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible No. 1 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P43, P50 to P53, P72 to P74 2 Power-on reset selection With power-on reset Without power-on reset Selectable Setting possible Fixed to “with power-on reset” 3 Selection of the main clock oscillation stabilization time (at 10 MHz) Approx. 218/FCH (Approx. 26.2 ms) Approx. 217/FCH (Approx. 13.1 ms) Approx. 214/FCH (Approx. 1.6 ms) Approx. 24/FCH (Approx. 0 ms) FCH : Main clock frequency Selectable Setting possible Fixed to 218/FCH (Approx. 26.2 ms) 4 Reset pin output Reset output provided No reset output Selectable Setting possible Fixed to “with reset output” 5 Single/dual-clock system option Single clock Dual clock Selectable by Can be set per pin* pin Selectable * : Pull-up resistors cannot be set for P50 to P53. 54 Setting possible Fixed to “without pull-up resistor” MB89PV630-101 Single-clock system MB89T635R-101 Single-clock system MB89T637R-101 Single-clock system MB89PV630-102 Dual-clock systems MB89T635R-102 Dual-clock systems MB89T637R-102 Dual-clock systems MB89630R Series ■ ORDERING INFORMATION Part number MB89635RP-SH MB89T635RP-SH MB89636RP-SH MB89637RP-SH MB89P637P-SH MB89T637RP-SH Package Remarks 64-pin Plastic SH-DIP (DIP-64P-M01) MB89635RPF MB89T635RPF MB89636RPF MB89637RPF MB89P637PF MB89T637RPF 64-pin Plastic QFP (FPT-64P-M06) MB89635RPFM MB89636RPFM MB89637RPFM MB89T635PFM 64-pin Plastic QFP (FPT-64P-M09) MB89W637C-SH 64-pin Ceramic SH-DIP (DIP-64C-A06) MB89PV630CF 64-pin Ceramic MQFP (MQP-64C-P01) MB89PV630C-SH 64-pin Ceramic MDIP (MDP-64C-P02) 55 MB89630R Series ■ PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) +0.22 58.00 –0.55 +.008 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 5.65(.222)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN +0.50 1.00 –0 +.020 .039 –0 0.51(.020)MIN 0.45±0.10 (.018±.004) 15°MAX 19.05(.750) TYP 1.778±0.18 (.070±.007) 55.118(2.170)REF 1.778(.070) MAX C 1994 FUJITSU LIMITED D64001S-3C-4 64-pin Plastic QFP (FPT-64P-M06) Dimensions in mm (inches) 24.70±0.40(.972±.016) 3.35(.132)MAX (Mounting height) 20.00±0.20(.787±.008) 51 0.05(.002)MIN (STAND OFF) 33 52 32 14.00±0.20 (.551±.008) 18.70±0.40 (.736±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 64 20 "A" LEAD No. 1 19 1.00(.0394) TYP 0.40±0.10 (.016±.004) 0.15±0.05(.006±.002) 0.20(.008) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.00(.709)REF 22.30±0.40(.878±.016) C 56 1994 FUJITSU LIMITED F64013S-3C-2 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX 0 10° 1.20±0.20 (.047±.008) Dimensions in mm (inches) MB89630R Series 64-pin Plastic QFP (FPT-64P-M09) 48 14.00±0.20(.551±.008)SQ 33 12.00±0.10(.472±.004)SQ 49 +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 32 9.75 (.384) REF 13.00 (.512) NOM 1 PIN INDEX 64 LEAD No. 17 1 0.65(.0256)TYP Details of "A" part 16 0.30±0.10 (.012±.004) "A" 0.13(.005) M +0.05 0.127 –0.02 +.002 .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) 0 C 10° 0.50±0.20 (.020±.008) Dimensions in mm (inches) 1994 FUJITSU LIMITED F64018S-1C-2 64-pin Ceramic SH-DIP (DIP-64C-A06) 56.90±0.56 (2.240±.022) 8.89(.350) DIA TYP R1.27(.050) REF 18.75±0.25 (.738±.010) INDEX AREA 1.27±0.25 (.050±.010) 5.84(.230)MAX 0.25±0.05 (.010±.004) 3.40±0.36 (.134±.014) 1.45(.057) MAX C 1994 FUJITSU LIMITED D64006SC-1-2 1.778±0.180 (.070±.007) 0.90±0.10 (.0355±.0040) +0.13 0.46 –0.08 +.005 .018 –.003 19.05±0.25 (.750±.010) 0°~9° 55.118(2.170)REF Dimensions in mm (inches) 57 MB89630R Series 64-pin Ceramic MQFP (MQP-64C-P01) INDEX AREA 18.70(.736)TYP 12.00(.472)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) +0.40 1.20 –0.20 +.016 .047 –.008 1.00±0.25 (.039±.010) 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 22.30±0.33 (.878±.013) 0.30(.012) TYP 24.70(.972) TYP 1.27±0.13 (.050±.005) 0.30(.012)TYP 7.62(.300)TYP 0.40±0.10 (.016±.004) 18.00(.709) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 9.48(.373)TYP 11.68(.460)TYP 10.82(.426) 0.15±0.05 MAX (.006±.002) 0.50(.020)TYP C Dimensions in mm (inches) 1994 FUJITSU LIMITED M64004SC-1-3 64-pin Ceramic MDIP (MDP-64C-P02) 0°~9° 56.90±0.64 (2.240±.025) 15.24(.600) TYP 18.75±0.30 (.738±.012) 2.54±0.25 (.100±.010) 33.02(1.300)REF INDEX AREA 0.25±0.05 (.010±.002) 1.27±0.25 (.050±.010) 10.16(.400)MAX 1.778±0.25 (.070±.010) C 58 19.05±0.30 (.750±.012) 1994 FUJITSU LIMITED M64002SC-1-4 +0.13 0.46 –0.08 +.005 .018 –.003 55.12(2.170)REF 0.90±0.13 (.035±.005) 3.43±0.38 (.135±.015) Dimensions in mm (inches) MB89630R Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ All Rights Reserved. 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If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9609 FUJITSU LIMITED Printed in Japan 59