FUJITSU SEMICONDUCTOR DATA SHEET DS07-12537-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89670R/670AR Series MB89673R/673AR/675R/675AR MB89677AR/P677A/PV670A ■ OUTLINE The MB89670R/670AR series has been developed as a line of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC*-8L family CPU core which can operate at low voltage but at high speed, the microcontrollers contain pheripheral functions such as timers, a serial interface, a 10-bit A/D converter, a UART, an 8/16-bit up/down counter/timer, and an external interrupt. The MB89670R/670AR series is applicable to a wide range of applications from consumer appliances to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • High-speed processing at low voltage • Minimum execution time: 0.4 µ[email protected] V, 0.8 µ[email protected] V, 2.0 µ[email protected] V • I/O ports: max. 69 channels (Continued) ■ PACKAGE 80-pin Plastic QFP (FPT-80P-M06) (FPT-80P-M06) 80-pin Plastic LQFP (FPT-80P-M11) (FPT-80P-M11) 80-pin Ceramic MQFP (MQP-80C-P01) (MQP-80C-P01) MB89670R/670AR Series (Continued) • Timers: 9 channels (MB89675AR/677AR/P677A/PV670A: 12 channels) 8-bit PWM timer: 3 channels (MB89675AR/677AR/P677A/PV670A: 6 channels) (also usable as a reload timer or 8-bit PWM timer) 16-bit timer/counter 21-bit timebase timer 8/16-bit timer (8 bits × 2 channels or 16 bits) 8/16-bit up/down counter/timer (8 bits × 2 channels or 16 bits) • 2-channel serial interfaces 8-bit synchronized serial: 1 channel (Switchable transfer direction allows communication with various equipment.) UART: 1 channel (internal full-duplex double buffer) • External interrupts: 8 channels Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Buzzer output • 10-bit A/D converter Input: 8 channels • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) • Bus interface function Including hold and ready functions 2 MB89670R/670AR Series ■ PRODUCT LINEUP Part number MB89673R*1 MB89673AR MB89675R*1 MB89675AR MB89677AR MB89P677A MB89PV670A Item Classification One-time PROM product (for development) Mass-produced products (mask ROM products) ROM size 8 K × 8 bits (internal mask ROM) 16 K × 8 bits (internal mask ROM) RAM size 384 × 8 bits 512 × 8 bits 32 K × 8 bits (internal mask ROM) Piggyback/ evaluation product (for development) 48 K × 8 bits (external ROM) 1 K × 8 bits CPU functions The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs@10 MHz to 6.4 µs@10 MHz 3.6 µs@10 MHz to 57.6 µs@10 MHz Ports Output ports (N-channel open-drain): Output ports (CMOS): I/O ports (N-channel open-drain): I/O ports (CMOS): Input ports: Total: 14 (12 also serve as peripherals.) 8 (All also serve as peripherals.) 7 (All also serve as peripherals.) 32 (All also serve as peripherals.) 8 (All also serve as peripherals.) 69 Option Specify when ordering masking Timebase timer Set with EPROM programmer 21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms@10 MHz) 8/16-bit up/down counter/timer 8 bits × 2 channels or 16 bits × 1 channel Timer operation Up/down counter operation Phase difference counting (double mode, quadruple mode) 16-bit timer/counter 16-bit timer operation 16-bit event counter operation (edge selectable) 8/16-bit timer/counter 8 bits × 2 channels or 16 bits × 1 channel Reload timer operation (toggled output capable) Event counter operation 8-bit PWM timer 1, 2 Setting not possible 8 bits × 2 channels reload timer operation (toggled output capable) 8 bits × 2 channels PWM operation (four frequencies fixed) 8 bits × 1 channel PPG operation (variable frequency) Capable of output switching between 2 channels in any mode 8-bit PWM timer 3, 4, 5, 6 8-bit reload timer operation (toggled output capable) 8-bit PWM operation (four frequencies fixed) Capable of output switching between 2 channels in any mode 8-bit serial I/O 8 bits LSB first/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) (Continued) 3 MB89670R/670AR Series (Continued) Part number MB89673R*1 MB89673AR MB89675R*1 MB89675AR MB89677AR MB89P677A MB89PV670A Item UART Variable data length (7 or 8 bits) On-chip baud rate generator Error detection function On-chip full-duplex double buffer NRZ transfer format CLK synchrnous/asynchronous data transfer capable 10-bit A/D converter 10 bits × 8 channels External interrupt 8 channels (Rising edge/falling edge) Power supply voltage*2 2.2 V to 6.0 V EPROM for use 2.7 V to 6.0 V MBM27C512 -20TV — *1: 8-bit PWM timer 4, 5, and 6 are not provided for the MB89673R/MB89675R. *2: The minimum operating voltage varies with the operating frequency, the function, and the connected ICE. ■ PACKAGE AND CORRESPONDING PRODUCTS MB89673R MB89675R Package MB89673AR MB89675AR MB89677AR MB89P677A MB89PV670A FPT-80P-M06 × FPT-80P-M11 ×* MQP-80C-P01 : Available × × × × : Not available * : Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available 80QF-80QF2-8L-UP + (MQP-80C-P01 or FPT-80P-M06) → for conversion to FPT-80P-M11 80QF-80QF2-8L-DWN Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Note: For more information about each package, see section “■ Package Dimensions.” 4 MB89670R/670AR Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, make sure of its differences from the product that will actually be used. Take particular care on the following points: • On the MB89P677A, the program area starts from address 8007H, while on the MB89677AR and MB89PV670A starts from 8000H. (On the MB89P677A, the option setting data can be read by reading the addresses “8000H” to “8006H”, while on the MB89677AR and MB89PV670A, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P677A.) • The stack area, etc., is set at the upper limit of the RAM. • The external area is used. 2. Current Consumption • In the case of the MB89PV670A, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following point: • Options are fixed on the MB89PV670A. 4. Differences between the MB89670/670A and MB89670R/670AR Series • Memory access area Memory access area of both the MB89677A and MB89677AR is the same. The access are of the MB89673 is different from that of the MB89673R and MB89673AR respectively in the external bus mode. See below. Memory area Address MB89673 MB89673R/673AR 0000H to 007FH I/O area I/O area 0080H to 01FFH RAM area RAM area 0200H to 027FH 0280H to BFFFH Access prohibited External area C000H to DFFFH E000H to FFFFH External area Access prohibited ROM area ROM area 5 MB89670R/670AR Series • Electrical specifications/characteristics Electrical specifications/characteristics of the MB89673R/673AR/677AR are the same with that of the MB89670/670A series. • The other specifications Both the MB89673R/673AR/677AR and the MB89670/670A series are the same. ■ CORRESPONDENCE BETWEEN THE MB89670/670A SERIES AND MB89670R/670AR SERIES • The MB89670R/670AR series is the reduction version of the MB89670/670A series. • The MB89670/670A and MB89670R/670AR sereis consist of the following products: MB89670/ 670A series MB89670R/ 670AR series MB89673 — — — MB89677A MB89P677A MB89PV670A MB89673R MB89673AR MB89675R MB89675AR MB89677AR • Differences between the MB89670A/670AR series and MB89670/670R series 8-bit PWM timer 4, 5, and 6 is not provided for the MB89670/670R series. See the table below for the provided 8-bit PWM timer and the corresponding pin for the MB89670A/670AR series and MB89670/670R series. Function 6 Pin name for MB89670A/670AR series Pin name for MB89670/670R series 8-bit PWM timer 1 P40/PWM00 P40/PWM00, P41/PWM01 8-bit PWM timer 2 P42/PWM10/BZ2 P42/PWM10/BZ2, P43/PWM11 8-bit PWM timer 3 P30/PWM20 P30/PWM20, P31/PWM21 8-bit PWM timer 4 P31/PWM21 — 8-bit PWM timer 5 P41/PWM01 — 8-bit PWM timer 6 P43/PWM11 — MB89670R/670AR Series ■ PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P74/SCK P75/SO P76/SI AVSS AVR AVCC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/INT0/ADST P61/INT1 P62/INT2 P63/INT3 P64/INT4 P65/INT5 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P66/INT6 P67/INT7 P84 P85 VSS P40/PWM00 P41/PWM01 VCC P42/PWM10/BZ2 P43/PWM11 P44/TCI P45/TCO1 P46/TCO2 P47/EC P30/PWM20 P31/PWM21 P32/UDZ1 P33/UDB1 P34/UDA1 P35/UDZ2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P21/HAK P20/BUFC P17/A15 P16/A14 P15/A13 P14/A12 P13/A11 P12/A10 P11/A09 P10/A08 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P37/UDA2 P36/UDB2 P73/UI P72/UO P71/UCK P70/BZ1 P83 P82 P81 P80 MOD0 MOD1 X0 X1 VSS RST P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ (FPT-80P-M11) 7 MB89670R/670AR Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P76/SI AVSS AVR AVCC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/INT0/ADST P61/INT1 P62/INT2 P63/INT3 (Top view) 100 99 98 97 96 95 94 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 93 92 91 90 89 88 87 86 85 110 111 112 81 82 83 84 101 102 103 104 105 106 107 108 109 Each pin inside the dashed line is for the MB89PV670A only. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P64/INT4 P65/INT5 P66/INT6 P67/INT7 P84 P85 VSS P40/PWM00 P41/PWM01 VCC P42/PWM10/BZ2 P43/PWM11 P44/TCI P45/TCO1 P46/TCO2 P47/EC P30/PWM20 P31/PWM21 P32/UDZ1 P33/UDB1 P34/UDA1 P35/UDZ2 P36/UDB2 P37/UDA2 P17/A15 P16/A14 P15/A13 P14/A12 P13/A11 P12/A10 P11/A09 P10/A08 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P75/SO P74/SCK P73/UI P72/UO P71/UCK P70/BZ1 P83 P82 P81 P80 MOD0 MOD1 X0 X1 VSS RST P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC (FPT-80P-M06) (MQP-80C-P01) • Pin assignment on package top (MB89PV670A only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 A2 97 N.C. 105 OE/VPP 82 A15 90 A1 98 O4 106 N.C. 83 A12 91 A0 99 O5 107 A11 84 A7 92 N.C. 100 O6 108 A9 85 A6 93 O1 101 O7 109 A8 86 A5 94 O2 102 O8 110 A13 87 A4 95 O3 103 CE 111 A14 88 A3 96 VSS 104 A10 112 VCC N.C.: Internally connected. Do not use. 8 MB89670R/670AR Series ■ PIN DESCRIPTION Pin no. Pin name LQFP*1 QFP*2 MQFP*3 11 13 X0 12 14 X1 Circuit type Function A Clock oscillator pins B Operating mode selection pins Connect directly to VCC or VSS. 9 11 MOD0 10 12 MOD1 14 16 RST C Reset I/O pin This pin is of a N-ch open-drain output type with pull-up resistor and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 38 to 31 40 to 33 P00/AD0 to P07/AD7 D General-purpose I/O ports When an external bus is used, these ports function as multiplex pins of lower address output and data I/O. 30 to 23 32 to 25 P10/A08 to P17/A15 D General-purpose I/O ports When an external bus is used, these ports function as upper address output pins. 22 24 P20/BUFC F General-purpose output port When an external bus is used, this port can also be used as a buffer control output by setting the BCTR. 21 23 P21/HAK F General-purpose output port When an external bus is used, this port can also be used as a hold acknowledge output by setting the BCTR. 20 22 P22/HRQ D General-purpose output port When an external bus is used, this port can also be used as a hold request input by setting the BCTR. 19 21 P23/RDY D General-purpose output port When an external bus is used, this port functions as a ready input. 18 20 P24/CLK F General-purpose output port When an external bus is used, this port functions as a clock output. 17 19 P25/WR F General-purpose output port When an external bus is used, this port functions as a write signal output. 16 18 P26/RD F General-purpose output port When an external bus is used, this port functions as a read signal output. 15 17 P27/ALE F General-purpose output port When an external bus is used, this port functions as an address latch signal output. *1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 (Continued) 9 MB89670R/670AR Series Pin no. Circuit type Function QFP*2 MQFP*3 46 48 P30/PWM20 D General-purpose I/O port Also serves as the PWM20 output for the 8-bit PWM timer. 45 47 P31/PWM21 D General-purpose I/O port Also serves as the PWM21 output for the 8-bit PWM timer. 44 46 P32/UDZ1 E General-purpose I/O port Also serves as the Z-phase input for the 8/16-bit up/down counter/timer. 43 45 P33/UDB1 E General-purpose I/O port Also serves as the B-phase input for the 8/16-bit up/down counter/timer. 42 44 P34/UDA1 E General-purpose I/O ports Also serves as the A-phase input for the 8/16-bit up/down counter/timer. 41 43 P35/UDZ2 E General-purpose I/O port Also serves as the Z-phase input for the 8/16-bit up/down counter/timer. 40 42 P36/UDB2 E General-purpose I/O port Also serves as the B-phase input for the 8/16-bit up/down counter/timer. 39 41 P37/UDA2 E General-purpose I/O port Also serves as the A-phase input for the 8/16-bit up/down counter/timer. 55 57 P40/PWM00 D General-purpose I/O port Also serves as the PWM00 output for the 8-bit PWM timer. 54 56 P41/PWM01 D General-purpose I/O port Also serves as the PWM01 output for the 8-bit PWM timer. 52 54 P42/PWM10/ BZ2 D General-purpose I/O port Also serves as the PWM10 and the BZ2 output for the 8-bit PWM timer. 51 53 P43/PWM11 D General-purpose I/O port Also serves as the PWM11 output for the 8-bit PWM timer. 50 52 P44/TCI E General-purpose I/O port Also serves as the TCI input for the 8/16-bit timer/counter. 49 51 P45/TCO1 D General-purpose I/O port Also serves as the TCO1 output for the 8/16-bit timer/counter. 48 50 P46/TCO2 D General-purpose I/O port Also serves as the TCO2 output for the 8/16-bit timer/counter. *1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 10 Pin name LQFP*1 (Continued) MB89670R/670AR Series (Continued) Pin no. LQFP*1 QFP*2 MQFP*3 47 49 74 to 67 76 to 69 66 68 65 to 59 67 to 61 4 Pin name Circuit type Function P47/EC E General-purpose I/O port Also serves as the input for the16-bit timer/counter. The EC input is of a hysteresis input type. P50/AN0 to P57/AN7 I N-ch open-drain output ports Also serve as the analog inputs for the 10-bit A/D converter. P60/INT0/ ADST J General-purpose input port The software pull-up resistor is provided. Also serves as an external interrupt input (INT0) and an 10-bit A/D converter external start-up. This port is of a hysteresis input type. P61/INT1 to P67/INT7 J General-purpose input ports A software pull-up resistor is provided. Also serve as external interrupt inputs (INT1 to INT7). These ports are of a hysteresis input type. 6 P70/BZ1 G N-ch open-drain I/O port Also serves as a buzzer output. 3 5 P71/UCK K N-ch open-drain I/O port Also serves as a UART clock I/O (UCK), switchable to CMOS. 2 4 P72/UO K N-ch open-drain I/O port Also serves as a UART data output (UO), switchable to CMOS. 1 3 P73/UI G N-ch open-drain I/O port Also serves as a UART data input (UI). 80 2 P74/SCK K N-ch open-drain I/O port Also serves as the clock I/O (SCK) for the 8-bit serial I/O, switchable to CMOS. 79 1 P75/SO K N-ch open-drain I/O port Also serves as the data output (SO) for the 8-bit serial I/O, switchable to CMOS. 78 80 P76/SI G N-ch open-drain I/O port Also serves as the data input (SI) for the 8-bit serial I/O. 8 to 5, 57, 58 10 to 7, 59, 60 P80 to P83, P85, P84 H N-ch open-drain output ports 53 55 VCC — Power supply pin 13, 56 15, 58 VSS — Power supply (GND) pin 75 77 AVCC — A/D converter power supply pin Use this pin at the same voltage as VCC. 76 78 AVR — A/D converter reference voltage input pin 77 79 AVSS — A/D converter power supply pin Use this pin at the same voltage as VSS. *1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 11 MB89670R/670AR Series • External EPROM pins (MB89PV670A only) Pin no. 12 Pin name I/O Function 82 83 84 85 86 87 88 89 90 91 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 93 94 95 O1 O2 O3 I Data input pins 96 VSS O Power supply (GND) pin 98 99 100 101 102 O4 O5 O6 O7 O8 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby. 104 A10 O Address output pin 105 OE/VPP O ROM output enable pin Outputs “L” at all times. 107 108 109 A11 A9 A8 O Address output pins 110 A13 O 111 A14 O 112 VCC O 81 92 97 106 N.C. — Internally connected pins Be sure to leave them open. MB89670R/670AR Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks • Crystal or ceramic oscillation type • Oscillation feedback resistor of approximately 1 MΩ at 5.0 V X1 X0 Standby control signal B C • Output pull-up resistor (P-ch) of approximately 50 kΩ at 5.0 V • Hysteresis input R P-ch N-ch D • CMOS output • CMOS inout R P-ch P-ch N-ch • Pull-up resistor optional (except P22 and P23) E • CMOS output • CMOS input • The peripheral is of a hysteresis input type. R P-ch P-ch N-ch Peripheral Port • Pull-up resistor optional (Continued) 13 MB89670R/670AR Series (Continued) Type Circuit Remarks F • CMOS output P-ch N-ch G • N-ch open-drain output • Hysteresis input R P-ch P-ch N-ch • Pull-up resistor optional H • N-ch open-drain output N-ch I • N-ch open-drain output • Analog input P-ch N-ch Analog input J • Hysteresis input • With software pull-up resistor R P-ch Pull-up control signal K • CMOS output • Hysteresis input R P-ch P-ch N-ch • Pull-up resistor optional 14 MB89670R/670AR Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 15 MB89670R/670AR Series ■ PROGRAMMING TO THE EPROM ON THE MB89P677A The MB89P677A is an OTPROM version of the MB89670R/670AR series. 1. Features • 32-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in the EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in the EPROM mode is diagrammed below. Address Single chip 0000H EPROM mode (Corresponding addresses on the EPROM programmer) I/O 0080H RAM 0480H External area 8000H 0000H Option area Not available 8007H 0007H PROM 32 KB FFFFH 16 EPROM 32 KB 7FFFH MB89670R/670AR Series 3. Programming to the EPROM In EPROM mode, the MB89P677A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as a single chip assign to 0007H to 7FFFH in the EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “7. Setting OTPROM Options.”) (3) Program with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield Due to the nature of the blanked OTPROM microcomputer, bit programming test can’t be conducted as Fujitsu’s shipping test. Therefore a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Part number Package Compatible socket adapter Sun Hayato Co., Ltd. MB89P677APF MB89P677PFM QFP-80 QFP-80 ROM-80QF-28DP-8L2 ROM-80QF2-28DP-8L Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. 17 MB89670R/670AR Series 7. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Address Bit 7 Bit 6 Bit 5 Bit 4 Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable 0001H P17 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes 0002H P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes 0003H P47 Pull-up 1: No 0: Yes 0000H 0004H 0005H 0006H Bit 3 Bit 1 Bit 0 Reset pin output 1: Yes 0: No Power-on reset 1: Yes 0: No Oscillation stabilization time 00: 24/FC 10: 217/FC 01: 214/FC 11: 218/FC P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable Vacancy Vacancy Vacancy Readable Readable Readable P74 Pull-up 1: No 0: Yes P73 Pull-up 1: No 0: Yes P72 Pull-up 1: No 0: Yes P71 Pull-up 1: No 0: Yes P70 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable P04 to P07 Pull-up 1: No 0: Yes P00 to P03 Pull-up 1: No 0: Yes P76 Pull-up 1: No 0: Yes P75 Pull-up 1: No 0: Yes Notes: • Each bit is set to “1” as the initialized value. • Do not write “0” to the vacant bit. The read value of the vacant bit is “1”, unless “0” is written to it. 18 Bit 2 MB89670R/670AR Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32(Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 3. Memory Space Memory space in each mode is diagrammed below. Address Single chip EPROM mode (Corresponding address on the EPROM programmer) 0000H 0000H I/O 0080H Not available RAM 0480H External area 4000H 8000H 4000H 8000H * 8007H * 8007H PROM 48 KB FFFFH EPROM 48 KB FFFFH *: Note: For the MB89P677A, this area is an option setting area. 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 4000H to FFFFH. (3) Program to 4000H to FFFFH with the EPROM programmer. 19 MB89670R/670AR Series ■ BLOCK DIAGRAM 1. Block Diagram of MB89673R/89675R X0 X1 Timebase timer Oscillator Clock controller CMOS I/O port 16-bit up/down counter/timer Reset circuit (WDT) Internal data bus RST RAM 8-bit up/down counter/timer P37/UDA2 P36/UDB2 P35/UDZ2 8-bit up/down counter/timer P34/UDA1 P33/UDB1 P32/UDZ1 F2MC-8L CPU 16-bit timer/counter P47/EC ROM 8/16-bit timer CMOS I/O port 8 P00/AD0 to P07/AD7 16 8 P46/TCO2 8-bit timer P45/TCO1 P44/TCI 2-channel 8-bit PWM timer P10/A08 to P17/A15 MOD0 MOD1 External bus interface 8-bit timer #2 8-bit timer #1 P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC P31/PWM21 P30/PWM20 CMOS output port N-ch open-drain output port P80 to P85 8 8-bit serial I/O P76/SI P75/SO P74/SCK UART P73/UI P72/UO P71/UCK Buzzer output P70/BZ1 8 10-bit A/D converter AVR AVCC AVSS Input port P60/INT0/ADST to P67/INT7 8 The other pins VCC, VSS, MOD0, MOD1 20 P43/PWM11 P42/PWM10/BZ2 P41/PWM01 P40/PWM00 8-bit PWM timer #3 6 P50/AN0 to P57/AN7 8-bit timer N-ch open-drain I/O port 8 External interrupt MB89670R/670AR Series 2. Block Diagram of MB89673AR /89675AR/89677AR/89P677A/89PV670A Timebase timer X0 X1 Oscillator CMOS I/O port Clock controller Reset circuit (WDT) RST RAM F2MC-8L CPU Internal data bus 16-bit up/down counter/timer 8-bit up/down counter/timer P37/UDA2 P36/UDB2 P35/UDZ2 8-bit up/down counter/timer P34/UDA1 P33/UDB1 P32/UDZ1 16-bit timer/counter P47/EC 8/16-bit timer ROM CMOS I/O port 8-bit timer P46/TCO2 8-bit timer P45/TCO1 P44/TCI 8 P00/AD0 to P07/AD7 16 8-bit PWM timer #3 P30/PWM20 8-bit PWM timer #4 P31/PWM21 8-bit PWM timer #5 P41/PWM01 8-bit PWM timer #6 P43/PWM11 8 P10/A08 to P17/A15 MOD0 MOD1 External bus interface P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC 2-channel 8-bit PWM timer 8-bit timer #1 CMOS output port 6 P80 to P85 P50/AN0 to P57/AN7 8 N-ch open-drain output port 8-bit timer #2 8-bit serial I/O P76/SI P75/SO P74/SCK UART P73/UI P72/UO P71/UCK Buzzer output P70/BZ1 8 10-bit AD converter AVR AVCC AVSS P40/PWM00 P42/PWM10/BZ2 Input port P60/INT0/ADST to P67/INT7 8 8 External interrupt N-ch open-drain I/O port The other pins VCC, VSS, MOD0, MOD1 21 MB89670R/670AR Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89670R/670AR series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is allocated at the lowest address. The data area is allocated immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the program area. The memory space of the MB89670R/670AR series is structured as illustrated below. • Memory Space MB89675R MB89675AR MB89673R MB89673AR 0000H 0000H 0080H 0100H I/O RAM 0080H 0100H Register 384 B 0000H I/O 0080H RAM 0100H Register 512 B 0200H 0200H MB89677AR MB89P677A MB89PV670A 0000H I/O RAM 0080H 0100H Register 1 KB I/O RAM 1 KB Register 0200H 0200H 0480H 0480H Not available 0280H 0280H External area External area 4000H External area External area 8000H 8000H * 8007H 8007H Option PROM (One-time PROM product)* * 8007H 8007H External area External area C000H 8000H 8000H * C000H Not available ROM 16 KB E000H Programmable ROM 32 KB Programmable ROM 48 KB ROM 8 KB FFFFH FFFFH FFFFH FFFFH *: Since addresses 8000H to 8006H for the MB89P677A comprise an option area, pay attention to use this area for the other products in this series. 22 MB89670R/670AR Series 2. Registers The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating the instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits : Program counter PC FFFDH A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status I-flag = 0, IL1, IL0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the Program Status Register 15 PS 14 13 12 RP 11 10 9 8 Vacancy Vacancy Vacancy RP 7 6 5 4 3 2 1 0 H I IL1, IL0 N Z V C CCR 23 MB89670R/670AR Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, IL0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise. V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 24 MB89670R/670AR Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are of 8 bits each and allocated in the register banks of the memory. One bank contains eight registers and up to 32 banks can be used on every product of the MB89670R/670AR series. The bank currently in use is indicated by the register bank pointer (RP). • Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 25 MB89670R/670AR Series ■ I/O MAP Address Read/Write Register abbreviation 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (W) BCTR External bus pin control register 06H Register name (Vacancy) 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Timebase timer control register 0BH (Vacancy) 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (W) DDR4 Port 4 data direction register 10H (R/W) PDR5 Port 5 data register 11H (R) PDR6 Port 6 data register 12H (R/W) PPCR Port 6 pull-up control register 13H (R/W) PDR7 Port 7 data register 14H (R/W) PDR8 Port 8 data/port 7 swiching register 15H (R/W) BZCR Buzzer register 16H (R/W) CNTR #3 PWM control register #3 17H (R/W) COMP #3 PWM compare register #3 18H (R/W) TMCR 16-bit timer control register 19H (R/W) TCHR 16-bit timer count register (H) 1AH (R/W) TCLR 16-bit timer count register (L) 1BH (Vacancy) 1CH (R/W) SMR Serial mode register 1DH (R/W) SDR Serial data register 1EH to 1FH (Vacancy) (Continued) 26 MB89670R/670AR Series Address Read/Write Register abbreviation 20H (R/W) ADC1 A/D converter control register 1 21H (R/W) ADC2 A/D converter control register 2 22H (R/W) ADCH A/D converter data register H 23H (R/W) ADCL A/D converter data register L 24H (R/W) T2CR Timer 2 control register 25H (R/W) T1CR Timer 1 control register 26H (R/W) T2DR Timer 2 data register 27H (R/W) T1DR Timer 1 data register 28H (R/W) CNTR1 PWM 1 control register 29H (R/W) CNTR2 PWM 2 control register 2AH (R/W) CNTR3 PWM 3 control register 2BH (W) COMR2 PWM 2 compare register 2CH (W) COMR1 PWM 1 compare register 2DH to 2FH Register name (Vacancy) 30H (R) (W) UDCR1 RCR1 Up/down counter register 1 Reload compare register1 31H (R) (W) UDCR2 RCR2 Up/down counter register 2 Reload compare register2 32H (R/W) CCRA1 Counter control register A1 33H (R/W) CCRA2 Counter control register A2 34H (R/W) CCRB1 Counter control register B1 35H (R/W) CCRB2 Counter control register B2 36H (R/W) CSR1 Counter status register 1 37H (R/W) CSR2 Counter status register 2 38H (R/W) EIC1 External interrupt 1 control register 1 39H (R/W) EIC2 External interrupt 1 control register 2 3AH (R/W) EIE2 External interrupt 2 control register 3BH (R/W) EIF2 External interrupt 2 flag register 3CH to 3FH (Vacancy) (Continued) 27 MB89670R/670AR Series (Continued) Address Read/Write Register abbreviation 40H (R/W) USMR UART serial mode register 41H (R/W) USCR UART serial rate control register 42H (R/W) USTR UART status register 43H (R) (W) RXDR TXDR UART receiving data register UART transmitting data register 44H 45H (Vacancy) (R/W) RRDR 46H to 47H Baud rate generator reload data register (Vacancy) 48H* (R/W) CNTR #4 PWM control register #4 49H* (R/W) COMP #4 PWM compare register #4 4AH* (R/W) CNTR #5 PWM control register #5 4BH* (R/W) COMP #5 PWM compare register #5 4CH* (R/W) CNTR #6 PWM control register #6 4DH* (R/W) COMP #6 PWM compare register #6 4E to 7BH (Vacancy) 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH * : For the MB89673R/675R, these are (vacancies). Note: Do not use (vacancies). 28 Register name (Vacancy) MB89670R/670AR Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Rated value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V * AVCC VSS – 0.3 VCC + 0.3 V * A/D converter reference input voltage AVR VSS – 0.3 VCC + 0.3 V AVR must not exceed “AVCC + 0.3 V”. Input voltage VI VSS – 0.3 VCC + 0.3 V VO1 VSS – 0.3 VCC + 0.3 V Except P80 to P85 VO2 VSS – 0.3 VSS + 7.0 V P80 to P85 IOL — 20 mA IOLAV1 — 4 mA Average value (operating current × operating rate) IOLAV2 — 8 mA Average value (operating current × operating rate) P80 to P85 “L” level total maximum output current ∑IOL — 100 mA “L” level total average output current ∑IOLAV — 40 mA “H” level maximum output current IOH — –20 mA “H” level average output current IOHAV — –4 mA “H” level total maximum output current ∑IOH — –50 mA “H” level total average output current ∑IOHAV — –20 mA Power consumption PD — 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Output voltage “L” level maximum output current “L” level average output current Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : Use AVCC and VCC set at the same voltage. Take care that AVR does not exceed “AVCC + 0.3 V” and AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 29 MB89670R/670AR Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Rated value Symbol Parameter VCC AVCC Power supply voltage Unit Remarks 6.0 V Normal operation assurance range MB89673R/673AR/675R/675AR/677AR 2.7* 6.0 V Normal operation assurance range MB89PV670A/P677A 1.5 6.0 V Retains the RAM state in the stop mode Min. Max. 2.2* A/D converter reference input voltage AVR 0.0 AVCC V Operating temperature TA –40 +85 °C * : These values vary with the operating frequency, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” Figure 1 Operating Voltage vs. Clock Operating Frequency 6 5 A/D converter accuracy assured in the VCC = AVCC = 3.5 V to 6.0 V range. Operating voltage (V) Operation assurance range 4 3 2 1 Clock operating frequency (MHz) 1.0 2.0 4.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Minimum execution time (µs) 0.8 0.4 Note: The shaded area is additional operating assurance range only for the MB89673R/673AR/675R/675AR/677AR. 30 MB89670R/670AR Series The horizontal line of the graph in the figure 1 indicates the operating frequency of the external oscillator and the lower horizontal line indicates the min. instruction execution time = 4/FC. In the case of changing the operating clock with the clock gear function, be sure to convert it into the min. instruction execution time on the lower horizontal line since the operating voltage range is dependent on the min. instruction execution time. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 31 MB89670R/670AR Series 3. DC Characteristics (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Pin name Symbol Condition Rated value Min. Typ. Max. 0.7 VCC VCC + 0.3 P32 to P37, P44, and P47 are of a port input type. V P32 to P37, P44, and P47 are of a peripheral input type. V P32 to P37, P44, and P47 are of a port input type. 0.2 VCC V P32 to P37, P44, and P47 are of a peripheral input type. VSS + 6.0 V 4.0 V IOL = 4.0 mA 0.4 V P80 to P85 IOL = 10 mA 0.5 V VOL3 RST IOL = 4.0 mA — — 0.4 V ILI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P76, MOD0, MOD1 0.0 V < VI < VCC — — ±5 µA ILI2 P80 to P85 0.0 V < VI < VCC — — ±1 µA RPULL P00 to P07, P10 to P17, P30 to P37, P40 to P47, P60 to P67, P70 to P76, RST VI = 0.0 V 25 50 100 kΩ P00 to P07, P10 to P17, P30 to P37, P40 to P47 VIHS RST, MOD0, MOD1, P32 to P37, P44, P47, P60 to P67, P70 to P76 VIL P00 to P07, P10 to P17, P30 to P37, P40 to P47 VILS RST, MOD0, MOD1, P32 to P37, P44, P47, P60 to P67, P70 to P76 VSS − 0.3 Open-drain output VD pin applied voltage P80 to P85 VSS − 0.3 “H” level output voltage VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P71, P72, P74, P75 IOH = –2.0 mA VOL1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P76 VOL2 “H” level input voltage “L” level input voltage Input leakage current (Hi-z output leakage current) Pull-up resistance Remarks V VIH “L” level output voltage Unit 0.8 VCC — VSS − 0.3 VCC + 0.3 0.3 VCC Without pull-up resistor option With pull-up resistor option (Continued) 32 MB89670R/670AR Series (Continued) Parameter (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Pin name Symbol Condition FC = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs ICC1 Sleep mode VCC ICCS1 Power supply current*1 ICCS2 Min. Typ. Max. — 12 20 Unit mA — 1 2 mA — 1.5 2.5 mA MB89P677A FC = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs — 3 7 mA FC = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs — 1 1.5 mA ICCH VCC = 3.0 V TA = +25°C Stop mode — — 1 mA IA FC = 10 MHz When A/D converter starts — 6 8 mA FC = 10 MHz TA = +25°C When A/D converter is at a stop — — 1 µA f = 1 MHz — 10 — pF AVCC IAH Input capacitance CIN Other than AVCC, AVSS, VCC, and VSS Remarks MB89673R/ 673AR/ 675R/675AR/ 677AR/ PV670A FC = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs ICC2 Rated value *1: The measurement conditions of the power supply current are as follows. The external clock is used. The output pins are open. VCC is upon the condition above the table. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Note: The current consumption of connected EPROM and ICE is not considered on MB89PV670A. 33 MB89670R/670AR Series 4. AC Characteristics (1) Reset Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Condition tZLZH — Rated value Min. Max. 48 tHCYL — Unit Remarks ns tZLZH 0.8 VCC RST 0.2 VCC 0.2 VCC (2) Specifications for Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Rated value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Min. internal time to next power-on reset Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 34 0.2 V 0.2 V 0.2 V MB89670R/670AR Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Pin name Symbol Parameter Rated value Condition Min. Max. Unit Remarks Clock frequency FC X0, X1 1 10 MHz Clock cycle time tXCYL X0, X1 100 1000 ns Input clock pulse width PWH PWL X0 20 — ns External clock Input clock rising/falling time tCR tCF X0 — 10 ns External clock — • Clock Timing Conditions tXCYL PWH PWL tCF tCR 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC • Clock Configurations When a crystal or ceramic resonator is used X0 When an external clock is used X1 X0 FC C1 X1 Open C2 (4) Instruction Cycle (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Instruction cycle tinst (minimum execution time) Rated value (typical) Unit 4/FC, 8/FC, 16/FC, 64/FC µs Remarks (4/FC) tinst = 0.4 µs when operating at FC = 10 MHz 35 MB89670R/670AR Series (5) Clock Output Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Cycle time tCYC CLK CLK ↑ → CLK ↓ tCHCL CLK Condition — Rated value Max. 1/2 tinst* — µs 1/4 tinst – 0.07 1/4 tinst µs * : For information on tinst, see “(4) Instruction Cycle.” tCYC tCHCL 2.4 V 2.4 V CLK 0.8 V 36 Unit Min. Remarks MB89670R/670AR Series (6) Bus Read Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Rated value Condition Min. Max. Unit Remarks Valid address → RD ↓ time tAVRL RD, A15 to A08, AD7 to AD0 1/4 tinst* – 0.06 — µs RD pulse width tRLRH RD 1/2 tinst *– 0.02 — µs Valid address → Data read time tAVDV AD7 to AD0, A15 to A08 — 1/2 tinst * µs No wait RD ↓ → Data read time tRLDV RD, AD7 to AD0 — 1/2 tinst *– 0.08 µs No wait RD ↑ → Data hold time tRHDX AD7 to AD0, RD 0 — ns RD ↑ → ALE ↑ time tRHLH RD, ALE 1/4 tinst* – 0.04 — µs RD ↑ → Address loss time tRHAX RD, A15 to A08 1/4 tinst* – 0.04 — µs RD ↓ → CLK ↑ time tRLCH RD, CLK 1/4 tinst* – 0.04 — µs CLK ↓ → RD ↑ time tCLRH RD, CLK 0 — ns RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — ns BUFC ↑ → Valid address time tBHAV A15 to A08, AD7 to AD0, BUFC 5 — ns — * : For information on tinst, see “(4) Instruction Cycle.” 2.4 V CLK 0.8 V tRHLH ALE 0.8 V AD 2.4 V 0.7 VCC 0.7 VCC 2.4 V 0.8 V 0.3 VCC 0.3 VCC 0.8 V tAVDV tRHDX 2.4 V A 2.4 V tCLRH 0.8 V tRLCH 0.8 V tAVRL tRLDV 2.4 V 0.8 V tRHAX tRLRH 2.4 V RD 0.8 V tRLBL tBHAV 2.4 V BUFC 0.8 V 37 MB89670R/670AR Series (7) Bus Write Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Rated value Condition Min. Max. Valid address → ALE ↓ time tAVLL AD7 to AD0, ALE, A15 to A08 1/4 tinst* 2 – 0.064 — µs ALE ↓ time → Address loss time tLLAX AD7 to AD0, ALE, A15 to A08 5*1 — ns Valid address → WR ↓ time tAVWL WR, ALE 1/4 tinst* 2 – 0.06 — µs WR pulse width tWLWH WR 1/2 tinst* 2 – 0.02 — µs Writing data → WR ↑ time tDVWL AD7 to AD0, WR 1/2 tinst* 2 – 0.06 — µs WR ↑ → Address loss time tWHAX WR, A15 to A08 1/4 tinst* 2 – 0.04 — µs — WR ↑ → Data hold time tWHDX AD7 to AD0, WR 1/4 tinst* 2 – 0.04 — µs WR ↑ → ALE ↑ time tWHLH WR, ALE 1/4 tinst* – 0.04 — µs WR ↓ → CLK ↑ time tWLCH WR, CLK — µs CLK ↓ → WR ↑ time tCLWH WR, CLK 0 — ns ALE pulse width tLHLL ALE 1/4 tinst* 2 – 0.035 — µs ALE ↓ → CLK ↑ time tLLCH ALE, CLK 1/4 tinst* 2 – 0.03 — µs inst* 2 1/4 t – 0.04 *1: These characteristics are also applicable to the bus read timing. *2: For information on tinst, see “(4) Instruction Cycle.” 2.4 V CLK 0.8 V tLHLL tLLCH tWHLH 2.4 V ALE 0.8 V tAVLL 0.8 V tLLAX 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V 2.4 V AD tDVWH 2.4 V 0.8 V tWHDX 2.4 V tCLWH tWLCH A 0.8 V 0.8 V tAVWL tWHAX tWLWH 2.4 V WR 0.8 V 38 Unit Remarks MB89670R/670AR Series (8) Ready Input Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol RDY valid → CLK ↑ time tYVCH CLK ↑ → RDY loss time tCHYX Pin name Rated value Condition Unit Remarks Min. Max. 60 — ns * 0 — ns * RDY, CLK — RDY, CLK * : These characteristics are also applicable to the read cycle. 2.4 V CLK 2.4 V ALE AD Address Data A WR tYVCH tCHYX 2.4 V 2.4 V RDY 0.8 V 0.8 V tYVCH tCHYX Note: The bus cycle is also extended in the read cycle in the same manner. 39 MB89670R/670AR Series (9) Serial I/O Timing (AVCC = 5.0 V ±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → valid SI hold time tSHIX SCK, SI Serial clock “H” pulse width tSHSL SCK Serial clock “L” pulse width tSLSH SCK Rated value Condition Internal shift clock mode Max. 2 tinst* — µs –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs 1 tinst* — µs 1 tinst* — µs 0 200 ns External shift clock mode SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK 1/2 tinst* — µs SCK ↑ → valid SI hold time tSHIX SCK, SI 1/2 tinst* — µs * : For information on tinst, see “(4) Instruction Cycle.” • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI • External Shift Clock Mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI 40 Unit Min. Remarks MB89670R/670AR Series (10) Peripheral Input Timing (AVCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Pin name Condition Rated value Min. Max. Unit Peripheral input “H” pulse width 1 tILIH1 TCI 1 tinst* — µs Peripheral input “L” pulse width 1 tIHIL1 TCI 1 tinst* — µs Peripheral input “H” pulse width 2 tILIH2 EC, INT0 to INT7 2 tinst* — µs Peripheral input “L” pulse width 2 tIHIL2 EC, INT0 to INT7 2 tinst* — µs Peripheral input “H” pulse width 3 tILIH3 ADST 64 tinst* — µs Peripheral input “L” pulse width 3 tIHIL3 ADST A/D mode 64 tinst* — µs Peripheral input “H” pulse width 3 tILIH3 ADST 64 tinst* — µs Peripheral input “L” pulse width 3 tIHIL3 ADST Sense mode 64 tinst* — µs — Remarks * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 tILIH1 0.8 VCC TCI 0.2 VCC 0.2 VCC tIHIL2 EC INT0 to INT7 0.8 VCC tILIH2 0.8 VCC 0.2 VCC 0.2 VCC tIHIL3 tILIH3 0.8 VCC ADST 0.2 VCC 0.8 VCC 0.8 VCC 0.2 VCC 41 MB89670R/670AR Series (11) Up/down Counter Input Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Rated value Min. Max. Unit AIN input “1” pulse width tAHL 2 tinst* — µs AIN input “0” pulse width tALL 2 tinst* — µs BIN input “1” pulse width tBHL 2 tinst* — µs BIN input “0” pulse width tBLL 2 tinst* — µs AIN ↑ → BIN ↑ time tAUBU 1 tinst* — µs BIN ↑ → AIN ↓ time tBUAD 1 tinst* — µs AIN ↓ → BIN ↓ time tADBD 1 tinst* — µs BIN ↓ → AIN ↑ time tBDAU 1 tinst* — µs BIN ↑ → AIN ↑ time tBUAU 1 tinst* — µs AIN ↑ → BIN ↓ time tAUBD 1 tinst* — µs BIN ↓ → AIN ↓ time tBDAD 1 tinst* — µs AIN ↓ → BIN ↑ time tADBU 1 tinst* — µs ZIN input “1” pulse width tZHL 1 tinst* — µs ZIN input “0” pulse width tZLL 1 tinst* — µs P33, P34, P36, P37 — P32, P35 * : For information on tinst, see “(4) Instruction Cycle.” 42 Condition Remarks MB89670R/670AR Series tAHL AIN tALL 0.8 VCC 0.8 VCC 0.2 VCC tAUBU tBUAD 0.2 VCC tADBD 0.8 VCC tBDAU 0.8 VCC BIN 0.2 VCC tBHL 0.2 VCC tBLL tBHL tBLL 0.8 VCC 0.8 VCC 0.8 VCC BIN 0.2 VCC tBUAU tAUBD tBDAD 0.8 VCC 0.2 VCC tADBU 0.8 VCC AIN 0.2 VCC tAHL 0.8 VCC 0.2 VCC tALL 0.8 VCC tZHL ZIN tZLL 0.2 VCC 0.2 VCC 43 MB89670R/670AR Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 3.5 V to 6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Resolution Linearity error — Differential linearity error — Total error Rated value Unit Min. Typ. Max. — — 10 bit — — ±2.0 LSB — — ±1.5 LSB — — ±3.0 LSB Remarks AVCC = AVR = VCC Zero transition voltage VOT AN0 to AN7 AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV Full-scale transition voltage VFST AN0 to AN7 AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV — — 4 LSB — — 13.2 µs At 10 MHz oscillation — — 7.2 µs At 10 MHz oscillation AN0 to AN7 — — 10 µA AN0 to AN7 0 — AVR V AVR 0 — AVCC V AVR — 200 µA Interchannel disparity A/D mode conversion time — — Sense mode conversion time Analog port input current IAIN Analog input voltage — Reference voltage Reference voltage supply current IR AVR = 5.0 V 6. Notes on Using A/D Converter • The smaller | AVR – AVSS |, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 kΩ If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 µs at 10 MHz oscillation). An analog input equivalent circuit is shown below. • Analog Input Equivalent Circuit Sample hold circuit R ≤ 10 kΩ is recommended. C Analog input pin R 60 pF 3 kΩ Comparator Analog channel selector If R > 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. 44 closes for approx. 15 instruction cycles after starting A/D conversion. Microcontrollers internal circuit MB89670R/670AR Series Since the A/D converter contains a sample hold circuit, the level of the analog input pin might not stabilize within the sampling period after starting A/D, resulting in inaccurate A/D conversion values, if the input impedance to the analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin. It is recommended to keep the input impedance to the analog pin from exceeding 10 kΩ. If it exceeds 10 kΩ, it is recommended to connect a capacitor of approx. 0.1 µF to the analog input pin. Except for the sampling period after starting A/D, the input leakage current of the analog input pin is less than 10 µA. 7. A/D Converter Glossary • Resolution Analog-change that are identifiable with the A/D converter. • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error The deviation of the input voltage needed to change the output code by 1 LSB from the theoretical voltage • Total error The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. Theoreticall I/O characteristics Total error VFST 3FF 3FF 3FE 3FE 3FD 1.5 LSB Digital output Digital output 3FD 004 003 Actual conversion value {1 LSB × N + 0.5 LSB} 004 VNT 003 VOT 002 Actual conversion value 002 1 LSB Theoretical value 001 001 0.5 LSB AVSS AVR 1 LSB = VFST – VOT 1022 AVSS AVR Analog input Analog input (V) Total error of digital output N = VNT – {1 LSB × N + 0.5 LSB } 1 LSB (Continued) 45 MB89670R/670AR Series (Continued) Zero transition error Full-scale transition error 004 Theoretical value Actual conversion value 3FF Actual conversion value Digital output Digital output 003 002 Theoretical value 3FE VFST (Actual measured value) 3FD Actual conversion value Actual conversion value 001 3FC VOT (Actual measured value) AVSS 3FF AVR Analog input Analog input Linearity error Differential linearity error Theoretical value Actual conversion value N+1 3FE {1 LSB × N + VOT} Actual conversion value VNT VFST (Actual measured value) 004 003 V(N + 1)T N N–1 Actual conversion value 002 Digital output Digital output 3FD VNT Actual conversion value Theoretical value N–2 001 VOT (Actual measured value) AVSS AVR Analog input Linearity error of digital output N = 46 AVSS AVR Analog input VNT – {1 LSB × N + VOT} 1 LSB Differential linearity error of digital output N = V(N+1)T – VNT 1 LSB – 1 MB89670R/670AR Series ■ EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage VOL1 vs. IOL VOL1 (V) 0.8 0.7 VCC = 2.5 V 0.6 0.5 VCC = 3.0 V 0.4 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.3 0.2 0.1 0.7 VCC = 2.5 V 0.6 0.5 VCC = 3.0 V 0.4 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.3 0.2 0.1 0 1 2 3 4 5 6 IOL (mA) (2) “H” Level Output Voltage VCC – VOH (V) 1.0 TA = +25°C 0.9 0 2 4 6 8 10 12 IOL (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) VCC – VOH vs. IOH VCC = 2.5 V 0.8 VIN vs. VCC VIN (V) 5.0 4.5 TA = +25°C 4.0 3.5 0.7 VCC = 3.0 V 0.6 0.5 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.4 0.3 3.0 2.5 2.0 1.5 0.2 1.0 0.1 0.5 0.0 0.0 VOL2 vs. IOL VOL2 (V) 0.8 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 IOH (mA) 0 1 2 3 4 5 6 7 VCC (V) 47 MB89670R/670AR Series (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN vs. VCC VIN (V) 5.0 4.5 TA = +25°C 4.0 VIHS 3.5 3.0 2.5 2.0 VILS 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level (5) Power Supply Current (External Clock) ICC (mA) 20 ICC vs. VCC ICCS vs. VCC ICCS (mA) 10 15 ICC1 8 6 10 ICCS1 4 2 5 ICCS2 0 ICC2 0 3 4 5 3 4 6 VCC (V) (6) Pull-up Resistance RPULL vs. VCC RPULL (kΩ) 1000 TA = +25°C 500 100 50 10 1 48 2 3 4 5 6 VCC (V) 5 6 VCC (V) MB89670R/670AR Series ■ INSTRUCTIONS (136 instructions) Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8/3 bits) rel Branch relative address (8 bits) @ Register indirect (e.g.: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 49 MB89670R/670AR Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) indicates that the contents at address ‘×’ is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The contents addressed by the contents at address ‘×’ is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions. An instruction cycle consists of 2 machine cycles. #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A changed contents of the TL, TH and AH when instruction is executed. Symbols in the column indicate the following: • • • • “–” indicates no change. dH is the upper 8 bits of the data in the operation. AL and AH must become the contents of AL and AH each prior to the instruction executed. “00” becomes “00”. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: e.g.: 48 to 4F ← This indicates 48, 49, ... 4F. 50 MB89670R/670AR Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, the data transfered at “T ← A” is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 51 MB89670R/670AR Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 52 MB89670R/670AR Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 53 54 0 0 NOP 1 MULU 1 SWAP DIVU A 2 ROLC A CMP A 2 3 RET RETI 4 5 6 7 8 9 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC SETC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A ADDC A SUBC A A XCH XOR AND OR A, T A A A A B C D E F MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX 3 RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP 4 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP 6 MOV CMP ADDC SUBC XOR AND OR DAA A,#d8 A,#d8 A,#d8 MOV XOR AND OR MOV DAS CMP A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A@,IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC CLRB BBC MOVW MOVW MOVW XCHW dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX 7 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP 8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel 9 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 rel A B C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 rel E MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel MB89670R/670AR Series H H ■ INSTRUCTION MAP LL MB89670R/670AR Series ■ MASK OPTIONS Part number MB89673R MB89673AR MB89675R MB89675AR MB89677AR MB89P677A MB89PV670A Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible 1 Pull-up resistors P10 to P17, P30 to P37, P40 to P47, P70 to P76 Selectable by pin Selectable by pin 2 Pull-up resistors P00 to P03 Selectable by pin Selectable in 4-pin unit 3 Pull-up resistors P04 to P07 Selectable by pin Selectable in 4-pin unit 4 Power-on reset With power-on reset Without power-on reset Selectable Selectable Fixed to “with power-on reset” Selectable Selectable Fixed to Approx. 218/FC (Approx. 26.2 ms) Selectable Selectable Fixed to “with reset output” No. Oscillation stabilization time selection (at 10 MHz) 5 Approx. 218/FC (approx. 26.2 ms) Approx. 217/FC (approx. 13.1 ms) Approx. 214/FC (approx. 1.6 ms) Approx. 24/FC (approx. 0 ms) Fixed to “without pull-up resistor” FC: Clock frequency 6 Reset pin output With reset output Without reset output ■ ORDERING INFORMATION Part number Package MB89673RPF MB89673ARPF MB89675RPF MB89675ARPF MB89677ARPF MB89P677APF 80-pin Plastic QFP (FPT-80P-M06) MB89673RPFM MB89673ARPFM MB89675RPFM MB89675ARPFM MB89677ARPFM MB89P677APFM 80-pin Plastic LQFP (FPT-80P-M11) MB89PV670ACF 80-pin Ceramic MQFP (MQP-80C-P01) Remarks 55 MB89670R/670AR Series ■ PACKAGE DIMENSIONS 80-pin Plastic QFP (FPT-80P-M06) 23.90±0.40(.941±.016) 64 20.00±0.20(.787±.008) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 41 65 40 14.00±0.20 (.551±.008) 12.00(.472) REF 17.90±0.40 (.705±.016) 16.30±0.40 (.642±.016) INDEX 80 25 "A" LEAD No. 1 24 0.80(.0315)TYP 0.35±0.10 (.014±.004) 0.16(.006) 0.15±0.05(.006±.002) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.30±0.40(.878±.016) C 56 1994 FUJITSU LIMITED F80010S-3C-2 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX 0 10° 0.80±0.20 (.031±.008) Dimensions in mm (inches) MB89670R/670AR Series 80-pin Plastic LQFP (FPT-80P-M11) +0.20 1.50 −0.10 +.008 .059 −.004 16.00±0.20(.630±.008)SQ 14.00±0.10(.551±.004)SQ 60 41 61 (Mounting height) 40 12.35 (.486) REF 15.00 (.591) NOM 1 PIN INDEX 80 LEAD No. 21 1 0.65(.0256)TYP 0.30±0.10 (.012±.004) 20 0.13(.005) 0.10(.004) C 1995 FUJITSU LIMITED F80016S-1C-3 Details of "A" part "A" M 0.10±0.10 (STAND OFF) (.004±.004) +0.05 0.127 −0.02 +.002 .005 −.001 0 10˚ 0.50±0.20 (.020±.008) Dimensions in mm (inches) 57 MB89670R/670AR Series 80-pin Ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) +0.40 1.20 –0.20 +.016 .047 –.008 INDEX AREA 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.40(.724) REF INDEX 1.27±0.13 (.050±.005) 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 0.15±0.05 8.70(.343) (.006±.002) MAX C 58 1994 FUJITSU LIMITED M80001SC-4-2 Dimensions Dimensions in in mm mm (inches) (inches) MB89670R/670AR Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9803 FUJITSU LIMITED Printed in Japan