FUJITSU SEMICONDUCTOR DATA SHEET DS07-12516-4E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89870 Series MB89875/P875/PV870 ■ DESCRIPTION The MB89870 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a PWM timer, a serial interface, an A/D converter, an external interrupt, an LCD controller/ driver, and a watch prescaler. ■ FEATURES • • • • • • • • • • • • • F2MC-8L family CPU core Dual-clock control system Maximum memory space: 64 Kbytes Minimum execution time: 0.4 µs/10 MHz Interrupt processing time: 3.6 µs/10 MHz I/O ports: max. 45 channels 21-bit timebase timer 8-bit PWM timer: 1 channel, 1 output channel 8/16-bit timer/counter: 2 channels (16 bits × 1 channel) 8-bit serial I/O: 1 channel 10-bit A/D converter: 8 channels OP amp: 4 channels External interrupt (wake-up function): 8 channels (Continued) ■ PACKAGE 80-pin Plastic LQFP 80-pin Plastic QFP 80-pin Ceramic MQFP (FPT-80P-M05) (FPT-80P-M06) (MQP-80C-P01) MB89870 Series (Continued) • Watch prescaler (15 bits) • LCD controller/driver: 16 to 24 segments × 2 to 4 commons • Power-on reset function • Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) • LQFP-80 (0.50-mm pitch) and QFP-80 (0.80-mm pitch) package ■ PRODUCT LINEUP Part number Parameter Classification ROM size RAM size MB89875 MB89P875 MB89PV870 Mass production product (mask ROM product) One-time PROM product Piggyback/evaluation product (for development) 16 K × 8 bits (internal mask ROM) 16 K × 8 bits (internal PROM) 32 K × 8 bits (external ROM) 512 × 8 bits 12 × 8 bits LCD display RAM CPU functions Ports 8-bit PWM timer Timers 1 K × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs/10 MHz to 6.4 µs/10 MHz, 61.0 µs/32.768 kHz 3.6 µs/10 MHz to 57.6 µs/10 MHz, 549.3 µs/32.768 kHz General-purpose I/O ports (CMOS): 45 (42 ports also serve as peripherals and 8 ports are also an N-ch open-drain type.) 8-bit interval timer operation (square output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 1 channel 7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 1 channel 8-bit timer operation (operating clock cycle) × 2 channels 16-bit timer operation (operating clock cycle) × 1 channel 8-bit Serial I/O 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) LCD controller 24 segments × 4 commons 10-bit A/D converter 10-bit resolution × 8 channels A/D conversion mode (conversion time: 13.2 µs) Sense mode (conversion time: 7.2 µs) OP amps 4 channels The output can be used for A/D converter input. (Continued) 2 MB89870 Series (Continued) Part number External interrupt MB89P875 MB89875 Parameter MB89PV870 8 independent channels (edge selection, interrupt vector, and source flag) Rising edge/falling edge selectable (4 channels) Rising edge/falling edge/both edges selectable (4 channels) Used also for wake-up from stop/sleep mode (Edge detection is also permitted in stop mode.) Low-power Consumption (Standby mode) Subclock mode, sleep mode, watch mode, and stop mode Process CMOS Operating voltage* 2.2 V to 6.0 V 2.7 V to 6.0 V EPROM for use MBM27C256A-20TV * : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89875 MB89P875 MB89PV870 FPT-80P-M05 × FPT-80P-M06 × MQP-80C-P01 : Available × × : Not available Note: For more information about each package, see section “■ Package Dimensions.” 3 MB89870 Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89PV870, the program area starts from address 8006H but on the MB89P875 and MB89875 starts from 8000H. (On the MB89P875, addresses BFF0H to BFF6H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV870 and MB89875, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P875.) 2. Current Consumption • In the case of the MB89PV870, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • A pull-up resistor cannot be selectable for P30 to P37 if they are used as the analog input pin for an A/D converter. • A pull-up resistor cannot be selectable for P10 to P17, and P34 to P37 if an OP amp is used. • A pull-up resistor is not selectable for P40 to P47 and P23, P24 if they are used as LCD pins. • Options are fixed on the MB89PV870. 4 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P46/SEG22 P47/SEG23 AVSS AVR AVCC P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4/OUT0 P35/AN5/OUT1 P36/AN6/OUT2 VSS P37/AN7/OUT3 X1 X0 MOD1 MOD0 RST P00/INT0 P01/INT1 P02/INT2 P03/INT3 P04/INT4 P05/INT5 P06/INT6 P07/INT7 P10/IN0– P11/IN0+ P12/IN1– P13/IN1+ P14/IN2– P15/IN2+ P16/IN3– P17/IN3+ P50/PWM P51/TO2 P52/TO1 P53/EC P54/BUZ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P45/SEG21 P44/SEG20 P43/SEG19 P42/SEG18 P41/SEG17 P40/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 MB89870 Series ■ PIN ASSIGNMENT (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG1 SEG0 COM0 COM1 COM2/P24 COM3/P23 V3 VCC V2 V1 V0 VSS P22 P21 P20 X1A X0A P57/SCK P56/SO P55/SI (FPT-80P-M05) 5 MB89870 Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P43/SEG19 P42/SEG18 P41/SEG17 P40/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P03/INT3 P04/INT4 P05/INT5 P06/INT6 P07/INT7 P10/IN0– P11/IN0+ P12/IN1– P13/IN1+ P14/IN2– P15/IN2+ P16/IN3– P17/IN3+ P50/PWM P51/TO2 P52/TO1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P44/SEG20 P45/SEG21 P46/SEG22 P47/SEG23 AVSS AVR AVCC P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4/OUT0 P35/AN5/OUT1 P36/AN6/OUT2 VSS P37/AN7/OUT3 X1 X0 MOD1 MOD0 RST P00/INT0 P01/INT1 P02/INT2 (FPT-80P-M06) 6 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2/P24 COM3/P23 V3 VCC V2 V1 V0 VSS P22 P21 P20 X1A X0A P57/SCK P56/SO P55/SI P54/BUZ P53/EC MB89870 Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P43/SEG19 P42/SEG18 P41/SEG17 P40/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 (Top view) 100 99 98 97 96 95 94 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 110 111 112 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Each pin inside the dashed line is for the MB89PV870 only. SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2/P24 COM3/P23 V3 VCC V2 V1 V0 VSS P22 P21 P20 X1A X0A P57/SCK P56/SO P55/SI P54/BUZ P53/EC P03/INT3 P04/INT4 P05/INT5 P06/INT6 P07/INT7 P10/IN0– P11/IN0+ P12/IN1– P13/IN1+ P14/IN2– P15/IN2+ P16/IN3– P17/IN3+ P50/PWM P51/TO2 P52/TO1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P44/SEG20 P45/SEG21 P46/SEG22 P47/SEG23 AVSS AVR AVCC P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4/OUT0 P35/AN5/OUT1 P36/AN6/OUT2 VSS P37/AN7/OUT3 X1 X0 MOD1 MOD0 RST P00/INT0 P01/INT1 P02/INT2 (MQP-80C-P01) • Pin assignment on package top (MB89PV870 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 A2 97 N.C. 105 OE 82 VPP 90 A1 98 O4 106 N.C. 83 A12 91 A0 99 O5 107 A11 84 A7 92 N.C. 100 O6 108 A9 85 A6 93 O1 101 O7 109 A8 86 A5 94 O2 102 O8 110 A13 87 A4 95 O3 103 CE 111 A14 88 A3 96 VSS 104 A10 112 VCC N.C.: Internally connected. Do not use. 7 MB89870 Series ■ PIN DESCRIPTION Pin no. QFP*2 MQFP*3 15 17 X1 16 18 X0 44 46 X0A 45 47 X1A 17 19 MOD1 18 20 MOD0 19 21 20 to 27 22 to 29 28, 29, 30, 31, 32, 33, 34, 35 Circuit type Function A Main clock crystal oscillator pins (max. 10 MHz) B Subclock crystal oscillator pins (32.768 kHz) C Operating mode selection pins Connect to VSS (GND) when using. RST J Reset I/O pin “L” is output from this pin by an internal source. The internal circuit is initialized by the input of “L”. P00/INT0 to P07/INT7 D General-purpose I/O ports Also serve as an external interrupt input (wake-up function). External interrupt input is hysteresis input. 30, 31, 32, 33, 34, 35, 36, 37 P10/IN0–, P11/IN0+, P12/IN1–, P13/IN1+, P14/IN2–, P15/IN2+, P16/IN3–, P17/IN3+ E General-purpose I/O ports Also serve as the input for the OP amp 46 to 48 48 to 50 P20 to P22 F General-purpose I/O ports 6 to 9 8 to 11 P30/AN0 to P33/AN3 E General-purpose I/O ports Also serve as the input for the A/D converter. 10 to 14 12 to 16 P34/AN4/OUT0 to P37/AN7/OUT3 G General-purpose I/O ports Also serve as the A/D converter input and the output for the OP amp. 75 to 80, 1,2 77 to 80, 1 to 4 P40/SEG16 to P47/SEG23 H General-purpose I/O ports Also serve as an LCD controller/driver segment output. 36 38 P50/PWM F General-purpose I/O port The output type can be switched between N-ch open-drain and CMOS. Also serves as an 8-bit PWM timer. 37, 38, 39 39, 40, 41 P51/TO2, P52/TO1, P53/EC F General-purpose I/O ports The output type can be switched between N-ch open-drain and CMOS. Also serves as an 8/16-bit timer/counter. *1: FPT-80P-M05 *2: FPT-80P-M06 *3: MQP-80C-P01 8 Pin name LQFP*1 (Continued) MB89870 Series (Continued) Pin no. Pin name Circuit Function LQFP*1 QFP*2 MQFP*3 40 42 P54/BUZ F General-purpose I/O port The output type can be switched between N-ch open-drain and CMOS. Also serves as a buzzer output. 41, 42, 43 43, 44, 45 P55/SI, P56/SO, P57/SCK F General-purpose I/O ports The output type can be switched between N-ch open-drain and CMOS. Also serve as an 8-bit serial I/O. 59 to 74 61 to 76 SEG15 to SEG0 I LCD controller/driver segment output pins 58, 57 60, 59 COM0, COM1 I LCD controller/driver common output pins 56, 55 58, 57 COM2/P24, COM3/P23 H LCD controller/driver common output pins These pins can be used as general-purpose I/O ports when they are not used as common output pins. 50 to 54 52 to 56 V3 to V0 — LCD driving power supply pins 5 7 AVCC — A/D converter and OP amp power supply pin 4 6 AVR — A/D converter reference voltage input pin 3 5 AVSS — A/D converter and OP amp power supply (GND) pin 53 55 VCC — Power supply pin 13, 49 15, 51 VSS — Power supply (GND) pins type *1: FPT-80P-M05 *2: FPT-80P-M06 *3: MQP-80C-P01 9 MB89870 Series • External EPROM pins (MB89PV870 only) Pin no. 10 Pin name I/O Function 82 VPP O “H” level output pin 83 84 85 86 87 88 89 90 91 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 93 94 95 O1 O2 O3 I Data input pins 96 VSS O Power supply (GND) pin 98 99 100 101 102 O4 O5 O6 O7 O8 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby. 104 A10 O Address output pin 105 OE O ROM output enable pin Outputs “L” at all times. 107 108 109 A11 A9 A8 O Address output pins 110 A13 O 111 A14 O 112 VCC O EPROM power supply pin 81 92 97 106 N.C. — Internally connected pins Be sure to leave them open. MB89870 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A Main clock • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X1 N-ch P-ch P-ch X0 N-ch Main clock control signal B Subclock • At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V X1A N-ch P-ch P-ch X0A N-ch Subclock control signal C • CMOS hysteresis input D • CMOS I/O (when selected as general-purpose ports) • Hysteresis input (when selected as an external interrupt input) • Pull-up resistor optional at approximately 50 kΩ/5.0 V R P-ch P-ch N-ch E R P-ch N-ch Analog input • Analog input • CMOS I/O (when selected as general-purpose ports) • Pull-up resistor optional at approximately 50 kΩ/5.0 V P-ch P-ch N-ch (Continued) 11 MB89870 Series (Continued) Type Circuit Remarks F • CMOS I/O (when selected as general-purpose ports) • P50 to P57 are output only and can be switched between CMOS output and N-ch open-drain output. • Pull-up resistor optional at approximately 50 kΩ/5.0 V R P-ch P-ch N-ch G P-ch R Analog output N-ch Analog output P-ch • • • • Analog input Analog output CMOS I/O (when selected as general-purpose ports) Pull-up resistor optional at approximately 50 kΩ/5.0 V P-ch N-ch H R P-ch N-ch P-ch P-ch N-ch • LCD controller/driver output • CMOS I/O (when selected as general-purpose ports) • Pull-up resistor optional at approximately 50 kΩ/5.0 V P-ch N-ch I P-ch • LCD controller/driver output N-ch P-ch N-ch J R P-ch N-ch 12 • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • CMOS hysteresis input MB89870 Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 13 MB89870 Series ■ PROGRAMMING TO THE EPROM ON THE MB89P875 The MB89P875 is an OTPROM version of the MB89870 series. 1. Features • 16-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below. Address Single chip 0000H EPROM mode (Corresponding address on the EPROM programmer) I/O 0080H RAM 0280H Not available 3FF0H BFF0H Not available Option area 3FF6H BFF6H Not available C000H Vacancy 4000H EPROM 16 KB PROM 16 KB FFFFH 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P875 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF6H of the EPROM programmer. (For information about each corresponding option, see “7. Setting OTPROM Options.”) (3) Program to 3FF0H to 7FFFH with the EPROM programmer. 14 MB89870 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Recommended programmer manufacturer and programmer name Part No. Package Compatible socket adapter Sun Hayato Co., Ltd. Minato Electronics Inc. Advantest Corp. 1890A R4945A MB89P875PFV LQFP-80 ROM-80SQF-28DP-8L Recommended Recommended MB89P875PF QFP-80 ROM-80QF-28DP-8L3 Recommended Recommended Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Minato Electronics Inc.: TEL: USA (1)-916-348-6066 JAPAN (81)-45-591-5611 Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111 15 MB89870 Series 7. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Address Bit 7 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Reset pin output 1: Yes 0: No Power-on reset 1: Yes 0: No 00: 218/FCH 01: 217/FCH 10: 213/FCH 11: 0 Vacancy Readable and writable Readable and writable Single/dualclock system 1: Dual clock 0: Single clock P07 Pull-up 1: No 0: Yes P06 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes Vacancy Vacancy P40 to P43 Pull-up 1: No 0: Yes P16, P17 Pull-up 1: No 0: Yes P14, P15 Pull-up 1: No 0: Yes P12, P13 Pull-up 1: No 0: Yes P10, P11 Pull-up 1: No 0: Yes 3FF0H Readable and writable Oscillation stabilization time 3FF2H Readable and writable Readable and writable P44 to P47 Pull-up 1: No 0: Yes P37 3FF3H Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P57 Pull-up 3FF4H 1: No 0: Yes P56 Pull-up 1: No 0: Yes P55 Pull-up 1: No 0: Yes P54 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable P24 Pull-up 1: No 0: Yes P23 Pull-up 1: No 0: Yes P22 Pull-up 1: No 0: Yes P21 Pull-up 1: No 0: Yes P20 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Reserved bit Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable 3FF5H 3FF6H Readable and writable Note: Each bit is set to ‘1’ as the initialized value. 16 Bit 3 Vacancy Vacancy 3FF1H Bit 6 MB89870 Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Compatible socket part number LCC-32 (Rectangle) ROM-32LC-28DP-YG LCC-32 (Square) ROM-32LC-28DP-S Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 3. Memory Space Memory space in 32-Kbyte PROM is diagrammed below. Address Single chip 0000H Corresponding addresses on the EPROM programmer I/O 0080H RAM 0480H Not available 0000H 8000H Not available Not available 0006H 8006H PROM 32 KB PROM 32 KB FFFFH 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0006H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 17 MB89870 Series ■ BLOCK DIAGRAM I/O port Timebase timer X0 X1 Main clock oscillator 8-bit PWM timer P50/PWM 8-bit timer/counter 2 P51/TO2 Clock controller Subclock oscillator (32.768 kHz) X0A X1A P52/TO1 8-bit timer/counter 1 Reset circuit (Watchdog) RST P53/EC Buzzer output P54/BUZ 8-bit serial I/O P55/SI P56/SO P57/SCK P40/SEG16 to P47/SEG23 COM2/P24, COM3/P23 COM0, COM1 8 8 LCD controller/driver Internal bus I/O port 3 2 P20 to P22 I/O port 2 COM: 2 to 4 I/O port 16 SEG: 16 to 24 SEG0 to SEG15 8 8 External interrupt V0 to V3 P00/INT0 to P07/INT7 4 10-bit A/D converter 4 4 P30/AN0 to P33/AN3 P34/AN4/OUT0 LCD display RAM (12 × 8 bits) RAM – + P10/IN0– P11/IN0+ P35/AN5/OUT1 F2MC-8L CPU – + P12/IN1– P13/IN1+ P36/AN6/OUT2 ROM – + Other pins MOD × 2, V CC × 1 V SS × 2 AV CC , AV SS , AVR 18 P14/IN2– P15/IN2+ P37/AN7/OUT3 – + P16/IN3– P17/IN3+ MB89870 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89870 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89870 series is structured as illustrated below. • Memory Space 0000H MB89PV870 0000H RAM 512 B 0100H 0100H 0200H I/O RAM 512 B Register Register Register MB89P875 0080H 0080H RAM 1 KB 0100H 0000H I/O I/O 0080H MB89875 0200H 0200H 0280H 0280H Not available 0480H Not available 8000H Not available BFF0H Not available C000H C000H External ROM 32 KB PROM 16 KB ROM 16 KB FFFFH FFFFH FFFFH 19 MB89870 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code 16 bits Initial value FFFDH : Program counter PC A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status I-flag = 0, IL1,0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the Program Status Register 15 PS 14 13 12 RP 10 9 8 Vacancy Vacancy Vacancy RP 20 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89870 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 21 MB89870 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89875 (RAM 512 × 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. • Register Bank Configuraiton This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 22 MB89870 Series ■ I/O MAP Address Read/write Register name 00H R/W PDR0 Port 0 data register 01H W DDR0 Port 0 data direction register 02H R/W PDR1 Port 1 data register 03H W DDR1 Port 1 data direction register 04H R/W PDR2 Port 2 data register 05H R/W DDR2 Port 2 data direction register 06H Register description Vacancy 07H R/W SCC System clock control register 08H R/W SMC Standby control register 09H R/W WDTE Watchdog timer control register 0AH R/W TBCR Timebase timer control register 0BH R/W WCR Watch prescaler control register 0CH R/W PDR3 Port 3 data register 0DH R/W DDR3 Port 3 data direction register 0EH R/W PDR4 Port 4 data register 0FH R/W DDR4 Port 4 data direction register 10H Vacancy 11H Vacancy 12H Vacancy 13H Vacancy 14H Vacancy 15H Vacancy 16H R/W PDR5 Port 5 data register 17H R/W DDR5 Port 5 data direction register 18H Vacancy 19H Vacancy 1AH R/W CHG5 Port 5 switching register 1BH Vacancy 1CH Vacancy 1DH W ICR3 Port 3 input control register 1EH R/W CNTR PWM control register 1FH W COMP PWM compare register (Continued) 23 MB89870 Series (Continued) Address Read/write Register name 20H Vacancy 21H Vacancy 22H Vacancy 23H Vacancy 24H R/W T2CR Timer 2 control register 25H R/W T1CR Timer 1 control register 26H R/W T2DR Timer 2 data register 27H R/W T1DR Timer 1 data register 28H R/W SMR Serial mode register 29H R/W SDR Serial data register 2AH Vacancy 2BH Vacancy 2CH R/W OPC OP amp control register 2DH R/W ADC1 A/D converter control register 1 2EH R/W ADC2 A/D converter control register 2 2FH R/W ADCH A/D converter data register H 30H R/W ADCL A/D converter data register L 31H R/W EIE1 External interrupt 1 enable register 32H R/W EIF1 External interrupt 1 flag register 33H R/W EIE2 External interrupt 2 enable register 34H to 5FH 60H to 6BH Vacancy R/W VRAM 6CH to 6FH Display data RAM Vacancy 70H R/W LCR1 LCD controller/driver control register 1 71H R/W LCR2 LCD controller/driver control register 2 72H to 7BH Vacancy 7CH W ILR1 Interrupt level setting register 1 7DH W ILR2 Interrupt level setting register 2 7EH W ILR3 Interrupt level setting register 3 7FH Note: Do not use vacancies. 24 Register description Vacancy MB89870 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. Max. Unit Power supply voltage VCC AVCC VSS – 0.3 VSS + 7.0 V A/D converter reference input voltage AVR VSS – 0.3 VSS + 7.0 V LCD power supply voltage V0 to V3 VSS – 0.3 VSS + 7.0 V Input voltage VI VSS – 0.3 VCC + 0.3 V Output voltage VO VSS – 0.3 VCC + 0.3 V “L” level maximum output current IOL 20 mA “L” level average output current IOLAV 4 mA “L” level total maximum output current ∑IOL 100 mA “L” level total average output current ∑IOLAV 40 mA “H” level maximum output current IOH –20 mA “H” level average output current IOHAV –4 mA “H” level total maximum output current ∑IOH –50 mA “H” level total average output current ∑IOHAV –20 mA Power consumption PD 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Remarks * V0 to V3 must not exceed VCC. Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : Use AVCC and VCC set at the same voltage. Take care so that AVR does not exceed AVCC + 0.3 V and AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 25 MB89870 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Power supply voltage Symbol VCC AVCC Value Unit Remarks Min. Max. 2.2* 6.0* V Normal operation assurance range* MB89875 2.7 6.0 V Normal operation assurance range MB89PV870/P875 1.5 6.0 V Retains the RAM state in stop mode A/D converter reference input voltage AVR 0.0 AVCC V LCD power supply voltage V0 to V3 VSS VCC V Operating temperature TA –40 +85 °C LCD power supply range (The optimum value is dependent on the LCD element in use.) * : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” 26 MB89870 Series Figure 1 Operating Voltage vs. Main Clock Operating Frequency 6 Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range 5 Operating voltage (V) Operation assurance range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 4.0 2.0 0.8 Minimum execution time (instruction cycle) (ms) 0.4 Note: The shaded area is assured only for the MB89875. Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 27 MB89870 Series 3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition VIH P20 to P24, P30 to P37, P40 to P47, P50 to P52, P54, P56 VIHS Value Unit Remarks Min. Typ. Max. 0.7 VCC VCC + 0.3 V P00 to P07, P10 to P17, MOD0, MOD1, RST, P53, P55, P57 0.8 VCC VCC + 0.3 V VIL P20 to P24, P30 to P37, P40 to P47, P50 to P52, P54, P56 VSS − 0.3 0.3 VCC V VILS P00 to P07, P10 to P17, MOD0, MOD1, RST, P53, P55, P57 — VSS − 0.3 0.2 VCC V VD P50 to P57 — VSS − 0.3 VCC – 0.3 V “H” level output voltage VOH P00 to P07, P10 to P17, P20 to P24, P30 to P37, IOH = –2.0 mA P40 to P47, P50 to P57 4.0 V “L” level output voltage VOL P00 to P07, P10 to P17, P20 to P24, P30 to P37, IOL = 4.0 mA P40 to P47, P50 to P57 0.4 V Input leakage current (Hi-Z output ILI leakage current) P00 to P07, P10 to P17, P20 to P24, P30 to P37, 0.0 V < VI < P40 to P47, P50 to P57 VCC MOD0, MOD1, RST ±5 µA With pull-up resistor Pull-up resistance P00 to P07, P10 to P17, P20 to P24, P30 to P37, VI = 0.0 V P40 to P47, P50 to P57 25 50 100 kΩ With pull-up resistor “H” level input voltage “L” level input voltage Open-drain output pin application voltage RPULL N-ch opendrain (Continued) 28 MB89870 Series Symbol Pin name ICC1 FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs ICC2 FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs — 12 20 mA — 1.0 2 mA — 1.5 2.5 FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs — 3 7 mA FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs — 0.5 1.5 mA — 50 100 µA MB89875/ PV870 — 500 700 µA MB89P875 ICCLS FCL = 32.768 kHz, VCC = 3.0 V Subclock sleep mode — 15 50 µA ICCT FCL = 32.768 kHz, VCC = 3.0 V • Watch mode • Main clock stop mode at dualclock system — 3 15 µA ICCH TA = +25°C • Subclock stop mode • Main clock stop mode at singleclock system — — 1 µA IA FCH = 10 MHz, when A/D conversion is activated — 1.5 3 mA FCH = 10 MHz, TA = +25°C, when A/D conversion is stopped — — 1 µA Sleep mode Parameter (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. ICCS1 ICCS2 ICCL VCC Power supply current*1 AVCC IAH FCL = 32.768 kHz, VCC = 3.0 V Subclock mode MB89875/ PV870 mA MB89P875 (Continued) 29 MB89870 Series (Continued) Parameter LCD divided resistance Symbol RLCD COM0 to 3 output RVCOM impedance Pin name (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. Between VCC and V0 at VCC = 5.0 V 300 500 750 kΩ — 2.5 kΩ — 15 kΩ — ±1 µA f = 1 MHz — 10 pF COM0 to 3 V1 to V3 = 5.0 V SEG0 to 24 output impedance RVSEG SEG0 to 24 LCD controller/ driver leakage current ILCDL V0 to V3, COM0 to 3 SEG0 to SEG24 Input capacitance CIN Other than AVCC, AVSS, VCC, and VSS *1: The power supply current is measured at the external clock. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Note: For pins which serve as the LCD and ports (P23, P24 and P40 to P47), see the port parameter when these pins are used as ports and the LCD parameter when they are used as LCD pins. 30 MB89870 Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 48 tHCYL — Unit Remarks ns tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cutoff time tOFF Condition — Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 0.2 V 0.2 V 0.2 V 31 MB89870 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Pin name FCH Condition Value Unit Remarks Min. Typ. Max. X0, X1 1 — 10 MHz FCL X0A, X1A — 32.768 — kHz tHCYL X0, X1 100 — 1000 ns tLCYL X0A, X1A — 30.5 — µs Input clock pulse width PWH PWL X0 20 — — ns External clock Input clock rising/ falling time tCR tCF X0 — — 10 ns External clock Clock frequency Clock cycle time 32 Symbol — MB89870 Series X0 and X1 Timing and Conditions tHCYL PWL P WH tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic resonator is used X0 When an external clock is used X0 X1 X1 Open X0A and X1A Timing and Conditions tLCYL X0A 0.2 VCC 0.2 VCC Subclock Conditions When a crystal or ceramic resonator is used X0A X1A 33 MB89870 Series (4) Instruction Cycle Parameter Symbol Instruction cycle tinst (minimum execution time) Value (typical) Unit Remarks 4/FCH, 8/FCH, 16/FCH, 64/FCH µs (4/FCH) tinst = 0.4 µs when operating at FCH = 10 MHz 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz Note: When operating at 10 MHz, the cycle varies with the set execution time. (5) Serial I/O Timing (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → valid SI hold time tSHIX SCK, SI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Condition Internal shift clock mode SCK External shift clock mode Value Max. 2 tinst* — µs –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs 1 tinst* — µs 1 tinst* — µs 0 200 ns SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK 1/2 tinst* — µs SCK ↑ → valid SI hold time tSHIX SCK, SI 1/2 tinst* — µs * : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V t SLOV 2.4 V SO 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI 34 Unit Min. tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Remarks MB89870 Series (6) Peripheral Input Timing (VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Peripheral input “H” pulse width 2 tILIH2 Peripheral input “L” pulse width 2 tIHIL2 Value Pin name EC INT7 to INT0 Unit Min. Max. 1 tinst* — µs 1 tinst* — µs 2 tinst* — µs 2 tinst* — µs Remarks * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 tILIH1 EC 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tIHIL2 tILIH2 INT7 to INT0 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 35 MB89870 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition Resolution — Total error — Linearity error Differential linearity error Zero transition voltage VOT Full-scale transition voltage VFST AVR = AVCC — Interchannel disparity A/D mode conversion time Analog input voltage — Reference voltage — AN0 to AN7 IR AVR Reference voltage supply current IRH Typ. Max. — — 10 bit — — ±3.0 LSB — — ±2.0 LSB — — ±1.5 LSB AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV — 4.0 LSB — 33 tinst* — µs — 18 tinst* — µs — — 10 µA 0.0 — AVR V 0.0 — AVCC V AVR = 5.0 V, when A/D conversion is activated — 200 µA AVR = 5.0 V, when A/D conversion is stopped — — 1 µA — IAIN Unit Remarks Min. — Sense mode conversion time Analog port input current Value — * : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 6. A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values 36 MB89870 Series Digital output 11 1111 1111 11 1111 • 1110 00 0000 00 0000 00 0000 • • • • • • • • • • • • • • • • • • • Theoretical conversion value Actual conversion value (1 LSB × N + VOT) 1 LSB = AVR 1024 Linearity error = Linearity error Differential linearity error = Total error = VNT – (1 LSB × N + VOT) 1 LSB V( N + 1 ) T – VNT – 1 1 LSB VNT – (1 LSB × N + 1 LSB) 1 LSB 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input 7. Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89870 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. • Analog Input Equivalent Circuit Sample hold circuit . C =. 33 pF Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. . R =. 6 kΩ Close for 8 instruction cycles after activating A/D conversion. Analog channel selector • Error The smaller the | AVR – AVSS |, the greater the error would become relatively. 37 MB89870 Series 8. OP Amp Electrical Characteristics (1) AVCC = 5.0 V (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Condition I/O voltage range — IN0± to IN3± Minimum load resistance — Maximum load resistance Parameter Value Unit Remarks Min. Typ. Max. — 0.5 VCC – 1.25 0.5 VCC 0.5 VCC + 1.25 V — — 100 — — kΩ — — — — — 100 pF Offset voltage — — — –10 0 +10 mV Gain-bandwidth production — — — — 1.8 — MHz DC gain — — — — 75 — dB Slew rate — — — — 0.9 — V/µs (2) AVCC = 3.0 V (AVCC = VCC = 2.7 V to 3.3 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Condition I/O voltage range — IN0± to IN3± Minimum load resistance — Maximum load resistance Parameter 38 Value Unit Remarks Min. Typ. Max. — 0.5 0.5 VCC – 0.35 VCC – 1.20 V — — 250 — — kΩ — — — — — 100 µA Offset voltage — — — –10 0 +10 mV Gain-bandwidth production — — — — 0.5 — MHz DC gain — — — — 75 — dB Slew rate — — — — 0.1 — V/µs MB89870 Series ■ EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) “H” Level Output Voltage VOL vs. IOL VCC – VOH vs. IOH VOL (V) VCC = 2.5 V TA = +25 °C 0.5 VCC = 3.0 V 0.4 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V –1.0 –1.5 –2.0 –2.5 3.5 VIN vs. VCC TA = +25°C VIHS 2.5 3.0 VILS 2.0 2.5 2.0 1.5 1.0 1.5 0.5 1.0 0.0 0.5 0 1 2 3 4 5 6 –3.0 IOH (mA) (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) 3.5 3.0 4.0 0.0 VCC = 2.5 V 4.0 TA = +25 °C 4.5 TA = +25 °C VIN (V) 5.0 4.5 VIN vs. VCC VIN (V) 5.0 VCC – VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.5 0.0 7 VCC (V) 0 1 2 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 39 MB89870 Series (5) Power Supply Current (External Clock) ICCS1 vs. VCC, ICCS2 vs. V CC ICC1 vs. VCC, ICC2 vs. VCC ICCS (mA) 5.0 ICC (mA) 16 Divide by 4 (ICC1) FCH = 10 MHz TA = +25°C 14 4.0 12 Divide by 4 (ICC1) 3.5 10 3.0 Divide by 8 8 2.5 Divide by 8 2.0 6 Divide by 16 4 Divide by 16 1.5 Divide by 64 (ICC2) 1.0 2 Divide by 64 (ICC2) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) ICCL vs. VCC ICCL (µA) 200 TA = +25 °C 180 0.5 0 2.0 40 35 120 30 100 25 80 20 60 15 40 10 20 5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) 3.0 3.5 4.0 4.5 5.0 0 2.0 2.5 5.5 6.0 6.5 VCC (V) ICCLS vs. VCC TA = +25 °C 45 140 2.5 2.5 ICCLS (µA) 50 160 0 2.0 FCH = 10 MHz TA = +25°C 4.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) (Continued) 40 MB89870 Series (Continued) ICCT vs. VCC ICCH vs. VCC ICCT (µA) 20 ICCH (µA) 2.0 TA = +25 ¡C 18 TA = +25 °C 1.8 16 1.6 14 1.4 12 1.2 10 1.0 8 0.8 6 0.6 4 0.4 2 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 2.0 6.5 VCC (V) 2.5 3.0 3.5 IA vs. AVCC FCH = 10 MHz TA = + 25 °C 4.5 160 3.5 140 3.0 120 2.5 100 2.0 80 1.5 60 1.0 40 0.5 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 0 2.0 6.5 AVCC (V) 5.5 6.0 6.5 VCC (V) TA = +25 °C 180 4.0 0 2.0 4.5 IR vs. AVR IR (µA) 200 IA (mA) 5.0 4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVR (V) (6) Pull-up Resistance RPULL vs. VCC RPULL (kΩ) 1000 TA = +25 °C 100 10 1 2 3 4 5 6 VCC (V) 41 MB89870 Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR 42 Meaning Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) MB89870 Series Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • • • • “–” indicates no change. dH is the 8 upper bits of operation description data. AL and AH must become the contents of AL and AH prior to the instruction executed. 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 43 MB89870 Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 44 MB89870 Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 45 MB89870 Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 46 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L F A ADDC ADDC A SUBC SUBC A MOV A XOR AND OR CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP MOV CMP DAS MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel 8 9 A B C D E F rel rel rel rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP 7 CLRB BBC MOVW MOVW MOVW XCHW dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 XCH XOR AND OR A, T A A SETC A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 CMP CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A MOV E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A DIVU SETI 9 4 8 RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89870 Series ■ INSTRUCTION MAP 47 MB89870 Series ■ MASK OPTIONS No. Part number MB89875 MB89P875 MB89PV870 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible 1 Pull-up resistors P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50 to P57 Specify by pin (in 2-pin unit for P10 to P17, and in 4-pin unit for P40 to P47) 2 Power-on reset selection With power-on reset Without power-on reset Selectable Selectable Fixed to with poweron reset 3 Selection of the oscillation stabilization time initial value 218/FCH (Approx. 26.2 ms) 217/FCH (Approx. 13.1 ms) 213/FCH (Approx. 0.8 ms) 24/FCH (Approx. 0 ms) Selectable Selectable Fixed to 218/FCH (Approx. 26.2 ms) 4 Selection either single- or dual-clock system Single clock Dual Clock Selectable Selectable Fixed to dual-clock system 5 Reset pin output With reset output Without reset output Selectable Selectable Fixed to with reset output Notes: • • • • Specify by pin (in 2-pin unit for P10 Fixed to without pullto P17, and in 4-pin up resistor unit for P40 to P47) Reset is input asynchronized with the internal clock whether with or without power-on reset. P30 to P37 should be set to without pull-up resistor when an A/D conveter is used. P10 to P17, P34 to P37 should be set to without pull-up resistor when an OP amp is used. P40 to P47 and P23 and P24 should be set to without pull-up resistor when an LCD controller/driver is used. ■ ORDERING INFORMATION Part number MB89875PFV MB89P875PFV 80-pin Plastic LQFP (FPT-80P-M05) MB89875PF MB89P875PF 80-pin Plastic QFP (FPT-80P-M06) MB89PV870CF 48 Package 80-pin Ceramic MQFP (MQP-80C-P01) Remarks MB89870 Series ■ PACKAGE DIMENSIONS 80-pin Plastic LQFP (FPT-80P-M05) +0.20 14.00±0.20(.551±.008)SQ 1.50 –0.10 +.008 .059 –.004 12.00±0.10(.472±.004)SQ 60 (Mounting height) 41 61 40 9.50 (.374) REF 13.00 (.512) NOM INDEX 80 21 LEAD No. 1 20 Details of "A" part "A" +0.08 +0.05 0.18 –0.03 0.50±0.08 (.0197±.0031) 0.127 –0.02 +.003 +.002 0.10±0.10 (STAND OFF) (.004±.004) .005 –.001 .007 –.001 0.50±0.20(.020±.008) 0.10(.004) 0 C Dimensions in mm (inches) 1995 FUJITSU LIMITED F80008S-2C-5 80-pin Plastic QFP (FPT-80P-M06) 10° 23.90±0.40(.941±.016) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 20.00±0.20(.787±.008) 64 41 65 40 14.00±0.20 (.551±.008) 12.00(.472) REF 17.90±0.40 (.705±.016) 16.30±0.40 (.642±.016) INDEX 80 25 "A" LEAD No. 1 24 0.80(.0315)TYP 0.35±0.10 (.014±.004) 0.16(.006) 0.15±0.05(.006±.002) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.30±0.40(.878±.016) C 1994 FUJITSU LIMITED F80010S-3C-2 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX 0 10° 0.80±0.20 (.031±.008) Dimensions in mm (inches) 49 MB89870 Series 80-pin Ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP +.016 .047 –.008 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) +0.40 1.20 –0.20 INDEX AREA 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.40(.724) REF INDEX 1.27±0.13 (.050±.005) 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 0.15±0.05 8.70(.343) (.006±.002) MAX C 50 1994 FUJITSU LIMITED M80001SC-4-2 Dimensions in mm (inches) MB89870 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9812 FUJITSU LIMITED Printed in Japan 51