Fujitsu MB89935B 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12541-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89930A Series
MB89935A/935B/P935A/PV930A
■ DESCRIPTION
The MB89930A series is a line of single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an
external interrupt.
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MB89600 Series CPU core
Maximum memory space : 64 Kbytes
Minimum execution time : 0.4 µs/10 MHz
Interrupt processing time : 3.6 µs/10 MHz
I/O ports : max. 21channels
21-bit timebase timer
8-bit PWM timer
8/16-bit capture timer/counter
10-bit A/D converter : 8 channels
UART
8-bit serial I/O
External interrupt 1 : 3 channels
External interrupt 2 : 8 channels
Wild Register : 2 bytes
(Continued)
■ PACKAGE
30-pin plastic SSOP
48-pin ceramic MQFP
(FPT-30P-M02)
(MQP-48C-P01)
MB89930A Series
(Continued)
• Low-power consumption modes ( sleep mode, and stop mode)
• SSOP-30 and MQFP-48 package
• CMOS Technology
■ PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
MB89935A
MB89935B
MB89P935A
MB89PV930A
Mass production product
(mask ROM product)
One-time PROM product
(for small-scale production)
Piggyback/evaluation product
(for development)
16 K × 8 bits
(internal mask ROM)
16 K × 8 bits
(internal PROM)
32 K × 8 bits
(external EPROM)
512 × 8 bits
RAM size
CPU functions
Ports
21-bit time
base timer
Number of instructions :
Instruction bit length :
Instruction length :
Data bit length :
Minimum execution time :
Interrupt processing time :
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 µs to 6.4 µs (10 MHz)
3.6 µs to 57.6 µs (10 MHz)
General-purpose I/O ports (CMOS) : 21 (also serve as peripherals )
(4 ports are also an N-ch open-drain type.)
21-bit Interrupt cycle : 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms with 10-MHz main clock
Watching timer
Reset generation cycle : 419.4 ms minimum with 10-MHz main clock
8-bit PWM timer
8-bit interval timer operation (square output capable, operating clock cycle :
0.4 µs , 3.2 µs, 6.4 µs, 25.6 µs)
8-bit resolution PWM operation (conversion cycle : 102.4 µs to 26.84 ms)
Count clock selectable between 8-bit and 16-bit timer/counter outputs
8/16-bit capture,
timer/counter
8-bit capture timer/counter × 1 channel + 8-bit timer or
16-bit capture timer/counter × 1 channel
Capable of event count operation and square wave output using external clock input with
8-bit timer 0 or 16-bit counter
UART
8-bit Serial I/O
12-bit PPG timer
Transfer data length : 6/7/8 bits
8 bits LSB first/MSB first selectable
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks : 0.8 µs, 6.4 µs, 25.6 µs)
Output frequency : Pulse width and cycle selectable
External interrupt 1
(wake-up function)
3 channels (Interrupt vector, request flag, request output enabled)
Edge selectable (Rising edge, falling edge, or both edges)
Also available for resetting stop/sleep mode (Edge detectable even in stop mode)
External interrupt 2
(wake-up function)
1 channel with 8 inputs (Independent L-level interrupt and input enable)
Also available for resetting stop/sleep mode (Level detectable even in stop mode)
(Continued)
2
MB89930A Series
(Continued)
Part number
Parameter
10-bit A/D converter
MB89935A
MB89935B
MB89P935A
MB89PV930A
10-bit precision × 8 channels
A/D conversion function (Conversion time : 15.2 µs/10 MHz)
Continuous activation by 8/16-bit timer/counter output or time-base timer counter
Wild Register
8-bit × 2
Standby mode
Sleep mode, and Stop mode
*Power supply
Voltage
2.2 V to 5.5 V
3.0 V to 5.5 V
2.7 V to 5.5 V
* : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89935A
MB89935B
MB89P935A
×*
FPT-30P-M02
×
MQP-48C-P01
: Available
MB89PV930A
×
×
× : Not available
* : Adapter for 48-pin to 30-pin conversion (manufactured by Sun Hayato Co., Ltd.)
Part number : 48QF-30SOP-8L
Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
2. Current Consumption
In the case of the MB89PV930A, add the current consumed by the EPROM which is connected to the top socket.
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using
options check section “■ MASK OPTIONS” Take particular care on the following points :
Options are fixed on the MB89PV930A and MB89P935A.
4. Difference between MB89935A and MB89935B
MB89935B is different from MB89935A in that the internal circuit and oscillator have been changed and the
radiated noise and current consumption while oscillation is active is reduced. For details of the characteristics
of current consumption, see “■ EXAMPLE CHARACTERISTICS”.
3
MB89930A Series
■ PIN ASSIGNMENT
(TOP VIEW)
P04/INT24
1
30
VCC
P05/INT25
2
29
P03/INT23/AN7
P06/INT26
3
28
P02/INT22/AN6
P07/INT27
4
27
P01/INT21/AN5
MOD0
5
26
P00/INT20/AN4
MOD1
6
25
P43/AN3
RST
7
24
P42/AN2
X0
8
23
P41/AN1
X1
9
22
P40/AN0
VSS
10
21
AVSS
P37/BZ/PPG
11
20
P50/PWM
P36/INT12
12
19
P30/UCK/SCK
P35/INT11
13
18
P31/UO/SO
P34/TO/INT10
14
17
P32/UI/SI
P33/EC
15
16
C
(FPT-30P-M02)
(Continued)
4
MB89930A Series
(Continued)
N.C.
N.C.
N.C.
N.C.
N.C.
48
47
46
45
44
43
42
41
40
39
38
37
P35/INT11
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
(TOP VIEW)
1
36
N.C.
P33/EC
2
35
P36/INT12
P32/UI/SI
3
34
P37/BZ/PPG
P31/UO/SO
4
33
X1
P30/UCK/SCK
5
32
X0
P40/AN0
6
31
RST
P41/AN1
7
30
MOD1
P42/AN2
8
29
MOD0
P43/AN3
9
28
P07/INT27
27
P06/INT26
26
P05/INT25
25
P04/INT24
P01/INT21/AN5
11
P02/INT22/AN6
12
60
59
58
57
56
55
54
53
77
78
79
80
49
50
51
52
10
69
70
71
72
73
74
75
76
N.C.
N.C.
N.C.
N.C.
N.C.
P50/PWM
N.C.
N.C.
N.C.
VCC
P03/INT23/AN7
AVSS
13
14
15
16
17
18
19
20
21
22
23
24
P00/INT20/AN4
68
67
66
65
64
63
62
61
P34/TO/INT10
(MQP-48C-P01)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
49
VPP
57
N.C.
65
O4
73
OE
50
A12
58
A2
66
O5
74
N.C.
51
A7
59
A1
67
O6
75
A11
52
A6
60
A0
68
O7
76
A9
53
A5
61
O1
69
O8
77
A8
54
A4
62
O2
70
CE
78
A13
55
A3
63
O3
71
A10
79
A14
56
N.C.
64
VSS
72
N.C.
80
VCC
N.C. : Internally connected. Do not use.
5
MB89930A Series
■ PIN DESCRIPTION
Pin No.
SSOP*1 MQFP*2
8
32
Pin name
X0
9
33
X1
5
29
MOD0
6
30
MOD1
7
31
Circuit
type
RST
P00/INT20/AN4
26 to 29 10 to 13
to P03/INT23/AN7
Function
A
Pins for connecting the crystal resonator for the main clock.
To use an eternal clock, input the signal to X0 and leave X1
open.
B
Memory access mode setting input pins.
Connect the pin directly to Vss.
C
Reset I/O pin.
This pin serves as an N-channel open-drain output with pullup resistor and a hysteresis input as well. The pin outputs the
“L” signal (optionally) in response to an internal reset request.
Also, it initializes the
internal circuit upon input of the “L” signal.
G
General-purpose CMOS I/O ports.
These pins also serve as an input (wake-up input) of external
interrupt 2 or as an A/D converter analog input. The input of
external interrupt 2 is a hysteresis input.
D
General-purpose CMOS I/O ports.
These pins also serve as an input (wake-up input) of external
interrupt 2. The input of external interrupt 2 is a hysteresis input.
1 to 4
25 to 28
P04/INT24 to
P07/INT27
19
5
P30/UCK/SCK
D
General-purpose CMOS I/O ports.
This pin also serves as the clock I/O pin for the UART or 8-bit
serial I/O. The resource is a hysteresis input.
18
4
P31/UO/SO
E
General-purpose CMOS I/O ports.
This pin also serves as the data output pin for the UART or 8bit serial I/O.
17
3
P32/UI/SI
D
General-purpose CMOS I/O ports.
This pin also serves as the data input pin for the UART or 8-bit
serial I/O. The resource is a hysteresis input.
D
General-purpose CMOS I/O ports.
This pin also serves as the external clock input pin for the 8/
16-bit capture timer/counter. The resource is a hysteresis input.
15
2
P33/EC
14
1
P34/TO/INT10
D
General-purpose CMOS I/O ports.
This pin also serves as the output pin for the 8/16-bit capture
timer/counter or as the input pin for external interrupt 1. The
resource is a hysteresis input.
13, 12
48, 35
P35/INT11,
P36/INT12
D
General-purpose CMOS I/O ports.
These pins also serve as the input pin for external
interrupt 1. The resource is a hysteresis input.
(Continued)
*1 : FPT-30P-M02
*2 : MQP-48C-P01
6
MB89930A Series
(Continued)
Pin No.
Pin name
Circuit
type
Function
34
P37/BZ/PPG
E
General-purpose CMOS I/O ports.
This pin also serves as the buzzer output pin or the 12-bit programmable pulse generator output.
20
24
P50/PWM
E
General-purpose CMOS I/O ports.
This pin also serves as the 8-bit PWM output pin. The pin is a
hysteresis input.
22 to 25
6 to 9
P40/AN0 to
P43/AN3
F
General-purpose CMOS I/O ports. These pins can also be
used as N-channel open-drain ports.
The pins also serve as A/D converter analog input pins.
30
18
VCC

Power supply pin
10
42
VSS

Power (GND) pin
21
14
AVSS

Power supply pin for the A-D converter.
Apply equal potential to this pin and the VSS pin.
16

C

Capacitance pin for regulating the power supply.
Connect an external ceramic capacitor of about 0.1 µF.

15,16,17
19,20,21
22,23,36
37,38,39
40,41,43
44,45,46
47
N.C.

Internally connected pins
Be sure to leave them open.
SSOP*1
MQFP*2
11
*1 : FPT-30P-M02
*2 : MQP-48C-P01
7
MB89930A Series
■ EXTERNAL EPROM PIN DESCRIPTION (MB89PV930A only)
8
Pin No.
Pin name
I/O
Function
49
VPP
O
“H” level output pin
50
51
52
53
54
55
58
59
60
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
61
62
63
O1
O2
O3
I
Data input pins
64
VSS
O
Power supply (GND) pin
65
66
67
68
69
O4
O5
O6
O7
O8
I
Data input pins
70
CE
O
ROM chip enable pin
Outputs “H” during standby.
71
A10
O
Address output pin
73
OE
O
ROM output enable pin
Outputs “L” at all times.
75
76
77
78
79
A11
A9
A8
A13
A14
O
Address output pins
80
VCC
O
EPROM power supply pin
56
57
72
74
N.C.

Internally connected pins
Be sure to leave them open.
MB89930A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Crystal oscillation type
X1
A
X0
Standby control signal
• Hysteresis input
B
P-ch
• At an output pull-up resister (P-ch) of approximately 50 kΩ/5.0 V
• Hysteresis input
C
N-ch
•
•
•
•
P-ch
D
CMOS output
CMOS input
Hysteresis input (Resource input)
Pull-up resistor optional
P-ch
N-ch
(Continued)
9
MB89930A Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• CMOS input
• Pull-up resistor optional
P-ch
P-ch
E
N-ch
P-ch
open-drain control
•
•
•
•
CMOS output
CMOS input
Analog input
N-ch open-drain output available
•
•
•
•
CMOS output
CMOS input
Hysteresis input (Resouce input)
Analog input
N-ch
F
Analog input
A/D enable
P-ch
P-ch
G
N-ch
Analog input
A/D enable
10
MB89930A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog input from exceeding the digital power supply (VCC) when the analog system
power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input terminals open may lead to permanent damage due to malfunction and latchup; pull up
or pull down the terminals through the resistors of 2 kΩ or more.
Make the unused I/O terminal in a state of output and leave it open and if it is in an input state, handle it with
the same procedure as the input terminals.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Treatment of Power Supply Pins on Microcontrollers with A/D Converters
Connect to be AVSS = VSS even if the A/D converters are not in use.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
7.
About the Wild Register Function
No wild register can be debugged on the MB89PV930A. For the operation check, test the MB89P935A installed
on a target system.
8. Program Execution in RAM
When the MB89PV930A is used, no program can be executed in RAM.
11
MB89930A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato
Co., Ltd.) listed below.
Package
Compatible socket part number
LCC-32
ROM-32LC-28DP-S
Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403
FAX (81) -3-5396-9106
3. Memory Space.
Normal operating mode
Address
0000H
I/O
0080H
RAM 512 B
0280H
Not available
Corresponding adresses on the
ROM programmer
Address
8000H
0000H
PROM 32 KB
FFFFH
EPROM 32 KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
12
MB89930A Series
■ PROGRAMMING TO THE OTPROM WITH MB89P935A
1. Memory Space
Normal operating mode
Address
0000H
I/O
0080H
RAM 512 B
0280H
Corresponding adresses on the
ROM programmer
Not available
Address
C000H
C000H
PROM 16 KB
PROM 16 KB
FFFFH
FFFFH
2. Programming to the OTPROM
To program to the OTPROM using an EPROM programmer AF200 (manufacturer : Yokogawa Digital Computer
Corp.) .
Inquiry : Yokogawa Digital Computer Corp. : TEL (81) -42-333-6224
Note : Programming to the OTPROM with MB89P935A is serial programming mode only.
3. Programming Adaptor for OTPROM
To program to the OTPROM using an EPROM programmer AF200, use the programming adapter (manufacturer
: Sun Hayato Co., Ltd.) listed below.
Adaptor socket : ROM3-FPT30M02-8L
Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403
FAX (81) -3-5396-9106
13
MB89930A Series
■ BLOCK DIAGRAM
X0
Main clock
oscillator
X1
Timebase timer
Clock controller
8 bit PWM
Reset circuit
CMOS I/O port
P00 / INT20 / AN4
4
to
P03 / INT23 / AN7
External
interrupt2
(wake-up)
4
UART
8 bit
serial I/O
10 bit A/D
Converter
AVSS
Port 4
P40 / AN0
4
to
P43 / AN3
P33 / EC
8/16 bit
capture timer/
counter
4
CMOS I/O port
(N-ch OD)
Exernal
interrupt 1
P30 / UCK / SCK
P31 / UO / SO
P32 / UI / SI
Port 3
8
UART prescaler
Internal bus
4
Port 0
P04 / INT24
to
P07 / INT27
P50 / PWM
Serial function switching
RST
Port 5
CMOS I/O port
3
P34 / TO / INT10
2
P35 / INT11
to
P36 / INT12
512 byte RAM
12 bit PPG
P37 / BZ / PPG
F2MC - 8 L CPU
Other pins
VCC, VSS, MOD1, MOD0, C
Buzzer output
16 Kbyte ROM
Wild register
14
CMOS I/O port
MB89930A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89930A series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89930A series is structured as illustrated below.
• Memory Space
MB89935A/B
MB89P935A
0000H
I/O
0080H
I/O
0080H
RAM 512 B
I/O
0080H
RAM 512 B
RAM 512 B
0100H
Register
0100H
Register
0100H
MB89PV930A
0000H
Register
0000H
0200H
0200H
0200H
0280H
0280H
0280H
Not available
Not available
Not available
8000H
C000H
C000H
ROM 16 KB
FFFFH
External EPROM
32 KB
PROM 16 KB
FFFFH
FFFFH
15
MB89930A Series
2. Registers
The MB89930A series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided :
Program counter (PC) :
A 16-bit register for indicating instruction storage positions
Accumulator (A) :
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is
used.
Index register (IX) :
A 16-bit register for index modification
Extra pointer (EP) :
A 16-bit pointer for indicating a memory address
Stack pointer (SP) :
A 16-bit register for indicating a stack area
Program status (PS) :
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bit
: Program counter
FFFDH
A
: Accumulator
Indeterminate
T
: Temporary accumulator
Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
PC
RP
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
: Program status
CCR
PS
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR) . (See the diagram below.)
• Structure of the Program Status Register
RP
PS
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9
R4
R3 R2 R1 R0
−
−
H-flag
I-flag
IL1,0
N-flag
Z-flag
× : Undefined
V-flag
C-flag
16
bit8
−
bit7
H
bit6
I
bit5
IL1
bit4
IL0
bit3
N
bit2
Z
bit1
bit0
V
C
CCR initial value
X011XXXXB
MB89930A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
Low OP codes
RP
"0"
Generated addresses
"0"
"0"
"0"
"0"
"0"
A15 A14 A13 A12 A11 A10
"0"
A9
"1"
A8
R4
A7
R3
A6
R2
R1
A5
R0
A4
b2
A3
A2
b1
A1
b0
A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I-flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”.
Cleared to “0” at the reset.
IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
0
0
0
1
1
0
2
1
1
3
N-flag :
Z-flag :
V-flag :
C-flag :
Interrupt level
1
High-low
High
Low = no interrupt
Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is cleared to “0”.
Set to “1” when an arithmetic operation results in 0. Cleared otherwise.
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the
overflow does not occur.
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
“0” otherwise. Set to the shift-out value in the case of a shift instruction.
17
MB89930A Series
The following general-purpose registers are provided :
General-purpose registers : An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 16 banks can be used on the MB89930A series. The bank currently in use is
indicated by the register bank pointer (RP) ..
• Register Bank Configuraiton
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
16 banks
Memory area
18
MB89930A Series
■ I/O MAP
Address
Register name
Register description
0000H
PDR0
Port 0 data register
0001H
DDR0
Port 0 data direction register
0002H to 00006H
Read/write
Initial value
R/W
X X XXXX X X
W
0 0 0 00 0 0 0
Vacancy
0007H
SYCC
System clock control register
R/W
1 - - MM 1 0 0
0008H
STBC
Standby control register
R/W
0 0 0 10 - - -
0009H
WDTC
Watchdog timer control register
W
0 - - - XX XX
000AH
TBTC
Timebase timer control register
R/W
0 0 - - - 0 0 0
R/W
X X XXXX X X
Vacancy
000BH
000CH
PDR3
Port 3 data register
000DH
DDR3
Port 3 data direction register
W
0 0 0 00 0 0 0
000EH
RSFR
Reset flag register
R
XXXX- - - -
000FH
PDR4
Port 4 data register
R/W
- - - - XX XX
0010H
DDR4
Port 4 data direction register
R/W
- - - - 0 0 0 0
0011H
OUT4
Port 4 output format register
R/W
- - - - 0 0 0 0
0012H
PDR5
Port 5 data register
R/W
- - - - - - - X
0013H
DDR5
Port 5 data direction register
R/W
- - - - - - - 0
0014H
RCR21
12-bit PPG control register 1
R/W
0 0 0 00 0 0 0
0015H
RCR22
12-bit PPG control register 2
R/W
- - 0 00 0 0 0
0016H
RCR23
12-bit PPG control register 3
R/W
0 - 0 00 0 0 0
0017H
RCR24
12-bit PPG control register 4
R/W
- - 0 00 0 0 0
0018H
BZCR
Buzzer register
R/W
- - - - - 0 0 0
0019H
TCCR
Capture control register
R/W
0 0 0 00 0 0 0
001AH
TCR1
Timer 1 control register
R/W
0 0 0 00 0 0 0
001BH
TCR0
Timer 0 control register
R/W
0 0 0 - 0 0 0 0
001CH
TDR1
Timer 1 data register
R/W
X X XXXX X X
001DH
TDR0
Timer 0 data register
R/W
X X XXXX X X
001EH
TCPH
Capture data register H
R
X X XXXX X X
001FH
TCPL
Capture data register L
R
X X XXXX X X
0020H
TCR2
Timer output control register
R/W
- - - - - - 0 0
R/W
0 - 0 00 0 0 0
W
X X XXXX X X
R/W
0 0 0 00 0 0 0
Vacancy
0021H
0022H
CNTR
PWM control register
0023H
COMR
PWM compare register
00024H
EIC1
External interrupt 1 Control register 1
(Continued)
19
MB89930A Series
Address
Register name
0025H
EIC2
Register description
External interrupt 1 Control register 2
0026H
Read/write
Initial value
R/W
- - - - 0 0 0 0
Vacancy
0027H
0028H
SMC
Serial mode control register
R/W
0 0 0 00 - 0 0
0029H
SRC
Serial rate control register
R/W
- - 0 11 0 0 0
002AH
SSD
Serial status and data register
R/W
0 0 1 00 - 1 X
SIDR
Serial input data register
R
X X XXXX X X
SODR
Serial output data register
W
X X XXXX X X
R/W
- - - - 0 0 1 0
002BH
002CH
UPC
Clock division selection register
002DH to 0002FH
Vacancy
0030H
ADC1
A/D converter control register 1
R/W
- 0 0 00 0 0 0
0031H
ADC2
A/D converter control register 2
R/W
- 0 0 00 0 0 1
0032H
ADDH
A/D converter data register H
R/W
- - - - - - XX
0033H
ADDL
A/D converter data register L
R/W
X X XXXX X X
0034H
ADEN
A/D enable register
R/W
0 0 0 00 0 0 0
0035H
Vacancy
0036H
EIE2
External interrupt 2 control register1
R/W
0 0 0 00 0 0 0
0037H
EIF2
External interrupt 2 control register2
R/W
- - - - - - - 0
Vacancy
0038H
0039H
SMR
Serial mode register
R/W
0 0 0 00 0 0 0
003AH
SDR
Serial data register
R/W
X X XXXX X X
003BH
SSEL
Serial function switching register
R/W
- - - - - - - 0
003CH to 003FH
Vacancy
0040H
WRARH0
Upper-address setting register
R/W
X X XXXX X X
0041H
WRARL0
Lower-address setting register
R/W
X X XXXX X X
0042H
WRDR0
Data setting register 0
R/W
X X XXXX X X
0043H
WRARH1
Upper-address setting register
R/W
X X XXXX X X
0044H
WRARL1
Lower-address setting register
R/W
X X XXXX X X
0045H
WRDR1
Data setting register 1
R/W
X X XXXX X X
0046H
WREN
Address comparison EN registor
R/W
X X XXXX 0 0
0047H
WROR
Wild-register data test register
R/W
- - - - - - 0 0
R/W
0 0 0 00 0 0 0
0048H to 006FH
0070H
Vacancy
PUL0
Port-0 pull-up setting register
(Continued)
20
MB89930A Series
(Continued)
Address
Register name
Register description
Read/write
Initial value
0071H
PUL3
Port-3 pull-up setting register
R/W
0 0 0 00 0 0 0
0072H
PUL5
Port-5 pull-up setting register
R/W
- - - - - - - 0
0073H to 007AH
Vacancy
007BH
ILR1
Interrupt level setting register1
W
1 1 1 11 1 1 1
007CH
ILR2
Interrupt level setting register2
W
1 1 1 11 1 1 1
007DH
ILR3
Interrupt level setting register3
W
1 1 1 11 1 1 1
007EH
ILR4
Interrupt level setting register4
W
1 1 1 11 1 1 1
007FH
ITR
Interrupt test register
Not available
- - - - - - 0 0
- : Unused, X : Undefined, M : Set using the mask option
Note : Do not use vacancies.
21
MB89930A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS − 0.3
VSS + 6.0
V
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 6.0
V
IOL1

20
mA
Pins P40 to P43
IOL2

10
mA
Pins excluding P40 to P43
“L” level average output current
IOLAV

4
mA
Average value (operating
current × operating rate)
“L” level total maximum output current
ΣIOL

100
mA
“H” level maximum output current
IOH

−10
mA
“H” level average output current
IOHAV

−2
mA
“H” level total maximum output current
ΣIOH

−50
mA
Power consumption
Pd

200
mW
Operating temperature
Ta
−40
+85
°C
Tstg
−55
+150
°C
Power supply voltage
“L” level maximum output current
Storage temperature
Average value (operating
current × operating rate)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
MB89930A Series
2. Recommended Operating Conditions
Value
Symbol
Parameter
Unit
Remarks
Min.
Max.
2.2
5.5
V
Normal operation assurance range
MB89935A/B
1.5
6.0
V
Retains the RAMstate in stop mode
VIH
0.7 VCC
VCC + 0.3
V
P00 to P07, P30 to P37, P40 to P43, P50,
UI/SI
VIHS
0.8 VCC
VCC + 0.3
V
MOD0/1, RST, EC, INT20 to INT27,
UCK/SCK, INT10 to INT12
VIL
VSS − 0.3
0.3 VCC
V
P00 to P07, P30 to P37, P40 to P43,
P50, UI/SI
VILS
VSS − 0.3
0.2 VCC
V
MOD0/1, RST, EC, INT20 to INT27,
UCK/SCK, INT10 to INT12
Open-drain output pin
application voltage
VD
VSS − 0.3
VCC + 0.3
V
P40 to P43
Operating temperature
Ta
−40
+85
°C
Power supply voltage
VCC
“H” level input voltage
“L” level input voltage
6
Operating voltage (V)
5
Analog accuracy assurance range
4
Operation assurance range
3
2
: Area is assured only for the MB89935A/B
1
0
1
2
3
5
6
7
4
Operating Frequency (MHz)
8
9
10
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
23
MB89930A Series
3. DC Characteristics
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, FCH = 10 MHz (External clock) , Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
VIH
P00 to P07,
P30 to P37, P40 to P43,
P50 , UI/SI
Value
Unit
Remarks
Min.
Typ.
Max.

0.7 VCC

VCC + 0.3
V
VIHS
RST, MOD0/1,
UCK/SCK, EC,
INT20 to INT27,
INT10 to INT12

0.8 VCC

VCC + 0.3
V
VIL
P00 to P07,
P30 to P37, P40 to P43,
P50 , UI/SI

VSS − 0.3

0.3 VCC
V
VILS
RST, MOD0/1,
UCK/SCK, EC,
INT20 to INT27,
INT10 to INT12

VSS − 0.3

0.2 VCC
V
Open-drain
output pin
application
voltage
VD
P40 to P43

VSS − 0.3

VCC + 0.3
V
“H” level
output voltage
VOH
P00 to P07, P30 to P37,
IOH = −4.0 mA
P40 to P43, P50
2.4


V
VOL1
P00 to P07, P30 to P37,
IOL = 4.0 mA
P50, RST


0.4
V
VOL2
P40 to P43


0.4
V
P00 to P07, P30 to P37,
P40 to P43, P50 ,
0.45 V < VI < VCC
MOD0/1


±5
Without
µA pull-up
resistor
P00 to P07, P30 to P37,
VI = 0.0 V
P40 to P43, P50
25
50
100
kΩ

8
12
mA
MB89935A/
B

6
9
mA
MB89P935
A

10
15
mA
MB89935A/
B

8
12
mA
MB89P935
A

4
6
mA
MB89935A/
B

3
5
mA
MB89P935
A
“H” level input
voltage
“L” level input
voltage
“L” level
output voltage
Input leakage
current
Pull-up
resistance
ILI
RPULL
ICC
Power supply
current
VCC
ICCS
Normal operation
mode
(External clock,
highest gear
speed)
Sleep mode
(External clock,
highest gear
speed)
IOL = 12.0 mA
When A/D
converter stops
When A/D
converter starts
When A/D
converter stops
(Continued)
24
MB89930A Series
(Continued)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, FCH = 10 MHz (External clock) , Ta = −40 °C to +85 °C)
Parameter
Symbol
Power supply
current
ICCH
Input
capacitance
CIN
Pin name
VCC
Stop mode
Ta = +25 °C
(External clock)
Other than AVSS, VCC,
VSS
Condition
When A/D
converter stops

Value
Unit
Remarks
1
µA
MB89935A/
B

10
µA
MB89P935
A
10

pF
MB89P935
A
Min.
Typ.
Max.




25
MB89930A Series
4. AC Characteristics
(1) Reset Timing
(AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Condition
tZLZH

RST “L” pulse width
Value
Min.
Max.
16 tHCYL

Unit
Remarks
ns
tHCYL : 1 oscillating clock cycle time
tZLZH
RST
0.2 VCC
0.2 VCC
Note : When the power-on reset option is not on, leave the external reset on until oscillation becomes stable.
(2) Power-on Reset
(AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Power supply rising time
tR
Power supply cutoff time
tOFF
Condition

tR
Value
Unit
Min.
Max.

50
ms
1

ms
Remarks
Due to repeated operations
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
Note : The supply voltage must be set to the minimum value required for operation within the prescribed default
oscillation settling time.
26
MB89930A Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, Ta = –40°C to +85°C)
Symbol
Parameter
Condition
Value
Min.
Max.
Unit
Clock frequency
FCH
1
10
MHz
Clock cycle time
tXCYL
100
1000
ns
Input clock pulse width
tWH
tWL
20

ns
Input clock rising/falling time
tCR
tCF

10
ns

Remarks
• X0 and X1 Timing and Conditions
tXCYL
tWH
tCR
tWL
tCF
X0
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Main Clock Conditions
When a crystal or ceramic
resonator is used
X0
When an exernal
clock is used
X1
X0
X1
open
(4) Instruction Cycle.
Parameter
Symbol
Value (typical)
Unit
Instruction cycle
(minimum execution time)
tINST
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
Remarks
tINST = 0.4 µs when operating
at FCH = 10 MHz (4/FCH)
27
MB89930A Series
(5) Recommended Resonator Manufactures
• Sample application of ceramic resonator
X0
X1
R
C1
Resonator
manufacturer
Murata
Mfg. Co., Ltd.
C2
Frequency
(MHz)
C1
C2
R
CSTS0400MG06
4.00
Built-in
Built-in
330 Ω
CSTCC4.00MG0H6
4.00
Built-in
Built-in
330 Ω
CSTS0800MG06
8.00
Built-in
Built-in
Not required
CSTCC8.00MG0H6
8.00
Built-in
Built-in
Not required
CST10.0MTW
10.00
Built-in
Built-in
Not required
CSTCC10.0MG0H6
10.00
Built-in
Built-in
Not required
Resonator
Inquiry : Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc. : TEL1-404-436-1300
• Murata Europe Management GmbH : TEL 49-911-66870
• Murata Electronics Singapore (Pte.) : TEL 65-758-4233
28
MB89930A Series
(6) Peripheral Input Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
INT10 to INT12,
INT20 to INT27, EC
Value
Unit
Min.
Max.
2 tINST*

µs
2 tINST*

µs
Remarks
* : For information on tINST see “ (4) Instruction Cycle”.
tIHIL
tILIH
INT10 to INT12,
INT20 to INT27, EC
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Peripheral input “H” noise limit
tIHNC
Peripheral input “L” noise limit
tILNC
Pin name
INT10 to INT12, EC
tIHNC
INT10 to INT12, EC
Value
Unit
Min.
Typ.
Max.
7
15
23
ns
7
15
23
ns
Remarks
tILNC
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
29
MB89930A Series
(7) UART, Serial I/O Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK/SCK
UCK/SCK ↓ → SO time
tSLOV
Valid SI → UCK/SCK↑
Parameter
Condition
Value
Max.
2 tINST*

µs
−200
200
ns
tIVSH
UCK/SCK, SO Internal shift
UCK/SCK, SI clock mode
1/2 tINST*

µs
UCK/SCK ↑ → Valid SI hold time
tSHIX
UCK/SCK, SI
1/2 tINST*

µs
Serial clock “H” pulse width
tSHSL
UCK/SCK
tINST*

µs
Serial clock “L” pulse width
tSLSH
UCK/SCK
tINST*

µs
UCK/SCK ↓ → SO time
tSLOV
UCK/SCK, SO
0
200
ns
Valid SI → UCK/SCK
tIVSH
UCK/SCK, SI
1/2 tINST*

µs
UCK/SCK ↑ → Valid SI hold time
tSHIX
UCK/SCK, SI
1/2 tINST*

µs
External
shift clock
mode
* : For information on tinst, see “ (4) Instruction Cycle”.
• Internal Shift Clock Mode
tSCYC
2.4 V
UCK/SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SO
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
SI
• External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
UCK/SCK
0.2 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
30
Unit Remarks
Min.
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
MB89930A Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
Parameter
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)
Value
Symbol
Typ.
Max.


10
bit
−5.0

+5.0
LSB
−3.0

+3.0
LSB
−2.5

+2.5
LSB
Resolution
Total error

Linearity error
Differential linearity error
Zero transition voltage
VOT
Full-scale transition voltage
VFST
Unit
Min.
AVSS − 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB
V
VCC − 6.5 LSB
VCC − 1.5 LSB
VCC + 2.0 LSB
V


38 tINST*
µs
A/D mode conversion time
Remarks
Analog port input current
IAIN


10
µA
Analog input voltage range

0

VCC
V
* : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”
(2) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics
• Differential linearity error (unit : LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit : LSB)
The difference between theoretical and actual conversion values
Theoretical I/O characteristics
Total error
VFST
3FF
3FF
3FE
3FE
1.5 LSB
3FD
Digital output
Digital output
3FD
004
003
VOT
{1 LSB × N + 0.5 LSB}
004
VNT
Actual conversion
value
003
1 LSB
002
Actual conversion
value
002
001
001
0.5 LSB
AVSS
VCC
Theoretical value
AVSS
Analog input
1 LSB =
VFST − VOT
1022
VCC
Analog input
(V)
Total error of digital output N =
VNT − {1 LSB × N + 0.5 LSB}
1 LSB
31
MB89930A Series
Zero transition error
Full-scale transition error
Theoretical value
004
Actual conversion value
3FF
Actual conversion value
Digital output
Digital output
003
002
Theoretical
conversion
value
Actual conversion
value
3FE
VFST
(Measured
value)
3FD
001
VOT
(Measured value)
Actual conversion
value
3FC
VCC
Analog input
Analog input
Linearity error
Differential linearity error
3FF
Actual conversion value
3FE
{1 LSB × N + VOT}
Theoretical conversion value
N+1
Actual conversion value
3FD
VFST
(Measured
value)
Digital output
Digital output
AVSS
VNT
004
Actual conversion
value
003
002
001
Theoretical conversion
value
AVSS
N
N−1
N−2
VOT (Measured value)
VCC
Actual conversion
value
VCC
Analog input
VNT − {1 LSB × N + VOT}
1 LSB
Differential linearity of error digital output N =
32
VNT
AVSS
Analog input
Linearity error of digital output N =
V (N + 1) T
V (N + 1) T − VNT
1 LSB
−1
MB89930A Series
(3) Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89930A series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for 16 instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 4 kΩ) .
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
• Analog Input Equivalent Circuit
Analog input pin
Sample hold circuit
Comparator
R
If the analog input
impedance is higher than
4 kΩ, it is recommended to
connect an external
capacitor of approx. 0.1 µF.
C
Close for 16 instruction cycles after
activating A/D conversion
Analog channel selector
• Error
The smaller the | VCC − AVSS |, the greater the error would become relatively.
33
MB89930A Series
■ EXAMPLE CHARACTERISTICS
• Power supply current (MB89935A/MB89935B/MB89P935A : 8 MHz ( when FAR resonator [NM8000] is used)
MB89935A
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
MB89935B
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
MB89935A/MB89935B/
MB89P935A
MB89P935A/
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
FAR : [NM8000]
ICC (mA)
(FCH = 8 MHz, Ta = +25 °C)
8
ICC (mA)
(FCH = 8 MHz, Ta = +25 °C)
8
ICC (mA)
ICC (mA)
(FCH = 8 MHz, Ta = +25 °C)
(FCH = 8 MHz, Ta = +25 °C)
8
2
6
6
6
ICC1
(gear : 4 divide)
ICC1
(gear : 4 divide)
4
4 ICC1
(gear : 4 divide)
4
ICC2
(gear : 64 divide)
2
ICC2
(gear : 64 divide)
2
1
MB89935A
MB89P935A
2
ICC2 (gear : 64 divide)
0
0
MB89935B
0
0
3
4
5
VCC (V)
6
3
4
5
VCC (V)
6
3
4
5
VCC (V)
6
3
4
5
VCC (V)
6
FAR : [NM8000]
External clock
MB89935A
Sleep mode
(ICCs1 − VCC, ICCs2 − VCC)
MB89935B
Sleep mode
(ICCs1 − VCC, ICCs2 − VCC)
MB89935A/MB89935B/
MB89P935A
MB89P935A/
Sleep mode
(ICCs1 − VCC, ICCs2 − VCC)
FAR : [NM8000]
ICCs (mA)
(FCH = 8 MHz, Ta = +25 °C)
4
ICCs (mA)
(FCH = 8 MHz, Ta = +25 °C)
4
ICCs (mA)
ICCs (mA)
(FCH = 8 MHz, Ta = +25 °C)
(FCH = 8 MHz, Ta = +25 °C)
4
2
3
3
3
ICCs1
(gear : 4 divide)
2
2
1
ICCs2
(gear : 64 divide)
ICCs1
(gear : 4 divide)
2
ICCs1
(gear : 4 divide)
MB89935A
1
MB89P935A
1
ICCs2
(gear : 64 divide)
0
0
3
4
5
VCC (V)
6
FAR : [NM8000]
External clock
34
1
ICCs2
(gear : 64 divide)
0
3
4
5
VCC (V)
6
MB89935B
0
3
4
5
VCC (V)
6
3
4
5
VCC (V)
6
MB89930A Series
• MB89935A/MB89935B/MB89P935A : 4 MHz (when FAR resonator [NM4000] used)
MB89935A/MB89935B/
MB89P935A/
MB89935A
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
MB89935B
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
MB89P935A
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
ICC (mA)
(FCH = 4 MHz, Ta = +25 °C)
4
ICC (mA)
(FCH = 4 MHz, Ta = +25 °C)
4
ICC (mA)
ICC (mA)
(FCH = 4 MHz, Ta = +25 °C)
(FCH = 4 MHz, Ta = +25 °C)
4
2
3
3
FAR : [NM4000]
3
ICC1
(gear : 4 divide)
ICC1
(gear : 4 divide)
ICC1
(gear : 4 divide)
2
2
2
1
MB89935A
1
ICC2
(gear : 64 divide)
0
ICC2
(gear : 64 divide)
1
0
3
4
5
VCC (V)
6
MB89P935A
1
ICC2
(gear : 64 divide)
0
3
4
5
VCC (V)
6
3
4
5
VCC (V)
MB89935B
0
6
3
4
5
VCC (V)
6
FAR : [NM4000]
External clock
MB89935A
Seep mode
(ICCs1 − VCC, ICCs2 − VCC)
MB89935B
Seep mode
(ICCs1 − VCC, ICCs2 − VCC)
MB89P935A
Seep mode
(ICCs1 − VCC, ICCs2 − VCC)
MB89935A/MB89935B/
MB89P935A/
FAR : [NM4000]
ICCs (mA)
(FCH = 4 MHz, Ta = +25 °C)
4
ICCs (mA)
(FCH = 4 MHz, Ta = +25 °C)
4
ICCs (mA)
ICC (mA)
(FCH = 4 MHz, Ta = +25 °C)
(FCH = 4 MHz, Ta = +25 °C)
4
2
3
3
3
2
2
2
ICCs1
(gear : 4 divide)
ICCs1
(gear : 4 divide)
1
1
ICCs2
(gear : 64 divide)
0
4
5
VCC (V)
6
MB89935A
MB89P935A
1
0
3
1
ICCs1
(gear : 4 divide)
3
ICCs2
(gear : 64 divide)
4
5
6
VCC (V)
ICCs2
(gear : 64 divide)
0
3
4
5
VCC (V)
6
MB89935B
0
3
4
5
VCC (V)
6
FAR : [NM4000]
External clock
35
MB89930A Series
• MB89935A/MB89935B : 10 MHz (when external clock is used)
MB89935A/B
Normal operation mode
(ICC1 − VCC, ICC2 − VCC)
MB89935A/B
Normal operation mode
(ICCs1 − VCC, ICCs2 − VCC)
ICC (mA)
(FCH = 10 MHz, Ta = +25 °C)
8
6
MB89935A/B
Normal operation mode
(ICCh − VCC)
ICCs (mA)
(FCH = 10 MHz, Ta = +25 °C)
4
3
ICCh (µA)
(FCH = 10 MHz, Ta = +25 °C)
0.4
0.3
ICC1
(gear : 4 divide)
4
2
0.2
ICCs1
(gear : 4 divide)
2
1
ICC2
(gear : 64 divide)
0.1
ICCs2
(gear : 64 divide)
0
0
0
3
4
5
VCC (V)
6
0
0
3
4
5
VCC (V)
6
MB89935A/MB89935B
Stop mode (ICCh − VCC)
10
6
8
6
6
4
4
2
2
0
25
50
75
100
125
150
(FCH = 10 MHz, VCC = 5.5 V)
10
8
Temperature (°C)
36
4
5
VCC (V)
ICCh (µA)
(FCH = 10 MHz, VCC = 5.5 V)
−25
3
MB89P935A
Stop mode (ICCh − VCC)
ICCh (µA)
0
−50
0
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
MB89930A Series
(2) “L” level output voltage
VOL vs. IOL1
VOL vs. IOL2
VCC = 2.0 V
VOL (V)
0.6
VCC = 2.0 V
VOL (V)
0.6
0.5
0.5
VCC = 2.5 V
0.4
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 6.0 V
0.3
VCC = 2.5 V
0.4
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 6.0 V
0.3
0.2
0.2
0.1
0.1
0.0
VCC = 3.0 V
0.0
1
2
3
4
5
6
4
6
8
IOL1 (mA)
10
12
14
16
IOL2 (mA)
(3) “H” level output voltage
(VCC − VOH) vs. IOH
VCC − VOH (V)
0.8
VCC = 2.0 V
0.7
VCC = 2.5 V
0.6
0.5
VCC = 3.0 V
0.4
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 6.0 V
0.3
0.2
0.1
0.0
−1
−2
−3
−4
−5
−6
IOH (mA)
37
MB89930A Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1
Symbol
dir
off
ext
#vct
#d8
#d16
dir: b
rel
@
A
AH
AL
T
TH
TL
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
×
(×)
(( × ))
Instruction Symbols
Meaning
Direct address (8 bits)
Offset (8 bits)
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
38
MB89930A Series
Table 2
Mnemonic
Transfer Instructions (48 instructions)
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Note
During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
39
MB89930A Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
(Continued)
40
MB89930A Series
(Continued)
Mnemonic
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
~
#
Operation
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
41
L
42
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
9
A
B
C
D
E
F
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
R7
R6
R5
R4
R3
R2
R1
R0
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
rel
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
8
A
A
SETC
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
CMPW
CMP
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
7
F
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6
dir: 6,rel A,@IX +d @IX +d,A
IX,#d16
A,IX
E
6
D
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
C
5
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
A
A
DIVU
SETI
9
4
8
RORC
7
3
6
ROLC
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89930A Series
■ INSTRUCTION MAP
MB89930A Series
■ MASK OPTIONS
Part number
MB89935A/B
Specifying procedure
Specify when ordering masking
1
Selection of initial value of main
clock oscillation settling time*
(with FCH = 10 MHz)
01 : 214/FCH (Approx.1.63 ms)
10 : 217/FCH (Approx.13.1 ms)
11 : 218/FCH (Approx.26.2 ms)
Selectable
Fixed to 218/FCH
(Approx. 26.2 ms)
Fixed to 218/FCH
(Approx. 26.2 ms)
2
Power-on reset selection
With power-on reset
Without power-on reset
Selectable
Available
Available
3
Reset pin output
With reset output
Without reset output
Selectable
With reset output
With reset output
No
MB89P935A
MB89PV930A
Setting not possible
FCH : Main clock oscillation frequency
* : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set
■ ORDERING INFORMATION
Part number
MB89935APFV
MB89935BPFV
MB89P935APFV
MB89PV930ACFV
Package
Remarks
30-pin Plastic SSOP
(FPT-30P-M02)
48-pin Ceramic MQFP
(MQP-48C-P01)
43
MB89930A Series
■ PACKAGE DIMENSIONS
30-pin plastic LQFP
(FPT-30P-M02)
* : This dimension does not include resin protrusion.
+0.20
* 9.70±0.10(.382±.004)
INDEX
0.65±0.12(.0256±.0047)
1.25 –0.10
+.008 (Mounting height)
.049 –.004
0.10(.004)
5.60±0.10
(.220±.004)
+0.10
7.60±0.20
(.299±.008)
6.60(.260)
NOM
"A"
+0.05
0.22 –0.05
0.15 –0.02
+.004
–.002
.006 –.001
.009
+.002
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
9.10(.358)REF
0
C
10°
0.50±0.20
(.020±.008)
1994 FUJITSU LIMITED F30003S-2C-3
Dimensions in mm (inches)
(Continued)
44
MB89930A Series
(Continued)
48-pin ceramic MQFP
(MQP-48C-P01)
17.20(.677)TYP
PIN No.1 INDEX
15.00±0.25
(.591±.010)
14.82±0.35
(.583±.014)
1.50(.059)TYP
8.80(.346)REF
1.00(.040)TYP
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
+0.13
10.92 –0.0
+.005
.430 –0
7.14(.281) 8.71(.343)
TYP
TYP
PAD No.1 INDEX
0.30(.012)TYP
+0.45
4.50(.177)TYP
1.10 –0.25
+.018
.043 –.010
0.40±0.08
(.016±.003)
0.60(.024)TYP
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches)
45
MB89930A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0010
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.