Fujitsu MB89P185PFM-104 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12404-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89180 Series
MB89181/182/183/P185/PV180
■ DESCRIPTION
The MB89180 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, timers, a serial interface, a remote control
transmission output, external interrupts, an LCD controller/driver, and a watch prescaler.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
•
•
•
•
•
•
•
•
•
F2MC-8L family CPU core
Dual-clock control system
High speed operation at low voltage
Minimum execution time: 0.95 µs/2.7 V, 1.33 µs/2.2 V
I/O ports: max. 64 channels
21-bit time-base timer
8/16-bit timer/counter: 1 channel (8 bits × 2 channels)
8-bit serial I/O: 1 channel
LCD controller/driver: max. 32 segments outputs × 4 commons
(Continued)
■ PACKAGE
64-pin Plastic QFP
64-pin Plastic QFP
64-pin Plastic SQFP
(FPT-64P-M06)
(FPT-64P-M09)
(FPT-64P-M03)
64-pin Ceramic MQFP
(MQP-64C-P01)
MB89180 Series
(Continued)
• Remote control transmission output
• Buzzer output
• Watch prescaler (15 bits)
• External interrupts (wake-up function)
Four independent channels with edge detection function plus eight “L” level-interrupt channels
■ PRODUCT LINEUP
Part number
Parameter
MB89181
MB89182
MB89183
Classification
Mass production products
(mask ROM products)
ROM size
4 K × 8 bits
(internal mask
ROM)
6 K × 8 bits
(internal mask
ROM)
RAM size
128 × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
Ports
I/O ports (N-ch open drain):
8 K × 8 bits
(internal mask
ROM)
MB89P185
MB89PV180
Piggyback/
evaluation
One-time
product (for
PROM product
evaluation and
development)
16K × 8 bits
(internal PROM,
programming
with generalpurpose
EPROM
programmer)
32 K × 8 bits
(external ROM)
256 × 8 bits
512 × 8 bits
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.95 µs/4.2 MHz
8.57 µs/4.2 MHz
8 (6 ports also serve as peripherals, and 3 ports are a
heavy-current drive type.)
Output ports (N-ch open drain): 18 (16 ports also serve as segment pins*1, and 2 ports
serve as booster capacitor connection pins.)
I/O ports (CMOS):
16 (12 ports also serve as an external interrupt, and
8 ports also serve as segment pins*1.)
Output port (CMOS):
1 (also serves as a remote control pin.)
Total:
43 (max.)
8/16-bit timer/
counter
8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel
8-bit serial I/O
8 bits
LSB first/MSB first selectability
LDC controller/driver
External interrupt
(wake-up function)
Common output:
4 (COM2 and COM3 also serve as output ports.)
Segment output:
32 (max.)*1
Bias power supply pins:
3
LCD display RAM size:
32 × 4 bits
Dividing resistor for LCD driving (external resistor selectability)
4 channels (edge selection, also serve as segment pins.)*1
8 channels (only for a level interrupt)
(Continued)
2
MB89180 Series
(Continued)
Part number
MB89181
Parameter
Buzzer output
MB89182
MB89183
Standby mode
1 (pulse width and cycle are selectable by software.)
Sleep mode, stop mode, and watch mode
Process
EPROM for use
MB89PV180
1 (7 frequency types are selectable by software.)
Remote control
transmission output
Operating voltage*
MB89P185
CMOS
2
2.7 V to 6.0 V
3
2.2 V* to 6.0 V

MBM27C256A-20TV
(LCC package)
*1: Selected by the mask option. See section “■ Mask Options.”
*2: Varies with conditions such as the operating frequency and the connected ICE. (See section “■ Electrical
Characteristics.”)
*3: The operation at less than 2.2 V is assured separately. Please contact FUJITSU LIMITED.
3
MB89180 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89181
MB89182
MB89183
Package
MB89P185
MB89PV180
FPT-64P-M06
×
FPT-64P-M09
×
×
FPT-64P-M03
MQP-64C-P01
: Available
×
×
×
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89181, addresses 0140H and later of the register bank cannot be used. On the MB89182, MB89183,
and MB89P185 microcontrollers, addresses 0180H and later of the register bank cannot be used.
• On the MB89P185, addresses BFF0H to BFF5H comprise the option setting area, option settings can be read
by reading these addresses.
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV180, add the current consumed by the EPROM which is connected to the top
socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.” )
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following point:
• Options are fixed on the MB89PV180 except the segment output selection.
4
MB89180 Series
■ PIN ASSIGNMENT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2/P31
COM3/P32
VCC
V3
V2
V1
P30/RCO
P00/INT20
P01/INT21
P02/INT22
(Top view)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21 *2
P22/TO
P23/SI
P24/SO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
*1
*1
*1
*1
*1 SEG20/P54
*1 SEG21/P55
*1 SEG22/P56
*1 SEG23/P57
SEG24/INT10/P10
SEG25/INT11/P11
SEG26/INT12/P12
VSS
SEG27/INT13/P13
*1 SEG28/P14
*1 SEG29/P15
*1 SEG30/P16
*1 SEG31/P17
*2 BUZ/P27
*2 P26
SCK/P25
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
SEG4
SEG5
SEG6
SEG7
SEG8/P40
SEG9/P41
SEG10/P42
SEG11/P43
SEG12/P44
SEG13/P45
SEG14/P46
SEG15/P47
SEG16/P50
SEG17/P51
SEG18/P52
SEG19/P53
(FPT-64P-M03)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
5
MB89180 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2/P31
COM3/P32
VCC
V3
V2
V1
P30/RCO
P00/INT20
P01/INT21
P02/INT22
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
*1
*1
*1
*1
*1 SEG20/P54
*1 SEG21/P55
*1 SEG22/P56
*1 SEG23/P57
SEG24/INT10/P10
SEG25/INT11/P11
SEG26/INT12/P12
VSS
SEG27/INT13/P13
*1 SEG28/P14
*1 SEG29/P15
*1 SEG30/P16
*1 SEG31/P17
*2 BUZ/P27
*2 P26
SCK/P25
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SEG4
SEG5
SEG6
SEG7
*1 SEG8/P40
*1 SEG9/P41
*1 SEG10/P42
*1 SEG11/P43
*1 SEG12/P44
*1 SEG13/P45
*1 SEG14/P46
*1 SEG15/P47
*1 SEG16/P50
*1 SEG17/P51
*1 SEG18/P52
*1 SEG19/P53
(FPT-64P-M09)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
6
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21 *2
P22/TO
P23/SI
P24/SO
MB89180 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
SEG2
SEG1
SEG0
COM0
COM1
COM2/P31
COM3/P32
VCC
V3
V2
V1
P30/RCO
P00/INT20
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21*2
P22/TO
P23/SI
P24/SO
P25/SCK
*1
*1
*1
*1
*1 SEG22/P56
*1 SEG23/P57
SEG24/INT10/P10
SEG25/INT11/P11
SEG26/INT12/P12
VSS
SEG27/INT13/P13
*1 SEG28/P14
*1 SEG29/P15
*1 SEG30/P16
*1 SEG31/P17
*2 BUZ/P27
*2 P26
20
21
22
23
24
25
26
27
28
29
30
31
32
SEG3
SEG4
SEG5
SEG6
SEG7
*1 SEG8/P40
*1 SEG9/P41
*1 SEG10/P42
*1 SEG11/P43
*1 SEG12/P44
*1 SEG13/P45
*1 SEG14/P46
*1 SEG15/P47
*1 SEG16/P50
*1 SEG17/P51
*1 SEG18/P52
*1 SEG19/P53
*1 SEG20/P54
*1 SEG21/P55
(FPT-64P-M06)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
7
MB89180 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
SEG2
SEG1
SEG0
COM0
COM1
COM2/P31
COM3/P32
VCC
V3
V2
V1
P30/RCO
P00/INT20
(Top view)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
84
83
82
81
80
79
78
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
77
76
75
74
73
72
71
70
69
94
95
96
65
66
67
68
85
86
87
88
89
90
91
92
93
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21*2
P22/TO
P23/SI
P24/SO
P25/SCK
*1
*1
*1
*1
*1 SEG22/P56
*1 SEG23/P57
SEG24/INT10/P10
SEG25/INT11/P11
SEG26/INT12/P12
VSS
SEG27/INT13/P13
*1 SEG28/P14
*1 SEG29/P15
*1 SEG30/P16
*1 SEG31/P17
*2 BUZ/P27
*2 P26
20
21
22
23
24
25
26
27
28
29
30
31
32
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8/P40
SEG9/P41
SEG10/P42
SEG11/P43
SEG12/P44
SEG13/P45
SEG14/P46
SEG15/P47
SEG16/P50
SEG17/P51
SEG18/P52
SEG19/P53
SEG20/P54
SEG21/P55
(MQP-64C-P01)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
• Pin assignment on package top (MB89PV180 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
N.C.
73
A2
81
N.C.
89
OE
66
VPP
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
71
A4
79
O3
87
CE
95
A14
72
A3
80
VSS
88
A10
96
VCC
N.C.: Internally connected. Do not use.
8
MB89180 Series
■ PIN DESCRIPTION
Pin no.
Pin name
QFP*1
SQFP*3
QFP*2
MQFP*4
39
40
X0
38
39
X1
40
41
MODA
43
44
RST
Circuit
type
Function
A
Main clock crystal oscillator pins
CR oscillation selectability (only for the mask ROM
products)
C
Operating mode selection pin
Connect directly to VSS.
D
44 to 51
45 to 52
P07/INT27 to
P00/INT20
21 to 23
22 to 24
P10/INT10/
SEG24 to
P12/INT12/
SEG26
25
26
P13/INT13/
SEG27
26 to 29
27 to 30
37
38
P20/EC
H
General-purpose N-ch open-drain I/O port
Also serves as the external clock input for the 8-bit
timer counter. The resource is a hysteresis input type.
36
37
P21
I
General-purpose N-ch open-drain I/O port
35
36
P22/TO
I
General-purpose N-ch open-drain I/O port
Also serves as the 8-bit timer/counter output
34
35
P23/SI
H
General-purpose N-ch open-drain I/O port
Also serves as the data input for the 8-bit serial I/O.
The resource is a hysteresis input type.
33
34
P24/SO
I
General-purpose N-ch open-drain I/O port
Also serves as the data output for the 8-bit serial I/O.
32
33
P25/SCK
H
General-purpose N-ch open-drain I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
The resource is a hysteresis input type.
*1:
*2:
*3:
*4:
FPT-64P-M09
FPT-64P-M06
FPT-64P-M03
MQP-64C-P01
P14/SEG28 to
P17/SEG31
E
Reset I/O pin
This pin is an N-ch open drain output type with a pullup resistor, and hysteresis input type. “L” is output
from this pin by an internal reset source. The internal
circuit is initialized by the input of “L”.
General-purpose I/O ports
Also serve as external interrupt 2 input (wake-up
function).
External interrupt 2 input is hysteresis input.
E/K
General-purpose I/O ports
Also serve as external interrupt 1 input.
The interrupt 1 input is a hysteresis type.
Also serve as LCD controller/driver segment output.
Switching is done by the mask option.
F/K
General-purpose I/O ports
Also serve as LCD controller/driver segment output.
Switching is done by the mask option.
(Continued)
9
MB89180 Series
(Continued)
Pin no.
Circuit
type
Function
QFP*2
MQFP*4
31
32
P26
I
General-purpose N-ch open-drain I/O port
30
31
P27/BUZ
I
General-purpose N-ch open-drain I/O port
Also serves as a buzzer output.
52
53
P30/RCO
G
General-purpose output-only port
Also serves as a remote control transmission output
pin.
13 to 20
14 to 21
P50/SEG16 to
P57/SEG23
J/K
5 to 12
6 to 13
P40/SEG8 to
P47/SEG15
J/K
N-ch open-drain type general-purpose output ports
Also serve as LCD controller/driver segment output
pins.
Switching is done by the mask option.
61 to 64,
1 to 4
62 to 64,
1 to 5
57,
58
*1:
*2:
*3:
*4:
10
Pin name
QFP*1
SQFP*3
SEG7 to SEG0
K
LCD controller/driver segment output-only pins
58,
59
COM3/P32,
COM2/P31
L
N-ch open-drain type general-purpose output ports
Also serve as LCD controller/driver common output
pins.
59,
60
60,
61
COM1,
COM0
K
LCD controller/driver common output-only pins
53,
54,
55
54,
55,
56
V1,
V2,
V3
—
LCD driving power supply pins
42
43
X0A
B
Subclock crystal oscillator pins (32.768 kHz)
41
42
X1A
56
57
VCC

Power supply pin
24
25
VSS

Power supply (GND) pin
FPT-64P-M09
FPT-64P-M06
FPT-64P-M03
MQP-64C-P01
MB89180 Series
• External EPROM pins (MB89PV180 only)
Pin no.
Pin name
I/O
Function
66
VPP
O
“H” level output pin
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
77
78
79
O1
O2
O3
I
Data input pins
80
VSS
O
Power supply (GND) pin
82
83
84
85
86
O4
O5
O6
O7
O8
I
Data input pins
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
88
A10
O
Address output pin
89
OE
O
ROM output enable pin
Outputs “L” at all times.
91
92
93
A11
A9
A8
O
Address output pins
94
A13
O
95
A14
O
96
VCC
O
EPROM power supply pin
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
11
MB89180 Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• Crystal or ceramic oscillation type (main clock)
At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
• CR oscillation type (main clock)
(Selectable only for the MB89181/182/183)
X1
X0
Standby control signal
B
• Crystal or ceramic oscillation type (subclock)
• At an oscillation feedback resistor of approximately
4.5 MΩ/5.0 V
X1A
X0A
Standby control signal
C
D
• Output pull-up resistor
• P-ch of approximately 50 KΩ/5.0 V
• Hysteresis input
R
P-ch
N-ch
E
• CMOS I/O
The resource is a hysteresis input type.
R
P-ch
P-ch
N-ch
Port
Resource
F
• Pull-up resistor optional
(MB89181/182/183/P185)
• CMOS I/O
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(MB89181/182/183/P185)
(Continued)
12
MB89180 Series
(Continued)
Type
Circuit
G
Remarks
• CMOS output
• The P-ch output is a heavy-current drive type.
P-ch
N-ch
H
• N-ch open-drain I/O
• CMOS input
• The resource is a hysteresis input type.
R
P-ch
N-ch
Port
Resource
I
• Pull-up resistor optional
(MB89181/182/183)
• N-ch open-drain I/O
• CMOS input
• P21, P26, and P27 are a heavy-current drive type.
R
P-ch
N-ch
• Pull-up resistor optional
(MB89181/182/183)
J
• N-ch open-drain output
R
P-ch
N-ch
K
P-ch
• Pull-up resistor optional
(MB89181/182/183)
• LCD controller/driver segment output
N-ch
P-ch
N-ch
L
• N-ch open-drain output
• Common output
N-ch
P-ch
N-ch
P-ch
N-ch
13
MB89180 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
14
MB89180 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P875
The MB89P185 is an OTPROM version of the MB89180 series.
1. Features
• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
Normal operating mode
0000H
EPROM mode
(Corresponding address on the EPROM programmer)
I/O
0080H
RAM
0180H
Not available
8000H
0000H
Vacancy
(Read value undefined)
3FF0H
Option area
Not available
3FF6H
Vacancy
(Read value undefined)
4000H
C000H
Program area
(EPROM)
16 KB
ROM
16 KB
FFFFH
7FFFH
15
MB89180 Series
3. Programming to the EPROM
In EPROM mode, the MB89P185 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH
in operating mode assign to 4000H to 7FFFH in EPROM mode).
Program to 4000H to 7FFFH with the EPROM programmer.
(3) Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each
corresponding option, see “7. PROM Option Bit Map.”)
Program to 3FF0H to 3FF5H with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
FPT-64P-M09
ROM-64QF2-28DP-8L2
FPT-64P-M06
ROM-64QF-28DP-8L3
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or
VCC and VSS can stabilize programming operations.
16
MB89180 Series
7. PROM Option Bit Map
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
3FF0H
Bit 7
Bit 6
Vacancy
Vacancy
Readable
Readable
Bit 5
Bit 4
Oscillation stabilization delay time
WTM1
WTM0
See “■ Mask Options”
Bit 3
Vacancy
Readable
Bit 2
Bit 1
Bit 0
Reset pin
output
1: Yes
0: No
Clock mode
selection
1: Dual clock
0: Single clock
Power-on
reset
1: Yes
0: No
P07
Pull-up
3FF1H
1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
P17
Pull-up
3FF2H
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
3FF3H
3FF4H
3FF5H
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• Address 3FF6H cannot be read and should not be accessed.
17
MB89180 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32(Rectangle)
ROM-32LC-28DP-YG
LCC-32(Square)
ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Normal operating mode
Corresponding address in ROM programmer
0000H
I/O
0080H
RAM
0180H
Not available
8000H
0000H
Not available
Not available
4000H
C000H
PROM
16KB
FFFFH
EPROM
16KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH.
(3) Program to 4000H to 7FFFH with the EPROM programmer.
18
MB89180 Series
■ BLOCK DIAGRAM
X0
X1
N-ch open-drain I/O port
Main clock oscillator
P26 *2
8-bit timer/counter
Clock controller
P22/TO
Port 0
External interrupt 2
(wake-up function)
P25/SCK
P24/SO
P23/SI
Port 3
P30/RCO
P27 *2 /BUZ
Buzzer output
4
CMOS I/O port
P32/COM3
8-bit serial I/O
8
P00/INT20
to P07/INT27
P31/COM2
P20/EC
Remote control
transmission output
P14 to P17
CMOS I/O port
4
External interrupt 1
(wake-up function)
N-ch open-drain output port
(Only P30 for CMOS output port)
4
Port 1
8
8-bit timer/counter
Port 2
21-bit time-base timer
Internal bus
P21 *2
Subclock oscillator
(32.768 kHz)
X0A
X1A
P10/INT10 to
P13/INT13
4
8
4
RST
SEG28 to SEG31 *1
(Also serve as P14 to P17.)
SEG24 to SEG27 *1
(Also serve as P10 to P13.)
Reset circuit
8
RAM
( 256 × 8 bit s m ax . )
SEG0 to SEG7
2
LCD controller/driver
COM0, COM1
COM2 (Also serves as P31.)
COM3 (Also serves as P32.)
F 2 M C- 8L
CPU
3
V1 to V3
RO M
( 8 K × 8 bit s m ax . )
16
MODA
V CC
V SS
Other pins
M O DA
V CC
V SS
32 × 4 bits
VRAM
Port 4 and port 5
4
4
4
P57/SEG23 *1
to P54/SEG20 *1
P53/SEG19 *1
to P50/SEG16 *1
P47/SEG15 *1
to P44/SEG12 *1
4
N-ch open-drain output port
P43/SEG11 *1
to P40/SEG8 *1
*1: The segment or port function is selected by the mask option.
*2: N-ch open-drain heavy-current drive type
19
MB89180 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89180 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89180 series is structured as illustrated below.
Memory Space
0000H
0080H
MB89PV180
I/O
RAM
512 B
0100H
0000H
0080H
00C0H
MB89181
I/O
0000H
0080H
I/O
0000H
0080H
MB89183
I/O
0000H
0080H
MB89P185
I/O
Unused
RAM
256 B
RAM
128 B
0100H
Register
MB89182
RAM
256 B
0100H
0100H
0100H
Register
RAM
256 B
Register
Register
Register
0140H
0180H
0180H
0180H
0200H
0280H
Unused
Unused
Unused
Unused
Unused
8000H
C000H
E000H
External ROM
32 KB
E800H
F000H
FFFFH
20
FFFFH
ROM
4 KB
ROM
6KB
FFFFH
ROM
16 KB
ROM
8 KB
FFFFH
FFFFH
MB89180 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
: Program counter
PC
FFFDH
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
21
MB89180 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
22
MB89180 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 8 banks can be used on the MB89181 (RAM 128 × 8 bits) and a total of 16 banks
can be used on the MB89182/183 (RAM 256 × 8 bits). The bank currently in use is indicated by the register
bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
8 banks (MB89181)
16 banks (MB89182/183)
Memory area
23
MB89180 Series
■ I/O MAP
Address
Read/write
Register name
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
(W)
DDR2
Port 2 data direction register
06H
Register description
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Time-base timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
Vacancy
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
PDR5
Port 5 data register
10H
(R/W)
BZCR
Buzzer register
11H
Vacancy
12H
Vacancy
13H
Vacancy
14H
(R/W)
RCR1
Remote control transmission control register 1
15H
(R/W)
RCR2
Remote control transmission control register 2
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH
(R/W)
SMR1
Serial mode register
1DH
(R/W)
SDR1
Serial mode register
1EH to 2FH
Vacancy
(Continued)
24
MB89180 Series
(Continued)
Address
Read/write
Register name
30H
(R/W)
EIE1
External interrupt 1 enable register
31H
(R/W)
EIF1
External interrupt 1 flag register
32H
(R/W)
EIE2
External interrupt 2 enable register
33H
(R/W)
EIF2
External interrupt 2 flag register
34H to 5FH
60H to 6FH
Vacancy
(R/W)
VRAM
70H to 71H
72H
Register description
Display data RAM
Vacancy
(R/W)
LCR1
73H to 7BH
LCD controller/driver control register 1
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
Note: Do not use vacancies.
25
MB89180 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
VSS – 0.3
VSS + 7.0
V
LCD power supply voltage
V1 to V3
VSS – 0.3
VSS + 7.0
V
V1 to V3 must not exceed VCC.
VI1
VSS – 0.3
VCC + 0.3
V
VI1 must not exceed Vss + 7.0 V.
Except P20 to P27 without a pullup resistor
VI2
VSS – 0.3
VSS + 7.0
V
P20 to P27 without a pull-up
resistor
Input voltage
VO1
VSS – 0.3
VCC + 0.3
V
VO1 must not exceed Vss + 7.0 V.
Except P20 to P27, P40 to P47,
and P50 to P57 without a pull-up
resistor
VO2
VSS – 0.3
VSS + 7.0
V
P20 to P27, P40 to P47, and P50
to P57 without a pull-up resistor
IOL1

10
mA
Except P21, P26, P27, and power
supply pins
IOL2

20
mA
P21, P26, and P27
Output voltage
“L” level output current
IOLAV1

4
mA
Average value (operating
current × operating rate)
Except P21, P26, P27, and power
supply pins
IOLAV2

8
mA
Average value (operating
current × operating rate)
P21, P26, and P27
“L” level total output current
∑IOL

80
mA
“L” level total average output
current
∑IOLAV

40
mA
Average value (operating
current × operating rate)
IOH1

–5
mA
Except P30 and power supply pins
IOH2

–10
mA
P30
“L” level average output current
“H” level output current
(Continued)
26
MB89180 Series
(Continued)
(VSS = 0.0 V)
Symbol
Value
Unit
Remarks
–2
mA
Average value (operating
current × operating rate)
Except P30 and power supply pins

–4
mA
Average value (operating
current × operating rate)
P30
∑IOH

–20
mA
“H” level total average output
current
∑IOHAV

–10
mA
Power consumption
PD

300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Parameter
Min.
Max.
IOHAV1

IOHAV2
“H” level total output current
“H” level average output current
Average value (operating
current × operating rate)
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Power supply voltage
Symbol
VCC
Value
Unit
Remarks
6.0
V
Guaranteed normal operation range,
applicable to the mask ROM products
2.7*1
6.0
V
MB89P185/PV180
1.5
6.0
V
RAM data holding assurance range in
stop mode
V1 to V3 pins
Min.
Max.
2.2*1
Power supply voltage for LCD
V1 to V3
VSS
VCC*2
V
Operating temperature
TA
–40
+85
°C
*1: The minimum operating power supply voltage varies with the operating frequency and execution time (instruction
cycle).
*2: The liquid-crystal power supply range and optimum value vary depending on the characteristics of the liquidcrystal display element used.
27
MB89180 Series
6
5
Operating voltage (V)
Operation assurance range
4
3
2
1
0
1
2
Main clock operating frequency (MHz)
4.0
3
2.0
4
5
1.0
0.8
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89181/182/183.
Figure 1
28
Operating Voltage vs. Main Clock Operating Frequency
MB89180 Series
3. DC Characteristics
Parameter
Symbol
VIH
P00 to P07,
P10 to P17,
P20 to P27
0.7 VCC
—
VCC +
0.3
V
CMOS
input
VIHS
RST, MODA, EC,
SI, SCK,
INT10 to INT13,
INT20 to INT27
0.8 VCC
—
VCC +
0.3
V
Hysteresis
input
VIL
P00 to P07,
P10 to P17,
P20 to P27
VSS –
0.3
—
0.3 VCC
V
CMOS
input
VILS
RST, MODA,
EC, SI, SCK,
INT10 to
INT13, INT20
to INT27
VSS –
0.3
—
0.2 VCC
V
Hysteresis
input
VD
P20 to P27,
P40 to P47,
P50 to P57
VSS –
0.3
—
VSS +
6.0
V
Without pullup resistor
“H” level input
voltage
“L” level input
voltage
Open-drain output
pin application
voltage
Pin
(VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
—
P00 to P07,
P10 to P17
IOH = –2.0 mA
2.4
—
—
V
P30
IOH = –6.0 mA
4.0
—
—
V
VOL
P00 to P07,
P10 to P17,
P20, P22 to P25,
P30 to P32,
P40 to P47,
P50 to P57
IOL = +1.8 mA
—
—
0.4
V
VOL2
P21, P26, P27 IOL = +8.0 mA
—
—
0.4
V
VOL3
RST
IOL = +4.0 mA
—
—
0.4
V
ILI1
MODA,
P00to P07,
P10 to P17,
P30 to P32
0.0 V < VI < VCC
—
—
±5
µA
Without pullup resistor
ILI2
P20 to P27,
P40 to P47,
P50 to P57
0.0 V < VI < 6 V
—
—
±1
µA
Without pullup resistor
Pull-up
resistance
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57, RST
VI = 0.0 V
25
50
100
kΩ
Without pullup resistor
Common output
impedance
RVCOM
COM0 to
COM3
V1 to V3 = 5.0
V
—
—
2.5
kΩ
Segment output
impedance
RVSEG
SEG0 to
SEG31
V1 to V3 = 5.0
V
—
—
15
kΩ
“H” level output VOH1
voltage
VOH2
“L” level output
voltage
Input leakage
current
(Hi-z output
leakagecurrent)
(Continued)
29
MB89180 Series
(Continued)
Parameter
LCD divided
resistor value
Symbol
Pin
RLCD
LCD controller/
driver leakage ILCDL
current
—
V1 to V3,
COM0 to COM3,
SEG0 to SEG31
ICC1
ICC2
ICCL
Power supply
current*2
ICCS1
VCC
ICCS2
(VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
Between
VCC and VSS
300
500
750
kΩ
—
—
±1
µA
FCH = 4.2 MHz
VCC = 5.0 V
tinst*2 = 0.95 µs
—
3.0
4.5
mA
MB89181/
182/183/
PV180
• Main clock
operation mode
—
3.8
6.0
mA
MB89P185
FCH = 4.2 MHz
VCC = 3.0 V
tinst*2 = 15.2 µs
—
0.25
0.4
mA
• Main clock
operation mode
MB89181/
182/183/
PV180
—
0.85
1.4
mA
MB89P185
FCL = 32.768
kHz
VCC = 3.0 V
tinst*2 = 61 µs
—
0.05
0.1
mA
MB89181/
182/183/
PV180
• Subclock
operation mode
—
0.65
1.1
mA
MB89P185
FCH = 4.2 MHz
VCC = 5.0 V
tinst*2 = 0.95 µs
• Main clock
sleep mode
—
0.8
1.2
mA
FCH = 4.2 MHz
VCC = 3.0 V
tinst*2 = 15.2 µs
• Main clock
sleep mode
—
0.2
0.3
mA
—
25
50
µA
—
FCL = 32.768 kHz
VCC = 3.0 V
tinst*2 = 61 µs
ICCSL
• Subclock mode
FCL = 32.768 kHz
ICCT
VCC = 3.0 V
• Watch mode
—
10
15
µA
—
0.1
1
µA
ICCH
TA = +25°C
VCC = 5.0 V
• Stop mode
MB89181/
182/183
—
0.1
10
µA
MB89PV18
0/P185
f = 1 MHz
—
10
—
pF
Input capacitance CIN
Other VCC and VSS
*1: The measurement conditions of power supply current are as follows: the external clock, open output pins, and
the external LCD dividing resistor. In the case of the MB89PV180, the current consumed by the connected
EPROM and ICE is not included.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Note: For pins which serve as the segment (SEG8 to SEG31) and ports (P10 to P17, P40 to P47, and P50 to P57),
see the port parameter when these pins are used as ports and the segment parameter when they are used
as segment pins.
30
MB89180 Series
4. AC Characteristics
(1) Reset Timing
Symbol
Parameter
RST “L” pulse width
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Max.
Condition
tZLZH
—
48 tHCYL
—
ns
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
Min.
Max.
—
50
ms
Power-on reset function only
1
—
ms
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tR
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
31
MB89180 Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Clock frequency
Clock cycle time
Input clock pulse width
Input clock pulse rising/
falling time
Value
Pin
Min.
Typ.
Max.
Unit
Remarks
FCH
X0, X1
1
—
4.2
MHz
Main clock
FCL
X0A, X1A
—
32.768
—
kHz
Subclock
tHCYL
X0, X1
238
—
1000
ns
Main clock
tLCYL
X0A, X1A
—
30.5
—
µs
Subclock
PWH
PWL
X0
20
—
—
ns
PWHL
PWLL
X0A
—
15.2
—
µs
tCR
tCF
X0, X0A
—
—
10
ns
External clock
X0 and X1 Timing and Conditions
tHCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
Main clock Conditions
When crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
When CR oscillation
option is used
X0
X1
FCH
FCH
Open
C1
32
C2
FCH
R1
C
MB89180 Series
X0A and X1A Timing and Conditions
tLCYL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tCF
tCR
Subclock Conditions
When crystal
or
ceramic resonator is used
X0A
X1A
When an external clock is used
X0A
X0A
X1A
Open
R2
When single-clock
option is used
X1A
Open
FCL
FCL
C1
C2
(4) Instruction Cycle
Parameter
Symbol
Instruction cycle
tinst
(minimum execution time)
Value (typical)
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH) tinst = 0.95 µs when operating
at FCH = 4.2 MHz
2/FCL
µs
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
33
MB89180 Series
(5) Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Pin
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
SCK
Serial clock “L” pulse width
tSLSH
SCK
Value
Condition
Internal shift
clock mode
Max.
2 tinst*
—
µs
–200
200
ns
0.5 tinst*
—
µs
0.5 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
External shift
clock mode
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
0.5 tinst*
—
µs
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
0.5 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 V cc
0.8 V cc
0.2 V cc
0.2 V cc
External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
SCK
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
34
Unit
Min.
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Remarks
MB89180 Series
(6) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Unit Remarks
Min.
Max.
Symbol
Parameter
Peripheral input “H” pulse width 1
tILIH1
INT10 to INT13, EC
1 tinst*
—
µs
Peripheral input “L” pulse width 1
tIHIL1
INT10 to INT13, EC
1 tinst*
—
µs
Peripheral input “H” pulse width 2
tILIH2
INT20 to INT27
2 tinst*
—
µs
Peripheral input “L” pulse width 2
tIHIL2
INT20 to INT27
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
INT10 to INT13,
EC
tILIH1
0.8 VCC
0.2 VCC
0.2 VCC
tIHIL2
0.8 VCC
tILIH2
INT20 to INT27
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
35
MB89180 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” level Output Voltage
VOL2 vs.IOL
VOL1 vs. IOL
VCC = 2.5 V
VOL1 (V)
0.6
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.0 V
TA = +25°C
0.5
0.4
VOL2 (V)
VCC = 2.0 V
1.0
TA = +25°C
0.9
VCC = 2.5 V
VCC = 3.0 V
VCC = 5.0 V
0.8
VCC = 6.0 V
0.7
VCC = 4.0 V
0.6
VCC = 5.0 V
VCC = 6.0 V
0.5
0.3
0.4
0.2
0.3
0.2
0.1
0
0.1
0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
0
2
4
6
8
10
12 14
16 18
20
IOL (mA)
(2) “H” level Output Voltage
VCC vs. VOH2 vs. IOH
VCC vs.VOH1 vs. IOH
VCC vs. VOH1 (V) VCC = 2.0 V
1.0
TA = +25°C
0.9
VCC = 2.5 V VCC = 3.0 V
VCC = 2.5 V VCC = 3.0 V
0.8
VCC = 4.0 V
0.8
VCC = 4.0 V
0.7
VCC = 5.0 V
VCC = 6.0 V
0.7
VCC = 5.0 V
VCC = 6.0 V
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
36
VCC vs. VOH2 (V) VCC = 2.0 V
1.0
TA = +25°C
0.9
0
–1
–2
–3
–4
–5
IOH (mA)
0
0
–1
–2
–3
–4 –5
–6
–7
–8
–9 –10
IOH (mA)
MB89180 Series
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN vs. VCC
VIN (V)
5.0
VIN (V)
5.0
TA = +25°C
4.5
TA = +25°C
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
VIHS
VILS
0
1
2
3
4
5
6
7
VCC (V)
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(5) Power Supply Current (External Clock)
ICC1 vs. VCC (Mask ROM products)
ICC1 (mA)
5.0
TA = +25°C
4.5
ICC2 vs. VCC (Mask ROM products)
ICC2 (mA)
1.0
TA = +25°C
0.9
0.8
4.0
FCH = 4.2 MHz
3.5
3.0
FCH = 3 MHz
FCH = 3 MHz
0.6
2.5
0.5
2.0
0.4
FCH = 1 MHz
0.3
1.5
FCH = 1 MHz
1.0
0.2
0.1
0.5
0
FCH = 4.2 MHz
0.7
1
2
3
4
5
6
7
VCC (V)
0
1
2
3
4
5
6
7
VCC (V)
(Continued)
37
MB89180 Series
(Continued)
ICCS1 vs. VCC
ICCS1 (mA)
1.2
TA = +25°C
1.1
FCH = 4.2 MHz
1.0
ICCS2 vs. VCC
ICCS2 (mA)
1.0
TA = +25°C
0.9
0.8
0.9
FCH = 3 MHz
0.8
0.7
0.7
0.6
0.6
0.5
FCH = 4.2 MHz
FCH = 3 MHz
0.5
FCH = 1 MHz
0.4
0.4
FCH = 1 MHz
0.3
0.3
0.2
0.2
0.1
0.1
0
1
2
3
4
5
6
7
VCC (V)
0
1
2
3
4
5
6
7
VCC (V)
ICCT vs. VCC
ICCL vs. VCC (Mask ROM units)
ICCT (µA)
30
ICCL (µA)
200
TA = +25°C
TA = +25°C
180
25
160
140
FCL = 32.768 kHz
FCL = 32.768 kHz
20
120
15
100
80
10
60
40
5
20
0
0
1
2
3
4
5
6
7
VCC (V)
1
2
3
4
5
6
7
VCC (V)
(Continued)
38
MB89180 Series
(Continued)
ICCSL vs. VCC
ICCSL (µA)
200
TA = +25°C
180
160
140
120
100
FCL = 32.768 kHz
80
60
40
20
0
1
2
3
4
5
6
7
VCC (V)
(6) Pull-up Resistance Value
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
TA = +85°C
TA = +25°C
50
TA = –40°C
10
1
2
3
4
5
6
7
VCC (V)
39
MB89180 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
40
MB89180 Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
41
MB89180 Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
42
MB89180 Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
43
MB89180 Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
44
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
0
0
1
NOP
SWAP
2
3
RET
RETI
4
5
PUSHW
A
6
7
8
9
POPW MOV
MOVW CLRI
A
A,ext
A,PS
SETI
INCW
DECW JMP
MOVW
CLRB BBC
A
A
@A
A,PC
dir: 0 dir: 0,rel
SETC
INCW
DECW MOVW MOVW
CLRB BBC
SP
SP
SP,A
A,SP
dir: 1 dir: 1,rel
1
PUSHW POPW MOV
MULU DIVU
JMP
CALL
MOVW CLRC
IX
A
A addr16 addr16
IX
ext,A
PS,A
2
ROLC
CMP
A
A
ADDC SUBC XCH
XOR
AND
OR
A
A
A, T
A
A
A
A
B
C
D
E
F
INCW
DECW MOVW MOVW
MOV
MOV
CLRB BBC
IX
IX
IX,A
A,IX
@A,T
A,@A
dir: 2 dir: 2,rel
3
RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW
INCW
DECW MOVW MOVW
MOVW MOVW CLRB BBC
A
A
A
A
EP
EP
EP,A
A,EP
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
4
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
5
MOVW MOVW MOVW XCHW
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
CLRB BBC
A,dir
dir,A SP,#d16
A,SP
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
6
MOV
A,@IX +d
7
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
CLRB BBC
MOVW MOVW MOVW XCHW
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16
A,EP
8
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
9
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
rel
A
INC
DEC
CALLV BP
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
R2
R2
#2
rel
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
B
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
rel
C
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
D
INC
DEC
CALLV BZ
MOV A CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
R5
R5
#5
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
CMP
A,@IX +d
ADDC
A,@IX +d
SUBC
A,@IX +d
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
MOV @IX
+d,A
XOR
AND
A,@IX +d A,@IX +d
OR
A,@IX +d
DAS
MOV
CMP
@IX +d,#d8 @IX +d,#d8
■ INSTRUCTION MAP
L H
CLRB BBC
MOVW MOVW MOVW XCHW
dir: 4 dir: 4,rel
A,ext
ext,A A,#d16
A,PC
MOVW
MOVW
CLRB BBC
MOVW XCHW
dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16
A,IX
45
E
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
F
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
R7
R7
#7
rel
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
MB89180 Series
rel
MB89180 Series
■ MASK OPTIONS
No.
MB89181/182/183
MB89P185
MB89PV180
Specifying procedure
Specify when
ordering masking
Set with EPROM
programmer
Setting not
possible
Can be set per pin
(P10 to P17 are
available only when
segment output is not
selected.)
Pull-up resistors
P00 to P07, P10 to P17
Can be set per pin
(P10 to P17 are
available only when
segment output is not
selected.)
2
Pull-up resistors
P40 to P47, P50 to P57
Can be set per pin
(Available only when
segment output is
not selected.)
Fixed to without pullup resistor
3
Pull-up resistors
P20 to P27
Can be set per pin
Fixed to without pullup resistor
4
Power-on reset
With power-on reset
Without power-on reset
Selectable
Selectable
Fixed to with poweron reset
5
Selection of oscillation stabilization
delay time
The initial value of the main clock
oscillation stabilization time is
selectable by bit value of WTM1
and WTM0.
Selectable
WTM1 WTM0
0
0: 22/FCH
0
1: 212/FCH
1
0: 216/FCH
1
1: 218/FCH
Selectable
WTM1 WTM0
0
0: 22/FCH
0
1: 212/FCH
1
0: 216/FCH
1
1: 218/FCH
Fixed to oscillation
stabilization time of
216/FCH
6
Main clock oscillation type
Crystal or ceramic oscillator
CR
Selectable
Crystal or ceramic
oscillator
Crystal or ceramic
oscillator
7
Reset pin output
With reset output
Without reset output
Selectable
Selectable
With reset output
8
Clock mode selection
Dual-clock mode
Single-clock mode
Selectable
Selectable
Fixed to dual-clock
mode
9
Segment output selection
32 segments:No port selection
28 segments:Selection of P17 to
P14
24 segments: Selection of P17 to
P10
20 segments:Selection of P17 to
P10,and P57 to P54
16 segments:Selection of P17 to
P10,and P57 to P50
12 segments:Selection of P17 to
P10,P57 to P50, and P47 to P44
8 segments: Selection of P17 to
P10,P57 to P50, and P47 to P40
1
46
Part number
Selectable
Selects the number
of segments.
Fixed to without pullup resistor
-101: 32 segments
-102: 28 segments
-103: 24 segments
-104: 20 segments
-105: 16 segments
-106: 12 segments
-107: 8 segments
MB89180 Series
■ ORDERING INFORMATION
Part number
Package
MB89181PF
MB89182PF
MB89183PF
MB89P185PF-101
MB89P185PF-102
MB89P185PF-103
MB89P185PF-104
MB89P185PF-105
MB89P185PF-106
MB89P185PF-107
64-pin Plastic QFP
(FPT-64P-M06)
MB89181FM
MB89182FM
MB89183FM
MB89P185PFM-101
MB89P185PFM-102
MB89P185PFM-103
MB89P185PFM-104
MB89P185PFM-105
MB89P185PFM-106
MB89P185PFM-107
64-pin Plastic QFP
(FPT-64P-M09)
MB89181PFV
MB89182PFV
MB89183PFV
MB89PV180CF-101
MB89PV180CF-102
MB89PV180CF-103
MB89PV180CF-104
MB89PV180CF-105
MB89PV180CF-106
MB89PV180CF-107
Remarks
64-pin Plastic SQFP
(FPT-64P-M03)
64-pin Ceramic MQFP
(MQP-64C-P01)
47
MB89180 Series
■ PACKAGE DIMENSIONS
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
3.35(.132)MAX
20.00±0.20(.787±.008)
51
0.05(.002)MIN (Mounting height)
(STAND OFF)
33
52
32
14.00±0.20
(.551±.008)
18.70±0.40
(.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
20
64
"A"
LEAD No.
19
1
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
0.15±0.05(.006±.002)
0.20(.008)
M
Details of "A" part
Details of "B" part
0.25(.010)
"B"
0.30(.012)
0.10(.004)
0.63(.025)MAX
22.30±0.40(.878±.016)
C
0 10°
1.20±0.20
(.047±.008)
0.18(.007)MAX
18.00(.709)REF
Dimensions in mm (inches)
1994 FUJITSU LIMITED F64013S-3C-2
64 pin, Plastic QFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
48
33
12.00±0.10(.472±.004)SQ
49
+0.20
1.50 –0.10
+.008
.059 –.004
32
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
LEAD No.
17
1
0.65(.0256)TYP
Details of "A" part
16
0.30±0.10
(.012±.004)
"A"
0.13(.005)
M
+0.05
0.127 –0.02
+.002
.005 –.001
0.10±0.10 (STAND OFF)
(.004±.004)
0.10(.004)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches).
48
MB89180 Series
(Continued)
64 pin, PlasticLQFP
(FPT-64P-M03)
+0.20
1.50 −0.10
+.008
.059 −.004
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
48
(Mounting Height)
33
49
32
7.50
(.295)
REF
11.00
(.433)
NOM
INDEX
64
LEAD No.
Details of "A" part
17
16
1
"A"
+0.08
0.10±0.10
(STAND OFF)
(.004±.004)
+0.05
0.18 −0.03
+.003
.007 −.001
0.50±0.08
(.0197±.0031)
0.127 −0.02
+.002
.005 −.001
0.50±0.20
(.020±.008)
0.10(.004)
C
0
1995 FUJITSU LIMITED F64009S-2C-5
10˚
Dimensions in mm (inches).
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
+0.40
1.20 –0.20
+.016
.047 –.008
1.00±0.25
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.40±0.10
(.016±.004)
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
1994 FUJITSU LIMITED M64004SC-1-3
10.82(.426)
0.15±0.05 MAX
(.006±.002)
Dimensions in mm (inches)
49
MB89180 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F9703
 FUJITSU LIMITED Printed in Japan