Fujitsu MB90337PMC 16-bit microcontroller Datasheet

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13735-4E
16-bit Microcontroller
CMOS
F2MC-16LX MB90335 Series
MB90337/F337/V330A
■ DESCRIPTION
The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral
devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but
also HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices
such as displays and audio devices, and control of mobile devices that support USB communications. While
inheriting the AT architecture of the F2MC* family, the instruction set supports the C language and extended
addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial
collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in oscillation circuit and PLL clock frequency multiplication circuit
• Oscillation clock
• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)
• Clock for USB is 48 MHz
• Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable
• Minimum execution time of instruction : 41.7 ns (6 MHz oscillation clock, 4-time multiplied : machine clock
24 MHz and at operating VCC = 3.3 V)
• The maximum memory space: 16 Mbytes
• 24-bit addressing
• Bank addressing
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.9
MB90335 Series
• Instruction system
• Data types: Bit, Byte, Word, Long word
• Addressing mode (23 types)
• Enhanced high-precision computing with 32-bit accumulator
• Enhanced Multiply/Divide instructions with sign and the RETI instruction
• Instruction system compatible with high-level language (C language) and multi-task
• Employing system stack pointer
• Instruction set symmetry and barrel shift instructions
• Program Patch Function (2 address pointer)
• 4-byte instruction queue
• Interrupt function
• Priority levels are programmable
• 20 interrupts function
• Data transfer function
• Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels
• μDMAC : Maximum 16 channels
• Low Power Consumption Mode
• Sleep mode (with the CPU operating clock stopped)
• Time-base timer mode (with the oscillator clock and time-base timer operating)
• Stop mode (with the oscillator clock stopped)
• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)
• Package
• LQFP-64P (FPT-64P-M23 : 0.65 mm pin pitch)
• Process : CMOS technology
• Operation guaranteed temperature: − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)
(Continued)
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MB90335 Series
(Continued)
• Internal peripheral function (resource)
• I/O port : Max 45 ports
• Time-base timer : 1channel
• Watchdog timer : 1 channel
• 16-bit reload timer : 1 channel
• Multi-functional timer
• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse are
freely programmable.
• 16-bit PWC timer : 1 channel
Timer function and pulse width measurement function
• UART: 2 channels
• Equipped with a full duplex (8-bit long) double buffer
• Selectable asynchronous transfer or clock-synchronous serial (extended I/O serial) transfer.
• Extended I/O serial interface : 1 channel
• DTP/External interrupt circuit (8 channels)
• Activate the extended intelligent I/O service by external interrupt input
• Interrupt output by external interrupt input
• Delayed interrupt output module
• Outputs an interrupt request for task switching
• USB: 1 channel
• USB function (supports USB 2.0 Full Speed)
• Supports Full Speed/Up to 6 endpoints can be specified.
• Dual port RAM (supports FIFO mode).
• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible
• USB HOST function
2
• I C Interface: 1 channel
• Supports Intel SM bus standards and Phillips I2C bus standards
• Two-wire data transfer protocol specification
• Master and slave transmission/reception
DS07-13735-4E
3
MB90335 Series
■ PRODUCT LINEUP
Part number
MB90V330A
For evaluation
Type
MB90F337
Built-in Flash Memory
MB90337
Built-in MASK ROM
ROM capacity
No
64 Kbytes
RAM capacity
28 Kbytes
4 Kbytes
Used bit
⎯
CPU functions
Number of basic instructions
Minimum instruction
execution time
Addressing type
Program Patch Function
Maximum memory space
: 351 instructions
: 41.7 ns / at oscillation of 6 MHz
(When 4 times are used : Machine clock of 24 MHz)
: 23 types
: For 2 address pointers
: 16 Mbytes
Ports
I/O Ports(CMOS) Max 45 ports
UART
Equipped with full-duplex double buffer
Clock synchronous or asynchronous operation selectable.
It can also be used for I/O serial.
Built-in special baud-rate generator
Built-in 2 channels
16-bit reload timer
16-bit reload timer operation
Built-in 1 channel
Multi-functional timer
8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels)
16-bit PWC timer × 1 channel
DTP/External interrupt
8 channels
Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable
I2C
1 channel
Emulator-specific
power supply *
Extended I/O serial interface 1 channel
USB
1 channel
USB function (correspond to USB 2.0 Full Speed)
USB HOST function
Withstand voltage of 5 V
8 ports (Excluding UTEST and I/O for I2C)
Low Power Consumption
Mode
Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode
Process
CMOS
Operating voltage VCC
3.3 V ± 0.3 V (at maximum machine clock 24 MHz)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to
the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
■ PACKAGES AND PRODUCT MODELS
Package
FPT-64P-M23 (LQFP)
MB90337
MB90F337
MB90V330A
PGA-299C-A01 (PGA)
: Yes
: No
Note : See “■ PACKAGE DIMENSIONS” for details.
4
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MB90335 Series
■ PIN ASSIGNMENT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P51
P41/TOT0
P40/TIN0
P67/INT7/SDA0
P66/INT6/SCL0
P65/INT5/PWC
P64/INT4/SCK
P63/INT3/SOT
P62/INT2/SIN
P61/INT1
P60/INT0
P27/PPG3
P26/PPG2
P25/PPG1
P50
Vcc
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vss
X1
X0
P24/PPG0
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P52
P53
Vss
MD2
MD1
MD0
RST
P54
P00
P01
P02
P03
P04
P05
P06
P07
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
UTEST
Vss
DVM
DVP
Vcc
Vss
HVM
HVP
Vcc
HCON
P42/SIN0
P43/SOT0
P44/SCK0
P45/SIN1
P46/SOT1
P47/SCK1
(FPT-64P-M23)
DS07-13735-4E
5
MB90335 Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type*
46 , 47
X0, X1
A
It is a terminal which connects the oscillator.
Oscillation
When connecting an external clock, leave the X1 pin side
status
unconnected.
23
RST
F
Reset input External reset input pin.
25 to 32
P00 to P07
Status at
reset/
function
Function
I
General purpose input/output port.
The ports can be set to be added with a pull-up resistor
(RD00 to RD07 = 1) by the pull-up resistor setting register
(RDR0). (When the power output is set, it is invalid.)
33 to 40
P10 to P17
I
General purpose input/output port.
The ports can be set to be added with a pull-up resistor
(RD10 to RD17 = 1) by the pull-up resistor setting register
(RDR1). (When the power output is set, it is invalid.)
41 to 44
P20 to P23
D
General purpose input/output port.
45
51 to 53
62
63
11
12
13
14
15
16
P24
PPG0
P25 to P27
PPG1 to PPG3
P40
TIN0
P41
TOT0
P42
SIN0
P43
SOT0
P44
SCK0
P45
SIN1
P46
SOT1
P47
SCK1
D
D
H
H
H
H
H
H
H
H
General purpose input/output port.
Functions as output pins of PPG timers ch.0.
General purpose input/output port.
Functions as output pins of PPG timers ch.1 to ch.3.
General purpose input/output port.
Function as event input pin of 16-bit reload timer.
General purpose input/output port.
Port input Function as output pin of 16-bit reload timer.
General purpose input/output port.
(Hi-Z)
Functions as a data input pin for UART ch.0.
General purpose input/output port.
Functions as a data output pin for UART ch.0.
General purpose input/output port.
Functions as a clock I/O pin for UART ch.0.
General purpose input/output port.
Functions as a data input pin for UART ch.1.
General purpose input/output port.
Functions as a data output pin for UART ch.1.
General purpose input/output port.
Functions as a clock I/O pin for UART ch.1.
50
P50
K
General purpose input/output port.
64
P51
K
General purpose input/output port.
17, 18
P52, P53
K
General purpose input/output port.
24
P54
K
General purpose input/output port.
(Continued)
6
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MB90335 Series
(Continued)
Pin no.
54, 55
Pin name
P60, P61
INT0, INT1
I/O
Circuit
type*
Status at
reset/
function
General purpose input/output port (withstand voltage of 5 V) .
C
Functions as the input pin for external interrupt ch.0 and ch.1.
P62
56
57
58
INT2
General purpose input/output port (withstand voltage of 5 V) .
C
Functions as the input pin for external interrupt ch.2.
SIN
Data input pin for extended I/O serial interface.
P63
General purpose input/output port (withstand voltage of 5 V) .
INT3
C
Functions as the input pin for external interrupt ch.3.
SOT
Data output pin for extended I/O serial interface.
P64
General purpose input/output port (withstand voltage of 5 V) .
INT4
C
SCK
INT5
Functions as the input pin for external interrupt ch.4.
Port input
(Hi-Z)
P65
59
C
Clock I/O pin for extended I/O serial interface.
General purpose input/output port (withstand voltage of 5 V) .
Functions as the input pin for external interrupt ch.5.
PWC
Functions as the PWC input pin.
P66
General purpose input/output port (withstand voltage of 5 V) .
INT6
60
Functions as the input pin for external interrupt ch.6.
C
Functions as the input/output pin for I2C interface clock. The port
output must be placed in Hi-Z state during I2C interface
operation.
SCL0
P67
61
Function
INT7
General purpose input/output port (withstand voltage of 5 V) .
Functions as the input pin for external interrupt ch.7.
C
Functions as the I2C interface data input/output pin. The port output must be placed in Hi-Z state during I2C interface operation.
SDA0
UTEST
input
USB test pin.
Connect this to a pull-down resistor during normal usage.
1
UTEST
C
3
DVM
J
USB function D − pin.
USB input USB function D + pin.
(SUSPEND) USB HOST D − pin.
4
DVP
J
7
HVM
J
8
HVP
J
10
HCON
E
21, 22
MD1, MD0
B
20
MD2
G
5, 9, 49
Vcc
2, 6,
19, 48
Vss
⎯
USB HOST D + pin.
High output External pull-up resistor connection pin.
Mode input Input pin for selecting operation mode.
Power
supply
Power supply pin.
Power supply pin (GND).
* : For circuit information, refer to “■ I/O CIRCUIT TYPE”.
DS07-13735-4E
7
MB90335 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
• Oscillation feedback resistor of
approx. 1 MΩ
• With standby control
X0
Standby control signal
B
CMOS hysteresis input
CMOS hysteresis
input
C
• CMOS hysteresis input
• N-ch open drain output
N-ch
Nout
CMOS hysteresis input
Standby control signal
D
P-ch
Pout
N-ch
Nout
CMOS hysteresis input
Standby control signal
E
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
Notes : • Share one output buffer because
both output of I/O port and
internal resource are used.
• Share one input buffer because
both input of I/O port and internal
resource are used.
CMOS output
P-ch
Pout
N-ch
Nout
F
CMOS hysteresis input with pull-up
resistor of approx. 50 kΩ
R
CMOS hysteresis
input
G
R
CMOS hysteresis
input
• CMOS hysteresis input with pull-down
resistor of approx. 50 kΩ
• Flash product is not provided with pulldown resistor.
(Continued)
8
DS07-13735-4E
MB90335 Series
(Continued)
Type
Circuit
Remarks
H
P-ch
Pout
N-ch
Nout
Open drain control
signal
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
With open drain control signal
CMOS hysteresis input
Standby control signal
I
• CMOS output
• CMOS input
(With input interception function at
standby)
• Programmable input pull-up resistor
Control signal
R
P-ch
Pout
N-ch
Nout
CMOS input
Standby control signal
J
USB I/O pin
D + input
D - input
D+
Differential input
D−
Full D + output
Full D - output
Low D + output
Low D - output
Direction
Speed
K
P-ch
Pout
N-ch
Nout
• CMOS output
• CMOS input
(With input interception function at
standby)
CMOS input
Standby control signal
DS07-13735-4E
9
MB90335 Series
■ HANDLING DEVICES
1. Preventing latch-up and turning on power supply
latch-up may occur on CMOS IC under the following conditions:
• If a voltage higher than VCC or lower than VSS is applied to input and output pins.
• A voltage higher than the rated voltage is applied between VCC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using CMOS IC, take great care to prevent the occurrence of latch-up.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
3. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub-clock or stop mode. When suing an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
• Using external clock
X0
OPEN
X1
4. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS pins
near this device.
5. About crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that
X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to
the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
6. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
10
DS07-13735-4E
MB90335 Series
7. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage
operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations
(peak-to-peak value) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply
voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply
switching.
8. Writing to flash memory
For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.
For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
9. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,
design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error.
If an error is detected, retransmit the data.
DS07-13735-4E
11
MB90335 Series
■ BLOCK DIAGRAM
X0, X1
RST
MD0 to MD2
Clock control
circuit
F2MC-16LX
CPU
Interrupt
controller
RAM
8/16-bit PPG
timer
ch.0 to ch.3*
PPG0 to PPG3
16-bit PWC
PWC
SIO
SIN
SOT
SCK
ROM
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
SCL0
SDA0
TOT0
TIN0
I2C
16-bit reload
timer
DVP
DVM
HVP
HVM
HCON
UTEST
INT0 to INT7
Internal data bus
UART/SIO
ch.0, ch.1
μDMAC
USB
(function)
(HOST)
External interrupt
I/O port (port 0, 1, 2, 4, 5, 6)
P00
P10
P20
P40
P50
P60
P07
P17
P27
P47
P54
P67
* : Channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode.
Note : I/O ports share pins with peripheral function (resources) .
For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.
Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
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MB90335 Series
■ MEMORY MAP
Single chip mode (with ROM mirror function)
MB90V330A
FFFFFFH
ROM (FF bank)
FF0000H
00FFFFH
008000H
007FFFH
007900H
MB90F337
FFFFFFH
ROM (FF bank)
FF0000H
ROM area
(image of FF bank)
Peripheral area
00FFFFH
008000H
007FFFH
007900H
MB90337
FFFFFFH
ROM (FF bank)
FF0000H
ROM area
(image of FF bank)
Peripheral area
00FFFFH
008000H
007FFFH
007900H
ROM area
(image of FF bank)
Peripheral area
007100H
RAM area
(28 Kbytes)
000100H
Register
0000FBH
001100H
000100H
0000FBH
Peripheral area
000000H
RAM area
(4 Kbytes)
Register
001100H
000100H
0000FBH
Peripheral area
000000H
RAM area
(4 Kbytes)
Register
Peripheral area
000000H
Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H
to FFFFFFH” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.
• The ROM mirror function is effective for using the C compiler small model.
• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in
bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be
reproduced in bank 00.
• When the C compiler small model is used, the data table mirror image can be shown at “008000H to
00FFFFH” by storing the data table at “FF8000H to FFFFFFH”.
Therefore, data tables in the ROM area can be referred without declaring the far addressing with
the pointer.
DS07-13735-4E
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MB90335 Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated register
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8-bit
16-bit
32-bit
• General purpose registers
MSB
LSB
16-bit
000180H + RP × 10H
RW0
RL0
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
• Processor status
Bit 15
PS
14
13 12
ILM
8 7
RP
0
CCR
DS07-13735-4E
MB90335 Series
■ I/O MAP
Address
Register
abbreviation
Read/
Write
Resource name
Initial Value
000000H
PDR0
Port 0 Data Register
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 Data Register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 Data Register
R/W
Port 2
XXXXXXXXB
Register
000003H
Prohibited
000004H
PDR4
Port 4 Data Register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 Data Register
R/W
Port 5
- - - XXXXXB
000006H
PDR6
Port 6 Data Register
R/W
Port 6
XXXXXXXXB
000007H
to
00000FH
Prohibited
000010H
DDR0
Port 0 Direction Register
R/W
Port 0
0 0 0 0 0 0 0 0B
000011H
DDR1
Port 1 Direction Register
R/W
Port 1
0 0 0 0 0 0 0 0B
000012H
DDR2
Port 2 Direction Register
R/W
Port 2
0 0 0 0 0 0 0 0B
000013H
Prohibited
000014H
DDR4
Port 4 Direction Register
R/W
Port 4
0 0 0 0 0 0 0 0B
000015H
DDR5
Port 5 Direction Register
R/W
Port 5
- - - 0 0 0 0 0B
000016H
DDR6
Port 6 Direction Register
R/W
Port 6
0 0 0 0 0 0 0 0B
000017H
to
00001AH
Prohibited
00001BH
ODR4
Port 4 Output Pin Register
R/W
Port 4 (Open-drain
0 0 0 0 0 0 0 0B
control)
00001CH
RDR0
Port 0 Pull-up Resistance Register
R/W
Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B
00001DH
RDR1
Port 1 Pull-up Resistance Register
R/W
Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B
00001EH
Prohibited
00001FH
000020H
SMR0
Serial Mode Register 0
R/W
0 0 1 0 0 0 0 0B
000021H
SCR0
Serial Control Register 0
R/W
0 0 0 0 0 1 0 0B
SIDR0
Serial Input Data Register 0
R
SODR0
Serial Output Data Register 0
W
000022H
000023H
SSR0
000024H
UART0
XXXXXXXXB
Serial Status Register 0
R/W
0 0 0 0 1 0 0 0B
UTRLR0
UART Prescaler Reload Register 0
R/W
000025H
UTCR0
UART Prescaler Control Register 0
R/W
Communication 0 0 0 0 0 0 0 0B
Prescaler (UART0) 0 0 0 0 - 0 0 0B
000026H
SMR1
Serial Mode Register 1
R/W
0 0 1 0 0 0 0 0B
000027H
SCR1
Serial Control Register 1
R/W
0 0 0 0 0 1 0 0B
SIDR1
Serial Input Data Register 1
R
SODR1
Serial Output Data Register 1
W
000028H
000029H
SSR1
Serial Status Register 1
R/W
UART1
XXXXXXXXB
0 0 0 0 1 0 0 0B
(Continued)
DS07-13735-4E
15
MB90335 Series
Address
Register
abbreviation
Read/
Write
00002AH
UTRLR1
UART Prescaler Reload Register 1
R/W
00002BH
UTCR1
UART Prescaler Control Register 1
R/W
Communication 0 0 0 0 0 0 0 0B
Prescaler (UART1) 0 0 0 0 - 0 0 0B
0 0 0 0 0 0 0 0B
Register
00002CH
to
00003BH
ENIR
DTP/Interrupt Enable Register
R/W
00003DH
EIRR
DTP/Interrupt source Register
R/W
Request Level Setting Register Lower
R/W
Request Level Setting Register Upper
R/W
00003FH
Initial Value
Prohibited
00003CH
00003EH
Resource name
ELVR
000040H
to
000045H
DTP/External
interrupt
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Prohibited
000046H
PPGC0
PPG0 Operation Mode Control Register
R/W
PPG ch.0
0X0 0 0XX1B
000047H
PPGC1
PPG1 Operation Mode Control Register
R/W
PPG ch.1
0X0 0 0 0 0 1B
000048H
PPGC2
PPG2 Operation Mode Control Register
R/W
PPG ch.2
0X0 0 0XX1B
000049H
PPGC3
PPG3 Operation Mode Control Register
R/W
PPG ch.3
0X0 0 0 0 0 1B
R/W
PPG ch.0/ch.1
0 0 0 0 0 0XXB
R/W
PPG ch.2/ch.3
0 0 0 0 0 0 XXB
Serial Mode Control Status Register
R/W
0 0 0 0 0 0 1 0B
Serial Data Register
R/W
Extended Serial
I/O
Communication Prescaler Control
Register
R/W
Communication
Prescaler
0XXX0 0 0 0B
PWC Control Status Register
R/W
00004AH
Prohibited
00004BH
00004CH
PPG01
PPG0 and PPG1 Output Control Register
00004DH
00004EH
Prohibited
PPG23
PPG2 and PPG3 Output Control Register
00004FH
to
000057H
000058H
000059H
Prohibited
SMCS
00005AH
SDR
00005BH
SDCR
00005CH
00005DH
00005EH
00005FH
000060H
PWCSR
PWCR
DIVR
PWC Data Buffer Register
R/W
PWC Dividing Ratio Control Register
R/W
000061H
000062H
000063H
000064H
000065H
16
XXXX0 0 0 0B
XXXXXXXXB
0 0 0 0 0 0 0 0B
16-bit
PWC Timer
0 0 0 0 0 0 0 XB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - - - 0 0B
Prohibited
TMCSR0
TMR0
TMRLR0
TMR0
TMRLR0
Timer Control Status Register
0 0 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
16-bit Timer Register Lower
R
16-bit Reload Register Lower
W
16-bit Timer Register Upper
R
XXXXXXXXB
16-bit Reload Register Upper
W
XXXXXXXXB
(Continued)
16-bit Reload
Timer
XXXXXXXXB
XXXXXXXXB
DS07-13735-4E
MB90335 Series
Address
Register
abbreviation
Register
000066H
to
00006EH
Read/
Resource name
Write
Initial Value
ROM Mirror
Function
Selection Module
- - - - - - 1 1B
Prohibited
00006FH
ROMM
ROM Mirroring Function Selection
Register
W
000070H
IBSR0
I2C Bus Status Register
R
000071H
000072H
000073H
000074H
IBCR0
ICCR0
IADR0
IDAR0
2
I C Bus Control Register
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
2
R/W
I C Bus Interface XX 0 XXXXXB
2
R/W
XXXXXXXXB
2
R/W
XXXXXXXXB
0 0 0 0 0 0 0 0B
I C Bus Clock Control Register
I C Bus Address Register
I C Bus Data Register
000075H
to
00009AH
2
Prohibited
00009BH
DCSR
DMA Descriptor Channel Specification
Register
R/W
00009CH
DSRL
DMA Status Register Lower
R/W
00009DH
DSRH
DMA Status Register Upper
R/W
00009EH
PACSR
Program Address Detection Control
Status Register
R/W
Address Match
Detection
0 0 0 0 0 0 0 0B
00009FH
DIRR
Delayed Interrupt Source generate/
release Register
R/W
Delayed Interrupt
- - - - - - - 0B
0000A0H
LPMCR
Low Power Consumption Mode Control
Register
R/W
Low Power
Consumption
control circuit
0 0 0 1 1 0 0 0B
0000A1H
CKSCR
Clock Selection Register
R/W
Clock
1 1 1 1 1 1 0 0B
R/W
μDMAC
0 0 0 0 0 0 0 0B
0000A2H
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Prohibited
0000A3H
0000A4H
μDMAC
DSSR
DMA Stop Status Register
0000A5H
to
0000A7H
Prohibited
0000A8H
WDTC
Watchdog Timer Control Register
R/W
Watchdog Timer X - XXX 1 1 1B
0000A9H
TBTC
Time-base Timer Control Register
R/W
Time-base Timer 1 - - 0 0 1 0 0B
0000AAH
Prohibited
0000ABH
0000ACH
DERL
DMA Enable Register Lower
R/W
0000ADH
DERH
DMA Enable Register Upper
R/W
0000AEH
FMCS
Flash Memory Control Status Register
R/W
0000AFH
μDMAC
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Flash Memory I/F 0 0 0 X 0 0 0 0B
Prohibited
(Continued)
DS07-13735-4E
17
MB90335 Series
Address
Register
abbreviation
Read/
Write
0000B0H
ICR00
Interrupt Control Register 00
R/W
0 0 0 0 0 1 1 1B
0000B1H
ICR01
Interrupt Control Register 01
R/W
0 0 0 0 0 1 1 1B
0000B2H
ICR02
Interrupt Control Register 02
R/W
0 0 0 0 0 1 1 1B
0000B3H
ICR03
Interrupt Control Register 03
R/W
0 0 0 0 0 1 1 1B
0000B4H
ICR04
Interrupt Control Register 04
R/W
0 0 0 0 0 1 1 1B
0000B5H
ICR05
Interrupt Control Register 05
R/W
0 0 0 0 0 1 1 1B
0000B6H
ICR06
Interrupt Control Register 06
R/W
0 0 0 0 0 1 1 1B
0000B7H
ICR07
Interrupt Control Register 07
R/W
0000B8H
ICR08
Interrupt Control Register 08
R/W
0000B9H
ICR09
Interrupt Control Register 09
R/W
0 0 0 0 0 1 1 1B
0000BAH
ICR10
Interrupt Control Register 10
R/W
0 0 0 0 0 1 1 1B
0000BBH
ICR11
Interrupt Control Register 11
R/W
0 0 0 0 0 1 1 1B
0000BCH
ICR12
Interrupt Control Register 12
R/W
0 0 0 0 0 1 1 1B
0000BDH
ICR13
Interrupt Control Register 13
R/W
0 0 0 0 0 1 1 1B
0000BEH
ICR14
Interrupt Control Register 14
R/W
0 0 0 0 0 1 1 1B
0000BFH
ICR15
Interrupt Control Register 15
R/W
0 0 0 0 0 1 1 1B
0000C0H
HCNT0
Host Control Register 0
R/W
0 0 0 0 0 0 0 0B
0000C1H
HCNT1
Host Control Register 1
R/W
0 0 0 0 0 0 0 1B
0000C2H
HIRQ
Host Interruption Register
R/W
0 0 0 0 0 0 0 0B
0000C3H
HERR
Host Error Status Register
R/W
0 0 0 0 0 0 1 1B
0000C4H
HSTATE
Host State Status Register
R/W
XX 0 1 0 0 1 0B
0000C5H
HFCOMP
SOF Interrupt FRAME Compare Register
R/W
0 0 0 0 0 0 0 0B
Register
HRTIMER
Retry Timer Setting Register
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
HADR
Host Address Register
HEOF
EOF Setting Register
HFRAME
FRAME Setting Register
HTOKEN
Host Token End Point Register
0000CFH
0000D0H
0000D1H
Interrupt
Controller
R/W
0000C6H
0000C7H
Resource name
R/W
Initial Value
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 0 0 0B
USB HOST
0 0 0 0 0 0 0 0B
R/W
XXXXXX 0 0B
R/W
X 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
XX 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
XXXXX 0 0 0B
R/W
0 0 0 0 0 0 0 0B
Prohibited
UDCC
UDC Control Register
R/W
R/W
USB Function
1 0 1 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Continued)
18
DS07-13735-4E
MB90335 Series
Address
0000D2H
0000D3H
0000D4H
0000D5H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
0000DBH
0000DCH
0000DDH
0000DEH
0000DFH
0000E0H
0000E1H
0000E2H
0000E3H
0000E4H
0000E5H
0000E6H
0000E7H
0000E8H
0000E9H
0000EAH
0000EBH
0000ECH
0000EDH
0000EEH
0000EFH
0000F0H
0000F1H
0000F2H
0000F3H
0000F4H
0000F5H
0000F6H
0000F7H
0000F8H
0000F9H
Register
abbreviation
Register
EP0C
EP0 Control Register
EP1C
EP1 Control Register
EP2C
EP2 Control Register
EP3C
EP3 Control Register
EP4C
EP4 Control Register
EP5C
EP5 Control Register
TMSP
Time Stamp Register
UDCS
UDCIE
UDC Status Register
UDC Interrupt Enable Register
EP0IS
EP0I Status Register
EP0OS
EP0O Status Register
EP1S
EP1 Status Register
EP2S
EP2 Status Register
EP3S
EP3 Status Register
EP4S
EP4 Status Register
EP5S
EP5 Status Register
EP0DT
EP0 Data Register
EP1DT
EP1 Data Register
EP2DT
EP2 Data Register
EP3DT
EP3 Data Register
EP4DT
EP4 Data Register
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W, R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Resource name
Initial Value
USB Function
0 1 0 0 0 0 0 0B
XXXX 0 0 0 0B
0 0 0 0 0 0 0 0B
0 1 1 0 0 0 0 1B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXX0 0 0B
XX0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
1 0 XXX 1 XXB
0 XXXXXXXB
1 0 0 XX 0 0 0B
XXXXXXXXB
1 0 0 0 0 0 0 XB
XXXXXXXXB
1 0 0 0 0 0 0 0B
XXXXXXXXB
1 0 0 0 0 0 0 0B
XXXXXXXXB
1 0 0 0 0 0 0 0B
XXXXXXXXB
1 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
DS07-13735-4E
19
MB90335 Series
Address
0000FAH
0000FBH
Register
abbreviation
EP5DT
Read/
Write
Register
R/W
EP5 Data Register
R/W
0000FCH
to
0000FFH
Prohibited
000100H
to
001100H
RAM Area
Resource name
USB Function
Initial Value
XXXXXXXXB
XXXXXXXXB
Program Address Detection Register
ch.0 Lower
R/W
XXXXXXXXB
Program Address Detection Register
ch.0 Middle
R/W
XXXXXXXXB
001FF2H
Program Address Detection Register
ch.0 Upper
R/W
001FF3H
Program Address Detection Register
ch.1 Lower
R/W
Program Address Detection Register
ch.1 Middle
R/W
XXXXXXXXB
Program Address Detection Register
ch.1 Upper
R/W
XXXXXXXXB
001FF0H
001FF1H
001FF4H
PADR0
PADR1
001FF5H
007900H
PRLL0
PPG Reload Register Lower ch.0
R/W
007901H
PRLH0
PPG Reload Register Upper ch.0
R/W
007902H
PRLL1
PPG Reload Register Lower ch.1
R/W
007903H
PRLH1
PPG Reload Register Upper ch.1
R/W
007904H
PRLL2
PPG Reload Register Lower ch.2
R/W
007905H
PRLH2
PPG Reload Register Upper ch.2
R/W
007906H
PRLL3
PPG Reload Register Lower ch.3
R/W
007907H
PRLH3
PPG Reload Register Upper ch.3
R/W
007908H
to
00790BH
Address Match
Detection
PPG ch.0
PPG ch.1
PPG ch.2
PPG ch.3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Prohibited
00790CH
FWR0
Flash Memory Program Control
Register 0
R/W
Flash
0 0 0 0 0 0 0 0B
00790DH
FWR1
Flash Memory Program Control
Register 1
R/W
Flash
0 0 0 0 0 0 0 0B
00790EH
SSR0
Sector Conversion Setting Register
R/W
Flash
0 0 XXXXX0B
00790FH
to
00791FH
Prohibited
(Continued)
20
DS07-13735-4E
MB90335 Series
(Continued)
Address
Register
abbreviation
Register
Read/
Write
007920H
DBAPL
DMA Buffer Address Pointer Lower 8-bit
R/W
XXXXXXXXB
007921H
DBAPM
DMA Buffer Address Pointer Middle 8-bit
R/W
XXXXXXXXB
007922H
DBAPH
DMA Buffer Address Pointer Upper 8-bit
R/W
XXXXXXXXB
007923H
DMACS
DMA Control Register
R/W
XXXXXXXXB
007924H
DIOAL
DMA I/O Register Address Pointer Lower
8-bit
R/W
007925H
DIOAH
DMA I/O Register Address Pointer
Upper 8-bit
R/W
XXXXXXXXB
007926H
DDCTL
DMA Data Counter Lower 8-bit
R/W
XXXXXXXXB
007927H
DDCTH
DMA Data Counter Upper 8-bit
R/W
XXXXXXXXB
007928H
to
007FFFH
Resource name
μDMAC
Initial Value
XXXXXXXXB
Prohibited
• Explanation on read/write
R/W : Readable and Writable
R
: Read only
W : Write only
• Explanation of initial values
0
: Initial value is “0”.
1
: Initial value is “1”.
X
: Initial value is undefined.
: Initial value is undefined (None).
Note : No I/O instruction can be used for registers located between 007900H and 007FFFH.
DS07-13735-4E
21
MB90335 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
μDMAC
support
Interrupt vector
Interrupt control
register
Number*
Address
ICR
Address
1
Reset
×
×
#08
08H
FFFFDCH
⎯
⎯
INT 9 instruction
×
×
#09
09H
FFFFD8H
⎯
⎯
Exceptional treatment
×
×
#10
0AH
FFFFD4H
⎯
⎯
USB Function1
×
0, 1
#11
0BH
FFFFD0H
USB Function2
×
2 to 6*2
#12
0CH
FFFFCCH
USB Function3
×
×
#13
0DH
FFFFC8H
USB Function4
×
×
#14
0EH
FFFFC4H
USB HOST1
×
×
#15
0FH
FFFFC0H
USB HOST2
×
×
#16
10H
FFFFBCH
I2C ch.0
×
×
#17
11H
FFFFB8H
×
#18
12H
FFFFB4H
⎯
#19
13H
FFFFB0H
×
#20
14H
FFFFACH
⎯
#21
15H
FFFFA8H
×
#22
16H
FFFFA4H
14
#23
17H
FFFFA0H
×
#24
18H
FFFF9CH
DTP/External interrupt ch.0/ch.1
No
⎯
DTP/External interrupt ch.2/ch.3
No
⎯
DTP/External interrupt ch.4/ch.5
PWC/Reload timer ch.0
DTP/External interrupt ch.6/ch.7
No
⎯
⎯
#25
19H
FFFF98H
No
⎯
⎯
#26
1AH
FFFF94H
No
⎯
⎯
#27
1BH
FFFF90H
No
⎯
⎯
#28
1CH
FFFF8CH
No
⎯
⎯
#29
1DH
FFFF88H
×
×
#30
1EH
FFFF84H
⎯
⎯
#31
1FH
FFFF80H
×
×
#32
20H
FFFF7CH
No
⎯
⎯
#33
21H
FFFF78H
No
⎯
⎯
#34
22H
FFFF74H
No
⎯
⎯
#35
23H
FFFF70H
No
⎯
⎯
#36
24H
FFFF6CH
13
#37
25H
FFFF68H
9
#38
26H
FFFF64H
12
#39
27H
FFFF60H
PPG ch.0/ch.1
No
PPG ch.2/ch.3
UART (Send completed) ch.0/ch.1
Extended serial I/O
×
UART(Reception completed)
ch.0/ch.1
Time-base timer
×
×
#40
28H
FFFF5CH
Flash memory status
×
×
#41
29H
FFFF58H
Delay interrupt output module
×
×
#42
2AH
FFFF54H
Priority
High
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
ICR06 0000B6H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
ICR12 0000BCH
ICR13 0000BDH
ICR14 0000BEH
ICR15 0000BFH
Low
(Continued)
22
DS07-13735-4E
MB90335 Series
(Continued)
: Available. EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.
With a stop request).
: Available (The interrupt request flag is cleared by the interrupt clear signal).
: Available when any interrupt source sharing ICR is not used.
× : Unavailable
*1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has
priority.
*2 : Ch.2 and ch.3 can be used in USB HOST operation.
Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted,
the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation
factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt
requests when using the EI2OS.
• The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt
factors in the same interrupt control register (ICR).
• If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are
cleared by the μDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the
DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “ 0 ” in the
appropriate resource, and take measures by software polling.
■ CONTENT OF USB INTERRUPTION FACTOR
USB interrupt factor
Details
USB function 1
End Point 0-IN, End Point 0-OUT
USB function 2
End Point 1-5 *
USB function 3
SUSP, SOF, BRST, WKOP, COHF
USB function 4
SPIT
USB HOST1
DIRQ, CHHIRQ, URIRQ, RWKIRQ
USB HOST2
SOFIRQ, CMPIRQ
* : End Point 1and 2 can be used in USB HOST operation.
DS07-13735-4E
23
MB90335 Series
■ USB
1. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.
Features of USB function
• Supports USB 2.0 Full Speed
• Supports full speed (12 Mbps).
• The device status is auto-answer.
• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16.
• Toggle check by data synchronization bit.
• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these
three commands can be processed the same way as the class vendor commands).
• The class vendor commands can be received as data and responded via firmware.
• Supports up to a maximum of six EndPoints (EndPoint0 is fixed to control transfer).
• Two built-in transfer data buffers for each end point (one IN buffer and one OUT buffer for end point 0).
• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).
24
DS07-13735-4E
MB90335 Series
2. USB HOST
USB HOST provides minimal host operations required and is a function that enables data to be transferred
between devices without PC intervention.
• Features of USB HOST
• Automatic detection of Low Speed/Full Speed transfer
• Low Speed/Full Speed transfer support
• Automatic detection of connection and cutting device
• Reset sending function support to USB-bus
• Support of IN/OUT/SETUP/SOF token
• In-token handshake packet automatic transmission (excluding STALL)
• Handshake packet automatic detection at out-token
• Supports a maximum packet length of 256 bytes
• Error (CRC error/toggle error/time-out) various supports
• Wake-Up function support
• Restrictions on USB HOST
USB HOST
HUB support
*
Bulk transfer
Transfer
Control transfer
Interrupt transfer
Isochronous transfer
Transfer speed
×
Low Speed
Full Speed
×
PRE packet support
SOF packet support
CRC error
Toggle error
Error
Time-out
Maximum packet < receive data
Detection of connection and cutting of device
Transfer speed detection
×
: Supported
: Not supported
* : Only supports full speed, and supports hubs up to one level.
DS07-13735-4E
25
MB90335 Series
■ SECTOR CONFIGURATION OF FLASH MEMORY
512 Kbits flash memory is located in FFH bank in the CPU memory map.
SA1 (4 Kbytes)
SA2 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA5 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4Kbytes)
FF0000H
70000H
FF0FFFH
70FFFH
FF1000H
71000H
FF1FFFH
71FFFH
FF2000H
72000H
FF2FFFH
72FFFH
FF3000H
73000H
FF3FFFH
73FFFH
FF4000H
74000H
FF7FFFH
77FFFH
FF8000H
78000H
FFBFFFH
7BFFFH
FFC000H
7C000H
FFCFFFH
7CFFFH
FFD000H
7D000H
FFDFFFH
7DFFFH
FFE000H
7E000H
FFEFFFH
7EFFFH
FFF000H
7F000H
FFFFFFH
7FFFFH
Upper Bank
SA0 (4 Kbytes)
Lower Bank
Flash Memory CPU address Writer address *
* : Flash memory writer address indicates the address equivalent to the CPU address when data is written
to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel
programmer are executed based on writer addresses.
26
DS07-13735-4E
MB90335 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp
current
“L” level maximum output
current
Rating
Symbol
Unit
Remarks
Min
Max
VSS − 0.3
VSS + 4.0
V
VSS − 0.3
VSS + 4.0
V
*2
VSS − 0.3
VSS + 6.0
V
N-ch open-drain
(Withstand voltage I/O of 5 V)*3
− 0.5
VSS + 4.5
V
USB I/O
VSS − 0.3
VSS + 4.0
V
*2
− 0.5
VSS + 4.5
V
USB I/O
ICLAMP
− 2.0
+2.0
mA
*4
Σ⏐ICLAMP⏐
⎯
20
mA
*4
IOL1
⎯
10
mA
Other than USB I/O*5
IOL2
⎯
43
mA
USB I/O*5
VCC
VI
VO
“L” level average output
current
IOLAV1
⎯
4
mA
*6
IOLAV2
⎯
15/4.5
mA
USB-IO
(Full speed/Low speed) *6
“L” level maximum total
output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*7
IOH1
⎯
− 10
mA
Other than USB I/O*5
IOH2
⎯
− 43
mA
USB I/O*5
“L” level average total
output current
“H” level maximum output
current
“H” level average output
current
IOHAV1
⎯
−4
mA
*6
IOHAV2
⎯
−15/−4.5
mA
USB-IO
(Full speed/Low speed) *6
“H” level maximum total
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
270
mW
Operating temperature
TA
− 40
+ 85
°C
− 55
+ 150
°C
− 55
+ 125
°C
“H” level average total
output current
Storage temperature
Tstg
*7
USB I/O
*1 : The parameter is based on VSS = 0.0 V.
*2 : VI and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*3 : Applicable to pins : P60 to P67, UTEST
(Continued)
DS07-13735-4E
27
MB90335 Series
(Continued)
*4 : •
•
•
•
•
•
•
•
•
•
Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P54
Use within recommended operating conditions.
Use at DC voltage (current)
The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply
is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the +B input pin open.
Note that analog system input/output pins other than P60 to P67, DVP, DVM, HVP, HVM, UTEST, HCON
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*5 : A peak value of an applicable one pin is specified as a maximum output current.
*6 : The average output current specifies the mean value of the current flowing in the relevant single pin during a
period of 100 ms.
*7 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins
during a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
DS07-13735-4E
MB90335 Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
3.0
3.6
V
At normal operation (When using USB)
2.7
3.6
V
At normal operation (When not using USB)
1.8
3.6
V
Hold state of stop operation
VIH
0.7 VCC
VCC + 0.3
V
CMOS input pin
VIHS1
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input pin
VIHS2
0.8 VCC
VSS + 5.3
V
N-ch open-drain
(Withstand voltage I/O of 5 V)*
VIHM
VCC − 0.3
VCC + 0.3
V
MD pin input
VIHUSB
2.0
VCC + 0.3
V
USB pin input
VIL
VSS − 0.3
0.3 VCC
V
CMOS input pin
VILS
VSS − 0.3
0.2 VCC
V
CMOS hysteresis input pin
VILM
VSS − 0.3
VSS + 0.3
V
MD pin input
VILUSB
VSS
0.8
V
USB pin input
Differential input
sensitivity
VDI
0.2
⎯
V
USB pin input
Differential common
mode input voltage
range
VCM
0.8
2.5
V
USB pin input
Operating
temperature
TA
− 40
+ 85
°C
When not using USB
0
+ 70
°C
When using USB
Power supply voltage
Input “H” voltage
Input “L” voltage
VCC
* : Applicable to pins : P60 to P67, UTEST
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13735-4E
29
MB90335 Series
3. DC Characteristics
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Output “H”
voltage
Output “L”
voltage
Input leak
current
Symbol
VOH
VOL
Pin name
Max
VCC − 0.5
⎯
Vcc
V
2.8
⎯
3.6
V
Vss
⎯
Vss + 0.4
V
0
⎯
0.3
V
Input pins other than
VCC = 3.3 V,
P60 to P67, HVP,
Vss < VI < VCC
HVM, DVP, DVM
− 10
⎯
+ 10
μA
HVP, HVM, DVP,
DVM
−5
⎯
+5
μA
25
50
100
kΩ
⎯
0.1
10
μA
⎯
55
65
mA MB90F337
⎯
50
60
mA MB90337
⎯
50
60
mA MB90F337
⎯
45
55
mA MB90337
VCC = 3.3 V,
Internal frequency 24 MHz,
At sleep mode
⎯
25
40
mA
VCC = 3.3 V,
Internal frequency 24 MHz,
At timer mode
⎯
3.5
10
mA
VCC = 3.3 V,
Internal frequency 3 MHz,
At timer mode
⎯
1.0
2.0
mA
TA = +25 °C,
At stop mode
⎯
1
40
μA
Output pins other
than P60 to P67,
HVP, HVM, DVP,
DVM
IOH = −4.0 mA
HVP, HVM, DVP,
DVM
RL = 15 kΩ ± 5%
Output pins other
than HVP, HVM, DVP, IOL = 4.0 mA
DVM
RPULL
Open drain
output leak
current
ILIOD P60 to P67
P00 to P07,
P10 to P17
ICCH
⎯
VCC = 3.3 V,
TA = + 25 °C
⎯
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating
At non-operating USB
(USTP = 1)
VCC
ICTS
RL = 1.5 kΩ ± 5%
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating
At USB operating
(USTP = 0)
ICC
ICCS
Unit Remarks
Typ
Pull-up
resistance
Power
supply
current
Value
Min
HVP, HVM, DVP,
DVM
IIL
Conditions
(Continued)
30
DS07-13735-4E
MB90335 Series
(Continued)
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Value
Conditions
Unit Remarks
Min
Typ
Max
Parameter
Symbol
Input
capacitance
CIN
Other than Vcc and
Vss
⎯
⎯
5
15
pF
Pull-up
resistor
Rup
RST
⎯
25
50
100
kΩ
Pull-down
resistor
Rdown MD2
VCC = 3.0 V
At TA = +25 °C
25
50
100
kΩ MB90337
USB I/O
output
impedance
ZUSB
⎯
3
⎯
14
Ω
Pin name
DVP, DVM
HVP, HVM
Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.
DS07-13735-4E
31
MB90335 Series
4. AC Characteristics
(1) Clock input timing
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Symbol
Pin
name
Clock frequency
fCH
X0, X1
Clock cycle time
tHCYL
X0, X1
Input clock pulse width
PWH
PWL
Input clock rise time and fall
time
Parameter
Value
Unit
Remarks
Min
Typ
Max
⎯
6
⎯
MHz When oscillator is used
6
⎯
24
MHz External clock input
⎯
166.7
⎯
ns
When oscillator is used
166.7
⎯
41.7
ns
External clock input
X0
10
⎯
⎯
ns
A reference duty ratio is
30% to 70%.
tcr
tcf
X0
⎯
⎯
5
ns
At external clock
Internal operating clock
frequency
fCP
⎯
3
⎯
24
Internal operating clock
cycle time
tCP
⎯
42
⎯
333
MHz When main clock is used
ns
When main clock is used
• Clock Timing
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tcf
32
tcr
DS07-13735-4E
MB90335 Series
• PLL operation guarantee range
Relation between power supply voltage and internal operation clock frequency
Power supply voltage VCC (V)
PLL operation guarantee range
3.6
3.0
2.7
Normal operation
assurance range
3
6
12
24
Internal clock fCP (MHz)
Note : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V.
Relation between internal operation clock frequency and external clock frequency
4x
Internal clock fCP (MHz)
24
External clock
2x
12
1x
6
3
24
6
External clock FC (MHz)
The AC standards provide that the following measurement reference voltages.
• Output signal waveform
• Input signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Hysteresis input/other than MD input pin
0.7 VCC
0.3 VCC
DS07-13735-4E
33
MB90335 Series
(2) Reset
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Reset input
time
Symbol
Pin
name
tRSTL
Value
Conditions
RST
Min
Max
Unit
Remarks
500
⎯
ns
At normal operating,
At time base timer mode,
At main sleep mode,
At PLL sleep mode
Oscillation time of
oscillator* + 500 ns
⎯
μs
At stop mode
⎯
* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several
dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a
ceramic oscillator, and 0 milliseconds on an external clock.
• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 VCC
0.2 VCC
• During stop mode
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operation
clock
Oscillation time
of oscillator
500 ns
Oscillation stabilization wait time
Execute instruction
Internal reset
34
DS07-13735-4E
MB90335 Series
(3) Power-on reset
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Power supply rising time
Power supply shutdown time
Symbol
Pin name Conditions
tR
VCC
VCC
tOFF
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
⎯
Remarks
Waiting time
until power-on
Notes : • VCC must be lower than 0.2 V before the power supply is turned on.
• The above standard is a value for performing a power-on reset.
• In the device, there are internal registers which is initialized only by a power-on reset. When the initialization
of these items is expected, turn on the power supply according to the standards.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : Sudden change of power supply voltage may activate the power-on reset function.
When changing the power supply voltage during operation as illustrated below, voltage fluctuation should
be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL
clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
3.0 V
The rising edge should be 50 mV/ms
or less.
RAM data hold
VSS
DS07-13735-4E
35
MB90335 Series
(4) UART0, UART1 I/O extended serial timing
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCKx
SCK ↓ → SOT delay time
tSLOV
SCKx
SOTx
Valid SIN → SCK ↑
tIVSH
SCKx
SINx
SCK ↑ → valid
SIN hold time
tSHIX
Serial clock H pulse width
Value
Conditions
Unit
Min
Max
8 tCP
⎯
ns
− 80
+ 80
ns
100
⎯
ns
SCKx
SINx
60
⎯
ns
tSHSL
SCKx, SINx
4 tCP
⎯
ns
Serial clock L pulse width
tSLSH
SCKx, SINx
4 tCP
⎯
ns
SCK ↓ → SOT delay time
tSLOV
SCKx
SOTx
⎯
150
ns
Valid SIN → SCK ↑
tIVSH
SCKx
SINx
60
⎯
ns
SCK ↑ → valid
SIN hold time
tSHIX
SCKx
SINx
60
⎯
ns
Internal shift clock
Mode output pin is
CL = 80 pF + 1 TTL
External shift clock
Mode output pin is
CL = 80 pF + 1 TTL
Notes : • Above rating is the case of CLK synchronous mode.
• CL is a load capacitance value on pins for testing.
• tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
36
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
DS07-13735-4E
MB90335 Series
(5) I2C timing
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
SCL clock frequency
(Repeat) [start] condition hold
time
SDA ↓ → SCL ↓
Symbol
tHDSTA
tLOW
SCL clock “H” width
tHIGH
Repeat [start] condition setup time
SCL ↑ → SDA ↓
tSUSTA
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
[Stop] condition setup time
SCL ↑ → SDA ↑
Bus free time between [stop]
condition and [start] condition
tSUDAT
tSUSTO
tBUS
Value
Unit
Min
Max
0
100
kHz
4.0
⎯
μs
4.7
⎯
μs
4.0
⎯
μs
4.7
⎯
μs
0
3.45*3
μs
Power-supply of external pull-up resistor
at 5.0 V
fCP*1 ≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply of external pull-up resistor
at 3.6 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
250*4
⎯
Power-supply of external pull-up resistor
at 5.0 V
fCP*1 > 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply of external pull-up resistor
at 3.6 V
fCP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2
200*4
⎯
4.0
⎯
μs
4.7
⎯
μs
fSCL
SCL clock “L” width
Data setup time
SDA ↓ ↑ → SCL ↑
Conditions
Power-supply of external pull-up resistor
at 5.0 V
R = 1.2 kΩ, C = 50 pF*2
Power-supply of external pull-up resistor
at 3.6 V
R = 1.0 kΩ, C = 50 pF*2
Power-supply of external pull-up resistor
at 5.0 V
R = 1.2 kΩ, C = 50 pF*2
Power-supply of external pull-up resistor
at 3.6 V
R = 1.0 kΩ, C = 50 pF*2
ns
*1 : fCP is internal operating clock frequency. Refer to “ (1) Clock input timing”.
*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA, SCL set-up time”.
DS07-13735-4E
37
MB90335 Series
•Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
•Timing definition
SDA
tLOW
tBUS
tHDSTA
tSUDAT
SCL
tHDSTA
38
tHDDAT
tHIGH
tSUSTA
tSUSTO
DS07-13735-4E
MB90335 Series
(6) Timer Input Timing
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Symbol
Pin name
Conditions
tTIWH
tTIWL
PWC
⎯
Input pulse width
Value
Min
Max
4 tCP
⎯
Unit
ns
Note : tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
PWC
tTIWH
tTIWL
(7) Timer output timing
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Symbol
Pin name
Conditions
tTO
PPGx
⎯
CLK ↑ → TOUT change time
PPG0 to PPG3 change time
Value
Min
Max
30
⎯
Unit
ns
2.4 V
CLK
tTO
2.4 V
0.8 V
PPGx
(8) Trigger Input Timing
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)
Parameter
Input pulse width
Symbol
tTRGH
tTRGL
Pin name Conditions
INTx
⎯
Value
Unit
Remarks
Min
Max
5 tCP
⎯
ns
At normal operating
1
⎯
μs
At Stop mode
Note : tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
INTx
tTRGH
DS07-13735-4E
tTRGL
39
MB90335 Series
5. USB characteristics
(VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
Min
Max
Input High level voltage
VIH
2.0
⎯
V
Input Low level voltage
VIL
⎯
0.8
V
Differential input sensitivity
VDI
0.2
⎯
V
Differential common mode range
VCM
0.8
2.5
V
Output High level voltage
VOH
2.8
3.6
V
IOH = −200 μA
Output Low level voltage
VOL
0.0
0.3
V
IOL = 2 mA
Cross over voltage
VCRS
1.3
2.0
V
tFR
4
20
ns
Full Speed
tLR
75
300
ns
Low Speed
tFF
4
20
ns
Full Speed
tLF
75
300
ns
Low Speed
tRFM
90
111.11
%
(TFR/TFF)
tRLM
80
125
%
(TLR/TLF)
ZDRV
28
44
Ω
Including Rs = 27 Ω
RS
25
30
Ω
Recommended value
= 27 Ω at using USB*
Symbol
Input
characteristics
Value
Symbol
Parameter
Rise time
Output
characteristics
Fall time
Rising/falling time matching
Output impedance
Series resistance
Unit
Remarks
* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV.
• Data signal timing (Full Speed)
Rise time
DVP/HVP
90%
VCRS
Fall time
90%
10%
10%
DVM/HVM
tFF
tFR
• Data signal timing (Low Speed)
Rise time
HVP
HVM
90%
VCRS
90%
10%
10%
tLR
40
Fall time
tLF
DS07-13735-4E
MB90335 Series
• Load condition (Full Speed)
ZUSB
DVP/HVP
RS = 27 Ω
Testing point
CL = 50 pF
ZUSB
DVM/HVM
RS = 27 Ω
Testing point
CL = 50 pF
• Load condition (Low Speed)
ZUSB
HVP
RS = 27 Ω
Testing point
CL = 50 pF ∼ 150 pF
ZUSB
HVM
RS = 27 Ω
Testing point
CL = 50 pF ∼ 150 pF
DS07-13735-4E
41
MB90335 Series
6. Flash memory write/erase characteristics
Parameter
Condition
Value
Unit
Remarks
0.5
s
Excludes 00H programming
prior to erasure.
0.5
7.5
s
Excludes 00H programming
prior to erasure.
⎯
2.6
⎯
s
Excludes 00H programming
prior to erasure.
⎯
16
3600
μs
Except for over head time of
system
⎯
10000
⎯
⎯
cycle
Average
TA = + 85 °C
20
⎯
⎯
year
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2
Sector erase time
(16 Kbytes sector)
⎯
Chip erase time
TA = + 25 °C
VCC = 3.0 V
Word (8 bits width)
programming time
Program/erase cycle
Flash data retention time
*
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
42
DS07-13735-4E
MB90335 Series
■ ORDERING INFORMATION
Part number
Package
MB90F337PMC
MB90337PMC
64-pin plastic LQFP
(FPT-64P-M23)
MB90V330ACR
299-pin ceramic PGA
(PGA-299C-A01)
DS07-13735-4E
Remarks
For evaluation
43
MB90335 Series
■ PACKAGE DIMENSION
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
64
17
1
"A"
16
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
©2003-2008
FUJITSU
LIMITED F64034S-c-1-2
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F64034S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
44
DS07-13735-4E
MB90335 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Changed the USB.
USB Mini-Host → USB HOST
11
■ HANDLING DEVICES
Added the item “9. Serial communication”.
⎯
■ PERIPHERAL RESOURCES
Deleted the section.
■ USB
Changed the item name from “PERIPHERAL RESOURCES” to
“USB Function”.
2. USB HOST
Changed the title of the table:
Differences between the USB HOST and USB Mini-HOST →
Restrictions on USB HOST
Changed “HUB support”.
×→ *
Added the following under the table:
“* : Only supports full speed, and supports hubs up to one level.”
26
■ SECTOR CONFIGURATION OF
FLASH MEMORY
Changed the item name from “PERIPHERAL RESOURCES” to
“SECTOR CONFIGURATION OF FLASH MEMORY”.
30
Corrected the column of pin name of Input leak current param■ ELECTRICAL CHARACTERISTICS
eter.
3. DC Characteristics
Output pins → Input pins
24, 25
The vertical lines marked in the left side of the page show the changes.
DS07-13735-4E
45
MB90335 Series
MEMO
46
DS07-13735-4E
MB90335 Series
MEMO
DS07-13735-4E
47
MB90335 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
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http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
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Edited: Sales Promotion Department