FUJITSU SEMICONDUCTOR DATA SHEET DS07-13711-1E 16-Bit Original Microcontroller CMOS F2MC-16LX MB90420G/5G (A) Series MB90423G/423GA/F423G/F423GA/V420G MB90427G/427GA/428G/428GA/F428G/F428GA ■ DESCRIPTIONS The FUJITSU MB90420G/5G (A) Series is a 16-bit general purpose high-capacity microcontroller designed for vehicle meter control applications etc. The instruction set retains the same AT architecture as the FUJITSU original F2MC-8L and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced (signed) multipler-divider computation and bit processing. In addition, A 32-bit accumulator is built in to enable long word processing. ■ FEATURES • 16-bit input capture (4 channels) Detects rising, falling, or both edges. 16-bit capture register × 4 Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request. • 16-bit reload timer (2 channels) 16-bit reload timer operation (select toggle output or one-shot output) Event count function selection provided (Continued) ■ PACKAGES Plastic QFP, 100-pin Plastic LQFP, 100-pin (FPT-100P-M06) (FPT-100P-M05) MB90420G/5G (A) Series • Clock timer (main clock) Operates directly from oscillator clock. Compensates for oscillator deviation Read/write enabled second/minute/hour register Signal interrupt • 16-bit PPG (3 channels) Output pins (3) , external trigger input pin (1) Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26 • Delay interrupt Generates interrupt for task switching. Interruptions to CPU can be generated/deleted by software setting. • External interrupts (8 channels) 8-channel independent operation Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level. • A/D converter 10-bit or 8-bit resolution × 8 channels (input multiplexed) Conversion time : 6.13 µs or less (at fCP = 16 MHz) External trigger startup available (P50/INT0/ADTG) Internal timer startup available (16-bit reload timer 1) • UART (2 channels) Full duplex double buffer type Supports asynchronous/synchronous transfer (with start/stop bits) Internal timer can be selected as clock (16-bit reload timer 0) Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps Synchronous : 500 Kbps, 1Mbps, 2Mbps (at fCP = 16 MHz) • CAN interface *1 Conforms to CAN specifications version 2.0 Part A and B. Automatic resend in case of error. Automatic transfer in response to remote frame. 16 prioritized message buffers for data and messages for data and ID Multiple message support Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks Supports up to 1 Mbps CAN WAKEUP function (connects RX internally to INT0) • LCD controller/driver (1 channel) Segment driver and command driver with direct LCD panel (display) drive capability • Low voltage/Program Looping detect reset *2 Automatic reset when low voltage is detected Program Looping detection function • Stepping motor controller (4 channels) High current output for all channels × 4 Synchronized 8/10-bit PWM for all channels × 2 • Sound generator 8-bit PWM signal mixed with tone frequency from 8-bit reload counter. PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16MHz) Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1) (Continued) 2 MB90420G/5G (A) Series (Continued) • Input/output ports Push-pull output and Schmitt trigger input Programmable in bit units for input/output or peripheral signals. • Flash memory Supports automatic programming, Embeded AlgorithmTM, write/erase/erase pause/erase resume instructions Flag indicates algorithm completion Minato Electronics flash writer Boot block configuration Erasable by blocks Block protection by external programming voltage *1 : MB90420G (A) series has 2 channels built-in, MB90425G (A) series has 1 channel built-in *2 : Built-in to MB90420GA/5GA series only. Not built-in to MB90420G/5G series. Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc. 3 MB90420G/5G (A) Series ■ PRODUCT LINEUP • MB90420G (A) Series Part number MB90V420G Parameter Configuration MB90F423G *1 Evaluation model MB90423G *2 Flash ROM model CPU System clock MB90F423GA *1 MB90423GA *2 Mask ROM model 2 F MC-16LX CPU On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4) ROM External Flash ROM 128 KB Mask ROM 128 KB RAM 6 KB 6 KB 6 KB CAN interface 2 channels Low voltage/ CPU operation detection reset No Packages Emulator dedicated power supply* No QFP100, LQFP100 No Yes MB90F428GA MB90427G*2 MB90427GA*2 MB90428G*1 MB90428GA*1 Flash ROM model CPU System clock No PGA-256 • MB90425G (A) Series Part number MB90F428G Parameter Configuration Yes Mask ROM model 2 F MC-16LX CPU On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4) ROM Flash ROM 128 KB Mask ROM 64 KB Mask ROM 128 KB RAM 6 KB 4 KB 6 KB CAN interface Low voltage/ CPU operation detection reset Packages Emulator dedicated power supply* 1 channel No Yes No Yes No Yes QFP100, LQFP100 * : When used with evaluation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-507 Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) . *1 : Under development *2 : Planned 4 MB90420G/5G (A) Series ■ PIN ASSIGNMENTS (TOP VIEW) VSS X0 X1 VCC P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1 P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 COM0 COM1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C P90/SEG22 P91/SEG23 V0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A P57/SGA RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS P53/INT3 MD2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 MD1 MD0 P52/INT2 (/TX1) P51/INT1 (/RX1) P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P50/INT0/ADTG AVRH AVCC V3 V2 V1 (FPT-100P-M06) (Continued) 5 MB90420G/5G (A) Series (Continued) (TOP VIEW) P57/SGA 76 X1A 77 X0A 78 VSS 79 X0 80 X1 81 VCC 82 P00/SIN0/INT4 83 P01/SOT0/INT5 84 P02/SCK0/INT6 85 P03/SIN1/INT7 86 P04/SOT1 87 P05/SCK1/TRG 88 P06/PPG0/TOT1 89 P07/PPG1/TIN1 90 P10/PPG2 91 P11/TOT0/WOT 92 P12/TIN0/IN3 93 P13/IN2 94 P14/IN1 95 P15/IN0 96 COM0 97 COM1 98 COM2 99 COM3 100 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P53/INT3 MD2 MD1 MD0 P52/INT2 (/TX1) P51/INT1 (/RX1) P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P50/INT0/ADTG AVRH AVCC V3 V2 V1 V0 P91/SEG23 P90/SEG22 (FPT-100P-M05) 6 RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS MB90420G/5G (A) Series ■ PIN DESCRIPTIONS Pin no. Symbol LQFP QFP 80 82 X0 81 83 X1 78 80 X0A Circuit type A A 77 79 X1A 75 77 RST B P00 83 84 85 86 85 86 87 88 SIN0 89 G 89 90 91 93 Reset input pin. UART ch.0 serial data input pin. General purpose input/output port. SOT0 G UART ch.0 serial data output pin. INT5 INT5 external interrupt input pin. P02 General purpose input/output port. SCK0 G UART ch.0 serial clock input/output pin. INT6 INT6 external interrupt input pin. P03 General purpose input/output port. SIN1 G P04 SOT1 SCK1 UART ch.1 serial data input pin. INT7 external interrupt input pin. G General purpose input/output port. UART ch.1 serial data output pin. General purpose input/output port. G UART ch.1 serial clock input/output pin. TRG 16-bit PPG ch.0-2 external trigger input pin. P06 General purpose input/output port. PPG0 G PPG1 P10 PPG2 16-bit PPG ch.0 output pin. 16-bit reload timer ch.1 TOT output pin. General purpose input/output port. G TIN1 91 Low speed oscillator output pin. If no oscillator is connected, leave open. P01 P07 92 Low speed oscillator input pin. If no oscillator is connected, apply pull-down processing. INT4 external interrupt input pin. TOT1 90 High speed oscillator output pin. INT4 P05 88 High speed oscillator input pin. General purpose input/output port. INT7 87 Description 16-bit PPG ch.1 output pin. 16-bit reload timer ch.1 TIN output pin. G General purpose input/output port. 16-bit PPG ch.2 output pin. (Continued) 7 MB90420G/5G (A) Series Pin no. LQFP QFP Symbol Circuit type P11 92 93 94 95 TOT0 Description General purpose input/output port. G 16-bit reload timer ch.0 TOT output pin. WOT Real-time clock timer WOT output pin. P12 General purpose input/output port. TIN0 G IN3 P13 to P15 16-bit reload timer ch.0 TIN output pin. Input capture ch.3 trigger input pin. 96 to 98 97 to 100 99 to 100, 1 to 2 COM0 to COM3 I LCD controller/driver common output pins. 1 to 8, 10 to 13 3 to 10, 12 to 15 SEG0 to SEG11 I LCD controller/driver segment output pins. IN2 to IN0 G General purpose input/output ports. 94 to 96 P36 to P37 14 to 15 16 to 17 16 to 20, 22 to 24 18 to 22, 24 to 26 SEG12 to SEG13 General purpose output ports. E P40 to P47 SEG14 to SEG21 28 to 29 SEG22 to SEG23 E 36 INT0 E 38 to 41, 43 to 46 G General purpose input output ports. F P51 45 47 INT1 G INT2 General purpose input output port. G (TX1 *) 50 52 P53 INT3 INT1 external interrupt input pin. CAN interface 1 RX intput pin. P52 48 A/D converter input pins. General purpose input output port. (RX1 *) 46 INT0 external interrupt input pin. A/D converter external trigger input pin. P60 to P67 AN0 to AN7 LCD controller/driver segment output pins. General purpose input output ports. ADTG 36 to 39, 41 to 44 LCD controller/driver segment output pins. General purpose input output ports. P50 34 LCD controller/driver segment output pins. General purpose input output ports. P90 to P91 26 to 27 Input capture ch.0-2 trigger input pins. INT2 external interrupt input pin. CAN interface 1 TX output pin. G General purpose input output port. INT3 external interrupt input pin. * : MB90420G (A) series only. (Continued) 8 MB90420G/5G (A) Series Pin no. LQFP QFP Symbol Circuit type P70 to P73 52 to 55 54 to 57 PWM1P0 PWM1M0 PWM2P0 PWM2M0 General purpose input output ports. H P74 to P77 57 to 60 59 to 62 PWM1P1 PWM1M1 PWM2P1 PWM2M1 64 to 67 PWM1P2 PWM1M2 PWM2P2 PWM2M2 H 69 to 72 72 74 73 75 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P54 TX0 P55 RX0 H 76 SGO H G G Stepping motor controller ch.3 output pins. General purpose input output port. CAN interface 0 TX output pin. General purpose output port. CAN interface 0 RX input pin. General purpose input output port. G FRCK P57 Stepping motor controller ch.2 output pins. General purpose input output ports. P56 74 Stepping motor controller ch.1 output pins. General purpose input output ports. P84 to P87 67 to 70 Stepping motor controller ch.0 output pins. General purpose input output ports. P80 to P83 62 to 65 Description Sound generator SG0 output pin. Free-run timer clock input pin. 78 28 to 31 30 to 33 V0 to V3 LCD controller /driver reference power supply pins. 56, 66 58, 68 DVCC High current output buffer with dedicated power supply input pins (pin numbers 54-57, 59-62, 64-67, 69-72) . DVSS High current output buffer with dedicated power supply GND pins (pin numbers 54-57, 59-62, 64-67, 69-72) . 51, 61, 71 53, 63, 73 SGA G General purpose input output port. 76 Sound generator SGA output pin. 32 34 AVCC A/D converter dedicated power supply input pin. 35 37 AVSS A/D converter dedicated GND supply pin. 33 35 AVRH A/D converter Vref + input pin. Vref − AVss. (Continued) 9 MB90420G/5G (A) Series (Continued) Pin no. Symbol Circuit type 49 50 MD0 MD1 B* Test mode input pins. Connect to VCC. 49 51 MD2 D* Text mode input pin. Connect to VSS. 25 27 C External capacitor pin. Connect an 0.1 µF capacitor between this pin and VSS. 21, 82 23, 84 VCC Power supply input pins. VSS GND power supply pins. LQFP QFP 47 48 9, 40, 79 11, 42, 81 * : Type C in the flash ROM models. 10 Description MB90420G/5G (A) Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation feedback resistance : approx. 1 MΩ X1 A X0 Standby control signal • Pull-up resistance attached : approx. 50 kΩ, hysteresis input B Hysteresis input • Hysteresis input C Hysteresis input Hyteresis input D • Pull-down resistance attached : approx. 50 kΩ, hysteresis input • No pull-down resistance on flash models. • CMOS output • LCDC output • Hysteresis input E LCDC output Hysteresis input (Continued) 11 MB90420G/5G (A) Series (Continued) Type Circuit Remarks • CMOS output • Hysteresis input • Analog input F Analog input Hysteresis input • CMOS output • Hysteresis input G Hysteresis input • CMOS high current output • Hysteresis input High current H Hysteresis input • LCDC output I 12 LCDC output MB90420G/5G (A) Series ■ HANDLING DEVICES When handling semiconductor devices, care must be taken with regard to the following ten matters. • Strictly observe maximum rated voltages (prevent latchup) • Stable supply voltage • Power-on procedures • Treatment of unused input pins • Treatment of A/D converter power supply pins • Use of external clock signals • Power supply pins • Proper sequence of A/D converter power supply analog input • Handling the power supply for high-current output buffer pins (DVCC, DVSS) • Pull-up/pull-down resistance • Precautions when not using a sub clock signal. Precautions for Handling Semiconductor Devices • Strictly observe maximum rated voltages (prevent latchup) When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AVCC, AVRH, DVCC) and analog input do not exceed the digital power supply (VCC) . Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH,DVCC) may be turned on in any sequence. • Stable supply voltage Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage can cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial frequencies (50 to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less. • Power-on procedures In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during poweron should be attained within 50 µs (0.2 V to 2.7 V) . • Treatment of unused input pins If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 kΩ. Also any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins. • Treatment of A/D converter power supply pins Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS. 13 MB90420G/5G (A) Series • Use of external clock signals Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and the X1 pin should be left open, as shown in Figure 3. X0 X1 OPEN MB90420G/425G (A) Series Sample external clock connection • Power supply pins Devices are designed to prevent problems such as latchup when multiple VCC and VSS supply pins are used, by providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all such pins should always be connected externally to power supplies and ground. As shown in Figure 4, all VCC power supply pins must have the same potential. All VSS power supply pins should be handled in the same way. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted operating range. VCC VSS VCC VSS VSS VCC VCC VSS VSS VCC Power supply input pins (VCC/VSS) In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and VSS as close to the pins as possible. • Proper sequence of A/D converter power supply analog input A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off before the digital power supply is switched on (VCC) . In both power-on and shut-off, care should be taken that AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, be sure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digital power supplies are turned off and on at the same time.) 14 MB90420G/5G (A) Series • Handling the power supply for high-current output buffer pins (DVCC, DVSS) Always apply power to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is turned on. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DVCC, DVSS) before switching off the digital power supply (VCC) . (There will be no problem if high-current output buffer pins and digital power supplies are turned off and on at the same time.) Even when high-current output buffer pins are used as general purpose ports, the power for high current output buffer pins (DVCC, DVSS) should be applied to these pins. • Pull-up/pull-down resistance The MB90420G/5G series does not support internal pull-up/pull-down resistance. If necessary, use external components. • Precautions for when not using a sub clock signal. If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave the X1A pin open. 15 MB90420G/5G (A) Series ■ BLOCK DIAGRAM P57/SGA P56/SGO/FRCK P55/RX0 P54/TX0 P53/INT3 P52/INT2 (/TX1) P51/INT1 (/RX1) P50/INT0/ADTG P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1 Clock control circuit CPU F2MC-16LX core RAM Interrupt controller ROM Low voltage detector reset Sound generator CAN controller Port 5 External interrupt (8 ch) Port 8 Stepping motor Controller 0/1/2/3 UART0/1 Prescaler 0/1 Port 0 PPG0/1/2 P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 F2MC-16LX BUS X0, X1 X0A, X1A RST Port 7 A/D converter (8 ch) P67 - P60/ AN7 - AN0 AVCC/AVSS AVRH Port 9 P91 - P90/ SEG23 - SEG22 Port 4 P47 - P40/ SEG21 - SEG14 Port 3 P37 - P36/ SEG13 - SEG12 Real-time Clock timer ICU0/1/2/3 Free-run timer Evaluation device (MB90V420G) No built-in ROM Built-in RAM is 6 KB. 16 P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 Port 6 Port 1 Reload timer 0/1 P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 LCD controller/ driver SEG11 - SEG0 COM3 - COM0 V3 - V0 MB90420G/5G (A) Series ■ MEMORY MAP Single chip mode (with ROM mirror function) 000000H Peripheral area 0000C0H 000100H Register RAM area Address #2 003900H Peripheral area 004000H 010000H ROM area (FF bank image) FF0000H Address #1 ROM area FFFFFFH : Internal access memory : Access prohibited Parts No. Address #1 Address #2 MB90423G (A) FE0000H 001900H MB90427G (A) FF0000H 001100H MB90428G (A) FE0000H 001900H MB90F423G (A) FE0000H 001900H MB90F428G (A) FE0000H 001900H MB90V420G FE0000H * 001900H * : MB90V420G has no built-in ROM. On the tool side this area may be considered a ROM decoder. Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH. 17 MB90420G/5G (A) Series ■ I/O MAP • Other than CAN Interface Address Register name Symbol Read/write Peripheral function Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 - - XX XX XX (Disabled) 02H 03H Port 3 data register PDR3 R/W Port 3 XX - - - - - - 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 - - - - - -XX 0AH to 0FH (Disabled) 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 - - 000000 12H (Disabled) 13H Port 3 direction register DDR3 R/W Port 3 00 - - - - - - 14H Port 4 direction register DDR4 R/W Port 4 00000000 15H Port 5 direction register DDR5 R/W Port 5 00000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 00000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 - - - - - - 00 1AH Analog input enable ADER R/W Port 6, A/D 11111111 1BH to 1FH (Disabled) 20H A/D control status register lower ADCSL R/W 21H A/D control status register higher ADCSH R/W 22H A/D data register lower ADCRL R 23H A/D data register higher ADCRH R/W 0 0 1 0 1 XXX Compare clear register CPCLR R/W XXXXXXXX R/W XXXXXXXX 24H 25H 26H R/W 00000000 A/D converter 16-bit free-run timer 00000000 XXXXXXXX 00000000 Timer data register TCDT 28H Timer control status register lower TCCSL R/W 00000000 29H Timer control status register higher TCCSH R/W 0- - 00000 27H R/W 00000000 (Continued) 18 MB90420G/5G (A) Series Address Register name Symbol Read/write Peripheral function 2AH PPG0 control status register lower PCNTL0 R/W 2BH PPG0 control status register higher PCNTH0 R/W 2CH PPG1 control status register lower PCNTL1 R/W 2DH PPG1 control status register higher PCNTH1 R/W 2EH PPG2 control status register lower PCNTL2 R/W 2FH PPG2 control status register higher PCNTH2 R/W 30H External interrupt enable ENIR R/W 31H External interrupt request EIRR R/W 32H External interrupt level lower ELVRL R/W 33H External interrupt level higher ELVRH R/W 00000000 34H Serial mode register 0 SMR0 R/W 00000-00 35H Serial control register 0 SCR0 R/W 00000100 36H Input data register 0/ Output data register 0 SIDR0/ SODR0 R/W 37H Serial status register 0 SSR0 R/W 00001000 38H Serial mode register 1 SMR1 R/W 00000−00 39H Serial control register 1 SCR1 R/W 00000100 3AH Input data register 1/ Output data register 1 SIDR1/ SODR1 R/W 3BH Serial status register 1 SSR1 R/W 16-bit PPG0 16-bit PPG1 16-bit PPG2 Initial value 00000000 000000000000000 000000000000000 000000000000000 External interrupt UART 0 UART1 XXXXXXXX 00000000 XXXXXXXX XXXXXXXX 00001000 (Disabled) 3CH 3DH Clock division control register 0 CDCR0 R/W Prescaler 0---0000 3EH CAN wake-up control register CWUCR R/W CAN - - - - - - - 0 3FH Clock division control register 1 CDCR1 R/W Prescaler 0---0000 40H to 4FH Area reserved for CAN interface 0 50H Timer control status register 0 lower TMCSR0L R/W 51H Timer control status register 0 highTMCSR0H er R/W 53H Timer register 0/ Reload register 0 R/W 54H Timer control status register 1 lower TMCSR1L R/W 55H Timer control status register 1 highTMCSR1H er R/W 57H Timer register 1/ Reload register 1 TMR1/ TMRLR1 R/W 58H Clock timer control register lower WTCRL R/W 59H Clock timer control register higher WTCRH R/W 52H 56H TMR0/ TMRLR0 00000000 16-bit reload timer 0 - - - 00000 XXXXXXXX XXXXXXXX 00000000 16-bit reload timer 1 - - - 00000 XXXXXXXX XXXXXXXX Real-time clock timer 000- - 000 00000000 (Continued) 19 MB90420G/5G (A) Series Address Register name Symbol Read/write Peripheral function Initial value 5AH Sound control register lower SGCRL R/W 00000000 5BH Sound control register higher SGCRH R/W 0 - - - - - 00 5CH Frequency data register SGFR R/W 5DH Amplitude data register SGAR R/W 5EH Decrement grade register SGDR R/W XXXXXXXX 5FH Tone count register SGTR R/W XXXXXXXX Input capture register 0 IPCP0 R 60H 61H 62H 63H 64H 65H 66H 67H 68H Input capture register 1 IPCP1 R Input capture register 2 IPCP2 R IPCP3 R Input capture control status 0/1 ICS01 R/W 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input capture 2/3 Input capture register 3 XXXXXXXX XXXXXXXX Input capture 0/1 69H 6AH Sound generator XXXXXXXX XXXXXXXX XXXXXXXX Input capture 0/1 00000000 Input capture 2/3 00000000 LCD controller/ driver 00010000 (Disabled) Input capture control status 2/3 ICS23 6BH R/W (Disabled) 6CH LCDC control register lower LCRL R/W 6DH LCDC control register higher LCRH R/W 6EH Low voltage detect reset control register LVRC R/W Low voltage detect reset 10111000 6FH ROM mirror ROMM W ROM mirror XXXXXXX1 70H to 7FH 80H Area reserved for CAN interface 1 PWM control register 0 81H 82H PWM control register 1 87H to 9DH R/W Stepping motor controller0 00000--0 PWC1 R/W Stepping motor controller1 00000--0 Stepping motor controller2 00000--0 Stepping motor controller3 00000--0 (Disabled) PWM control register 2 85H 86H PWC0 (Disabled) 83H 84H 00000000 PWC2 R/W (Disabled) PWM control register 3 PWC3 R/W (Disabled) (Continued) 20 MB90420G/5G (A) Series (Continued) Address Register name Symbol Read/write Peripheral function Initial value PACSR R/W Address match detection function - - - - - 0-0 DIRR R/W Delayed interrupt - - - - - - -0 Power saving mode LPMCR R/W 00011000 Clock select CKSCR R/W Power saving control circuit 11111100 9EH ROM correction control register 9FH Delay interrupt/release A0H A1H A2H to A7H (Disabled) A8H Watchdog control WDTC R/W Watchdog timer XXXXX 1 1 1 A9H Time base timer control register TBTC R/W Time base timer 1 - - 00100 AAH Clock timer control register WTC R/W Clock timer (sub clock) 1X000000 Flash interface 0 0 0 X 0 XX 0 ABH to ADH AEH (Disabled) Flash control register AFH FMCS R/W (Disabled) B0H Interrupt control register 00 ICR00 R/W 00000111 B1H Interrupt control register 01 ICR01 R/W 00000111 B2H Interrupt control register 02 ICR02 R/W 00000111 B3H Interrupt control register 03 ICR03 R/W 00000111 B4H Interrupt control register 04 ICR04 R/W 00000111 B5H Interrupt control register 05 ICR05 R/W 00000111 B6H Interrupt control register 06 ICR06 R/W 00000111 B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 00000111 BAH Interrupt control register 10 ICR10 R/W 00000111 BBH Interrupt control register 11 ICR11 R/W 00000111 BCH Interrupt control register 12 ICR12 R/W 00000111 BDH Interrupt control register 13 ICR13 R/W 00000111 BEH Interrupt control register 14 ICR14 R/W 00000111 BFH Interrupt control register 15 ICR15 R/W 00000111 C0H to FFH Interrupt controller 00000111 00000111 (Disabled) 21 MB90420G/5G (A) Series Address Register name Symbol Read/write Peripheral function Initial value 1FF0H ROM correction address 0 PADR0 R/W XXXXXXXX 1FF1H ROM correction address 1 PADR0 R/W XXXXXXXX 1FF2H ROM correction address 2 PADR0 R/W 1FF3H ROM correction address 3 PADR1 R/W 1FF4H ROM correction address 4 PADR1 R/W XXXXXXXX 1FF5H ROM correction address 5 PADR1 R/W XXXXXXXX 3900H to 391FH 3920H 3921H 3922H 3923H 3924H 3925H 3929H 392AH 392BH 392CH 392DH PPG0 down counter register PDCR0 R PPG0 cycle setting register PCSR0 W PPG0 duty setting register PDUT0 W 3931H 3932H 3933H 3934H 3935H 3936H to 3959H XXXXXXXX 11111111 11111111 16-bit PPG 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Disabled) PPG1 down counter register PDCR1 R PPG1 cycle setting register PCSR1 W PPG1 duty setting register PDUT1 W 392EH to 392FH 3930H XXXXXXXX (Disabled) 3926H to 3927H 3928H Address match detection function 11111111 11111111 16-bit PPG 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Disabled) PPG2 down counter register PDCR2 R PPG2 cycle setting register PCSR2 W PPG2 duty setting register PDUT2 W 11111111 11111111 16 bit PPG 2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Disabled) (Continued) 22 MB90420G/5G (A) Series Address Register name Symbol Read/write Peripheral function 395AH 395BH Initial value XXXXXXXX Sub second data register WTBR R/W 395CH XXXXXXXX Real time clock timer - - - XXXXX 395DH Second data register WTSR R/W 395EH Minute data register WTMR R/W - - XXXXXX 395FH Hour data register WTHR R/W - - - XXXXX 3960H to LCD display RAM 396FH VRAM R/W 3970H to 397FH 3980H LCD controller/ driver - - XXXXXX XXXXXXXX (Disabled) XXXXXXXX PWM1 compare register 0 PWC10 R/W PWM2 compare register 0 PWC20 R/W 3984H PWM1 select register 0 PWS10 R/W - - 000000 3985H PWM2 select register 0 PWS20 R/W -0000000 3981H 3982H 3983H 3986H to 3987H 3988H - - - - - - XX Stepping motor controller 0 XXXXXXXX - - - - - - XX (Disabled) XXXXXXXX PWM1 compare register 1 PWC11 R/W PWM2 compare register 1 PWC21 R/W 398CH PWM1 select register 1 PWS11 R/W --000000 398DH PWM2 select register 1 PWS21 R/W -0000000 3989H 398AH 398BH 398EH to 398FH 3990H - - - - - - XX Stepping motor controller 1 XXXXXXXX - - - - - - XX (Disabled) XXXXXXXX PWM1 compare register 2 PWC12 R/W PWM2 compare register 2 PWC22 R/W 3994H PWM1 select register 2 PWS12 R/W --000000 3995H PWM2 select register 2 PWS22 R/W -0000000 3991H 3992H 3993H 3996H to 3997H - - - - - - XX Stepping motor controller 2 XXXXXXXX - - - - - - XX (Disabled) (Continued) 23 MB90420G/5G (A) Series (Continued) Address 3998H Register name Symbol Read/write Peripheral function Initial value XXXXXXXX PWM1 compare register 3 PWC13 R/W PWM2 compare register 3 PWC23 R/W 399CH PWM1 select register 3 PWS13 R/W --000000 399DH PWM2 select register 3 PWS23 R/W -0000000 3999H 399AH 399BH - - - - - - XX Stepping motor controller 3 399EH to 39FFH (Disabled) 3A00H to 3AFFH Area reserved for CAN interface 0 3B00H to 3BFFH Area reserved for CAN interface 1 3C00H to 3CFFH Area reserved for CAN interface 0 3D00H to 3DFFH Area reserved for CAN interface 1 3E00H to 3EFFH (Disabled) XXXXXXXX - - - - - - XX • Initial value symbols : “0” initial value 0. “1” initial value 1. “X” initial value undetermined “-” initial value undetermined (none) • Write/read symbols : “R/W” read/write enabled “R” read only “W” write only • Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited. 24 MB90420G/5G (A) Series • I/O Map for CAN Interface Address CAN0 CAN1 000040H 000070H 000041H 000071H 000042H 000072H 000043H 000073H 000044H 000074H 000045H 000075H 000046H 000076H 000047H 000077H 000048H 000078H 000049H 000079H 00004AH 00007AH 00004BH 00007BH 00004CH 00007CH 00004DH 00007DH 00004EH 00007EH 00004FH 00007FH 003C00H 003D00H 003C01H 003D01H 003C02H 003D02H 003C03H 003D03H 003C04H 003D04H 003C05H 003D05H 003C06H 003D06H 003C07H 003D07H 003C08H 003D08H 003C09H 003D09H 003C0AH 003D0AH 003C0BH 003D0BH 003C0CH 003D0CH 003C0DH 003D0DH 003C0EH 003D0EH 003C0FH 003D0FH Register name Symbol Read/ write Initial value Message buffer valid area BVALR (R/W) 00000000 00000000 Transmission request register TREQR (R/W) 00000000 00000000 Transmission cancel register TCANR (W) 00000000 00000000 Transmission completed register TCR (R/W) 00000000 00000000 Receiving completed register RCR (R/W) 00000000 00000000 Remote request receiving register RRTRR (R/W) 00000000 00000000 Receiving overrun register ROVRR (R/W) 00000000 00000000 Receiving interrupt enable register RIER (R/W) 00000000 00000000 Control status register CSR (R/W, R) 00---000 0----0-1 Last event indicator register LEIR (R/W) -------- 000-0000 RX/TX error counter RTEC (R) 00000000 00000000 Bit timing register BTR (R/W) -1111111 11111111 IDE register IDER (R/W) Transmission RTR register TRTRR (R/W) Remote frame receiving wait register RFWTR (R/W) Transmission interrupt enable register TIER (R/W) XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX 00000000 00000000 (Continued) 25 MB90420G/5G (A) Series Address CAN0 CAN1 003C10H 003D10H 003C11H 003D11H 003C12H 003D12H 003C13H 003D13H 003C14H 003D14H 003C15H 003D15H 003C16H 003D16H 003C17H 003D17H 003C18H 003D18H 003C19H 003D19H 003C1AH 003D1AH Register name Acceptance mask select register Acceptance mask register 0 Acceptance mask register 1 Symbol AMSR AMR0 AMR1 Read/ write 003B00H to General purpose RAM 003B1FH 003A20H 003B20H 003A21H 003B21H 003A22H 003B22H 003A23H 003B23H 003A24H 003B24H 003A25H 003B25H 003A26H 003B26H 003A27H 003B27H 003A28H 003B28H 003A29H 003B29H 003A2AH 003B2AH ID register 0 ID register 1 ID register 2 IDR0 IDR1 IDR2 003A2FH 003B2FH 003A30H 003B30H 003A31H 003B31H 003A32H 003B32H 003A33H 003B33H ID register 3 ID register 4 IDR3 IDR4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) (R/W) XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) (R/W) (R/W) 003A2CH 003B2CH 003A2EH 003B2EH XXXXXXXX (R/W) 003A2BH 003B2BH 003A2DH 003B2DH XXXXXXXX (R/W) 003C1BH 003D1BH 003A00H to 003A1FH Initial value (R/W) (R/W) (Continued) 26 MB90420G/5G (A) Series Address CAN0 CAN1 003A34H 003B34H 003A35H 003B35H 003A36H 003B36H 003A37H 003B37H 003A38H 003B38H 003A39H 003B39H 003A3AH 003B3AH Register name ID register 5 ID register 6 Symbol IDR5 IDR6 Read/ write 003A3FH 003B3FH 003A40H 003B40H 003A41H 003B41H 003A42H 003B42H 003A43H 003B43H 003A44H 003B44H 003A45H 003B45H 003A46H 003B46H 003A47H 003B47H 003A48H 003B48H 003A49H 003B49H 003A4AH 003B4AH ID register 7 ID register 8 ID register 9 ID register 10 IDR7 IDR8 IDR9 IDR10 003A4FH 003B4FH 003A50H 003B50H 003A51H 003B51H 003A52H 003B52H 003A53H 003B53H ID register 11 ID register 12 IDR11 IDR12 XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) (R/W) (R/W) 003A4CH 003B4CH 003A4EH 003B4EH XXXXX- - - (R/W) 003A4BH 003B4BH 003A4DH 003B4DH XXXXXXXX (R/W) 003A3CH 003B3CH 003A3EH 003B3EH XXXXXXXX (R/W) 003A3BH 003B3BH 003A3DH 003B3DH Initial value (R/W) (R/W) (Continued) 27 MB90420G/5G (A) Series Address CAN0 CAN1 003A54H 003B54H 003A55H 003B55H 003A56H 003B56H 003A57H 003B57H 003A58H 003B58H 003A59H 003B59H 003A5AH 003B5AH Register name ID register 13 ID register 14 Symbol IDR13 IDR14 Read/ write 003A5FH 003B5FH 003A60H 003B60H 003A61H 003B61H 003A62H 003B62H 003A63H 003B63H 003A64H 003B64H 003A65H 003B65H 003A66H 003B66H 003A67H 003B67H 003A68H 003B68H 003A69H 003B69H 003A6AH 003B6AH 003A6BH 003B6BH 003A6CH 003B6CH 003A6DH 003B6DH 003A6EH 003B6EH 003A6FH 003B6FH 003A70H 003B70H 003A71H 003B71H 003A72H 003B72H 003A73H 003B73H 003A74H 003B74H 003A75H 003B75H ID register 15 IDR15 XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) 003A5CH 003B5CH 003A5EH 003B5EH XXXXXXXX (R/W) 003A5BH 003B5BH 003A5DH 003B5DH Initial value (R/W) DLC register 0 DLCR0 (R/W) - - - -XXXX - - - -XXXX DLC register 1 DLCR1 (R/W) - - - -XXXX - - - -XXXX DLC register 2 DLCR2 (R/W) - - - -XXXX - - - -XXXX DLC register 3 DLCR3 (R/W) - - - -XXXX - - - -XXXX DLC register 4 DLCR4 (R/W) - - - -XXXX - - - -XXXX DLC register 5 DLCR5 (R/W) - - - -XXXX - - - -XXXX DLC register 6 DLCR6 (R/W) - - - -XXXX - - - -XXXX DLC register 7 DLCR7 (R/W) - - - -XXXX - - - -XXXX DLC register 8 DLCR8 (R/W) - - - -XXXX - - - -XXXX DLC register 9 DLCR9 (R/W) - - - -XXXX - - - -XXXX DLC register 10 DLCR10 (R/W) - - - -XXXX - - - -XXXX (Continued) 28 MB90420G/5G (A) Series Address CAN0 CAN1 003A76H 003B76H 003A77H 003B77H 003A78H 003B78H 003A79H 003B79H 003A7AH 003B7AH 003A7BH 003B7BH 003A7CH 003B7CH 003A7DH 003B7DH 003A7EH 003B7EH Symbol Read/ write DLC register 11 DLCR11 (R/W) - - - -XXXX - - - -XXXX DLC register 12 DLCR12 (R/W) - - - -XXXX - - - -XXXX DLC register 13 DLCR13 (R/W) - - - -XXXX - - - -XXXX DLC register 14 DLCR14 (R/W) - - - -XXXX - - - -XXXX DLC register 15 DLCR15 (R/W) - - - -XXXX - - - -XXXX Register name Initial value 003A7FH 003B7FH 003A80H to 003A87H 003B80H to Data register 0 (8 bytes) 003B87H DTR0 (R/W) XXXXXXXX to XXXXXXXX 003A88H to 003A8FH 003B88H to Data register 1 (8 bytes) 003B8FH DTR1 (R/W) XXXXXXXX to XXXXXXXX 003A90H to 003A87H 003B90H to Data register 2 (8 bytes) 003B97H DTR2 (R/W) XXXXXXXX to XXXXXXXX 003A98H to 003A9FH 003B98H to Data register 3 (8 bytes) 003B9FH DTR3 (R/W) XXXXXXXX to XXXXXXXX 003AA0H 003BA0H to to Data register 4 (8 bytes) 003AA7H 003BA7H DTR4 (R/W) XXXXXXXX to XXXXXXXX 003AA8H 003BA8H to to Data register 5 (8 bytes) 003AAFH 003BAFH DTR5 (R/W) XXXXXXXX to XXXXXXXX 003AB0H 003BB0H to to Data register 6 (8 bytes) 003AB7H 003BB7H DTR6 (R/W) XXXXXXXX to XXXXXXXX 003AB8H 003BB8H to to Data register 7 (8 bytes) 003ABFH 003BBFH DTR7 (R/W) XXXXXXXX to XXXXXXXX 003AC0H 003BC0H to to Data register 8 (8 bytes) 003AC7H 003BC7H DTR8 (R/W) XXXXXXXX to XXXXXXXX 003AC8H 003BC8H to to Data register 9 (8 bytes) 003ACFH 003BCFH DTR9 (R/W) XXXXXXXX to XXXXXXXX (Continued) 29 MB90420G/5G (A) Series (Continued) Address Symbol Read/ write Initial value 003AD0H 003BD0H to to Data register 10 (8 bytes) 003AD7H 003BD7H DTR10 (R/W) XXXXXXXX to XXXXXXXX 003AD8H 003BD8H to to Data register 11 (8 bytes) 003ADFH 003BDFH DTR11 (R/W) XXXXXXXX to XXXXXXXX 003AE0H 003BE0H to to Data register 12 (8 bytes) 003AE7H 003BE7H DTR12 (R/W) XXXXXXXX to XXXXXXXX 003AE8H 003BE8H to to Data register 13 (8 bytes) 003AEFH 003BEFH DTR13 (R/W) XXXXXXXX to XXXXXXXX 003AF0H to 003AF7H 003BF0H to Data register 14 (8 bytes) 003BF7H DTR14 (R/W) XXXXXXXX to XXXXXXXX 003AF8H 003BF8H to to Data register 15 (8 bytes) 003AFFH 003BFFH DTR15 (R/W) XXXXXXXX to XXXXXXXX CAN0 30 CAN1 Register name MB90420G/5G (A) Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source EI2OS compatible Interrupt vector Number Address Interrupt control register Priority ICR Address *2 High Reset × #08 08H FFFFDCH INT9 instruction × #09 09H FFFFD8H Exception processing × #10 0AH FFFFD4H CAN0 RX × #11 0BH FFFFD0H CAN0 TX/NS × #12 0CH FFFFCCH ICR00 0000B0H *1 CAN1 RX × #13 0DH FFFFC8H CAN1 TX/NS × #14 0EH FFFFC4H ICR01 0000B1H *1 Input capture 0 #15 0FH FFFFC0H DTP/external interrupt - ch 0 detected #16 10H FFFFBCH ICR02 0000B2H *1 Reload timer 0 #17 11H FFFFB8H DTP/external interrupt - ch 1 detected #18 12H FFFFB4H ICR03 0000B3H *1 Input capture 1 #19 13H FFFFB0H DTP/external interrupt - ch 2 detected #20 14H FFFFACH ICR04 0000B4H *1 Input capture 2 #21 15H FFFFA8H DTP/external interrupt - ch 3 detected #22 16H FFFFA4H ICR05 0000B5H *1 Input capture 3 #23 17H FFFFA0H DTP/external interrupt - ch 4/5 detected #24 18H FFFF9CH ICR06 0000B6H *1 PPG timer 0 #25 19H FFFF98H DTP/external interrupt - ch 6/7 detected #26 1AH FFFF94H ICR07 0000B7H *1 PPG timer 1 #27 1BH FFFF90H Reload timer 1 #28 1CH FFFF8CH ICR08 0000B8H *1 PPG timer 2 #29 1DH FFFF88H ICR09 0000B9H *1 ICR10 0000BAH *1 ICR11 0000BBH *1 ICR12 0000BCH *1 ICR13 0000BDH *1 ICR14 0000BEH *1 ICR15 0000BFH *1 Real time clock timer × #30 1EH FFFF84H Free-run timer over flow × #31 1FH FFFF80H #32 20H FFFF7CH A/D converter conversion end Free-run timer clear × #33 21H FFFF78H Sound generator × #34 22H FFFF74H Time base timer × #35 23H FFFF70H Clock timer (sub clock) × #36 24H FFFF6CH UART 1 RX #37 25H FFFF68H UART 1 TX #38 26H FFFF64H UART 0 RX #39 27H FFFF60H UART 0 TX #40 28H FFFF5CH Flash memory status × #41 29H FFFF58H Delayed interrupt generator module × #42 2AH FFFF54H Low 31 MB90420G/5G (A) Series : Compatible, with EI2OS stop function : Compatible : Compatible when interrupt sources sharing ICR are not in use × : Not compatible *1 : • Peripheral functions sharing the ICR register have the same interrupt level. • If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other cannot be used. • When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services, the interrupt from the other function cannot be used. *2 : Priority applies when interrupts of the same level are generated. 32 MB90420G/5G (A) Series ■ PERIPHERAL FUNCTIONS 1. I/O Ports The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in bit units by the port direction register (DDR) as required. The following list shows each of the functions as well as the shared peripheral function for each port. • • • • • • • • • Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG) Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/clock timer/ICU) Port 3 : General purpose I/O port, shared with peripheral functions (LCD) Port 4 : General purpose I/O port, shared with peripheral functions (LCD) Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG) Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter) Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) Port 9 : General purpose I/O port, shared with peripheral functions (LCD) (1) List of Functions Port Pin name Input format Output format Function General purpose I/O port P00/SIN0/INT4 Port 0 to P07/PPG1 Peripheral function General purpose I/O port P10/PPG2 to Port 1 P15/IN0 Port 3 P36/SEG12 to P37/SEG13 Port 4 P40/SEG14 to P47/SEG21 Peripheral function CMOS (hysteresis) Peripheral function P60/AN0 to P67/AN7 Port 7 P70/PWM1P0 to P77/PWM2M1 Port 8 P80/PWM1P2 to P87/PWM2M3 Port 9 P90/SEG22 to P91/SEG23 bit12 P15 P14 IN0 IN1 P37 P36 SEG13 SEG12 Peripheral function P57 P56 P55 P54 SGA SGO RX0 TX0 FRCK General purpose I/O port Peripheral function P77 P76 P75 P74 PWM2M1 PWM2P1 PWM1M1 PWM1P1 General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function CMOS (hysteresis) bit13 Peripheral function Analog CMOS (hysteresis) bit14 General purpose I/O port CMOS General purpose I/O port P50/INT0 to Port 5 P57/SGA Port 6 General purpose I/O port bit15 33 MB90420G/5G (A) Series (Continued) Port bit11 Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P07 P06 P05 P04 P03 P02 P01 P00 PPG1 PPG0 SCK1 SOT1 SIN1 SCK0 SOT0 SIN0 TIN1 TOT1 INT7 INT6 INT5 INT4 P13 P12 P11 P10 IN2 IN3 WOT PPG2 TIN0 TOT0 P47 P46 P45 P44 P43 P42 P41 P40 P53 P52 P51 P50 INT3 INT2 INT1 INT0 TX1 RX1 P67 P66 P65 P64 P63 P62 P61 P60 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 P73 P72 P71 P70 PWM2M0 PWM2P0 PWM1M0 PWM1P0 P87 P86 P85 P84 P83 P82 P81 P80 PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2 P91 P90 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write “0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset. 34 MB90420G/5G (A) Series (2) Block Diagrams Ports 0, 1, 3, 4, 5, 7, 8, 9 Peripheral function output Peripheral function input Peripheral function output enabled Internal data bus PDR (Port data register) PDR read Output latch PDR write Pin DDR (Port direction register) Direction latch DDR write DDR read Standby control (SPL = 1) or LCD output enabled Port 6 ADER Internal data bus PDR (Port data register) Analog input RDR read Output latch PDR write Pin DDR (Port direction register) Direction latch DDR write DDR read Standby control (SPL = 1) 35 MB90420G/5G (A) Series 2. Watchdog Timer/Time Base Timer/Clock Timer The watchdog timer, timer base timer, and clock timer have the following circuit configuration. • Watchdog timer : Watchdog counter, control register, watchdog reset circuit • Time base timer : 18-bit timer, interval interrupt control circuit • Clock timer : 15-bit timer, interval interrupt control circuit (1) Watchdog timer function The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit time base timer or 15-bit clock timer as a clock source, plus a control register and watchdog reset control circuit. After startup, this function will reset the CPU if not cleared within a given time. (2) Time base timer function The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock (base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register. (3) Clock timer function The clock timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator stabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the clock timer uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register. 36 MB90420G/5G (A) Series • Block Diagram Main base oscillator divided by 2 TBTC TBC1 Selector TBC0 TBR TBIE AND Q 211 213 216 218 TBTRES Clock input Time base timer 211 213 216 218 S R TBOF Time base interrupt WDTC WT1 Selector 2-bit counter OF CLR WT0 Watchdog reset generator circuit CLR WTE To WDGRST internal reset generator circuit F2MC-16LX bus WTC WDCS SCE AND Q SGW Power-on reset, sub-clock stop S R WTC2 Selector WTC0 WTR WTIE WTOF Clock interrupt AND Q S R 28 29 210 211 212 213 214 216 WTRES 210 213 214 216 Clock timer Clock input Sub base oscillator divided by 4 WDTC PONR From power-on generator WRST ERST RST pin SRST From RST bit in STBYC register 37 MB90420G/5G (A) Series 3. Input Capture This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits. (1) Input capture ( × 4) The input capture circuits consist of four independent external input pins and corresponding capture registers and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be generated. • The valid edge (rising edge, falling edge, both edges) of the external signal can be selected. • The four input capture circuits can operate independently. • The interrupt can be generated from the valid edge of the external input signal. (2) 16-bit free-run timer ( × 1) The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and prescaler. The output values from this counter are used as the base time for the input capture circuits. • The counter clock operation can be selected from 8 options. The eight internal clock settings are φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle. • Interrupts can be generated from overflow events, or from compare match events with the compare register. (Compare match operation requires a mode setting.) • The counter value can be initialized to “0000H” by a reset, soft clear, or a compare match with the compare register. (3) Block diagram φ interrupt #31 (1FH) IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Divider Clock 16-bit free-run timer F2MC-16LX bus 16-bit compare clear register Interrupt #33 (21H) Compare circuit MSI3 ∼ 0 ICLR ICRE A/D startup Edge detection IN0/2 Capture data register 0/2 EG11 EG10 EG01 Edge detection Capture data register 1/3 ICP0 ICP1 ICE0 EG00 IN1/3 ICE1 Interrupt #19, #23 Interrupt #15, #21 38 MB90420G/5G (A) Series 4. 16-bit Reload Timer The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in internal clock mode, or count down at the detection of the designated edge of an external signal. The user may select either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus an underflow occurs when counting from the value [Reload register setting + 1]. A selection of two counter operating modes are available. In reload mode, the counter is reset to the count value and continues counting after an underflow, and in one-shot mode the count stops after an underflow. The counter can generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services (EI2OS) . (1) 16-bit Reload timer operating modes Clock mode Counter mode Reload mode Internal clock mode Event count mode (external clock mode) One-shot mode Reload mode One-shot mode 16-bit reload timer operation Soft trigger operation External trigger operation External gate input operation Soft trigger operation (2) Internal clock mode One of three input clocks is selected as the count clock, and can be used in one of the following operations. • Soft trigger operation When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation starts.Trigger input at the TRG bit is normally valid with an external trigger input, as well as an external gate input. • External trigger operation Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin. • External gate input operation Counting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin. (3) Event count mode (External clock mode) In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at the TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used. (4) Counter operation • Reload mode In down count operation, when an underflow event (transition from “0000H” to “FFFFH”) occurs, the set count value is reloaded and count operation continues. The function can be used as an interval timer by generating an interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can be output from the TOT0/1 pin. Counter clock Counter clock period Interval time Internal clock 21/φ (0.125 µs) 0.125 µs to 8.192 ms 2 /φ (0.5 µs) 0.5 µs to 32.768 ms 2 /φ (2.0 µs) 2.0 µs to 131.1 ms 23/φ or greater (0.5 µs) 0.5 µs or greater 3 5 External clock φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz. 39 MB90420G/5G (A) Series (5) One-shot mode In down count operation, the count stops when an underflow event (transition from “0000H” to “FFFFH”) occurs. This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave form indicating that the count is in progress can be output form the TOT0 and TOT1 pins. (6) Block diagram Internal data bus TMRLR0 *1 <TMRLR1> 16-bit reload register Reload signal Reload control circuit TMR0 *1 <TMR1> 16-bit timer register (down counter) Count clock generator circuit Machine clock φ Prescaler CLK Gate input 3 UF Valid clock decision circuit Wait signal To UART 0, 1 *1 <To A/D converter> CLK Clear Internal clock Pins P12/TIN0 *1 <P07/TIN1> Input control circuit Clock selector 2 Operation control circuit CSL1 CSL0 WOD2 WOD1 WOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TNGSR0) *1 <TNGSR1> *1 : Channel 0 and channel 1. Figures in < > are for channel 1. *2 : Interrupt number 40 P11/TOT0 *1 <P06/TOT1> Select signal Function selection Pins EN External clock 3 Output signal generator Inverted circuit Interrupt request signal #17 (11h) *2 <#28 (10h)> MB90420G/5G (A) Series 5. Real Time Clock Timer The real time clock timer is composed of a real time clock timer control register, sub second data register, second/ minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Because the MCU oscillation frequency operates on a given real time clock timer operation, a 4 MHz frequency is assumed. The real time clock timer operates as a real world timer and provides real world time information. • Block diagram OE Main oscillator clock 1/2 clock divider 21-bit prescaler CO OE WOT EN Sub second register UPDT ST Second CI EN counter LOAD Hour counter Minute counter CO 6-bit CO 6-bit CO 5-bit Second/minute/hour register INTE0 INT0 INTE1 INT1 INTE2 INT2 INT3 INT3 IRQ 41 MB90420G/5G (A) Series 6. PPG Timer The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting, and 16-bit compare register with buffer for duty setting, plus pin control circuits. The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output pulse can be adjusted by rewriting the values in the two 16-bit registers. (1) PWM function Programmable to output a pulse, synchronized with a trigger. Can also be used as a D/A converter with an external circuit. (2) One-shot function Detects the edge of a trigger input, and outputs a single pulse. (3) Pin control • Set to “1” at a duty match (priority) . • Reset to “0” at a counter borrow event • Has a fixed output mode to output a simple all “L” ( or “H”) signal. • Polarity can be specified (4) 16-bit down counter • Select from four types of counter operation clocks. Four internal clocks (φ, φ/4, φ/16, φ/64) cycles. • The counter value can be initialized to “FFFFH” at a reset or counter borrow event. φ : Machine clock (5) Interrupt requests • Timer startup • Counter borrow event (period match) • Duty match event • Counter borrow event (period match) or duty match event (6) Multiple channels can be set to start up at an external trigger, or to restart during operation. 42 MB90420G/5G (A) Series (7) Block diagram PCSR PDUT Prescaler 1/1 1/4 CK 1/16 Load PSCT 16-bit down counter 1/32 Start CMP Borrow PPG mask Machine clock S PPG output Q R Inversion bit Enable Trigger input P05/TRG Interrupt selection Interrupt Edge detection Soft trigger 43 MB90420G/5G (A) Series 7. Delayed Interrupt Generator Module The delayed interrupt generator module is a module that generates interrupts for task switching. This module makes it possible to use software to generate/cancel interrupt requests to the F2MC-16LX CPU. • Block diagram F2MC-16LX bus Delayed interrupt source generate/delete decoder Source latch 44 MB90420G/5G (A) Series 8. DTP/External Interrupt Circuit The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected peripheral device and the F2MC-16LX CPU and sends interrupt requests or data transfer requests generated from the peripheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligent I/O services (EI2OS) . (1) DTP/external interrupt function The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source. And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an external interrupt or start the expanded intelligent I/O service (EI2OS) . When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI2OS) is prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the EI2OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, then branching to an interrupt routine after the completion of the specified number of data transfers. External interrupt Input pins Interrupt sources DTP function 8 pins (P50/INT0 to P53/INT3, P00/INT4 to P03 INT7) Request level setting register (ELVR) sets the detection level, or selected edge for each pin “H” level/ “L” level/ rising edge/falling edge input “H” level/ “L” level input Interrupt numbers #16 (10H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH) Interrupt control DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output Interrupt flags DTP/interrupt enable register (EIRR) stores interrupt sources Process selection When EI2OS prohibited (ICR : ISE = 0) When EI2OS is enabled (ICR : ISE = 1) Processing Branch to external interrupt processing routine EI2OS performs automatic data transfer, then after a specified number of cycles, branches to an interrupt routine ICR : Interrupt control register 45 MB90420G/5G (A) Series (2) Block diagram Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin Selector Selector Internal data bus P03/INT7 Pin P50/INT0 Pin Selector Selector P02/INT6 Pin P51/INT1 Selector Pin Selector P01/INT5 Pin P52/INT2 Selector Pin Selector Pin P00/INT4 P53/INT3 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request number #16 (10H) #18 (12H) #20 (14H) #22 (16H) #24 (18H) #26 (1AH) EN7 46 EN6 EN5 EN4 EN3 EN2 EN1 EN0 MB90420G/5G (A) Series 9. 8/10-bit A/D Converter The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analog input voltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, and the conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input from an external signal pin. (1) 8/10-bit A/D converter functions The A/D converter takes analog voltage signals (input voltage) input at analog input pins, and converts these to digital values, providing the following features. • Minimum conversion time is 6.13 µs (at machine clock frequency of 16 MHz, including sampling time) . • Minimum sampling time is 3.75 µs (at machine clock 16 MHz) • The conversion method is an RC sequential conversion in comparison with a sample hold circuit. • Either 10-bit or 8-bit resolution can be selected. • The analog input pin can select from 8 channels by a program setting. • At completion of A/D conversion, an interrupt request can be generated, or EI2OS can be started. • Because the conversion data protection function operates in an interrupt enabled state, no data is lost even in continuous conversion. • The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external trigger input (falling edge) . Three conversion modes are available Conversion mode Single conversion operation Single conversion mode Scan conversion operation Converts multiple consecutive channels (up Converts the specified channel (1 channel to 8 channels may be specified) one time, only) one time, then stops. then stops. Continuous conversion Converts the specified channel (1 channel Converts multiple consecutive channels (up mode only) repeatedly. to 8 channels may be specified) repeatedly. Converts multiple consecutive channels (up Converts the specified channel (1 channel to 8 channels may be specified) , however Stop conversion mode only) one time, then pauses, waits until pauses after conversion of each channel, the next start is applied. waits until the next start is applied. 47 MB90420G/5G (A) Series (2) Block diagram AVCC AVRH AVSS D/A converter Input circuit MPX Sequential comparator register Comparator Decoder Sample & hold circuit A/D data register ADCRH, L A/D control status register, high A/D control status register, low 16-bit reload timer 1 Timer start P50/ADTG φ 48 ADCSH, L Operating clock Trigger start Prescaler F2MC-16LX bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 MB90420G/5G (A) Series 10. UART The UART is a general purpose serial data communication interface for synchronous communication, or asynchronous (start-stop synchronized) communication with external devices. Functions include normal bi-directional functions, as well as master/slave type communication functions (multi-processor mode : master side only supported) . (1) UART Functions The UART is a general purpose serial data communication interface for sending and receiving of serial data with other CPU’s or peripheral devices, and provides the following functions. Functions Data buffer Transfer modes Baud rate Data length Signal type Receiving error detection Interrupt request Master/slave type communication function (multi-processor mode) Full duplex double buffer • Clock synchronous (no start/stop bits) • Clock asynchronous (start-stop synchronized) • Exclusive baud rate generator provides a selection of 8 rates • External clock input enabled • Internal clock (can use internal clock feed from 16-bit reload timer) • 7-bit (asynchronous normal mode only) • 8-bit NRZ (Non return to zero) • Framing errors • Overrun errors • Parity errors (not enabled in multiprocessor mode) • Receiving interrupt (receiving completed, receiving error detection) • Sending interrupt (sending completed) • Sending/receiving both compatible with expanded intelligent I/O services (EI2OS) 1 (master) -to-n (slave) communication enabled (only master side supported) . Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only. Operating mode 0 1 Normal mode Multi-processor mode Data length No parity Parity 7-bit or 8-bit 8+1* 1 Synchronization Asynchronous Asynchronous 2 Normal mode 8 Synchronous : Setting not available *1 : “+” indicates an address/data selection bit (A/D) for communication control. *2 : In receiving only one stop bit is detected. Stop bit length 1-bit or 2-bit *2 None 49 MB90420G/5G (A) Series (2) Block diagram Control bus Exclusive baud rate generator Receiving interrupt signals #39 (27H) * <#37 (25H) *> Sending interrupt signals #40 (28H) * <#38 (26H) *> Sending clock Clock selector 16-bit reload timer Pins P02/SCK0 <P05/SCK1> Receiving clock Receiving control circuit Sending control circuit Start bit detection circuit Sending start circuit Receiving bit counter Sending bit counter Receiving parity counter Sending parity counter Pin P01/SOT0 <P04/SOT1> Receiving shift register Pins P00/SIN0 <P03/SIN1> Sending shift register Receiving end SIDR0/1 Sending start SODR0/1 Receiving status judging circuit EI2OS receiving error generator circuit (to CPU) Internal data bus SMR0/1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE ∗: Interrupt number 50 SCR0/1 register PEN P SBL CL A/D REC RXE TXE SSR0/1 register PE ORE FRE RDRF TDRE BOS RIE TIE MB90420G/5G (A) Series 11. CAN Controller The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controller area network) controller is the standard protocol for serial transmissions among automotive controllers and is widely used in the industry. (1) CAN controller features The CAN controller has the following features. • Conforms to CAN specifications version 2.0 A and B. Supports sending and receiving in standard frame and expanded frame format. • Supports data frame sending by means of remote frame receiving. • 16 sending/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration • Supports full bit compare, full bit mask as well as partial bet mask filtering. Provides two receiving mask registers for either standard frame or expanded frame format. • Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz) • CAN WAKE UP function • The MB90420G (A) series has a two-channel built-in CAN controller. The MB90425G (A) series has a 1channel built-in CAN controller. 51 MB90420G/5G (A) Series (2) Block diagram F2MC-16LX bus Machine clock PSC PR PH RSJ TOE TS RS CSR HALT NIE NT NS1,0 TQ (operating clock) Prescaler 1-to-64 frequency divider Bit timing generator SYNC, TSEG1, TSEG2 BTR Node status change interrupt generator Bus state machine Node status change interrupt Error control RTEC Send/receive sequencer BVALR TREQR TBFx clear Send buffer decision TBFX Data counter TCANR TRTRR TCR TBFx, set, clear TIER Sending completed interrupt generator RCR RBFx, set RIER Receiving completed interrupt generator RRTRR RBFx, TBFx, set clear IDR0 ~ 15, DLCR0 ~ 15, DTR0 ~ 15, RAM LEIR 52 ARBLOST RBFx set TDLC RDLC Receiving completed interrupt Receiving bufferx decision RBFX RAM address generator ACK CRCER CRC generator error check Receiving shift register IDSEL Receiving filter TX generator generator ARBLOST 0 1 Output driver Stuffing CRC Sending completed interrupt AMSR AMR1 Overload frame generator Send shift register RFWTR AMR0 Error frame generator Receiving filter control TDLC RDLC IDSEL BITER, STFER, CRCER, FRMER, ACKER TBFX ROVRR IDLE, SUSPND, TX, RX, ERR, OVRLD BITER ACKER FRMER RBFX, TBFX, RDLC, TDLC, IDSEL STFER Destuffing/ stuffing error check Arbitration check Bit error check Acknowledge error check PH1 Form error check Input latch RX MB90420G/5G (A) Series 12. LCD Controller/Driver The LCD controller/driver has a built-in 16 × 8-bit display data memory, and controls the LCD display by means of four common outputs and 24 segment outputs. A selection of three duty outputs are available. This block can drive an LCD (liquid crystal display) panel directly. (1) LCD controller/driver functions The LCD controller/driver provides functions for directly displaying the contents of display data memory (display RAM) on the LCD panel by means of segment output and common output. • LCD drive voltage divider resistance is built-in. External divider resistance can also be connected. • Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used. • 16-byte display data memory (display RAM) is built-in. • The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) . • Drives the LCD directly. Bias 1/2 duty 1/2 bias 1/3 bias : Recommended mode × : Use prohibited 1/3 duty 1/4 duty × × × Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they cannot be used for segment output. 53 MB90420G/5G (A) Series (2) Block diagram V0 V1 V2 V3 LCDC control register L (LCRL) Divider resistance 4 Prescaler Timing controller Common driver 24 Display RAM, 16 × 8 bits Segment driver LCDC control register H (LCRH) Controller 54 COM0 COM1 COM2 COM3 AC circuit Internal data bus Time base timer output Driver SEG0 SEG1 SEG2 SEG3 SEG4 ∼ SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 MB90420G/5G (A) Series 13. Low voltage/Program Looping Detection Reset Circuit The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal is generated. The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal reset signal if not cleared within a given time after startup. (1) Low voltage detection reset circuit Detection voltage 4.0 V ± 0.3 V When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an internal reset signal is output. Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage condition generates an internal reset and releases stop mode. During an internal RAM write cycle, an internal reset is generated after the completion of writing. During the output of this internal reset, the reset output from the low voltage detection circuit is suppressed. (2) Program Looping detection reset circuit The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has a width of 5 machine cycles. Interval duration Number of oscillation clock cycles Approx. 262 ms * 220 cycles * : This value assumes an oscillation clock speed of 4 MHz. During recovery from standby mode the detection period is the maximum interval plus 20 µs. This circuit does not operate in modes where CPU operation is stopped. The Program Looping detection reset circuit counter is cleared under any of the following conditions. 1. Writing “0” to the LVRC register CL bit 2. Internal reset 3. Main oscillation clock stop 4. Transition to sleep mode 5. Transition to time base timer mode or clock mode 6. Start of hold 55 MB90420G/5G (A) Series (3) Block diagram Voltage comparator circuit VCC − + VSS Constant voltage source Program Looping detection circuit Oscillation clock Counter Internal reset OF Noise canceller Clear RESV0 RESV0 RESV1 RESV1 CL LVRF RESV0 CPUF Low voltage detection reset control register (LVRC) Internal data bus 56 MB90420G/5G (A) Series 14. Stepping Motor Controller The stepping motor controller is composed of two PWM pulse generators, four motor drivers and selector logic circuits. The four motor drivers have a high output drive capacity and can be directly connected to the four ends of two motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse generators. • Block diagram Machine clock OE1 Prescaler CK PWM1Pn PWM1 pulse generator EN P1 Output enable Selector PWM PWM1Mn P0 PWM1 compare register PWM1 selector register OE2 Output enable CK SC PWM2Pn PWM2 pulse generator CE EN Selector PWM PWM2Mn Load PWM2 compare register BS PWM2 select register n:0~3 57 MB90420G/5G (A) Series 15. Sound Generator The sound generator is composed of a sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter, and tone pulse counter. • Block diagram Clock input Prescaler S1 S0 8-bit PWM pulse generator CO EN PWM CI Frequency counter Toggle flip-flop CO EN Reload Amplitude data register Reload Q 1/d Frequency data register DEC DEC Decrement counter D EN CI CO EN SGA OE1 Decrement grade register Tone pulse counter Tone count register Blend TONE OE1 SGO OE2 OE2 CI CO EN INTE INT ST IRQ 58 MB90420G/5G (A) Series 16. Address Match Detect Function If the address setting is the same as the ROM correction address register, an INT9 instruction is executed. The ROM correction function can be implemented by processing the INT9 interrupt service routine. Two address registers are used, each with its own compare enable bit. When there is a match between the address register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is forcibly executed by the CPU. Address latch ROM correction address register Compare • Block diagram Enable bit F2MC-16LX CPU core F2MC-16LX bus 59 MB90420G/5G (A) Series 17. ROM Mirror Function Select Module The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated to the FF bank to be viewed in the 00 bank. • Block diagram F2MC-16LX bus ROM mirror function select register Address area FF bank 00 bank ROM 60 MB90420G/5G (A) Series ■ ELECTRICAL CHARACTERISTICS (VSS = AVSS = DVSS = 0 V) 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min. Max. VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*1 VAVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ VAVRH DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*1 Input voltage VI VSS − 0.3 VCC + 0.3 V Output voltage VO VSS − 0.3 VCC + 0.3 V Clamp current ICLAMP −2.0 2.0 mA IOL1 15 mA Other than P70-P77, P80-P87 IOL2 40 mA P70-77, P80-87 IOLAV1 4 mA Other than P70-P77, P80-P87 IOLAV2 30 mA P70-77, P80-87 ΣIOL1 100 mA Other than P70-P77, P80-P87 ΣIOL2 330 mA P70-77, P80-87 ΣIOLAV1 50 mA Other than P70-P77, P80-P87 ΣIOLAV2 250 mA P70-77, P80-87 OH1 2 −15 mA Other than P70-P77, P80-P87 IOH2*2 −40 mA P70-77, P80-87 IOHAV1*3 −4 mA Other than P70-P77, P80-P87 OHAV2 3 * −30 mA P70-77, P80-87 ΣIOH1 −100 mA Other than P70-P77, P80-P87 ΣIOH2 −330 mA P70-77, P80-87 ΣIOHAV1*4 −50 mA Other than P70-P77, P80-P87 ΣI −250 mA P70-77, P80-87 Power supply voltage “L”level maximum output current*2 “L”level average output current*3 “L”level maximum total output current “L”level average total output current I “H”level maximum output current “H”level average output current “H”level maximum total output current “H”level average total output current I * OHAV2 4 * Power consumption PD 500 mW Operating temperature TA −40 +105 °C TSTG −55 +150 °C Storage temperature *1 : Care must be taken to ensure that AVCC and DVCC do not exceed VCC at power-on etc. *2 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins. *3 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “operating factor”. *4 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “ operating factor”. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 61 MB90420G/5G (A) Series 2. Recommended Operating Conditions Parameter Power supply voltage Symbol VCC AVCC DVCC (VSS = DVSS = AVSS = 0.0 V) Value Unit Remarks 5.5 V In normal operation: (MB90F428G/F428GA, MB90428G/428GA, MB90427G/427GA) 3.0 5.5 V Holding stop operation status (MB90F428G, MB90428G, MB90427G) 4.5 5.5 V Holding stop operation status (MB90F428GA, MB90428GA, MB90427GA) Use a ceramic capacitor or other capacitor of equivalent frequency characteristics. A smoothing capacitor on the VCC pin should have a capacitance greater than Cs. Min. Max. 4.5 Smoothing capacitor* CS 0.1 1.0 µF Operating temperature TA −40 +105 °C * : For smoothing capacitor Cs connections, see the illustration below. • C pin connection C CS VSS DVSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 62 MB90420G/5G (A) Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Symbol Pin name Conditions “H”level input voltage VIHS VIHM “L”level input voltage Unit Remarks VCC + 0.3 V CMOS hysteresis input pin*1 VCC + 0.3 V MD pin*2 VSS − 0.3 0.6 VCC V CMOS hysteresis input pin*1 VSS − 0.3 VSS + 0.3 V MD pin*2 45 72 mA 38 61 MB90428G/GA mA MB90427G/GA MB90423G/GA 15 24 mA 13 21 MB90428G/GA, mA MB90427G/GA MB90423G/GA Operating frequency FCP = 2 MHz, time base timer mode 0.75 1.0 mA ICCL Operating frequency FCP = 8 kHz, TA = 25 °C, subclock operation 0.35 0.7 mA ICCLS Operating frequency FCP = 8 kHz, TA = 25 °C, sub sleep operation 40 100 µA ICCT Operating frequency FCP = 8 kHz, TA = 25 °C, clock mode 40 100 µA Min. Typ. Max. 0.8 VCC VCC − 0.3 VILS VILM Operating frequency FCP = 16 MHz, normal operation ICC Operating frequency FCP = 16 MHz, sleep mode ICCS Power supply current*3 Value ICTS VCC MB90F428G/GA MB90F423G/GA MB90F428G/GA MB90F423G/GA *1 : All input pins except X0, X0A, MD0, MD1, MD2 pins. *2 : MD0, MD1, MD2 pins. *3 : Current values are provisional, and may be changed without prior notice for purposes of characteristic improve ment, etc. Supply current values assume external clock feed from the 1 pin and X1A pin. Users must be aware that supply current levels differ depending on whether an external clock or oscillator is useed. (Continued) 63 MB90420G/5G (A) Series (Continued) Parameter (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Sym bol Pin name Conditions Value Min. Power supply current *3 ICCH VCC Typ. 5 Max. Unit 20 MB90F428G MB90F423G µA MB90428G MB90427G MB90423G MB90F428GA MB90F423GA µA MB90428GA MB90427GA MB90423GA TA = 25 °C, stop mode 40 100 IIL All input pins VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC −5 5 µA Input capacitance 1 CIN1 Other than Vcc, Vss, DVcc, DVss, Avcc, Avss, C, P70 to P77, P80 to P87 5 15 pF Input capacitance 2 CIN2 P70 to P77, P80 to P87 15 45 pF Pull-up resistance RUP RST, MD0, MD1 25 50 100 kΩ 25 50 100 kΩ Input leakage current Pull-down resistance RDOWN MD2 Remarks Output H voltage 1 VOH1 Other than P70 to P77, P80 to P87 VCC = 4.5 V IOH = −4.0 mA VCC − 0.5 V Output H voltage 2 VOH2 P70 to P77, P80 to P87 VCC = 4.5 V IOH = −30.0 mA VCC − 0.5 V Output L voltage 1 VOL1 Other than P70 to P77, P80 to P87 VCC = 4.5 V IOL = 4.0 mA 0.4 V Output L voltage 2 VOL2 P70 to P77, P80 to P87 VCC = 4.5 V IOL = 30.0 mA 0.5 V *3: Current values are provisional, and may be changed without prior notice for purposes of characteristic improve ment, etc. Supply current values assume external clock feed from the 1 pin and X1A pin. Users must be aware that supply current levels differ depending on whether an external clock or oscillator is useed. (Continued) 64 MB90420G/5G (A) Series (Continued) Parameter Symbol Pin name Conditions Value Min. Typ. Max. Unit Remarks ∆VOH2 PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3 VCC = 4.5 V IOH = 30.0 mA VOH2 maximum variation 0 90 mV *4 Large current output drive capacity variation 2 ∆VOL2 PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3 VCC = 4.5 V IOH = 30.0 mA VOL2 maximum variation 0 90 mV *4 LCD divider resistance RLCD V0 to V1, V1 to V2, V2 to V3 50 100 200 kΩ COM0 to COM3 output impedance RVCOM COMn (n = 0 to 3) 2.5 kΩ SEG0 to SEG3 output impedance RVSEG SEGn (n = 00 to 23) 15 kΩ ILCDC V0 to V3 COMm (m = 00 to 23) SEGn (n = 00 to 23) −5.0 +5.0 kΩ Large current output drive capacity variation 1 LCD leakage current *4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simultaneously ON. Similarly for other channels. 65 MB90420G/5G (A) Series 4. AC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) (1) Clock timing Parameter Symbol Pin name FC Unit Remarks Min. Typ. Max. X0, X1 4 MHz FLC X0A, X1A 32.768 kHz tCYL X0, X1 250 ns tLCYL X0A, X1A 30.5 µs PWH, PWL X0 10 ns PWLH, PWLL X0A 15.2 µs tcr, tcf X0, X0A 5 ns FCP 2 16 MHz FLCP 8.192 kHz Using sub clock tCP 62.5 — 500 ns Using main clock, PLL clock tLCP 122.1 µs Using sub clock ∆f 5 % Base oscillation clock frequency Base oscillation clock cycle time Input clock pulse width Value Conditions Input clock rise, fall time Input operating clock frequency Input operating clock cycle time Frequency variability ratio* (locked) Use duty ratio of 40 to 60% as a guideline With external clock signal Using main clock, PLL clock *: The frequency variability ratio is the maximum proportion of variation from the set central frequency using a multiplier in locked operation. + ∆f = α fo +α × 100 (%) Central frequency fo −α − • X0, X1 clock timing t 0.8 VCC X0 0.2 VCC P PLCYL tcf tcr • X0A, X1A clock timing tHCYL 0.8 VCC X0A 0.2 VCC PWH PWL tcf 66 tcr MB90420G/5G (A) Series • Range of warranted operation Relation between internal operating clock frequency and supply voltage MB90F428GA, MB90428GA, MB90427GA range of warranted operation Supply voltage VCC (V) 5.5 3.7 3.3 3.0 PLL range of warranted operation MB90F428G, MB90428G, MB90427G range of warranted operation 2 8 12 16 Internal clock frequency fCP (MHz) The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA enter reset mode at supply voltage below 4 V ± 0.3 V. Relation between oscillator clock frequency and internal operating clock frequency Internal operating clock frequency PLL clock Main clock Multiplier ×1 Oscillation clock frequency 4 MHz 2 MHz Multiplier ×2 Multiplier ×3 Multiplier ×4 8 MHz 12 MHz 16 MHz • Sample oscillator circuit Oscillator element Oscillator Frequency manufacturer TBD X0 TBD 4 MHz C1 C2 R TBD TBD TBD X1 R C1 C2 67 MB90420G/5G (A) Series AC ratings are defined for the following measurement reference voltage values: • Input signal waveform Hysteresis input pin 68 • Output signal waveform Output pin 0.8 VCC 2.4 V 0.6 VCC 0.8 V MB90420G/5G (A) Series (2) Reset input (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Reset input time Symbol Pin name Conditions tRSTL RST Value Min. Max. 16 tCP Unit Remarks ns tRSTL RST 0.6 VCC 0.6 VCC (3) Power-on reset, power on conditions Parameter Symbol Power supply rise time (VSS = 0.0 V, TA = −40 °C to +105 °C) Pin Conditions name tR Power supply start voltage VOFF Power supply attained voltage VON Power supply cutoff time tOFF VCC Value Unit Min. Max. 0.05 30 ms 0.2 V 2.7 V 50 ms Remarks For repeat operation tR 2.7 V VCC 0.2 V 0.2 V 0.2 V tOFF Extreme variations in voltage supply may activate a power-on reset. As the illustration below shows, when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however it is permissible to use the PLL clock during a voltage drop of 1mV/s or less. 5.0 V VCC 4.5 (V) 420G/425G series 3.0 (V) 420GA/425GA series 0V VSS A rise slope of 50 mV or less is recommended RAM data hold 69 MB90420G/5G (A) Series (4) UART0, UART1 timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol Pin name Serial clock cycle time tSCYC SCK fall to SOT delay time tSLOV Valid SIN to SCK rise tIVSH SCK rise to valid SIN hold time tSHIX Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Parameter SCK fall to SOT delay time tSLOV Valid SIN to SCK rise tIVSH SCK rise to valid SIN hold time tSHIX Conditions Value Unit Min. Max. SCK0, SCK1 8 tCP ns SCK0, SCK1 SOT0, SOT1 −80 80 ns 100 ns 60 ns 4 tCP ns 4 tCP ns 150 ns 60 ns 60 ns SCK0, SCK1 SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SOT0, SOT1 SCK0, SCK1 SIN0, SIN1 Notes : • AC ratings are for CLK synchronous mode. • CL is load capacitance connected to pin during testing. • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.6 VCC 0.6 VCC • External shift clock mode tSLSH SCK 0.6 VCC tSHSL 0.8 VCC 0.8 VCC 0.6 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 70 tSHIX 0.8 VCC 0.8 VCC 0.6 VCC 0.6 VCC Remarks Internal shift clock mode output pin CL = 80 pF + 1•TTL External shift clock mode output pin CL = 80 pF + 1•TTL MB90420G/5G (A) Series (5) Timer input timing Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol Pin name Conditions tTIWH tTIWL TIN0, TIN1, IN0, IN1, IN2, IN3, Input pulse width Value Min. Max. 4 tCP Unit Remarks ns • Timer input timing tTIWH 0.8 VCC TIN0 ∼ TIN1 IN0 ∼ IN3 0.8 VCC 0.6 VCC (6) Trigger input timing Parameter Input pulse width tTIWL 0.6 VCC (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol Pin name Conditions tTRGL IRQ0 to IRQ7 Value Min. Max. 5 tCP Unit Remarks ns • Trigger input timing tTRGH IRQ0 ∼ IRQ7 0.8 VCC tTRGL 0.8 VCC 0.6 VCC 0.6 VCC 71 MB90420G/5G (A) Series (7) Low voltage detection (VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol Pin name Conditions Parameter Value Remarks 4.3 V During voltage drop V During voltage rise Typ. Max. 3.7 4.0 0.1 Detection voltage VDL VCC Hysteresis width VHYS VCC Power supply voltage fluctuation ratio dV/dt VCC −0.1 0.02 V/µs Detection delay time td 35 µs Internal reset VCC dV dt VHYS Vni td 72 Unit Min. td MB90420G/5G (A) Series 5. A/D Conversion Block (1) Electrical Characteristics Parameter (VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol Pin name Resolution Total error Value Unit Remarks Min. Typ. Max. 10 bit ±5.0 LSB Non-linear error ±2.5 LSB Differential linear error ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS AVSS AVSS − 3.5 LSB + 0.5 LSB + 4.5 LSB V Full scale transition voltage VFST AN0 to AN7 AVRH AVRH AVRH − 6.5 LSB − 1.5 LSB + 1.5 LSB V 1 LSB = (AVRH − AVSS) / 1024 Sampling time tSMP 2.000 µs *1 Compare time tCMP 4.125 µs *2 A/D conversion time tCNV 6.125 µs *3 Analog port input current IAIN AN0 to AN7 10 µA VAVSS = VAIN = VAVCC Analog input current VAIN AN0 to AN7 0 AVRH V AVR+ AVRH 3.0 AVCC V 2.3 6.0 mA 5 µA *4 Reference voltage Power supply current IA IAH AVCC Reference voltage feed current IR AVRH 200 400 600 µA VAVRH = 5.0 V IRH AVRH 5 µA *4 Inter-channel variation — AN0 to AN7 4 LSB *1 : At FCP = 16 MHz, tSMP = 32 × tCP = 2.000 (µs) . *2 : At FCP = 16 MHz, tCMP = 66 × tCP = 4.125 (µs) . *3 : Equivalent to conversion time per channel at FCP = 16 MHz, and selection of tSMP = 32 × tCP and tCMP = 32 × tCP. *4 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in stop mode. Notes : •The relative error increases as AVRH is reduced. •The output impedance (rs) on the external analog input circuit should be used as follows. External circuit output impedance rs = 5 kΩ max. •If the output impedance on the external circuit is too great, the analog voltage sampling time may be insufficient. •If DC inhibitor capacitance is placed between the external circuit and input pin, then a capacitance value several thousand times the value of the chip internal sampling capacitance (CSH) should be selected in order to suppress the effects of voltage division with CSH. 73 MB90420G/5G (A) Series • Analog input equivalent circuit Microcontroller internal circuits Input pin AN0 rS RSH CSH Comparator Input pin AN7 S/H circuit VS External circuits Analog channel selector <Recommended and guide values for element parameters> rs = 5 kΩ or less RSH = approx. 3 kΩ CSH = approx. 25 pF Note : These element parameters are intended as guidelines for reference, and are not warranted for actual use. 74 MB90420G/5G (A) Series (2) Definition of terms • Resolution Indicates the ability of the A/D converter to discriminate in analog conversion. 10-bit resolution indicates that analog voltage can be resolved into 210 = 1024 levels. • Total error Expresses the difference between actual and logical values. It is the total value of errors that can come from offset error, gain error, non-linearity error and noise. • Linearity error Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s zero transition point (00 0000 0000 ←→ 00 0000 0001) and full scale transition point (11 1111 1110 ←→ 11 1111 1111) . • Differential linearity error Expresses the deviation of the logical value of input voltage required to create a variation of 1 SLB in output code. • 10-bit A/D converter conversion characteristics 11 11 11 11 1111 1111 1111 1111 1111 1110 1101 1100 . . 1 LSB × N + VOT . . Digital output . . . . . Linearity error . . . . 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VNT V(N + 1)T VOT VFST Analog input 1 LSB = VFST − VOT 1022 Linearity error = Differential linearity error = VNT − (1 LSB × N + VOT) [LSB] 1 LSB V (N + 1) T − VNT − 1 [LSB] 1 LSB 75 MB90420G/5G (A) Series ■ EXAMPLE CHARACTERISTICS ICC − VCC (TA = +25 °C) 40 35 FC = 16 MHz ICC (mA) 30 25 FC = 11 MHz 20 FC = 8 MHz 15 FC = 5 MHz 10 FC = 4 MHz 5 FC = 2 MHz 0 3.5 4.5 5.5 6.5 VCC (V) ICCS − VCC (TA = +25 °C) 3.5 3 FC = 16 MHz ICCS (mA) 2.5 FC = 11 MHz 2 FC = 8 MHz 1.5 1 FC = 5 MHz FC = 4 MHz 0.5 FC = 2 MHz 0 3.5 4.5 5.5 6.5 VCC (V) ICTS − VCC (TA = +25 °C) FC = 16 MHz 900 800 FC = 11 MHz ICTS (µA) 700 FC = 8 MHz FC = 5 MHz 600 500 FC = 4 MHz FC = 2 MHz 400 300 200 100 0 3.5 4.5 5.5 6.5 VCC (V) (Continued) 76 MB90420G/5G (A) Series (Continued) ICCL − VCC (FC = 8 kHz) 500 ICCL (µA) 400 Ta = 25 °C 300 Ta = 125 °C Ta = −40 °C 200 100 0 3.5 4.5 5.5 6.5 VCC (V) ICCLS − VCC (FC = 8 kHz) 70 60 Ta = 125 °C ICCLS (µA) 50 40 Ta = 25 °C 30 Ta = −40 °C 20 10 0 3.5 4.5 5.5 6.5 VCC (V) ICCT − VCC (FC = 8 kHz) 70 60 Ta = 125 °C ICCT (µA) 50 40 Ta = 25 °C 30 Ta = −40 °C 20 10 0 3.5 4.5 5.5 6.5 VCC (V) 77 MB90420G/5G (A) Series ■ INSTRUCTIONS (351 INSTRUCTIONS) Table 1 Item Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the “~” column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers “0”. X : Extends with a sign before transferring. – : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. – : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. – : No change. S : Set by execution of instruction. R : Reset by execution of instruction. Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. – : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. • Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done × the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 78 MB90420G/5G (A) Series Table 2 Explanation of Symbols in Tables of Instructions Symbol A Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH AH AL Upper 16 bits of A Lower 16 bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel ear eam rlst PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list 79 MB90420G/5G (A) Series Table 3 Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Effective Address Fields Address format RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Number of bytes in address extension * Register direct “ea” corresponds to byte, word, and long-word types, starting from the left 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 Register indirect 0C 0D 0E 0F @RW0 + @RW1 + @RW2 + @RW3 + Register indirect with post-increment 10 11 12 13 14 15 16 17 @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 Register indirect with 8-bit displacement 18 19 1A 1B @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 Register indirect with 16-bit displacement 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address — 0 0 1 2 0 0 2 2 Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the tables of instructions. 80 MB90420G/5G (A) Series Table 4 Number of Execution Cycles for Each Type of Addressing (a) Code Operand Number of execution cycles for each type of addressing Number of register accesses for each type of addressing 00 to 07 Ri RWi RLi 08 to 0B @RWj 2 1 0C to 0F @RWj + 4 2 10 to 17 @RWi + disp8 2 1 18 to 1B @RWj + disp16 2 1 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 4 4 2 1 2 2 0 0 Listed in tables of instructions Listed in tables of instructions Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand (b) byte (c) word (d) long Cycles Access Cycles Access Cycles Access Internal register +0 1 +0 1 +0 2 Internal memory even address Internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 Even address on external data bus (16 bits) Odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 External data bus (8 bits) +1 1 +4 2 +8 4 Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value) in the tables of instructions. • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory — +2 External data bus (16 bits) — +3 External data bus (8 bits) +3 — Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. • Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for “worst case” calculations. 81 MB90420G/5G (A) Series Table 7 Mnemonic # Transfer Instructions (Byte) [41 Instructions] ~ RG B Operation LH AH I S T N Z V C RMW MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 Z Z Z Z Z Z Z Z Z Z * * * * * * * – * * – – – – – – – – – – – – – – – – – – – – – * – * – * – * – * – * – * – * – * – R * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 0 0 1 1 0 0 0 0 1 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) X * X * X * X * X * X * X * X – X * X * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi) +disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * – – * – * * * * * * * * * * * * – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 2 3 0 (b) byte ((A)) ← (AH) – – – – – * * – – – XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam 4 2 2+ 5+ (a) 7 2 2+ 9+ (a) 2 0 4 2 0 2× (b) 0 2× (b) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 82 MB90420G/5G (A) Series Table 8 Transfer Instructions (Word/Long Word) [38 Instructions] RG B 2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 – – – – – – – – – word (A) ← ((RWi) +disp8) – word (A) ← ((RLi) +disp8) – MOVW dir, A MOVW addr16, A MOVW SP, A MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) 2 3 0 (c) XCHW XCHW XCHW XCHW 2 4 2+ 5+ (a) 2 7 2+ 9+ (a) MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 A, ear A, eam RWi, ear RWi, eam # ~ Operation LH AH I S T N Z V C RMW * * * * * * * – * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word ((RWi) +disp8) ← (A) – word ((RLi) +disp8) ← (A) – word (RWi) ← (ear) – word (RWi) ← (eam) – word (ear) ← (RWi) – word (eam) ← (RWi) – word (RWi) ← imm16 – word (io) ← imm16 – word (ear) ← imm16 – word (eam) ← imm16 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * – * – * * * * * * * * * * * * * * – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word ((A)) ← (AH) – – – – – * * – – – 2 0 0 2× (c) 4 0 2 2× (c) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 2 4 2+ 5+ (a) 5 3 2 0 0 0 (d) 0 long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * – – – – – – – – – 2 4 2+ 5+ (a) 2 0 0 (d) long (ear) ← (A) long (eam) ← (A) – – – – – – – – – – * * * * – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 83 MB90420G/5G (A) Series Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # ~ RG B Operation 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2× (b) 0 0 (b) 0 0 (b) 0 (b) 0 2× (b) 0 0 (b) 0 byte (A) ← (A) +imm8 byte (A) ← (A) +(dir) byte (A) ← (A) +(ear) byte (A) ← (A) +(eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear) + (C) byte (A) ← (A) + (eam) + (C) Z Z Z Z – Z Z Z Z byte (A) ← (AH) + (AL) + (C) (decimal) Z Z byte (A) ← (A) –imm8 Z byte (A) ← (A) – (dir) Z byte (A) ← (A) – (ear) Z byte (A) ← (A) – (eam) – byte (ear) ← (ear) – (A) – byte (eam) ← (eam) – (A) byte (A) ← (AH) – (AL) – (C) Z byte (A) ← (A) – (ear) – (C) Z byte (A) ← (A) – (eam) – (C) Z byte (A) ← (AH) – (AL) – (C) (decimal) Z 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2× (c) 0 (c) 0 0 (c) 0 0 2× (c) 0 (c) word (A) ← (AH) + (AL) word (A) ← (A) +(ear) word (A) ← (A) +(eam) word (A) ← (A) +imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) – (AL) word (A) ← (A) – (ear) word (A) ← (A) – (eam) word (A) ← (A) –imm16 word (ear) ← (ear) – (A) word (eam) ← (eam) – (A) word (A) ← (A) – (ear) – (C) word (A) ← (A) – (eam) – (C) A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) +imm32 long (A) ← (A) – (ear) long (A) ← (A) – (eam) long (A) ← (A) –imm32 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 84 MB90420G/5G (A) Series Table 10 Mnemonic Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW INC INC ear eam 2 2 2+ 5+ (a) 2 0 0 byte (ear) ← (ear) +1 2× (b) byte (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DEC DEC ear eam 2 3 2+ 5+ (a) 2 0 0 byte (ear) ← (ear) –1 2× (b) byte (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCW INCW ear eam 2 3 2+ 5+ (a) 2 0 0 word (ear) ← (ear) +1 2× (c) word (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECW ear DECW eam 2 3 2+ 5+ (a) 2 0 0 word (ear) ← (ear) –1 2× (c) word (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCL INCL ear eam 2 7 2+ 9+ (a) 4 0 0 long (ear) ← (ear) +1 2× (d) long (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECL DECL ear eam 2 7 2+ 9+ (a) 4 0 0 long (ear) ← (ear) –1 2× (d) long (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 11 Mnemonic Compare Instructions (Byte/Word/Long Word) [11 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW CMP CMP CMP CMP A A, ear A, eam A, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (AH) – (AL) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← imm8 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPW CMPW CMPW CMPW A 1 A, ear 2 A, eam 2+ A, #imm16 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (AH) – (AL) word (A) ← (ear) word (A) ← (eam) word (A) ← imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPL CMPL CMPL A, ear 2 A, eam 2+ A, #imm32 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (A) ← (ear) word (A) ← (eam) word (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 85 MB90420G/5G (A) Series Table 12 Mnemonic Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # ~ 1 RG B Operation LH AH I S T N Z V C RMW DIVU A 1 * 0 0 word (AH) /byte (AL) – – – – – – – * * – DIVU A, ear 2 *2 1 0 word (A)/byte (ear) – – – – – – – * * – DIVU A, eam 2+ *3 0 *6 word (A)/byte (eam) – – – – – – – * * – *4 1 0 long (A)/word (ear) – – – – – – – * * – DIVUW A, eam 2+ *5 0 *7 long (A)/word (eam) – – – – – – – * * – MULU MULU MULU 0 0 byte (AH) *byte (AL) → word (A) 1 0 byte (A) *byte (ear) → word (A) 0 (b) byte (A) *byte (eam) → word (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 word (AH) *word (AL) → long (A) 1 0 word (A) *word (ear) → long (A) 0 (c) word (A) *word (eam) → long (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – DIVUW A, ear 2 A 1 *8 A, ear 2 *9 A, eam 2+ *10 MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: Quotient → byte (AL) Remainder → byte (AH) Quotient → byte (A) Remainder → byte (ear) Quotient → byte (A) Remainder → byte (eam) Quotient → word (A) Remainder → word (ear) Quotient → word (A) Remainder → word (eam) 3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 × (b) normally. (c) when the result is zero or when an overflow occurs, and 2 × (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 86 MB90420G/5G (A) Series Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] Mnemonic # ~ RG B 0 DIV A 2 *1 0 DIV A, ear 2 *2 1 DIV A, eam 2 + *3 0 DIVW A, ear 2 *4 1 DIVW A, eam 2+ *5 0 MULU MULU MULU MULUW MULUW MULUW A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 Operation word (AH) /byte (AL) Quotient → byte (AL) Remainder → byte (AH) 0 word (A)/byte (ear) Quotient → byte (A) Remainder → byte (ear) *6 word (A)/byte (eam) Quotient → byte (A) Remainder → byte (eam) 0 long (A)/word (ear) Quotient → word (A) Remainder → word (ear) *7 long (A)/word (eam) Quotient → word (A) Remainder → word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) → word (A) byte (A) *byte (ear) → word (A) byte (A) *byte (eam) → word (A) word (AH) *word (AL) → long (A) word (A) *word (ear) → long (A) word (A) *word (eam) → long (A) LH AH I S T N Z V C RMW Z – – – – – – * * – Z – – – – – – * * – Z – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: *2: *3: *4: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. • When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. • For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes” and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.” 87 MB90420G/5G (A) Series Table 14 Mnemonic # ~ Logical 1 Instructions (Byte/Word) [39 Instructions] RG B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) and imm8 byte (A) ← (A) and (ear) byte (A) ← (A) and (eam) byte (ear) ← (ear) and (A) byte (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * OR OR OR OR OR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) or imm8 byte (A) ← (A) or (ear) byte (A) ← (A) or (eam) byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * XOR XOR XOR XOR XOR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) xor imm8 byte (A) ← (A) xor (ear) byte (A) ← (A) xor (eam) byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * NOT NOT NOT A ear eam 1 2 2 3 2+ 5+ (a) 0 2 0 0 byte (A) ← not (A) 0 byte (ear) ← not (ear) 2× (b) byte (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * ANDW ANDW ANDW ANDW ANDW ANDW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) and (A) word (A) ← (A) and imm16 word (A) ← (A) and (ear) word (A) ← (A) and (eam) word (ear) ← (ear) and (A) word (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * ORW ORW ORW ORW ORW ORW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * XORW XORW XORW XORW XORW XORW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * 0 2 0 0 word (A) ← not (A) 0 word (ear) ← not (ear) 2× (c) word (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * NOTW A NOTW ear NOTW eam 1 2 2 3 2+ 5+ (a) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 88 MB90420G/5G (A) Series Table 15 Logical 2 Instructions (Long Word) [6 Instructions] Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW ANDL A, ear ANDL A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) and (ear) long (A) ← (A) and (eam) – – – – – – – – – – * * * * R R – – – – ORL ORL A, ear A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) or (ear) long (A) ← (A) or (eam) – – – – – – – – – – * * * * R R – – – – XORL A, ea XORL A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) xor (ear) long (A) ← (A) xor (eam) – – – – – – – – – – * * * * R R – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 16 Mnemonic Sign Inversion Instructions (Byte/Word) [6 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW 2 0 0 byte (A) ← 0 – (A) X – – – – * * * * – – – – – – – – – – – * * * * * * * * – * – – – – – * * * * – – – – – – – – – – – * * * * * * * * – * NEG A 1 NEG NEG ear eam 2 3 2+ 5+ (a) 2 0 NEGW A 1 0 NEGW ear NEGW eam 2 3 2+ 5+ (a) 2 2 0 0 byte (ear) ← 0 – (ear) 2× (b) byte (eam) ← 0 – (eam) 0 word (A) ← 0 – (A) 0 word (ear) ← 0 – (ear) 2× (c) word (eam) ← 0 – (eam) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 17 Mnemonic # ~ RG B NRML A, R0 2 *1 1 0 Normalize Instruction (Long Word) [1 Instruction] Operation LH long (A) ← Shift until first digit is “1” – byte (R0) ← Current shift count AH I S T N Z V C RMW – – – – – * – – – *1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 89 MB90420G/5G (A) Series Table 18 Mnemonic RORC A ROLC A Shift Instructions (Byte/Word/Long Word) [18 Instructions] # ~ RG B 2 2 2 2 0 0 0 0 Operation LH AH I S T N Z V C RMW byte (A) ← Right rotation with carry byte (A) ← Left rotation with carry – – – – – – – – – – * * * * – – * * – – 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 0 0 2× (b) 2 0 0 2× (b) byte (ear) ← Right rotation with carry byte (eam) ← Right rotation with carry byte (ear) ← Left rotation with carry byte (eam) ← Left rotation with carry – – – – – – – – – – – – – – – – * * * * * * * * – – – – * * * * – * – * 2 2 2 *1 *1 *1 1 1 1 0 0 0 byte (A) ← Arithmetic right barrel shift (A, R0) byte (A) ← Logical right barrel shift (A, R0) byte (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – ASRW A LSRW A/SHRW A LSLW A/SHLW A 1 1 1 2 2 2 0 0 0 0 0 0 word (A) ← Arithmetic right shift (A, 1 bit) – – – – – – – – * * * – – * R * – – – * * – – – * * * – – – ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 word (A) ← Arithmetic right barrel shift (A, R0) word (A) ← Logical right barrel shift (A, R0) word (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (A) ← Arithmetic right shift (A, R0) – – – – – – * – – * – – – * * * * * * – – – * * * – – – RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0 word (A) ← Logical right shift (A, 1 bit) word (A) ← Logical left shift (A, 1 bit) long (A) ← Logical right barrel shift (A, R0) long (A) ← Logical left barrel shift (A, R0) – – – – – – *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 90 MB90420G/5G (A) Series Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel rel rel rel rel Branch 1 Instructions [31 Instructions] RG B Operation * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 # ~ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 1 3 2 2+ 2 2+ 4 2 3 3 4+ (a) 5 6+ (a) 4 0 0 1 0 2 0 0 0 0 0 (c) 0 (d) 0 CALL CALL CALL CALLV CALLP 2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 6 7+ (a) 6 7 10 1 0 0 0 2 (c) 2× (c) (c) 2× (c) 2× (c) CALLP @eam *6 2+ 11+ (a) 0 *2 CALLP addr24 *7 4 0 2× (c) *1: *2: *3: *4: *5: *6: *7: 10 LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) ← (A) word (PC) ← addr16 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← (ear), (PCB) ← (ear +2) word (PC) ← (eam), (PCB) ← (eam +2) word (PC) ← ad24 0 to 15, (PCB) ← ad24 16 to 23 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← addr16 Vector call instruction word (PC) ← (ear) 0 to 15, (PCB) ← (ear) 16 to 23 word (PC) ← (eam) 0 to 15, (PCB) ← (eam) 16 to 23 word (PC) ← addr0 to 15, (PCB) ← addr16 to 23 4 when branching, 3 when not branching. (b) + 3 × (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 91 MB90420G/5G (A) Series Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE ear, #imm8, rel eam, #imm8, rel* 10 CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel*10 Branch 2 Instructions [19 Instructions] # ~ RG B Operation 3 4 1 * *1 0 0 0 0 Branch when byte (A) ≠ imm8 Branch when word (A) ≠ imm16 4 4+ 5 5+ *2 *3 *4 *3 1 0 1 0 0 (b) 0 (c) Branch when byte (ear) ≠ imm8 Branch when byte (eam) ≠ imm8 Branch when word (ear) ≠ imm16 Branch when word (eam) ≠ imm16 *5 2 0 DBNZ ear, rel 3 DBNZ eam, rel 3+ *6 N Z V C RMW – – – – – – * – – – – * * * * * * * – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – Branch when byte (ear) = (ear) – 1, and (ear) ≠ 0 2 2× (b) Branch when byte (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * Branch when word (ear) = (ear) – 1, and (ear) ≠ 0 2× (c) Branch when word (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt – – – – – – – – – – – – – – * – – – – * – – – – * – – – – – At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. – – – – – – – – – – – – – – – – – – – – Return from subroutine Return from subroutine – – – – – – – – – – – – – – – – – – – – DWBNZ ear, rel 3 *5 2 DWBNZ eam, rel 3+ *6 2 INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 20 16 17 20 15 0 0 0 0 0 8× (c) 6× (c) 6× (c) 8× (c) *7 LINK #imm8 2 6 0 (c) UNLINK 1 5 0 (c) RET *8 RETP *9 1 1 4 6 0 0 (c) (d) 0 LH AH I – – – – R R R R * S – – – – S S S S * T – – – – – – – – * – – – – * *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 92 MB90420G/5G (A) Series Table 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] # ~ RG B Operation PUSHW A PUSHW AH PUSHW PS PUSHW rlst 1 1 1 2 4 4 4 *3 0 0 0 *5 (c) (c) (c) *4 POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 *5 (c) (c) (c) *4 JCTX @A 1 14 0 AND CCR, #imm8 OR CCR, #imm8 2 2 3 3 0 0 MOV RP, #imm8 MOV ILM, #imm8 2 2 2 2 Mnemonic LH AH I S T N Z V C RMW word (SP) ← (SP) –2, ((SP)) ← (A) word (SP) ← (SP) –2, ((SP)) ← (AH) word (SP) ← (SP) –2, ((SP)) ← (PS) (SP) ← (SP) –2n, ((SP)) ← (rlst) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word (A) ← ((SP)), (SP) ← (SP) +2 word (AH) ← ((SP)), (SP) ← (SP) +2 word (PS) ← ((SP)), (SP) ← (SP) +2 (rlst) ← ((SP)), (SP) ← (SP) +2n – – – – * – – – – – – – – – – – – – – – – – * * * * * * * – – – – – – – – – – – – – * * * * * * * – 0 0 byte (CCR) ← (CCR) and imm8 – – byte (CCR) ← (CCR) or imm8 – – * * * * * * * * * * * * * * – – 0 0 0 0 byte (RP) ←imm8 byte (ILM) ←imm8 – – – – – – – – – – – – – – – – – – – – MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) 1 1 0 0 0 0 0 0 word (RWi) ←ear word (RWi) ←eam word(A) ←ear word (A) ←eam – – – – – – * * – – – – – – – – – – – – ADDSP #imm8 ADDSP #imm16 2 3 3 3 0 0 0 0 word (SP) ← (SP) +ext (imm8) word (SP) ← (SP) +imm16 – – – – – – – – – – – – – – – – – – – – MOV MOV 2 2 *1 1 0 0 0 0 byte (A) ← (brgl) byte (brg2) ← (A) Z * – – – – – – – – * * * * – – – – – – 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 6× (c) Context switch instruction Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count × (c), or push count × (c) *5: Pop count or push count. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 93 MB90420G/5G (A) Series Table 22 Bit Manipulation Instructions [21 Instructions] # ~ RG B MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A 3 4 3 7 7 6 0 0 0 SETB dir:bp SETB addr16:bp SETB io:bp 3 4 3 7 7 7 CLRB dir:bp CLRB addr16:bp CLRB io:bp 3 4 3 BBC BBC BBC dir:bp, rel addr16:bp, rel io:bp, rel BBS BBS BBS Mnemonic Operation LH AH I S T N Z V C RMW Z Z Z * * * – – – – – – – – – * * * * * * – – – – – – – – – 2× (b) bit (dir:bp) b ← (A) 2× (b) bit (addr16:bp) b ← (A) 2× (b) bit (io:bp) b ← (A) – – – – – – – – – – – – – – – * * * * * * – – – – – – * * * 0 0 0 2× (b) bit (dir:bp) b ← 1 2× (b) bit (addr16:bp) b ← 1 2× (b) bit (io:bp) b ← 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 7 7 7 0 0 0 2× (b) bit (dir:bp) b ← 0 2× (b) bit (addr16:bp) b ← 0 2× (b) bit (io:bp) b ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – SBBS addr16:bp, rel 5 *3 0 2× (b) Branch when (addr16:bp) b = 1, bit = 1 – – – – – – * – – * WBTS io:bp 3 *4 0 *5 Wait until (io:bp) b = 1 – – – – – – – – – – WBTC io:bp 3 *4 0 *5 Wait until (io:bp) b = 0 – – – – – – – – – – *1: *2: *3: *4: *5: byte (A) ← (dir:bp) b byte (A) ← (addr16:bp) b byte (A) ← (io:bp) b 8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 23 Mnemonic SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # ~ RG B Operation 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (A) 0 to 7 ↔ (A) 8 to 15 word (AH) ↔ (AL) byte sign extension word sign extension byte zero extension word zero extension LH AH I S T N Z V C RMW – – X – Z – – * – X – Z – – – – – – – – – – – – – – – – – – – – * * R R – – * * * * – – – – – – – – – – – – – – – – – – Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 94 MB90420G/5G (A) Series Table 24 Mnemonic # ~ RG B MOVS/MOVSI MOVSD 2 2 2 * *2 5 * *5 3 * *3 SCEQ/SCEQI SCEQD 2 2 *1 *1 *5 *5 FISL/FILSI 2 6m +6 *5 String Instructions [10 Instructions] Operation LH AH I S T N Z V C RMW Byte transfer @AH+ ← @AL+, counter = RW0 Byte transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – *4 *4 Byte retrieval (@AH+) – AL, counter = RW0 Byte retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – *3 Byte filling @AH+ ← AL, counter = RW0 – – – – – * * – – – MOVSW/MOVSWI 2 MOVSWD 2 *2 *2 *8 *8 *6 *6 Word transfer @AH+ ← @AL+, counter = RW0 Word transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – SCWEQ/SCWEQI SCWEQD 2 2 *1 *1 *8 *8 *7 *7 Word retrieval (@AH+) – AL, counter = RW0 Word retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – FILSW/FILSWI 2 6m +6 *8 *6 Word filling @AH+ ← AL, counter = RW0 – – – – – * * – – – m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case *3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) × n *5: 2 × (RW0) *6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) × n *8: 2 × (RW0) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 95 MB90420G/5G (A) Series ■ ORDERING INFORMATION Part number 96 Package MB90F428GAPF MB90F423GAPF MB90428GAPF MB90427GAPF MB90423GAPF MB90F428GPF MB90F423GPF MB90428GPF MB90427GPF MB90423GPF Plastic QFP, 100-pin (FPT-100P-M06) MB90F428GAPFV MB90F423GAPFV MB90428GAPFV MB90427GAPFV MB90423GAPFV MB90F428GPFV MB90F423GPFV MB90428GPFV MB90427GPFV MB90423GPFV Plastic LQFP, 100-pin (FPT-100P-M05) Remarks MB90420G/5G (A) Series ■ PACKAGE DIMENSIONS Plastic QFP, 100-pin (FPT-100P-M06) 23.90±0.40(.941±.016) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 20.00±0.20(.787±.008) 80 51 81 50 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) 12.35(.486) REF 16.30±0.40 (.642±.016) INDEX 31 100 "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.15±0.05(.006±.002) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.85(.742)REF 22.30±0.40(.878±.016) C 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10° 0.80±0.20 (.031±.008) 1994 FUJITSU LIMITED F100008-3C-2 Dimensions in mm (inches) (Continued) 97 MB90420G/5G (A) Series (Continued) Plastic LQFP, 100-pin (FPT-100P-M05) +0.20 16.00±0.20(.630±.008)SQ 75 1.50 –0.10 +.008 14.00±0.10(.551±.004)SQ 76 (Mouting height) .059 –.004 51 50 12.00 (.472) REF 15.00 (.591) NOM Details of "A" part 0.15(.006) INDEX 100 0.15(.006) 26 0.15(.006)MAX LEAD No. 1 "B" 25 0.40(.016)MAX "A" 0.50(.0197)TYP +0.08 0.18 –0.03 +.003 .007 –.001 +0.05 0.08(.003) M 0.127 –0.02 +.002 Details of "B" part .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) C 0.50±0.20(.020±.008) 0~10° 1995 FUJITSU LIMITED F100007S-2C-3 Dimensions in mm (inches) 98 MB90420G/5G (A) Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0012 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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