FUJITSU MICROELECTRONICS DATA SHEET DS07-13711-5E 16-Bit Original Microcontroller CMOS F2MC-16LX MB90420G/425G Series MB90423GA/423GC/F423GA/F423GC/427GA/427GC/428GA/428GC/ MB90F428GA/F428GC/V420G ■ DESCRIPTIONS The FUJITSU MICROELECTRONICS MB90420G/425G Series is a 16-bit general purpose high-capacity microcontroller designed for vehicle meter control applications etc. The instruction set retains the same AT architecture as the FUJITSU MICROELECTRONICS original F2MC-8L and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced (signed) multipler-divider computation and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing. ■ FEATURES • 16-bit input capture (4 channels) Detects rising, falling, or both edges. 16-bit capture register × 4 Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request. • 16-bit reload timer (2 channels) 16-bit reload timer operation (select toggle output or one-shot output) Event count function selection provided • Watch timer (main clock) Operates directly from oscillator clock. Compensates for oscillator deviation Read/write enabled second/minute/hour register Signal interrupt (Continued) The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.8 MB90420G/425G Series • 16-bit PPG (3 channels) Output pins (3) , external trigger input pin (1) Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26 • Delay interrupt Generates interrupt for task switching. Interruptions to CPU can be generated/deleted by software setting. • External interrupts (8 channels) 8-channel independent operation Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level. • A/D converter 10-bit or 8-bit resolution × 8 channels (input multiplexed) Conversion time : 6.13 µs or less (at fCP = 16 MHz) External trigger startup available (P50/INT0/ADTG) Internal timer startup available (16-bit reload timer 1) • UART (2 channels) Full duplex double buffer type Supports asynchronous/synchronous transfer (with start/stop bits) Internal timer can be selected as clock (16-bit reload timer 0) Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps Synchronous : 500 Kbps, 1Mbps, 2Mbps (at fCP = 16 MHz) • CAN interface *1 Conforms to CAN specifications version 2.0 Part A and B. Automatic resend in case of error. Automatic transfer in response to remote frame. 16 prioritized message buffers for data and messages for data and ID Multiple message support Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks Supports up to 1 Mbps CAN WAKEUP function (connects RX internally to INT0) • LCD controller/driver (1 channel) Segment driver and command driver with direct LCD panel (display) drive capability • Low voltage/Program Looping detect reset *2 Automatic reset when low voltage is detected Program Looping detection function • Stepping motor controller (4 channels) High current output for all channels × 4 Synchronized 8/10-bit PWM for all channels × 2 • Sound generator 8-bit PWM signal mixed with tone frequency from 8-bit reload counter. PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16MHz) Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1) • Input/output ports Push-pull output and Schmitt trigger input Programmable in bit units for input/output or peripheral signals. (Continued) 2 DS07-13711-5E MB90420G/425G Series (Continued) • Flash memory Supports automatic programming, Embeded AlgorithmTM, write/erase/erase pause/erase resume instructions Flag indicates algorithm completion Minato Electronics flash writer Boot block configuration Erasable by blocks Block protection by external programming voltage *1 : MB90420G series has 2 channels built-in, MB90425G series has 1 channel built-in *2 : Built-in to MB90420GA/425GA series only. Not built-in to MB90420GC/425GC series. Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc. DS07-13711-5E 3 MB90420G/425G Series ■ PRODUCT LINEUP • MB90420G Series Part number MB90F423GA MB90F423GC MB90423GA MB90423GC MB90V420G Parameter Flash ROM model Configuration Evaluation model F MC-16LX CPU CPU 1 system Clock System clock Mask ROM model 2 2 systems 1 system 2 systems 2 systems On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4) ROM Flash ROM 128 KB Mask ROM 128 KB External RAM 6 KB 6 KB 6 KB 2 channels CAN interface Low voltage/ CPU operation detection reset Yes No Packages Yes No No QFP100, LQFP100 PGA-256 ⎯ No Emulator dedicated power supply* * : When used with emulation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-50 Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) . • MB90425G Series Part number MB90F428GA MB90F428GC MB90427GA MB90427GC MB90428GA MB90428GC Parameter Configuration Flash ROM model CPU Clock System clock Mask ROM model 2 F MC-16LX CPU 1 system 2 systems 1 system 2 systems 1 system 2 systems On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4) ROM Flash ROM 128 KB Mask ROM 64 KB Mask ROM 128 KB RAM 6 KB 4 KB 6 KB CAN interface Low voltage/CPU operation detection reset Packages Emulator dedicated power supply 1 channel Yes No Yes No Yes No QFP100, LQFP100 ⎯ Note : MB90V420G can be used as evaluation model for MB90420G/425G series. 4 DS07-13711-5E MB90420G/425G Series ■ PIN ASSIGNMENTS • QFP 100 (TOP VIEW) VSS X0 X1 VCC P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1 P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 COM0 COM1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C P90/SEG22 P91/SEG23 V0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A P57/SGA RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS P53/INT3 MD2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 MD1 MD0 P52/INT2 (/TX1) P51/INT1 (/RX1) P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P50/INT0/ADTG AVRH AVCC V3 V2 V1 (FPT-100P-M06) DS07-13711-5E 5 MB90420G/425G Series • LQFP 100 (TOP VIEW) P57/SGA 76 X1A 77 X0A 78 VSS 79 X0 80 X1 81 VCC 82 P00/SIN0/INT4 83 P01/SOT0/INT5 84 P02/SCK0/INT6 85 P03/SIN1/INT7 86 P04/SOT1 87 P05/SCK1/TRG 88 P06/PPG0/TOT1 89 P07/PPG1/TIN1 90 P10/PPG2 91 P11/TOT0/WOT 92 P12/TIN0/IN3 93 P13/IN2 94 P14/IN1 95 P15/IN0 96 COM0 97 COM1 98 COM2 99 COM3 100 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P53/INT3 MD2 MD1 MD0 P52/INT2 (/TX1) P51/INT1 (/RX1) P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P50/INT0/ADTG AVRH AVCC V3 V2 V1 V0 P91/SEG23 P90/SEG22 (FPT-100P-M20) 6 DS07-13711-5E MB90420G/425G Series ■ PIN DESCRIPTIONS Pin no. Symbol LQFP QFP 80 82 X0 81 83 X1 78 80 X0A Circuit type A A 77 79 X1A 75 77 RST B P00 83 84 85 86 85 86 87 88 SIN0 89 G 89 90 91 93 Reset input pin. UART ch.0 serial data input pin. General purpose input/output port. SOT0 G UART ch.0 serial data output pin. INT5 INT5 external interrupt input pin. P02 General purpose input/output port. SCK0 G UART ch.0 serial clock input/output pin. INT6 INT6 external interrupt input pin. P03 General purpose input/output port. SIN1 G P04 SOT1 SCK1 UART ch.1 serial data input pin. INT7 external interrupt input pin. G General purpose input/output port. UART ch.1 serial data output pin. General purpose input/output port. G UART ch.1 serial clock input/output pin. TRG 16-bit PPG ch.0-2 external trigger input pin. P06 General purpose input/output port. PPG0 G PPG1 P10 PPG2 16-bit PPG ch.0 output pin. 16-bit reload timer ch.1 TOT output pin. General purpose input/output port. G TIN1 91 Low speed oscillator output pin. If no oscillator is connected, leave open. P01 P07 92 Low speed oscillator input pin. If no oscillator is connected, apply pull-down processing. INT4 external interrupt input pin. TOT1 90 High speed oscillator output pin. INT4 P05 88 High speed oscillator input pin. General purpose input/output port. INT7 87 Description 16-bit PPG ch.1 output pin. 16-bit reload timer ch.1 TIN output pin. G General purpose input/output port. 16-bit PPG ch.2 output pin. (Continued) DS07-13711-5E 7 MB90420G/425G Series Pin no. LQFP QFP Symbol Circuit type P11 92 93 94 95 Description General purpose input/output port. TOT0 G 16-bit reload timer ch.0 TOT output pin. WOT Real-time watch timer WOT output pin. P12 General purpose input/output port. TIN0 G IN3 16-bit reload timer ch.0 TIN output pin. Input capture ch.3 trigger input pin. P13 to P15 96 to 98 97 to 100 99 to 100, 1 to 2 COM0 to COM3 I LCD controller/driver common output pins. 1 to 8, 10 to 13 3 to 10, 12 to 15 SEG0 to SEG11 I LCD controller/driver segment output pins. IN2 to IN0 G General purpose input/output ports. 94 to 96 P36 to P37 14 to 15 16 to 17 16 to 20, 22 to 24 18 to 22, 24 to 26 SEG12 to SEG13 General purpose output ports. E P40 to P47 SEG14 to SEG21 28, 29 SEG22, SEG23 E 36 E 38 to 41, 43 to 46 INT0 G P60 to P67 AN0 to AN7 47 General purpose input output ports. F INT1 G (RX1 * ) General purpose input output port. INT2 G 1 (TX1 * ) 50 52 P53 INT3 INT1 external interrupt input pin. CAN interface 1 RX intput pin. P52 48 A/D converter input pins. General purpose input output port. 1 46 INT0 external interrupt input pin. A/D converter external trigger input pin. P51 45 LCD controller/driver segment output pins. General purpose input output ports. ADTG 36 to 39, 41 to 44 LCD controller/driver segment output pins. General purpose input output ports. P50 34 LCD controller/driver segment output pins. General purpose input output ports. P90, P91 26, 27 Input capture ch.0-2 trigger input pins. INT2 external interrupt input pin. CAN interface 1 TX output pin. G General purpose input output port. INT3 external interrupt input pin. (Continued) 8 DS07-13711-5E MB90420G/425G Series Pin no. LQFP QFP Symbol Circuit type P70 to P73 52 to 55 54 to 57 PWM1P0 PWM1M0 PWM2P0 PWM2M0 General purpose input output ports. H P74 to P77 57 to 60 59 to 62 PWM1P1 PWM1M1 PWM2P1 PWM2M1 64 to 67 PWM1P2 PWM1M2 PWM2P2 PWM2M2 H 69 to 72 72 74 73 75 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P54 TX0 P55 RX0 H 76 SGO H G G Stepping motor controller ch.3 output pins. General purpose input output port. CAN interface 0 TX output pin. General purpose output port. CAN interface 0 RX input pin. General purpose input output port. G FRCK P57 Stepping motor controller ch.2 output pins. General purpose input output ports. P56 74 Stepping motor controller ch.1 output pins. General purpose input output ports. P84 to P87 67 to 70 Stepping motor controller ch.0 output pins. General purpose input output ports. P80 to P83 62 to 65 Description Sound generator SGO output pin. Free-run timer clock input pin. 78 28 to 31 30 to 33 V0 to V3 ⎯ LCD controller /driver reference power supply pins. 56, 66 58, 68 DVCC ⎯ High current output buffer with dedicated power supply input pins (pin numbers 54-57, 59-62, 64-67, 69-72) . DVSS ⎯ High current output buffer with dedicated power supply GND pins (pin numbers 54-57, 59-62, 64-67, 69-72) . 51, 61, 71 53, 63, 73 SGA G General purpose input output port. 76 Sound generator SGA output pin. 32 34 AVCC ⎯ A/D converter dedicated power supply input pin. 35 37 AVSS ⎯ A/D converter dedicated GND supply pin. 33 35 AVRH ⎯ A/D converter Vref + input pin. Vref − AVss. (Continued) DS07-13711-5E 9 MB90420G/425G Series (Continued) Pin no. LQFP QFP 47, 48 49, 50 Symbol Circuit type MD0, MD1 C Description Test mode input pins. Connect to VCC. 2 49 51 MD2 C/D * 25 27 C ⎯ External capacitor pin. Connect an 0.1 µF capacitor between this pin and VSS. 21, 82 23, 84 VCC ⎯ Power supply input pins. VSS ⎯ GND power supply pins. 9, 40, 79 11, 42, 81 Text mode input pin. Connect to VSS. *1 : MB90420G series only. *2 : Type C in the flash ROM models, type D in the mask ROM models. 10 DS07-13711-5E MB90420G/425G Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation feedback resistance : approx. 1 MΩ (X0, X1 : MAIN) • Oscillation feedback resistance : approx. 10 MΩ (X0A, X1A : SUB) X1/X1A A X0/X0A Standby control signal • Pull-up resistance attached : approx. 50 kΩ, hysteresis input B Hysteresis input • Hysteresis input C Hysteresis input • Pull-down resistance attached : approx. 50 kΩ, hysteresis input Hyteresis input D • CMOS output • LCDC output • Hysteresis input E LCDC output Hysteresis input (Continued) DS07-13711-5E 11 MB90420G/425G Series (Continued) Type Circuit Remarks • CMOS output • Hysteresis input • Analog input F Analog input Hysteresis input • CMOS output • Hysteresis input G Hysteresis input • CMOS high current output • Hysteresis input High current H Hysteresis input • LCDC output I 12 LCDC output DS07-13711-5E MB90420G/425G Series ■ HANDLING DEVICES Precautions for Handling Semiconductor Devices • Strictly observe maximum rated voltages (prevent latchup) When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AVCC, AVRH) , analog input and dedicated power supply for the high current output buffer pins (DVCC) do not exceed the digital power supply (VCC) . Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH) and dedicated power supply for the high current output buffer pins (DVCC) may be turned on in any sequence. • Stable supply voltage Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage can cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial frequencies (50 Hz to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less. • Power-on procedures In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during poweron should be attained within 50 µs (0.2 V to 2.7 V) . • Treatment of unused pins If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 kΩ. Any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins. Any unused output pins should be left open. • Treatment of A/D converter power supply pins Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS. • Use of external clock signals Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and the X1 pin should be left open, as shown in the following figure. X0 OPEN X1 MB90420G/425G Series Sample external clock connection DS07-13711-5E 13 MB90420G/425G Series • Power supply pins Devices are designed to prevent problems such as latchup when multiple VCC and VSS supply pins are used, by providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all such pins should always be connected externally to power supplies and ground. As shown in figure below, all VCC power supply pins must have the same potential. All VSS power supply pins should be handled in the same way. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted operating range. VCC VSS VCC VSS VSS VCC VCC VSS VSS VCC Power supply input pins (VCC/VSS) In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and VSS as close to the pins as possible. • Proper sequence of A/D converter power supply analog input A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off before the digital power supply is switched on (VCC) . In both power-on and shut-off, care should be taken that AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, be sure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digital power supplies are turned off and on at the same time.) • Handling the power supply for high-current output buffer pins (DVCC, DVSS) Always apply power to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is turned on. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DVCC, DVSS) before switching off the digital power supply (VCC) . (There will be no problem if high-current output buffer pins and digital power supplies are turned off and on at the same time.) Even when high-current output buffer pins are used as general purpose ports, the power for high current output buffer pins (DVCC, DVSS) should be applied to these pins. • Pull-up/pull-down resistance The MB90420G/425G series does not support internal pull-up/pull-down resistance. If necessary, use external components. 14 DS07-13711-5E MB90420G/425G Series • Precautions for when not using a sub clock signal. If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave the X1A pin open. • Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. DS07-13711-5E 15 MB90420G/425G Series ■ BLOCK DIAGRAM P57/SGA P56/SGO/FRCK P55/RX0 P54/TX0 P53/INT3 P52/INT2 (/TX1) P51/INT1 (/RX1) P50/INT0/ADTG P00/SIN0/INT4 P01/SOT0/INT5 P02/SCK0/INT6 P03/SIN1/INT7 P04/SOT1 P05/SCK1/TRG P06/PPG0/TOT1 P07/PPG1/TIN1 Clock control circuit CPU F2MC-16LX core RAM Interrupt controller ROM Low voltage/ CPU operation detection reset Sound generator CAN controller Port 5 External interrupt (8 ch) Port 8 Stepping motor Controller 0/1/2/3 UART0/1 Prescaler 0/1 Port 0 PPG0/1/2 P10/PPG2 P11/TOT0/WOT P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 F2MC-16LX BUS X0, X1 X0A, X1A RST Port 7 A/D converter (8 ch) P67 to P60/ AN7 to AN0 AVCC/AVSS AVRH Port 9 P91, P90/ SEG23, SEG22 Port 4 P47 to P40/ SEG21 to SEG14 Port 3 P37, P36/ SEG13 to SEG12 Real-time Watch timer ICU0/1/2/3 Free-run timer P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 Port 6 Port 1 Reload timer 0/1 P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 LCD controller/ driver SEG11 to SEG0 COM3 to COM0 V3 to V0 Evaluation device (MB90V420G) No built-in ROM Built-in RAM is 6 KB. Note: MB90420G series is equipped with 2-channel CAN interface and MB90425G series is equipped with 1-channel CAN interface. MB90F423GA, MB90423GA, MB90F428GA, MB90427GA and MB90428GA have low voltage/CPU operation detection reset. MB90F423GC, MB90423GC, MB90F428GC, MB90427GC, MB90428GC and MB90V420G do not have low voltage/CPU operation detection reset. See “■ Product Lineup” for detail. 16 DS07-13711-5E MB90420G/425G Series ■ MEMORY MAP Single chip mode (with ROM mirror function) 000000H Peripheral area 0000C0H 000100H Register RAM area Address #2 003900H Peripheral area 004000H ROM area (FF bank image) 010000H Address #1 ROM area FFFFFFH : Internal access memory : Access prohibited Parts No. Address #1 Address #2 MB90423GA/GC FE0000H 001900H MB90427GA/GC FF0000H 001100H MB90428GA/GC FE0000H 001900H MB90F423GA/GC FE0000H 001900H MB90F428GA/GC FE0000H 001900H MB90V420G FE0000H 001900H Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH. DS07-13711-5E 17 MB90420G/425G Series ■ I/O MAP • Other than CAN Interface Address Register name Symbol Read/write Peripheral function Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 - - XX XX XX (Disabled) 02H 03H Port 3 data register PDR3 R/W Port 3 XX - - - - - - 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 - - - - - -XX 0AH to 0FH (Disabled) 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 --000000 (Disabled) 12H 13H Port 3 direction register DDR3 R/W Port 3 00 - - - - - - 14H Port 4 direction register DDR4 R/W Port 4 00000000 15H Port 5 direction register DDR5 R/W Port 5 00000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 00000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 - - - - - - 00 1AH Analog input enable ADER R/W Port 6, A/D 11111111 1BH to 1FH (Disabled) 20H A/D control status register lower ADCSL R/W 21H A/D control status register higher ADCSH R/W 22H A/D data register lower ADCRL R 23H A/D data register higher ADCRH R/W 0 0 1 0 1 XXX Compare clear register CPCLR R/W XXXXXXXX R/W XXXXXXXX 24H 25H 26H R/W 00000000 A/D converter 16-bit free-run timer 00000000 XXXXXXXX 00000000 Timer data register TCDT 28H Timer control status register lower TCCSL R/W 00000000 29H Timer control status register higher TCCSH R/W 0- - 00000 27H R/W 00000000 (Continued) 18 DS07-13711-5E MB90420G/425G Series Address Register name Symbol Read/write Peripheral function 2AH PPG0 control status register lower PCNTL0 R/W 2BH PPG0 control status register higher PCNTH0 R/W 2CH PPG1 control status register lower PCNTL1 R/W 2DH PPG1 control status register higher PCNTH1 R/W 2EH PPG2 control status register lower PCNTL2 R/W 2FH PPG2 control status register higher PCNTH2 R/W 30H External interrupt enable ENIR R/W 31H External interrupt request EIRR R/W 32H External interrupt level lower ELVRL R/W 33H External interrupt level higher ELVRH R/W 00000000 34H Serial mode register 0 SMR0 R/W 00000-00 35H Serial control register 0 SCR0 R/W 16-bit PPG0 16-bit PPG1 16-bit PPG2 Initial value 00000000 000000000000000 000000000000000 000000000000000 External interrupt 00000000 00000000 00000100 UART 0 36H Input data register 0/ Output data register 0 SIDR0/ SODR0 R/W 37H Serial status register 0 SSR0 R/W 00001000 38H Serial mode register 1 SMR1 R/W 00000−00 39H Serial control register 1 SCR1 R/W 00000100 3AH Input data register 1/ Output data register 1 SIDR1/ SODR1 R/W 3BH Serial status register 1 SSR1 R/W UART1 XXXXXXXX XXXXXXXX 00001000 (Disabled) 3CH 3DH Clock division control register 0 CDCR0 R/W Prescaler 0---0000 3EH CAN wake-up control register CWUCR R/W CAN -------0 3FH Clock division control register 1 CDCR1 R/W Prescaler 0---0000 40H to 4FH Area reserved for CAN interface 0 50H Timer control status register 0 lower TMCSR0L R/W 51H Timer control status register 0 highTMCSR0H er R/W 53H Timer register 0/ Reload register 0 R/W 54H Timer control status register 1 lower TMCSR1L R/W 55H Timer control status register 1 highTMCSR1H er R/W 57H Timer register 1/ Reload register 1 TMR1/ TMRLR1 R/W 58H Watch timer control register lower WTCRL R/W 59H Watch timer control register higher WTCRH R/W 52H 56H TMR0/ TMRLR0 00000000 16-bit reload timer 0 - - -00000 XXXXXXXX XXXXXXXX 00000000 16-bit reload timer 1 - - - 00000 XXXXXXXX XXXXXXXX Real-time watch timer 000- - 000 00000000 (Continued) DS07-13711-5E 19 MB90420G/425G Series Address Register name Symbol Read/write Peripheral function Initial value 5AH Sound control register lower SGCRL R/W 00000000 5BH Sound control register higher SGCRH R/W 0 - - - - - 00 5CH Frequency data register SGFR R/W 5DH Amplitude data register SGAR R/W 5EH Decrement grade register SGDR R/W XXXXXXXX 5FH Tone count register SGTR R/W XXXXXXXX Input capture register 0 IPCP0 R 60H 61H 62H 63H 64H 65H 66H 67H 68H Input capture register 1 IPCP1 R Input capture register 2 IPCP2 R IPCP3 R Input capture control status 0/1 ICS01 R/W 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input capture 2/3 Input capture register 3 XXXXXXXX XXXXXXXX Input capture 0/1 69H 6AH Sound generator XXXXXXXX XXXXXXXX XXXXXXXX Input capture 0/1 00000000 Input capture 2/3 00000000 LCD controller/ driver 00010000 (Disabled) Input capture control status 2/3 ICS23 6BH R/W (Disabled) 6CH LCD control register lower LCRL R/W 6DH LCD control register higher LCRH R/W 6EH Low voltage/CPU operation detection reset control register LVRC R/W Low voltage/CPU operation detection reset 10111000 6FH ROM mirror ROMM W ROM mirror XXXXXXX1 70H to 7FH 80H Area reserved for CAN interface 1 PWM control register 0 PWC0 81H 82H PWM control register 1 PWC1 87H to 9DH Stepping motor controller0 00000--0 R/W Stepping motor controller1 00000--0 Stepping motor controller2 00000--0 Stepping motor controller3 00000--0 (Disabled) PWM control register 2 PWC2 85H 86H R/W (Disabled) 83H 84H 00000000 R/W (Disabled) PWM control register 3 PWC3 R/W (Disabled) (Continued) 20 DS07-13711-5E MB90420G/425G Series Address Register name Symbol Read/write Peripheral function Initial value PACSR R/W Address match detection function - - - - - 0-0 DIRR R/W Delayed interrupt - - - - - - -0 Power saving mode LPMCR R/W 00011000 Clock select CKSCR R/W Power saving control circuit 11111100 9EH ROM correction control register 9FH Delay interrupt/release A0H A1H A2H to A7H (Disabled) A8H Watchdog control WDTC R/W Watchdog timer XXXXX 1 1 1 A9H Time base timer control register TBTC R/W Time base timer 1 - -00100 AAH Watch timer control register WTC R/W Watch timer (sub-clock) 1X000000 Flash interface 0 0 0 X 0 XX 0 ABH to ADH AEH (Disabled) Flash control register AFH FMCS R/W (Disabled) B0H Interrupt control register 00 ICR00 R/W 00000111 B1H Interrupt control register 01 ICR01 R/W 00000111 B2H Interrupt control register 02 ICR02 R/W 00000111 B3H Interrupt control register 03 ICR03 R/W 00000111 B4H Interrupt control register 04 ICR04 R/W 00000111 B5H Interrupt control register 05 ICR05 R/W 00000111 B6H Interrupt control register 06 ICR06 R/W 00000111 B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 00000111 BAH Interrupt control register 10 ICR10 R/W 00000111 BBH Interrupt control register 11 ICR11 R/W 00000111 BCH Interrupt control register 12 ICR12 R/W 00000111 BDH Interrupt control register 13 ICR13 R/W 00000111 BEH Interrupt control register 14 ICR14 R/W 00000111 BFH Interrupt control register 15 ICR15 R/W 00000111 C0H to FFH Interrupt controller 00000111 00000111 (Disabled) (Continued) DS07-13711-5E 21 MB90420G/425G Series Address Register name Symbol Read/write Peripheral function Initial value 1FF0H ROM correction address 0 PADR0 R/W XXXXXXXX 1FF1H ROM correction address 1 PADR0 R/W XXXXXXXX 1FF2H ROM correction address 2 PADR0 R/W 1FF3H ROM correction address 3 PADR1 R/W 1FF4H ROM correction address 4 PADR1 R/W XXXXXXXX 1FF5H ROM correction address 5 PADR1 R/W XXXXXXXX 3900H to 391FH 3920H 3921H 3922H 3923H 3924H 3925H 3929H 392AH 392BH 392CH 392DH PPG0 down counter register PDCR0 R PPG0 cycle setting register PCSR0 W PPG0 duty setting register PDUT0 W 3931H 3932H 3933H 3934H 3935H 3936H to 3959H XXXXXXXX 11111111 11111111 16-bit PPG 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Disabled) PPG1 down counter register PDCR1 R PPG1 cycle setting register PCSR1 W PPG1 duty setting register PDUT1 W 392EH to 392FH 3930H XXXXXXXX (Disabled) 3926H to 3927H 3928H Address match detection function 11111111 11111111 16-bit PPG 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Disabled) PPG2 down counter register PDCR2 R PPG2 cycle setting register PCSR2 W PPG2 duty setting register PDUT2 W 11111111 11111111 16 bit PPG 2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Disabled) (Continued) 22 DS07-13711-5E MB90420G/425G Series Address Register name Symbol Read/write Peripheral function XXXXXXXX 395AH 395BH Initial value Sub second data register WTBR R/W 395CH XXXXXXXX Real time watch timer - - - XXXXX 395DH Second data register WTSR R/W 395EH Minute data register WTMR R/W - - XXXXXX 395FH Hour data register WTHR R/W - - - XXXXX 3960H to LCD display RAM 396BH VRAM R/W 396CH to 397FH 3980H LCD controller/ driver - - XXXXXX XXXXXXXX (Disabled) XXXXXXXX PWM1 compare register 0 PWC10 R/W PWM2 compare register 0 PWC20 R/W 3984H PWM1 select register 0 PWS10 R/W - - 000000 3985H PWM2 select register 0 PWS20 R/W -0000000 3981H 3982H 3983H 3986H to 3987H 3988H - - - - - - XX Stepping motor controller 0 XXXXXXXX - - - - - - XX (Disabled) XXXXXXXX PWM1 compare register 1 PWC11 R/W PWM2 compare register 1 PWC21 R/W 398CH PWM1 select register 1 PWS11 R/W --000000 398DH PWM2 select register 1 PWS21 R/W -0000000 3989H 398AH 398BH 398EH to 398FH 3990H - - - - - - XX Stepping motor controller 1 XXXXXXXX - - - - - - XX (Disabled) XXXXXXXX PWM1 compare register 2 PWC12 R/W PWM2 compare register 2 PWC22 R/W 3994H PWM1 select register 2 PWS12 R/W --000000 3995H PWM2 select register 2 PWS22 R/W -0000000 3991H 3992H 3993H 3996H to 3997H - - - - - - XX Stepping motor controller 2 XXXXXXXX - - - - - - XX (Disabled) (Continued) DS07-13711-5E 23 MB90420G/425G Series (Continued) Address 3998H Register name Symbol Read/write Peripheral function Initial value XXXXXXXX PWM1 compare register 3 PWC13 R/W PWM2 compare register 3 PWC23 R/W 399CH PWM1 select register 3 PWS13 R/W --000000 399DH PWM2 select register 3 PWS23 R/W -0000000 3999H 399AH 399BH - - - - - - XX Stepping motor controller 3 399EH to 39FFH (Disabled) 3A00H to 3AFFH Area reserved for CAN interface 0 3B00H to 3BFFH Area reserved for CAN interface 1 3C00H to 3CFFH Area reserved for CAN interface 0 3D00H to 3DFFH Area reserved for CAN interface 1 3E00H to 3EFFH (Disabled) XXXXXXXX - - - - - - XX • Initial value symbols : “0” initial value 0. “1” initial value 1. “X” initial value undetermined “-” initial value undetermined (none) • Write/read symbols : “R/W” read/write enabled “R” read only “W” write only • Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited. 24 DS07-13711-5E MB90420G/425G Series • I/O Map for CAN Interface Address CAN0 CAN1 000040H 000070H 000041H 000071H 000042H 000072H 000043H 000073H 000044H 000074H 000045H 000075H 000046H 000076H 000047H 000077H 000048H 000078H 000049H 000079H 00004AH 00007AH 00004BH 00007BH 00004CH 00007CH 00004DH 00007DH 00004EH 00007EH 00004FH 00007FH 003C00H 003D00H 003C01H 003D01H 003C02H 003D02H 003C03H 003D03H 003C04H 003D04H 003C05H 003D05H 003C06H 003D06H 003C07H 003D07H 003C08H 003D08H 003C09H 003D09H 003C0AH 003D0AH 003C0BH 003D0BH 003C0CH 003D0CH 003C0DH 003D0DH 003C0EH 003D0EH 003C0FH 003D0FH Register name Symbol Read/ write Initial value Message buffer valid area BVALR (R/W) 00000000 00000000 Transmission request register TREQR (R/W) 00000000 00000000 Transmission cancel register TCANR (W) 00000000 00000000 Transmission completed register TCR (R/W) 00000000 00000000 Receiving completed register RCR (R/W) 00000000 00000000 Remote request receiving register RRTRR (R/W) 00000000 00000000 Receiving overrun register ROVRR (R/W) 00000000 00000000 Receiving interrupt enable register RIER (R/W) 00000000 00000000 Control status register CSR (R/W, R) 00---000 0----0-1 Last event indicator register LEIR (R/W) -------- 000-0000 RX/TX error counter RTEC (R) 00000000 00000000 Bit timing register BTR (R/W) -1111111 11111111 IDE register IDER (R/W) Transmission RTR register TRTRR (R/W) Remote frame receiving wait register RFWTR (R/W) Transmission interrupt enable register TIER (R/W) XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX 00000000 00000000 (Continued) DS07-13711-5E 25 MB90420G/425G Series Address CAN0 CAN1 003C10H 003D10H 003C11H 003D11H 003C12H 003D12H 003C13H 003D13H 003C14H 003D14H 003C15H 003D15H 003C16H 003D16H 003C17H 003D17H 003C18H 003D18H 003C19H 003D19H 003C1AH 003D1AH Register name Acceptance mask select register Acceptance mask register 0 Acceptance mask register 1 Symbol AMSR AMR0 AMR1 Read/ write 003B00H to General purpose RAM 003B1FH 003A20H 003B20H 003A21H 003B21H 003A22H 003B22H 003A23H 003B23H 003A24H 003B24H 003A25H 003B25H 003A26H 003B26H 003A27H 003B27H 003A28H 003B28H 003A29H 003B29H 003A2AH 003B2AH ID register 0 ID register 1 ID register 2 ⎯ IDR0 IDR1 IDR2 003A2FH 003B2FH 003A30H 003B30H 003A31H 003B31H 003A32H 003B32H 003A33H 003B33H ID register 3 ID register 4 IDR3 IDR4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) (R/W) XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) (R/W) (R/W) 003A2CH 003B2CH 003A2EH 003B2EH XXXXXXXX (R/W) 003A2BH 003B2BH 003A2DH 003B2DH XXXXXXXX (R/W) 003C1BH 003D1BH 003A00H to 003A1FH Initial value (R/W) (R/W) (Continued) 26 DS07-13711-5E MB90420G/425G Series Address CAN0 CAN1 003A34H 003B34H 003A35H 003B35H 003A36H 003B36H 003A37H 003B37H 003A38H 003B38H 003A39H 003B39H 003A3AH 003B3AH Register name ID register 5 ID register 6 Symbol IDR5 IDR6 Read/ write 003A3FH 003B3FH 003A40H 003B40H 003A41H 003B41H 003A42H 003B42H 003A43H 003B43H 003A44H 003B44H 003A45H 003B45H 003A46H 003B46H 003A47H 003B47H 003A48H 003B48H 003A49H 003B49H 003A4AH 003B4AH ID register 7 ID register 8 ID register 9 ID register 10 IDR7 IDR8 IDR9 IDR10 003A4FH 003B4FH 003A50H 003B50H 003A51H 003B51H 003A52H 003B52H 003A53H 003B53H ID register 11 ID register 12 IDR11 IDR12 XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) (R/W) (R/W) 003A4CH 003B4CH 003A4EH 003B4EH XXXXX- - - (R/W) 003A4BH 003B4BH 003A4DH 003B4DH XXXXXXXX (R/W) 003A3CH 003B3CH 003A3EH 003B3EH XXXXXXXX (R/W) 003A3BH 003B3BH 003A3DH 003B3DH Initial value (R/W) (R/W) (Continued) DS07-13711-5E 27 MB90420G/425G Series Address CAN0 CAN1 003A54H 003B54H 003A55H 003B55H 003A56H 003B56H 003A57H 003B57H 003A58H 003B58H 003A59H 003B59H 003A5AH 003B5AH Register name ID register 13 ID register 14 Symbol IDR13 IDR14 Read/ write 003A5FH 003B5FH 003A60H 003B60H 003A61H 003B61H 003A62H 003B62H 003A63H 003B63H 003A64H 003B64H 003A65H 003B65H 003A66H 003B66H 003A67H 003B67H 003A68H 003B68H 003A69H 003B69H 003A6AH 003B6AH 003A6BH 003B6BH 003A6CH 003B6CH 003A6DH 003B6DH 003A6EH 003B6EH 003A6FH 003B6FH 003A70H 003B70H 003A71H 003B71H 003A72H 003B72H 003A73H 003B73H 003A74H 003B74H 003A75H 003B75H ID register 15 IDR15 XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX XXXXXXXX XXXXXXXX XXXXX- - - XXXXXXXX (R/W) 003A5CH 003B5CH 003A5EH 003B5EH XXXXXXXX (R/W) 003A5BH 003B5BH 003A5DH 003B5DH Initial value (R/W) DLC register 0 DLCR0 (R/W) - - - -XXXX - - - -XXXX DLC register 1 DLCR1 (R/W) - - - -XXXX - - - -XXXX DLC register 2 DLCR2 (R/W) - - - -XXXX - - - -XXXX DLC register 3 DLCR3 (R/W) - - - -XXXX - - - -XXXX DLC register 4 DLCR4 (R/W) - - - -XXXX - - - -XXXX DLC register 5 DLCR5 (R/W) - - - -XXXX - - - -XXXX DLC register 6 DLCR6 (R/W) - - - -XXXX - - - -XXXX DLC register 7 DLCR7 (R/W) - - - -XXXX - - - -XXXX DLC register 8 DLCR8 (R/W) - - - -XXXX - - - -XXXX DLC register 9 DLCR9 (R/W) - - - -XXXX - - - -XXXX DLC register 10 DLCR10 (R/W) - - - -XXXX - - - -XXXX (Continued) 28 DS07-13711-5E MB90420G/425G Series Address CAN0 CAN1 003A76H 003B76H 003A77H 003B77H 003A78H 003B78H 003A79H 003B79H 003A7AH 003B7AH 003A7BH 003B7BH 003A7CH 003B7CH 003A7DH 003B7DH 003A7EH 003B7EH Symbol Read/ write DLC register 11 DLCR11 (R/W) - - - -XXXX - - - -XXXX DLC register 12 DLCR12 (R/W) - - - -XXXX - - - -XXXX DLC register 13 DLCR13 (R/W) - - - -XXXX - - - -XXXX DLC register 14 DLCR14 (R/W) - - - -XXXX - - - -XXXX DLC register 15 DLCR15 (R/W) - - - -XXXX - - - -XXXX Register name Initial value 003A7FH 003B7FH 003A80H to 003A87H 003B80H to Data register 0 (8 bytes) 003B87H DTR0 (R/W) XXXXXXXX to XXXXXXXX 003A88H to 003A8FH 003B88H to Data register 1 (8 bytes) 003B8FH DTR1 (R/W) XXXXXXXX to XXXXXXXX 003A90H to 003A87H 003B90H to Data register 2 (8 bytes) 003B97H DTR2 (R/W) XXXXXXXX to XXXXXXXX 003A98H to 003A9FH 003B98H to Data register 3 (8 bytes) 003B9FH DTR3 (R/W) XXXXXXXX to XXXXXXXX 003AA0H 003BA0H to to Data register 4 (8 bytes) 003AA7H 003BA7H DTR4 (R/W) XXXXXXXX to XXXXXXXX 003AA8H 003BA8H to to Data register 5 (8 bytes) 003AAFH 003BAFH DTR5 (R/W) XXXXXXXX to XXXXXXXX 003AB0H 003BB0H to to Data register 6 (8 bytes) 003AB7H 003BB7H DTR6 (R/W) XXXXXXXX to XXXXXXXX 003AB8H 003BB8H to to Data register 7 (8 bytes) 003ABFH 003BBFH DTR7 (R/W) XXXXXXXX to XXXXXXXX 003AC0H 003BC0H to to Data register 8 (8 bytes) 003AC7H 003BC7H DTR8 (R/W) XXXXXXXX to XXXXXXXX 003AC8H 003BC8H to to Data register 9 (8 bytes) 003ACFH 003BCFH DTR9 (R/W) XXXXXXXX to XXXXXXXX (Continued) DS07-13711-5E 29 MB90420G/425G Series (Continued) Address Symbol Read/ write Initial value 003AD0H 003BD0H to to Data register 10 (8 bytes) 003AD7H 003BD7H DTR10 (R/W) XXXXXXXX to XXXXXXXX 003AD8H 003BD8H to to Data register 11 (8 bytes) 003ADFH 003BDFH DTR11 (R/W) XXXXXXXX to XXXXXXXX 003AE0H 003BE0H to to Data register 12 (8 bytes) 003AE7H 003BE7H DTR12 (R/W) XXXXXXXX to XXXXXXXX 003AE8H 003BE8H to to Data register 13 (8 bytes) 003AEFH 003BEFH DTR13 (R/W) XXXXXXXX to XXXXXXXX 003AF0H to 003AF7H 003BF0H to Data register 14 (8 bytes) 003BF7H DTR14 (R/W) XXXXXXXX to XXXXXXXX 003AF8H 003BF8H to to Data register 15 (8 bytes) 003AFFH 003BFFH DTR15 (R/W) XXXXXXXX to XXXXXXXX CAN0 30 CAN1 Register name DS07-13711-5E MB90420G/425G Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source EI2OS compatible Interrupt vector Number Address Interrupt control register Priority ICR Address *2 High Reset × #08 08H FFFFDCH ⎯ ⎯ INT9 instruction × #09 09H FFFFD8H ⎯ ⎯ Exception processing × #10 0AH FFFFD4H ⎯ ⎯ CAN0 RX × #11 0BH FFFFD0H CAN0 TX/NS × #12 0CH FFFFCCH ICR00 0000B0H *1 CAN1 RX × #13 0DH FFFFC8H CAN1 TX/NS × #14 0EH FFFFC4H ICR01 0000B1H *1 Input capture 0 #15 0FH FFFFC0H DTP/external interrupt - ch 0 detected #16 10H FFFFBCH ICR02 0000B2H *1 Reload timer 0 #17 11H FFFFB8H DTP/external interrupt - ch 1 detected #18 12H FFFFB4H ICR03 0000B3H *1 Input capture 1 #19 13H FFFFB0H DTP/external interrupt - ch 2 detected #20 14H FFFFACH ICR04 0000B4H *1 Input capture 2 #21 15H FFFFA8H DTP/external interrupt - ch 3 detected #22 16H FFFFA4H ICR05 0000B5H *1 Input capture 3 #23 17H FFFFA0H DTP/external interrupt - ch 4/5 detected #24 18H FFFF9CH ICR06 0000B6H *1 PPG timer 0 #25 19H FFFF98H DTP/external interrupt - ch 6/7 detected #26 1AH FFFF94H ICR07 0000B7H *1 PPG timer 1 #27 1BH FFFF90H Reload timer 1 #28 1CH FFFF8CH ICR08 0000B8H *1 PPG timer 2 #29 1DH FFFF88H ICR09 0000B9H *1 ICR10 0000BAH *1 ICR11 0000BBH *1 ICR12 0000BCH *1 ICR13 0000BDH *1 ICR14 0000BEH *1 ICR15 0000BFH *1 Real time watch timer × #30 1EH FFFF84H Free-run timer over flow × #31 1FH FFFF80H #32 20H FFFF7CH A/D converter conversion end Free-run timer clear × #33 21H FFFF78H Sound generator × #34 22H FFFF74H Time base timer × #35 23H FFFF70H Watch timer (sub-clock) × #36 24H FFFF6CH UART 1 RX #37 25H FFFF68H UART 1 TX #38 26H FFFF64H UART 0 RX #39 27H FFFF60H UART 0 TX #40 28H FFFF5CH Flash memory status × #41 29H FFFF58H Delayed interrupt generator module × #42 2AH FFFF54H DS07-13711-5E Low 31 MB90420G/425G Series : Compatible, with EI2OS stop function : Compatible : Compatible when interrupt sources sharing ICR are not in use × : Not compatible *1 : • Peripheral functions sharing the ICR register have the same interrupt level. • If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other cannot be used. • When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services, the interrupt from the other function cannot be used. *2 : Priority applies when interrupts of the same level are generated. 32 DS07-13711-5E MB90420G/425G Series ■ PERIPHERAL FUNCTIONS 1. I/O Ports The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in bit units by the port direction register (DDR) as required. The following list shows each of the functions as well as the shared peripheral function for each port. • • • • • • • • • Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG) Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/watch timer/ICU) Port 3 : General purpose I/O port, shared with peripheral functions (LCD) Port 4 : General purpose I/O port, shared with peripheral functions (LCD) Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG) Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter) Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) Port 9 : General purpose I/O port, shared with peripheral functions (LCD) (1) List of Functions Port Pin name Port 0 P00/SIN0/INT4 to P07/PPG1 Port 1 P10/PPG2 to P15/IN0 Port 3 P36/SEG12, P37/SEG13 Port 4 P40/SEG14 to P47/SEG21 Port 5 P50/INT0 to P57/SGA Port 6 P60/AN0 to P67/AN7 Port 7 P70/PWM1P0 to P77/PWM2M1 Port 8 P80/PWM1P2 to P87/PWM2M3 Port 9 P90/SEG22, P91/SEG23 Input format Output format CMOS (hysteresis) (Automotive level*) CMOS Analog CMOS (hysteresis) (Automotive level*) CMOS (hysteresis) (Automotive level*) Function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function General purpose I/O port Peripheral function (Continued) DS07-13711-5E 33 MB90420G/425G Series (Continued) Port Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P07 P06 P05 P04 P03 P02 P01 P00 PPG1 PPG0 SCK1 SOT1 SIN1 SCK0 SOT0 SIN0 TIN1 TOT1 ⎯ ⎯ INT7 INT6 INT5 INT4 ⎯ ⎯ P15 P14 P13 P12 P11 P10 ⎯ ⎯ IN0 IN1 IN2 IN3 WOT PPG2 ⎯ ⎯ ⎯ ⎯ ⎯ TIN0 TOT0 ⎯ P37 P36 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SEG13 SEG12 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P47 P46 P45 P44 P43 P42 P41 P40 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 P57 P56 P55 P54 P53 P52 P51 P50 SGA SGO RX0 TX0 INT3 INT2 INT1 INT0 ⎯ FRCK ⎯ ⎯ ⎯ TX1 RX1 ⎯ P67 P66 P65 P64 P63 P62 P61 P60 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 P77 P76 P75 P74 P73 P72 P71 P70 PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 P87 P86 P85 P84 P83 P82 P81 P80 PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P91 P90 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SEG23 SEG22 *: Range of input voltage. For ratings see “3. DC Characteristics” in “■ ELECTRICAL CHARACTERISTICS”. Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write “0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset. 34 DS07-13711-5E MB90420G/425G Series (2) Block Diagrams Ports 0, 1, 3, 4, 5, 7, 8, 9 Peripheral function output Peripheral function input Peripheral function output enabled Internal data bus PDR (Port data register) PDR read Output latch PDR write Pin DDR (Port direction register) Direction latch DDR write DDR read Standby control (SPL = 1) or LCD output enabled Port 6 ADER Internal data bus PDR (Port data register) Analog input RDR read Output latch PDR write Pin DDR (Port direction register) Direction latch DDR write DDR read Standby control (SPL = 1) DS07-13711-5E 35 MB90420G/425G Series 2. Watchdog Timer/Time Base Timer/Watch Timer The watchdog timer, timer base timer, and watch timer have the following circuit configuration. • Watchdog timer : Watchdog counter, control register, watchdog reset circuit • Time base timer : 18-bit timer, interval interrupt control circuit • Watch timer : 15-bit timer, interval interrupt control circuit (1) Watchdog timer function The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit time base timer or 15-bit watch timer as a clock source, plus a control register and watchdog reset control circuit. After startup, this function will reset the CPU if not cleared within a given time. (2) Time base timer function The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock (base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register. (3) Watch timer function The watch timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator stabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the watch timer uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register. 36 DS07-13711-5E MB90420G/425G Series • Block Diagram Main base oscillator divided by 2 TBTC TBC1 Selector TBC0 TBR TBIE AND Q 211 213 216 218 TBTRES Clock input Time base timer 211 213 216 218 S R TBOF Time base interrupt WDTC WT1 Selector 2-bit counter OF CLR WT0 Watchdog reset generator circuit CLR WTE To WDGRST internal reset generator circuit F2MC-16LX bus WTC WDCS SCE AND Q SCM Power-on reset, sub-clock stop S R WTC2 to WTC0 Selector WTR WTIE WTOF AND Q S R 28 29 210 211 212 213 214 216 WTRES 210 213 214 216 Watch timer Clock input Sub base oscillator divided by 4 Watch interrupt WDTC PONR From power-on generator WRST ERST RST pin SRST From RST bit in LPMCR register DS07-13711-5E 37 MB90420G/425G Series 3. Input Capture This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits. (1) Input capture ( × 4) The input capture circuits consist of four independent external input pins and corresponding capture registers and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be generated. • The valid edge (rising edge, falling edge, both edges) of the external signal can be selected. • The four input capture circuits can operate independently. • The interrupt can be generated from the valid edge of the external input signal. (2) 16-bit free-run timer ( × 1) The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and prescaler. The output values from this counter are used as the base time for the input capture circuits. • The counter clock operation can be selected from 8 options. The eight internal clock settings are φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle. • Interrupts can be generated from overflow events, or from compare match events with the compare register. (Compare match operation requires a mode setting.) • The counter value can be initialized to “0000H” by a reset, soft clear, or a compare match with the compare register. (3) Block diagram φ interrupt #31 (1FH) IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Divider Clock 16-bit free-run timer F2MC-16LX bus 16-bit compare clear register Interrupt #33 (21H) Compare circuit MSI2 to MSI0 ICLR ICRE A/D startup Edge detection IN0/2 Capture data register 0/2 EG11 EG10 EG01 Edge detection Capture data register 1/3 ICP0 ICP1 ICE0 EG00 IN1/3 ICE1 Interrupt #19, #23 Interrupt #15, #21 38 DS07-13711-5E MB90420G/425G Series 4. 16-bit Reload Timer The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in internal clock mode, or count down at the detection of the designated edge of an external signal. The user may select either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus an underflow occurs when counting from the value [Reload register setting + 1]. A selection of two counter operating modes are available. In reload mode, the counter is reset to the count value and continues counting after an underflow, and in one-shot mode the count stops after an underflow. The counter can generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services (EI2OS) . (1) 16-bit Reload timer operating modes Clock mode Counter mode Reload mode Internal clock mode Event count mode (external clock mode) One-shot mode Reload mode One-shot mode 16-bit reload timer operation Soft trigger operation External trigger operation External gate input operation Soft trigger operation (2) Internal clock mode One of three input clocks is selected as the count clock, and can be used in one of the following operations. • Soft trigger operation When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation starts.Trigger input at the TRG bit is normally valid with an external trigger input, as well as an external gate input. • External trigger operation Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin. • External gate input operation Counting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin. (3) Event count mode (External clock mode) In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at the TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used. (4) Counter operation • Reload mode In down count operation, when an underflow event (transition from “0000H” to “FFFFH”) occurs, the set count value is reloaded and count operation continues. The function can be used as an interval timer by generating an interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can be output from the TOT0/1 pin. Counter clock Counter clock period Interval time Internal clock External clock 21/φ (0.125 µs) 0.125 µs to 8.192 ms 2 /φ (0.5 µs) 0.5 µs to 32.768 ms 25/φ (2.0 µs) 2.0 µs to 131.1 ms 23/φ or greater (0.5 µs) 0.5 µs or greater 3 φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz. DS07-13711-5E 39 MB90420G/425G Series (5) One-shot mode In down count operation, the count stops when an underflow event (transition from “0000H” to “FFFFH”) occurs. This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave form indicating that the count is in progress can be output form the TOT0 and TOT1 pins. (6) Block diagram Internal data bus TMRLR0 *1 <TMRLR1> 16-bit reload register Reload control circuit Reload signal TMR0 *1 <TMR1> 16-bit timer register (down counter) UF CLK Machine clock Prescaler Gate input 3 Valid clock decision circuit Wait signal To UART 0,1*1 <To A/D converter> CLK Input control circuit Pins P12/TIN0 *1 <P07/TIN1> Clock selector External clock 3 ⎯ 2 ⎯ ⎯ P11/TOT0 *1 <P06/TOT1> Select signal Operation control circuit CSL1 CSL0 WOD2 WOD1 WOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TNGSR0)*1 <TNGSR1> *1: Channel 0 and channel 1. Figures in < *2: Interrupt number 40 Pins EN Function selection ⎯ Output signal generator Inverted circuit > are for channel 1. Interrupt request signal #17 (11h)*2 <#28 (1CH)> DS07-13711-5E MB90420G/425G Series 5. Real Time Watch Timer The real time watch timer is composed of a real time watch timer control register, sub second data register, second/minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Because the MCU oscillation frequency operates on a given real time watch timer operation, a 4 MHz frequency is assumed. The real time watch timer operates as a real world timer and provides real world time information. • Block diagram OE Main oscillator clock 1/2 clock divider 21-bit prescaler CO OE WOT EN Sub second register UPDT ST Second CI EN counter LOAD Hour counter Minute counter CO 6-bit CO CO 6-bit 5-bit Second/minute/hour register INTE0 INT0 INTE1 INT1 INTE2 INT2 INTE3 INT3 IRQ#30 DS07-13711-5E 41 MB90420G/425G Series 6. PPG Timer The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting, and 16-bit compare register with buffer for duty setting, plus pin control circuits. The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output pulse can be adjusted by rewriting the values in the two 16-bit registers. (1) PWM function Programmable to output a pulse, synchronized with a trigger. Can also be used as a D/A converter with an external circuit. (2) One-shot function Detects the edge of a trigger input, and outputs a single pulse. (3) Pin control • Set to “1” at a duty match (priority) . • Reset to “0” at a counter borrow event • Has a fixed output mode to output a simple all “L” ( or “H”) signal. • Polarity can be specified (4) 16-bit down counter • Select from four types of counter operation clocks. Four internal clocks (φ, φ/4, φ/16, φ/64) cycles. • The counter value can be initialized to “FFFFH” at a reset or counter borrow event. φ : Machine clock (5) Interrupt requests • Timer startup • Counter borrow event (period match) • Duty match event • Counter borrow event (period match) or duty match event (6) Multiple channels can be set to start up at an external trigger, or to restart during operation. 42 DS07-13711-5E MB90420G/425G Series (7) Block diagram PCSR PDUT Prescaler 1/1 1/4 CK 1/16 Load PCNT 16-bit down counter 1/64 Start CMP Borrow PPG mask Machine clock S PPG output Q R Inversion bit Enable Trigger input P05/SCK1/TRG Interrupt selection Interrupt IRQ#25, 27, 29 Edge detection Soft trigger DS07-13711-5E 43 MB90420G/425G Series 7. Delayed Interrupt Generator Module The delayed interrupt generator module is a module that generates interrupts for task switching. This module makes it possible to use software to generate/cancel interrupt requests to the F2MC-16LX CPU. • Block diagram F2MC-16LX bus Delayed interrupt source generate/delete decoder Source latch 44 DS07-13711-5E MB90420G/425G Series 8. DTP/External Interrupt Circuit The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected peripheral device and the F2MC-16LX CPU and sends interrupt requests or data transfer requests generated from the peripheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligent I/O services (EI2OS) . (1) DTP/external interrupt function The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source. And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an external interrupt or start the expanded intelligent I/O service (EI2OS) . When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI2OS) is prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the EI2OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, then branching to an interrupt routine after the completion of the specified number of data transfers. External interrupt Input pins Interrupt sources DTP function 8 pins (P50/INT0/ADTG to P53/INT3, P00/SIN0/INT4 to P03/INT7) Request level setting register (ELVR) sets the detection level, or selected edge for each pin “H” level/ “L” level/ rising edge/falling edge input “H” level/ “L” level input Interrupt numbers #16 (10H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH) Interrupt control DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output Interrupt flags DTP/interrupt enable register (EIRR) stores interrupt sources Process selection When EI2OS prohibited (ICR : ISE = 0) When EI2OS is enabled (ICR : ISE = 1) Processing Branch to external interrupt processing routine EI2OS performs automatic data transfer, then after a specified number of cycles, branches to an interrupt routine ICR : Interrupt control register DS07-13711-5E 45 MB90420G/425G Series (2) Block diagram Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin Selector Selector Internal data bus P03/INT7 Pin P50/INT0 Pin Selector Selector P02/INT6 Pin P51/INT1 Selector Pin Selector P01/INT5 Pin P52/INT2 Selector Pin Selector Pin P00/INT4 P53/INT3 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request number #16 (10H) #18 (12H) #20 (14H) #22 (16H) #24 (18H) #26 (1AH) EN7 46 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DS07-13711-5E MB90420G/425G Series 9. 8/10-bit A/D Converter The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analog input voltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, and the conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input from an external signal pin. (1) 8/10-bit A/D converter functions The A/D converter takes analog voltage signals (input voltage) input at analog input pins, and converts these to digital values, providing the following features. • Minimum conversion time is 6.13 µs (at machine clock frequency of 16 MHz, including sampling time) . • Minimum sampling time is 3.75 µs (at machine clock 16 MHz) • The conversion method is an RC sequential conversion in comparison with a sample hold circuit. • Either 10-bit or 8-bit resolution can be selected. • The analog input pin can select from 8 channels by a program setting. • At completion of A/D conversion, an interrupt request can be generated, or EI2OS can be started. • Because the conversion data protection function operates in an interrupt enabled state, no data is lost even in continuous conversion. • The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external trigger input (falling edge) . Three conversion modes are available Conversion mode Single conversion operation Single conversion mode Scan conversion operation Converts multiple consecutive channels (up Converts the specified channel (1 channel to 8 channels may be specified) one time, only) one time, then stops. then stops. Continuous conversion Converts the specified channel (1 channel Converts multiple consecutive channels (up mode only) repeatedly. to 8 channels may be specified) repeatedly. Converts multiple consecutive channels (up Converts the specified channel (1 channel to 8 channels may be specified) , however Stop conversion mode only) one time, then pauses, waits until pauses after conversion of each channel, the next start is applied. waits until the next start is applied. DS07-13711-5E 47 MB90420G/425G Series (2) Block diagram AVCC AVRH AVSS D/A converter Sequential comparator register Comparator Decoder Sample & hold circuit A/D data register F2MC-16LX bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit MPX ADCRH, L A/D control status register, high A/D control status register, low 16-bit reload timer 1 Timer start P50/ADTG φ 48 Trigger start ADCSH, L Operating clock Prescaler DS07-13711-5E MB90420G/425G Series 10. UART The UART is a general purpose serial data communication interface for synchronous communication, or asynchronous (start-stop synchronized) communication with external devices. Functions include normal bi-directional functions, as well as master/slave type communication functions (multi-processor mode : master side only supported) . (1) UART Functions The UART is a general purpose serial data communication interface for sending and receiving of serial data with other CPU’s or peripheral devices, and provides the following functions. Functions Data buffer Transfer modes Baud rate Data length Signal type Receiving error detection Interrupt request Master/slave type communication function (multi-processor mode) Full duplex double buffer • Clock synchronous (no start/stop bits) • Clock asynchronous (start-stop synchronized) • Exclusive baud rate generator provides a selection of 8 rates • External clock input enabled • Internal clock (can use internal clock feed from 16-bit reload timer) • 7-bit (asynchronous normal mode only) • 8-bit NRZ (Non return to zero) • Framing errors • Overrun errors • Parity errors (not enabled in multiprocessor mode) • Receiving interrupt (receiving completed, receiving error detection) • Sending interrupt (sending completed) • Sending/receiving both compatible with expanded intelligent I/O services (EI2OS) 1 (master) -to-n (slave) communication enabled (only master side supported) . Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only. Operating mode 0 Data length No parity Normal mode 1 Multi-processor mode 2 Normal mode Parity 7-bit or 8-bit Synchronization Asynchronous 8+1* ⎯ Asynchronous 8 ⎯ Synchronous 1 Stop bit length 1-bit or 2-bit *2 None ⎯ : Setting not available *1 : “+ ” indicates an address/data selection bit (A/D) for communication control. *2 : In receiving only one stop bit is detected. DS07-13711-5E 49 MB90420G/425G Series (2) Block diagram Control bus Machine clock Exclusive baud rate generator Communication prescaler Control register (CDCR) Receiving interrupt signals #39 (27H) * <#37 (25H) *> Sending interrupt signals #40 (28H) * <#38 (26H) *> Sending clock Clock selector Receiving clock 16-bit reload timer Pins P02/SCK0 <P05/SCK1> Receiving control circuit Sending control circuit Start bit detection circuit Sending start circuit Receiving bit counter Sending bit counter Receiving parity counter Sending parity counter Pin P01/SOT0 <P04/SOT1> Receiving shift register Pins P00/SIN0 <P03/SIN1> Sending shift register Receiving end SIDR0/1 Sending start SODR0/1 Receiving status judging circuit EI2OS receiving error generator circuit (to CPU) Internal data bus SMR0/1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0/1 register PEN P SBL CL A/D REC RXE TXE SSR0/1 register PE ORE FRE RDRF TDRE BOS RIE TIE *: Interrupt number 50 DS07-13711-5E MB90420G/425G Series 11. CAN Controller The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controller area network) controller is the standard protocol for serial transmissions among automotive controllers and is widely used in the industry. (1) CAN controller features The CAN controller has the following features. • Conforms to CAN specifications version 2.0 A and B. Supports sending and receiving in standard frame and expanded frame format. • Supports data frame sending by means of remote frame receiving. • 16 sending/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration • Supports full bit compare, full bit mask as well as partial bet mask filtering. Provides two receiving mask registers for either standard frame or expanded frame format. • Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz) • CAN WAKE UP function • The MB90420G series has a two-channel built-in CAN controller. The MB90425G series has a 1-channel builtin CAN controller. DS07-13711-5E 51 MB90420G/425G Series (2) Block diagram F2MC-16LX bus Machine clock PSC PR PH RSJ TOE TS RS CSR HALT NIE NT NS1,0 TQ (operating clock) Prescaler 1-to-64 frequency divider Bit timing generator SYNC, TSEG1, TSEG2 BTR Node status change interrupt generator Bus state machine Node status change interrupt Error control RTEC Send/receive sequencer BVALR TREQR TBFx clear Send buffer decision TBFX Data counter TCANR TRTRR TCR TBFx, set, clear TIER Sending completed interrupt generator RCR RBFx, set RIER Receiving completed interrupt generator RRTRR RBFx, TBFx, set clear IDR0 ~ 15, DLCR0 ~ 15, DTR0 ~ 15, RAM ARBLOST RBFx set TDLC RDLC Receiving completed interrupt Receiving bufferx decision RBFX RAM address generator ACK CRCER CRC generator error check Receiving shift register IDSEL Receiving filter TX generator generator ARBLOST 0 1 Output driver Stuffing CRC Sending completed interrupt AMSR AMR1 Overload frame generator Send shift register RFWTR AMR0 Error frame generator Receiving filter control TDLC RDLC IDSEL BITER, STFER, CRCER, FRMER, ACKER TBFX ROVRR IDLE, SUSPND, TX, RX, ERR, OVRLD BITER ACKER FRMER STFER Destuffing/ stuffing error check Arbitration check Bit error check Acknowledge error check PH1 Form error check Input latch RX RBFX, TBFX, RDLC, TDLC, IDSEL LEIR 52 DS07-13711-5E MB90420G/425G Series 12. LCD Controller/Driver The LCD controller/driver has a built-in 16 × 8-bit display data memory, and controls the LCD display by means of four common outputs and 24 segment outputs. A selection of three duty outputs are available. This block can drive an LCD (liquid crystal display) panel directly. (1) LCD controller/driver functions The LCD controller/driver provides functions for directly displaying the contents of display data memory (display RAM) on the LCD panel by means of segment output and common output. • LCD drive voltage divider resistance is built-in. External divider resistance can also be connected. • Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used. • 16-byte display data memory (display RAM) is built-in. • The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) . • Drives the LCD directly. Bias 1/2 duty 1/2 bias 1/3 bias 1/3 duty 1/4 duty × × × : Recommended mode × : Use prohibited Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they cannot be used for segment output. DS07-13711-5E 53 MB90420G/425G Series (2) Block diagram V0 V1 V2 V3 LCDC control register Low (LCRL) Divider resistance 4 Prescaler Timing controller Common driver COM0 COM1 COM2 COM3 AC circuit Internal data bus Time base timer output 24 Display RAM, 16 × 8 bits Segment driver SEG0 SEG1 SEG2 SEG3 SEG4 ∼ SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 LCDC control register High (LCRH) Controller 54 Driver DS07-13711-5E MB90420G/425G Series 13. Low voltage/Program Looping Detection Reset Circuit The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal is generated. The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal reset signal if not cleared within a given time after startup. (1) Low voltage detection reset circuit Detection voltage 4.0 V ± 0.3 V When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an internal reset signal is output. Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage condition generates an internal reset and releases stop mode. During an internal RAM write cycle, an internal reset is generated after the completion of writing. During the output of this internal reset, the reset output from the low voltage detection circuit is suppressed. (2) Program Looping detection reset circuit The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has a width of 5 machine cycles. Interval duration 220/FC (Approx. 262 ms *) * : This value assumes an oscillation clock waveform of 4 MHz. During recovery from standby mode the detection period is the maximum interval plus 20 µs. This circuit does not operate in modes where CPU operation is stopped. The Program Looping detection reset circuit counter is cleared under any of the following conditions. 1. Writing “0” to the LVRC register CL bit 2. Internal reset 3. Main oscillation clock stop 4. Transition to sleep mode 5. Transition to time base timer mode or watch mode DS07-13711-5E 55 MB90420G/425G Series (3) Block diagram Voltage comparator circuit VCC − + VSS Constant voltage source Program Looping detection circuit Main oscillation clock Over flow Noise canceller Clear Reserved Reserved Reserved Reserved CL Internal reset Counter LVRF Reserved CPUF Low voltage/CPU operation detection reset control register (LVRC) Internal data bus 56 DS07-13711-5E MB90420G/425G Series 14. Stepping Motor Controller The stepping motor controller is composed of two PWM pulse generators, four motor drivers and selector logic circuits. The four motor drivers have a high output drive capacity and can be directly connected to the four ends of two motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse generators. • Block diagram Machine clock OE1 Prescaler CK PWM1Pn PWM1 pulse generator EN P1 Output enable Selector PWM PWM1Mn P0 PWM1 compare register PWM1 selector register OE2 Output enable CK SC PWM2Pn PWM2 pulse generator CE EN Selector PWM PWM2Mn Load PWM2 compare register DS07-13711-5E BS PWM2 select register n:0~3 57 MB90420G/425G Series 15. Sound Generator The sound generator is composed of a sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter, and tone pulse counter. • Block diagram Clock input Prescaler S1 S0 8-bit PWM pulse generator CO EN PWM CI Frequency counter Toggle flip-flop CO EN Reload Amplitude data register Reload Q 1/d Frequency data register DEC DEC Decrement counter D EN CI CO EN SGA OE1 Decrement grade register Tone pulse counter Tone count register Blend TONE OE1 SGO OE2 OE2 CI CO EN INTE INT ST IRQ#34 58 DS07-13711-5E MB90420G/425G Series 16. Address Match Detect Function If the address setting is the same as the address detection register, an INT9 instruction is executed. The integrated address match detection function can be implemented by processing the INT9 interrupt service routine. Two address registers are used, each with its own compare enable bit. When there is a match between the address register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is forcibly executed by the CPU. Address latch Address detection register Compare • Block diagram Enable bit F2MC-16LX CPU core F2MC-16LX bus DS07-13711-5E 59 MB90420G/425G Series 17. ROM Mirror Function Select Module The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated to the FF bank to be viewed in the 00 bank. • Block diagram F2MC-16LX bus ROM mirror function select register Address area FF bank 00 bank ROM 60 DS07-13711-5E MB90420G/425G Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Symbol VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2 AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*2 DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2 VI VSS − 0.3 VCC + 0.3 V *3 VO VSS − 0.3 VCC + 0.3 V ICLAMP − 400 + 400 µA *7 ⎯ 4 mA *7 IOL1 ⎯ 15 mA Other than P70 to P77, and P80 to P87 IOL2 ⎯ 40 mA P70 to P77, P80 to P87 IOLAV1 ⎯ 4 mA Other than P70 to P77, and P80 to P87 IOLAV2 ⎯ 30 mA P70 to P77, P80 to P87 Σ IOL1 ⎯ 100 mA Other than P70 to P77, and P80 to P87 Σ IOL2 ⎯ 330 mA P70 to P77, P80 to P87 Σ IOLAV1 ⎯ 50 mA Other than P70 to P77, and P80 to P87 Σ IOLAV2 ⎯ 250 mA P70 to P77, P80 to P87 I OH1 4 ⎯ − 15 mA Other than P70 to P77, and P80 to P87 I OH2 4 ⎯ − 40 mA P70 to P77, P80 to P87 I OHAV1 5 ⎯ − 4 mA Other than P70 to P77, and P80 to P87 I OHAV2 5 * ⎯ − 30 mA P70 to P77, P80 to P87 Σ IOH1 ⎯ − 100 mA Other than P70 to P77, and P80 to P87 Σ IOH2 Maximum clamp current Total maximum clamp current Σ | ICLAMP | “L”level maximum output current*4 “L”level average output current*5 “L”level maximum total output current “H”level maximum output current “H”level average output current “H”level maximum total output current “H”level average total output current * * * ⎯ − 330 mA P70 to P77, and P80 to P87 ΣI OHAV1 6 ⎯ − 50 mA Other than P70 to P77, and P80 to P87 ΣI OHAV2 6 ⎯ − 250 mA P70 to P77, P80 to P87 * * Power consumption PD ⎯ 500 mW Operating temperature TA − 40 + 105 °C TSTG − 55 + 150 °C Storage temperature Remarks Max 1 “L”level average total output current Unit Min Input voltage*1 Output voltage* Rating *1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V. *2 : AVCC, AVRH and DVCC shall never exceed VCC. Also, AVRH shall never exceed AVCC. *3 : The maximum current to/from and input is limited by some means with extenal components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “operating factor”. (Continued) DS07-13711-5E 61 MB90420G/425G Series (Continued) *6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “ operating factor”. *7 : • Applicable to pins : P00 to P07, P10 to P15, P50 to P57, P70 to P77, P80 to P87 • Use within recommended operating conditions. • Use at DC voltage (current) . • The + B signal should always be applied with a limiting resistance placed between the + B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B signal input. • Sample recommended circuits : • Input/Output equivalent circuits Protective diode VCC P-ch Limiting resistance + B input (0 V to 16 V) N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 62 DS07-13711-5E MB90420G/425G Series 2. Recommended Operating Conditions (VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Power supply voltage VCC AVCC DVCC Value Min Max Unit Remarks 3.7 5.5 V (MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, MB90423GA) Low voltage detection reset starts to work when power supply voltage is 4.0 V ± 0.3 V. 3.0 5.5 V (MB90F428GC, MB90F423GC, MB90428GC, MB90427GC, MB90423GC) 4.3 5.5 V Holding stop operation status (MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, MB90423GA) 3.0 5.5 V Holding stop operation status (MB90F428GC, MB90F423GC, MB90428GC, MB90427GC, MB90423GC) Use a ceramic capacitor or other capacitor of equivalent frequency characteristics. A bypass capacitor on the VCC pin should have a capacitance greater than Cs. Smoothing capacitor* CS 0.1 1.0 µF Operating temperature TA − 40 + 105 °C * : For smoothing capacitor Cs connections, see the illustration below. • C pin connection C CS VSS DVSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-13711-5E 63 MB90420G/425G Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Value Pin Conditions Unit Remarks Parameter Symbol name Min Typ Max CMOS hysteresis ⎯ V CC + 0.3 V IHS ⎯ 0.8 V CC ⎯ V Automotive level “H”level input pin*1 input voltage ⎯ VCC − 0.3 ⎯ VCC + 0.3 V MD pin*2 VIHM ⎯ CMOS hysteresis ⎯ VSS − 0.3 ⎯ VILS ⎯ 0.5 VCC V Automotive level “L”level input pin*1 input voltage ⎯ VSS − 0.3 ⎯ VSS + 0.3 V MD pin*2 VILM ⎯ MB90F428GA/GC ⎯ 45 72 mA MB90F423GA/GC Operating frequency FCP = 16 MHz, ICC MB90428GA/GC normal operation ⎯ 38 61 mA MB90427GA/GC MB90423GA/GC MB90F428GA/GC ⎯ 15 24 mA MB90F423GA/GC Operating frequency ICCS FCP = 16 MHz, MB90428GA/GC sleep mode ⎯ 13 21 mA MB90427GA/GC MB90423GA/GC Operating frequency FCP = 2 MHz, ⎯ 0.75 1.0 mA ICTS time base timer mode MB90F428GC Operating frequency MB90F423GC FCP = 8 kHz, TA = + 25 °C, ⎯ 0.35 0.7 mA MB90428GC ICCL subclock operation MB90427GC MB90423GC Power supply MB90F428GC VCC Operating frequency current*3 MB90F423GC FCP = 8 kHz, TA = + 25 °C, ICCLS ⎯ 10 30 µA MB90428GC sub sleep operation MB90427GC MB90423GC MB90F428GC Operating frequency MB90F423GC FCP = 8 kHz, TA = + 25 °C, ⎯ 40 100 µA MB90428GC ICCT watch mode MB90427GC MB90423GC MB90F428GC MB90F423GC ⎯ 5 20 µA MB90428GC MB90427GC MB90423GC TA = + 25 °C, ICCH stop mode MB90F428GA MB90F423GA ⎯ 40 100 µA MB90428GA MB90427GA MB90423GA (Continued) 64 DS07-13711-5E MB90420G/425G Series (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Sym bol Input leakage current IIL All input pins Input capacitance 1 Pin name Conditions Value Unit Min Typ Max VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC − 5 ⎯ 5 µA CIN1 Other than Vcc, Vss, DVcc, DVss, Avcc, Avss, C, P70 to P77, P80 to P87 ⎯ ⎯ 5 15 pF Input capacitance 2 CIN2 P70 to P77, P80 to P87 ⎯ ⎯ 15 45 pF Pull-up resistance RUP RST, MD0, MD1 ⎯ 25 50 100 kΩ ⎯ 25 50 100 kΩ Pull-down resistance RDOWN MD2 Output H voltage 1 VOH1 Other than P70 to P77, P80 to P87 VCC = 4.5 V IOH = −4.0 mA VCC − 0.5 ⎯ ⎯ V Output H voltage 2 VOH2 P70 to P77, P80 to P87 VCC = 4.5 V IOH = −30.0 mA VCC − 0.5 ⎯ ⎯ V Output L voltage 1 VOL1 Other than P70 to P77, P80 to P87 VCC = 4.5 V IOL = 4.0 mA ⎯ ⎯ 0.4 V Output L voltage 2 VOL2 P70 to P77, P80 to P87 VCC = 4.5 V IOL = 30.0 mA ⎯ ⎯ 0.55 V PWM1Pn, Large current PWM1Mn, output drive ∆VOH2 PWM2Pn, capacity PWM2Mn, variation 1 n = 0 to 3 VCC = 4.5 V IOH = 30.0 mA VOH2 maximum variation 0 ⎯ 90 mV *4 VCC = 4.5 V IOH = 30.0 mA VOL2 maximum variation 0 ⎯ 90 mV *4 50 100 200 kΩ Large current output drive capacity variation 2 ∆VOL2 PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3 LCD internal divider resistance RLCD V0 to V1, V1 to V2, V2 to V3 ⎯ Remarks (Continued) DS07-13711-5E 65 MB90420G/425G Series (Continued) (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Pin name Parameter Symbol COM0 to COM3 output impedance RVCOM COMn (n = 0 to 3) SEG0 to SEG3 output impedance RVSEG ILCDC LCD leakage current Conditions Value Unit Min Typ Max ⎯ ⎯ ⎯ 2.5 kΩ SEGn (n = 00 to 23) ⎯ ⎯ ⎯ 15 kΩ V0 to V3 COMm (m = 0 to 3) SEGn (n = 00 to 23) ⎯ − 5.0 ⎯ + 5.0 µA Remarks *1 : All input pins except X0, X0A, MD0, MD1, MD2 pins. *2 : MD0, MD1, MD2 pins. *3 : Supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware that supply current levels differ depending on whether an external clock or oscillator is used. *4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simultaneously ON. Similarly for other channels. 66 DS07-13711-5E MB90420G/425G Series 4. AC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) (1) Clock timing Parameter Symbol Pin name FC Unit Typ Max X0, X1 ⎯ 4 ⎯ MHz FLC X0A, X1A ⎯ 32.768 ⎯ kHz tCYL X0, X1 ⎯ 250 ⎯ ns tLCYL X0A, X1A ⎯ 30.5 ⎯ µs PWH, PWL X0 10 ⎯ ⎯ ns PWLH, PWLL X0A ⎯ 15.2 ⎯ µs Base oscillation clock cycle time Input clock rise, fall time Value Min Base oscillation clock frequency Input clock pulse width Conditions ⎯ Remarks Use duty ratio of 40 to 60% as a guideline With external clock signal tcr, tcf X0, X0A ⎯ ⎯ 5 ns FCP ⎯ 2 ⎯ 16 MHz FLCP ⎯ ⎯ 8.192 ⎯ kHz Using sub clock tCP ⎯ 62.5 — 500 ns Using main clock, PLL clock tLCP ⎯ ⎯ 122.1 ⎯ µs Using sub clock Input operating clock frequency Input operating clock cycle time Using main clock, PLL clock • X0 clock timing tCYL 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr • X0A clock timing tLCYL 0.8 VCC X0A 0.2 VCC PWLL PWLH tcf DS07-13711-5E tcr 67 MB90420G/425G Series • Range of warranted operation Relation between internal operating clock frequency and supply voltage MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, MB90423GA range of warranted operation 5.5 MB90V420G range of warranted operation Supply voltage VCC (V) 4.5 3.7 3.3 3.0 PLL range of warranted operation MB90F428GC, MB90F423GC, MB90428GC, MB90427GC, MB90423GC range of warranted operation 2 8 12 16 Internal clock frequency fCP (MHz) The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA enter reset mode at supply voltage below 4 V ± 0.3 V. Relation between oscillator clock frequency and internal operating clock frequency Internal operating clock frequency PLL clock Main clock Multiplier ×1 Oscillation clock frequency 4 MHz 2 MHz ⎯ Multiplier ×2 Multiplier ×3 Multiplier ×4 8 MHz 12 MHz 16 MHz Frequency C1 C2 4 MHz 39 [pF] (Typ) 39 [pF] (Typ) • Sample oscillator circuit Oscillator element manufacturer Oscillator Murata Manufacturing Co., Ltd. CSTCR4M00G15 ( ) A-R0 MB90F428A X0 X1 CERALOCK ® C1 68 C2 DS07-13711-5E MB90420G/425G Series AC ratings are defined for the following measurement reference voltage values: • Input signal waveform Hysteresis input pin • Output signal waveform Output pin 0.8 VCC 2.4 V 0.5 VCC 0.8 V DS07-13711-5E 69 MB90420G/425G Series (2) Reset input (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Value Symbol Pin name Conditions Reset input time tRSTL ⎯ RST Min Max 16 tCP ⎯ Oscillator oscillation time* + 16 tCP ⎯ Unit Remarks ns In normal operation ms In stop mode, sub clock mode, sub sleep mode, watch mode *: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several hundred ms; for a FAR/ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 100 µs. Note : tCP : See “ (1) Clock input timing”. • Under normal operation tRSTL RST 0.5 VCC 0.5 VCC • In stop mode, sub clock mode, sub sleep mode, watch mode tRSTL RST 0.5 Vcc X0 Internal operation clock 0.5 Vcc 90 % of amplitude Oscillator oscillation time 16 tcp Oscillator stabilization wait time Execution of the instruction Internal reset 70 DS07-13711-5E MB90420G/425G Series (3) Power-on reset, power on conditions (VSS = 0.0 V, TA = 40 °C to + 105 °C) Parameter Symbol Power supply rise time Pin Conditions name tR Power supply start voltage VOFF Power supply attained voltage VON Power supply cutoff time tOFF VCC ⎯ Value Unit Min Max 0.05 30 ms ⎯ 0.2 V 2.7 ⎯ V 50 ⎯ ms Remarks For repeat operation tR 2.7 V VCC 0.2 V 0.2 V 0.2 V tOFF Extreme variations in voltage supply may activate a power-on reset. As the illustration below shows, when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however it is permissible to use the PLL clock during a voltage drop of 1V/s or less. 5.0 V VCC A rise slope of 50 mV or less is recommended 3.0 V 0V DS07-13711-5E VSS RAM data hold 71 MB90420G/425G Series (4) UART0, UART1 timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK fall to SOT delay time tSLOV Valid SIN to SCK rise tIVSH SCK rise to valid SIN hold time tSHIX Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH SCK fall to SOT delay time tSLOV Valid SIN to SCK rise tIVSH SCK rise to valid SIN hold time tSHIX Conditions Value Unit Min Max SCK0, SCK1 8 tCP ⎯ ns SCK0, SCK1 SOT0, SOT1 − 80 80 ns 100 ⎯ ns 60 ⎯ ns 4 tCP ⎯ ns 4 tCP ⎯ ns ⎯ 150 ns 60 ⎯ ns 60 ⎯ ns ⎯ SCK0, SCK1 SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SOT0, SOT1 ⎯ SCK0, SCK1 SIN0, SIN1 Remarks Internal shift clock mode output pin CL = 80 pF + 1•TTL External shift clock mode output pin CL = 80 pF + 1•TTL Notes : • AC ratings are for CLK synchronous mode. • CL is load capacitance connected to pin during testing. • tCP : See “ (1) Clock timing”. • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.5 VCC 0.5 VCC • External shift clock mode tSLSH SCK 0.5 VCC tSHSL 0.8 VCC 0.8 VCC 0.5 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 72 tSHIX 0.8 VCC 0.8 VCC 0.5 VCC 0.5 VCC DS07-13711-5E MB90420G/425G Series (5) Timer input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Symbol Pin name Conditions tTIWH tTIWL TIN0, TIN1, IN0, IN1, IN2, IN3, ⎯ Input pulse width Value Min Max 4 tCP ⎯ Unit Remarks ns Note : tCP : See “ (1) Clock timing”. • Timer input timing tTIWH 0.8 VCC TIN0 ∼ TIN1 IN0 ∼ IN3 tTIWL 0.8 VCC 0.5 VCC 0.5 VCC (6) Trigger input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Input pulse width Symbol Pin name Conditions tTRGH, tTRGL INT0 to INT7 ⎯ Value Unit Remarks ⎯ ns Under normal operation ⎯ µs In stop mode Min Max 5 tCP 1 Note : tCP : See “ (1) Clock timing”. • Trigger input timing tTRGH INT0 ∼ INT7 0.8 VCC tTRGL 0.8 VCC 0.5 VCC DS07-13711-5E 0.5 VCC 73 MB90420G/425G Series (7) Low voltage detection (VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks Detection voltage VDL VCC ⎯ 3.7 4.0 4.3 V During voltage drop Hysteresis width VHYS VCC ⎯ 0.1 ⎯ ⎯ V During voltage rise Power supply voltage fluctuation ratio dV/dt VCC ⎯ − 0.1 ⎯ 0.02 V/µs Detection delay time td ⎯ ⎯ ⎯ ⎯ 35 µs Internal reset VCC dV dt VHYS VDL td 74 td DS07-13711-5E MB90420G/425G Series 5. A/D Conversion Block (1) Electrical Characteristics (VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C) Parameter Symbol Pin name Resolution ⎯ Total error Value Unit Remarks Min Typ Max ⎯ ⎯ ⎯ 10 bit ⎯ ⎯ ⎯ ⎯ ±5.0 LSB Non-linear error ⎯ ⎯ ⎯ ⎯ ±2.5 LSB Differential linear error ⎯ ⎯ ⎯ ⎯ ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS AVSS AVSS − 3.5 LSB + 0.5 LSB + 4.5 LSB V Full scale transition voltage VFST AN0 to AN7 AVRH AVRH AVRH − 6.5 LSB − 1.5 LSB + 1.5 LSB V 1 LSB = (AVRH − AVSS) / 1024 Sampling time tSMP ⎯ 2.000 ⎯ ⎯ µs *1 Compare time tCMP ⎯ 4.125 ⎯ ⎯ µs *2 A/D conversion time tCNV ⎯ 6.125 ⎯ ⎯ µs *3 Analog port input current IAIN AN0 to AN7 ⎯ ⎯ 10 µA VAVSS = VAIN = VAVCC Analog input current VAIN AN0 to AN7 0 ⎯ AVRH V AVR+ AVRH 3.0 ⎯ AVCC V ⎯ 2.3 6.0 mA ⎯ ⎯ 5 µA *4 Reference voltage Power supply current IA IAH AVCC Reference voltage feed current IR AVRH 50 180 260 µA VAVRH = 5.0 V IRH AVRH ⎯ ⎯ 5 µA *4 Inter-channel variation — AN0 to AN7 ⎯ ⎯ 4 LSB *1 : At FCP = 16 MHz, tSMP = 32 × tCP = 2.000 (µs) . *2 : At FCP = 16 MHz, tCMP = 66 × tCP = 4.125 (µs) . *3 : Equivalent to conversion time per channel at FCP = 16 MHz, and selection of tSMP = 32 × tCP and tCMP = 66 × tCP. *4 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in stop mode. DS07-13711-5E 75 MB90420G/425G Series • Notes of the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion presicion. • Analog input circuit model R Analog input Comparator C During sampling : ON R 2.4 kΩ (Max) 2.6 kΩ (Max) 3.2 kΩ (Max) MB90420GA/420GC MB90F420GA/F420GC MB90V420G C 36.4 pF (Max) 28.0 pF (Max) 30.0 pF (Max) Note : The values are reference values. • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 20 kΩ) MB90V420G MB90V420G 100 90 80 70 60 50 40 30 20 10 0 MB90F420GA/ F420GC 0 5 10 External impedance [kΩ] External impedance [kΩ] (External impedance = 0 kΩ to 100 kΩ) MB90420GA/ 420GC 15 20 25 30 35 Minimum sampling time [µs] 20 18 16 14 12 10 8 6 4 2 0 MB90F420GA/ F420GC 0 1 2 3 MB90420GA/ 420GC 4 5 6 7 8 Minimum sampling time [µs] • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |AVRH| becomes smaller, values of relative errors grow larger. 76 DS07-13711-5E MB90420G/425G Series (2) Definition of terms • Resolution Indicates the ability of the A/D converter to discriminate in analog conversion. 10-bit resolution indicates that analog voltage can be resolved into 210 = 1024 levels. • Total error Expresses the difference between actual and logical values. It is the total value of errors that can come from offset error, gain error, non-linearity error and noise. • Linearity error Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s zero transition point (00 0000 0000 ←→ 00 0000 0001) and full scale transition point (11 1111 1110 ←→ 11 1111 1111) . • Differential linearity error Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code. • 10-bit A/D converter conversion characteristics 11 11 11 11 1111 1111 1111 1111 1111 1110 1101 1100 . . 1 LSB × N + VOT . . Digital output . . . . . Linearity error . . . . 00 00 00 00 0000 0000 0000 0000 0011 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input 1 LSB = VFST − VOT 1022 Linearity error = Differential linearity error = DS07-13711-5E VNT − (1 LSB × N + VOT) [LSB] 1 LSB V (N + 1) T − VNT − 1 [LSB] 1 LSB 77 MB90420G/425G Series 6. Flash Memory Program and Erase Performances Parameter Remarks 15 s Excludes 00H programming prior erasure 5 ⎯ s Excludes 00H programming prior erasure ⎯ 16 3,600 µs Excludes system-level overhead ⎯ 10,000 ⎯ ⎯ cycle Average TA = + 85 °C 10 ⎯ ⎯ year * Sector erase time Chip erase time Word (16 bit width) programming time Erase/Program cycle Flash data retention time Value Unit Conditions TA = + 25 °C VCC = 5.0 V Min Typ Max ⎯ 1 ⎯ * : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) 78 DS07-13711-5E MB90420G/425G Series ■ EXAMPLE CHARACTERISTICS ICC − VCC (TA = + 25 °C) 40 35 FC = 16 MHz 30 ICC (mA) 25 FC = 11 MHz 20 FC = 8 MHz 15 FC = 5 MHz 10 FC = 4 MHz 5 FC = 2 MHz 0 3.5 4.5 5.5 6.5 VCC (V) ICTS − VCC (TA = + 25 °C) FC = 16 MHz 900 800 FC = 11 MHz ICTS (µA) 700 FC = 8 MHz FC = 5 MHz 600 500 FC = 4 MHz FC = 2 MHz 400 300 200 100 0 3.5 4.5 5.5 6.5 VCC (V) ICCL − VCC (FC = 8 kHz) 500 400 ICCL (µA) TA = +25 °C 300 TA = +125 °C TA = −40 °C 200 100 0 3.5 4.5 5.5 6.5 VCC (V) DS07-13711-5E 79 MB90420G/425G Series (Continued) (Continued) ICCLS − VCC (FC = 8 kHz) 70 60 TA = +125 °C ICCLS (µA) 50 40 TA = +25 °C 30 TA = −40 °C 20 10 0 3.5 4.5 5.5 6.5 VCC (V) ICCT − VCC (FC = 8 kHz) 70 60 TA = +125 °C ICCT (µA) 50 40 TA = +25 °C 30 TA = −40 °C 20 10 0 3.5 4.5 5.5 6.5 VCC (V) 80 DS07-13711-5E MB90420G/425G Series ■ ORDERING INFORMATION Part number Package MB90F423GAPF MB90F423GCPF MB90F428GAPF MB90F428GCPF MB90423GAPF MB90423GCPF MB90427GAPF MB90427GCPF MB90428GAPF MB90428GCPF Plastic QFP, 100-pin (FPT-100P-M06) MB90F423GAPMC MB90F423GCPMC MB90F428GAPMC MB90F428GCPMC MB90423GAPMC MB90423GCPMC MB90427GAPMC MB90427GCPMC MB90428GAPMC MB90428GCPMC Plastic LQFP, 100-pin (FPT-100P-M20) DS07-13711-5E Remarks 81 MB90420G/425G Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 31 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" ©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6 C 2002 FUJITSU LIMITED F100008S-c-5-5 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 82 DS07-13711-5E MB90420G/425G Series (Continued) 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.65 g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M20) 100-pin plastic LQFP (FPT-100P-M20) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 26 100 1 0.08(.003) (0.50(.020)) 0.25(.010) 0.60±0.15 (.024±.006) 25 0.20±0.05 (.008±.002) 0.10±0.10 (.004±.004) (Stand off) 0˚~8˚ "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX M 0.145±0.055 (.0057±.0022) ©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2 C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-13711-5E 83 MB90420G/425G Series ■ MAIN CHANGES IN THIS EDITION Page 5 81 83 Section Change Results The package code is changed. (FPT-100P-M05 → FPT-100P-M20) ■ PIN ASSIGNMENTS Figure of QFP package pin assignment is changed. Order informations are changed. (MB90423GAPFV → MB90423GAPMC, MB90423GCPFV → MB90423GCPMC, MB90427GAPFV → MB90427GAPMC, MB90427GCPFV → MB90427GCPMC, ■ ORDERING INFORMATION MB90428GAPFV → MB90428GAPMC, MB90428GCPFV → MB90428GCPMC, MB90F423GAPFV→ MB90F423GAPMC, MB90F423GCPFV→ MB90F423GCPMC, MB90F428GAPFV→ MB90F428GAPMC, MB90F428GCPFV→ MB90F428GCPMC) The package figure is changed. ■ PACKAGE DIMENSIONS (FPT-100P-M05 → FPT-100P-M20) The vertical lines marked in the left side of the page show the changes. 84 DS07-13711-5E MB90420G/425G Series MEMO DS07-13711-5E 85 MB90420G/425G Series MEMO 86 DS07-13711-5E MB90420G/425G Series MEMO DS07-13711-5E 87 MB90420G/425G Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. 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