FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13501-6E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90210 Series
MB90214/P214A/P214B/W214A/W214B/V210
■ OUTLINE
The MB90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras,
VTRs, and copiers. The F2MC-16F CPU integrated in this series is based on the F2MC*-16, while providing
enhanced instructions for high-level languages and supporting extended addressing modes.
The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels, a 10bit A/D converter with 8 channels, UART serial ports with 3 channels (1 channel for CTS and 1 channel for dual
input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit PPG timer with 1 channel.
MB90P214B/W214B is under development.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ PACKAGE
80-pin Plastic QFP
80-pin Ceramic QFP
(FPT-80P-M06)
(FPT-80C-C02)
MB90210 Series
■ FEATURES
F2MC-16F CPU
• Minimum execution time: 62.5 ns/16-MHz oscillation (using a duty control system)
• Instruction sets optimized for controllers
Upward object-compatible with the F2MC-16(H)
Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator
• Extended intelligent I/O service (Automatic transfer function independent of instructions) access area
expanded to 64 Kbytes
• Enhanced instruction set applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function
• Increased execution speed: 8-byte instruction queue
• Powerful interrupt functions: 8 levels and 29 sources
Integrated Peripheral Resources
• ROM
: 64 Kbytes (MB90214)
EPROM : 64 Kbytes (MB90W214A/W214B)
OTPROM: 64Kbytes (MB90P214A/P214B)
• RAM: 3 Kbytes (MB90214)
4 Kbytes (MB90P214A/P214B/W214A/W214B/V210)
• General-purpose ports: max. 65 channels
• PWC timer with time measurement function: 4 channels
• 10-bit A/D converter: 8 channels
• UART: 3 channels
• Including: 1 channel with CTS function
1 channel with I/O pin switching function
• 16-bit reload timer
Toggled output, external clock, and gate functions: 4 channels
External clock and gate functions: 4 channels
• 8-bit PPG timer: 1 channel
• DTP/External-interrupt inputs: 4 channels
• Write-inhibit RAM: 256 bytes (MB90V210: 512 bytes)
• Timebase counter: 18 bits
• Clock gear function
• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode
2
MB90210 Series
Product Description
• MB90214 is a mask ROM product.
• MB90P214A/P214B are OTPROM products.
• MB90W214A/W214B are EPROM products. ES only.
• Operating temperature of MB90P214A/W214A is –40°C to +85°C. (However, the AC characteristics is assured
in –40°C to +70°C)
• MB90V210 is a evaluation device for the program development. ES only.
3
MB90210 Series
■ PRODUCT LINEUP
Part number
MB90P214A
MB90P214B
MB90214
Item
Classification
OTPROM product
EPROM product
MB90V210
For evaluation
ROM size
64 Kbytes
64 Kbytes
64 Kbytes
—
RAM size
3 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
CPU functions
The number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
412
8 or 16 bits
1 to 7 bytes
1, 4, 8, 16, or 32 bits
62.5 ns/16 MHz
1.0 µs/16 MHz (min.)
Ports
I/O ports (N-ch open-drain):
I/O ports (CMOS):
Total:
8
57
65
PWC timer
10-bit
A/D converter
Number of channels: 4
16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.31 ms)
16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width
measurement, inter-edge measurement, and divided-frequency measurement)
Resolution: 10 or 8 bits, Number of inputs: 8
Single conversion mode (conversion for each input channel)
Scan conversion mode (continuous conversion for up to 8 consecutive channels)
Continuous conversion mode (repeated conversion for a selected channel)
Stop conversion mode (conversion every fixed cycle)
UART
Number of channels: 3
(1 channel with CTS function; 1 channel with I/O pin switching function)
Clock-synchronous transfer mode
(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)
Asynchronous transfer mode
(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)
Timer
Number of channels: 4 channels × 2 types
16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.05 s)
8-bit PPG timer
DTP/External
interrupt
Write-inhibit RAM
Number of channels: 1
8-bit PPG operation (operating clock cycle: 0.25 µs to 6 s)
Number of inputs: 4
External interrupt mode (allowing interrupts to activate at four different request levels)
Simple DMA start mode (allowing extended I2OS to activate at two different request levels)
RAM size: 256 bytes (MB90V210: 512 bytes)
RAM write-protectable with WI pin
Standby mode
Stop mode (activated by software or hardware) and sleep mode
Gear function
Machine clock operating frequency switching: 16, 8, 4, or 1 MHz (at 16 MHz oscillation)
Package
4
Mask ROM product
MB90W214A
MB90W214B
FPT-80P-M06
FPT-80C-C02
PGA-256C-A02
MB90210 Series
■ DIFFERENCES BETWEEN MB90214 (MASK ROM PRODUCT) AND MB90P214A/P214B/
W214A/W214B
Part number
MB90214
MB90P214A
MB90P214B
MB90W214A
MB90W214B
Mask ROM
64 Kbytes
OTPROM
64 Kbytes
EPROM
64 Kbytes
Item
ROM
Pin function
43 pins
MD2 pin
MD2/VPP pin
Note: MB90V210, device used for evaluation, is not warranted for electrical specifications.
5
P16D14
P17D15
P20A00/TIN0
P21/A01/TIN1
P22/A02/TIN2
P23/A03/TIN3
P24/A04/TIN4
P25/A05/TIN5
P26/A06/TIN6
P27/A07/TIN7
VSS
P30/A08
P31/A09/PPG
P32/A10/TOUT0
P33/A11/TOUT1
P34/A12/TOUT2
P35/A13/TOUT3
P36/A14/SCK3
P37/A15/S I D3
P40/A16/SOD3
P41/A17/SCK2
P42/A18/S I D2
P43/A19/SOD2
P44/A20/PWC0/POUT0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
X0
VSS
RST
P57/WI
P56/RD
P55/WRL
P54/WRH/CTS0/INT3
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
P82/INT2/ATG
P81/INT1
P80/INT0
P75/SOD0
P74/SID0
P73/SCK0
P72/SOD1
P71/SID1
P70/SCK1
HST
MD2
MD1
MD0
MB90210 Series
■ PIN ASSIGNMENT
(Top view)
X1
VCC
P00/D00
P01/D01
P02/D02
P03/D03
P04/D04
P05/D05
P06/D06
P07/D07
P10/D08
P11/D09
P12/D10
P13/D11
P14/D12
P15/D13
6
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(FPT-80P-M06)
(FPT-80C-C02)
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
VSS
P61/AN1
P60/AN0
AVSS
AVRL
AVRH
AVCC
PWC3/P47/A23/POUT3
PWC2/P46/A22/POUT2
PWC1/P45/A21/POUT1
MB90210 Series
■ PIN DESCRIPTION
Pin no.
Pin name
QFP*
64,
65
X0,
X1
62
Circuit
type
Function
A
Crystal oscillator pins (16 MHz)
RST
H
External reset request input pin
66
VCC
Power supply
Digital circuit power supply pin
11,
34,
63
VSS
Power supply
Digital circuit grounding level
67 to 74
P00 to P07
B
D00 to D07
75 to 80,
1,
2
P10 to P15,
P16,
P17
I/O pins for the lower eight bits of external data bus
These pins are available in an external-bus mode.
B
D08 to D13,
D14,
D15
3 to 6
7 to 10
12
P20 to P23
General-purpose I/O ports
These ports are available only in the single-chip mode.
General-purpose I/O ports
These ports are available in the single-chip mode and in an
external-bus mode with the 8-bit data bus specified.
I/O pins for the upper eight bits of external data bus
These pins are available in an external-bus mode with the 16-bit
data bus specified.
E
General-purpose I/O ports
These ports are available only in the single-chip mode.
A00 to A03
Output pins for external address buses A00 to A03
These pins are available in an external-bus mode.
TIN0 to TIN3
16-bit reload timer 1 (ch.0 to ch.3) input pins
These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) input specification is “enabled”. The data on the pin is read
as the 16-bit reload timer 1 (ch.0 to ch.3) input (TIN0 to TIN3).
P24 to P27
E
General-purpose I/O ports
These ports are available only in the single-chip mode.
A04 to A07
Output pins for external address buses A04 to A07
These pins are available in an external-bus mode.
TIN4 to TIN7
16-bit reload timer 2 (ch.4 to ch.7) input pins
These pins are available when the 16-bit reload timer 2 (ch.4 to
ch.7) input specification is “enabled”. The data on the pin is read
as the 16-bit reload timer 2 (ch.4 to ch.7) input (TIN4 to TIN7).
P30
A08
* : FPT-80P-M06, FPT-80C-C02
E
General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is “port.”
Output pin for external address bus A08
This pin is available in an external-bus mode and when the middle
address control register set to “address.”
(Continued)
7
MB90210 Series
Pin no.
QFP*
13
14 to 17
18
19
Pin name
P31
Function
E
General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is “port”, with the 8-bit PPG
output is disabled.
A09
Output pin for external address bus A09
This pin is available in an external-bus mode and when the middle
address control register setting is “address.”
PPG
PPG timer output pin
This pin is available when the PPG operation mode control
register specification is the PPG output pin.
P32 to P35
E
General-purpose I/O ports
These ports are available in the single-chip mode or when the
middle address control register setting is “port”, with the 16-bit
reload timer 1 (ch.0 to ch.3) output is disabled.
A10 to A13
Output pins for external address buses A10 to A13
These pins are available in an external-bus mode and when the
middle address control register setting is “address.”
TOUT0 to TOUT3
16-bit reload timer 1 (ch.0 to ch.3) output pin
These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) is output operation.
P36
E
General-purpose I/O port
This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the middle
address control register setting is “port.”
A14
Output pin for external address bus A14
This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the middle address
control register setting is “address.”
SCK3
UART (ch.2) clock output pin (SCK3)
This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK3)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.
P37
E
General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is “port.”
A15
Output pin for external address bus A15
This pin is available in an external-bus mode and when middle
address control register setting is “address.”
SID3
UART (ch.2) serial data input pin (SID3)
Since this input is used whenever the SID3 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.
* : FPT-80P-M06, FPT-80C-C02
8
Circuit
type
(Continued)
MB90210 Series
Pin no.
QFP*
20
21
22
23
Pin name
P40
Circuit
type
Function
E
General-purpose I/O port
This port is available when the UART (ch.2) serial data output
from SOD3 is disabled either in the single-chip mode or when the
upper address control register setting is “port.”
A16
Output pin for external address bus A16
This pin is available when the UART (ch.2) serial data output
from SOD3 is disabled in an external-bus mode and when the
upper address control register setting is “address.”
SOD3
UART (ch.2) serial data output pin (SOD3)
This pin is available when the UART (ch.2) serial data output is
enabled.
P41
E
General-purpose I/O port
This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the upper
address control register setting is “port.”
A17
Output pin for external address bus A17
This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the upper address
control register setting is “address.”
SCK2
UART (ch.2) clock output pin (SCK2)
This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK2)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.
P42
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A18
Output pin for external address bus A18
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
SID2
UART (ch.2) serial data input pin (SID2)
Since this input is used whenever the SID2 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.
P43
E
General-purpose I/O port
This port is available when the UART (ch.2) serial data output
from SOD2 is disabled either in the single-chip mode or when the
upper address control register setting is “port.”
A19
Output pin for external address bus A19
This pin is available when the UART (ch.2) serial data output
from SOD2 is disabled in an external-bus mode and when the
upper address control register setting is “address.”
SOD2
UART (ch.2) serial data output pin (SOD2)
This pin is available when the UART (ch.2) serial data output
from SOD2 is enabled.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
9
MB90210 Series
Pin no.
QFP*
24
Pin name
PWC0
Circuit
type
E
POUT0
25
26
27
P45
PWC timer input pin
Since this input is used whenever the PWC0 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
PWC timer output pin
This pin is available when the PWC0 is output operation.
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A21
Output pin for external address bus A21
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
PWC1
PWC timer data sample input pin
Since this input is used whenever the PWC1 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT1
PWC timer output pin
This pin is available when the PWC1 is output operation.
P46
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A22
Output pin for external address bus A22
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
PWC2
PWC timer input pin
Since this input is used whenever the PWC2 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT2
PWC timer output pin
This pin is available when the PWC2 is output operation.
P47
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A23
Output pin for external address bus A23
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
PWC3
PWC timer input pin
Since this input is used whenever the PWC3 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT3
PWC timer output pin
This pin is available when the PWC3 is output operation.
* : FPT-80P-M06, FPT-80C-C02
10
Function
(Continued)
MB90210 Series
Pin no.
QFP*
54
Pin name
P50
Circuit
type
Function
E
General-purpose I/O port
This port is available in the single-chip mode and when the CLK
output is disabled.
CLK
55
P51
CLK output pin
This pin is available in an external-bus mode with the CLK output
enabled.
E
RDY
56
P52
Ready signal input pin
This pin is available in an external-bus mode and when the ready
function is enabled.
E
HAK
57
P53
P54
General-purpose I/O port
This port is available in the single-chip mode or when the hold
function is disabled.
Hold acknowledge output pin
This pin is available in an external-bus mode and when the hold
function is enabled.
E
HRQ
58
General-purpose I/O port
This port is available in the single-chip mode or when the ready
function is disable.
General-purpose I/O port
This port is available in the single-chip mode or when the hold
function is disabled in an external-bus mode.
Hold request input pin
This pin is available in an external-bus mode and when the hold
function is enabled.
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.
D
General-purpose I/O port
This port is available in the single-chip mode, in the external bus
8-bit mode, or when the WRH pin output is disabled.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
CTS0
UART (ch.0) clear-to-send input pin
Since this input is used whenever the UART (ch.0) CTS function
is enabled, the output by any other function must be suspended
unless the output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
WRH
Write strobe output pin for the upper eight bits of data bus
This pin is available in the external bus 16-bit mode with the
WRH pin output enabled in an external-bus mode.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
11
MB90210 Series
Pin no.
Pin name
QFP*
Circuit
type
Function
58
INT3
D
External interrupt request input pin
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
59
P55
E
General-purpose I/O port
This port is available in the single-chip mode or when the WRL
pin output is disabled.
WRL
60
P56
Write strobe output pin for the lower eight bits of data bus
This pin is available in an external-bus mode and when the WRL
pin output is enabled.
E
RD
61
P57
Data bus read strobe output pin
This pin is available in an external-bus mode.
D
WI
32,
33,
35 to 40
P60,
P61,
P62 to P67
C
Open-drain I/O ports
These ports are available when the analog input enable register
setting is “port.”
10-bit A/D converter analog input pins
These pins are available when the analog input enable register
setting is “analog input.”
MD0 to MD2
F
Operation mode select signal input pins
Connect these pins directly to VCC or VSS.
44
HST
G
Hardware standby input pin
45
P70
E
General-purpose I/O port
This port is available when the UART (ch.1) clock output is
disabled.
* : FPT-80P-M06, FPT-80C-C02
12
General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
RAM write disable request input
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
AN0,
AN1,
AN2 to AN7
41 to 43
General-purpose I/O port
This port is available in the single-chip mode.
(Continued)
MB90210 Series
Pin no.
QFP*
Pin name
Circuit
type
Function
45
SCK1
E
UART (ch.1) clock output pin
This pin is available when the UART (ch.1) clock output is
enabled.
UART (ch.1) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.1) specification is external clock mode.
46
P71
E
General-purpose I/O port
This port is always available.
SID1
47
P72
UART (ch.1) serial data input pin
Since this input is used whenever the UART (ch.1) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
E
SOD1
48
P73
UART (ch.1) serial data output pin
This pin is available when the UART (ch.1) serial data output is
enabled.
E
SCK0
49
P74
P75
E
P80,
P81
* : FPT-80P-M06, FPT-80C-C02
General-purpose I/O port
This port is always available.
UART (ch.0) serial data input pin
Since this input is used whenever the UART (ch.0) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
E
SOD0
51,
52
General-purpose I/O port
This port is available when the UART (ch.0) clock output is
disabled.
UART (ch.0) clock output pin
This pin is available when the UART (ch.0) clock output is
enabled.
UART (ch.0) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.0) specification is external clock mode.
SID0
50
General-purpose I/O port
This port is available when the UART (ch.1) serial data output is
disabled.
General-purpose I/O port
This port is available when the UART (ch.0) serial data output is
disabled.
UART (ch.0) serial data output pin
This pin is available when the UART (ch.0) serial data output is
enabled.
D
General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
(Continued)
13
MB90210 Series
(Continued)
Pin no.
QFP*
Pin name
Function
51,
52
INT0,
INT1
D
External interrupt request input pin
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
53
P82
D
General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
INT2
External interrupt request input pin
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
ATG
10-bit A/D converter trigger input pin
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
28
AVCC
Power supply
Analog circuit power supply pin
This power supply must be turned on or off with a potential equal
to or higher than AVCC applied to VCC.
Be sure that AVCC= VCC before use and during operation.
29
AVRH
Power supply
Analog circuit reference voltage input pin
This pins must be turned on or off with a potential equal to or
higher than AVRH applied to AVCC.
30
AVRL
Power supply
Analog circuit reference voltage input pin
31
AVSS
Power supply
Analog circuit grounding level
* : FPT-80P-M06, FPT-80C-C02
14
Circuit
type
MB90210 Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• Oscillation feedback resistor: Approx.1 MΩ
MB90214
MB90P214B
MB90W214B
X1
X0
Standby control
• Oscillation feedback resistor: Approx.1 MΩ
MB90P214A
MB90W214A
X1
X0
Standby control
B
R
Digital output
R
Digital output
R
Digital input
• CMOS-level I/O
Standby control provided
MB90214: With or without pull-up/pull-down
reisistor optional
MB90P214A/P214B: Without pull-up/pull-down
resistor
MB90W214A/W214B: Without pull-up/pull-down
resistor
Standby control
C
• N-ch open-drain output
• CMOS-level hysteresis input
A/D control provided
Digital output
R
A/D input
Digital input
D
R
Digital output
R
Digital output
R
Digital input
• CMOS-level output
• CMOS-level hysteresis input
Standby control not provided
MB90214: With or without pull-up/pull-down
reisistor optional
MB90P214A/P214B: Without pull-up/pull-down
resistor
MB90W214A/W214B: Without pull-up/pull-down
resistor
(Continued)
15
MB90210 Series
(Continued)
Type
Circuit
Remarks
E
R
Digital output
R
Digital output
R
Digital input
F
• CMOS-level output
• CMOS-level hysteresis input
Standby control provided
MB90214: With or without pull-up/pull-down
reisistor optional
MB90P214A/P214B: Without pull-up/pull-down
resistor
MB90W214A/W214B: Without pull-up/pull-down
resistor
• CMOS-level input with no standby control
Mask ROM products only:
MD2: With pull-down resistor
MD1: With pull-up resistor
MD0: With pull-down resistor
R
Digital input
• COMS-level input with no standby control
MD2 of OTPROM products/EPROM products
only
R
Digital input
VPP power supply
G
• CMOS-level hysteresis input
Standby control not provided
• With input analog filter (40 ns Typ.)
R
Analog filter
H
Digital input
• CMOS-level hysteresis input
Standby control not provided
• With input analog filter (40 ns Typ.)
• With pull-up resistor
MB90214: With or without pull-up/pull-down
resistor optional
MB90P214A/W214A/P214B/W214B:
With pull-up resistor
Pull-up
resistor
R
R
Analog filter
: P-type transistor
Digital input
: N-type transistor
Note: The pull-up and pull-down resistors are always connected, regardless of the state.
16
MB90210 Series
■ HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup when a voltage higher than VCC or lower than VSS is applied to input or output
pins, or when a voltage exceeding the rating is applied between VCC and VSS.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.
Also, take care to prevent the analog power supply (AVCC and AVRH) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Pins when A/D is not Used
Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.
4. Precautions when Using an External Clock
To reset the internal circuit properly by the Low-level input to the RST pin, the “L” level input to the RST pin
must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
5. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
6. Supply Voltage Variation
The operation assurance range for the VCC supply voltage is as given in the ratings. However, sudden changes
in the supply voltage can cause misoperation, even if the voltage remains within the rated range. Therefore, it
is important to supply a stable voltage to the IC. The recommended power supply control guidelines are that
the commercial frequency (50 to 60 Hz) ripple variation (P-P value) on VCC should be less than 10% of the
standard VCC value and that the transient rate of change during sudden changes, such as during power supply
switching, should be less than 0.1 V/ms.
7. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.
• Use of External Clock
X0
MB90210
X1
Note: When using an external clock, be sure to input external clock more than 6 machine cycles after
setting the HST pin to “L” to transfer to the hardware standby mode.
17
MB90210 Series
8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN7).
When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog
inputs (AN0 to AN7) first, then the digital power supply (VCC).
When turning AVRH on or off, be careful not to let it exceed AVCC.
18
MB90210 Series
■ PROGRAMMING FOR MB90P214A/P214B/W214A/W214B
In EPROM mode, the MB90P214A/P214B/W214A/W214B functions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (64 K × 8 bits) in the MB90P214A/P214B/W214A/
W214B are in the “1” state. Data is written to the ROM by selectively programming “0’s” into the desired bit
locations. Bits cannot be set to “1” electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000.
(2) Load program data into the EPROM programmer at 10000H to 1FFFFH.
Note that ROM addresses FF0000H to FFFFFFH in the operation mode in the MB90P214A/P214B/W214A/
W214B series assign to 10000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
FFFFFFH
1FFFFH*
FF0000H
10000H*
Operation mode
EPROM mode
(Corresponding addresses on the EPROM mode)
* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 10000H/1FFFFH.
(3) Mount the MB90P214A/P214B/W214A/W214B on the adapter socket, then fit the adapter socket onto the
EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting
orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between VCC and GND,
between VPP and GND.
(6) Since the MB90P214A and MB90W214A have CMOS-level input, programming to them may be impossible
depending on the output level of the general-purpose programmer. In that case, connect a pull-up resistor
to the adapter socket side.
Note: The mask ROM products (MB90214) does not support EPROM mode. Data cannot, therefore, be read by
the EPROM programmer.
19
MB90210 Series
3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Part No.
MB90P214B
Package
QFP-80
Compatible socket adapter
Sun Hayato Co., Ltd.
Recommended
programmer
manufacturer
and programmer
name
Advantest corp.
ROM-80QF-32DP-16F
R4945A
(main unit)
+
R49451A
(adapter)
Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Advantest Corp.:
TEL: Except JAPAN (81)-3-3930-4111
4. Erase Procedure
Data written in the MB90W214A/W214B are erased (from “0” to “1”) by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.
Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm2).
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.
Data in the MB90W214A/W214B are erased by exposure to light with a wavelength of 4000 Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537 Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000 Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.
20
MB90210 Series
5. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
6. Programming Yeild
MB90P214A/P214B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
7. Pin Assignment in EPROM Mode
(1) Pins compatible with MBM27C1000
MBM27C1000
MB90P214A, MB90P214B,
MB90W214A, MB90W214B
MBM27C1000
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
1
VPP
43
MD2 (VPP)
32
VCC
2
OE
59
P55
31
PGM
3
A15
19
P37
30
N.C.
4
A12
16
P34
29
5
A07
10
P27
6
A06
9
7
A05
8
MB90P214A, MB90P214B,
MB90W214A, MB90W214B
Pin no.
Pin name
60
P56
A14
18
P36
28
A13
17
P35
P26
27
A08
12
P30
8
P25
26
A09
13
P31
A04
7
P24
25
A11
15
P33
9
A03
6
P23
24
A16
20
P40
10
A02
5
P22
23
A10
14
P32
11
A01
4
P21
22
CE
58
P54
12
A00
3
P20
21
D07
74
P07
13
D00
67
P00
20
D06
73
P06
14
D01
68
P01
19
D05
72
P05
15
D02
69
P02
18
D04
71
P04
16
GND
17
D03
70
P03
21
MB90210 Series
(2) Power supply and ground connection pins
Type
Pin no.
Pin name
Power supply
41
42
44
66
MD0
MD1
HST
VCC
GND
11
30
31
34
56
57
62
63
VSS
AVRL
AVSS
VSS
P52
P53
RST
VSS
(3) Pins other than MBM27C1000-compatible pins
Pin no.
22
Pin name
Treatment
64
X0
Pull up to 4.7 kΩ.
65
X1
Open
1
2
21
to
27
28
29
32
33
35
to
40
45
to
50
51
to
53
54
55
61
75
to
80
P16
P17
P41
to
P47
AVCC
AVRH
P60
P61
P62
to
P67
P70
to
P75
P80
to
P82
P50
P51
P57
P10
to
P15
Connect a pull-up resistor of approximately 1 MΩ to each pin.
MB90210 Series
■ BLOCK DIAGRAM
4
7
Write-inhibit
RAM
WI
CTS0
SCK3
SID3
SOD3
SCK2
SID2
SOD2
SCK1
SID1
SOD1
SCK0
SID0
SOD0
TOUT0 to
TOUT3
TIN0 to
TIN3
PWC
timer
×4
Clock controller
Internal data bus
X1
X0
RST
HST
MD2
MD1
MD0
4
INT0 to INT3
DTP/External
interrupt
×4
13
UART × 3
16-bit
timer 1
×4
8
PWC0 to PWC3
/POUT0 to POUT3
External bus
interface
47
D00 to D15
A00 to A23
CLK
RDY
HAK
HRQ
WRH
WRL
RD
F2MC-16F
CPU
RAM
TIN4 to
TIN7
ATG
AN0 to
AN7
AVCC
AVRH
AVRL
AVSS
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P75
P80 to P82
PPG
4
16-bit
timer 2
×4
ROM
13
10-bit
A/D converter
8 ch.
65
8-bit
I/Otimer
port
PPG
8-bit
PPG timer
23
MB90210 Series
■ PROGRAMMING MODEL
Dedicated Registers
AL
AH
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
USPCU
User stack upper register
SSPCU
System stack upper register
USPCL
User stack lower register
SSPCL
System stack lower register
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
General-purpose Registers
Max.32 banks
Upper
R7
R6
RW 7
R5
R4
RW 6
R3
R2
RW 5
R1
R0
RW 4
RL 3
RL 2
RW3
RL 1
RW 2
Lower
RW 1
RL 0
RW 0
000180H + RP × 10H
16 bits
MSB
Processor Status (PS)
ILM
RP
LSB
—
I
S
T
N
CCR
24
Z
V
C
MB90210 Series
■ MEMORY MAP
Single chip
Internal ROM
and external bus
ROM area
ROM area
ROM area
ROM area
FF bank
image
FF bank
image
Write-inhibit RAM
Write-inhibit RAM
External ROM
and external bus
FFFFFFH
Address #1
010000H
Address #2
Address #3
Address #4
Write-inhibit RAM
Address #5
Address #6
: Internal
000380H
RAM
Registers
RAM
Registers
RAM
Registers
000180H
: External
000100H
0000C0H
Peripherals
Peripherals
Peripherals
: No access
000000H
Type
Address #1
Address #2
Address #3
Address #4
Address #5
Address #6
MB90214
FF0000H
004000H
001300H
001200H
001100H
000D00H
MB90P214A/P214B
MB90W214A/W214B
FF0000H
004000H
001300H
001200H
001100H
001100H
(FE0000H)
004000H
001300H
001300H
001100H
001100H
MB90V210
25
MB90210 Series
■ I/O MAP
Register
name
Access
000000H *3 Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
000001H *3 Port 1 data register
PDR1
R/W
Port 1
XXXXXXXX
000002H *3 Port 2 data register
PDR2
R/W
Port 2
XXXXXXXX
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXX
000004H *3 Port 4 data register
PDR4
R/W
Port 4
XXXXXXXX
000005H *3 Port 5 data register
PDR5
R/W
Port 5
XXXXXXXX
000006H
Port 6 data register
PDR6
R/W
Port 6
11111111
000007H
Port 7 data register
PDR7
R/W
Port 7
– – XXXXXX
000008H
Port 8 data register
PDR8
R/W
Port 8
––– –– XX X
Address
000003H *
Register
3
000009H
to 0FH
Resource
name
Initial value
(Reserved area) *1
000010H *3 Port 0 data direction register
DDR0
R/W
Port 0
00000000
Port1 data direction register
DDR1
R/W
Port 1
00000000
000012H *3 Port 2 data direction register
DDR2
R/W
Port 2
00000000
000013H *3 Port 3 data direction register
DDR3
R/W
Port 3
00000000
Port 4 data direction register
DDR4
R/W
Port 4
00000000
000015H *3 Port 5 data direction register
DDR5
R/W
Port 5
00000000
000016H
Analog input enable register
ADER
R/W
Port 6
11111111
000017H
Port 7 data direction register
DDR7
R/W
Port 7
– – 0 00 00 0
000018H
Port 8 data direction register
DDR8
R/W
Port 8
– – – – – 0 00
UART (ch.0)
00000100
000011H *
000014H *
3
3
000019H
to 1FH
(Reserved area) *1
000020H
Mode control register 0
UMC0
R/W
000021H
Status register 0
USR0
R/W
000022H
Input data register 0/output data
register 0
UIDR0/
UODR0
R/W
000023H
Rate and data register 0
URD0
R/W
000024H
Mode control register 1
UMC1
R/W
000025H
Status register 1
USR1
R/W
000026H
Input data register 1/output data
register 1
UIDR1/
UODR1
R/W
000027H
Rate and data register 1
URD1
R/W
00010000
XXXXXXXX
00000000
UART (ch.1)
00000100
00010000
XXXXXXXX
00000000
(Continued)
26
MB90210 Series
Address
Register
Register
name
Access
Resource
name
Initial value
000028H
Mode control register 2
UMC2
R/W
000029H
Status register 2
USR2
R/W
00010000
00002AH
Input data register 2/output data
register 2
UIDR2/
UODR2
R/W
XXXXXXXX
00002BH
Rate and data register 2
URD2
R/W
00000000
00002CH
UART redirect control register
URDR
R/W
00002DH
to 2FH
00000100
UART (ch.0/2)
– – – 0 0000
DTP/external
interrupt
– – – – 0000
(Reserved area) *1
000030H
Interrupt/DTP enable register
ENIR
R/W
000031H
Interrupt/DTP factor register
EIRR
R/W
000032H
Request level setting register
ELVR
R/W
000033H
000034H
UART (ch.2)
– – – – 0000
00000000
(Reserved area) *1
AD control status register
ADCS
R/W
000035H
000036H
to 37H
AD data register
000038H
to 39H
10-bit A/D
converter
00000000
00000000
ADCD
R/W
*4
Timer control status register 0
TMCSR0
R/W
16-bit reload
timer 1 (ch.0)
00000000
– – – – 0 0 00
00003AH
to 3BH
Timer control status register 1
TMCSR1
R/W
16-bit reload
timer 1 (ch.1)
00000000
– – – – 0 0 00
00003CH
to 3DH
Timer control status register 2
TMCSR2
R/W
16-bit reload
timer 1 (ch.2)
00000000
– – – – 0 0 00
00003EH
to 3FH
Timer control status register 3
TMCSR3
R/W
16-bit reload
timer 1 (ch.3)
00000000
– – – – 0 0 00
000040H
Timer 0 timer register
TMR0
R
16-bit reload
timer 1 (ch.0)
XXXXXXXX
000041H
000042H
Timer 0 reload register
TMRLR0
XXXXXXXX
0 – – – – – XX
W
XXXXXXXX
XXXXXXXX
000043H
000044H
Timer 1 timer register
TMR1
R
000045H
000046H
000047H
XXXXXXXX
Timer 1 reload register
TMRLR1
W
16-bit reload
timer 1 (ch.1)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
27
MB90210 Series
Address
000048H
Register
Timer 2 timer register
Register
name
Access
TMR2
R
000049H
00004AH
Timer 2 reload register
TMRLR2
Resource
name
Initial value
16-bit reload
timer 1 (ch.2)
XXXXXXXX
W
XXXXXXXX
00004BH
00004CH
XXXXXXXX
Timer 3 timer register
TMR3
R
00004DH
00004EH
Timer 3 reload register
TMRLR3
16-bit reload
timer 1 (ch.3)
W
Timer 4 timer register
TMR4
R
Timer 4 reload register
TMRLR4
16-bit reload
timer 2 (ch.4)
W
Timer 5 timer register
TMR5
R
Timer 5 reload register
TMRLR5
16-bit reload
timer 2 (ch.5)
W
Timer 6 timer register
TMR6
R
Timer 6 reload register
TMRLR6
16-bit reload
timer 2 (ch.6)
W
Timer 7 timer register
TMR7
R
Timer 7 reload register
TMRLR7
16-bit reload
timer 2 (ch.7)
W
Timer control status register 4
000065H
TMCSR4
R/W
16-bit reload
timer 2 (ch.4)
00000000
16-bit reload
timer 2 (ch.5)
00000000
16-bit reload
timer 2 (ch.6)
00000000
(Reserved area) *1
Timer control status register 5
TMCSR5
R/W
(Reserved area) *1
000063H
000064H
XXXXXXXX
XXXXXXXX
000061H
000062H
XXXXXXXX
XXXXXXXX
00005FH
000060H
XXXXXXXX
XXXXXXXX
00005DH
00005EH
XXXXXXXX
XXXXXXXX
00005BH
00005CH
XXXXXXXX
XXXXXXXX
000059H
00005AH
XXXXXXXX
XXXXXXXX
000057H
000058H
XXXXXXXX
XXXXXXXX
000055H
000056H
XXXXXXXX
XXXXXXXX
000053H
000054H
XXXXXXXX
XXXXXXXX
000051H
000052H
XXXXXXXX
XXXXXXXX
00004FH
000050H
XXXXXXXX
Timer control status register 6
TMCSR6
R/W
(Reserved area) *1
(Continued)
28
MB90210 Series
Address
000066H
Register
Timer control status register 7
PWC0 divide ratio register
PWC1 divide ratio register
00006BH
00006CH
PWC2 divide ratio register
DIVR0
R/W
DIVR1
R/W
DIVR2
R/W
PWC3 divide ratio register
DIVR3
R/W
00000000
PWC timer
(ch.0)
––––––00
PWC timer
(ch.1)
––––––00
PWC timer
(ch.2)
––––––00
PWC timer
(ch.3)
––––––00
(Reserved area) *1
PWC0 control status register
PWCSR0
R/W
000071H
000072H
16-bit reload
timer 2 (ch.7)
(Reserved area) *1
00006FH
000070H
R/W
Initial value
(Reserved area) *1
00006DH
00006EH
TMCSR7
Resource
name
(Reserved area) *1
000069H
00006AH
Access
(Reserved area) *1
000067H
000068H
Register
name
PWC0 data buffer register
PWCR0
PWC timer
(ch.0)
R/W
00000000
PWC1 control status register
PWCSR1
R/W
000075H
000076H
PWC1 data buffer register
PWCR1
PWC timer
(ch.1)
R/W
PWC2 control status register
PWCSR2
R/W
PWC2 data buffer register
PWCR2
PWC timer
(ch.2)
R/W
PWC3 control status register
PWCSR3
R/W
PWC3 data buffer register
PWCR3
PWC timer
(ch.3)
R/W
00000000
00000000
000080H
to 87H
000089H
00000000
00000000
00007FH
000088H
00000000
00000000
00007DH
00007EH
00000000
00000000
00007BH
00007CH
00000000
00000000
000079H
00007AH
00000000
00000000
000077H
000078H
00000000
00000000
000073H
000074H
00000000
(Reserved area) *1
PPG operation mode control register
PPGC
R/W
8-bit PPG timer
00000––1
(Reserved area) *1
(Continued)
29
MB90210 Series
Address
00008AH
Register
PPG reload register
Register
name
Access
Resource
name
Initial value
PRL
R/W
8-bit PPG timer
XXXXXXXX
00008BH
XXXXXXXX
00008CH
to 8DH
00008EH
(Reserved area) *1
WI control register
00008FH
to 9EH
00009FH
WICR
R/W
Write-inhibit RAM
–– – X –– – –
(Reserved area) *1
Delayed interrupt source generate/
release register
Standby control register
DIRR
R/W
Delayed interrupt
generation module
–––––––0
STBYC
R/W
Low-power
consumption
mode
0001∗∗∗∗
External pin
########
0000A0H
0000A1H
to A2H
(Reserved area) *1
0000A3H
Middle address control register
MACR
W
0000A4H
Upper address control register
HACR
W
########
0000A5H
External pin control register
EPCR
W
##0–0#00
0000A6H
to A7H
(Reserved area) *1
0000A8H
Watchdog timer control register
WTC
R/W
Watchdog timer
XXXXXXXX
0000A9H
Timebase timer control register
TBTC
R/W
Timebase timer
1 – –0 0 00 0
Interrupt
controller
0 0 00 0 11 1
0000AAH
to AFH
(Reserved area) *1
0000B0H
Interrupt control register 00
ICR00
R/W
0000B1H
Interrupt control register 01
ICR01
R/W
0000B2H
Interrupt control register 02
ICR02
R/W
0 0 00 0 11 1
0000B3H
Interrupt control register 03
ICR03
R/W
0 0 00 0 11 1
0000B4H
Interrupt control register 04
ICR04
R/W
0 0 00 0 11 1
0000B5H
Interrupt control register 05
ICR05
R/W
0 0 00 0 11 1
0000B6H
Interrupt control register 06
ICR06
R/W
0 0 00 0 11 1
0000B7H
Interrupt control register 07
ICR07
R/W
0 0 00 0 11 1
0000B8H
Interrupt control register 08
ICR08
R/W
0 0 00 0 11 1
0000B9H
Interrupt control register 09
ICR09
R/W
0 0 00 0 11 1
0 0 00 0 11 1
(Continued)
30
MB90210 Series
(Continued)
Address
Register
Register
name
Access
Resource
name
0000BAH
Interrupt control register 10
ICR10
R/W
0000BBH
Interrupt control register 11
ICR11
R/W
0000BCH
Interrupt control register 12
ICR12
R/W
0 0 00 0 11 1
0000BDH
Interrupt control register 13
ICR13
R/W
0 0 00 0 11 1
0000BEH
Interrupt control register 14
ICR14
R/W
0 0 00 0 11 1
0000BFH
Interrupt control register 15
ICR15
R/W
0 0 00 0 11 1
0000C0H
to FFH
Interrupt
controller
Initial value
0 0 00 0 11 1
0 0 00 0 11 1
(External area) *2
Initial value
0: The initial value of this bit is 0.
1: The initial value of this bit is 1.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
∗ : The initial value of this bit varies with the reset source.
#: The initial value of this bit varies with the operation mode.
*1: Access inhibited
*2: The only area available for the external access below address 0000FFH is this area. Accesses to these addresses
are handled as accesses to an external I/O area.
*3: When the external bus is enabled, do not access any register not serving as a general-purpose port in the areas
from address 000000H to 000005H and from 000010H to 000015H.
*4: Writing to bit 15 is possible. Writing to other bits is used as a test function.
31
MB90210 Series
■ INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT
CONTROL REGISTERS
Interrupt source
EI2OS
support
Interrupt vector
No.
Interrupt control register
Address
ICR
Address
Reset
×
# 08
08H
FFFFDCH
—
—
INT9 instruction
×
# 09
09H
FFFFD8H
—
—
Exceptional
×
# 10
0AH
FFFFD4H
—
—
UART interrupt #0
# 11
0BH
FFFFD0H
ICR00
000B0H
UART interrupt #1
# 12
0CH
FFFFCCH
UART interrupt #2
# 13
0DH
FFFFC8H
ICR01
000B1H
UART interrupt #3
# 14
0EH
FFFFC4H
PWC timer # 0 · count completed
# 15
0FH
FFFFC0H
ICR02
000B2H
PWC timer # 0 · overflow
# 16
10H
FFFFBCH
PWC timer # 1 · count completed
# 17
11H
FFFFB8H
ICR03
000B3H
PWC timer # 1 · overflow
# 18
12H
FFFFB4H
PWC timer # 2 · count completed
# 19
13H
FFFFB0H
ICR04
000B4H
PWC timer # 2 · overflow
# 20
14H
FFFFACH
PWC timer # 3 · count completed
# 21
15H
FFFFA8H
ICR05
000B5H
PWC timer # 3 · overflow
# 22
16H
FFFFA4H
16-bit reload timer 1 # 0 overflow
# 23
17H
FFFFA0H
ICR06
000B6H
16-bit reload timer 1 # 1 overflow
# 24
18H
FFFF9CH
16-bit reload timer 1 # 2 overflow
# 25
19H
FFFF98H
ICR07
000B7H
16-bit reload timer 1 # 3 overflow
# 26
1AH
FFFF94H
16-bit reload timer 2 # 4 overflow
# 27
1BH
FFFF90H
ICR08
000B8H
16-bit reload timer 2 # 5 overflow
# 28
1CH
FFFF8CH
16-bit reload timer 2 # 6 overflow
# 29
1DH
FFFF88H
ICR09
000B9H
16-bit reload timer 2 # 7 overflow
# 30
1EH
FFFF84H
A/D converter count completed
# 31
1FH
FFFF80H
ICR10
000BAH
Timebase timer interval interrupt
# 32
20H
FFFF7CH
UART2 · transmission completed
# 33
21H
FFFF78H
ICR11
000BBH
UART2 · reception completed
# 34
22H
FFFF74H
(Continued)
32
MB90210 Series
(Continued)
Interrupt source
EI2OS
support
Interrupt vector
No.
Address
Interrupt control register
ICR
Address
ICR12
0000BCH
UART1 · transmission completed
# 35
23H
FFFF70H
UART1 · reception completed
# 36
24H
FFFF6CH
UART0 · transmission completed
# 37
25H
FFFF68H
ICR13
0000BDH
UART0 · reception completed
# 39
27H
FFFF60H
ICR14
0000BEH
Delayed interrupt generation module
×
# 42
2AH
FFFF54H
ICR15
0000BFH
Stack fault
×
# 255
FFH
FFFC00H
—
—
: EI2OS is supported (with stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (with stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (with no stop request).
× : EI2OS is not supported.
33
MB90210 Series
■ PERIPHERAL RESOURCES
1. Parallel Ports
The MB90210 series has 57 I/O pins and 8 open-drain I/O pins.
Ports 0 to 5, 7, and 8 are I/O ports. Each of these ports serves as an input port when the data direction register
value is 0 and as an output port when the value is 1.
Port 6 is an open-drain port, which may be used as a port when the analog input enable register value is 0.
(1) Register Configuration
• Port data registers 0 to 8 (PDR0 to PDR8)
Port data register
Address: PDR1
PDR3
PDR5
PDR7
000001 H
000003H
000005H
000007H
Bit
15
PDx7
Read/write → (R/W)
Initial value → (X)
Port data register
Address: PDR0
PDR2
PDR4
PDR6
PDR8
Read/write →
Initial value →
13
12
11
10
9
8
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
Bit
000000 H
000002H
000004H
000006H
000008H
14
2
1
0
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
(R/W)
(X)
(1)
(R/W)
(X)
(1)
(R/W)
(X)
(1)
(R/W)
(X)
(1)
(R/W)
(X)
(1)
(R/W)
(X)
(1)
(R/W)
(X)
(1)
(R/W)
(X)
(1) ← Only for the PDR6
PDRx
Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.
• Port direction registers 0 to 5, 7, and 8 (DDR0 to DDR5, DDR7, and DDR8)
Port direction register
Address: DDR1
DDR3
DDR5
DDR7
000011 H
000013H
000015H
000017H
Bit
15
DDx7
Read/write → (R/W)
Initial value → (0)
Port direction register
Address: DDR0
DDR2
DDR4
DDR8
Bit
000010 H
000012H
000014H
000018H
Read/write →
Initial value →
14
13
12
11
10
8
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
( 0)
7
6
5
4
3
2
1
0
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.
Port 6 has no DDR.
34
9
DDRx
MB90210 Series
• Analog input enable register (ADER)
Analog input enable register
Bit
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
Address: ADER 000016 H
Read/write →
Initial value →
ADER
(2) Block Diagram
• I/O port (Port 0 to 5, 7, and 8)
Internal data bus
Port data register read
Port data register
Pin
Port data register write
Port direction register
Port direction register write
Port direction register read
• I/O port with an open-drain output (Port 6)
RMW
(Read-modify-write instruction)
Internal data bus
Port data register read
Pin
Port data register
Port data register write
Analog input enable register
Analog input enable register write
Analog input enable register read
35
MB90210 Series
2. 16-bit Reload Timer 1 (with Event Count Function)
The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output
pin (TOUT), and a control register. The input clock can be selected from among three internal clocks and one
external clock. At the output pin (TOUT), the pulses in the toggled output waveform are output in the reload
mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin
(TIN) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock
mode.
MB90210 series contains four channels for this timer.
(1) Register Configuration
• Timer control status register (TMCSR)
Timer control status register (Upper byte)
Address: ch.0
ch.1
ch.2
ch.3
Bit
15
14
13
12
11
10
9
8
000039H
00003BH
00003DH
00003FH
—
—
—
—
CSL1
CSL0
MOD2
MOD1
Read/write →
Initial value →
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
Timer control status register (Lower byte) Bit
Address: ch.0 000038 H
ch.1 00003AH
ch.2 00003CH
ch.3 00003EH
Read/write →
Initial value →
2
1
0
MDO0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
TMCSRx
• Timer register (TMR)
Timer register (Upper byte)
Address: ch.0
ch.1
ch.2
ch.3
Bit
15
Read/write →
Initial value →
(R)
(X)
Timer register (Lower byte)
Address: ch.0
ch.1
ch.2
ch.3
36
14
13
12
11
10
9
8
000041H
000045H
000049H
00004DH
Bit
000040H
000044H
000048H
00004CH
Read/write →
Initial value →
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
7
6
5
4
3
2
1
0
TMRx
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
MB90210 Series
• Reload register (TMRLR)
Reload register (Upper byte)
Address: ch.0
ch.1
ch.2
ch.3
Bit
15
Read/write →
Initial value →
(W)
(X)
Reroal register (Lower byte)
Address: ch.0
ch.1
ch.2
ch.3
14
13
12
11
10
9
8
000043H
000047H
00004BH
00004FH
Bit
000042H
000046H
00004AH
00004EH
Read/write →
Initial value →
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
7
6
5
4
3
2
1
0
TMRLRx
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(2) Block Diagram
16
16-bit reload register
8
Reload
RELD
16-bit down counter
UF
OUTE
Internal data bus
16
OUTL
2
OUT
CTL.
GATE
I NTE
2
UF
IRQ
CSL 1
Clock selector
CNTE
CSL 0
Clear
EI2 OSCLR
TRG
Retrigger
2
IN CTL
Port (TIN)
EXCK
φ
2
1
φ
2
3
φ
2
5
3
MOD 2
MOD 1
Internal clock
Port (TOUT)
Prescaler clear
UART (timer 1 ch.2 output)
A/D (timer 1 ch.3 output)
MOD 0
3
37
MB90210 Series
3. 16-bit Reload Timer 2 (with Gate Mode)
The 16-bit reload timer 2 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), and an
8-bit control register. The input clock can be selected from among four internal clocks.
The MB90210 series contains four channels for this timer.
(1) Register Configuration
• Timer control status register (TMCSR)
Timer control status register
Address: ch.4
ch.5
ch.6
ch.7
Bit
7
6
5
4
3
2
1
0
000060 H
000062H
000064H
000066H
CSL1
CSL0
GATE
GATL
RELD
INTE
UF
STRT
Read/write →
Initial value →
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
TMCSRx
• Timer register (TMR)
Timer register (Upper byte)
Address: ch.4
ch.5
ch.6
ch.7
Bit
Read/write →
Initial value →
Timer register (Lower byte)
Address: ch.4
ch.5
ch.6
ch.7
15
14
13
12
11
10
9
8
000051H
000055H
000059H
00005DH
(R)
(X)
Bit
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
7
6
5
4
3
2
1
0
000050H
000054H
000058H
00005CH
TMRx
Read/write →
Initial value →
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
9
8
• Reload register (TMRLR)
Reload register (Upper byte)
Address: ch.4
ch.5
ch.6
ch.7
Bit
Read/write →
Initial value →
Reload register (Lower byte)
Address: ch.4
ch.5
ch.6
ch.7
14
13
12
11
10
(W)
(X)
Bit
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
7
6
5
4
3
2
1
0
000052H
000056H
00005AH
00005EH
Read/write →
Initial value →
38
15
000053H
000057H
00005BH
00005FH
TMRLRx
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
MB90210 Series
(2) Block Diagram
16
16-bit reload register
4
Reload
UF
16-bit down counter
Internal data bus
16
RELD
2
INTE
GATE
UF
CSL 1
IRQ
Clear
EI 2 OSCLR
Clear (RELD = 0)
Clock selector
STRT
CSL 0
2
IN CTL
φ
φ
φ
φ
22
25
26
28
Port (TIN)
2
GATE
GATL
2
39
MB90210 Series
4. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:
•
•
•
•
•
•
•
•
•
•
Full duplex double buffer
Data transfer synchronous or asynchronous with clock pulses
Multiprocessor mode support (Mode 2)
Built-in dedicated baud-rate generator (Nine types)
Arbitrary baud-rate setting from external clock input or internal timer
(Use the 16-bit reroad timer 1 channel 2 for internal timer.)
Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
Variable data length (7 to 9 bit no parity, 6 to 8 bit with parity)
Error detection function (Framing, overrun, parity)
Interrupt function (Two sources for transmission and reception)
Transfer in NRZ format
The MB90210 series contains three channels for the UART.
UART channel 0 has the CTS function.
UART channel 2 provides dual I/O pin switching.
(1) Register Configuration
• Serial mode control register (UMC)
Serial mode control register
Address: ch.0
ch.1
ch.2
Bit
7
6
5
4
3
2
1
0
000020 H
000024H
000028H
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
Read/write →
Initial value →
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
9
8
UMC
• Status register (USR)
Status register
Address: ch.0
ch.1
ch.2
Bit
000021 H
000025H
000029H
Read/write →
Initial value →
15
14
13
12
11
10
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
2
1
USR
• Input data register (UIDR)/output data register (UODR)
Input data register/output data register
Address: ch.0
ch.1
ch.2
Bit
000022 H
000026H
00002AH
Read/write →
Initial value →
40
7
6
5
4
3
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
UIDR (read)/
UODR (write)
MB90210 Series
• Rate and data register (URD)
Rate and data register
Address: ch.0
ch.1
ch.2
Bit
000023 H
000027H
00002BH
15
BCH
Read/write → (R/W)
Initial value → (0)
14
13
12
11
10
9
8
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
URDx
• UART redirect control register (URDR)
UART redirect control register
Bit
Address:
7
6
5
4
3
2
1
0
00002C H
—
—
—
CTE
CSP
CTSE
UDPE
SEL3
Read/write →
Initial value →
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
URDR
41
MB90210 Series
(2) Block Diagram
CONTROL BUS
Reception interrupt
(To CPU)
Dedicated baud-rate clock
16-bit reload timer 1 channel 2
(internally connected)
SCK0 to SCK3
Transmitting clock pulse
Transmission interrupt
(To CPU)
Clock
selector circuit Receiving clock pulse
External clock
SID0 to SID3
Reception control circuit
Transmission control circuit
Start bit detector
Transmission control
circuit
Received bit counter
Transmission bit
counter
Recieved parity
bit counter
Transmission parity
counter
SOD0 to SOD3
Reception status
detection circuit
Reception shifter
Transmission shifter
Start of
transmission
End of reception
SIDR
UODR
Reception error
occurence signal for
EI2OS (To CPU)
Internal data bus
UMC
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
CONTROL BUS
42
MB90210 Series
5. 10-bit A/D Converter
The 10-bit A/D converter converts the analog input voltage to a digital value. It has the following features:
Conversion time: min.6.125 µs per channel (at 16-MHz machine clock)
RC-type successive approximation with built-in sample-and-hold circuit
10-bit or 8-bit resolution
Eight analog input channels programmable for selection
Single conversion mode: Selects and converts one channel.
Scan conversion mode: Converts multiple consecutive channels (up to eight channels programmable).
Consecutive conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing
synchronized conversion start).
• On completion of A/D conversion, the converter can generate an interrupt request to the CPU. This interrupt
generation can activate the EI2OS to transfer the A/D conversion result to memory, making the converter
suitable for continuous operation.
• Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected.
Use the 16-bit reroad timer 1 channel 3 for the timer.
•
•
•
•
(1) Register Configuration
• A/D Control status register (ADCS1 and ADCS0)
A/D Control status register (Upper byte)
Address:
Bit 15
14
13
12
11
10
9
8
INT
INTE
PAUS
STS1
STS0
STRT
—
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(—)
(0)
7
6
5
4
3
2
1
0
000034 H
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
Read/write →
Initial value →
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
BUSY
000035 H
Read/write → (R/W)
Initial value → (0)
A/D Control status register (Lower byte)
Address:
Bit
ADCS1
ADCS0
• A/D Data registers (ADCD1 and ADCD0)
A/D Data register (Upper byte)
Address:
Bit 15
14
13
12
11
10
9
8
000037 H
S10
—
—
—
—
—
D9
D8
Read/write →
Initial value →
(W)
(0)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R)
(X)
(R)
(X)
A/D Data register (Lower byte)
Address:
Bit
ADCD1
7
6
5
4
3
2
1
0
000036 H
D7
D6
D5
D4
D3
D2
D1
D0
Read/write →
Initial value →
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
ADCD0
43
MB90210 Series
(2) Block Diagram
AV CC
AVRH/AVRL
AV SS
D/A converter
MPX
Input circuit
Successive
approximation register
Internal data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Comparator
Decorder
Sample-and-hold circuit
A/D data register
ADCD0, ADCD1
A/D control status register
Trigger activation
ADCS0, ADCS1
ATG
Timer activation
16-bit reload timer 1 channel 3
(internally connected)
Machine clock (φ)
44
Operation clock
Prescaler
MB90210 Series
6. PWC(Pulse Width Count) Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an
input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using
these components, the PWC timer provides the following features:
• Timer functions:
An interrupt request can be generated at set time intervals.
Pulse signals synchronized with the timer cycle can be output.
The reference internal clock can be selected from among three internal clocks.
• Pulse-width count functions:
The time between arbitrary pulse input events can be counted.
The reference internal clock can be selected from among three internal clocks.
Various count modes:
“H” pulse width (↑ to ↓) /“L” pulse width (↑ to ↓)
Rising-edge cycle (↑ to ↑) /Falling-edge cycle (↓ to ↓)
Count between edges (↑ or ↓ to ↓ or ↑)
Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.
The MB90210 series contains four channels for the PWC timer.
(1) Register Configuration
• PWC control status register (PWCSR)
PWC control status register (Upper byte)
Address: ch.0 000071 H
ch.1 000075H
ch.2 000079H
ch.3 00007DH
15
14
13
12
11
10
9
8
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
Read/write → (R/W)
Initial value → (0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
7
6
5
4
3
PWC control status register (Lower byte)
Address: ch.0
ch.1
ch.2
ch.3
Bit
Bit
2
1
0
000070 H
000074H
000078H
00007CH
CKS1
CKS0
PIS1
PIS0
S/C
MOD2
MOD1
MOD0
Read/write →
Initial value →
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
PWCSRx
45
MB90210 Series
• PWC data buffer register (PWCR)
PWC data buffer register (Upper byte)
Address: ch.0 000073 H
ch.1 000077H
ch.2 00007BH
ch.3 00007FH
Bit
15
Read/write → (R/W)
Initial value → (0)
PWC data buffer register (Lower byte)
Address: ch.0
ch.1
ch.2
ch.3
Bit
14
13
12
11
10
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
9
(R/W)
(0)
2
8
(R/W)
(0)
1
0
000072 H
000076H
00007AH
00007EH
PWCR
Read/write →
Initial value →
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
• PWC divide ratio control register (DIVR)
Divide ratio control register
Address: ch.0
ch.1
ch.2
ch.3
46
Bit
7
6
5
4
3
2
1
0
000068 H
00006AH
00006CH
00006EH
—
—
—
—
—
—
DIV1
DIV0
Read/write →
Initial value →
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
DIVR
MB90210 Series
(2) Block Diagram
PWCR read
Error detection
ERR
16
PWCR
16
Internal clock
(machine clock/4)
Write enable
Data transfer
Overflow
16
Clock
16-bit up-count timer
22
2
Timer clear
Count enable
Control bit output
Control circuit
Flag setting, etc.
Internal data bus
16
Reload
Start edge
select
Count start edge
Count edge end
3
Clock
divider
CKS 1
CKS 0
Divider clear
End edge Dividing
select
ON/OFF
PWC0
PWC1
PWC2
PWC3
Edge
detection
Count end interrupt edge
PIS 1 CKS 1
ERR PIS 0 CKS 0
Overflow interrupt request
8-bit
divider
PIS 1
PIS 0
15
PWCSR
Divide ratio
select
2
DIVR
Overflow
F.F.
POUT
*
* : The POUT pins of the MB90210 series are assigned as follows:
Channel
POUT pin
PWC
ch.0
P44/A20/PWC0/POUT0
PWC
ch.1
P45/A21/PWC1/POUT1
PWC
ch.2
P46/A22/PWC2/POUT2
PWC
ch.3
P47/A23/PWC3/POUT3
47
MB90210 Series
7. 8-bit PPG Timer
This block is an 8-bit reload timer module for PPG output by controlling pulse output according to the timer
operation.
The hardware configuration of this block is an 8-bit down counter, two 8-bit reload registers, an 8-bit control
register, and an external pulse output pin. Using these components, the module provides the following features:
PPG output operation: The module outputs pulse waves of any period and duty factor. It can also be used as
a D/A converter using an external circuit.
(1) Register Configuration
• PPG operation mode control register (PPGC)
PPG operation mode control register
Address:
Bit
000088 H
Read/write →
Initial value →
7
6
5
4
3
2
1
0
PEN
PCKS
POE
Reserved
PUF
—
—
Reserved
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(—)
(—)
(—)
(—)
(R/W)
(1)
PPGC
• PPG reload registers (PRLL and RRLH)
PPG reload register
Address:
Bit 15
14
11
10
9
8
PRLH
Bit
PPG reload register
7
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
00008A H
Read/write →
Initial value →
48
12
00008B H
Read/write → (R/W)
Initial value → (X)
Address:
13
PRLL
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
MB90210 Series
(2) Block Diagram
PPG
output pin
(Port section)
Output enable
Output A of timebase counter
Output B of timebase counter
PPG
output latch
Invert
Count clock
selection
Clear
PEN
PCNT (Down counter)
Reload
L/H selector
PRLL
PRLBH
PRLH
Low-byte data bus
High-byte data bus
PPGC
Operation
mode control
49
MB90210 Series
8. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives
a DMA request or an interrupt request generated by the external peripherals and reports it to the F2MC-16F
CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels
of “H” and “L” for extended intelligent I/O service or, and four request levels of “H,” “L,” rising edge and falling
edge for external interrupt requests.
(1) Register Configuration
• Interrupt/DTP enable register (ENIR)
Interrupt/DTP enable register
Address:
Bit
000030H
Read/write →
Initial value →
7
6
5
4
3
2
1
0
—
—
—
—
EN3
EN2
EN1
EN0
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
—
—
—
—
ER3
ER2
ER1
ER0
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
ENIR
• Interrupt/DTP source register (EIRR)
Interrupt/DTP source register
Address:
Bit
000031 H
Read/write →
Initial value →
EIRR
• Request level setting register (ELVR)
Request level setting register
Address:
Bit
000032 H
Read/write →
Initial value →
50
ELVR
MB90210 Series
(2) Block Diagram
Internal data bus
4
4
4
8
Interrupt/DTP enable register
Gate
Source F/F
Edge detection circuit
4
INT
Interrupt/DTP source register
Request level setting register
51
MB90210 Series
9. Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase timer as
the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18bit timer and an interval interrupt control circuit.
(1) Register Configuration
• Watchdog timer control register (WTC)
Watchdog timer control register
Address:
Bit
0000A8H
Read/write →
Initial value →
7
6
5
4
3
2
1
0
PONR
STBR
WRST
ERST
SRST
WTE
WT1
WT0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
WTC
• Timebase timer control register (TBTC)
Timebase timer control register
Address:
Bit 15
0000A9H
Read/write →
Initial value →
52
14
13
12
11
10
9
8
Reserved
—
—
TBIE
TBOF
TBR
TBC1
TBC0
(W)
(1)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
(R/W)
(0)
TBTC
MB90210 Series
(2) Block Diagram
Oscillation clock
TBTC
TBC1
Selector
TBC0
2 12
2 14
2 16
2 18
TBTRES
Clock input
Timebase timer
TBR
TBIE
AND
Q
2 14 2 16
2 17 2 18
S
R
Internal data bus
TBOF
Timebase
interrupt
WTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog
reset
generator
CLR
WDGRST
To internal reset generator
WTE
PONR
From power-on occurence
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit in STBYC
register
53
MB90210 Series
10. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F2MC-16F CPU to generate or cancel by software.
(1) Register Configuration
• Delayed interrupt source generate/release register (DIRR)
Delayed interrupt source generate/release register Bit 15
Address:
14
13
12
11
10
9
8
00009FH
—
—
—
—
—
—
—
R0
Read/write →
Initial value →
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
Internal data bus
(2) Block Diagram
54
Delayed interrupt source
generate/release register
Source latch
DIRR
MB90210 Series
11. Write-inhibit RAM
The write-inhibit RAM is write-protectable with the WI pin input. Maintaining the “L” level input to the WI pin
prevents a certain area of RAM from being written. The WI pin has a 4-machine-cycle filter.
(1) Register Configuration
• WI control register (WICR)
WI control register
Address:
Bit
7
6
5
4
3
2
1
0
00008EH
—
—
—
WI
—
—
—
—
Read/write →
Initial value →
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(1)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
WICR
(2) Write-inhibit RAM Area
Write-inhibit RAM area
001100H to 0011FFH (MB90214/P214A/P214B/W214A/W214B)
001100H to 0012FFH (MB90V210)
(3) Block Diagram
Access to other area
WI
4-machine-cycle
skew removal
4-machine-cycle
skew removal
L
H
S
R
Q
S
Q
Preceded
R
Write-inhibit
circuit
Select
WR
Writeinhibit
RAM
RAM
decoder
Internal data bus
55
MB90210 Series
12. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function
The MB90210 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware
standby mode, and gear function.
Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop
mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data.
The clock gear function divides the external clock frequency, which is used usually as it is, to provide a lower
machine clock frequency. This function can therefore lower the overall operation speed without changing the
oscillation frequency. The function can select the machine clock as a division of the frequency of crystal oscillation
or external clock input by 1, 2, 4, or 16.
The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode
or hardware standby mode.
(1) Register Configuration
• Standby control register (STBYC)
Standby control register
Address:
Bit
7
6
5
4
3
2
1
0
0000A0H
STP
SLP
SPL
RST
OSC1
OSC0
CLK1
CLK0
Read/write →
Initial value →
(W)
(0)
(W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(*)
(R/W)
(*)
(R/W)
(*)
(R/W)
(*)
Note: The initial value(*) of bit0 to bit3 is changed by reset source.
56
STBYC
MB90210 Series
(2) Block Diagram
Oscillation clock
Gear divider circuit
1/1 1/2 1/4 1/16
CPU clock
CPU clock
generator
STBYC
CLK1
Selector
Internal data bus
CLK0
Peripheral clock
Peripheral clock
generator
SLP
Standby control circuit
STP
RST Clear HST start
HST pin
Interrupt request
or RST
OSC1
Selector
OSC0
20
16
2
17
2
18
2
Clock input
Timebase timer
2
SPL
Pin high-impedance control circuit
14
2
16
2
17
18
2
Pin HI–Z
RST pin
RST
Internal reset generator
Internal RST
To watchdog timer
WDGRST
57
MB90210 Series
■ ELECTRICAL CHARACTERISTICS (MB90V210, device used for evaluation, is excluded)
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin
name
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
VCC
VSS – 0.3
VSS + 7.0
V
Program voltage
VPP
VPP
VSS – 0.3
13.0
V
MB90P214A/W214A
MB90P214B/W214B
AVCC
AVCC
VSS – 0.3
VCC + 0.3
V
Power supply voltage
for A/D converter
AVRH
AVRL
AVRH
AVRL
VSS – 0.3
AVCC
V
Reference voltage for A/D
converter
Input voltage
VI *1
—
VSS – 0.3
VCC + 0.3
V
Output voltage
VO
*2
VSS – 0.3
VCC + 0.3
V
“L” level output current
IOL
*3
—
20
mA
Rush current
“L” level total output current
ΣIOL
*3
—
50
mA
Total output current
“H” level output current
IOH
*2
—
–10
mA
Rush current
“H” level total output current
ΣIOH
*2
—
–48
mA
Total output current
Power consumption
Pd
—
—
650
mW
Operating temperature
TA
—
–40
+105
°C
MB90214/P214B/W214B
–40
+85
°C
MB90P214A/W214A
Storage temperature
Tstg
—
–55
+150
°C
Analog power supply voltage
*1: VI and VO must not exceed VCC + 0.3 V.
*2: Output pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82
*3: Output pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P75, P80 to P82
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
58
MB90210 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
Analog power supply
voltage
Clock frequency
Operating temperature
Symbol
Pin
name
Value
Unit
Remarks
Min.
Max.
4.5
5.5
V
When operating
3.0
5.5
V
Retains the RAM state in stop
mode
Power supply voltage for A/D
converter
VCC
VCC
AVCC
AVCC
4.5
VCC + 0.3
V
AVRH
AVRH
AVRL
AVCC
V
AVRL
AVRL
AVSS
AVRH
V
10
16
MHz
–40
+105
°C
Single-chip mode
MB90214/P214B/W214B
–40
+85
°C
Single-chip mode
MB90P214A/W214A
–40
+70
°C
External bus mode
FC
TA*
—
—
Reference voltage for A/D
converter
* : Excluding the temperature rise due to the heat produced.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
59
MB90210 Series
3. DC Characteristics
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Parameter
“H” level input
voltage
“L” level input
voltage
“H” level output
voltage
“L” level output
voltage
Input leakage
current
Analog power
supply voltage
Symbol
Condition
Value
Min.
Typ.
Max.
Unit
Remarks
VIH
*1
—
0.7 VCC
—
VCC + 0.3
V
CMOS level input
VIHS
*2
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIHM
MD0 to MD2
—
VCC – 0.3
—
VCC + 0.3
V
VIL
*1
—
VSS– 0.3
—
0.3 VCC
V
CMOS level input
VILS
*2
—
VSS – 0.3
—
0.2 VCC
V
Hysteresis input
VILM
MD0 to MD2
—
VSS – 0.3
—
VSS+ 0.3
V
VOH
*3
VCC = 4.5 V
IOH = –4.0 mA
VCC – 0.5
—
VCC
V
VOH1
X1
VCC = 4.5 V
IOH = –2.0 mA
VCC – 2.3
—
VCC
V
VOL
*4
VCC = 4.5 V
IOL = 4.0 mA
0
—
0.4
V
VOL1
X1
VCC = 4.5 V
IOL = 2.0 mA
0
—
VCC – 2.3
V
VCC =5.5 V
II
*1
*2
0.2 VCC < VI < 0.8
VCC
—
—
±10
µA
II2
X0
VCC =5.5 V
—
—
±25
µA
—
3
7
mA
—
—
—
5*5
µA
—
—
10
—
pF
IA
IAH
Input capacitance CIN
Pull-up resistor
Pin name
0.2 VCC < VIH < 0.8 VCC
FC = 16 MHz
AVCC
*6
Except pins with
pull-up/pull-down
resistor and RST
pin
In stop mode,
TA = +25°C
RST
—
22
50
110
kΩ
*7
MB90214
MB90P214A/
W214A/P214B/
W214B
MD1
—
110
300
650
kΩ
*7
MB90214
Generic pin
—
22
50
110
kΩ
*7
MB90214
MD0, MD2
—
110
300
650
kΩ
*7
MB90214
Generic pin
—
22
50
110
kΩ
*7
MB90214
RpuIU
Pull-down resistor RpuID
(Continued)
60
MB90210 Series
(Continued)
Parameter
Power supply
voltage*9
Symbol
Pin name
Condition
ICC
VCC
FC = 16 MHz
ICCS
VCC
FC = 16 MHz
ICCH
VCC
—
Value
Unit
Remarks
Min.
Typ.
Max.
—
50*8
80
mA MB90214
—
70*8
100
MB90P214A/
W214A
mA
MB90P214B/
W214B
—
—
40
mA In sleep mode
—
5
10
µA
TA = +25°C
In stop mode
In hardware
standby input
time
*1: CMOS level input (P00 to P07, P10 to P17, X0)
*2: Hysteresis input pins (RST, HST, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 P70 to P75, P80
to P82)
*3: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82)
*4: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to
P75, P80 to P82)
*5: The current value applies to the CPU stop mode with A/D converter inactive (VCC = AVCC = AVRH = +5.5 V).
*6: Other than VCC, VSS, AVCC and AVSS
*7: A list of availabilities of pull-up/pull-down resistors
Pin name
MB90214
MB90P214A/W214A
MB90P214B/W214B
RST
Availability of pull-up resistors is
optionally defined.
Pull-up resistors
available
Pull-up resistors
available
MD1
Pull-up resistors available
Unavailable
Unavailable
MD0, MD2
Pull-down resistors available
Unavailable
Unavailable
Generic pin
Availability of pull-up/pull-down
resistors is optionally defined.
Unavailable
Unavailable
*8: VCC = +5.0 V, VSS = 0.0 V, TA = +25°C, FC = 16 MHz
*9: Measurement condition of power supply current; external clock pin and output pin are open.
Measurement condition of VCC; see the table above mentioned.
61
MB90210 Series
2. AC Characteristics
(1) Clock Timing Standards
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol name
Condition
Unit
Remarks
Parameter
Min. Typ. Max.
Clock frequency
FC
X0, X1
—
10
—
16
MHz
Clock cycle time
tC
X0, X1
—
62.5
—
100
ns
1/FC
Input clock pulse width
PWH
PWL
X0
—
0.4 tC
—
0.6 tC
ns
Duty ratio: 60%
Input clock rising/falling time
tcr
tcf
X0
—
—
—
8
ns
tcr + tcf
• Clock Input Timings
tC
0.7 VCC
0.7 VCC
0.3 VCC
X0
PWH
PWL
tcr
tcf
• Clock Conditions
When a crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
Open
C1
C2
C1 = C2 = 10 pF
Select the optimum capacity value for the resonator.
62
MB90210 Series
• Relationship between Clock Frequency and Power Supply Voltage
V CC
[V]
Single-chip mode
(MB90214/P214B/W214B)
(MB90P214A/W214A)
External bus mode
: (TA = –40°C to +105°C, FC = 10 to 16 MHz)
: (TA = –40°C to +85°C, FC = 10 to 16 MHz)
: (TA = –40°C to +70°C, FC = 10 to 16 MHz)
5.5
Operation assurance range
4.5
0
16
10
FC
[MHz]
(2) Clock Output Timing Standards
Parameter
Machine cycle time
CLK ↑ → CLK↓
Symbol
External mode: (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Condition
Unit Remarks
name
Min.
Typ.
Max.
tCYC
tCHCL
Load condition:
80 pF
CLK
62.5
—
1600
ns
tCYC/
2 – 20
—
tCYC/2
ns
*
* : tCYC = n/FC, n gear ratio (1, 2, 4, 16)
tCYC
tCHCL
CLK
1/2 VCC
1/2 VCC
63
MB90210 Series
(3) Recommended Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Series)
X0
X1
FAR
C1 *2
*1
C2 *2
*1: Fujitsu Acoustic Resonator
FAR part number
Frequency
(built-in capacitor type)
FAR-C4C F-1 6000- 02
Initial deviation of
FAR frequency
(TA = +25°C)
Temperature
characteristics of
FAR frequency
(TA = –20°C to +60°C)
±0.5%
±0.5%
±0.5%
±0.5%
16.00
FAR-C4C F-1 6000- 12
Load
capacitance*2
Built-in
Inquiry: FUJITSU LIMITED
(4) Reset and Hardware Standby Input Standards
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
Typ.
Max.
Reset input time
tRSTL
RST
Hardware standby input time tHSTL
HST
—
5 tCYC
—
—
ns
5 tCYC
—
—
ns
* : The machine cycle (tCYC) at hardware standby input is set to 1/16 divided oscillation.
tRSTL, tHSTL
RST
HST
0.2 VCC
64
0.2 VCC
*
MB90210 Series
(5) Power on Supply Specifications (Power-on Reset)
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
Typ.
Max.
Power supply rising time
tR
VCC
—
—
—
30
ms
Power supply cut-off time
tOFF
VCC
—
1
—
—
ms
*
* : Before the power rising, VCC must be less than +0.2 V.
Notes: • The above specifications are for the power-on reset.
• Always apply power-on reset using these specifications, regardless of whether or not
the power-on reset is needed.
• There are some internal registers (such as STBYC) which are only initialized by the power-on reset.
• Power-on Reset
tR
VCC
4.5 V
0.2 V
0.2 V
0.2 V
tOFF
Note: Caution on switching power supply
Abrupt change of supply voltage may initiate power-on reset, even if the above requirements are not met.
It is, therefore, recommended to power up gradually during the instantaneous change of power supply as
shown in the figure below.
• Changing Power Supply
Main power
supply voltage
The rising edge should be 50 mV/ms or less.
Subpower
supply voltage
VSS
65
MB90210 Series
(6) Bus Read Timing
Parameter
Symbol
Pin
name
Valid address → RD ↓ time
tAVRL
A23 to A00
RD pulse width
tRLRH
RD
RD ↓ → valid data input
tRLDV
RD ↑ → data hold time
tRHDX
Valid address→ valid data
input
tAVDV
RD ↑ → address valid time
tRHAX
Valid address → CLK ↑ time
tAVCH
RD ↓ → CLK ↓ time
tRLCL
(VCC = +4.5 to +5.5 , VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit Remarks
Min.
Max.
tCYC/2 – 20
—
ns
tCYC – 25
—
ns
—
tCYC – 30
ns
0
—
ns
—
3 tCYC/2 – 40
ns
tCYC/2 – 20
—
ns
A23 to A00
CLK
tCYC/2 – 25
—
ns
RD, CLK
tCYC/2 – 25
—
ns
D15 to D00 Load
condition:
80 pF
A23 to A00
tAVCH
tRLCL
0.7 VCC
CLK
0.3 VCC
tRLRH
tAVRL
RD
0.7 VCC
0.3 VCC
tRHAX
A23 to A00
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tRHDX
tRLDV
tAVDV
D15 to D00
0.7 VCC
0.3 VCC
66
Read data
0.7 VCC
0.3 VCC
MB90210 Series
(7) Bus Write Timing
Parameter
Symbol
(VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit Remarks
Min.
Max.
Pin name
Valid address → WR ↓ time tAVWL
A23 to A00
tCYC/2 – 20
—
ns
WR ↓ pulse width
tWLWH
WRL, WRH
tCYC – 25
—
ns
Valid data output → WR ↑
time
tDVWH
tCYC – 40
—
ns
WR ↑ → data hold time
tWHDX
tCYC/2 – 20
—
ns
Load
condition:
80 pF
D15 to D00
WR ↑ → address valid time tWHAX
A23 to A00
tCYC/2 – 20
—
ns
WR ↓ → CLK ↓ time
WRL, WRH, CLK
tCYC/2 – 25
—
ns
tWLCH
tWLCL
0.3 VCC
CLK
tWLWH
WR
(WRL, WRH)
0.7 VCC
0.3 VCC
tWHAX
tAVWL
0.7 VCC
0.3 VCC
A23 to A00
tDVWH
D15 to D00
Undefined
tWHDX
0.7 VCC
Write data
0.3 VCC
67
MB90210 Series
(8) Ready Signal Input Timing
Parameter
(VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol Pin name
RDY setup time
tRYHS
RDY hold time
tRYHH
Load condition:
80 pF
RDY
40
—
ns
0
—
ns
Note: Use the auto-ready function if the RDY setup time is insufficient.
CLK
0.7 VCC
0.7 VCC
A23 to A00
RD/WR
(WRL, WRH)
tRYHS
RDY
No wait
tRYHH
0.8 VCC
tRYHS
tRYHH
0.8 VCC
Wait
0.8 VCC
0.8 VCC
0.2 VCC
(9) Hold Timing
Symbol
Parameter
Pin floating → HAK ↓ time
tXHAL
HAK ↑ → pin valid time
tHAHV
Pin
name
HAK
(VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit
Remarks
Min.
Max.
Load condition:
80 pF
30
tCYC
ns
tCYC
2tCYC
ns
Note: It takes at least one cycle for HAK to vary after HRQ is fetched.
HRQ
0.8 VCC
0.2 VCC
0.3 VCC
HAK
tXHAL
tHAHV
Each pin
High impedance
68
0.7 VCC
MB90210 Series
(10) UART Timing
Single-chip mode
MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol name
Condition
Unit
Remarks
Parameter
Min.
Max.
Serial clock cycle time tSCYC
8 tCYC
—
ns
SCLK ↓ → SOUT
delay time
tSLOV
–80
80
ns
Valid SIN → SCLK ↑
tIVSH
100
—
ns
SCLK ↑ → Valid SIN
hold time
tSHIX
60
—
ns
4 tCYC
—
ns
4 tCYC
—
ns
Serial clock “H” pulse
tSHSL
width
—
Load condition:
80 pF
Serial clock “L” pulse
width
tSLSH
SCLK ↓ → SOUT
delay time
tSLOV
—
150
ns
Valid SIN → SCLK ↑
tIVSH
60
—
ns
SCLK ↑ → Valid SIN
hold time
tSHIX
60
—
ns
Internal shift
clock mode
output pin
External shift
clock mode
output pin
Notes: • These AC characteristics assume the CLK synchronous mode.
• tCYC is the machine cycle (unit: ns).
69
MB90210 Series
• Internal Shift Clock Mode
tSCYC
SCK
0.7 VCC
0.3 VCC
0.3 VCC
tSLOV
0.7 VCC
SOD
0.3 VCC
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SID
0.8 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
SCK
tSHSL
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
tSLOV
SOD
0.7 VCC
0.3 VCC
tIVSH
SID
70
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
MB90210 Series
(11) Resource Input Timing
Single-chip mode
MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Parameter
Min.
Typ.
Max.
4 tCYC
—
—
ns
TIN0 to TIN3
Input pulse width
tTIWH
tTIWL
2 tCYC
—
—
2 tCYC
—
—
ns
2 tCYC
—
—
ns
INT0 to INT3
3 tCYC
—
—
ns
ATG
2 tCYC
—
—
ns
WI
4 tCYC
—
—
ns
Load
condition:
PWC0 to PWC3 80 pF
TIN4 to TIN7
tWIWL
0.8 VCC
External event
count input mode
Trigger input/
Gate input mode
Gate input mode
0.8 VCC
TIN0 to TIN7
PWC0 to PWC3
INT0 to INT3
WI
0.2 VCC
tTIWH
0.2 VCC
tTIWL, tWIWL
(12) Resource Output Timing
MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min. Max.
Single-chip mode
CLK ↑ →
TOUT transition time
tTO
TOUT0 to TOUT3
PPG
POUT0 to POUT3
CLK
TOUT0 to TOUT3
PPG
POUT0 to POUT3
Load condition:
80 pF
—
30
ns
0.7 VCC
0.7 VCC
0.3VCC
tTO
71
MB90210 Series
5. A/D Converter Electrical Characteristics
Single-chip mode MB90214/P214B/W214B:
(AVCC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +105°C, +4.5 V ≤ AVRH – AVRL)
Single-chip mode MBP90214A/W214A:
(AVCC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C, +4.5 V ≤ AVRH – AVRL)
External bus mode:
(AVCC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +70°C, +4.5 V ≤ AVRH – AVRL)
Value
Unit
Remarks
Symbol Pin name
Condition
Parameter
Min.
Typ.
Max.
Resolution
n
—
—
—
—
10
bit
Total error
—
—
—
–3.0
—
+3.0
LSB
Linearity error
—
—
—
–2.0
—
+2.0
LSB
Differential
linearity error
—
—
—
—
—
±1.5
LSB
Zero transition
voltage
VOT
Full-scale
transition voltage
VFST
Conversion time
TCONV
—
AVRL – 1.5 AVRL + 0.5 AVRL + 2.5 LSB
—
AVRH – 3.5 AVRH – 1.5 AVRH + 0.5 LSB
AN0 to AN7
6.125
—
—
µs
98 machine
3.75
—
—
µs
60 machine
—
—
—
±0.1
µA
—
AVRL
—
AVRH
V
AVRH
—
AVRL
—
AVCC
V
AVRL
—
AVSS
—
AVRH
V
—
—
200
500
µA
—
—
—
5*
µA
—
—
—
4
LSB
—
tCYC = 62.5 ns
Sampling period
TSAMP
Analog port input
current
IAIN
Analog input
voltage
VAIN
Analog reference
voltage
Reference voltage
supply current
Interchannel
disparity
—
cycles
cycles
AN0 to AN7
—
IR
IRH
—
AVRH
AN0 to AN7
* : The current value applies to the CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = +5.5 V).
Notes: (1) The smaller the | AVRH – AVRL |, the greater the error would become relatively.
(2) Use the output impedance of the external circuit for analog input under the following conditions:
.
External circuit output impedance < approx. 10 kΩ (Sampling period =. 3.75 µs, tCYC = 62.5 ns)
(3) Precision values are standard values applicable to sleep mode.
(4) If VCC/AVCC or VSS/AVSS is caused by a noise to drop to below the analog input voltage, the analog input
current is likely to increase. In such cases, a bypass capacitor or the like should be provided in the external
circuit to suppress the noise.
72
MB90210 Series
• Equivalent Circuit of Analog Input Circuit
C0
Analog input
Comparator
R ON1
External impedance
R ON2
RON1: Approx. 1.5 kΩ
RON2: Approx. 1.5 kΩ
C0: Approx. 60 pF
C1
C1: Approx. 4 pF
Note: The values shown here are reference values.
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
Total error: Difference between actual and logical values. This error is caused by a zero transition error,
full-scale transition error, linearity error, differential linearity error, or by noise.
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Digital output
11 1111 1111
11 1111 1110
11 1111 1101
•
Theoretical value
Actual conversion value
•
•
Theoretical value V NT
Total error
•
N+1
N
N–1
•
•
•
Linerity error
•
N × 1LSB + V 0T
00 0000 0010
00 0000 0001
00 0000 0000
AVRL
V NT
V(N–1)T
V(N+1)T
AVRH – AVRL
1LSB = VFST – V0T • 1LSB theoretical value =
1022
1022
N = 0 to 1022
V
NT– (N × 1LSB + V0T)
Linearity error =
VNT (N = 0) = V0T
1LSB
VNT (N = 1022) = VFST
V
NT – V(N – 1) T
Differential linearity error =
– 1 N = 1 to 1022
1LSB
V 0T V 1T
•
•
•
•
V 2T
AVRH (V)
V FST
VNT – { ( N + 0.5 ) × 1LSB theoretical value }
Total error =
N = 0 to 1022
1LSB theoretical value
73
MB90210 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current
I CCH vs. T A example characteristics
I CCH (µA)
40
I CC vs. T A example characteristics
I CC (mA)
100
F C = 16 MHz
External clock input
V CC = 5.5 V
90
V CC = 5.5 V
30
80
20
MB90P214A
70
10
60
0
MB90214
50
–10
40
–50
0
50
100
–50
150
0
50
100
150
T A (°C)
T A (°C)
Note: These are not assured value of characteristics but example characteristics.
(2) Output Voltage
V OL vs. I OL example characteristics
V OL (V)
V OH vs. I OH example characteristics
V OH (V)
5.5
T A = +25°C
V CC = 5.0 V
5.0
2.0
4.5
1.0
4.0
0.5
3.5
0.0
T A = +25°C
V CC = 5.0 V
1.5
–0.5
3.0
–15
–10
–5
I OH (mA)
0
5
–5
0
5
10
I OL (mA)
Note: These are not assured value of characteristics but example characteristics.
74
15
20
25
MB90210 Series
(3) Pull-up/Pull-down Resistor
Pull-down resistor example characteristics
R pul D (kΩ)
100
Pull-up resistor example characteristics
R pul U (kΩ)
100
V CC = 4.5 V
90
90
V CC = 5.0 V
80
80
V CC = 5.5 V
70
70
V CC = 4.5 V
60
60
V CC = 5.0 V
V CC = 5.5 V
50
50
40
40
30
30
20
20
–50
0
50
100
150
–50
0
50
T A (°C)
100
150
T A (°C)
Pull-down resistor example characteristics
R pul D (kΩ)
Pull-up resistor example characteristics
R pul U (kΩ)
500
500
V CC = 5.5 V
400
400
300
300
200
200
V CC = 5.5 V
100
100
–50
0
50
100
–50
150
0
50
100
150
T A (°C)
T A (°C)
Note: These are not assured value of characteristics but example characteristics.
(4) Analog Filter
Analog filter example characteristics
Input pulse width (ns)
80
T A = +25°C
70
60
50
40
30
Filtering enable
20
10
4.0
4.5
5.0
5.5
6.0
V CC (V)
Note: These are not assured value of characteristics but example characteristics.
75
MB90210 Series
■ INSTRUCTIONS (421 INSTRUCTIONS)
Table 1
Description of Items in Instruction List
Item
Mnemonic
Description
English upper case and symbol: Described directly in assembler code.
English lower case: Converted in assembler code.
Number of letters after English lower case: Describes bit width in code.
#
Describes number of bytes.
~
Describes number of cycles.
For other letters in other items, refer to table 4.
B
Describes correction value for calculating number of actual states.
Number of actual states is calculated by adding value in the ~section.
Operation
Describes operation of instructions.
LH
Describes a special operation to 15 bits to 08 bits of the accumulator.
Z : Transfer 0.
X : Sign-extend and transfer.
– : No transmission
AH
Describes a special operation to the upper 16-bit of the accumulator.
* : Transmit from AL to AH.
– : No transfer.
Z : Transfer 00H to AH.
X : Sign-extend AL and transfer 00H or FFH to AH.
I
S
T
N
Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),
V (overflow), and C (carry) flags.
* : Changes after execution of instruction.
– : No changes.
S : Set after execution of instruction.
R : Reset after execution of instruction.
Z
V
C
RMW
76
Describes whether or not the instruction is a read-modify-write type (a data is read out from
memory etc. in single cycle, and the result is written into memory etc.).
* : Read-modify-write instruction
– : Not read-modify-write instruction
Note: Not used to addresses having different functions for reading and writing operations.
MB90210 Series
Table 2
Description of Symbols in Instruction Table
Item
A
Description
32-bit accumlator
The bit length is dependent on the instructions to be used.
Byte : Lower 8-bit of AL
Word :16-bit of AL
Long : AL: 32-bit of AH
AH
Upper 16-bit of A
AL
Lower 16-bit of A
SP
Stack pointer (USP or SSP)
PC
Program counter
SPCU
Stack pointer upper limited register
SPCL
Stack pointer lower limited register
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
Ri
DTB, ADB, SSB, USB, DPR
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
addr16
addr24
ad24 0 to 15
ad24 16 to 23
io
#imm4
#imm8
#imm16
#imm32
ext (imm8)
disp8
disp16
bp
vct4
vct8
Specify shortened direct address.
Specify direct address.
Specify physical direct address.
bit0 to bit15 of addr24
bit16 to bit 23 of addr24
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data calculated by sign-extending an 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset value
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
Specify PC relative branch.
Specify effective address (code 00 to 07).
Specify effective address (code 08 to 1F).
rlst
Register allocation
77
MB90210 Series
Table 3
Code
00
01
02
03
04
05
06
07
Symbol
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Field
Address type
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension block*
Register direct
"ea" corresponds to byte, word, and
long word from left respectively.
—
Register indirect
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
0
Register indirect with post increment
0
1
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
2
0
0
2
2
Note: Number of bytes for address extension corresponds to “+” in the # (number of bytes) part in the instruction
table.
78
MB90210 Series
Table 4
Number of Execution Cycles in Addressing Modes
(a)*
Code
Operand
00 to 07
Ri
RWi
RLi
Listed in instruction table
08 to 0B
@RWj
1
0C to 0F
@RWj +
4
10 to 17
@RWi + disp8
1
18 to 1B
@RWj + disp16
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
2
2
2
1
Number of execution cycles for addressing modes
Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.
Table 5
Correction Value for Number of Cycles for Calculating Actual Number of Cycles
(b)*
(c)*
(d)*
byte
word
long
Internal register
+0
+0
+0
Internal RAM even address
Internal RAM odd address
+0
+0
+0
+1
+0
+2
Other than internal RAM even address
Other than internal RAM odd address
+1
+1
+1
+3
+2
+6
External data bus 8-bit
+1
+3
+6
Operand
Notes: (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.
79
MB90210 Series
Table 6
Transmission Instruction (Byte) [50 Instructions]
Mnemonic
MOV A, dir
MOV A, addr16
MOV A, Ri
MOV A, ear
MOV A, eam
MOV A, io
MOV A, #imm8
MOV A, @A
MOV A, @RLi + disp8
MOV A, @SP + disp8
MOVP A, addr24
MOVP A, @A
MOVN A, #imm4
#
~
2
2
2
3
1
1
1
2
2 + 2 + (a)
2
2
2
2
2
2
6
3
3
3
3
5
2
2
1
1
B
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RWi + disp8
A, @RLi + disp8
A, @SP + disp8
MOVPX A, addr24
MOVPX A, @A
2
2
2
3
1
2
1
2
2 + 2 + (a)
2
2
2
2
2
2
3
2
6
3
3
3
3
5
2
2
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVP
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi + disp8, A
@SP + disp8, A
addr24, A
MOV
MOV
MOVP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Ri, ear
Ri, eam
@A, Ri
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
MOV
@AL, AH
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
*
–
*
I
–
–
–
–
–
–
–
–
–
–
–
–
–
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
(b)
X
X
X
X
X
X
X
X
byte (A) ← ((RWi) + disp8) X
byte (A) ← ((RLi) + disp8) X
byte (A) ← ((SP) + disp8) X
X
byte (A) ← (addr24)
X
byte (A) ← ((A))
*
*
*
*
*
*
*
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
3
1
1
2
2
2 + 2 + (a)
2
2
6
3
3
3
3
5
(b)
(b)
0
0
(b)
(b)
(b)
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte (addr24) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2 + 3 + (a)
3
2
3
2
2 + 3 + (a)
2
2
3
3
3
3
2
3
3 + 2 + (a)
0
(b)
(b)
0
(b)
0
(b)
(b)
0
(b)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(b)
byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
3
2
2 + 3 + (a) 2 × (b)
0
4
2
2 + 5 + (a) 2 × (b)
byte (A) ← ((RLi) + disp8)
byte (A) ← ((SP) + disp8)
byte (A) ← (addr24)
byte (A) ← ((A))
byte (A) ← imm4
byte ((RLi) + disp8) ← (A)
byte ((SP) + disp8) ← (A)
LH AH
S
–
–
–
–
–
–
–
–
–
–
–
–
–
T
–
–
–
–
–
–
–
–
–
–
–
–
–
N
*
*
*
*
*
*
*
*
*
*
*
*
R
Z
*
*
*
*
*
*
*
*
*
*
*
*
*
V
–
–
–
–
–
–
–
–
–
–
–
–
–
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
80
MB90210 Series
Table 7
Mnemonic
#
Transmission Instruction (Word) [40 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
2
2
A, dir
2
3
A, addr16
2
1
A, SP
1
1
A, RWi
1
2
A, ear
2 + 2 + (a)
A, eam
2
2
A, io
2
2
A, @A
2
3
A, #imm16
3
A, @RWi + disp8 2
6
3
A, @RLi + disp8
3
A, @SP + disp8 3
3
5
MOVPW A, addr24
2
2
MOVPW A, @A
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
–
–
–
–
–
–
–
–
–
word (A) ← ((RWi) +disp8) –
word (A) ← ((RLi) +disp8) –
word (A) ← ((SP) + disp8) –
–
word (A) ← (addr24)
–
word (A) ← ((A))
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
4
1
1
2
2+
2
2
3
3
5
2
2
2+
2
2+
3
4
4
4+
2
2
2
2
1
2
2 + (a)
2
3
6
3
3
3
2
3 + (a)
3
3 + (a)
2
3
2
2 + (a)
(c)
(c)
0
0
0
0
(c)
(c)
(c)
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← imm16
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
–
–
–
–
–
–
–
–
word ((RWi) +disp8) ← (A) –
word ((RLi) +disp8) ← (A) –
word ((SP) + disp8) ← (A) –
–
word (addr24) ← (A)
–
word ((A)) ← (RWi)
–
word (RWi) ← (ear)
–
word (RWi) ← (eam)
–
word (ear) ← (RWi)
–
word (eam) ← (RWi)
–
word (RWi) ← imm16
–
word (io) ← imm16
–
word (ear) ← imm16
–
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
(c)
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVPW
MOVPW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, #imm16
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi + disp8, A
@RLi + disp8, A
@SP + disp8, A
addr24, A
@A, RWi
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
MOVW @AL, AH
XCHW
XCHW
XCHW
XCHW
A, ear
A, eam
RWi, ear
RWi, eam
0
3
2
2 + 3 + (a) 2 × (c)
0
4
2
2 + 5 + (a) 2 × (c)
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
81
MB90210 Series
Table 8
Mnemonic
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A
MOVPL @A, RLi
MOVL
MOVPL
MOVL
MOVL
@SP + disp8, A
addr24, A
ear, A
eam, A
Transmission Instruction (Long) [11 Instructions]
#
~
2
2
2 + 3 + (a)
5
3
3
4
5
4
2
3
2
5
3
4
5
4
2
2
2 + 3 + (a)
B
0
(d)
0
(d)
(d)
(d)
Operation
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (A) ← (addr24)
long (A) ← ((A))
–
–
–
–
–
–
–
–
–
–
–
–
I
–
–
–
–
–
–
(d)
long ((A)) ← (RLi)
–
–
–
–
–
*
*
–
–
–
(d)
(d)
0
(d)
long ((SP) + disp8) ← (A)
long (addr24) ← (A)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
long (A) ← ((SP) + disp8)
LH AH
S
–
–
–
–
–
–
T
–
–
–
–
–
–
N
*
*
*
*
*
*
Z
*
*
*
*
*
*
V
–
–
–
–
–
–
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
82
MB90210 Series
Table 9
Mnemonic
#
~
Add/Subtract (Byte, Word, Long) [42 Instructions]
B
Operation
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
0
2
(b)
3
0
2
3 + (a) (b)
0
2
3 + (a) 2 × (b)
0
2
0
2
3 + (a) (b)
0
3
0
2
(b)
3
0
2
3 + (a) (b)
0
2
3 + (a) 2 × (b)
0
2
0
2
3 + (a) (b)
0
3
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
0
2
0
2
3 + (a) (c)
0
2
0
2
3 + (a) 2 × (c)
0
2
3 + (a) (c)
0
2
0
2
3 + (a) (c)
0
2
0
2
3 + (a) 2 × (c)
0
2
3 + (a) (c)
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
5
2
2 + 6 + (a)
4
5
5
2
2 + 6 + (a)
4
5
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A, ear
A, eam
A, #imm32
A, ear
A, eam
A, #imm32
0
(d)
0
0
(d)
0
LH AH
I
S
T
N
Z
V
C RMW
byte (A) ← (AH) – (AL) – (C) (decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) – (ear) + (A)
word (eam) – (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
–
–
*
*
–
–
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) – imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
83
MB90210 Series
Table 10
Mnemonic
#
Increment/Decrement (Byte, Word, Long) [12 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
INCW
INCW
ear
eam
word (ear) ← (ear) +1
0
2
2
2 + 3 + (a) 2 × (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
–
–
–
–
–
*
DECW ear
2
2
0
word (ear) ← (ear) –1
*
–
*
*
–
*
DECW eam
2 + 3 + (a) 2 × (c) word (eam) ← (eam) –1
–
–
–
–
–
*
*
*
INCL
INCL
ear
eam
long (ear) ← (ear) +1
0
4
2
2 + 5 + (a) 2 × (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
long (ear) ← (ear) –1
0
4
2
2 + 5 + (a) 2 × (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 11
Mnemonic
#
~
Compare (Byte, Word, Long) [11 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2 + 3 + (a)
2
2
0
0
(b)
0
byte (AH) – (AL)
byte (A) – (ear)
byte (A) – (eam)
byte (A) – imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2 + 3 + (a)
2
3
0
0
(c)
0
word (AH) – (AL)
word (A) – (ear)
word (A) – (eam)
word (A) – imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2 + 7 + (a)
5
3
0
(d)
0
word (A) – (ear)
word (A) – (eam)
word (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
84
MB90210 Series
Table 12
Mnemonic
Unsigned Multiply/Division (Word, Long) [11 Instructions]
#
~
B
0
Operation
DIVU
A
1
*1
DIVU
A, ear
2
*2
DIVU
A, eam
DIVUW
A, ear
2
*4
DIVUW
A, eam
2+
*5
MULU
MULU
MULU
MULUW
MULUW
MULUW
A
A, ear
A, eam
A
A, ear
A, eam
1
2
2+
1
2
2+
*8 0 byte (AH) byte (AL) → word (A)
*9 0 byte (A) byte (ear) → word (A)
*10 (b) byte (A) byte (eam) → word (A)
*11 0 word (AH) word (AL) → long (A)
*12 0 word (A) word (ear) → long (A)
*13 (c) word (A) word (eam) → long (A)
2 + *3
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of
Cycles.”
*1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation.
*2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation.
*3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation.
*4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation.
*5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero.
*9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero.
*10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero.
*11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero.
*12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero.
*13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.
85
MB90210 Series
Table 13
Signed multiplication/division (Word, Long) [11 Instructions]
Mnemonic
DIV
A
#
2
~
*1
DIV
A, ear
2
*2
DIV
A, eam
DIVW
A, ear
DIVW
A, eam
2 + *5
MUL
MUL
MUL
MULW
MULW
MULW
A
A, ear
A, eam
A
A, ear
A, eam
2
2
2+
2
2
2+
2 + *3
2
*4
*8
*9
*10
*11
*12
*13
B
Operation
0 word (AH)/byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
0 byte (AH) × byte (AL) → word (A)
0 byte (A) × byte (ear) → word (A)
(b) byte (A) × byte (eam) → word (A)
0 word (AH) × word (AL) → long (A)
0 word (A) × word (ear) → long (A)
(b) word (A) × word (eam) → long (A)
Z
–
I
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LH AH
S
–
T
–
N
–
Z
–
V
*
C RMW
*
–
For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation.
Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation.
Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation.
*5: Positive divided: Set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation.
Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal
operation.
*6: Set to (b) when the division-by-0 or an overflow, and 2 × (b) for normal operation.
*7: Set to (c) when the division-by-0 or an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13:Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two
values because of detection before and after an operation.
When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
86
MB90210 Series
Table 14
Mnemonic
#
~
B
Logic 1 (Byte, Word) [39 Instructions]
Operation
LH AH
I
S
T
N
Z
V
C RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
0
2
2
0
2
2
2 + 3 + (a) (b)
0
3
2
2 + 3 + (a) 2 × (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
0
2
2
0
2
2
2 + 3 + (a) (b)
0
3
2
2 + 3 + (a) 2 × (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
XOR
XOR
XOR
XOR
XOR
NOT
NOT
NOT
A, #imm8
A, ear
A, eam
ear, A
eam, A
A
ear
eam
0
2
2
0
2
2
2 + 3 + (a) (b)
0
3
2
2 + 3 + (a) 2 × (b)
0
2
1
0
2
2
2 + 3 + (a) 2 × (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
0
2
1
0
2
3
0
2
2
2 + 3 + (a) (c)
0
3
2
2 + 3 + (a) 2 × (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
ORW
ORW
ORW
ORW
ORW
ORW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
0
2
1
0
2
3
0
2
2
2 + 3 + (a) (c)
0
3
2
2 + 3 + (a) 2 × (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
XORW
XORW
XORW
XORW
XORW
XORW
NOTW
NOTW
NOTW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
ear
eam
0
2
1
0
2
3
0
2
2
2 + 3 + (a) (c)
0
3
2
2 + 3 + (a) 2 × (c)
0
2
1
0
3
2
2 + 3 + (a) 2 × (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
Note: For (a) to (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
87
MB90210 Series
Table 15
Mnemonic
#
~
Logic 2 (Long) [6 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
ANDL
ANDL
A, ear
A, eam
2
5
2 + 6 + (a)
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
5
2 + 6 + (a)
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL
XORL
A, ear
A, eam
2
5
2 + 6 + (a)
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 16
Mnemonic
NEG
A
NEG
NEG
ear
eam
Sign Reverse (Byte, Word) [6 Instructions]
#
~
RG
B
Operation
1
2
0
0
byte (A) ← 0 – (A)
2
3
2
2 + 5 + (a) 0
NEGW ear
NEGW eam
S
T
N
Z
V
C
RMW
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
word (ear) ← 0 – (ear)
0
2 × (c) word (eam) ← 0 – (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
0
0
2
1
I
X
byte (ear) ← 0 – (ear)
0
2
3
2
2 + 5 + (a) 0 2 × (b) byte (eam) ← 0 – (eam)
NEGW A
LH AH
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 17
Mnemonic
ABS
A
ABSW A
ABSL A
Mnemonic
NRML
A, R0
Absolute Values (Byte, Word, Long) [3 Instructions]
#
~
B
2
2
2
2
2
4
0
0
0
Operation
byte (A) ← Absolute value (A)
word (A) ← Absolute value (A)
long (A) ← Absolute value (A)
–
–
–
Z
–
–
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
Table 18
Normalize Instruction (Long) [1 Instruction]
#
~
RG
B
Operation
2
*1
1
0
long (A) ← Shift to where “1”
is originally located
byte (R0) ← Number of shifts
in the operation
* : Set to 5 when the accumulator is all “0”, otherwise set to 5 + (R0).
88
LH AH
LH AH
–
–
–
–
–
I
S
T
N
Z
V
C
RMW
–
–
–
–
*
–
–
–
MB90210 Series
Table 19
Mnemonic
RORC A
ROLC A
Shift Type Instruction (Byte, Word, Long) [27 Instructions]
#
~
B
2
2
2
2
0
0
2
Operation
LH AH
I
S T N Z V C
RMW
byte (A) ← With right-rotate carry
byte (A) ← With left-rotate carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
3 + (a)
0
2 × (b)
0
2 × (b)
byte (ear) ← With right-rotate carry
byte (eam) ← With right-rotate carry
byte (ear) ← With left-rotate carry
byte (eam) ← With left-rotate carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
2
2+
2
2+
ASR
LSR
LSL
A, R0
A, R0
A, R0
2
2
2
*1
*1
*1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASR
LSR
LSL
A, #imm8
A, #imm8
A, #imm8
3
3
3
*3
*3
*3
0
0
0
byte (A) ← Arithmetic right barrel shift (A, imm8)
byte (A) ← Logical right barrel shift (A, imm8)
byte (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
1
LSRW A/SHRW A 1
LSLW A/SHLW A 1
2
2
2
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, #imm8 3
LSRW A, #imm8 3
LSLW A, #imm8 3
*3
*3
*3
0
0
0
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
word (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
0
0
0
long (A) ← Arithmetic right barrel shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, #imm8 3
LSRL A, #imm8 3
LSLL A, #imm8 3
*4
*4
*4
0
0
0
long (A) ← Arithmetic right barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
3 + (a)
2
long (A) ← Logical right barrel shift (A, imm8)
long (A) ← Logical left barrel shift (A, imm8)
Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
Set to 3 when R0 is 0, otherwise 3 + (R0).
Set to 3 when R0 is 0, otherwise 4 + (R0).
Set to 3 when imm8 is 0, otherwise 3 + imm8.
Set to 3 when imm8 is 0, otherwise 4 + imm8.
89
MB90210 Series
Table 20
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
#
~
B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
addr16
@ear
@eam
@ear *3
@eam *3
addr24
2
1
2
3
3
2
2 + 4 + (a)
3
2
2 + 4 + (a)
3
4
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
(c)
4
2
2 + 5 + (a) 2 × (c)
(c)
5
3
2 × (c)
5
1
2 × (c)
7
2
CALLP
@eam *6
2 + 8 + (a)
CALLP
addr24 *7
@A
4
7
0
0
0
(c)
0
(d)
0
*2
2 × (c)
Branch 1 [31 Instructions]
Operation
Branch if (Z) = 1
Branch if (Z) = 0
Branch if (C) = 1
Branch if (C) = 0
Branch if (N) = 1
Branch if (N) = 0
Branch if (V) = 1
Branch if (V) = 0
Branch if (T) = 1
Branch if (T) = 0
Branch if (V) xor (N) = 1
Branch if (V) xor (N) = 0
Branch if ((V) xor (N)) or (Z) = 1
Branch if ((V) xor (N)) or (Z) = 0
Branch if (C) or (Z) = 1
Branch if (C) or (Z) = 0
Branch unconditionally
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear + 2)
word (PC) ← (eam), (PCB) ← (eam + 2)
word (PC) ← ad24 0 – 15,
(PCB) ← ad24 16 – 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 – 15
(PCB) ← (ear) 16 – 23
word (PC) ← (eam) 0 – 15
(PCB) ← (eam) 16 – 23
word (PC) ← addr0 – 15,
(PCB) ← addr16 – 23
LH AH
I
S T N Z V C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (a), (c) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
90
Set to 3 when branch is executed, and 2 when branch is not executed.
3 × (c) + (b)
Reads (word) of the branch destination address.
W pushes to stack (word), and R reads (word) of the branch destination address.
Pushes to stack (word).
W pushes to stack (long), and R reads (long) of the branch destination address.
Pushes to stack (long).
MB90210 Series
Table 21
Mnemonic
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
CBNE
CWBNE
CWBNE
ear, #imm8, rel
eam, #imm8, rel
ear, #imm16, rel
eam, #imm16, rel
DBNZ
ear, rel
DBNZ
eam, rel
DWBNZ ear, rel
DWBNZ eam, rel
#
~
B
3 *1
4 *1
0
0
Operation
LH AH
I
S
T
N
Z
V
C RMW
Branch if word (A) ≠ imm16
Branch if byte (A) ≠ imm8
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch if byte (ear) ≠ imm8
Branch if byte (eam) ≠ imm8
Branch if word (ear) ≠ imm16
Branch if word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
byte (ear) = (ear) – 1,
Branch if (ear) ≠ 0
3 + *4 2 × (b) byte (eam) = (eam) – 1,
Branch if (eam) ≠ 0
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
word (ear) = (ear) – 1,
Branch if (ear) ≠ 0
3 + *4 2 × (c) word (eam) = (eam) – 1,
Branch if (eam) ≠ 0
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
*
S
S
S
S
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
–
–
Stores old frame pointer in
the beginning of the
function, set new frame
pointer, and reserves local
pointer area
Restore old frame pointer
from stack in the end of
the function
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
4+
5
5+
*1
*3
*1
*3
3 *2
3 *2
0
(b)
0
(c)
0
0
INT
#vct8
INT
addr16
INTP
addr24
INT9
RETI
RETIQ *6
2
3
4
1
1
2
14
12
13
14
9
11
8 × (c)
6 × (c)
6 × (c)
8 × (c)
6 × (c)
*5
LINK
2
6
(c)
UNLINK
1
5
(c)
RET *7
RETP *8
1
1
4
5
(c)
(d)
#imm8
Branch 2 [20 Instructions]
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
Set to 4 when branch is executed, and 3 when branch is not executed.
Set to 5 when branch is executed, and 4 when branch is not executed.
Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed.
Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed.
Set to 3 × (b) + 2 × (c) when an interrupt request is issued, and 6 × (c) for return.
This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an
interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector.
*7: Return from stack (word).
*8: Return from stack (long).
91
MB90210 Series
Table 22
Mnemonic
Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]
#
~
B
Operation
LH AH
I
S T N Z V C RMW
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
3
3
3
*3
(c)
(c)
(c)
*4
word (SP) ← (SP) – 2, ((SP)) ← (A) –
word (SP) ← (SP) – 2, ((SP)) ← (AH)
–
word (SP) ← (SP) – 2, ((SP)) ← (PS)
–
(PS) ← (PS) – 2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
3
*2
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) + 2
word (AH) ← ((SP)), (SP) ← (SP) + 2
word (PS) ← ((SP)), (SP) ← (SP) + 2
(rlst) ← ((SP)), (SP) ← (SP) + 2n
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
9
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
byte (CCR) ← (CCR) and imm8 –
–
byte (CCR) ← (CCR) or imm8
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
MOV
MOV
RP, #imm8
ILM, #imm8
2
2
2
2
0
0
byte (RP) ← imm8
byte (ILM) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVEA
MOVEA
MOVEA
MOVEA
RWi, ear
RWi, eam
A, ear
A, eam
0
0
0
0
word (RWi) ← ear
word (RWi) ← eam
word(A) ← ear
word (A) ← eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
2
2 + 2 + (a)
2
2
2 + 1 + (a)
6 × (c) Context switch instruction
2
3
3
3
0
0
word (SP) ← (SP) + ext (imm8) –
–
word (SP) ← (SP) + imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
A, brgl
2
brg2, A
2
brg2, #imm8 3
*1
1
2
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no change in flag
Prefix for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
CLRSPC
4
4
2
2
2
2
2
2
0
0
0
0
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
Enables stack check operation.
Disables stack check operation.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BTSCN A
BTSCNS A
BTSCND A
2
2
2
*5
*6
*7
0
0
0
Bit position of 1 in byte (A) from word (A)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
Bit position (× 2) of 1 in byte (A) from word (A)
Bit position (× 4) of 1 in byte (A) from word (A)
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB
: 2 states
DPR
: 3 states
*2: 3 + 4 × (number of POPs)
*3: 3 + 4 × (number of PUSHes)
*4: (Number of POPs) × (c), or (number of PUSHes) × (c)
*5: Set to 3 when AL is 0, 5 when AL is not 0.
*6: Set to 4 when AL is 0, 6 when AL is not 0.
*7: Set to 5 when AL is 0, 7 when AL is not 0.
92
MB90210 Series
Table 23
Mnemonic
Bit Manipulation Instruction [21 Instructions]
#
~
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC
BBC
BBC
Operation
LH AH
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
I
S T N Z V C RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2 × (b) bit (dir:bp) b ← (A)
2 × (b) bit (addr16:bp) b ← (A)
2 × (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
4
4
4
2 × (b) bit (dir:bp) b ← 1
2 × (b) bit (addr16:bp) b ← 1
2 × (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
4
4
4
2 × (b) bit (dir:bp) b ← 0
2 × (b) bit (addr16:bp) b ← 0
2 × (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch if (dir:bp) b = 0
Branch if (addr16:bp) b = 0
Branch if (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch if (dir:bp) b = 1
Branch if (addr16:bp) b = 1
Branch if (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS
addr16:bp, rel
5
*2
2 × (b) Branch if (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*3
*4
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*3
*4
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
Note: For (b), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
Set to 5 when branch is executed, and 4 when branch is not executed.
7 if conditions are met, 6 when conditions are not met.
Indeterminate times
Until conditions are met
93
MB90210 Series
Table 24
Mnemonic
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instruction (Byte, Word) [6 Instructions]
#
~
B
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
Operation
byte (A) 0 – 7 ↔ (A) 8 – 15
word (AH) ↔ (AL)
byte sign-extension
word sign-extension
byte zero-extension
word zero-extension
Table 25
Mnemonic
LH AH
I
S
T
N
Z
V
C RMW
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
I
S
T
N
Z
V
C RMW
–
–
X
–
Z
–
String Instruction [10 Instructions]
#
~
B
Operation
MOVS/MOVSI
2
*2
–
–
–
–
–
–
–
–
–
–
MOVSD
2
*2
*3 byte transfer @AH + ← @AL +,
Counter = RW0
*3 byte transfer @AH – ← @AL –,
Counter = RW0
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
2
*1
–
–
–
–
–
*
*
*
*
–
SCEQD
2
*1
*4 byte search (@AH +) – AL,
Counter = RW0
*4 byte search (@AH –) – AL,
Counter = RW0
–
–
–
–
–
*
*
*
*
–
FISL/FILSI
2 5m + 6 *5 byte fill @AH + ← AL,
Counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
2
*2
–
–
–
–
–
–
–
–
–
–
MOVSWD
2
*2
*6 word transfer @AH + ← @AL +,
Counter = RW0
*6 word transfer @AH – ← @AL –,
Counter = RW0
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
2
*1
–
–
–
–
–
*
*
*
*
–
SCWEQD
2
*1
*7 word search (@AH +) – AL,
Counter = RW0
*7 word search (@AH –) – AL,
Counter = RW0
–
–
–
–
–
*
*
*
*
–
FILSW/FILSWI
2 5m + 6 *8 word fill @AH + ← AL,
Counter = RW0
–
–
–
–
–
*
*
–
–
–
LH AH
m: RW0 value (counter value)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
94
–
–
–
–
–
–
3 when RW0 is 0, 2 + 6 × (RW0) when count out, and 6n + 4 when matched
4 when RW0 is 0, otherwise 2 + 6 × (RW0)
(b) × (RW0)
(b) × n
(b) × (RW0)
(c) × (RW0)
(c) × n
(c) × (RW0)
MB90210 Series
Table 26
Multiple Data Transfer Instructions [18 Instruction]
Mnemonic
MOVM @A, @RLi, #imm8
#
3
~
*1
MOVM @A, eam, #imm8
3+
*2
5
*1
MOVM addr16, @RLi, #imm8
MOVM addr16, @eam, #imm8 5 +
*2
MOVMW@A, @RLi, #imm8
3
*1
3+
*2
5
*1
MOVMW@A, eam, #imm8
MOVMWaddr16, @RLi, #imm8
MOVMWaddr16, @eam, #imm8 5 +
*2
MOVM @RLi, @A, #imm8
3
*1
MOVM @eam, A, #imm8
3+
*2
5
*1
MOVM @RLi, addr16, #imm8
MOVM @eam, addr16, #imm8 5 +
*2
MOVMW@RLi, @A, #imm8
3
*1
3+
*2
5
*1
MOVMW@eam, A, #imm8
MOVMW@RLi, addr16, #imm8
MOVMW@eam, addr16, #imm8 5 +
*2
MOVM bnk: addr16,
bnk: addr16, #imm8*5
7
*1
MOVMWbnk: addr16,
7
*1
bnk: addr16, #imm8*5
*1:
*2:
*3:
*4:
*5:
B
Operation
*3 Multiple data transfer
byte ((A)) ← ((RLi))
*3 Multiple data transfer
byte ((A)) ← (eam)
*3 Multiple data transfer
byte (addr16) ← ((RLi))
*3 Multiple data transfer
byte (addr16) ← (eam)
*4 Multiple data transfer
word ((A)) ← ((RLi))
*4 Multiple data transfer
word ((A)) ← (eam)
*4 Multiple data transfer
word (addr16) ← ((RLi))
*4 Multiple data transfer
word (addr16) ← (eam)
*3 Multiple data transfer
byte ((RLi)) ← ((A))
*3 Multiple data transfer
byte (eam) ← ((A))
*3 Multiple data transfer
byte ((RLi)) ← (addr16)
*3 Multiple data transfer
byte (eam) ← (addr16)
*4 Multiple data transfer
word ((RLi)) ← ((A))
*4 Multiple data transfer
word (eam) ← ((A))
*4 Multiple data transfer
word ((RLi)) ← (addr16)
*4 Multiple data transfer
word (eam) ← (addr16)
*3 Multiple data transfer
byte (bnk: addr16) ←
(bnk: addr16)
*4 Multiple data transfer
word (bnk: addr16) ←
(bnk: addr16)
–
–
I
–
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–
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LH AH
S
–
T
–
N
–
Z
–
V
–
C RMW
–
–
256 when 5 + imm8 × 5, imm8 is 0.
256 when 5 + imm8 × 5 + (a), imm8 is 0.
(Number of transfer cycles) × (b) × 2
(Number of transfer cycles) × (c) × 2
The bank register specified by bnk is the same as that for the MOVS instruction.
95
MB90210 Series
■ ORDERING INFORMATION
Part number
96
Type
Package
Remarks
MB90214
MB90P214A
MB90P214B
MB90214PF
MB90P214PF
MB90P214BPF
80-pin Plastic QFP
(FPT-80P-M06)
MB90W214A
MB90W214B
MB90W214ZF
MB90W214BZF
80-pin Ceramic QFP
(FPT-80C-C02)
Only ES level
MB90V210
MB90V210CR
256-pin Ceramic PGA
(PGA-256C-A02)
For evaluation
MB90210 Series
■ PACKAGE DIMENSIONS
80-pin Plastic QFP
(FPT-80P-M06)
3.35(.132)MAX (Mounting height)
0.05(.002)MIN
(STAND OFF)
23.90±0.40(.941±.016)
64
20.00±0.20(.787±.008)
41
65
40
14.00±0.20
(.551±.008)
12.00(.472)
REF
17.90±0.40
(.705±.016)
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
LEAD No.
1
24
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.16(.006)
0.15±0.05(.006±.002)
M
Details of "A" part
Details of "B" part
0.25(.010)
"B"
0.10(.004)
0.30(.012)
0.18(.007)MAX
18.40(.724)REF
22.30±0.40(.878±.016)
C
0 10°
0.80±0.20
(.031±.008)
0.58(.023)MAX
Dimensions in mm (inches)
1994 FUJITSU LIMITED F80010S-3C-2
80-pin Ceramic QFP
(FPT-80C-C02)
0.05(.002)MIN
(STAND OFF)
Ø8.89(.350)TYP
17.90±0.30
12.00(.472)
(.705±.012)
REF
+0.45
14.00 –0.15
+.018
.551–.006
16.30±0.25
(.642±.010)
INDEX AREA
0.80(.0315)TYP
0.35±0.10
(.014±.004)
18.40(.724) REF
0.15±0.05
(.006±.002)
1.45±0.20
(.057±.008)
+0.50
20.00 –0.20
+.020
.787 –.008
23.90±0.30
(.941±.012)
22.30±0.25
(.878±.010)
C
1994 FUJITSU LIMITED F80018SC-1-2
3.30(.130)MAX
(Mounting height)
0.80±0.20
(.0315±.008)
Dimensions in mm (inches)
97
MB90210 Series
MEMO
98
MB90210 Series
MEMO
99
MB90210 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9710
FUJITSU LIMITED Printed in Japan
10
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
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use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
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CAUTION:
Customers considering the use of our products in special
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representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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prior authorization by Japanese government should be required
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