Fujitsu MB95F114MW 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12611-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95110M series
MB95117M/F114MS/F114NS/F116MS/F116NS/
MB95F118MS/F118NS/F114MW/F114NW/F116MW/F116NW/
MB95F118MW/F118NW/FV100D-103
■ DESCRIPTION
The MB95110M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
• Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB95110M Series
(Continued)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• I2C*
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O port
• The number of maximum ports
• Single clock product : 39 ports
• Dual clock product : 37 ports
• Configuration
• General-purpose I/O ports (N-ch open drain) : 2 ports
• General-purpose I/O ports (CMOS)
: Single clock product : 37 ports
Dual clock product : 35 ports
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
2
MB95110M Series
■ MEMORY LINEUP
MB95F114MS/F114NS
MB95F114MW/F114NW
MB95F116MS/F116NS
MB95F116MW/F116NW
MB95F118MS/F118NS
MB95F118MW/F118NW
Flash memory
RAM
16 Kbytes
512 bytes
32 Kbytes
1 Kbyte
60 Kbytes
2 Kbytes
3
MB95110M Series
■ PRODUCT LINEUP
MB95117M
MB95F114MS MB95F114NS MB95F114MW MB95F114NW
MB95F116MS MB95F116NS MB95F116MW MB95F116NW
MB95F118MS MB95F118NS MB95F118MW MB95F118NW
MASK ROM product
Flash memory product
ROM capacity*
48 Kbytes
60 Kbytes (Max)
RAM capacity*1
2 Kbytes
2 Kbytes (Max)
Part number
Parameter
Type
1
Option*2
Reset output
Yes
Clock system
Selectable single/
dual clock*3
Low voltage
detection reset
Yes / No
CPU functions
Single clock
No
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
Yes
:
:
:
:
:
:
Dual clock
No
Yes
136
8 bits
1 to 3 bytes
1, 8, and 16 bits
61.5 ns (at machine clock frequency 16.25 MHz)
0.6 µs (at machine clock frequency 16.25 MHz)
Peripheral functions
• Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
General purpose I/O • Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports)
ports
Programmable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input level
Timebase timer
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
I2C
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate
generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
(Continued)
4
MB95110M Series
(Continued)
Part number
MB95117M
Parameter
LIN-UART
MB95F114MS MB95F114NS MB95F114MW MB95F114NW
MB95F116MS MB95F116NS MB95F116MW MB95F116NW
MB95F118MS MB95F118NS MB95F118MW MB95F118NW
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer
capable.
LIN functions available as the LIN master or LIN slave.
Peripheral functions
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(8 channels)
8/16-bit compound
timer (2 channels)
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer
× 1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
waveform output
Count clock : 7 internal clocks and external clock can be selected
16-bit PPG
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Watch counter
Counter value can be set from 0 to 63. (Capable of counting for 1minute when
(for dual clock product)
selecting clock source 1 second and setting counter value to 60)
Watch prescaler
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
(for dual clock product)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded AlgorithmTM *4
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch (for dual clock product) , and timebase timer
*1 : For ROM capacity and RAM capacity, refer to “1. Memory space” in “■ CPU CORE”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of the evaluation device in MB95110M series is MB95FV100D-103. When using it, the MCU
board (MB2146-303A) is required.
5
MB95110M Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
Remarks
(2 −2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95117M
Package
FPT-52P-M01
BGA-224P-M08
: Available
: Unavailable
6
MB95F114MS/F114NS MB95F114MW/F114NW
MB95F116MS/F116NS MB95F116MW/F116NW MB95FV100D-103
MB95F118MS/F118NS MB95F118MW/F118NW
MB95110M Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95110M series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95110M series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or write unexpectedly) .
Note that the values read from barred addresses are different between the Evaluation product and the Flash
memory or MASK ROM product. Therefore, the data must not be used for software processing.
The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardware malfunctions. Since the Evaluation, Flash memory, and MASK ROM products
are designed to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
• The current consumption of Flash memory product is typically greater than for MASK ROM product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGE AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating Voltage
The operating voltage are different among the Evaluation, Flash memory, and MASK ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
• Difference between RST and MOD Pins
The input type of RST and MOD pins is CMOS inputs on the Flash memory product.
The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull-down resistor is provided for
the MOD pin of the MASK ROM product.
7
MB95110M Series
■ PIN ASSIGNMENTS
P63/TO11
P62/TO10
P61/PPG11
P60/PPG10
P15
NC
P14/PPG0
P13/TRG0/ADTG
P12/UCK0
P11/UO0
P10/UI0
52
51
50
49
48
47
46
45
44
43
42
41 40
P07/INT07
P64/EC1
(TOP VIEW)
P37/AN07
4
36
P03/INT03
P36/AN06
5
35
P02/INT02
P35/AN05
6
34
P01/INT01
NC
7
33
NC
P34/AN04
8
32
P00/INT00
P33/AN03
9
31
RST
P32/AN02
10
30
PG1/X0A*
P31/AN01
11
29
PG2/X1A*
P30/AN00
12
28
C
AVss
13
27
Vcc
15
16
17
18
19
20
21
22
23
24
25 26
X1
14
Vss
P04/INT04
X0
37
MOD
3
P50/SCL0
P67/SIN
P51/SDA0
P05/INT05
NC
38
P20/PPG00
2
P21/PPG01
P66/SOT
P22/TO00
P06/INT06
P23/TO01
39
P24/EC0
1
AVcc
P65/SCK
(FPT-52P-M01)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
8
MB95110M Series
■ PIN DESCRIPTION
Pin no.
Pin name
1
P65/SCK
I/O
Circuit
type*
K
2
P66/SOT
3
P67/SIN
4
P37/AN07
5
P36/AN06
6
P35/AN05
8
P34/AN04
9
P33/AN03
10
P32/AN02
11
P31/AN01
12
P30/AN00
13
Function
General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
General-purpose I/O port.
The pin is shared with LIN-UART data output.
L
General-purpose I/O port.
The pin is shared with LIN-UART data input.
J
General-purpose I/O port.
The pins are shared with A/D converter analog input.
AVss
⎯
A/D converter power supply pin (GND)
14
AVcc
⎯
A/D converter power supply pin
15
P24/EC0
16
P23/TO01
17
P22/TO00
18
P21/PPG01
19
P20/PPG00
21
P51/SDA0
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input.
H
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.0 output.
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.0 output.
I
General-purpose I/O port.
The pin is shared with I2C ch.0 data I/O.
General-purpose I/O port.
The pin is shared with I2C ch.0 clock I/O.
22
P50/SCL0
23
MOD
24
X0
25
X1
26
Vss
⎯
Power supply pin (GND)
27
Vcc
⎯
Power supply pin
28
C
⎯
Capacitor connection pin
29
PG2/X1A
B
A
H/A
30
PG1/X0A
31
RST
B’
Operating mode designation pin
Main clock oscillation input pin
Main clock oscillation I/O pin
Single clock product is general-purpose port (PG2).
Dual clock product is sub clock I/O oscillation pin (32 kHz).
Single clock product is general-purpose port (PG1).
Dual clock product is sub clock input oscillation pin (32 kHz).
Reset pin
(Continued)
9
MB95110M Series
(Continued)
Pin no.
Pin name
32
P00/INT00
34
P01/INT01
35
P02/INT02
36
P03/INT03
37
P04/INT04
38
P05/INT05
39
P06/INT06
40
P07/INT07
41
P10/UI0
42
P11/UO0
43
P12/UCK0
44
P13/TRG0/
ADTG
45
P14/PPG0
47
P15
48
P60/PPG10
49
P61/PPG11
50
P62/TO10
51
P63/TO11
52
P64/EC1
7, 20, 33, 46
NC
I/O
Circuit
type*
Function
C
General-purpose I/O port.
The pins are shared with external interrupt input. Large current port.
G
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D trigger input (ADTG).
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
General-purpose I/O port.
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.1 output.
K
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.1 output.
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.1 clock input.
⎯
Internal connect pin.
Be sure this pin is left open.
*: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”
10
MB95110M Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1 (X1A)
Remarks
Clock input
A
N-ch
X0 (X0A)
Standby control
Mode input
B
R
Reset input
B’
N-ch
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
Dumping resistance : approx. 144 MΩ)
(Evaluation product : without dumping
resistance)
• Only for input
Hysteresis input only for MASK ROM
product
With pull-down resistor only for MASK
ROM
product
• Reset output
• Hysteresis input
Reset output
P-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Automotive input
N-ch
C
Hysteresis input
Automotive input
Standby control
External interrupt
enable
Pull-up control
R
P-ch
P-ch
G
N-ch
Digital output
•
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
Automotive input
Digital output
CMOS input
Hysteresis input
Standby control
Automotive input
(Continued)
11
MB95110M Series
Type
Circuit
Remarks
Pull-up control
R
P-ch
P-ch
H
Digital output
•
•
•
•
CMOS output
Hysteresis input
With pull-up control
Automotive input
•
•
•
•
N-ch open drain output
CMOS input
Hysteresis input
Automotive input
•
•
•
•
•
CMOS output
Hysteresis input
Analog input
With pull-up control
Automotive input
Digital output
N-ch
Hysteresis input
Automotive input
Standby control
N-ch
I
Digital output
CMOS input
Hysteresis input
Automotive input
Standby control
R
P-ch
Pull-up control
P-ch
N-ch
J
Digital output
Digital output
Analog input
Hysteresis input
A/D control
Standby control
Automotive input
P-ch
N-ch
K
Digital output
• CMOS output
• Hysteresis input
• Automotive input
Digital output
Hysteresis input
Standby control
Automotive input
(Continued)
12
MB95110M Series
(Continued)
Type
Circuit
P-ch
N-ch
L
Remarks
Digital output
Digital output
•
•
•
•
CMOS output
CMOS input
Hysteresis input
Automotive input
CMOS input
Hysteresis input
Standby control
Automotive input
13
MB95110M Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
14
MB95110M Series
■ PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
• Mode Pin (MOD)
Connect the mode pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection.
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
CS
• NC Pins
Any pins marked “NC” (not connected) must be left open.
• Analog Power Supply
Always set the same potential to AVCC and VCC. When VCC > AVCC, the current may flow through the AN00 to
AN07 pins.
15
MB95110M Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-52P-M01
TEF110-95118PMC
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
• MB95F118MS/F118NS/F118MW/F118NW (60 Kbytes)
Flash memory
CPU address
1000H
Programmer address*
71000H
1FFFH
2000H
71FFFH
72000H
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA2 (4Kbytes)
Lower bank
SA1 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
Upper bank
SA5 (16 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
16
MB95110M Series
• MB95F116MS/F116NS/F116MW/F116NW (32 Kbytes)
Flash memory
CPU address
8000H
Programmer address*
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA5 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• MB95F114MS/F114NS/F114MW/F114NW (16 Kbytes)
Flash memory
CPU address
C000H
Programmer address*
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to “17222”.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
17
MB95110M Series
■ BLOCK DIAGRAM
2
F MC-8FX CPU
RST
X0,X1
PG2/X1A*
PG1/X0A*
Reset control
ROM
RAM
Clock control
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt
8/16-bit PPG ch.1
P10/UI0
UART/SIO
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
16-bit PPG
P15
P20/PPG00
P21/PPG01
8/16-bit PPG ch.0
P22/TO00
P23/TO01
P24/EC0
8/16-bit compound
timer ch.0
P30/AN00 to P37/AN07
AVCC
AVSS
P50/SCL0
P51/SDA0
P62/TO10
Internal bus
P11/UO0
P60/PPG10
P61/PPG11
8/16-bit compound
timer ch.1
P63/TO11
P64/EC1
P65/SCK
LIN-UART
P66/SOT
P67/SIN
8/10-bit
A/D converter
I 2C
Port
Port
Other pins
MOD, VCC, VSS, C, NC
* : Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin.
18
MB95110M Series
■ CPU CORE
1. Memory space
Memory space of the MB95110M series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95110M series is shown below.
• Memory Map
MB95F114MS/F114NS
MB95F114MW/F114NW
MB95F116MS/F116NS
MB95F116MW/F116NW
MB95F118MS/F118NS
MB95F118MW/F118NW
MB95117M
0000H
0000H
0080H
0100H
RAM 2 Kbytes
0080H
I/O
RAM 2 Kbytes
0100H Register
0200H
Register
0200H
0880H
0000H
I/O
I/O
Access
prohibited
0F80H
Address #1
RAM 3.75 Kbytes
Access
prohibited
0F80H
Expanded I/O
Address #2
1000H
0080H
0100H Register
0200H
0F80H
Expanded I/O
MB95FV100D-103
Expanded I/O
1000H
Access
prohibited
Flash memory
60 Kbytes
Flash memory
4000H
MASK ROM
48 Kbytes
FFFFH
MB95F114MS/F114NS
MB95F114MW/F114NW
MB95F116MS/F116NS
MB95F116MW/F116NW
MB95F118MS/F118NS
MB95F118MW/F118NW
FFFFH
FFFFH
Flash memory
RAM
Address #1
Address #2
16 Kbytes
512 bytes
0280H
C000H
32 Kbytes
1 Kbyte
0480H
8000H
60 Kbytes
2 Kbytes
0880H
1000H
19
MB95110M Series
2. Register
The MB95110M series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
: A 16-bit register for index modification.
Extra pointer (EP)
: A 16-bit pointer to point to a memory address.
Stack pointer (SP)
: A 16-bit register to indicate a stack area.
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register.
Initial Value
16-bit
: Program counter
FFFDH
A
: Accumulator
0000H
T
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
PC
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the program status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PS
R4
R3
R2
RP
20
R1
R0
DP2
DP1
DP
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DP0
H
I
IL1
IL0
N
Z
V
C
CCR
MB95110M Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
"0"
"0"
"0"
"0"
"0"
"0"
OP code lower
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
N flag
Z flag
V flag
C flag
Low = no interruption
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB95110M Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains
8-register. Up to a total of 32 banks can be used on the MB95110M series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
107H
R6
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
22
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
MB95110M Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
⎯
(Disabled)
⎯
⎯
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
PDR3
Port 3 data register
R/W
00000000B
0011H
DDR3
Port 3 direction register
R/W
00000000B
0012H,
0013H
⎯
(Disabled)
⎯
⎯
0014H
PDR5
Port 5 data register
R/W
00000000B
0015H
DDR5
Port 5 direction register
R/W
00000000B
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0029H
⎯
(Disabled)
⎯
⎯
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
⎯
(Disabled)
⎯
⎯
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
002FH
PUL3
Port 3 pull-up register
R/W
00000000B
0030H
to
0034H
⎯
(Disabled)
⎯
⎯
(Continued)
23
MB95110M Series
Address
Register
abbreviation
Register name
R/W
Initial value
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG status control register (Upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register (Lower byte) ch.0
R/W
00000000B
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/7
R/W
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
(Continued)
24
MB95110M Series
Address
Register
abbreviation
Register name
R/W
Initial value
0060H
IBCR00
I2C bus control register 0 ch.0
R/W
00000000B
2
0061H
IBCR10
I C bus control register 1 ch.0
R/W
00000000B
0062H
IBSR0
I2C bus status register ch.0
R
00000000B
0063H
IDDR0
I2C data register ch.0
R/W
00000000B
I C address register ch.0
R/W
00000000B
0064H
2
IAAR0
2
0065H
ICCR0
I C clock control register ch.0
R/W
00000000B
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
(Mirror of register bank pointer (RP) and direct bank
pointer (DP) )
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (Upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
(Continued)
25
MB95110M Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F86H
WRARH2
Wild register address setting register (Upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control
register ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control
register ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG starting register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (Upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (Lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (Upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (Lower byte) ch.0
R/W
11111111B
(Continued)
26
MB95110M Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
0FC3H
AIDRL
A/D input disable register (Lower byte)
R/W
00000000B
0FC4H
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FE6H
⎯
(Disabled)
⎯
⎯
0FE7H
ILSR2
Input level select register 2
R/W
00000000B
0FE8H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
27
MB95110M Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
I2C ch.0
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch timer/counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
28
Interrupt
request
number
High
Low
MB95110M Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
Vcc
AVcc
Vss − 0.3
Vss + 6.0
V
*2
VI
Vss − 0.3
Vss + 6.0
V
*3
VO
Vss − 0.3
Vss + 6.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL1
IOL2
“L” level average
current
⎯
“H” level maximum
output current
mA
mA
12
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
“H” level average
current
⎯
− 15
− 15
mA
−4
⎯
mA
−8
IOHAV2
“H” level total average
output current
15
⎯
IOHAV1
“H” level total maximum
output current
15
4
IOLAV2
“L” level total average
output current
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
(Continued)
29
MB95110M Series
(Continued)
Parameter
Rating
Symbol
Min
Max
Unit
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
Storage temperature
Remarks
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc.
*3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, P60 to P67
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
MB95110M Series
2. Recommended Operating Conditions
(AVss = Vss = 0.0 V)
Parameter
Power supply
voltage
Symbol
VCC,
AVCC
⎯
Conditions
Value
Unit
Remarks
Min
Max
2.5*1
5.5
V
In normal
operation
2.3
5.5
V
Hold
condition in
STOP mode
2.7
5.5
V
In normal
operation
⎯
Other than
MB95FV100D103
2.3
5.5
V
MB95FV100DHold
103
condition in
STOP mode
VIH1
P10, P67
*2
0.7 Vcc
Vcc + 0.3
V
At selecting of CMOS input
level
VIH2
P50, P51
*2
0.7 Vcc
Vss + 5.5
V
At selecting of CMOS input
level
⎯
0.8 Vcc
Vcc + 0.3
V
Pin input at selecting of
AUTOMOTIVE input level
VIHS1
P00 to P07,
P10 to P15,
P20 to P24,
P30 to P37,
P60 to P67,
PG1*3,
PG2*3
*2
0.8 Vcc
Vcc + 0.3
V
Hysteresis input
VIHS2
P50, P51
*2
0.8 Vcc
Vss + 5.5
V
Hysteresis input
⎯
0.7 Vcc
Vcc + 0.3
V
CMOS input
(Flash memory product)
⎯
0.8 Vcc
Vcc + 0.3
V
Hysteresis input
(MASK ROM product)
VIHA
“H” level input
voltage
Pin name
VIHM
⎯
RST, MOD
(Continued)
31
MB95110M Series
(Continued)
Parameter
(AVss = Vss = 0.0 V)
Symbol
VIL
“L” level input
voltage
Pin name
P10, P50,
P51, P67
Value
Conditions
Min
Max
*2
Vss − 0.3
0.3 Vcc
V
At selecting of CMOS input
level
Unit
Remarks
VILA
⎯
⎯
Vss − 0.3
0.5 Vcc
V
Pin input at selecting of
AUTOMOTIVE input level
VILS
P00 to P07,
P10 to P15,
P20 to P24,
P30 to P37,
P50, P51,
P60 to P67,
PG1*3,
PG2*3
*2
Vss − 0.3
0.2 Vcc
V
Hysteresis input
⎯
Vss − 0.3
0.3 Vcc
V
CMOS input
(Flash memory product)
⎯
Vss − 0.3
0.2 Vcc
V
Hysteresis input
(MASK ROM product)
0.1
1.0
µF
*4
− 40
+ 85
°C Other than MB95FV100D-103
+5
+ 35
°C
VILM
RST, MOD
Smoothing
capacitor
CS
⎯
⎯
Operating
temperature
TA
⎯
⎯
MB95FV100D-103
*1 : The value is 2.9 V when the low voltage detection reset is used.
*2 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*3 : Single clock products only
*4 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC
pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the
diagram below.
• C pin connection diagram
C
CS
32
MB95110M Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
33
MB95110M Series
3. DC Characteristics
Parameter
“H” level output
voltage
“L” level output
voltage
Open-drain output application
voltage
Input leakage
current (Hi-Z
output leakage
current)
Open-drain
output leakage
current
Symbol
Pin name
Output pin
VOH1 other than
P00 to P07
VOH2 P00 to P07
Output pin
VOL1 other than
P00 to P07
VOL2 P00 to P07
(Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Conditions
Unit
Remarks
Min
Typ
Max
IOH = − 4.0 mA
VCC − 0.5
⎯
⎯
V
IOH = − 8.0 mA
VCC − 0.5
⎯
⎯
V
IOL = 4.0 mA
⎯
⎯
0.4
V
IOL = 12 mA
⎯
⎯
0.4
V
Vss − 0.3
⎯
Vss + 5.5
V
−5
⎯
+5
µA
⎯
⎯
5
µA
25
50
100
kΩ
25
50
100
kΩ
⎯
9.5
12.5
mA
⎯
30
35
mA
⎯
7.2
9.5
mA
⎯
15.2
20.0
mA
⎯
35.7
42.5
mA
⎯
11.6
15.2
mA
⎯
VD
P50, P51
ILI
Port other
0.0 V < VI < Vcc
than P50, P51
ILIOD P50, P51
0.0 V < VI < Vss +
5.5 V
P10 to P15,
P20 to P24,
VI = 0.0 V
P30 to P37,
1
1
PG1* , PG2*
Pull-up resistor
RPULL
Pull-down
resistor
RMOD MOD
VI = Vcc
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
Power supply
current*2
ICC
Vcc
(External
clock
operation)
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
When the pull-up
prohibition setting
When the pull-up
permission setting
MASK ROM
product
Flash memory
product (at other
than Flash memory
writing and
erasing)
Flash memory
product (at Flash
memory writing and
erasing)
MASK ROM
product
Flash memory
product (at other
than Flash memory
writing and
erasing)
Flash memory
product (at Flash
memory writing and
erasing)
MASK ROM
product
(Continued)
34
MB95110M Series
(Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Typ
Max
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main sleep mode
(divided by 2)
⎯
4.5
7.5
mA
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
⎯
7.2
12.0
mA
ICCL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
⎯
45
100
µA
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
10
81
µA
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
4.6
27
µA
⎯
9.3
12.5
mA
Flash memory
product
⎯
7.0
9.5
mA
MASK ROM
product
⎯
14.9
20.0
mA
Flash memory
product
⎯
11.2
15.2
mA
MASK ROM
product
ICCS
Power
supply
current*2
Conditions
ICCT
ICCMPLL
VCC
(External clock
operation) *2
VCC = 5.5 V
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by
2.5)
VCC = 5.5 V
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by
2.5)
(Continued)
35
MB95110M Series
(Continued)
Parameter
(Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
ICCSPLL
ICTS
Power
supply
current*2
VCC
(External clock
operation) *2
ICCH
ILVD
VCC
IA
AVcc
IAH
Input
capacitance
CIN
Conditions
Value
Unit
Min
Typ
Max
VCC = 5.5 V
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4)
TA = + 25 °C
⎯
160
400
µA
VCC = 5.5 V
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
⎯
0.15
1.10
mA
VCC = 5.5 V
FCH = 16 MHz
Timebase timer mode
TA = + 25 °C
⎯
0.24
1.76
mA
VCC = 5.5 V
Sub stop mode
TA = + 25 °C
⎯
5
20
µA
Current consumption for
low voltage detection
circuit only
⎯
38
50
µA
VCC = 5.5 V
FCH = 16 MHz
At operating of A/D
conversion
⎯
2.4
4.7
mA
VCC = 5.5 V
FCH = 16 MHz
At stopping A/D
conversion
TA = + 25 °C
⎯
1
5
µA
⎯
5
15
pF
Other than AVcc,
f = 1 MHz
AVss, Vcc, Vss
Remarks
Main stop
mode for single
clock product
*1 : Single clock product only
*2 : • The power-supply current is determined by the external clock. When both low voltage detection option is
selected, the power-supply current will be a value of adding current consumption of the low voltage detection
circuit (ILVD) to the specified value.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
36
MB95110M Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 2.5 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
SymCondiPin name
bol
tions
FCH
X0, X1
Clock frequency
FCL
Value
Unit
Remarks
16.25
MHz
When using main
oscillation circuit
⎯
32.50
MHz When using external clock
3.00
⎯
16.25
MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
⎯
32.768
⎯
kHz
When using sub
oscillation circuit
⎯
32.768
⎯
kHz
When using sub PLL
VCC = 2.3 V to 3.6 V
61.5
⎯
1000
ns
When using main
oscillation circuit
30.8
⎯
1000
ns
When using external clock
Min
Typ
Max
1.00
⎯
1.00
X0A, X1A
⎯
tHCYL
X0, X1
Clock cycle time
Input clock pulse width
Input clock rise time and
fall time
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
When using sub oscillation
circuit
tWH1
tWL1
X0
61.5
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0, X0A
⎯
⎯
5
ns
When using external clock
37
MB95110M Series
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0A
X1A
FCL
X0A
X1A
Open
FCL
38
MB95110M Series
(2) Source Clock/Machine Clock
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Sym- Pin
bol name
Parameter
Source clock cycle
time*1
(Clock before setting
division)
Source clock frequency
Machine clock cycle
time*2
(Minimum instruction
execution time)
Machine clock
frequency
tSCLK
Value
Unit
Remarks
Min
Typ
Max
61.5
⎯
2000
When using main clock
ns Min : FCH = 16.25 MHz, PLL multiplied by 1
Max : FCH = 1 MHz, divided by 2
7.6
⎯
61.0
When using sub clock
µs Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
16.25
⎯
FSP
⎯
0.50
⎯
FSPL
⎯
16.384
⎯
61.5
⎯
32000
When using main clock
ns Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
⎯
976.5
When using sub clock
µs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
0.031
⎯
16.250 MHz When using main clock
1.024
⎯
131.072 kHz When using sub clock
tMCLK
FMP
FMPL
131.072 kHz When using sub clock
⎯
⎯
MHz When using main clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
FCH
(main oscillation)
Devided by 2
Main PLL
×1
×2
× 2.5
SCLK
( source clock )
FCL
(sub oscillation)
Devided by 2
Sub PLL
×2
×3
×4
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
39
MB95110M Series
• Operating voltage − Operating frequency (TA = − 40 °C to + 85 °C)
• MB95F114MS/F114NS/F116MS/F116NS/F118MS/F118NS/F114MW/F114NW/F116MW/F116NW/F118MW/F118 NW
Main clock mode, main PLL mode,
operating guarantee range
5.5
Operating voltage (V)
Operating voltage (V)
Sub PLL operating guarantee range
Sub clock mode, watch mode,
operating guarantee range
2.45
32 kHz
16.384 kHz
5.5
3.5
2.45
0.5 MHz 3 MHz
131.072 kHz
10 MHz
16.25 MHz
PLL operating guarantee range
Main clock operating guarantee range
PLL operating guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• Operating voltage − Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-103
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
Operating voltage (V)
Operating voltage (V)
5.5
2.7
16.384 kHz
32 kHz
131.072 kHz
3.5
2.7
0.5MHz 3 MHz
10 MHz
PLL operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
• Main PLL operation frequency
10 MHz
Source clock frequency (FSP)
9 MHz
8 MHz
7.5 MHz
× 2.5
×2
7 MHz
6 MHz
×1
5 MHz
4 MHz
3 MHz
3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz
Main clock frequency (FMP)
40
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
MB95110M Series
(3) External Reset
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
RST “L” level
pulse width
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operating
Oscillation time of oscillator*2
+ 100
⎯
µs
At stop mode, sub clock mode,
sub sleep mode, and watch mode
100
⎯
µs
At timebase timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, and watch mode, and power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 µs
Oscillation time
Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
41
MB95110M Series
(4) Power-on Reset
(AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
⎯
⎯
50
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold condition in STOP mode
VSS
42
MB95110M Series
(5) Peripheral Input Timing
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Peripheral input “H” pulse
width
tILIH
Peripheral input “L” pulse
width
tIHIL
Value
Pin name
INT00 to INT07,
EC0, EC1, TRG0/ADTG
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
Remarks
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1, TRG0/ADTG
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
43
MB95110M Series
(6) UART/SIO, Serial I/O Timing
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Serial clock “H” pulse width
tSHSL
UCK0
Serial clock “L” pulse width
tSLSH
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Value
Max
Internal
clock
operation
Output pin:
CL = 80 pF
+ 1TTL.
4 tMCLK*
⎯
ns
− 190
+ 190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
External
clock
operation
Output pin:
CL = 80 pF
+ 1TTL.
4 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
⎯
190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
tIVSH
UI0
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
44
Unit
Min
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Remarks
MB95110M Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SymPin name
bol
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
SCK
Max
5 tMCLK*3
⎯
ns
+ 95
ns
⎯
ns
⎯
ns
* − tR
⎯
ns
* + 95
⎯
ns
⎯
2 tMCLK*3 + 95
ns
190
⎯
ns
* + 95
⎯
ns
MCLK 3
SCK
3t
MCLK 3
SCK
tSHSL
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
Valid SIN → SCK ↑
tIVSHE
SCK, SIN
t
External clock
operation output pin :
CL = 80 pF + 1 TTL.
Unit
Min
Internal clock
SCK, SOT
−95
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190
SCK, SIN
0
Serial clock “H” pulse width
SCK ↑ → valid SIN hold time
Value
Conditions
MCLK 3
tSHIXE
SCK, SIN
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
45
MB95110M Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tF
SOT
tSHSL
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
46
0.8 VCC
MB95110M Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Pin name
tSCYC
SCK
tSHOVI
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
Value
Conditions
Internal clock
SCK, SOT
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
SCK
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
t
* + 190
MCLK 3
MCLK 3
SCK
Unit
Min
t
SCK ↑ → SOT delay time
tSHOVE
SCK, SOT
Valid SIN → SCK ↓
tIVSLE
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXE
SCK, SIN
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
External clock
operation output pin :
CL = 80 pF + 1 TTL.
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
47
MB95110M Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
48
0.2 VCC
MB95110M Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Value
Conditions
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
49
MB95110M Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operating output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
SIN
50
tSLOVI
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
MB95110M Series
(8) I2C Timing
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin
name
Conditions
Standardmode
Fast-mode Unit Remarks
Min
Max
Min
Max
fSCL
SCL0
0
100
0
400
kHz
tHD;STA
SCL0
SDA0
4.0
⎯
0.6
⎯
µs
SCL clock “L” width
tLOW
SCL0
4.7
⎯
1.3
⎯
µs
SCL clock “H” width
tHIGH
SCL0
4.0
⎯
0.6
⎯
µs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA
SCL0
SDA0
4.7
⎯
0.6
⎯
µs
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
0
3.45*2
0
0.9*3
µs
Data setup time SDA ↓ ↑ → SCL ↑
tSU;DAT
SCL0
SDA0
0.25
⎯
0.1
⎯
µs
Stop condition setup time SCL ↑ →
SDA ↑
tSU;STO
SCL0
SDA0
4
⎯
0.6
⎯
µs
tBUF
SCL0
SDA0
4.7
⎯
1.3
⎯
µs
SCL clock frequency
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
SCL0 C = 50 pF*1
SDA0
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
tSU;DAT
tSU;STA
tSU;STO
51
MB95110M Series
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Sym- Pin
Condition
bol name
Value*2
Min
Max
Unit
Remarks
SCL clock “L” width
tLOW
SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns
Master mode
SCL clock “H” width
tHIGH
SCL0
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns
Master mode
ns
Master mode
Maximum value is
applied when m, n = 1, 8.
Otherwise, the minimum
value is applied.
Start condition hold
time
tHD;STA
SCL0
SDA0
(−1 + nm / 2) tMCLK − 20
Stop condition setup
time
tSU;STO
SCL0
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition setup
time
tSU;STA
SCL0
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Bus free time between
stop condition and
start condition
tBUF
SCL0
SDA0
(2 nm + 4) tMCLK − 20
⎯
ns
tHD;DAT
SCL0
SDA0
3 tMCLK − 20
⎯
ns
Master mode
ns
Master mode
When assuming that “L”
of SCL is not extended,
the minimum value is
applied to first bit of
continuous data.
Otherwise, the maximum
value is applied.
Data hold time
Data setup time
tSU;DAT
SCL0
SDA0
(−1 + nm) tMCLK + 20
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
R = 1.7 kΩ,
C = 50 pF*1
Setup time between
clearing interrupt and tSU;INT SCL0
SCL rising
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Minimum value is
applied to interrupt at 9th
SCL↓.
Maximum value is
applied to interrupt at 8th
SCL↓.
SCL clock “L” width
tLOW
SCL0
4 tMCLK − 20
⎯
ns
At reception
SCL clock “H” width
tHIGH
SCL0
4 tMCLK − 20
⎯
ns
At reception
Start condition
detection
tHD;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK
is used at reception
Stop condition
detection
tSU;STO
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK
is used at reception
Restart condition
detection condition
tSU;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK
is used at reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW − 3 tMCLK − 20
⎯
ns
At slave transmission
mode
(Continued)
52
MB95110M Series
(Continued)
Parameter
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Value*2
Sym- Pin
Condition
bol name
Data hold time
tHD;DAT
SCL0
SDA0
Data setup time
tSU;DAT
SCL0
R = 1.7 kΩ,
SDA0
C = 50 pF*1
SDA↓→SCL↑
(at wake-up function)
tWAKEUP
SCL0
SDA0
Unit
Remarks
Min
Max
0
⎯
ns
At reception
tMCLK − 20
⎯
ns
At reception
Oscillation stabilization
wait time
+ 2 tMCLK − 20
⎯
ns
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
53
MB95110M Series
(9) Low Voltage Detection
(AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Release voltage
VDL+
2.55
2.70
2.85
V
At power-supply rise
Detection voltage
VDL-
2.45
2.60
2.75
V
At power-supply fall
Hysteresis width
VHYS
70
100
⎯
mV
Power-supply start voltage
Voff
⎯
⎯
2.3
V
Power-supply end voltage
Von
4.9
⎯
⎯
V
0.3
⎯
⎯
µs
Slope of power supply that reset release
signal generates
⎯
3000
⎯
µs
Slope of power supply that reset release
signal generates within rating (VDL+)
300
⎯
⎯
µs
Slope of power supply that reset
detection signal generates
⎯
300
⎯
µs
Slope of power supply that reset
detection signal generates within rating
(VDL-)
Power-supply voltage
change time
(at power supply rise)
tr
Power-supply voltage
change time
(at power supply fall)
tf
Reset release delay time
td1
⎯
⎯
400
µs
Reset detection delay time
td2
⎯
⎯
30
µs
Current consumption
ILVD
⎯
38
50
µA
Current consumption for low voltage
detection circuit only
VCC
Von
Voff
time
VCC
tr
tf
VDL+
VHYS
VDL-
Internal reset signal
td2
54
td1
MB95110M Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Resolution
Total error
Linearity error
⎯
Differential linear error
Value
Unit
Min
Typ
Max
⎯
⎯
10
bit
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Remarks
Zero transition voltage
VOT
AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB
V
Full-scale transition
voltage
VFST
AVcc − 3.5 LSB AVcc − 1.5 LSB AVcc + 0.5 LSB
V
0.9
⎯
16500
µs
4.5 V ≤ AVcc ≤ 5.5 V
1.8
⎯
16500
µs
4.0 V ≤ AVcc < 4.5 V
0.6
⎯
∞
µs
4.5 V ≤ AVcc ≤ 5.5 V,
At external impedance <
5.4 kΩ
1.2
⎯
∞
µs
4.0 V ≤ AVcc < 4.5 V,
At external impedance <
2.4 kΩ
Compare time
Sampling time
⎯
⎯
Analog input current
IAIN
−0.3
⎯
+ 0.3
µA
Analog input voltage
VAIN
AVss
⎯
AVcc
V
⎯
AVss + 4.0
⎯
AVcc
V
AVcc pin
IR
⎯
600
900
µA
AVcc pin,
During A/D operation
IRH
⎯
⎯
5
µA
AVcc pin,
At stop mode
Reference voltage
Reference voltage
supply current
55
MB95110M Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision, Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc < 4.5 V
R
2.0 kΩ (Max)
8.2 kΩ (Max)
C
16 pF (Max)
16 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
10
0
AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
0
2
4
6
8
10
12
Minimum sampling time [µs]
14
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
20
18
16
14
12
10
8
6
4
2
0
AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
0
1
3
Minimum sampling time [µs]
• About errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
56
2
4
MB95110M Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVCC
AVSS
Analog input
1 LSB =
AVcc − AVss
1024
AVCC
Analog input
(V)
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
57
MB95110M Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004H
3FFH
Digital output
Digital output
Actual conversion
characteristic
003H
Ideal
characteristics
002H
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
N+1
3FEH
{1 LSB × N + VOT}
3FDH
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
003H
Digital output
Digital output
Ideal characteristics
Actual conversion
characteristic
N
N-1
Actual conversion
characteristic
N-2
001H
VOT (measurement value)
AVSS
Analog input
Linearity error in = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
AVCC
AVSS
Analog input
Differential linear error =
in digital output N
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVCC − 1.5 LSB [V]
58
VNT
Ideal characteristics
002H
V (N+1)T
V (N + 1) T − VNT
1 LSB
AVCC
−1
MB95110M Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
0.5*2
s
Excludes 00H programming prior erasure.
0.5*1
7.5*2
s
Excludes 00H programming prior erasure.
⎯
32
3600
µs
Excludes system-level overhead.
10000
⎯
⎯
cycle
Power supply voltage at
program/erase
4.5
⎯
5.5
V
Flash memory data retention
time
20*3
⎯
⎯
year
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2*1
Sector erase time
(16 Kbytes sector)
⎯
Byte programming time
Program/erase cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
59
MB95110M Series
■ MASK OPTION
Part number
No.
Specifying
procedure
MB95F114MS/F114NS MB95F114MW/F114NW
MB95117M MB95F116MS/F116NS MB95F116MW/F116NW
MB95F118MS/F118NS MB95F118MW/F118NW
MB95FV100D-103
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
1
Clock mode
select
• Single-system
clock mode
• Dual-system
clock mode
Specify
when
ordering
MASK
Single-system
clock mode
Dual-system
clock mode
Changing by the
switch on MCU board
2
Low voltage
detection reset*
• With low voltage
detection reset
• Without low
voltage
detection reset
Specify
when
ordering
MASK
Specified by
part number
Specified by
part number
Changing by the
switch on MCU board
3
Oscillation
stabilization
wait time
Fixed to oscillation
stabilization wait time of
(214−2) /FCH
Fixed to oscillation
stabilization wait time
of (214−2) /FCH
Fixed to
oscillation
Fixed to oscillation
stabilization stabilization wait time of
wait time of
(214−2) /FCH
(214−2) /FCH
* : Refer to table below about clock mode select, low voltage detection reset and reset output.
60
MB95110M Series
Part number
Clock mode select
Single-system
MB95117M
Dual-system
Low voltage
detection reset
No
Yes
No
Yes
MB95F114MS
No
MB95F114NS
Yes
MB95F116MS
MB95F116NS
Single-system
No
Yes
MB95F118MS
No
MB95F118NS
Yes
MB95F114MW
No
MB95F114NW
Yes
MB95F116MW
MB95F116NW
Dual-system
No
Yes
MB95F118MW
No
MB95F118NW
Yes
No
Single-system
Yes
Yes
MB95FV100D-103
No
Dual-system
Yes
Yes
61
MB95110M Series
■ ORDERING INFORMATION
Part number
Package
MB95117MPMC
MB95F114MSPMC
MB95F114NSPMC
MB95F116MSPMC
MB95F116NSPMC
MB95F118MSPMC
MB95F118NSPMC
MB95F114MWPMC
MB95F114NWPMC
MB95F116MWPMC
MB95F116NWPMC
MB95F118MWPMC
MB95F118NWPMC
MB2146-303A
(MB95FV100D-103PBT)
62
Remarks
52-pin plastic LQFP
(FPT-52P-M01)
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
(
)
MB95110M Series
■ PACKAGE DIMENSION
52-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Code
(Reference)
P-LQFP52-10×10-0.65
(FPT-52P-M01)
52-pin plastic LQFP
(FPT-52P-M01)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
39
27
40
26
Details of "A" part
0.10(.004)
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0˚~8˚
52
14
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
13
0.65(.026)
0.30
.012
C
+0.065
–0.035
+.0027
–.0014
0.13(.005)
M
2005 FUJITSU LIMITED F52001S-c-1-1
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
63
MB95110M Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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Please note that Fujitsu will not be liable against you and/or any
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Edited
Business Promotion Dept.
F0608